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gma500: cdv_intel_crt: drop unused variables
[deliverable/linux.git] / drivers / gpu / drm / gma500 / cdv_intel_display.c
CommitLineData
6a227d5f
AC		 1/*
2 * Copyright © 2006-2011 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * Authors:
18 * Eric Anholt <eric@anholt.net>
19 */
20
21#include <linux/i2c.h>
22#include <linux/pm_runtime.h>
23
24#include <drm/drmP.h>
25#include "framebuffer.h"
26#include "psb_drv.h"
27#include "psb_intel_drv.h"
28#include "psb_intel_reg.h"
29#include "psb_intel_display.h"
30#include "power.h"
31#include "cdv_device.h"
32
33
34struct cdv_intel_range_t {
35 int min, max;
36};
37
38struct cdv_intel_p2_t {
39 int dot_limit;
40 int p2_slow, p2_fast;
41};
42
43struct cdv_intel_clock_t {
44 /* given values */
45 int n;
46 int m1, m2;
47 int p1, p2;
48 /* derived values */
49 int dot;
50 int vco;
51 int m;
52 int p;
53};
54
55#define INTEL_P2_NUM 2
56
57struct cdv_intel_limit_t {
58 struct cdv_intel_range_t dot, vco, n, m, m1, m2, p, p1;
59 struct cdv_intel_p2_t p2;
60};
61
62#define CDV_LIMIT_SINGLE_LVDS_96 0
63#define CDV_LIMIT_SINGLE_LVDS_100 1
64#define CDV_LIMIT_DAC_HDMI_27 2
65#define CDV_LIMIT_DAC_HDMI_96 3
66
67static const struct cdv_intel_limit_t cdv_intel_limits[] = {
68 { /* CDV_SIGNLE_LVDS_96MHz */
69 .dot = {.min = 20000, .max = 115500},
70 .vco = {.min = 1800000, .max = 3600000},
71 .n = {.min = 2, .max = 6},
72 .m = {.min = 60, .max = 160},
73 .m1 = {.min = 0, .max = 0},
74 .m2 = {.min = 58, .max = 158},
75 .p = {.min = 28, .max = 140},
76 .p1 = {.min = 2, .max = 10},
77 .p2 = {.dot_limit = 200000,
78 .p2_slow = 14, .p2_fast = 14},
79 },
80 { /* CDV_SINGLE_LVDS_100MHz */
81 .dot = {.min = 20000, .max = 115500},
82 .vco = {.min = 1800000, .max = 3600000},
83 .n = {.min = 2, .max = 6},
84 .m = {.min = 60, .max = 160},
85 .m1 = {.min = 0, .max = 0},
86 .m2 = {.min = 58, .max = 158},
87 .p = {.min = 28, .max = 140},
88 .p1 = {.min = 2, .max = 10},
89 /* The single-channel range is 25-112Mhz, and dual-channel
90 * is 80-224Mhz. Prefer single channel as much as possible.
91 */
92 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
93 },
94 { /* CDV_DAC_HDMI_27MHz */
95 .dot = {.min = 20000, .max = 400000},
96 .vco = {.min = 1809000, .max = 3564000},
97 .n = {.min = 1, .max = 1},
98 .m = {.min = 67, .max = 132},
99 .m1 = {.min = 0, .max = 0},
100 .m2 = {.min = 65, .max = 130},
101 .p = {.min = 5, .max = 90},
102 .p1 = {.min = 1, .max = 9},
103 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
104 },
105 { /* CDV_DAC_HDMI_96MHz */
106 .dot = {.min = 20000, .max = 400000},
107 .vco = {.min = 1800000, .max = 3600000},
108 .n = {.min = 2, .max = 6},
109 .m = {.min = 60, .max = 160},
110 .m1 = {.min = 0, .max = 0},
111 .m2 = {.min = 58, .max = 158},
112 .p = {.min = 5, .max = 100},
113 .p1 = {.min = 1, .max = 10},
114 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
115 },
116};
117
118#define _wait_for(COND, MS, W) ({ \
119 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
120 int ret__ = 0; \
121 while (!(COND)) { \
122 if (time_after(jiffies, timeout__)) { \
123 ret__ = -ETIMEDOUT; \
124 break; \
125 } \
126 if (W && !in_dbg_master()) \
127 msleep(W); \
128 } \
129 ret__; \
130})
131
132#define wait_for(COND, MS) _wait_for(COND, MS, 1)
133
134
135static int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
136{
137 int ret;
138
139 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
140 if (ret) {
141 DRM_ERROR("timeout waiting for SB to idle before read\n");
142 return ret;
143 }
144
145 REG_WRITE(SB_ADDR, reg);
146 REG_WRITE(SB_PCKT,
147 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
148 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
149 SET_FIELD(0xf, SB_BYTE_ENABLE));
150
151 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
152 if (ret) {
153 DRM_ERROR("timeout waiting for SB to idle after read\n");
154 return ret;
155 }
156
157 *val = REG_READ(SB_DATA);
158
159 return 0;
160}
161
162static int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
163{
164 int ret;
165 static bool dpio_debug = true;
166 u32 temp;
167
168 if (dpio_debug) {
169 if (cdv_sb_read(dev, reg, &temp) == 0)
170 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
171 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
172 }
173
174 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
175 if (ret) {
176 DRM_ERROR("timeout waiting for SB to idle before write\n");
177 return ret;
178 }
179
180 REG_WRITE(SB_ADDR, reg);
181 REG_WRITE(SB_DATA, val);
182 REG_WRITE(SB_PCKT,
183 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
184 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
185 SET_FIELD(0xf, SB_BYTE_ENABLE));
186
187 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
188 if (ret) {
189 DRM_ERROR("timeout waiting for SB to idle after write\n");
190 return ret;
191 }
192
193 if (dpio_debug) {
194 if (cdv_sb_read(dev, reg, &temp) == 0)
195 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
196 }
197
198 return 0;
199}
200
201/* Reset the DPIO configuration register. The BIOS does this at every
202 * mode set.
203 */
204static void cdv_sb_reset(struct drm_device *dev)
205{
206
207 REG_WRITE(DPIO_CFG, 0);
208 REG_READ(DPIO_CFG);
209 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
210}
211
212/* Unlike most Intel display engines, on Cedarview the DPLL registers
213 * are behind this sideband bus. They must be programmed while the
214 * DPLL reference clock is on in the DPLL control register, but before
215 * the DPLL is enabled in the DPLL control register.
216 */
217static int
218cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
219 struct cdv_intel_clock_t *clock)
220{
221 struct psb_intel_crtc *psb_crtc =
222 to_psb_intel_crtc(crtc);
223 int pipe = psb_crtc->pipe;
224 u32 m, n_vco, p;
225 int ret = 0;
226 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
227 u32 ref_value;
228
229 cdv_sb_reset(dev);
230
231 if ((REG_READ(dpll_reg) & DPLL_SYNCLOCK_ENABLE) == 0) {
232 DRM_ERROR("Attempting to set DPLL with refclk disabled\n");
233 return -EBUSY;
234 }
235
236 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
237 ref_value = 0x68A701;
238
239 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
240
241 /* We don't know what the other fields of these regs are, so
242 * leave them in place.
243 */
244 ret = cdv_sb_read(dev, SB_M(pipe), &m);
245 if (ret)
246 return ret;
247 m &= ~SB_M_DIVIDER_MASK;
248 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
249 ret = cdv_sb_write(dev, SB_M(pipe), m);
250 if (ret)
251 return ret;
252
253 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
254 if (ret)
255 return ret;
256
257 /* Follow the BIOS to program the N_DIVIDER REG */
258 n_vco &= 0xFFFF;
259 n_vco |= 0x107;
260 n_vco &= ~(SB_N_VCO_SEL_MASK |
261 SB_N_DIVIDER_MASK |
262 SB_N_CB_TUNE_MASK);
263
264 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
265
266 if (clock->vco < 2250000) {
267 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
268 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
269 } else if (clock->vco < 2750000) {
270 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
271 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
272 } else if (clock->vco < 3300000) {
273 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
274 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
275 } else {
276 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
277 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
278 }
279
280 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
281 if (ret)
282 return ret;
283
284 ret = cdv_sb_read(dev, SB_P(pipe), &p);
285 if (ret)
286 return ret;
287 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
288 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
289 switch (clock->p2) {
290 case 5:
291 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
292 break;
293 case 10:
294 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
295 break;
296 case 14:
297 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
298 break;
299 case 7:
300 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
301 break;
302 default:
303 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
304 return -EINVAL;
305 }
306 ret = cdv_sb_write(dev, SB_P(pipe), p);
307 if (ret)
308 return ret;
309
310 /* always Program the Lane Register for the Pipe A*/
311 if (pipe == 0) {
312 /* Program the Lane0/1 for HDMI B */
313 u32 lane_reg, lane_value;
314
315 lane_reg = PSB_LANE0;
316 cdv_sb_read(dev, lane_reg, &lane_value);
317 lane_value &= ~(LANE_PLL_MASK);
318 lane_value |= LANE_PLL_ENABLE;
319 cdv_sb_write(dev, lane_reg, lane_value);
320
321 lane_reg = PSB_LANE1;
322 cdv_sb_read(dev, lane_reg, &lane_value);
323 lane_value &= ~(LANE_PLL_MASK);
324 lane_value |= LANE_PLL_ENABLE;
325 cdv_sb_write(dev, lane_reg, lane_value);
326
327 /* Program the Lane2/3 for HDMI C */
328 lane_reg = PSB_LANE2;
329 cdv_sb_read(dev, lane_reg, &lane_value);
330 lane_value &= ~(LANE_PLL_MASK);
331 lane_value |= LANE_PLL_ENABLE;
332 cdv_sb_write(dev, lane_reg, lane_value);
333
334 lane_reg = PSB_LANE3;
335 cdv_sb_read(dev, lane_reg, &lane_value);
336 lane_value &= ~(LANE_PLL_MASK);
337 lane_value |= LANE_PLL_ENABLE;
338 cdv_sb_write(dev, lane_reg, lane_value);
339 }
340
341 return 0;
342}
343
344/*
a12d6a07 345 * Returns whether any encoder on the specified pipe is of the specified type
6a227d5f
AC		 346 */
347bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type)
348{
349 struct drm_device *dev = crtc->dev;
350 struct drm_mode_config *mode_config = &dev->mode_config;
351 struct drm_connector *l_entry;
352
353 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
354 if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
a12d6a07
PJ		 355 struct psb_intel_encoder *psb_intel_encoder =
356 psb_intel_attached_encoder(l_entry);
357 if (psb_intel_encoder->type == type)
6a227d5f
AC		 358 return true;
359 }
360 }
361 return false;
362}
363
364static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
365 int refclk)
366{
367 const struct cdv_intel_limit_t *limit;
368 if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
369 /*
370 * Now only single-channel LVDS is supported on CDV. If it is
371 * incorrect, please add the dual-channel LVDS.
372 */
373 if (refclk == 96000)
374 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
375 else
376 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
377 } else {
378 if (refclk == 27000)
379 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
380 else
381 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
382 }
383 return limit;
384}
385
386/* m1 is reserved as 0 in CDV, n is a ring counter */
387static void cdv_intel_clock(struct drm_device *dev,
388 int refclk, struct cdv_intel_clock_t *clock)
389{
390 clock->m = clock->m2 + 2;
391 clock->p = clock->p1 * clock->p2;
392 clock->vco = (refclk * clock->m) / clock->n;
393 clock->dot = clock->vco / clock->p;
394}
395
396
397#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
398static bool cdv_intel_PLL_is_valid(struct drm_crtc *crtc,
399 const struct cdv_intel_limit_t *limit,
400 struct cdv_intel_clock_t *clock)
401{
402 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
403 INTELPllInvalid("p1 out of range\n");
404 if (clock->p < limit->p.min || limit->p.max < clock->p)
405 INTELPllInvalid("p out of range\n");
406 /* unnecessary to check the range of m(m1/M2)/n again */
407 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
408 INTELPllInvalid("vco out of range\n");
409 /* XXX: We may need to be checking "Dot clock"
410 * depending on the multiplier, connector, etc.,
411 * rather than just a single range.
412 */
413 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
414 INTELPllInvalid("dot out of range\n");
415
416 return true;
417}
418
419static bool cdv_intel_find_best_PLL(struct drm_crtc *crtc, int target,
420 int refclk,
421 struct cdv_intel_clock_t *best_clock)
422{
423 struct drm_device *dev = crtc->dev;
424 struct cdv_intel_clock_t clock;
425 const struct cdv_intel_limit_t *limit = cdv_intel_limit(crtc, refclk);
426 int err = target;
427
428
429 if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
430 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
431 /*
432 * For LVDS, if the panel is on, just rely on its current
433 * settings for dual-channel. We haven't figured out how to
434 * reliably set up different single/dual channel state, if we
435 * even can.
436 */
437 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
438 LVDS_CLKB_POWER_UP)
439 clock.p2 = limit->p2.p2_fast;
440 else
441 clock.p2 = limit->p2.p2_slow;
442 } else {
443 if (target < limit->p2.dot_limit)
444 clock.p2 = limit->p2.p2_slow;
445 else
446 clock.p2 = limit->p2.p2_fast;
447 }
448
449 memset(best_clock, 0, sizeof(*best_clock));
450 clock.m1 = 0;
451 /* m1 is reserved as 0 in CDV, n is a ring counter.
452 So skip the m1 loop */
453 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
454 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max;
455 clock.m2++) {
456 for (clock.p1 = limit->p1.min;
457 clock.p1 <= limit->p1.max;
458 clock.p1++) {
459 int this_err;
460
461 cdv_intel_clock(dev, refclk, &clock);
462
463 if (!cdv_intel_PLL_is_valid(crtc,
464 limit, &clock))
465 continue;
466
467 this_err = abs(clock.dot - target);
468 if (this_err < err) {
469 *best_clock = clock;
470 err = this_err;
471 }
472 }
473 }
474 }
475
476 return err != target;
477}
478
479int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
480 int x, int y, struct drm_framebuffer *old_fb)
481{
482 struct drm_device *dev = crtc->dev;
483 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
484 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
485 int pipe = psb_intel_crtc->pipe;
486 unsigned long start, offset;
487 int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
488 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
489 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
490 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
491 u32 dspcntr;
492 int ret = 0;
493
494 if (!gma_power_begin(dev, true))
495 return 0;
496
497 /* no fb bound */
498 if (!crtc->fb) {
499 dev_err(dev->dev, "No FB bound\n");
500 goto psb_intel_pipe_cleaner;
501 }
502
503
504 /* We are displaying this buffer, make sure it is actually loaded
505 into the GTT */
506 ret = psb_gtt_pin(psbfb->gtt);
507 if (ret < 0)
508 goto psb_intel_pipe_set_base_exit;
509 start = psbfb->gtt->offset;
01f2c773 510 offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
6a227d5f 511
01f2c773 512 REG_WRITE(dspstride, crtc->fb->pitches[0]);
6a227d5f
AC		 513
514 dspcntr = REG_READ(dspcntr_reg);
515 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
516
517 switch (crtc->fb->bits_per_pixel) {
518 case 8:
519 dspcntr |= DISPPLANE_8BPP;
520 break;
521 case 16:
522 if (crtc->fb->depth == 15)
523 dspcntr |= DISPPLANE_15_16BPP;
524 else
525 dspcntr |= DISPPLANE_16BPP;
526 break;
527 case 24:
528 case 32:
529 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
530 break;
531 default:
532 dev_err(dev->dev, "Unknown color depth\n");
533 ret = -EINVAL;
534 goto psb_intel_pipe_set_base_exit;
535 }
536 REG_WRITE(dspcntr_reg, dspcntr);
537
538 dev_dbg(dev->dev,
539 "Writing base %08lX %08lX %d %d\n", start, offset, x, y);
540
541 REG_WRITE(dspbase, offset);
542 REG_READ(dspbase);
543 REG_WRITE(dspsurf, start);
544 REG_READ(dspsurf);
545
546psb_intel_pipe_cleaner:
547 /* If there was a previous display we can now unpin it */
548 if (old_fb)
549 psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
550
551psb_intel_pipe_set_base_exit:
552 gma_power_end(dev);
553 return ret;
554}
555
556/**
557 * Sets the power management mode of the pipe and plane.
558 *
559 * This code should probably grow support for turning the cursor off and back
560 * on appropriately at the same time as we're turning the pipe off/on.
561 */
562static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
563{
564 struct drm_device *dev = crtc->dev;
565 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
566 int pipe = psb_intel_crtc->pipe;
567 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
568 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
569 int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE;
570 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
571 u32 temp;
6a227d5f
AC		 572
573 /* XXX: When our outputs are all unaware of DPMS modes other than off
574 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
575 */
576 switch (mode) {
577 case DRM_MODE_DPMS_ON:
578 case DRM_MODE_DPMS_STANDBY:
579 case DRM_MODE_DPMS_SUSPEND:
580 /* Enable the DPLL */
581 temp = REG_READ(dpll_reg);
582 if ((temp & DPLL_VCO_ENABLE) == 0) {
583 REG_WRITE(dpll_reg, temp);
584 REG_READ(dpll_reg);
585 /* Wait for the clocks to stabilize. */
586 udelay(150);
587 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
588 REG_READ(dpll_reg);
589 /* Wait for the clocks to stabilize. */
590 udelay(150);
591 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
592 REG_READ(dpll_reg);
593 /* Wait for the clocks to stabilize. */
594 udelay(150);
595 }
596
597 /* Jim Bish - switch plan and pipe per scott */
598 /* Enable the plane */
599 temp = REG_READ(dspcntr_reg);
600 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
601 REG_WRITE(dspcntr_reg,
602 temp | DISPLAY_PLANE_ENABLE);
603 /* Flush the plane changes */
604 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
605 }
606
607 udelay(150);
608
609 /* Enable the pipe */
610 temp = REG_READ(pipeconf_reg);
611 if ((temp & PIPEACONF_ENABLE) == 0)
612 REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
613
614 psb_intel_crtc_load_lut(crtc);
615
616 /* Give the overlay scaler a chance to enable
617 * if it's on this pipe */
618 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
619 break;
620 case DRM_MODE_DPMS_OFF:
621 /* Give the overlay scaler a chance to disable
622 * if it's on this pipe */
623 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
624
625 /* Disable the VGA plane that we never use */
626 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
627
628 /* Jim Bish - changed pipe/plane here as well. */
629
630 /* Wait for vblank for the disable to take effect */
631 cdv_intel_wait_for_vblank(dev);
632
633 /* Next, disable display pipes */
634 temp = REG_READ(pipeconf_reg);
635 if ((temp & PIPEACONF_ENABLE) != 0) {
636 REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
637 REG_READ(pipeconf_reg);
638 }
639
640 /* Wait for vblank for the disable to take effect. */
641 cdv_intel_wait_for_vblank(dev);
642
643 udelay(150);
644
645 /* Disable display plane */
646 temp = REG_READ(dspcntr_reg);
647 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
648 REG_WRITE(dspcntr_reg,
649 temp & ~DISPLAY_PLANE_ENABLE);
650 /* Flush the plane changes */
651 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
652 REG_READ(dspbase_reg);
653 }
654
655 temp = REG_READ(dpll_reg);
656 if ((temp & DPLL_VCO_ENABLE) != 0) {
657 REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
658 REG_READ(dpll_reg);
659 }
660
661 /* Wait for the clocks to turn off. */
662 udelay(150);
663 break;
664 }
6a227d5f
AC		 665 /*Set FIFO Watermarks*/
666 REG_WRITE(DSPARB, 0x3F3E);
667}
668
669static void cdv_intel_crtc_prepare(struct drm_crtc *crtc)
670{
671 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
672 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
673}
674
675static void cdv_intel_crtc_commit(struct drm_crtc *crtc)
676{
677 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
678 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
679}
680
6a227d5f
AC		 681static bool cdv_intel_crtc_mode_fixup(struct drm_crtc *crtc,
682 struct drm_display_mode *mode,
683 struct drm_display_mode *adjusted_mode)
684{
685 return true;
686}
687
688
689/**
690 * Return the pipe currently connected to the panel fitter,
691 * or -1 if the panel fitter is not present or not in use
692 */
693static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
694{
695 u32 pfit_control;
696
697 pfit_control = REG_READ(PFIT_CONTROL);
698
699 /* See if the panel fitter is in use */
700 if ((pfit_control & PFIT_ENABLE) == 0)
701 return -1;
702 return (pfit_control >> 29) & 0x3;
703}
704
705static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
706 struct drm_display_mode *mode,
707 struct drm_display_mode *adjusted_mode,
708 int x, int y,
709 struct drm_framebuffer *old_fb)
710{
711 struct drm_device *dev = crtc->dev;
712 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
713 int pipe = psb_intel_crtc->pipe;
714 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
715 int dpll_md_reg = (psb_intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
716 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
717 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
718 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
719 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
720 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
721 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
722 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
723 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
724 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
725 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
726 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
727 int refclk;
728 struct cdv_intel_clock_t clock;
729 u32 dpll = 0, dspcntr, pipeconf;
0313c0de 730 bool ok;
6a227d5f
AC		 731 bool is_crt = false, is_lvds = false, is_tv = false;
732 bool is_hdmi = false;
733 struct drm_mode_config *mode_config = &dev->mode_config;
734 struct drm_connector *connector;
735
736 list_for_each_entry(connector, &mode_config->connector_list, head) {
a12d6a07
PJ		 737 struct psb_intel_encoder *psb_intel_encoder =
738 psb_intel_attached_encoder(connector);
6a227d5f
AC		 739
740 if (!connector->encoder
741 || connector->encoder->crtc != crtc)
742 continue;
743
a12d6a07 744 switch (psb_intel_encoder->type) {
6a227d5f
AC		 745 case INTEL_OUTPUT_LVDS:
746 is_lvds = true;
747 break;
6a227d5f
AC		 748 case INTEL_OUTPUT_TVOUT:
749 is_tv = true;
750 break;
751 case INTEL_OUTPUT_ANALOG:
752 is_crt = true;
753 break;
754 case INTEL_OUTPUT_HDMI:
755 is_hdmi = true;
756 break;
757 }
758 }
759
760 refclk = 96000;
761
762 /* Hack selection about ref clk for CRT */
763 /* Select 27MHz as the reference clk for HDMI */
764 if (is_crt || is_hdmi)
765 refclk = 27000;
766
767 drm_mode_debug_printmodeline(adjusted_mode);
768
769 ok = cdv_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
770 &clock);
771 if (!ok) {
772 dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
773 return 0;
774 }
775
776 dpll = DPLL_VGA_MODE_DIS;
777 if (is_tv) {
778 /* XXX: just matching BIOS for now */
779/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
780 dpll |= 3;
781 }
782 dpll |= PLL_REF_INPUT_DREFCLK;
783
784 dpll |= DPLL_SYNCLOCK_ENABLE;
785 dpll |= DPLL_VGA_MODE_DIS;
786 if (is_lvds)
787 dpll |= DPLLB_MODE_LVDS;
788 else
789 dpll |= DPLLB_MODE_DAC_SERIAL;
790 /* dpll |= (2 << 11); */
791
792 /* setup pipeconf */
793 pipeconf = REG_READ(pipeconf_reg);
794
795 /* Set up the display plane register */
796 dspcntr = DISPPLANE_GAMMA_ENABLE;
797
798 if (pipe == 0)
799 dspcntr |= DISPPLANE_SEL_PIPE_A;
800 else
801 dspcntr |= DISPPLANE_SEL_PIPE_B;
802
803 dspcntr |= DISPLAY_PLANE_ENABLE;
804 pipeconf |= PIPEACONF_ENABLE;
805
806 REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
807 REG_READ(dpll_reg);
808
809 cdv_dpll_set_clock_cdv(dev, crtc, &clock);
810
811 udelay(150);
812
813
814 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
815 * This is an exception to the general rule that mode_set doesn't turn
816 * things on.
817 */
818 if (is_lvds) {
819 u32 lvds = REG_READ(LVDS);
820
821 lvds |=
822 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
823 LVDS_PIPEB_SELECT;
824 /* Set the B0-B3 data pairs corresponding to
825 * whether we're going to
826 * set the DPLLs for dual-channel mode or not.
827 */
828 if (clock.p2 == 7)
829 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
830 else
831 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
832
833 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
834 * appropriately here, but we need to look more
835 * thoroughly into how panels behave in the two modes.
836 */
837
838 REG_WRITE(LVDS, lvds);
839 REG_READ(LVDS);
840 }
841
842 dpll |= DPLL_VCO_ENABLE;
843
844 /* Disable the panel fitter if it was on our pipe */
845 if (cdv_intel_panel_fitter_pipe(dev) == pipe)
846 REG_WRITE(PFIT_CONTROL, 0);
847
848 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
849 drm_mode_debug_printmodeline(mode);
850
851 REG_WRITE(dpll_reg,
852 (REG_READ(dpll_reg) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
853 REG_READ(dpll_reg);
854 /* Wait for the clocks to stabilize. */
855 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
856
857 if (!(REG_READ(dpll_reg) & DPLL_LOCK)) {
858 dev_err(dev->dev, "Failed to get DPLL lock\n");
859 return -EBUSY;
860 }
861
862 {
863 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
864 REG_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
865 }
866
867 REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
868 ((adjusted_mode->crtc_htotal - 1) << 16));
869 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
870 ((adjusted_mode->crtc_hblank_end - 1) << 16));
871 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
872 ((adjusted_mode->crtc_hsync_end - 1) << 16));
873 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
874 ((adjusted_mode->crtc_vtotal - 1) << 16));
875 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
876 ((adjusted_mode->crtc_vblank_end - 1) << 16));
877 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
878 ((adjusted_mode->crtc_vsync_end - 1) << 16));
879 /* pipesrc and dspsize control the size that is scaled from,
880 * which should always be the user's requested size.
881 */
882 REG_WRITE(dspsize_reg,
883 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
884 REG_WRITE(dsppos_reg, 0);
885 REG_WRITE(pipesrc_reg,
886 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
887 REG_WRITE(pipeconf_reg, pipeconf);
888 REG_READ(pipeconf_reg);
889
890 cdv_intel_wait_for_vblank(dev);
891
892 REG_WRITE(dspcntr_reg, dspcntr);
893
894 /* Flush the plane changes */
895 {
896 struct drm_crtc_helper_funcs *crtc_funcs =
897 crtc->helper_private;
898 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
899 }
900
901 cdv_intel_wait_for_vblank(dev);
902
903 return 0;
904}
905
906/** Loads the palette/gamma unit for the CRTC with the prepared values */
907void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
908{
909 struct drm_device *dev = crtc->dev;
910 struct drm_psb_private *dev_priv =
911 (struct drm_psb_private *)dev->dev_private;
912 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
913 int palreg = PALETTE_A;
914 int i;
915
916 /* The clocks have to be on to load the palette. */
917 if (!crtc->enabled)
918 return;
919
920 switch (psb_intel_crtc->pipe) {
921 case 0:
922 break;
923 case 1:
924 palreg = PALETTE_B;
925 break;
926 case 2:
927 palreg = PALETTE_C;
928 break;
929 default:
930 dev_err(dev->dev, "Illegal Pipe Number.\n");
931 return;
932 }
933
934 if (gma_power_begin(dev, false)) {
935 for (i = 0; i < 256; i++) {
936 REG_WRITE(palreg + 4 * i,
937 ((psb_intel_crtc->lut_r[i] +
938 psb_intel_crtc->lut_adj[i]) << 16) |
939 ((psb_intel_crtc->lut_g[i] +
940 psb_intel_crtc->lut_adj[i]) << 8) |
941 (psb_intel_crtc->lut_b[i] +
942 psb_intel_crtc->lut_adj[i]));
943 }
944 gma_power_end(dev);
945 } else {
946 for (i = 0; i < 256; i++) {
c6265ff5 947 dev_priv->regs.psb.save_palette_a[i] =
6a227d5f
AC		 948 ((psb_intel_crtc->lut_r[i] +
949 psb_intel_crtc->lut_adj[i]) << 16) |
950 ((psb_intel_crtc->lut_g[i] +
951 psb_intel_crtc->lut_adj[i]) << 8) |
952 (psb_intel_crtc->lut_b[i] +
953 psb_intel_crtc->lut_adj[i]);
954 }
955
956 }
957}
958
959/**
960 * Save HW states of giving crtc
961 */
962static void cdv_intel_crtc_save(struct drm_crtc *crtc)
963{
964 struct drm_device *dev = crtc->dev;
965 /* struct drm_psb_private *dev_priv =
966 (struct drm_psb_private *)dev->dev_private; */
967 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
968 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
969 int pipeA = (psb_intel_crtc->pipe == 0);
970 uint32_t paletteReg;
971 int i;
972
973 if (!crtc_state) {
974 dev_dbg(dev->dev, "No CRTC state found\n");
975 return;
976 }
977
978 crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR);
979 crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF);
980 crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC);
981 crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0);
982 crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1);
983 crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B);
984 crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B);
985 crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B);
986 crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B);
987 crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B);
988 crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B);
989 crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B);
990 crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE);
991
992 /*NOTE: DSPSIZE DSPPOS only for psb*/
993 crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE);
994 crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS);
995
996 crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE);
997
998 DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
999 crtc_state->saveDSPCNTR,
1000 crtc_state->savePIPECONF,
1001 crtc_state->savePIPESRC,
1002 crtc_state->saveFP0,
1003 crtc_state->saveFP1,
1004 crtc_state->saveDPLL,
1005 crtc_state->saveHTOTAL,
1006 crtc_state->saveHBLANK,
1007 crtc_state->saveHSYNC,
1008 crtc_state->saveVTOTAL,
1009 crtc_state->saveVBLANK,
1010 crtc_state->saveVSYNC,
1011 crtc_state->saveDSPSTRIDE,
1012 crtc_state->saveDSPSIZE,
1013 crtc_state->saveDSPPOS,
1014 crtc_state->saveDSPBASE
1015 );
1016
1017 paletteReg = pipeA ? PALETTE_A : PALETTE_B;
1018 for (i = 0; i < 256; ++i)
1019 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
1020}
1021
1022/**
1023 * Restore HW states of giving crtc
1024 */
1025static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
1026{
1027 struct drm_device *dev = crtc->dev;
1028 /* struct drm_psb_private * dev_priv =
1029 (struct drm_psb_private *)dev->dev_private; */
1030 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1031 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
1032 /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */
1033 int pipeA = (psb_intel_crtc->pipe == 0);
1034 uint32_t paletteReg;
1035 int i;
1036
1037 if (!crtc_state) {
1038 dev_dbg(dev->dev, "No crtc state\n");
1039 return;
1040 }
1041
1042 DRM_DEBUG(
1043 "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1044 REG_READ(pipeA ? DSPACNTR : DSPBCNTR),
1045 REG_READ(pipeA ? PIPEACONF : PIPEBCONF),
1046 REG_READ(pipeA ? PIPEASRC : PIPEBSRC),
1047 REG_READ(pipeA ? FPA0 : FPB0),
1048 REG_READ(pipeA ? FPA1 : FPB1),
1049 REG_READ(pipeA ? DPLL_A : DPLL_B),
1050 REG_READ(pipeA ? HTOTAL_A : HTOTAL_B),
1051 REG_READ(pipeA ? HBLANK_A : HBLANK_B),
1052 REG_READ(pipeA ? HSYNC_A : HSYNC_B),
1053 REG_READ(pipeA ? VTOTAL_A : VTOTAL_B),
1054 REG_READ(pipeA ? VBLANK_A : VBLANK_B),
1055 REG_READ(pipeA ? VSYNC_A : VSYNC_B),
1056 REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE),
1057 REG_READ(pipeA ? DSPASIZE : DSPBSIZE),
1058 REG_READ(pipeA ? DSPAPOS : DSPBPOS),
1059 REG_READ(pipeA ? DSPABASE : DSPBBASE)
1060 );
1061
1062 DRM_DEBUG(
1063 "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1064 crtc_state->saveDSPCNTR,
1065 crtc_state->savePIPECONF,
1066 crtc_state->savePIPESRC,
1067 crtc_state->saveFP0,
1068 crtc_state->saveFP1,
1069 crtc_state->saveDPLL,
1070 crtc_state->saveHTOTAL,
1071 crtc_state->saveHBLANK,
1072 crtc_state->saveHSYNC,
1073 crtc_state->saveVTOTAL,
1074 crtc_state->saveVBLANK,
1075 crtc_state->saveVSYNC,
1076 crtc_state->saveDSPSTRIDE,
1077 crtc_state->saveDSPSIZE,
1078 crtc_state->saveDSPPOS,
1079 crtc_state->saveDSPBASE
1080 );
1081
1082
1083 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
1084 REG_WRITE(pipeA ? DPLL_A : DPLL_B,
1085 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
1086 REG_READ(pipeA ? DPLL_A : DPLL_B);
1087 DRM_DEBUG("write dpll: %x\n",
1088 REG_READ(pipeA ? DPLL_A : DPLL_B));
1089 udelay(150);
1090 }
1091
1092 REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0);
1093 REG_READ(pipeA ? FPA0 : FPB0);
1094
1095 REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1);
1096 REG_READ(pipeA ? FPA1 : FPB1);
1097
1098 REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL);
1099 REG_READ(pipeA ? DPLL_A : DPLL_B);
1100 udelay(150);
1101
1102 REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL);
1103 REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK);
1104 REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC);
1105 REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL);
1106 REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK);
1107 REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC);
1108 REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE);
1109
1110 REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE);
1111 REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS);
1112
1113 REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC);
1114 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
1115 REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF);
1116
1117 cdv_intel_wait_for_vblank(dev);
1118
1119 REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR);
1120 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
1121
1122 cdv_intel_wait_for_vblank(dev);
1123
1124 paletteReg = pipeA ? PALETTE_A : PALETTE_B;
1125 for (i = 0; i < 256; ++i)
1126 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
1127}
1128
1129static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
1130 struct drm_file *file_priv,
1131 uint32_t handle,
1132 uint32_t width, uint32_t height)
1133{
1134 struct drm_device *dev = crtc->dev;
1135 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1136 int pipe = psb_intel_crtc->pipe;
1137 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1138 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1139 uint32_t temp;
1140 size_t addr = 0;
1141 struct gtt_range *gt;
1142 struct drm_gem_object *obj;
1143 int ret;
1144
1145 /* if we want to turn of the cursor ignore width and height */
1146 if (!handle) {
1147 /* turn off the cursor */
1148 temp = CURSOR_MODE_DISABLE;
1149
1150 if (gma_power_begin(dev, false)) {
1151 REG_WRITE(control, temp);
1152 REG_WRITE(base, 0);
1153 gma_power_end(dev);
1154 }
1155
1156 /* unpin the old GEM object */
1157 if (psb_intel_crtc->cursor_obj) {
1158 gt = container_of(psb_intel_crtc->cursor_obj,
1159 struct gtt_range, gem);
1160 psb_gtt_unpin(gt);
1161 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1162 psb_intel_crtc->cursor_obj = NULL;
1163 }
1164
1165 return 0;
1166 }
1167
1168 /* Currently we only support 64x64 cursors */
1169 if (width != 64 || height != 64) {
1170 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
1171 return -EINVAL;
1172 }
1173
1174 obj = drm_gem_object_lookup(dev, file_priv, handle);
1175 if (!obj)
1176 return -ENOENT;
1177
1178 if (obj->size < width * height * 4) {
1179 dev_dbg(dev->dev, "buffer is to small\n");
1180 return -ENOMEM;
1181 }
1182
1183 gt = container_of(obj, struct gtt_range, gem);
1184
1185 /* Pin the memory into the GTT */
1186 ret = psb_gtt_pin(gt);
1187 if (ret) {
1188 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
1189 return ret;
1190 }
1191
1192 addr = gt->offset; /* Or resource.start ??? */
1193
1194 psb_intel_crtc->cursor_addr = addr;
1195
1196 temp = 0;
1197 /* set the pipe for the cursor */
1198 temp |= (pipe << 28);
1199 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1200
1201 if (gma_power_begin(dev, false)) {
1202 REG_WRITE(control, temp);
1203 REG_WRITE(base, addr);
1204 gma_power_end(dev);
1205 }
1206
1207 /* unpin the old GEM object */
1208 if (psb_intel_crtc->cursor_obj) {
1209 gt = container_of(psb_intel_crtc->cursor_obj,
1210 struct gtt_range, gem);
1211 psb_gtt_unpin(gt);
1212 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1213 psb_intel_crtc->cursor_obj = obj;
1214 }
1215 return 0;
1216}
1217
1218static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1219{
1220 struct drm_device *dev = crtc->dev;
1221 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1222 int pipe = psb_intel_crtc->pipe;
1223 uint32_t temp = 0;
1224 uint32_t adder;
1225
1226
1227 if (x < 0) {
1228 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1229 x = -x;
1230 }
1231 if (y < 0) {
1232 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1233 y = -y;
1234 }
1235
1236 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1237 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1238
1239 adder = psb_intel_crtc->cursor_addr;
1240
1241 if (gma_power_begin(dev, false)) {
1242 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1243 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1244 gma_power_end(dev);
1245 }
1246 return 0;
1247}
1248
1249static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
1250 u16 *green, u16 *blue, uint32_t start, uint32_t size)
1251{
1252 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1253 int i;
1254 int end = (start + size > 256) ? 256 : start + size;
1255
1256 for (i = start; i < end; i++) {
1257 psb_intel_crtc->lut_r[i] = red[i] >> 8;
1258 psb_intel_crtc->lut_g[i] = green[i] >> 8;
1259 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
1260 }
1261
1262 cdv_intel_crtc_load_lut(crtc);
1263}
1264
1265static int cdv_crtc_set_config(struct drm_mode_set *set)
1266{
1267 int ret = 0;
1268 struct drm_device *dev = set->crtc->dev;
1269 struct drm_psb_private *dev_priv = dev->dev_private;
1270
1271 if (!dev_priv->rpm_enabled)
1272 return drm_crtc_helper_set_config(set);
1273
1274 pm_runtime_forbid(&dev->pdev->dev);
1275
1276 ret = drm_crtc_helper_set_config(set);
1277
1278 pm_runtime_allow(&dev->pdev->dev);
1279
1280 return ret;
1281}
1282
1283/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
1284
1285/* FIXME: why are we using this, should it be cdv_ in this tree ? */
1286
1287static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock)
1288{
1289 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
1290 clock->p = clock->p1 * clock->p2;
1291 clock->vco = refclk * clock->m / (clock->n + 2);
1292 clock->dot = clock->vco / clock->p;
1293}
1294
1295/* Returns the clock of the currently programmed mode of the given pipe. */
1296static int cdv_intel_crtc_clock_get(struct drm_device *dev,
1297 struct drm_crtc *crtc)
1298{
1299 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1300 int pipe = psb_intel_crtc->pipe;
1301 u32 dpll;
1302 u32 fp;
1303 struct cdv_intel_clock_t clock;
1304 bool is_lvds;
1305 struct drm_psb_private *dev_priv = dev->dev_private;
1306
1307 if (gma_power_begin(dev, false)) {
1308 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
1309 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1310 fp = REG_READ((pipe == 0) ? FPA0 : FPB0);
1311 else
1312 fp = REG_READ((pipe == 0) ? FPA1 : FPB1);
1313 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1314 gma_power_end(dev);
1315 } else {
1316 dpll = (pipe == 0) ?
c6265ff5
AC		 1317 dev_priv->regs.psb.saveDPLL_A :
1318 dev_priv->regs.psb.saveDPLL_B;
6a227d5f
AC		 1319
1320 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1321 fp = (pipe == 0) ?
c6265ff5
AC		 1322 dev_priv->regs.psb.saveFPA0 :
1323 dev_priv->regs.psb.saveFPB0;
6a227d5f
AC		 1324 else
1325 fp = (pipe == 0) ?
c6265ff5
AC		 1326 dev_priv->regs.psb.saveFPA1 :
1327 dev_priv->regs.psb.saveFPB1;
6a227d5f 1328
648a8e34 1329 is_lvds = (pipe == 1) &&
c6265ff5 1330 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
6a227d5f
AC		 1331 }
1332
1333 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1334 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1335 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1336
1337 if (is_lvds) {
1338 clock.p1 =
1339 ffs((dpll &
1340 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1341 DPLL_FPA01_P1_POST_DIV_SHIFT);
1342 if (clock.p1 == 0) {
1343 clock.p1 = 4;
1344 dev_err(dev->dev, "PLL %d\n", dpll);
1345 }
1346 clock.p2 = 14;
1347
1348 if ((dpll & PLL_REF_INPUT_MASK) ==
1349 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1350 /* XXX: might not be 66MHz */
1351 i8xx_clock(66000, &clock);
1352 } else
1353 i8xx_clock(48000, &clock);
1354 } else {
1355 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1356 clock.p1 = 2;
1357 else {
1358 clock.p1 =
1359 ((dpll &
1360 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1361 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1362 }
1363 if (dpll & PLL_P2_DIVIDE_BY_4)
1364 clock.p2 = 4;
1365 else
1366 clock.p2 = 2;
1367
1368 i8xx_clock(48000, &clock);
1369 }
1370
1371 /* XXX: It would be nice to validate the clocks, but we can't reuse
1372 * i830PllIsValid() because it relies on the xf86_config connector
1373 * configuration being accurate, which it isn't necessarily.
1374 */
1375
1376 return clock.dot;
1377}
1378
1379/** Returns the currently programmed mode of the given pipe. */
1380struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
1381 struct drm_crtc *crtc)
1382{
1383 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1384 int pipe = psb_intel_crtc->pipe;
1385 struct drm_display_mode *mode;
1386 int htot;
1387 int hsync;
1388 int vtot;
1389 int vsync;
1390 struct drm_psb_private *dev_priv = dev->dev_private;
1391
1392 if (gma_power_begin(dev, false)) {
1393 htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1394 hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1395 vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1396 vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1397 gma_power_end(dev);
1398 } else {
1399 htot = (pipe == 0) ?
c6265ff5
AC		 1400 dev_priv->regs.psb.saveHTOTAL_A :
1401 dev_priv->regs.psb.saveHTOTAL_B;
6a227d5f 1402 hsync = (pipe == 0) ?
c6265ff5
AC		 1403 dev_priv->regs.psb.saveHSYNC_A :
1404 dev_priv->regs.psb.saveHSYNC_B;
6a227d5f 1405 vtot = (pipe == 0) ?
c6265ff5
AC		 1406 dev_priv->regs.psb.saveVTOTAL_A :
1407 dev_priv->regs.psb.saveVTOTAL_B;
6a227d5f 1408 vsync = (pipe == 0) ?
c6265ff5
AC		 1409 dev_priv->regs.psb.saveVSYNC_A :
1410 dev_priv->regs.psb.saveVSYNC_B;
6a227d5f
AC		 1411 }
1412
1413 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1414 if (!mode)
1415 return NULL;
1416
1417 mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
1418 mode->hdisplay = (htot & 0xffff) + 1;
1419 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1420 mode->hsync_start = (hsync & 0xffff) + 1;
1421 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1422 mode->vdisplay = (vtot & 0xffff) + 1;
1423 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1424 mode->vsync_start = (vsync & 0xffff) + 1;
1425 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1426
1427 drm_mode_set_name(mode);
1428 drm_mode_set_crtcinfo(mode, 0);
1429
1430 return mode;
1431}
1432
1433static void cdv_intel_crtc_destroy(struct drm_crtc *crtc)
1434{
1435 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1436
1437 kfree(psb_intel_crtc->crtc_state);
1438 drm_crtc_cleanup(crtc);
1439 kfree(psb_intel_crtc);
1440}
1441
1442const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
1443 .dpms = cdv_intel_crtc_dpms,
1444 .mode_fixup = cdv_intel_crtc_mode_fixup,
1445 .mode_set = cdv_intel_crtc_mode_set,
1446 .mode_set_base = cdv_intel_pipe_set_base,
1447 .prepare = cdv_intel_crtc_prepare,
1448 .commit = cdv_intel_crtc_commit,
1449};
1450
1451const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
1452 .save = cdv_intel_crtc_save,
1453 .restore = cdv_intel_crtc_restore,
1454 .cursor_set = cdv_intel_crtc_cursor_set,
1455 .cursor_move = cdv_intel_crtc_cursor_move,
1456 .gamma_set = cdv_intel_crtc_gamma_set,
1457 .set_config = cdv_crtc_set_config,
1458 .destroy = cdv_intel_crtc_destroy,
1459};
Linux kernel - Deliverables
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