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6a227d5f AC |
1 | /* |
2 | * Copyright © 2006-2011 Intel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., | |
15 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
16 | * | |
17 | * Authors: | |
18 | * Eric Anholt <eric@anholt.net> | |
19 | */ | |
20 | ||
21 | #include <linux/i2c.h> | |
22 | #include <linux/pm_runtime.h> | |
23 | ||
24 | #include <drm/drmP.h> | |
25 | #include "framebuffer.h" | |
26 | #include "psb_drv.h" | |
27 | #include "psb_intel_drv.h" | |
28 | #include "psb_intel_reg.h" | |
29 | #include "psb_intel_display.h" | |
30 | #include "power.h" | |
31 | #include "cdv_device.h" | |
32 | ||
2adb29ff PJ |
33 | static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit, |
34 | struct drm_crtc *crtc, int target, | |
35 | int refclk, struct gma_clock_t *best_clock); | |
6a227d5f | 36 | |
d6676096 | 37 | |
6a227d5f AC |
38 | #define CDV_LIMIT_SINGLE_LVDS_96 0 |
39 | #define CDV_LIMIT_SINGLE_LVDS_100 1 | |
40 | #define CDV_LIMIT_DAC_HDMI_27 2 | |
41 | #define CDV_LIMIT_DAC_HDMI_96 3 | |
220801bd AC |
42 | #define CDV_LIMIT_DP_27 4 |
43 | #define CDV_LIMIT_DP_100 5 | |
6a227d5f | 44 | |
2adb29ff | 45 | static const struct gma_limit_t cdv_intel_limits[] = { |
28bbda39 | 46 | { /* CDV_SINGLE_LVDS_96MHz */ |
6a227d5f AC |
47 | .dot = {.min = 20000, .max = 115500}, |
48 | .vco = {.min = 1800000, .max = 3600000}, | |
49 | .n = {.min = 2, .max = 6}, | |
50 | .m = {.min = 60, .max = 160}, | |
51 | .m1 = {.min = 0, .max = 0}, | |
52 | .m2 = {.min = 58, .max = 158}, | |
53 | .p = {.min = 28, .max = 140}, | |
54 | .p1 = {.min = 2, .max = 10}, | |
2adb29ff PJ |
55 | .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14}, |
56 | .find_pll = gma_find_best_pll, | |
6a227d5f AC |
57 | }, |
58 | { /* CDV_SINGLE_LVDS_100MHz */ | |
59 | .dot = {.min = 20000, .max = 115500}, | |
60 | .vco = {.min = 1800000, .max = 3600000}, | |
61 | .n = {.min = 2, .max = 6}, | |
62 | .m = {.min = 60, .max = 160}, | |
63 | .m1 = {.min = 0, .max = 0}, | |
64 | .m2 = {.min = 58, .max = 158}, | |
65 | .p = {.min = 28, .max = 140}, | |
66 | .p1 = {.min = 2, .max = 10}, | |
67 | /* The single-channel range is 25-112Mhz, and dual-channel | |
68 | * is 80-224Mhz. Prefer single channel as much as possible. | |
69 | */ | |
70 | .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14}, | |
2adb29ff | 71 | .find_pll = gma_find_best_pll, |
6a227d5f AC |
72 | }, |
73 | { /* CDV_DAC_HDMI_27MHz */ | |
74 | .dot = {.min = 20000, .max = 400000}, | |
75 | .vco = {.min = 1809000, .max = 3564000}, | |
76 | .n = {.min = 1, .max = 1}, | |
77 | .m = {.min = 67, .max = 132}, | |
78 | .m1 = {.min = 0, .max = 0}, | |
79 | .m2 = {.min = 65, .max = 130}, | |
80 | .p = {.min = 5, .max = 90}, | |
81 | .p1 = {.min = 1, .max = 9}, | |
82 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, | |
2adb29ff | 83 | .find_pll = gma_find_best_pll, |
6a227d5f AC |
84 | }, |
85 | { /* CDV_DAC_HDMI_96MHz */ | |
86 | .dot = {.min = 20000, .max = 400000}, | |
87 | .vco = {.min = 1800000, .max = 3600000}, | |
88 | .n = {.min = 2, .max = 6}, | |
89 | .m = {.min = 60, .max = 160}, | |
90 | .m1 = {.min = 0, .max = 0}, | |
91 | .m2 = {.min = 58, .max = 158}, | |
92 | .p = {.min = 5, .max = 100}, | |
93 | .p1 = {.min = 1, .max = 10}, | |
94 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, | |
2adb29ff | 95 | .find_pll = gma_find_best_pll, |
6a227d5f | 96 | }, |
220801bd AC |
97 | { /* CDV_DP_27MHz */ |
98 | .dot = {.min = 160000, .max = 272000}, | |
99 | .vco = {.min = 1809000, .max = 3564000}, | |
100 | .n = {.min = 1, .max = 1}, | |
101 | .m = {.min = 67, .max = 132}, | |
102 | .m1 = {.min = 0, .max = 0}, | |
103 | .m2 = {.min = 65, .max = 130}, | |
104 | .p = {.min = 5, .max = 90}, | |
105 | .p1 = {.min = 1, .max = 9}, | |
106 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10}, | |
107 | .find_pll = cdv_intel_find_dp_pll, | |
108 | }, | |
109 | { /* CDV_DP_100MHz */ | |
110 | .dot = {.min = 160000, .max = 272000}, | |
111 | .vco = {.min = 1800000, .max = 3600000}, | |
112 | .n = {.min = 2, .max = 6}, | |
113 | .m = {.min = 60, .max = 164}, | |
114 | .m1 = {.min = 0, .max = 0}, | |
115 | .m2 = {.min = 58, .max = 162}, | |
116 | .p = {.min = 5, .max = 100}, | |
117 | .p1 = {.min = 1, .max = 10}, | |
118 | .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10}, | |
119 | .find_pll = cdv_intel_find_dp_pll, | |
120 | } | |
6a227d5f AC |
121 | }; |
122 | ||
123 | #define _wait_for(COND, MS, W) ({ \ | |
124 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ | |
125 | int ret__ = 0; \ | |
126 | while (!(COND)) { \ | |
127 | if (time_after(jiffies, timeout__)) { \ | |
128 | ret__ = -ETIMEDOUT; \ | |
129 | break; \ | |
130 | } \ | |
131 | if (W && !in_dbg_master()) \ | |
132 | msleep(W); \ | |
133 | } \ | |
134 | ret__; \ | |
135 | }) | |
136 | ||
137 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) | |
138 | ||
139 | ||
37e7b184 | 140 | int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val) |
6a227d5f AC |
141 | { |
142 | int ret; | |
143 | ||
144 | ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); | |
145 | if (ret) { | |
146 | DRM_ERROR("timeout waiting for SB to idle before read\n"); | |
147 | return ret; | |
148 | } | |
149 | ||
150 | REG_WRITE(SB_ADDR, reg); | |
151 | REG_WRITE(SB_PCKT, | |
152 | SET_FIELD(SB_OPCODE_READ, SB_OPCODE) | | |
153 | SET_FIELD(SB_DEST_DPLL, SB_DEST) | | |
154 | SET_FIELD(0xf, SB_BYTE_ENABLE)); | |
155 | ||
156 | ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); | |
157 | if (ret) { | |
158 | DRM_ERROR("timeout waiting for SB to idle after read\n"); | |
159 | return ret; | |
160 | } | |
161 | ||
162 | *val = REG_READ(SB_DATA); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
37e7b184 | 167 | int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val) |
6a227d5f AC |
168 | { |
169 | int ret; | |
170 | static bool dpio_debug = true; | |
171 | u32 temp; | |
172 | ||
173 | if (dpio_debug) { | |
174 | if (cdv_sb_read(dev, reg, &temp) == 0) | |
175 | DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp); | |
176 | DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val); | |
177 | } | |
178 | ||
179 | ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); | |
180 | if (ret) { | |
181 | DRM_ERROR("timeout waiting for SB to idle before write\n"); | |
182 | return ret; | |
183 | } | |
184 | ||
185 | REG_WRITE(SB_ADDR, reg); | |
186 | REG_WRITE(SB_DATA, val); | |
187 | REG_WRITE(SB_PCKT, | |
188 | SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) | | |
189 | SET_FIELD(SB_DEST_DPLL, SB_DEST) | | |
190 | SET_FIELD(0xf, SB_BYTE_ENABLE)); | |
191 | ||
192 | ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); | |
193 | if (ret) { | |
194 | DRM_ERROR("timeout waiting for SB to idle after write\n"); | |
195 | return ret; | |
196 | } | |
197 | ||
198 | if (dpio_debug) { | |
199 | if (cdv_sb_read(dev, reg, &temp) == 0) | |
200 | DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp); | |
201 | } | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
206 | /* Reset the DPIO configuration register. The BIOS does this at every | |
207 | * mode set. | |
208 | */ | |
37e7b184 | 209 | void cdv_sb_reset(struct drm_device *dev) |
6a227d5f AC |
210 | { |
211 | ||
212 | REG_WRITE(DPIO_CFG, 0); | |
213 | REG_READ(DPIO_CFG); | |
214 | REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); | |
215 | } | |
216 | ||
217 | /* Unlike most Intel display engines, on Cedarview the DPLL registers | |
218 | * are behind this sideband bus. They must be programmed while the | |
219 | * DPLL reference clock is on in the DPLL control register, but before | |
220 | * the DPLL is enabled in the DPLL control register. | |
221 | */ | |
222 | static int | |
223 | cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, | |
2adb29ff | 224 | struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) |
6a227d5f | 225 | { |
213a8434 | 226 | struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc); |
6a227d5f AC |
227 | int pipe = psb_crtc->pipe; |
228 | u32 m, n_vco, p; | |
229 | int ret = 0; | |
230 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
acd7ef92 | 231 | int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB; |
6a227d5f | 232 | u32 ref_value; |
d235e64a | 233 | u32 lane_reg, lane_value; |
6a227d5f AC |
234 | |
235 | cdv_sb_reset(dev); | |
236 | ||
d235e64a AC |
237 | REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); |
238 | ||
239 | udelay(100); | |
6a227d5f AC |
240 | |
241 | /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */ | |
242 | ref_value = 0x68A701; | |
243 | ||
244 | cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value); | |
245 | ||
246 | /* We don't know what the other fields of these regs are, so | |
247 | * leave them in place. | |
248 | */ | |
acd7ef92 AC |
249 | /* |
250 | * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk | |
251 | * for the pipe A/B. Display spec 1.06 has wrong definition. | |
252 | * Correct definition is like below: | |
253 | * | |
254 | * refclka mean use clock from same PLL | |
255 | * | |
256 | * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll | |
257 | * | |
258 | * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA | |
259 | * | |
260 | */ | |
261 | ret = cdv_sb_read(dev, ref_sfr, &ref_value); | |
262 | if (ret) | |
263 | return ret; | |
264 | ref_value &= ~(REF_CLK_MASK); | |
265 | ||
266 | /* use DPLL_A for pipeB on CRT/HDMI */ | |
220801bd | 267 | if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) { |
acd7ef92 AC |
268 | DRM_DEBUG_KMS("use DPLLA for pipe B\n"); |
269 | ref_value |= REF_CLK_DPLLA; | |
270 | } else { | |
271 | DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); | |
272 | ref_value |= REF_CLK_DPLL; | |
273 | } | |
274 | ret = cdv_sb_write(dev, ref_sfr, ref_value); | |
275 | if (ret) | |
276 | return ret; | |
277 | ||
6a227d5f AC |
278 | ret = cdv_sb_read(dev, SB_M(pipe), &m); |
279 | if (ret) | |
280 | return ret; | |
281 | m &= ~SB_M_DIVIDER_MASK; | |
282 | m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); | |
283 | ret = cdv_sb_write(dev, SB_M(pipe), m); | |
284 | if (ret) | |
285 | return ret; | |
286 | ||
287 | ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco); | |
288 | if (ret) | |
289 | return ret; | |
290 | ||
291 | /* Follow the BIOS to program the N_DIVIDER REG */ | |
292 | n_vco &= 0xFFFF; | |
293 | n_vco |= 0x107; | |
294 | n_vco &= ~(SB_N_VCO_SEL_MASK | | |
295 | SB_N_DIVIDER_MASK | | |
296 | SB_N_CB_TUNE_MASK); | |
297 | ||
298 | n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); | |
299 | ||
300 | if (clock->vco < 2250000) { | |
301 | n_vco |= (2 << SB_N_CB_TUNE_SHIFT); | |
302 | n_vco |= (0 << SB_N_VCO_SEL_SHIFT); | |
303 | } else if (clock->vco < 2750000) { | |
304 | n_vco |= (1 << SB_N_CB_TUNE_SHIFT); | |
305 | n_vco |= (1 << SB_N_VCO_SEL_SHIFT); | |
306 | } else if (clock->vco < 3300000) { | |
307 | n_vco |= (0 << SB_N_CB_TUNE_SHIFT); | |
308 | n_vco |= (2 << SB_N_VCO_SEL_SHIFT); | |
309 | } else { | |
310 | n_vco |= (0 << SB_N_CB_TUNE_SHIFT); | |
311 | n_vco |= (3 << SB_N_VCO_SEL_SHIFT); | |
312 | } | |
313 | ||
314 | ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco); | |
315 | if (ret) | |
316 | return ret; | |
317 | ||
318 | ret = cdv_sb_read(dev, SB_P(pipe), &p); | |
319 | if (ret) | |
320 | return ret; | |
321 | p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK); | |
322 | p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); | |
323 | switch (clock->p2) { | |
324 | case 5: | |
325 | p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER); | |
326 | break; | |
327 | case 10: | |
328 | p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER); | |
329 | break; | |
330 | case 14: | |
331 | p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER); | |
332 | break; | |
333 | case 7: | |
334 | p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER); | |
335 | break; | |
336 | default: | |
337 | DRM_ERROR("Bad P2 clock: %d\n", clock->p2); | |
338 | return -EINVAL; | |
339 | } | |
340 | ret = cdv_sb_write(dev, SB_P(pipe), p); | |
341 | if (ret) | |
342 | return ret; | |
343 | ||
d6676096 ZY |
344 | if (ddi_select) { |
345 | if ((ddi_select & DDI_MASK) == DDI0_SELECT) { | |
346 | lane_reg = PSB_LANE0; | |
347 | cdv_sb_read(dev, lane_reg, &lane_value); | |
348 | lane_value &= ~(LANE_PLL_MASK); | |
349 | lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); | |
350 | cdv_sb_write(dev, lane_reg, lane_value); | |
351 | ||
352 | lane_reg = PSB_LANE1; | |
353 | cdv_sb_read(dev, lane_reg, &lane_value); | |
354 | lane_value &= ~(LANE_PLL_MASK); | |
355 | lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); | |
356 | cdv_sb_write(dev, lane_reg, lane_value); | |
357 | } else { | |
358 | lane_reg = PSB_LANE2; | |
359 | cdv_sb_read(dev, lane_reg, &lane_value); | |
360 | lane_value &= ~(LANE_PLL_MASK); | |
361 | lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); | |
362 | cdv_sb_write(dev, lane_reg, lane_value); | |
363 | ||
364 | lane_reg = PSB_LANE3; | |
365 | cdv_sb_read(dev, lane_reg, &lane_value); | |
366 | lane_value &= ~(LANE_PLL_MASK); | |
367 | lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); | |
368 | cdv_sb_write(dev, lane_reg, lane_value); | |
369 | } | |
370 | } | |
6a227d5f AC |
371 | return 0; |
372 | } | |
373 | ||
2adb29ff PJ |
374 | static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc, |
375 | int refclk) | |
6a227d5f | 376 | { |
2adb29ff PJ |
377 | const struct gma_limit_t *limit; |
378 | if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
6a227d5f AC |
379 | /* |
380 | * Now only single-channel LVDS is supported on CDV. If it is | |
381 | * incorrect, please add the dual-channel LVDS. | |
382 | */ | |
383 | if (refclk == 96000) | |
384 | limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96]; | |
385 | else | |
386 | limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100]; | |
d112a816 ZY |
387 | } else if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
388 | psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
220801bd AC |
389 | if (refclk == 27000) |
390 | limit = &cdv_intel_limits[CDV_LIMIT_DP_27]; | |
391 | else | |
392 | limit = &cdv_intel_limits[CDV_LIMIT_DP_100]; | |
6a227d5f AC |
393 | } else { |
394 | if (refclk == 27000) | |
395 | limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27]; | |
396 | else | |
397 | limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96]; | |
398 | } | |
399 | return limit; | |
400 | } | |
401 | ||
402 | /* m1 is reserved as 0 in CDV, n is a ring counter */ | |
2adb29ff | 403 | static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) |
6a227d5f AC |
404 | { |
405 | clock->m = clock->m2 + 2; | |
406 | clock->p = clock->p1 * clock->p2; | |
407 | clock->vco = (refclk * clock->m) / clock->n; | |
408 | clock->dot = clock->vco / clock->p; | |
409 | } | |
410 | ||
2adb29ff PJ |
411 | static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit, |
412 | struct drm_crtc *crtc, int target, | |
413 | int refclk, | |
414 | struct gma_clock_t *best_clock) | |
6a227d5f | 415 | { |
2adb29ff | 416 | struct gma_clock_t clock; |
220801bd AC |
417 | if (refclk == 27000) { |
418 | if (target < 200000) { | |
419 | clock.p1 = 2; | |
420 | clock.p2 = 10; | |
421 | clock.n = 1; | |
422 | clock.m1 = 0; | |
423 | clock.m2 = 118; | |
424 | } else { | |
425 | clock.p1 = 1; | |
426 | clock.p2 = 10; | |
427 | clock.n = 1; | |
428 | clock.m1 = 0; | |
429 | clock.m2 = 98; | |
430 | } | |
431 | } else if (refclk == 100000) { | |
432 | if (target < 200000) { | |
433 | clock.p1 = 2; | |
434 | clock.p2 = 10; | |
435 | clock.n = 5; | |
436 | clock.m1 = 0; | |
437 | clock.m2 = 160; | |
438 | } else { | |
439 | clock.p1 = 1; | |
440 | clock.p2 = 10; | |
441 | clock.n = 5; | |
442 | clock.m1 = 0; | |
443 | clock.m2 = 133; | |
444 | } | |
445 | } else | |
446 | return false; | |
447 | clock.m = clock.m2 + 2; | |
448 | clock.p = clock.p1 * clock.p2; | |
449 | clock.vco = (refclk * clock.m) / clock.n; | |
450 | clock.dot = clock.vco / clock.p; | |
2adb29ff | 451 | memcpy(best_clock, &clock, sizeof(struct gma_clock_t)); |
220801bd AC |
452 | return true; |
453 | } | |
454 | ||
657da160 | 455 | static int cdv_intel_pipe_set_base(struct drm_crtc *crtc, |
6a227d5f AC |
456 | int x, int y, struct drm_framebuffer *old_fb) |
457 | { | |
458 | struct drm_device *dev = crtc->dev; | |
213a8434 | 459 | struct drm_psb_private *dev_priv = dev->dev_private; |
6a227d5f AC |
460 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
461 | struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); | |
462 | int pipe = psb_intel_crtc->pipe; | |
213a8434 | 463 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
6a227d5f | 464 | unsigned long start, offset; |
6a227d5f AC |
465 | u32 dspcntr; |
466 | int ret = 0; | |
467 | ||
468 | if (!gma_power_begin(dev, true)) | |
469 | return 0; | |
470 | ||
471 | /* no fb bound */ | |
472 | if (!crtc->fb) { | |
473 | dev_err(dev->dev, "No FB bound\n"); | |
474 | goto psb_intel_pipe_cleaner; | |
475 | } | |
476 | ||
477 | ||
478 | /* We are displaying this buffer, make sure it is actually loaded | |
479 | into the GTT */ | |
480 | ret = psb_gtt_pin(psbfb->gtt); | |
481 | if (ret < 0) | |
482 | goto psb_intel_pipe_set_base_exit; | |
483 | start = psbfb->gtt->offset; | |
01f2c773 | 484 | offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); |
6a227d5f | 485 | |
213a8434 | 486 | REG_WRITE(map->stride, crtc->fb->pitches[0]); |
6a227d5f | 487 | |
213a8434 | 488 | dspcntr = REG_READ(map->cntr); |
6a227d5f AC |
489 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; |
490 | ||
491 | switch (crtc->fb->bits_per_pixel) { | |
492 | case 8: | |
493 | dspcntr |= DISPPLANE_8BPP; | |
494 | break; | |
495 | case 16: | |
496 | if (crtc->fb->depth == 15) | |
497 | dspcntr |= DISPPLANE_15_16BPP; | |
498 | else | |
499 | dspcntr |= DISPPLANE_16BPP; | |
500 | break; | |
501 | case 24: | |
502 | case 32: | |
503 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
504 | break; | |
505 | default: | |
506 | dev_err(dev->dev, "Unknown color depth\n"); | |
507 | ret = -EINVAL; | |
508 | goto psb_intel_pipe_set_base_exit; | |
509 | } | |
213a8434 | 510 | REG_WRITE(map->cntr, dspcntr); |
6a227d5f AC |
511 | |
512 | dev_dbg(dev->dev, | |
513 | "Writing base %08lX %08lX %d %d\n", start, offset, x, y); | |
514 | ||
213a8434 AC |
515 | REG_WRITE(map->base, offset); |
516 | REG_READ(map->base); | |
517 | REG_WRITE(map->surf, start); | |
518 | REG_READ(map->surf); | |
6a227d5f AC |
519 | |
520 | psb_intel_pipe_cleaner: | |
521 | /* If there was a previous display we can now unpin it */ | |
522 | if (old_fb) | |
523 | psb_gtt_unpin(to_psb_fb(old_fb)->gtt); | |
524 | ||
525 | psb_intel_pipe_set_base_exit: | |
526 | gma_power_end(dev); | |
527 | return ret; | |
528 | } | |
529 | ||
acd7ef92 AC |
530 | #define FIFO_PIPEA (1 << 0) |
531 | #define FIFO_PIPEB (1 << 1) | |
532 | ||
533 | static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe) | |
534 | { | |
535 | struct drm_crtc *crtc; | |
536 | struct drm_psb_private *dev_priv = dev->dev_private; | |
537 | struct psb_intel_crtc *psb_intel_crtc = NULL; | |
538 | ||
539 | crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
540 | psb_intel_crtc = to_psb_intel_crtc(crtc); | |
541 | ||
542 | if (crtc->fb == NULL || !psb_intel_crtc->active) | |
543 | return false; | |
544 | return true; | |
545 | } | |
546 | ||
547 | static bool cdv_intel_single_pipe_active (struct drm_device *dev) | |
548 | { | |
549 | uint32_t pipe_enabled = 0; | |
550 | ||
551 | if (cdv_intel_pipe_enabled(dev, 0)) | |
552 | pipe_enabled |= FIFO_PIPEA; | |
553 | ||
554 | if (cdv_intel_pipe_enabled(dev, 1)) | |
555 | pipe_enabled |= FIFO_PIPEB; | |
556 | ||
557 | ||
558 | DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled); | |
559 | ||
560 | if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB) | |
561 | return true; | |
562 | else | |
563 | return false; | |
564 | } | |
565 | ||
566 | static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc) | |
567 | { | |
568 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | |
569 | struct drm_mode_config *mode_config = &dev->mode_config; | |
570 | struct drm_connector *connector; | |
571 | ||
572 | if (psb_intel_crtc->pipe != 1) | |
573 | return false; | |
574 | ||
575 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
576 | struct psb_intel_encoder *psb_intel_encoder = | |
577 | psb_intel_attached_encoder(connector); | |
578 | ||
579 | if (!connector->encoder | |
580 | || connector->encoder->crtc != crtc) | |
581 | continue; | |
582 | ||
583 | if (psb_intel_encoder->type == INTEL_OUTPUT_LVDS) | |
584 | return true; | |
585 | } | |
586 | ||
587 | return false; | |
588 | } | |
589 | ||
590 | static void cdv_intel_disable_self_refresh (struct drm_device *dev) | |
591 | { | |
592 | if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { | |
593 | ||
594 | /* Disable self-refresh before adjust WM */ | |
595 | REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); | |
596 | REG_READ(FW_BLC_SELF); | |
597 | ||
598 | cdv_intel_wait_for_vblank(dev); | |
599 | ||
600 | /* Cedarview workaround to write ovelay plane, which force to leave | |
601 | * MAX_FIFO state. | |
602 | */ | |
603 | REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); | |
604 | REG_READ(OV_OVADD); | |
605 | ||
606 | cdv_intel_wait_for_vblank(dev); | |
607 | } | |
608 | ||
609 | } | |
610 | ||
611 | static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc *crtc) | |
612 | { | |
613 | ||
614 | if (cdv_intel_single_pipe_active(dev)) { | |
615 | u32 fw; | |
616 | ||
617 | fw = REG_READ(DSPFW1); | |
618 | fw &= ~DSP_FIFO_SR_WM_MASK; | |
619 | fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT); | |
620 | fw &= ~CURSOR_B_FIFO_WM_MASK; | |
621 | fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT); | |
622 | REG_WRITE(DSPFW1, fw); | |
623 | ||
624 | fw = REG_READ(DSPFW2); | |
625 | fw &= ~CURSOR_A_FIFO_WM_MASK; | |
626 | fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT); | |
627 | fw &= ~DSP_PLANE_C_FIFO_WM_MASK; | |
628 | fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT); | |
629 | REG_WRITE(DSPFW2, fw); | |
630 | ||
631 | REG_WRITE(DSPFW3, 0x36000000); | |
632 | ||
633 | /* ignore FW4 */ | |
634 | ||
635 | if (is_pipeb_lvds(dev, crtc)) { | |
636 | REG_WRITE(DSPFW5, 0x00040330); | |
637 | } else { | |
638 | fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) | | |
639 | (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) | | |
640 | (3 << CURSOR_B_FIFO_WM1_SHIFT) | | |
641 | (4 << CURSOR_FIFO_SR_WM1_SHIFT); | |
642 | REG_WRITE(DSPFW5, fw); | |
643 | } | |
644 | ||
645 | REG_WRITE(DSPFW6, 0x10); | |
646 | ||
647 | cdv_intel_wait_for_vblank(dev); | |
648 | ||
649 | /* enable self-refresh for single pipe active */ | |
650 | REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | |
651 | REG_READ(FW_BLC_SELF); | |
652 | cdv_intel_wait_for_vblank(dev); | |
653 | ||
654 | } else { | |
655 | ||
656 | /* HW team suggested values... */ | |
657 | REG_WRITE(DSPFW1, 0x3f880808); | |
658 | REG_WRITE(DSPFW2, 0x0b020202); | |
659 | REG_WRITE(DSPFW3, 0x24000000); | |
660 | REG_WRITE(DSPFW4, 0x08030202); | |
661 | REG_WRITE(DSPFW5, 0x01010101); | |
662 | REG_WRITE(DSPFW6, 0x1d0); | |
663 | ||
664 | cdv_intel_wait_for_vblank(dev); | |
665 | ||
666 | cdv_intel_disable_self_refresh(dev); | |
667 | ||
668 | } | |
669 | } | |
670 | ||
671 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
672 | static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc) | |
673 | { | |
674 | struct drm_device *dev = crtc->dev; | |
213a8434 | 675 | struct drm_psb_private *dev_priv = dev->dev_private; |
acd7ef92 AC |
676 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
677 | int palreg = PALETTE_A; | |
678 | int i; | |
679 | ||
680 | /* The clocks have to be on to load the palette. */ | |
681 | if (!crtc->enabled) | |
682 | return; | |
683 | ||
684 | switch (psb_intel_crtc->pipe) { | |
685 | case 0: | |
686 | break; | |
687 | case 1: | |
688 | palreg = PALETTE_B; | |
689 | break; | |
690 | case 2: | |
691 | palreg = PALETTE_C; | |
692 | break; | |
693 | default: | |
694 | dev_err(dev->dev, "Illegal Pipe Number.\n"); | |
695 | return; | |
696 | } | |
697 | ||
698 | if (gma_power_begin(dev, false)) { | |
699 | for (i = 0; i < 256; i++) { | |
700 | REG_WRITE(palreg + 4 * i, | |
701 | ((psb_intel_crtc->lut_r[i] + | |
702 | psb_intel_crtc->lut_adj[i]) << 16) | | |
703 | ((psb_intel_crtc->lut_g[i] + | |
704 | psb_intel_crtc->lut_adj[i]) << 8) | | |
705 | (psb_intel_crtc->lut_b[i] + | |
706 | psb_intel_crtc->lut_adj[i])); | |
707 | } | |
708 | gma_power_end(dev); | |
709 | } else { | |
710 | for (i = 0; i < 256; i++) { | |
6256304b | 711 | dev_priv->regs.pipe[0].palette[i] = |
acd7ef92 AC |
712 | ((psb_intel_crtc->lut_r[i] + |
713 | psb_intel_crtc->lut_adj[i]) << 16) | | |
714 | ((psb_intel_crtc->lut_g[i] + | |
715 | psb_intel_crtc->lut_adj[i]) << 8) | | |
716 | (psb_intel_crtc->lut_b[i] + | |
717 | psb_intel_crtc->lut_adj[i]); | |
718 | } | |
719 | ||
720 | } | |
721 | } | |
722 | ||
6a227d5f AC |
723 | /** |
724 | * Sets the power management mode of the pipe and plane. | |
725 | * | |
726 | * This code should probably grow support for turning the cursor off and back | |
727 | * on appropriately at the same time as we're turning the pipe off/on. | |
728 | */ | |
729 | static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
730 | { | |
731 | struct drm_device *dev = crtc->dev; | |
213a8434 | 732 | struct drm_psb_private *dev_priv = dev->dev_private; |
6a227d5f AC |
733 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
734 | int pipe = psb_intel_crtc->pipe; | |
213a8434 | 735 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
6a227d5f | 736 | u32 temp; |
6a227d5f AC |
737 | |
738 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
739 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
740 | */ | |
acd7ef92 AC |
741 | cdv_intel_disable_self_refresh(dev); |
742 | ||
6a227d5f AC |
743 | switch (mode) { |
744 | case DRM_MODE_DPMS_ON: | |
745 | case DRM_MODE_DPMS_STANDBY: | |
746 | case DRM_MODE_DPMS_SUSPEND: | |
acd7ef92 | 747 | if (psb_intel_crtc->active) |
25e9dc69 | 748 | break; |
acd7ef92 AC |
749 | |
750 | psb_intel_crtc->active = true; | |
751 | ||
6a227d5f | 752 | /* Enable the DPLL */ |
213a8434 | 753 | temp = REG_READ(map->dpll); |
6a227d5f | 754 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
213a8434 AC |
755 | REG_WRITE(map->dpll, temp); |
756 | REG_READ(map->dpll); | |
6a227d5f AC |
757 | /* Wait for the clocks to stabilize. */ |
758 | udelay(150); | |
213a8434 AC |
759 | REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); |
760 | REG_READ(map->dpll); | |
6a227d5f AC |
761 | /* Wait for the clocks to stabilize. */ |
762 | udelay(150); | |
213a8434 AC |
763 | REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); |
764 | REG_READ(map->dpll); | |
6a227d5f AC |
765 | /* Wait for the clocks to stabilize. */ |
766 | udelay(150); | |
767 | } | |
768 | ||
769 | /* Jim Bish - switch plan and pipe per scott */ | |
770 | /* Enable the plane */ | |
213a8434 | 771 | temp = REG_READ(map->cntr); |
6a227d5f | 772 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
213a8434 | 773 | REG_WRITE(map->cntr, |
6a227d5f AC |
774 | temp | DISPLAY_PLANE_ENABLE); |
775 | /* Flush the plane changes */ | |
213a8434 | 776 | REG_WRITE(map->base, REG_READ(map->base)); |
6a227d5f AC |
777 | } |
778 | ||
779 | udelay(150); | |
780 | ||
781 | /* Enable the pipe */ | |
213a8434 | 782 | temp = REG_READ(map->conf); |
6a227d5f | 783 | if ((temp & PIPEACONF_ENABLE) == 0) |
213a8434 | 784 | REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); |
6a227d5f | 785 | |
213a8434 | 786 | temp = REG_READ(map->status); |
acd7ef92 AC |
787 | temp &= ~(0xFFFF); |
788 | temp |= PIPE_FIFO_UNDERRUN; | |
213a8434 AC |
789 | REG_WRITE(map->status, temp); |
790 | REG_READ(map->status); | |
acd7ef92 | 791 | |
acd7ef92 | 792 | cdv_intel_crtc_load_lut(crtc); |
6a227d5f AC |
793 | |
794 | /* Give the overlay scaler a chance to enable | |
795 | * if it's on this pipe */ | |
796 | /* psb_intel_crtc_dpms_video(crtc, true); TODO */ | |
797 | break; | |
798 | case DRM_MODE_DPMS_OFF: | |
acd7ef92 | 799 | if (!psb_intel_crtc->active) |
25e9dc69 | 800 | break; |
acd7ef92 AC |
801 | |
802 | psb_intel_crtc->active = false; | |
803 | ||
6a227d5f AC |
804 | /* Give the overlay scaler a chance to disable |
805 | * if it's on this pipe */ | |
806 | /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ | |
807 | ||
808 | /* Disable the VGA plane that we never use */ | |
809 | REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); | |
810 | ||
811 | /* Jim Bish - changed pipe/plane here as well. */ | |
812 | ||
acd7ef92 | 813 | drm_vblank_off(dev, pipe); |
6a227d5f AC |
814 | /* Wait for vblank for the disable to take effect */ |
815 | cdv_intel_wait_for_vblank(dev); | |
816 | ||
817 | /* Next, disable display pipes */ | |
213a8434 | 818 | temp = REG_READ(map->conf); |
6a227d5f | 819 | if ((temp & PIPEACONF_ENABLE) != 0) { |
213a8434 AC |
820 | REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); |
821 | REG_READ(map->conf); | |
6a227d5f AC |
822 | } |
823 | ||
824 | /* Wait for vblank for the disable to take effect. */ | |
825 | cdv_intel_wait_for_vblank(dev); | |
826 | ||
827 | udelay(150); | |
828 | ||
829 | /* Disable display plane */ | |
213a8434 | 830 | temp = REG_READ(map->cntr); |
6a227d5f | 831 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { |
213a8434 | 832 | REG_WRITE(map->cntr, |
6a227d5f AC |
833 | temp & ~DISPLAY_PLANE_ENABLE); |
834 | /* Flush the plane changes */ | |
213a8434 AC |
835 | REG_WRITE(map->base, REG_READ(map->base)); |
836 | REG_READ(map->base); | |
6a227d5f AC |
837 | } |
838 | ||
213a8434 | 839 | temp = REG_READ(map->dpll); |
6a227d5f | 840 | if ((temp & DPLL_VCO_ENABLE) != 0) { |
213a8434 AC |
841 | REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); |
842 | REG_READ(map->dpll); | |
6a227d5f AC |
843 | } |
844 | ||
845 | /* Wait for the clocks to turn off. */ | |
846 | udelay(150); | |
847 | break; | |
848 | } | |
25e9dc69 | 849 | cdv_intel_update_watermark(dev, crtc); |
6a227d5f AC |
850 | /*Set FIFO Watermarks*/ |
851 | REG_WRITE(DSPARB, 0x3F3E); | |
852 | } | |
853 | ||
854 | static void cdv_intel_crtc_prepare(struct drm_crtc *crtc) | |
855 | { | |
856 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
857 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
858 | } | |
859 | ||
860 | static void cdv_intel_crtc_commit(struct drm_crtc *crtc) | |
861 | { | |
862 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
863 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
864 | } | |
865 | ||
6a227d5f | 866 | static bool cdv_intel_crtc_mode_fixup(struct drm_crtc *crtc, |
e811f5ae | 867 | const struct drm_display_mode *mode, |
6a227d5f AC |
868 | struct drm_display_mode *adjusted_mode) |
869 | { | |
870 | return true; | |
871 | } | |
872 | ||
873 | ||
874 | /** | |
875 | * Return the pipe currently connected to the panel fitter, | |
876 | * or -1 if the panel fitter is not present or not in use | |
877 | */ | |
878 | static int cdv_intel_panel_fitter_pipe(struct drm_device *dev) | |
879 | { | |
880 | u32 pfit_control; | |
881 | ||
882 | pfit_control = REG_READ(PFIT_CONTROL); | |
883 | ||
884 | /* See if the panel fitter is in use */ | |
885 | if ((pfit_control & PFIT_ENABLE) == 0) | |
886 | return -1; | |
887 | return (pfit_control >> 29) & 0x3; | |
888 | } | |
889 | ||
890 | static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, | |
891 | struct drm_display_mode *mode, | |
892 | struct drm_display_mode *adjusted_mode, | |
893 | int x, int y, | |
894 | struct drm_framebuffer *old_fb) | |
895 | { | |
896 | struct drm_device *dev = crtc->dev; | |
acd7ef92 | 897 | struct drm_psb_private *dev_priv = dev->dev_private; |
6a227d5f AC |
898 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
899 | int pipe = psb_intel_crtc->pipe; | |
213a8434 | 900 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
6a227d5f | 901 | int refclk; |
2adb29ff | 902 | struct gma_clock_t clock; |
6a227d5f | 903 | u32 dpll = 0, dspcntr, pipeconf; |
0313c0de | 904 | bool ok; |
6a227d5f | 905 | bool is_crt = false, is_lvds = false, is_tv = false; |
220801bd | 906 | bool is_hdmi = false, is_dp = false; |
6a227d5f AC |
907 | struct drm_mode_config *mode_config = &dev->mode_config; |
908 | struct drm_connector *connector; | |
2adb29ff | 909 | const struct gma_limit_t *limit; |
d6676096 | 910 | u32 ddi_select = 0; |
d112a816 | 911 | bool is_edp = false; |
6a227d5f AC |
912 | |
913 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
a12d6a07 PJ |
914 | struct psb_intel_encoder *psb_intel_encoder = |
915 | psb_intel_attached_encoder(connector); | |
6a227d5f AC |
916 | |
917 | if (!connector->encoder | |
918 | || connector->encoder->crtc != crtc) | |
919 | continue; | |
920 | ||
d6676096 | 921 | ddi_select = psb_intel_encoder->ddi_select; |
a12d6a07 | 922 | switch (psb_intel_encoder->type) { |
6a227d5f AC |
923 | case INTEL_OUTPUT_LVDS: |
924 | is_lvds = true; | |
925 | break; | |
6a227d5f AC |
926 | case INTEL_OUTPUT_TVOUT: |
927 | is_tv = true; | |
928 | break; | |
929 | case INTEL_OUTPUT_ANALOG: | |
930 | is_crt = true; | |
931 | break; | |
932 | case INTEL_OUTPUT_HDMI: | |
933 | is_hdmi = true; | |
934 | break; | |
220801bd AC |
935 | case INTEL_OUTPUT_DISPLAYPORT: |
936 | is_dp = true; | |
937 | break; | |
d112a816 ZY |
938 | case INTEL_OUTPUT_EDP: |
939 | is_edp = true; | |
940 | break; | |
d6676096 ZY |
941 | default: |
942 | DRM_ERROR("invalid output type.\n"); | |
943 | return 0; | |
6a227d5f AC |
944 | } |
945 | } | |
946 | ||
acd7ef92 AC |
947 | if (dev_priv->dplla_96mhz) |
948 | /* low-end sku, 96/100 mhz */ | |
949 | refclk = 96000; | |
950 | else | |
951 | /* high-end sku, 27/100 mhz */ | |
6a227d5f | 952 | refclk = 27000; |
d112a816 ZY |
953 | if (is_dp || is_edp) { |
954 | /* | |
955 | * Based on the spec the low-end SKU has only CRT/LVDS. So it is | |
956 | * unnecessary to consider it for DP/eDP. | |
957 | * On the high-end SKU, it will use the 27/100M reference clk | |
958 | * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise | |
959 | * it will be 27MHz. From the VBIOS code it seems that the pipe A choose | |
960 | * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. | |
961 | */ | |
220801bd AC |
962 | if (pipe == 0) |
963 | refclk = 27000; | |
964 | else | |
965 | refclk = 100000; | |
966 | } | |
6a227d5f | 967 | |
acd7ef92 AC |
968 | if (is_lvds && dev_priv->lvds_use_ssc) { |
969 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
970 | DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); | |
971 | } | |
972 | ||
6a227d5f | 973 | drm_mode_debug_printmodeline(adjusted_mode); |
d6676096 | 974 | |
2adb29ff | 975 | limit = psb_intel_crtc->clock_funcs->limit(crtc, refclk); |
6a227d5f | 976 | |
d6676096 | 977 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, |
6a227d5f AC |
978 | &clock); |
979 | if (!ok) { | |
2adb29ff PJ |
980 | DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d", |
981 | adjusted_mode->clock, clock.dot); | |
6a227d5f AC |
982 | return 0; |
983 | } | |
984 | ||
985 | dpll = DPLL_VGA_MODE_DIS; | |
986 | if (is_tv) { | |
987 | /* XXX: just matching BIOS for now */ | |
988 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
989 | dpll |= 3; | |
990 | } | |
acd7ef92 | 991 | /* dpll |= PLL_REF_INPUT_DREFCLK; */ |
6a227d5f | 992 | |
f76c0dde AC |
993 | if (is_dp || is_edp) { |
994 | cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
220801bd AC |
995 | } else { |
996 | REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0); | |
997 | REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0); | |
998 | REG_WRITE(PIPE_DP_LINK_M(pipe), 0); | |
999 | REG_WRITE(PIPE_DP_LINK_N(pipe), 0); | |
1000 | } | |
1001 | ||
6a227d5f | 1002 | dpll |= DPLL_SYNCLOCK_ENABLE; |
acd7ef92 | 1003 | /* if (is_lvds) |
6a227d5f AC |
1004 | dpll |= DPLLB_MODE_LVDS; |
1005 | else | |
acd7ef92 | 1006 | dpll |= DPLLB_MODE_DAC_SERIAL; */ |
6a227d5f AC |
1007 | /* dpll |= (2 << 11); */ |
1008 | ||
1009 | /* setup pipeconf */ | |
213a8434 | 1010 | pipeconf = REG_READ(map->conf); |
6a227d5f | 1011 | |
d112a816 ZY |
1012 | pipeconf &= ~(PIPE_BPC_MASK); |
1013 | if (is_edp) { | |
1014 | switch (dev_priv->edp.bpp) { | |
1015 | case 24: | |
1016 | pipeconf |= PIPE_8BPC; | |
1017 | break; | |
1018 | case 18: | |
1019 | pipeconf |= PIPE_6BPC; | |
1020 | break; | |
1021 | case 30: | |
1022 | pipeconf |= PIPE_10BPC; | |
1023 | break; | |
1024 | default: | |
1025 | pipeconf |= PIPE_8BPC; | |
1026 | break; | |
1027 | } | |
1028 | } else if (is_lvds) { | |
1029 | /* the BPC will be 6 if it is 18-bit LVDS panel */ | |
1030 | if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) | |
1031 | pipeconf |= PIPE_8BPC; | |
1032 | else | |
1033 | pipeconf |= PIPE_6BPC; | |
1034 | } else | |
1035 | pipeconf |= PIPE_8BPC; | |
1036 | ||
6a227d5f AC |
1037 | /* Set up the display plane register */ |
1038 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
1039 | ||
1040 | if (pipe == 0) | |
1041 | dspcntr |= DISPPLANE_SEL_PIPE_A; | |
1042 | else | |
1043 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
1044 | ||
1045 | dspcntr |= DISPLAY_PLANE_ENABLE; | |
1046 | pipeconf |= PIPEACONF_ENABLE; | |
1047 | ||
213a8434 AC |
1048 | REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); |
1049 | REG_READ(map->dpll); | |
6a227d5f | 1050 | |
d6676096 | 1051 | cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select); |
6a227d5f AC |
1052 | |
1053 | udelay(150); | |
1054 | ||
1055 | ||
1056 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
1057 | * This is an exception to the general rule that mode_set doesn't turn | |
1058 | * things on. | |
1059 | */ | |
1060 | if (is_lvds) { | |
1061 | u32 lvds = REG_READ(LVDS); | |
1062 | ||
1063 | lvds |= | |
1064 | LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | | |
1065 | LVDS_PIPEB_SELECT; | |
1066 | /* Set the B0-B3 data pairs corresponding to | |
1067 | * whether we're going to | |
1068 | * set the DPLLs for dual-channel mode or not. | |
1069 | */ | |
1070 | if (clock.p2 == 7) | |
1071 | lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
1072 | else | |
1073 | lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
1074 | ||
1075 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
1076 | * appropriately here, but we need to look more | |
1077 | * thoroughly into how panels behave in the two modes. | |
1078 | */ | |
1079 | ||
1080 | REG_WRITE(LVDS, lvds); | |
1081 | REG_READ(LVDS); | |
1082 | } | |
1083 | ||
1084 | dpll |= DPLL_VCO_ENABLE; | |
1085 | ||
1086 | /* Disable the panel fitter if it was on our pipe */ | |
1087 | if (cdv_intel_panel_fitter_pipe(dev) == pipe) | |
1088 | REG_WRITE(PFIT_CONTROL, 0); | |
1089 | ||
1090 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); | |
1091 | drm_mode_debug_printmodeline(mode); | |
1092 | ||
213a8434 AC |
1093 | REG_WRITE(map->dpll, |
1094 | (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); | |
1095 | REG_READ(map->dpll); | |
6a227d5f AC |
1096 | /* Wait for the clocks to stabilize. */ |
1097 | udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */ | |
1098 | ||
213a8434 | 1099 | if (!(REG_READ(map->dpll) & DPLL_LOCK)) { |
6a227d5f AC |
1100 | dev_err(dev->dev, "Failed to get DPLL lock\n"); |
1101 | return -EBUSY; | |
1102 | } | |
1103 | ||
1104 | { | |
1105 | int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; | |
213a8434 | 1106 | REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); |
6a227d5f AC |
1107 | } |
1108 | ||
213a8434 | 1109 | REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | |
6a227d5f | 1110 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
213a8434 | 1111 | REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | |
6a227d5f | 1112 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
213a8434 | 1113 | REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | |
6a227d5f | 1114 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
213a8434 | 1115 | REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | |
6a227d5f | 1116 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
213a8434 | 1117 | REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | |
6a227d5f | 1118 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
213a8434 | 1119 | REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | |
6a227d5f AC |
1120 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
1121 | /* pipesrc and dspsize control the size that is scaled from, | |
1122 | * which should always be the user's requested size. | |
1123 | */ | |
213a8434 | 1124 | REG_WRITE(map->size, |
6a227d5f | 1125 | ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); |
213a8434 AC |
1126 | REG_WRITE(map->pos, 0); |
1127 | REG_WRITE(map->src, | |
6a227d5f | 1128 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
213a8434 AC |
1129 | REG_WRITE(map->conf, pipeconf); |
1130 | REG_READ(map->conf); | |
6a227d5f AC |
1131 | |
1132 | cdv_intel_wait_for_vblank(dev); | |
1133 | ||
213a8434 | 1134 | REG_WRITE(map->cntr, dspcntr); |
6a227d5f AC |
1135 | |
1136 | /* Flush the plane changes */ | |
1137 | { | |
1138 | struct drm_crtc_helper_funcs *crtc_funcs = | |
1139 | crtc->helper_private; | |
1140 | crtc_funcs->mode_set_base(crtc, x, y, old_fb); | |
1141 | } | |
1142 | ||
1143 | cdv_intel_wait_for_vblank(dev); | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
6a227d5f AC |
1148 | |
1149 | /** | |
1150 | * Save HW states of giving crtc | |
1151 | */ | |
1152 | static void cdv_intel_crtc_save(struct drm_crtc *crtc) | |
1153 | { | |
1154 | struct drm_device *dev = crtc->dev; | |
213a8434 | 1155 | struct drm_psb_private *dev_priv = dev->dev_private; |
6a227d5f AC |
1156 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
1157 | struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; | |
213a8434 | 1158 | const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; |
6a227d5f AC |
1159 | uint32_t paletteReg; |
1160 | int i; | |
1161 | ||
1162 | if (!crtc_state) { | |
1163 | dev_dbg(dev->dev, "No CRTC state found\n"); | |
1164 | return; | |
1165 | } | |
1166 | ||
213a8434 AC |
1167 | crtc_state->saveDSPCNTR = REG_READ(map->cntr); |
1168 | crtc_state->savePIPECONF = REG_READ(map->conf); | |
1169 | crtc_state->savePIPESRC = REG_READ(map->src); | |
1170 | crtc_state->saveFP0 = REG_READ(map->fp0); | |
1171 | crtc_state->saveFP1 = REG_READ(map->fp1); | |
1172 | crtc_state->saveDPLL = REG_READ(map->dpll); | |
1173 | crtc_state->saveHTOTAL = REG_READ(map->htotal); | |
1174 | crtc_state->saveHBLANK = REG_READ(map->hblank); | |
1175 | crtc_state->saveHSYNC = REG_READ(map->hsync); | |
1176 | crtc_state->saveVTOTAL = REG_READ(map->vtotal); | |
1177 | crtc_state->saveVBLANK = REG_READ(map->vblank); | |
1178 | crtc_state->saveVSYNC = REG_READ(map->vsync); | |
1179 | crtc_state->saveDSPSTRIDE = REG_READ(map->stride); | |
6a227d5f AC |
1180 | |
1181 | /*NOTE: DSPSIZE DSPPOS only for psb*/ | |
213a8434 AC |
1182 | crtc_state->saveDSPSIZE = REG_READ(map->size); |
1183 | crtc_state->saveDSPPOS = REG_READ(map->pos); | |
6a227d5f | 1184 | |
213a8434 | 1185 | crtc_state->saveDSPBASE = REG_READ(map->base); |
6a227d5f AC |
1186 | |
1187 | DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", | |
1188 | crtc_state->saveDSPCNTR, | |
1189 | crtc_state->savePIPECONF, | |
1190 | crtc_state->savePIPESRC, | |
1191 | crtc_state->saveFP0, | |
1192 | crtc_state->saveFP1, | |
1193 | crtc_state->saveDPLL, | |
1194 | crtc_state->saveHTOTAL, | |
1195 | crtc_state->saveHBLANK, | |
1196 | crtc_state->saveHSYNC, | |
1197 | crtc_state->saveVTOTAL, | |
1198 | crtc_state->saveVBLANK, | |
1199 | crtc_state->saveVSYNC, | |
1200 | crtc_state->saveDSPSTRIDE, | |
1201 | crtc_state->saveDSPSIZE, | |
1202 | crtc_state->saveDSPPOS, | |
1203 | crtc_state->saveDSPBASE | |
1204 | ); | |
1205 | ||
213a8434 | 1206 | paletteReg = map->palette; |
6a227d5f AC |
1207 | for (i = 0; i < 256; ++i) |
1208 | crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); | |
1209 | } | |
1210 | ||
1211 | /** | |
1212 | * Restore HW states of giving crtc | |
1213 | */ | |
1214 | static void cdv_intel_crtc_restore(struct drm_crtc *crtc) | |
1215 | { | |
1216 | struct drm_device *dev = crtc->dev; | |
213a8434 | 1217 | struct drm_psb_private *dev_priv = dev->dev_private; |
6a227d5f AC |
1218 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
1219 | struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; | |
213a8434 | 1220 | const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; |
6a227d5f AC |
1221 | uint32_t paletteReg; |
1222 | int i; | |
1223 | ||
1224 | if (!crtc_state) { | |
1225 | dev_dbg(dev->dev, "No crtc state\n"); | |
1226 | return; | |
1227 | } | |
1228 | ||
1229 | DRM_DEBUG( | |
1230 | "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", | |
213a8434 AC |
1231 | REG_READ(map->cntr), |
1232 | REG_READ(map->conf), | |
1233 | REG_READ(map->src), | |
1234 | REG_READ(map->fp0), | |
1235 | REG_READ(map->fp1), | |
1236 | REG_READ(map->dpll), | |
1237 | REG_READ(map->htotal), | |
1238 | REG_READ(map->hblank), | |
1239 | REG_READ(map->hsync), | |
1240 | REG_READ(map->vtotal), | |
1241 | REG_READ(map->vblank), | |
1242 | REG_READ(map->vsync), | |
1243 | REG_READ(map->stride), | |
1244 | REG_READ(map->size), | |
1245 | REG_READ(map->pos), | |
1246 | REG_READ(map->base) | |
1247 | ); | |
6a227d5f AC |
1248 | |
1249 | DRM_DEBUG( | |
1250 | "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n", | |
1251 | crtc_state->saveDSPCNTR, | |
1252 | crtc_state->savePIPECONF, | |
1253 | crtc_state->savePIPESRC, | |
1254 | crtc_state->saveFP0, | |
1255 | crtc_state->saveFP1, | |
1256 | crtc_state->saveDPLL, | |
1257 | crtc_state->saveHTOTAL, | |
1258 | crtc_state->saveHBLANK, | |
1259 | crtc_state->saveHSYNC, | |
1260 | crtc_state->saveVTOTAL, | |
1261 | crtc_state->saveVBLANK, | |
1262 | crtc_state->saveVSYNC, | |
1263 | crtc_state->saveDSPSTRIDE, | |
1264 | crtc_state->saveDSPSIZE, | |
1265 | crtc_state->saveDSPPOS, | |
1266 | crtc_state->saveDSPBASE | |
213a8434 | 1267 | ); |
6a227d5f AC |
1268 | |
1269 | ||
1270 | if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { | |
213a8434 AC |
1271 | REG_WRITE(map->dpll, |
1272 | crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); | |
1273 | REG_READ(map->dpll); | |
6a227d5f | 1274 | DRM_DEBUG("write dpll: %x\n", |
213a8434 | 1275 | REG_READ(map->dpll)); |
6a227d5f AC |
1276 | udelay(150); |
1277 | } | |
1278 | ||
213a8434 AC |
1279 | REG_WRITE(map->fp0, crtc_state->saveFP0); |
1280 | REG_READ(map->fp0); | |
6a227d5f | 1281 | |
213a8434 AC |
1282 | REG_WRITE(map->fp1, crtc_state->saveFP1); |
1283 | REG_READ(map->fp1); | |
6a227d5f | 1284 | |
213a8434 AC |
1285 | REG_WRITE(map->dpll, crtc_state->saveDPLL); |
1286 | REG_READ(map->dpll); | |
6a227d5f AC |
1287 | udelay(150); |
1288 | ||
213a8434 AC |
1289 | REG_WRITE(map->htotal, crtc_state->saveHTOTAL); |
1290 | REG_WRITE(map->hblank, crtc_state->saveHBLANK); | |
1291 | REG_WRITE(map->hsync, crtc_state->saveHSYNC); | |
1292 | REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); | |
1293 | REG_WRITE(map->vblank, crtc_state->saveVBLANK); | |
1294 | REG_WRITE(map->vsync, crtc_state->saveVSYNC); | |
1295 | REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); | |
6a227d5f | 1296 | |
213a8434 AC |
1297 | REG_WRITE(map->size, crtc_state->saveDSPSIZE); |
1298 | REG_WRITE(map->pos, crtc_state->saveDSPPOS); | |
6a227d5f | 1299 | |
213a8434 AC |
1300 | REG_WRITE(map->src, crtc_state->savePIPESRC); |
1301 | REG_WRITE(map->base, crtc_state->saveDSPBASE); | |
1302 | REG_WRITE(map->conf, crtc_state->savePIPECONF); | |
6a227d5f AC |
1303 | |
1304 | cdv_intel_wait_for_vblank(dev); | |
1305 | ||
213a8434 AC |
1306 | REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); |
1307 | REG_WRITE(map->base, crtc_state->saveDSPBASE); | |
6a227d5f AC |
1308 | |
1309 | cdv_intel_wait_for_vblank(dev); | |
1310 | ||
213a8434 | 1311 | paletteReg = map->palette; |
6a227d5f AC |
1312 | for (i = 0; i < 256; ++i) |
1313 | REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); | |
1314 | } | |
1315 | ||
1316 | static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc, | |
1317 | struct drm_file *file_priv, | |
1318 | uint32_t handle, | |
1319 | uint32_t width, uint32_t height) | |
1320 | { | |
1321 | struct drm_device *dev = crtc->dev; | |
1322 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | |
1323 | int pipe = psb_intel_crtc->pipe; | |
1324 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; | |
1325 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; | |
1326 | uint32_t temp; | |
1327 | size_t addr = 0; | |
1328 | struct gtt_range *gt; | |
1329 | struct drm_gem_object *obj; | |
70b1304e | 1330 | int ret = 0; |
6a227d5f AC |
1331 | |
1332 | /* if we want to turn of the cursor ignore width and height */ | |
1333 | if (!handle) { | |
1334 | /* turn off the cursor */ | |
1335 | temp = CURSOR_MODE_DISABLE; | |
1336 | ||
1337 | if (gma_power_begin(dev, false)) { | |
1338 | REG_WRITE(control, temp); | |
1339 | REG_WRITE(base, 0); | |
1340 | gma_power_end(dev); | |
1341 | } | |
1342 | ||
1343 | /* unpin the old GEM object */ | |
1344 | if (psb_intel_crtc->cursor_obj) { | |
1345 | gt = container_of(psb_intel_crtc->cursor_obj, | |
1346 | struct gtt_range, gem); | |
1347 | psb_gtt_unpin(gt); | |
1348 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); | |
1349 | psb_intel_crtc->cursor_obj = NULL; | |
1350 | } | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
1355 | /* Currently we only support 64x64 cursors */ | |
1356 | if (width != 64 || height != 64) { | |
1357 | dev_dbg(dev->dev, "we currently only support 64x64 cursors\n"); | |
1358 | return -EINVAL; | |
1359 | } | |
1360 | ||
1361 | obj = drm_gem_object_lookup(dev, file_priv, handle); | |
1362 | if (!obj) | |
1363 | return -ENOENT; | |
1364 | ||
1365 | if (obj->size < width * height * 4) { | |
1366 | dev_dbg(dev->dev, "buffer is to small\n"); | |
70b1304e PJ |
1367 | ret = -ENOMEM; |
1368 | goto unref_cursor; | |
6a227d5f AC |
1369 | } |
1370 | ||
1371 | gt = container_of(obj, struct gtt_range, gem); | |
1372 | ||
1373 | /* Pin the memory into the GTT */ | |
1374 | ret = psb_gtt_pin(gt); | |
1375 | if (ret) { | |
1376 | dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); | |
70b1304e | 1377 | goto unref_cursor; |
6a227d5f AC |
1378 | } |
1379 | ||
1380 | addr = gt->offset; /* Or resource.start ??? */ | |
1381 | ||
1382 | psb_intel_crtc->cursor_addr = addr; | |
1383 | ||
1384 | temp = 0; | |
1385 | /* set the pipe for the cursor */ | |
1386 | temp |= (pipe << 28); | |
1387 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
1388 | ||
1389 | if (gma_power_begin(dev, false)) { | |
1390 | REG_WRITE(control, temp); | |
1391 | REG_WRITE(base, addr); | |
1392 | gma_power_end(dev); | |
1393 | } | |
1394 | ||
1395 | /* unpin the old GEM object */ | |
1396 | if (psb_intel_crtc->cursor_obj) { | |
1397 | gt = container_of(psb_intel_crtc->cursor_obj, | |
1398 | struct gtt_range, gem); | |
1399 | psb_gtt_unpin(gt); | |
1400 | drm_gem_object_unreference(psb_intel_crtc->cursor_obj); | |
6a227d5f | 1401 | } |
70b1304e PJ |
1402 | |
1403 | psb_intel_crtc->cursor_obj = obj; | |
1404 | return ret; | |
1405 | ||
1406 | unref_cursor: | |
1407 | drm_gem_object_unreference(obj); | |
1408 | return ret; | |
6a227d5f AC |
1409 | } |
1410 | ||
1411 | static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
1412 | { | |
1413 | struct drm_device *dev = crtc->dev; | |
1414 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | |
1415 | int pipe = psb_intel_crtc->pipe; | |
1416 | uint32_t temp = 0; | |
1417 | uint32_t adder; | |
1418 | ||
1419 | ||
1420 | if (x < 0) { | |
1421 | temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); | |
1422 | x = -x; | |
1423 | } | |
1424 | if (y < 0) { | |
1425 | temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); | |
1426 | y = -y; | |
1427 | } | |
1428 | ||
1429 | temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); | |
1430 | temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); | |
1431 | ||
1432 | adder = psb_intel_crtc->cursor_addr; | |
1433 | ||
1434 | if (gma_power_begin(dev, false)) { | |
1435 | REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); | |
1436 | REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); | |
1437 | gma_power_end(dev); | |
1438 | } | |
1439 | return 0; | |
1440 | } | |
1441 | ||
1442 | static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, | |
1443 | u16 *green, u16 *blue, uint32_t start, uint32_t size) | |
1444 | { | |
1445 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | |
1446 | int i; | |
1447 | int end = (start + size > 256) ? 256 : start + size; | |
1448 | ||
1449 | for (i = start; i < end; i++) { | |
1450 | psb_intel_crtc->lut_r[i] = red[i] >> 8; | |
1451 | psb_intel_crtc->lut_g[i] = green[i] >> 8; | |
1452 | psb_intel_crtc->lut_b[i] = blue[i] >> 8; | |
1453 | } | |
1454 | ||
1455 | cdv_intel_crtc_load_lut(crtc); | |
1456 | } | |
1457 | ||
1458 | static int cdv_crtc_set_config(struct drm_mode_set *set) | |
1459 | { | |
1460 | int ret = 0; | |
1461 | struct drm_device *dev = set->crtc->dev; | |
1462 | struct drm_psb_private *dev_priv = dev->dev_private; | |
1463 | ||
1464 | if (!dev_priv->rpm_enabled) | |
1465 | return drm_crtc_helper_set_config(set); | |
1466 | ||
1467 | pm_runtime_forbid(&dev->pdev->dev); | |
1468 | ||
1469 | ret = drm_crtc_helper_set_config(set); | |
1470 | ||
1471 | pm_runtime_allow(&dev->pdev->dev); | |
1472 | ||
1473 | return ret; | |
1474 | } | |
1475 | ||
1476 | /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ | |
1477 | ||
1478 | /* FIXME: why are we using this, should it be cdv_ in this tree ? */ | |
1479 | ||
2adb29ff | 1480 | static void i8xx_clock(int refclk, struct gma_clock_t *clock) |
6a227d5f AC |
1481 | { |
1482 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); | |
1483 | clock->p = clock->p1 * clock->p2; | |
1484 | clock->vco = refclk * clock->m / (clock->n + 2); | |
1485 | clock->dot = clock->vco / clock->p; | |
1486 | } | |
1487 | ||
1488 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
1489 | static int cdv_intel_crtc_clock_get(struct drm_device *dev, | |
1490 | struct drm_crtc *crtc) | |
1491 | { | |
213a8434 | 1492 | struct drm_psb_private *dev_priv = dev->dev_private; |
6a227d5f AC |
1493 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); |
1494 | int pipe = psb_intel_crtc->pipe; | |
213a8434 | 1495 | const struct psb_offset *map = &dev_priv->regmap[pipe]; |
6a227d5f AC |
1496 | u32 dpll; |
1497 | u32 fp; | |
2adb29ff | 1498 | struct gma_clock_t clock; |
6a227d5f | 1499 | bool is_lvds; |
6256304b | 1500 | struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; |
6a227d5f AC |
1501 | |
1502 | if (gma_power_begin(dev, false)) { | |
213a8434 | 1503 | dpll = REG_READ(map->dpll); |
6a227d5f | 1504 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
213a8434 | 1505 | fp = REG_READ(map->fp0); |
6a227d5f | 1506 | else |
213a8434 | 1507 | fp = REG_READ(map->fp1); |
6a227d5f AC |
1508 | is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); |
1509 | gma_power_end(dev); | |
1510 | } else { | |
6256304b | 1511 | dpll = p->dpll; |
6a227d5f | 1512 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) |
6256304b | 1513 | fp = p->fp0; |
6a227d5f | 1514 | else |
6256304b | 1515 | fp = p->fp1; |
6a227d5f | 1516 | |
648a8e34 | 1517 | is_lvds = (pipe == 1) && |
c6265ff5 | 1518 | (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN); |
6a227d5f AC |
1519 | } |
1520 | ||
1521 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
1522 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
1523 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
1524 | ||
1525 | if (is_lvds) { | |
1526 | clock.p1 = | |
1527 | ffs((dpll & | |
1528 | DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
1529 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
1530 | if (clock.p1 == 0) { | |
1531 | clock.p1 = 4; | |
1532 | dev_err(dev->dev, "PLL %d\n", dpll); | |
1533 | } | |
1534 | clock.p2 = 14; | |
1535 | ||
1536 | if ((dpll & PLL_REF_INPUT_MASK) == | |
1537 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
1538 | /* XXX: might not be 66MHz */ | |
1539 | i8xx_clock(66000, &clock); | |
1540 | } else | |
1541 | i8xx_clock(48000, &clock); | |
1542 | } else { | |
1543 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
1544 | clock.p1 = 2; | |
1545 | else { | |
1546 | clock.p1 = | |
1547 | ((dpll & | |
1548 | DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
1549 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
1550 | } | |
1551 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
1552 | clock.p2 = 4; | |
1553 | else | |
1554 | clock.p2 = 2; | |
1555 | ||
1556 | i8xx_clock(48000, &clock); | |
1557 | } | |
1558 | ||
1559 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
1560 | * i830PllIsValid() because it relies on the xf86_config connector | |
1561 | * configuration being accurate, which it isn't necessarily. | |
1562 | */ | |
1563 | ||
1564 | return clock.dot; | |
1565 | } | |
1566 | ||
1567 | /** Returns the currently programmed mode of the given pipe. */ | |
1568 | struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, | |
1569 | struct drm_crtc *crtc) | |
1570 | { | |
1571 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | |
1572 | int pipe = psb_intel_crtc->pipe; | |
213a8434 AC |
1573 | struct drm_psb_private *dev_priv = dev->dev_private; |
1574 | struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; | |
1575 | const struct psb_offset *map = &dev_priv->regmap[pipe]; | |
6a227d5f AC |
1576 | struct drm_display_mode *mode; |
1577 | int htot; | |
1578 | int hsync; | |
1579 | int vtot; | |
1580 | int vsync; | |
6a227d5f AC |
1581 | |
1582 | if (gma_power_begin(dev, false)) { | |
213a8434 AC |
1583 | htot = REG_READ(map->htotal); |
1584 | hsync = REG_READ(map->hsync); | |
1585 | vtot = REG_READ(map->vtotal); | |
1586 | vsync = REG_READ(map->vsync); | |
6a227d5f AC |
1587 | gma_power_end(dev); |
1588 | } else { | |
6256304b AC |
1589 | htot = p->htotal; |
1590 | hsync = p->hsync; | |
1591 | vtot = p->vtotal; | |
1592 | vsync = p->vsync; | |
6a227d5f AC |
1593 | } |
1594 | ||
1595 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
1596 | if (!mode) | |
1597 | return NULL; | |
1598 | ||
1599 | mode->clock = cdv_intel_crtc_clock_get(dev, crtc); | |
1600 | mode->hdisplay = (htot & 0xffff) + 1; | |
1601 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
1602 | mode->hsync_start = (hsync & 0xffff) + 1; | |
1603 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
1604 | mode->vdisplay = (vtot & 0xffff) + 1; | |
1605 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
1606 | mode->vsync_start = (vsync & 0xffff) + 1; | |
1607 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
1608 | ||
1609 | drm_mode_set_name(mode); | |
1610 | drm_mode_set_crtcinfo(mode, 0); | |
1611 | ||
1612 | return mode; | |
1613 | } | |
1614 | ||
1615 | static void cdv_intel_crtc_destroy(struct drm_crtc *crtc) | |
1616 | { | |
1617 | struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); | |
1618 | ||
1619 | kfree(psb_intel_crtc->crtc_state); | |
1620 | drm_crtc_cleanup(crtc); | |
1621 | kfree(psb_intel_crtc); | |
1622 | } | |
1623 | ||
22e7c385 PJ |
1624 | static void cdv_intel_crtc_disable(struct drm_crtc *crtc) |
1625 | { | |
1626 | struct gtt_range *gt; | |
1627 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
1628 | ||
1629 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
1630 | ||
1631 | if (crtc->fb) { | |
1632 | gt = to_psb_fb(crtc->fb)->gtt; | |
1633 | psb_gtt_unpin(gt); | |
1634 | } | |
1635 | } | |
1636 | ||
6a227d5f AC |
1637 | const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = { |
1638 | .dpms = cdv_intel_crtc_dpms, | |
1639 | .mode_fixup = cdv_intel_crtc_mode_fixup, | |
1640 | .mode_set = cdv_intel_crtc_mode_set, | |
1641 | .mode_set_base = cdv_intel_pipe_set_base, | |
1642 | .prepare = cdv_intel_crtc_prepare, | |
1643 | .commit = cdv_intel_crtc_commit, | |
22e7c385 | 1644 | .disable = cdv_intel_crtc_disable, |
6a227d5f AC |
1645 | }; |
1646 | ||
1647 | const struct drm_crtc_funcs cdv_intel_crtc_funcs = { | |
1648 | .save = cdv_intel_crtc_save, | |
1649 | .restore = cdv_intel_crtc_restore, | |
1650 | .cursor_set = cdv_intel_crtc_cursor_set, | |
1651 | .cursor_move = cdv_intel_crtc_cursor_move, | |
1652 | .gamma_set = cdv_intel_crtc_gamma_set, | |
1653 | .set_config = cdv_crtc_set_config, | |
1654 | .destroy = cdv_intel_crtc_destroy, | |
1655 | }; | |
2adb29ff PJ |
1656 | |
1657 | const struct gma_clock_funcs cdv_clock_funcs = { | |
1658 | .clock = cdv_intel_clock, | |
1659 | .limit = cdv_intel_limit, | |
1660 | .pll_is_valid = gma_pll_is_valid, | |
1661 | }; |