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drm/gma500/cdv: Convert to gma_pipe_set_base()
[deliverable/linux.git] / drivers / gpu / drm / gma500 / cdv_intel_display.c
CommitLineData
6a227d5f
AC		 1/*
2 * Copyright © 2006-2011 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * Authors:
18 * Eric Anholt <eric@anholt.net>
19 */
20
21#include <linux/i2c.h>
22#include <linux/pm_runtime.h>
23
24#include <drm/drmP.h>
25#include "framebuffer.h"
26#include "psb_drv.h"
27#include "psb_intel_drv.h"
28#include "psb_intel_reg.h"
fe477cc1 29#include "gma_display.h"
6a227d5f
AC		 30#include "power.h"
31#include "cdv_device.h"
32
2adb29ff
PJ		 33static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
34 struct drm_crtc *crtc, int target,
35 int refclk, struct gma_clock_t *best_clock);
6a227d5f 36
d6676096 37
6a227d5f
AC		 38#define CDV_LIMIT_SINGLE_LVDS_96 0
39#define CDV_LIMIT_SINGLE_LVDS_100 1
40#define CDV_LIMIT_DAC_HDMI_27 2
41#define CDV_LIMIT_DAC_HDMI_96 3
220801bd
AC		 42#define CDV_LIMIT_DP_27 4
43#define CDV_LIMIT_DP_100 5
6a227d5f 44
2adb29ff 45static const struct gma_limit_t cdv_intel_limits[] = {
28bbda39 46 { /* CDV_SINGLE_LVDS_96MHz */
6a227d5f
AC		 47 .dot = {.min = 20000, .max = 115500},
48 .vco = {.min = 1800000, .max = 3600000},
49 .n = {.min = 2, .max = 6},
50 .m = {.min = 60, .max = 160},
51 .m1 = {.min = 0, .max = 0},
52 .m2 = {.min = 58, .max = 158},
53 .p = {.min = 28, .max = 140},
54 .p1 = {.min = 2, .max = 10},
2adb29ff
PJ		 55 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
56 .find_pll = gma_find_best_pll,
6a227d5f
AC		 57 },
58 { /* CDV_SINGLE_LVDS_100MHz */
59 .dot = {.min = 20000, .max = 115500},
60 .vco = {.min = 1800000, .max = 3600000},
61 .n = {.min = 2, .max = 6},
62 .m = {.min = 60, .max = 160},
63 .m1 = {.min = 0, .max = 0},
64 .m2 = {.min = 58, .max = 158},
65 .p = {.min = 28, .max = 140},
66 .p1 = {.min = 2, .max = 10},
67 /* The single-channel range is 25-112Mhz, and dual-channel
68 * is 80-224Mhz. Prefer single channel as much as possible.
69 */
70 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
2adb29ff 71 .find_pll = gma_find_best_pll,
6a227d5f
AC		 72 },
73 { /* CDV_DAC_HDMI_27MHz */
74 .dot = {.min = 20000, .max = 400000},
75 .vco = {.min = 1809000, .max = 3564000},
76 .n = {.min = 1, .max = 1},
77 .m = {.min = 67, .max = 132},
78 .m1 = {.min = 0, .max = 0},
79 .m2 = {.min = 65, .max = 130},
80 .p = {.min = 5, .max = 90},
81 .p1 = {.min = 1, .max = 9},
82 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
2adb29ff 83 .find_pll = gma_find_best_pll,
6a227d5f
AC		 84 },
85 { /* CDV_DAC_HDMI_96MHz */
86 .dot = {.min = 20000, .max = 400000},
87 .vco = {.min = 1800000, .max = 3600000},
88 .n = {.min = 2, .max = 6},
89 .m = {.min = 60, .max = 160},
90 .m1 = {.min = 0, .max = 0},
91 .m2 = {.min = 58, .max = 158},
92 .p = {.min = 5, .max = 100},
93 .p1 = {.min = 1, .max = 10},
94 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
2adb29ff 95 .find_pll = gma_find_best_pll,
6a227d5f 96 },
220801bd
AC		 97 { /* CDV_DP_27MHz */
98 .dot = {.min = 160000, .max = 272000},
99 .vco = {.min = 1809000, .max = 3564000},
100 .n = {.min = 1, .max = 1},
101 .m = {.min = 67, .max = 132},
102 .m1 = {.min = 0, .max = 0},
103 .m2 = {.min = 65, .max = 130},
104 .p = {.min = 5, .max = 90},
105 .p1 = {.min = 1, .max = 9},
106 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
107 .find_pll = cdv_intel_find_dp_pll,
108 },
109 { /* CDV_DP_100MHz */
110 .dot = {.min = 160000, .max = 272000},
111 .vco = {.min = 1800000, .max = 3600000},
112 .n = {.min = 2, .max = 6},
113 .m = {.min = 60, .max = 164},
114 .m1 = {.min = 0, .max = 0},
115 .m2 = {.min = 58, .max = 162},
116 .p = {.min = 5, .max = 100},
117 .p1 = {.min = 1, .max = 10},
118 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
119 .find_pll = cdv_intel_find_dp_pll,
120 }
6a227d5f
AC		 121};
122
123#define _wait_for(COND, MS, W) ({ \
124 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
125 int ret__ = 0; \
126 while (!(COND)) { \
127 if (time_after(jiffies, timeout__)) { \
128 ret__ = -ETIMEDOUT; \
129 break; \
130 } \
131 if (W && !in_dbg_master()) \
132 msleep(W); \
133 } \
134 ret__; \
135})
136
137#define wait_for(COND, MS) _wait_for(COND, MS, 1)
138
139
37e7b184 140int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
6a227d5f
AC		 141{
142 int ret;
143
144 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
145 if (ret) {
146 DRM_ERROR("timeout waiting for SB to idle before read\n");
147 return ret;
148 }
149
150 REG_WRITE(SB_ADDR, reg);
151 REG_WRITE(SB_PCKT,
152 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
153 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
154 SET_FIELD(0xf, SB_BYTE_ENABLE));
155
156 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
157 if (ret) {
158 DRM_ERROR("timeout waiting for SB to idle after read\n");
159 return ret;
160 }
161
162 *val = REG_READ(SB_DATA);
163
164 return 0;
165}
166
37e7b184 167int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
6a227d5f
AC		 168{
169 int ret;
170 static bool dpio_debug = true;
171 u32 temp;
172
173 if (dpio_debug) {
174 if (cdv_sb_read(dev, reg, &temp) == 0)
175 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
176 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
177 }
178
179 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
180 if (ret) {
181 DRM_ERROR("timeout waiting for SB to idle before write\n");
182 return ret;
183 }
184
185 REG_WRITE(SB_ADDR, reg);
186 REG_WRITE(SB_DATA, val);
187 REG_WRITE(SB_PCKT,
188 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
189 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
190 SET_FIELD(0xf, SB_BYTE_ENABLE));
191
192 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
193 if (ret) {
194 DRM_ERROR("timeout waiting for SB to idle after write\n");
195 return ret;
196 }
197
198 if (dpio_debug) {
199 if (cdv_sb_read(dev, reg, &temp) == 0)
200 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
201 }
202
203 return 0;
204}
205
206/* Reset the DPIO configuration register. The BIOS does this at every
207 * mode set.
208 */
37e7b184 209void cdv_sb_reset(struct drm_device *dev)
6a227d5f
AC		 210{
211
212 REG_WRITE(DPIO_CFG, 0);
213 REG_READ(DPIO_CFG);
214 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
215}
216
217/* Unlike most Intel display engines, on Cedarview the DPLL registers
218 * are behind this sideband bus. They must be programmed while the
219 * DPLL reference clock is on in the DPLL control register, but before
220 * the DPLL is enabled in the DPLL control register.
221 */
222static int
223cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
2adb29ff 224 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
6a227d5f 225{
213a8434 226 struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc);
6a227d5f
AC		 227 int pipe = psb_crtc->pipe;
228 u32 m, n_vco, p;
229 int ret = 0;
230 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
acd7ef92 231 int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
6a227d5f 232 u32 ref_value;
d235e64a 233 u32 lane_reg, lane_value;
6a227d5f
AC		 234
235 cdv_sb_reset(dev);
236
d235e64a
AC		 237 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
238
239 udelay(100);
6a227d5f
AC		 240
241 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
242 ref_value = 0x68A701;
243
244 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
245
246 /* We don't know what the other fields of these regs are, so
247 * leave them in place.
248 */
acd7ef92
AC		 249 /*
250 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
251 * for the pipe A/B. Display spec 1.06 has wrong definition.
252 * Correct definition is like below:
253 *
254 * refclka mean use clock from same PLL
255 *
256 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
257 *
258 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
259 *
260 */
261 ret = cdv_sb_read(dev, ref_sfr, &ref_value);
262 if (ret)
263 return ret;
264 ref_value &= ~(REF_CLK_MASK);
265
266 /* use DPLL_A for pipeB on CRT/HDMI */
220801bd 267 if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
acd7ef92
AC		 268 DRM_DEBUG_KMS("use DPLLA for pipe B\n");
269 ref_value |= REF_CLK_DPLLA;
270 } else {
271 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
272 ref_value |= REF_CLK_DPLL;
273 }
274 ret = cdv_sb_write(dev, ref_sfr, ref_value);
275 if (ret)
276 return ret;
277
6a227d5f
AC		 278 ret = cdv_sb_read(dev, SB_M(pipe), &m);
279 if (ret)
280 return ret;
281 m &= ~SB_M_DIVIDER_MASK;
282 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
283 ret = cdv_sb_write(dev, SB_M(pipe), m);
284 if (ret)
285 return ret;
286
287 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
288 if (ret)
289 return ret;
290
291 /* Follow the BIOS to program the N_DIVIDER REG */
292 n_vco &= 0xFFFF;
293 n_vco |= 0x107;
294 n_vco &= ~(SB_N_VCO_SEL_MASK |
295 SB_N_DIVIDER_MASK |
296 SB_N_CB_TUNE_MASK);
297
298 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
299
300 if (clock->vco < 2250000) {
301 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
302 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
303 } else if (clock->vco < 2750000) {
304 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
305 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
306 } else if (clock->vco < 3300000) {
307 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
308 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
309 } else {
310 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
311 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
312 }
313
314 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
315 if (ret)
316 return ret;
317
318 ret = cdv_sb_read(dev, SB_P(pipe), &p);
319 if (ret)
320 return ret;
321 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
322 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
323 switch (clock->p2) {
324 case 5:
325 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
326 break;
327 case 10:
328 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
329 break;
330 case 14:
331 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
332 break;
333 case 7:
334 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
335 break;
336 default:
337 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
338 return -EINVAL;
339 }
340 ret = cdv_sb_write(dev, SB_P(pipe), p);
341 if (ret)
342 return ret;
343
d6676096
ZY		 344 if (ddi_select) {
345 if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
346 lane_reg = PSB_LANE0;
347 cdv_sb_read(dev, lane_reg, &lane_value);
348 lane_value &= ~(LANE_PLL_MASK);
349 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
350 cdv_sb_write(dev, lane_reg, lane_value);
351
352 lane_reg = PSB_LANE1;
353 cdv_sb_read(dev, lane_reg, &lane_value);
354 lane_value &= ~(LANE_PLL_MASK);
355 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
356 cdv_sb_write(dev, lane_reg, lane_value);
357 } else {
358 lane_reg = PSB_LANE2;
359 cdv_sb_read(dev, lane_reg, &lane_value);
360 lane_value &= ~(LANE_PLL_MASK);
361 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
362 cdv_sb_write(dev, lane_reg, lane_value);
363
364 lane_reg = PSB_LANE3;
365 cdv_sb_read(dev, lane_reg, &lane_value);
366 lane_value &= ~(LANE_PLL_MASK);
367 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
368 cdv_sb_write(dev, lane_reg, lane_value);
369 }
370 }
6a227d5f
AC		 371 return 0;
372}
373
2adb29ff
PJ		 374static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
375 int refclk)
6a227d5f 376{
2adb29ff 377 const struct gma_limit_t *limit;
fe477cc1 378 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
6a227d5f
AC		 379 /*
380 * Now only single-channel LVDS is supported on CDV. If it is
381 * incorrect, please add the dual-channel LVDS.
382 */
383 if (refclk == 96000)
384 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
385 else
386 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
fe477cc1
PJ		 387 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
388 gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
220801bd
AC		 389 if (refclk == 27000)
390 limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
391 else
392 limit = &cdv_intel_limits[CDV_LIMIT_DP_100];
6a227d5f
AC		 393 } else {
394 if (refclk == 27000)
395 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
396 else
397 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
398 }
399 return limit;
400}
401
402/* m1 is reserved as 0 in CDV, n is a ring counter */
2adb29ff 403static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
6a227d5f
AC		 404{
405 clock->m = clock->m2 + 2;
406 clock->p = clock->p1 * clock->p2;
407 clock->vco = (refclk * clock->m) / clock->n;
408 clock->dot = clock->vco / clock->p;
409}
410
2adb29ff
PJ		 411static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
412 struct drm_crtc *crtc, int target,
413 int refclk,
414 struct gma_clock_t *best_clock)
6a227d5f 415{
2adb29ff 416 struct gma_clock_t clock;
220801bd
AC		 417 if (refclk == 27000) {
418 if (target < 200000) {
419 clock.p1 = 2;
420 clock.p2 = 10;
421 clock.n = 1;
422 clock.m1 = 0;
423 clock.m2 = 118;
424 } else {
425 clock.p1 = 1;
426 clock.p2 = 10;
427 clock.n = 1;
428 clock.m1 = 0;
429 clock.m2 = 98;
430 }
431 } else if (refclk == 100000) {
432 if (target < 200000) {
433 clock.p1 = 2;
434 clock.p2 = 10;
435 clock.n = 5;
436 clock.m1 = 0;
437 clock.m2 = 160;
438 } else {
439 clock.p1 = 1;
440 clock.p2 = 10;
441 clock.n = 5;
442 clock.m1 = 0;
443 clock.m2 = 133;
444 }
445 } else
446 return false;
447 clock.m = clock.m2 + 2;
448 clock.p = clock.p1 * clock.p2;
449 clock.vco = (refclk * clock.m) / clock.n;
450 clock.dot = clock.vco / clock.p;
2adb29ff 451 memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
220801bd
AC		 452 return true;
453}
454
acd7ef92
AC		 455#define FIFO_PIPEA (1 << 0)
456#define FIFO_PIPEB (1 << 1)
457
458static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
459{
460 struct drm_crtc *crtc;
461 struct drm_psb_private *dev_priv = dev->dev_private;
462 struct psb_intel_crtc *psb_intel_crtc = NULL;
463
464 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
465 psb_intel_crtc = to_psb_intel_crtc(crtc);
466
467 if (crtc->fb == NULL || !psb_intel_crtc->active)
468 return false;
469 return true;
470}
471
472static bool cdv_intel_single_pipe_active (struct drm_device *dev)
473{
474 uint32_t pipe_enabled = 0;
475
476 if (cdv_intel_pipe_enabled(dev, 0))
477 pipe_enabled |= FIFO_PIPEA;
478
479 if (cdv_intel_pipe_enabled(dev, 1))
480 pipe_enabled |= FIFO_PIPEB;
481
482
483 DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled);
484
485 if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB)
486 return true;
487 else
488 return false;
489}
490
491static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc)
492{
493 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
494 struct drm_mode_config *mode_config = &dev->mode_config;
495 struct drm_connector *connector;
496
497 if (psb_intel_crtc->pipe != 1)
498 return false;
499
500 list_for_each_entry(connector, &mode_config->connector_list, head) {
501 struct psb_intel_encoder *psb_intel_encoder =
502 psb_intel_attached_encoder(connector);
503
504 if (!connector->encoder
505 || connector->encoder->crtc != crtc)
506 continue;
507
508 if (psb_intel_encoder->type == INTEL_OUTPUT_LVDS)
509 return true;
510 }
511
512 return false;
513}
514
515static void cdv_intel_disable_self_refresh (struct drm_device *dev)
516{
517 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
518
519 /* Disable self-refresh before adjust WM */
520 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
521 REG_READ(FW_BLC_SELF);
522
ad3c46ea 523 gma_wait_for_vblank(dev);
acd7ef92
AC		 524
525 /* Cedarview workaround to write ovelay plane, which force to leave
526 * MAX_FIFO state.
527 */
528 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
529 REG_READ(OV_OVADD);
530
ad3c46ea 531 gma_wait_for_vblank(dev);
acd7ef92
AC		 532 }
533
534}
535
536static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc *crtc)
537{
538
539 if (cdv_intel_single_pipe_active(dev)) {
540 u32 fw;
541
542 fw = REG_READ(DSPFW1);
543 fw &= ~DSP_FIFO_SR_WM_MASK;
544 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
545 fw &= ~CURSOR_B_FIFO_WM_MASK;
546 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
547 REG_WRITE(DSPFW1, fw);
548
549 fw = REG_READ(DSPFW2);
550 fw &= ~CURSOR_A_FIFO_WM_MASK;
551 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
552 fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
553 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
554 REG_WRITE(DSPFW2, fw);
555
556 REG_WRITE(DSPFW3, 0x36000000);
557
558 /* ignore FW4 */
559
560 if (is_pipeb_lvds(dev, crtc)) {
561 REG_WRITE(DSPFW5, 0x00040330);
562 } else {
563 fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
564 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
565 (3 << CURSOR_B_FIFO_WM1_SHIFT) |
566 (4 << CURSOR_FIFO_SR_WM1_SHIFT);
567 REG_WRITE(DSPFW5, fw);
568 }
569
570 REG_WRITE(DSPFW6, 0x10);
571
ad3c46ea 572 gma_wait_for_vblank(dev);
acd7ef92
AC		 573
574 /* enable self-refresh for single pipe active */
575 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
576 REG_READ(FW_BLC_SELF);
ad3c46ea 577 gma_wait_for_vblank(dev);
acd7ef92
AC		 578
579 } else {
580
581 /* HW team suggested values... */
582 REG_WRITE(DSPFW1, 0x3f880808);
583 REG_WRITE(DSPFW2, 0x0b020202);
584 REG_WRITE(DSPFW3, 0x24000000);
585 REG_WRITE(DSPFW4, 0x08030202);
586 REG_WRITE(DSPFW5, 0x01010101);
587 REG_WRITE(DSPFW6, 0x1d0);
588
ad3c46ea 589 gma_wait_for_vblank(dev);
acd7ef92
AC		 590
591 cdv_intel_disable_self_refresh(dev);
592
593 }
594}
595
596/** Loads the palette/gamma unit for the CRTC with the prepared values */
597static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
598{
599 struct drm_device *dev = crtc->dev;
213a8434 600 struct drm_psb_private *dev_priv = dev->dev_private;
acd7ef92
AC		 601 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
602 int palreg = PALETTE_A;
603 int i;
604
605 /* The clocks have to be on to load the palette. */
606 if (!crtc->enabled)
607 return;
608
609 switch (psb_intel_crtc->pipe) {
610 case 0:
611 break;
612 case 1:
613 palreg = PALETTE_B;
614 break;
615 case 2:
616 palreg = PALETTE_C;
617 break;
618 default:
619 dev_err(dev->dev, "Illegal Pipe Number.\n");
620 return;
621 }
622
623 if (gma_power_begin(dev, false)) {
624 for (i = 0; i < 256; i++) {
625 REG_WRITE(palreg + 4 * i,
626 ((psb_intel_crtc->lut_r[i] +
627 psb_intel_crtc->lut_adj[i]) << 16) |
628 ((psb_intel_crtc->lut_g[i] +
629 psb_intel_crtc->lut_adj[i]) << 8) |
630 (psb_intel_crtc->lut_b[i] +
631 psb_intel_crtc->lut_adj[i]));
632 }
633 gma_power_end(dev);
634 } else {
635 for (i = 0; i < 256; i++) {
6256304b 636 dev_priv->regs.pipe[0].palette[i] =
acd7ef92
AC		 637 ((psb_intel_crtc->lut_r[i] +
638 psb_intel_crtc->lut_adj[i]) << 16) |
639 ((psb_intel_crtc->lut_g[i] +
640 psb_intel_crtc->lut_adj[i]) << 8) |
641 (psb_intel_crtc->lut_b[i] +
642 psb_intel_crtc->lut_adj[i]);
643 }
644
645 }
646}
647
6a227d5f
AC		 648/**
649 * Sets the power management mode of the pipe and plane.
650 *
651 * This code should probably grow support for turning the cursor off and back
652 * on appropriately at the same time as we're turning the pipe off/on.
653 */
654static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
655{
656 struct drm_device *dev = crtc->dev;
213a8434 657 struct drm_psb_private *dev_priv = dev->dev_private;
6a227d5f
AC		 658 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
659 int pipe = psb_intel_crtc->pipe;
213a8434 660 const struct psb_offset *map = &dev_priv->regmap[pipe];
6a227d5f 661 u32 temp;
6a227d5f
AC		 662
663 /* XXX: When our outputs are all unaware of DPMS modes other than off
664 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
665 */
acd7ef92
AC		 666 cdv_intel_disable_self_refresh(dev);
667
6a227d5f
AC		 668 switch (mode) {
669 case DRM_MODE_DPMS_ON:
670 case DRM_MODE_DPMS_STANDBY:
671 case DRM_MODE_DPMS_SUSPEND:
acd7ef92 672 if (psb_intel_crtc->active)
25e9dc69 673 break;
acd7ef92
AC		 674
675 psb_intel_crtc->active = true;
676
6a227d5f 677 /* Enable the DPLL */
213a8434 678 temp = REG_READ(map->dpll);
6a227d5f 679 if ((temp & DPLL_VCO_ENABLE) == 0) {
213a8434
AC		 680 REG_WRITE(map->dpll, temp);
681 REG_READ(map->dpll);
6a227d5f
AC		 682 /* Wait for the clocks to stabilize. */
683 udelay(150);
213a8434
AC		 684 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
685 REG_READ(map->dpll);
6a227d5f
AC		 686 /* Wait for the clocks to stabilize. */
687 udelay(150);
213a8434
AC		 688 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
689 REG_READ(map->dpll);
6a227d5f
AC		 690 /* Wait for the clocks to stabilize. */
691 udelay(150);
692 }
693
694 /* Jim Bish - switch plan and pipe per scott */
695 /* Enable the plane */
213a8434 696 temp = REG_READ(map->cntr);
6a227d5f 697 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
213a8434 698 REG_WRITE(map->cntr,
6a227d5f
AC		 699 temp | DISPLAY_PLANE_ENABLE);
700 /* Flush the plane changes */
213a8434 701 REG_WRITE(map->base, REG_READ(map->base));
6a227d5f
AC		 702 }
703
704 udelay(150);
705
706 /* Enable the pipe */
213a8434 707 temp = REG_READ(map->conf);
6a227d5f 708 if ((temp & PIPEACONF_ENABLE) == 0)
213a8434 709 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
6a227d5f 710
213a8434 711 temp = REG_READ(map->status);
acd7ef92
AC		 712 temp &= ~(0xFFFF);
713 temp |= PIPE_FIFO_UNDERRUN;
213a8434
AC		 714 REG_WRITE(map->status, temp);
715 REG_READ(map->status);
acd7ef92 716
acd7ef92 717 cdv_intel_crtc_load_lut(crtc);
6a227d5f
AC		 718
719 /* Give the overlay scaler a chance to enable
720 * if it's on this pipe */
721 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
722 break;
723 case DRM_MODE_DPMS_OFF:
acd7ef92 724 if (!psb_intel_crtc->active)
25e9dc69 725 break;
acd7ef92
AC		 726
727 psb_intel_crtc->active = false;
728
6a227d5f
AC		 729 /* Give the overlay scaler a chance to disable
730 * if it's on this pipe */
731 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
732
733 /* Disable the VGA plane that we never use */
734 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
735
736 /* Jim Bish - changed pipe/plane here as well. */
737
acd7ef92 738 drm_vblank_off(dev, pipe);
6a227d5f 739 /* Wait for vblank for the disable to take effect */
ad3c46ea 740 gma_wait_for_vblank(dev);
6a227d5f
AC		 741
742 /* Next, disable display pipes */
213a8434 743 temp = REG_READ(map->conf);
6a227d5f 744 if ((temp & PIPEACONF_ENABLE) != 0) {
213a8434
AC		 745 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
746 REG_READ(map->conf);
6a227d5f
AC		 747 }
748
749 /* Wait for vblank for the disable to take effect. */
ad3c46ea 750 gma_wait_for_vblank(dev);
6a227d5f
AC		 751
752 udelay(150);
753
754 /* Disable display plane */
213a8434 755 temp = REG_READ(map->cntr);
6a227d5f 756 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
213a8434 757 REG_WRITE(map->cntr,
6a227d5f
AC		 758 temp & ~DISPLAY_PLANE_ENABLE);
759 /* Flush the plane changes */
213a8434
AC		 760 REG_WRITE(map->base, REG_READ(map->base));
761 REG_READ(map->base);
6a227d5f
AC		 762 }
763
213a8434 764 temp = REG_READ(map->dpll);
6a227d5f 765 if ((temp & DPLL_VCO_ENABLE) != 0) {
213a8434
AC		 766 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
767 REG_READ(map->dpll);
6a227d5f
AC		 768 }
769
770 /* Wait for the clocks to turn off. */
771 udelay(150);
772 break;
773 }
25e9dc69 774 cdv_intel_update_watermark(dev, crtc);
6a227d5f
AC		 775 /*Set FIFO Watermarks*/
776 REG_WRITE(DSPARB, 0x3F3E);
777}
778
6a227d5f
AC		 779/**
780 * Return the pipe currently connected to the panel fitter,
781 * or -1 if the panel fitter is not present or not in use
782 */
783static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
784{
785 u32 pfit_control;
786
787 pfit_control = REG_READ(PFIT_CONTROL);
788
789 /* See if the panel fitter is in use */
790 if ((pfit_control & PFIT_ENABLE) == 0)
791 return -1;
792 return (pfit_control >> 29) & 0x3;
793}
794
795static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
796 struct drm_display_mode *mode,
797 struct drm_display_mode *adjusted_mode,
798 int x, int y,
799 struct drm_framebuffer *old_fb)
800{
801 struct drm_device *dev = crtc->dev;
acd7ef92 802 struct drm_psb_private *dev_priv = dev->dev_private;
6a227d5f
AC		 803 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
804 int pipe = psb_intel_crtc->pipe;
213a8434 805 const struct psb_offset *map = &dev_priv->regmap[pipe];
6a227d5f 806 int refclk;
2adb29ff 807 struct gma_clock_t clock;
6a227d5f 808 u32 dpll = 0, dspcntr, pipeconf;
0313c0de 809 bool ok;
6a227d5f 810 bool is_crt = false, is_lvds = false, is_tv = false;
220801bd 811 bool is_hdmi = false, is_dp = false;
6a227d5f
AC		 812 struct drm_mode_config *mode_config = &dev->mode_config;
813 struct drm_connector *connector;
2adb29ff 814 const struct gma_limit_t *limit;
d6676096 815 u32 ddi_select = 0;
d112a816 816 bool is_edp = false;
6a227d5f
AC		 817
818 list_for_each_entry(connector, &mode_config->connector_list, head) {
a12d6a07
PJ		 819 struct psb_intel_encoder *psb_intel_encoder =
820 psb_intel_attached_encoder(connector);
6a227d5f
AC		 821
822 if (!connector->encoder
823 || connector->encoder->crtc != crtc)
824 continue;
825
d6676096 826 ddi_select = psb_intel_encoder->ddi_select;
a12d6a07 827 switch (psb_intel_encoder->type) {
6a227d5f
AC		 828 case INTEL_OUTPUT_LVDS:
829 is_lvds = true;
830 break;
6a227d5f
AC		 831 case INTEL_OUTPUT_TVOUT:
832 is_tv = true;
833 break;
834 case INTEL_OUTPUT_ANALOG:
835 is_crt = true;
836 break;
837 case INTEL_OUTPUT_HDMI:
838 is_hdmi = true;
839 break;
220801bd
AC		 840 case INTEL_OUTPUT_DISPLAYPORT:
841 is_dp = true;
842 break;
d112a816
ZY		 843 case INTEL_OUTPUT_EDP:
844 is_edp = true;
845 break;
d6676096
ZY		 846 default:
847 DRM_ERROR("invalid output type.\n");
848 return 0;
6a227d5f
AC		 849 }
850 }
851
acd7ef92
AC		 852 if (dev_priv->dplla_96mhz)
853 /* low-end sku, 96/100 mhz */
854 refclk = 96000;
855 else
856 /* high-end sku, 27/100 mhz */
6a227d5f 857 refclk = 27000;
d112a816
ZY		 858 if (is_dp || is_edp) {
859 /*
860 * Based on the spec the low-end SKU has only CRT/LVDS. So it is
861 * unnecessary to consider it for DP/eDP.
862 * On the high-end SKU, it will use the 27/100M reference clk
863 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise
864 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose
865 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
866 */
220801bd
AC		 867 if (pipe == 0)
868 refclk = 27000;
869 else
870 refclk = 100000;
871 }
6a227d5f 872
acd7ef92
AC		 873 if (is_lvds && dev_priv->lvds_use_ssc) {
874 refclk = dev_priv->lvds_ssc_freq * 1000;
875 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
876 }
877
6a227d5f 878 drm_mode_debug_printmodeline(adjusted_mode);
d6676096 879
2adb29ff 880 limit = psb_intel_crtc->clock_funcs->limit(crtc, refclk);
6a227d5f 881
d6676096 882 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
6a227d5f
AC		 883 &clock);
884 if (!ok) {
2adb29ff
PJ		 885 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
886 adjusted_mode->clock, clock.dot);
6a227d5f
AC		 887 return 0;
888 }
889
890 dpll = DPLL_VGA_MODE_DIS;
891 if (is_tv) {
892 /* XXX: just matching BIOS for now */
893/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
894 dpll |= 3;
895 }
acd7ef92 896/* dpll |= PLL_REF_INPUT_DREFCLK; */
6a227d5f 897
f76c0dde
AC		 898 if (is_dp || is_edp) {
899 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode);
220801bd
AC		 900 } else {
901 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
902 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
903 REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
904 REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
905 }
906
6a227d5f 907 dpll |= DPLL_SYNCLOCK_ENABLE;
acd7ef92 908/* if (is_lvds)
6a227d5f
AC		 909 dpll |= DPLLB_MODE_LVDS;
910 else
acd7ef92 911 dpll |= DPLLB_MODE_DAC_SERIAL; */
6a227d5f
AC		 912 /* dpll |= (2 << 11); */
913
914 /* setup pipeconf */
213a8434 915 pipeconf = REG_READ(map->conf);
6a227d5f 916
d112a816
ZY		 917 pipeconf &= ~(PIPE_BPC_MASK);
918 if (is_edp) {
919 switch (dev_priv->edp.bpp) {
920 case 24:
921 pipeconf |= PIPE_8BPC;
922 break;
923 case 18:
924 pipeconf |= PIPE_6BPC;
925 break;
926 case 30:
927 pipeconf |= PIPE_10BPC;
928 break;
929 default:
930 pipeconf |= PIPE_8BPC;
931 break;
932 }
933 } else if (is_lvds) {
934 /* the BPC will be 6 if it is 18-bit LVDS panel */
935 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
936 pipeconf |= PIPE_8BPC;
937 else
938 pipeconf |= PIPE_6BPC;
939 } else
940 pipeconf |= PIPE_8BPC;
941
6a227d5f
AC		 942 /* Set up the display plane register */
943 dspcntr = DISPPLANE_GAMMA_ENABLE;
944
945 if (pipe == 0)
946 dspcntr |= DISPPLANE_SEL_PIPE_A;
947 else
948 dspcntr |= DISPPLANE_SEL_PIPE_B;
949
950 dspcntr |= DISPLAY_PLANE_ENABLE;
951 pipeconf |= PIPEACONF_ENABLE;
952
213a8434
AC		 953 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
954 REG_READ(map->dpll);
6a227d5f 955
d6676096 956 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
6a227d5f
AC		 957
958 udelay(150);
959
960
961 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
962 * This is an exception to the general rule that mode_set doesn't turn
963 * things on.
964 */
965 if (is_lvds) {
966 u32 lvds = REG_READ(LVDS);
967
968 lvds |=
969 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
970 LVDS_PIPEB_SELECT;
971 /* Set the B0-B3 data pairs corresponding to
972 * whether we're going to
973 * set the DPLLs for dual-channel mode or not.
974 */
975 if (clock.p2 == 7)
976 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
977 else
978 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
979
980 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
981 * appropriately here, but we need to look more
982 * thoroughly into how panels behave in the two modes.
983 */
984
985 REG_WRITE(LVDS, lvds);
986 REG_READ(LVDS);
987 }
988
989 dpll |= DPLL_VCO_ENABLE;
990
991 /* Disable the panel fitter if it was on our pipe */
992 if (cdv_intel_panel_fitter_pipe(dev) == pipe)
993 REG_WRITE(PFIT_CONTROL, 0);
994
995 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
996 drm_mode_debug_printmodeline(mode);
997
213a8434
AC		 998 REG_WRITE(map->dpll,
999 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
1000 REG_READ(map->dpll);
6a227d5f
AC		 1001 /* Wait for the clocks to stabilize. */
1002 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
1003
213a8434 1004 if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
6a227d5f
AC		 1005 dev_err(dev->dev, "Failed to get DPLL lock\n");
1006 return -EBUSY;
1007 }
1008
1009 {
1010 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
213a8434 1011 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
6a227d5f
AC		 1012 }
1013
213a8434 1014 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
6a227d5f 1015 ((adjusted_mode->crtc_htotal - 1) << 16));
213a8434 1016 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
6a227d5f 1017 ((adjusted_mode->crtc_hblank_end - 1) << 16));
213a8434 1018 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
6a227d5f 1019 ((adjusted_mode->crtc_hsync_end - 1) << 16));
213a8434 1020 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
6a227d5f 1021 ((adjusted_mode->crtc_vtotal - 1) << 16));
213a8434 1022 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
6a227d5f 1023 ((adjusted_mode->crtc_vblank_end - 1) << 16));
213a8434 1024 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
6a227d5f
AC		 1025 ((adjusted_mode->crtc_vsync_end - 1) << 16));
1026 /* pipesrc and dspsize control the size that is scaled from,
1027 * which should always be the user's requested size.
1028 */
213a8434 1029 REG_WRITE(map->size,
6a227d5f 1030 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
213a8434
AC		 1031 REG_WRITE(map->pos, 0);
1032 REG_WRITE(map->src,
6a227d5f 1033 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
213a8434
AC		 1034 REG_WRITE(map->conf, pipeconf);
1035 REG_READ(map->conf);
6a227d5f 1036
ad3c46ea 1037 gma_wait_for_vblank(dev);
6a227d5f 1038
213a8434 1039 REG_WRITE(map->cntr, dspcntr);
6a227d5f
AC		 1040
1041 /* Flush the plane changes */
1042 {
1043 struct drm_crtc_helper_funcs *crtc_funcs =
1044 crtc->helper_private;
1045 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
1046 }
1047
ad3c46ea 1048 gma_wait_for_vblank(dev);
6a227d5f
AC		 1049
1050 return 0;
1051}
1052
6a227d5f
AC		 1053
1054/**
1055 * Save HW states of giving crtc
1056 */
1057static void cdv_intel_crtc_save(struct drm_crtc *crtc)
1058{
1059 struct drm_device *dev = crtc->dev;
213a8434 1060 struct drm_psb_private *dev_priv = dev->dev_private;
6a227d5f
AC		 1061 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1062 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
213a8434 1063 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
6a227d5f
AC		 1064 uint32_t paletteReg;
1065 int i;
1066
1067 if (!crtc_state) {
1068 dev_dbg(dev->dev, "No CRTC state found\n");
1069 return;
1070 }
1071
213a8434
AC		 1072 crtc_state->saveDSPCNTR = REG_READ(map->cntr);
1073 crtc_state->savePIPECONF = REG_READ(map->conf);
1074 crtc_state->savePIPESRC = REG_READ(map->src);
1075 crtc_state->saveFP0 = REG_READ(map->fp0);
1076 crtc_state->saveFP1 = REG_READ(map->fp1);
1077 crtc_state->saveDPLL = REG_READ(map->dpll);
1078 crtc_state->saveHTOTAL = REG_READ(map->htotal);
1079 crtc_state->saveHBLANK = REG_READ(map->hblank);
1080 crtc_state->saveHSYNC = REG_READ(map->hsync);
1081 crtc_state->saveVTOTAL = REG_READ(map->vtotal);
1082 crtc_state->saveVBLANK = REG_READ(map->vblank);
1083 crtc_state->saveVSYNC = REG_READ(map->vsync);
1084 crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
6a227d5f
AC		 1085
1086 /*NOTE: DSPSIZE DSPPOS only for psb*/
213a8434
AC		 1087 crtc_state->saveDSPSIZE = REG_READ(map->size);
1088 crtc_state->saveDSPPOS = REG_READ(map->pos);
6a227d5f 1089
213a8434 1090 crtc_state->saveDSPBASE = REG_READ(map->base);
6a227d5f
AC		 1091
1092 DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1093 crtc_state->saveDSPCNTR,
1094 crtc_state->savePIPECONF,
1095 crtc_state->savePIPESRC,
1096 crtc_state->saveFP0,
1097 crtc_state->saveFP1,
1098 crtc_state->saveDPLL,
1099 crtc_state->saveHTOTAL,
1100 crtc_state->saveHBLANK,
1101 crtc_state->saveHSYNC,
1102 crtc_state->saveVTOTAL,
1103 crtc_state->saveVBLANK,
1104 crtc_state->saveVSYNC,
1105 crtc_state->saveDSPSTRIDE,
1106 crtc_state->saveDSPSIZE,
1107 crtc_state->saveDSPPOS,
1108 crtc_state->saveDSPBASE
1109 );
1110
213a8434 1111 paletteReg = map->palette;
6a227d5f
AC		 1112 for (i = 0; i < 256; ++i)
1113 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
1114}
1115
1116/**
1117 * Restore HW states of giving crtc
1118 */
1119static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
1120{
1121 struct drm_device *dev = crtc->dev;
213a8434 1122 struct drm_psb_private *dev_priv = dev->dev_private;
6a227d5f
AC		 1123 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1124 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
213a8434 1125 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
6a227d5f
AC		 1126 uint32_t paletteReg;
1127 int i;
1128
1129 if (!crtc_state) {
1130 dev_dbg(dev->dev, "No crtc state\n");
1131 return;
1132 }
1133
1134 DRM_DEBUG(
1135 "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
213a8434
AC		 1136 REG_READ(map->cntr),
1137 REG_READ(map->conf),
1138 REG_READ(map->src),
1139 REG_READ(map->fp0),
1140 REG_READ(map->fp1),
1141 REG_READ(map->dpll),
1142 REG_READ(map->htotal),
1143 REG_READ(map->hblank),
1144 REG_READ(map->hsync),
1145 REG_READ(map->vtotal),
1146 REG_READ(map->vblank),
1147 REG_READ(map->vsync),
1148 REG_READ(map->stride),
1149 REG_READ(map->size),
1150 REG_READ(map->pos),
1151 REG_READ(map->base)
1152 );
6a227d5f
AC		 1153
1154 DRM_DEBUG(
1155 "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1156 crtc_state->saveDSPCNTR,
1157 crtc_state->savePIPECONF,
1158 crtc_state->savePIPESRC,
1159 crtc_state->saveFP0,
1160 crtc_state->saveFP1,
1161 crtc_state->saveDPLL,
1162 crtc_state->saveHTOTAL,
1163 crtc_state->saveHBLANK,
1164 crtc_state->saveHSYNC,
1165 crtc_state->saveVTOTAL,
1166 crtc_state->saveVBLANK,
1167 crtc_state->saveVSYNC,
1168 crtc_state->saveDSPSTRIDE,
1169 crtc_state->saveDSPSIZE,
1170 crtc_state->saveDSPPOS,
1171 crtc_state->saveDSPBASE
213a8434 1172 );
6a227d5f
AC		 1173
1174
1175 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
213a8434
AC		 1176 REG_WRITE(map->dpll,
1177 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
1178 REG_READ(map->dpll);
6a227d5f 1179 DRM_DEBUG("write dpll: %x\n",
213a8434 1180 REG_READ(map->dpll));
6a227d5f
AC		 1181 udelay(150);
1182 }
1183
213a8434
AC		 1184 REG_WRITE(map->fp0, crtc_state->saveFP0);
1185 REG_READ(map->fp0);
6a227d5f 1186
213a8434
AC		 1187 REG_WRITE(map->fp1, crtc_state->saveFP1);
1188 REG_READ(map->fp1);
6a227d5f 1189
213a8434
AC		 1190 REG_WRITE(map->dpll, crtc_state->saveDPLL);
1191 REG_READ(map->dpll);
6a227d5f
AC		 1192 udelay(150);
1193
213a8434
AC		 1194 REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
1195 REG_WRITE(map->hblank, crtc_state->saveHBLANK);
1196 REG_WRITE(map->hsync, crtc_state->saveHSYNC);
1197 REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
1198 REG_WRITE(map->vblank, crtc_state->saveVBLANK);
1199 REG_WRITE(map->vsync, crtc_state->saveVSYNC);
1200 REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
6a227d5f 1201
213a8434
AC		 1202 REG_WRITE(map->size, crtc_state->saveDSPSIZE);
1203 REG_WRITE(map->pos, crtc_state->saveDSPPOS);
6a227d5f 1204
213a8434
AC		 1205 REG_WRITE(map->src, crtc_state->savePIPESRC);
1206 REG_WRITE(map->base, crtc_state->saveDSPBASE);
1207 REG_WRITE(map->conf, crtc_state->savePIPECONF);
6a227d5f 1208
ad3c46ea 1209 gma_wait_for_vblank(dev);
6a227d5f 1210
213a8434
AC		 1211 REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
1212 REG_WRITE(map->base, crtc_state->saveDSPBASE);
6a227d5f 1213
ad3c46ea 1214 gma_wait_for_vblank(dev);
6a227d5f 1215
213a8434 1216 paletteReg = map->palette;
6a227d5f
AC		 1217 for (i = 0; i < 256; ++i)
1218 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
1219}
1220
1221static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
1222 struct drm_file *file_priv,
1223 uint32_t handle,
1224 uint32_t width, uint32_t height)
1225{
1226 struct drm_device *dev = crtc->dev;
1227 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1228 int pipe = psb_intel_crtc->pipe;
1229 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1230 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1231 uint32_t temp;
1232 size_t addr = 0;
1233 struct gtt_range *gt;
1234 struct drm_gem_object *obj;
70b1304e 1235 int ret = 0;
6a227d5f
AC		 1236
1237 /* if we want to turn of the cursor ignore width and height */
1238 if (!handle) {
1239 /* turn off the cursor */
1240 temp = CURSOR_MODE_DISABLE;
1241
1242 if (gma_power_begin(dev, false)) {
1243 REG_WRITE(control, temp);
1244 REG_WRITE(base, 0);
1245 gma_power_end(dev);
1246 }
1247
1248 /* unpin the old GEM object */
1249 if (psb_intel_crtc->cursor_obj) {
1250 gt = container_of(psb_intel_crtc->cursor_obj,
1251 struct gtt_range, gem);
1252 psb_gtt_unpin(gt);
1253 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1254 psb_intel_crtc->cursor_obj = NULL;
1255 }
1256
1257 return 0;
1258 }
1259
1260 /* Currently we only support 64x64 cursors */
1261 if (width != 64 || height != 64) {
1262 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
1263 return -EINVAL;
1264 }
1265
1266 obj = drm_gem_object_lookup(dev, file_priv, handle);
1267 if (!obj)
1268 return -ENOENT;
1269
1270 if (obj->size < width * height * 4) {
1271 dev_dbg(dev->dev, "buffer is to small\n");
70b1304e
PJ		 1272 ret = -ENOMEM;
1273 goto unref_cursor;
6a227d5f
AC		 1274 }
1275
1276 gt = container_of(obj, struct gtt_range, gem);
1277
1278 /* Pin the memory into the GTT */
1279 ret = psb_gtt_pin(gt);
1280 if (ret) {
1281 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
70b1304e 1282 goto unref_cursor;
6a227d5f
AC		 1283 }
1284
1285 addr = gt->offset; /* Or resource.start ??? */
1286
1287 psb_intel_crtc->cursor_addr = addr;
1288
1289 temp = 0;
1290 /* set the pipe for the cursor */
1291 temp |= (pipe << 28);
1292 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1293
1294 if (gma_power_begin(dev, false)) {
1295 REG_WRITE(control, temp);
1296 REG_WRITE(base, addr);
1297 gma_power_end(dev);
1298 }
1299
1300 /* unpin the old GEM object */
1301 if (psb_intel_crtc->cursor_obj) {
1302 gt = container_of(psb_intel_crtc->cursor_obj,
1303 struct gtt_range, gem);
1304 psb_gtt_unpin(gt);
1305 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
6a227d5f 1306 }
70b1304e
PJ		 1307
1308 psb_intel_crtc->cursor_obj = obj;
1309 return ret;
1310
1311unref_cursor:
1312 drm_gem_object_unreference(obj);
1313 return ret;
6a227d5f
AC		 1314}
1315
1316static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1317{
1318 struct drm_device *dev = crtc->dev;
1319 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1320 int pipe = psb_intel_crtc->pipe;
1321 uint32_t temp = 0;
1322 uint32_t adder;
1323
1324
1325 if (x < 0) {
1326 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1327 x = -x;
1328 }
1329 if (y < 0) {
1330 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1331 y = -y;
1332 }
1333
1334 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1335 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1336
1337 adder = psb_intel_crtc->cursor_addr;
1338
1339 if (gma_power_begin(dev, false)) {
1340 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1341 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1342 gma_power_end(dev);
1343 }
1344 return 0;
1345}
1346
1347static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
1348 u16 *green, u16 *blue, uint32_t start, uint32_t size)
1349{
1350 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1351 int i;
1352 int end = (start + size > 256) ? 256 : start + size;
1353
1354 for (i = start; i < end; i++) {
1355 psb_intel_crtc->lut_r[i] = red[i] >> 8;
1356 psb_intel_crtc->lut_g[i] = green[i] >> 8;
1357 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
1358 }
1359
1360 cdv_intel_crtc_load_lut(crtc);
1361}
1362
1363static int cdv_crtc_set_config(struct drm_mode_set *set)
1364{
1365 int ret = 0;
1366 struct drm_device *dev = set->crtc->dev;
1367 struct drm_psb_private *dev_priv = dev->dev_private;
1368
1369 if (!dev_priv->rpm_enabled)
1370 return drm_crtc_helper_set_config(set);
1371
1372 pm_runtime_forbid(&dev->pdev->dev);
1373
1374 ret = drm_crtc_helper_set_config(set);
1375
1376 pm_runtime_allow(&dev->pdev->dev);
1377
1378 return ret;
1379}
1380
1381/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
1382
1383/* FIXME: why are we using this, should it be cdv_ in this tree ? */
1384
2adb29ff 1385static void i8xx_clock(int refclk, struct gma_clock_t *clock)
6a227d5f
AC		 1386{
1387 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
1388 clock->p = clock->p1 * clock->p2;
1389 clock->vco = refclk * clock->m / (clock->n + 2);
1390 clock->dot = clock->vco / clock->p;
1391}
1392
1393/* Returns the clock of the currently programmed mode of the given pipe. */
1394static int cdv_intel_crtc_clock_get(struct drm_device *dev,
1395 struct drm_crtc *crtc)
1396{
213a8434 1397 struct drm_psb_private *dev_priv = dev->dev_private;
6a227d5f
AC		 1398 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1399 int pipe = psb_intel_crtc->pipe;
213a8434 1400 const struct psb_offset *map = &dev_priv->regmap[pipe];
6a227d5f
AC		 1401 u32 dpll;
1402 u32 fp;
2adb29ff 1403 struct gma_clock_t clock;
6a227d5f 1404 bool is_lvds;
6256304b 1405 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
6a227d5f
AC		 1406
1407 if (gma_power_begin(dev, false)) {
213a8434 1408 dpll = REG_READ(map->dpll);
6a227d5f 1409 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
213a8434 1410 fp = REG_READ(map->fp0);
6a227d5f 1411 else
213a8434 1412 fp = REG_READ(map->fp1);
6a227d5f
AC		 1413 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1414 gma_power_end(dev);
1415 } else {
6256304b 1416 dpll = p->dpll;
6a227d5f 1417 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6256304b 1418 fp = p->fp0;
6a227d5f 1419 else
6256304b 1420 fp = p->fp1;
6a227d5f 1421
648a8e34 1422 is_lvds = (pipe == 1) &&
c6265ff5 1423 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
6a227d5f
AC		 1424 }
1425
1426 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1427 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1428 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1429
1430 if (is_lvds) {
1431 clock.p1 =
1432 ffs((dpll &
1433 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1434 DPLL_FPA01_P1_POST_DIV_SHIFT);
1435 if (clock.p1 == 0) {
1436 clock.p1 = 4;
1437 dev_err(dev->dev, "PLL %d\n", dpll);
1438 }
1439 clock.p2 = 14;
1440
1441 if ((dpll & PLL_REF_INPUT_MASK) ==
1442 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1443 /* XXX: might not be 66MHz */
1444 i8xx_clock(66000, &clock);
1445 } else
1446 i8xx_clock(48000, &clock);
1447 } else {
1448 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1449 clock.p1 = 2;
1450 else {
1451 clock.p1 =
1452 ((dpll &
1453 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1454 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1455 }
1456 if (dpll & PLL_P2_DIVIDE_BY_4)
1457 clock.p2 = 4;
1458 else
1459 clock.p2 = 2;
1460
1461 i8xx_clock(48000, &clock);
1462 }
1463
1464 /* XXX: It would be nice to validate the clocks, but we can't reuse
1465 * i830PllIsValid() because it relies on the xf86_config connector
1466 * configuration being accurate, which it isn't necessarily.
1467 */
1468
1469 return clock.dot;
1470}
1471
1472/** Returns the currently programmed mode of the given pipe. */
1473struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
1474 struct drm_crtc *crtc)
1475{
1476 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1477 int pipe = psb_intel_crtc->pipe;
213a8434
AC		 1478 struct drm_psb_private *dev_priv = dev->dev_private;
1479 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1480 const struct psb_offset *map = &dev_priv->regmap[pipe];
6a227d5f
AC		 1481 struct drm_display_mode *mode;
1482 int htot;
1483 int hsync;
1484 int vtot;
1485 int vsync;
6a227d5f
AC		 1486
1487 if (gma_power_begin(dev, false)) {
213a8434
AC		 1488 htot = REG_READ(map->htotal);
1489 hsync = REG_READ(map->hsync);
1490 vtot = REG_READ(map->vtotal);
1491 vsync = REG_READ(map->vsync);
6a227d5f
AC		 1492 gma_power_end(dev);
1493 } else {
6256304b
AC		 1494 htot = p->htotal;
1495 hsync = p->hsync;
1496 vtot = p->vtotal;
1497 vsync = p->vsync;
6a227d5f
AC		 1498 }
1499
1500 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1501 if (!mode)
1502 return NULL;
1503
1504 mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
1505 mode->hdisplay = (htot & 0xffff) + 1;
1506 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1507 mode->hsync_start = (hsync & 0xffff) + 1;
1508 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1509 mode->vdisplay = (vtot & 0xffff) + 1;
1510 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1511 mode->vsync_start = (vsync & 0xffff) + 1;
1512 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1513
1514 drm_mode_set_name(mode);
1515 drm_mode_set_crtcinfo(mode, 0);
1516
1517 return mode;
1518}
1519
6a227d5f
AC		 1520const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
1521 .dpms = cdv_intel_crtc_dpms,
ad3c46ea 1522 .mode_fixup = gma_crtc_mode_fixup,
6a227d5f 1523 .mode_set = cdv_intel_crtc_mode_set,
3c447166 1524 .mode_set_base = gma_pipe_set_base,
ad3c46ea
PJ		 1525 .prepare = gma_crtc_prepare,
1526 .commit = gma_crtc_commit,
1527 .disable = gma_crtc_disable,
6a227d5f
AC		 1528};
1529
1530const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
1531 .save = cdv_intel_crtc_save,
1532 .restore = cdv_intel_crtc_restore,
1533 .cursor_set = cdv_intel_crtc_cursor_set,
1534 .cursor_move = cdv_intel_crtc_cursor_move,
1535 .gamma_set = cdv_intel_crtc_gamma_set,
1536 .set_config = cdv_crtc_set_config,
ad3c46ea 1537 .destroy = gma_crtc_destroy,
6a227d5f 1538};
2adb29ff
PJ		 1539
1540const struct gma_clock_funcs cdv_clock_funcs = {
1541 .clock = cdv_intel_clock,
1542 .limit = cdv_intel_limit,
1543 .pll_is_valid = gma_pll_is_valid,
1544};
Linux kernel - Deliverables
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