[deliverable/linux.git] / drivers / gpu / drm / gma500 / oaktrail_device.c

/**************************************************************************
 * Copyright (c) 2011, Intel Corporation.
 * All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 **************************************************************************/

#include <linux/backlight.h>
#include <linux/module.h>
#include <linux/dmi.h>
#include <drm/drmP.h>
#include <drm/drm.h>
#include <drm/gma_drm.h>
#include "psb_drv.h"
#include "psb_reg.h"
#include "psb_intel_reg.h"
#include <asm/intel-mid.h>
#include <asm/intel_scu_ipc.h>
#include "mid_bios.h"
#include "intel_bios.h"

static int oaktrail_output_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	if (dev_priv->iLVDS_enable)
		oaktrail_lvds_init(dev, &dev_priv->mode_dev);
	else
		dev_err(dev->dev, "DSI is not supported\n");
	if (dev_priv->hdmi_priv)
		oaktrail_hdmi_init(dev, &dev_priv->mode_dev);

	psb_intel_sdvo_init(dev, SDVOB);

	return 0;
}

/*
 *	Provide the low level interfaces for the Moorestown backlight
 */

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE

#define MRST_BLC_MAX_PWM_REG_FREQ	    0xFFFF
#define BLC_PWM_PRECISION_FACTOR 100	/* 10000000 */
#define BLC_PWM_FREQ_CALC_CONSTANT 32
#define MHz 1000000
#define BLC_ADJUSTMENT_MAX 100

static struct backlight_device *oaktrail_backlight_device;
static int oaktrail_brightness;

static int oaktrail_set_brightness(struct backlight_device *bd)
{
	struct drm_device *dev = bl_get_data(oaktrail_backlight_device);
	struct drm_psb_private *dev_priv = dev->dev_private;
	int level = bd->props.brightness;
	u32 blc_pwm_ctl;
	u32 max_pwm_blc;

	/* Percentage 1-100% being valid */
	if (level < 1)
		level = 1;

	if (gma_power_begin(dev, 0)) {
		/* Calculate and set the brightness value */
		max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
		blc_pwm_ctl = level * max_pwm_blc / 100;

		/* Adjust the backlight level with the percent in
		 * dev_priv->blc_adj1;
		 */
		blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
		blc_pwm_ctl = blc_pwm_ctl / 100;

		/* Adjust the backlight level with the percent in
		 * dev_priv->blc_adj2;
		 */
		blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
		blc_pwm_ctl = blc_pwm_ctl / 100;

		/* force PWM bit on */
		REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
		REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
		gma_power_end(dev);
	}
	oaktrail_brightness = level;
	return 0;
}

static int oaktrail_get_brightness(struct backlight_device *bd)
{
	/* return locally cached var instead of HW read (due to DPST etc.) */
	/* FIXME: ideally return actual value in case firmware fiddled with
	   it */
	return oaktrail_brightness;
}

static int device_backlight_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	unsigned long core_clock;
	u16 bl_max_freq;
	uint32_t value;
	uint32_t blc_pwm_precision_factor;

	dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
	dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
	bl_max_freq = 256;
	/* this needs to be set elsewhere */
	blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;

	core_clock = dev_priv->core_freq;

	value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
	value *= blc_pwm_precision_factor;
	value /= bl_max_freq;
	value /= blc_pwm_precision_factor;

	if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
			return -ERANGE;

	if (gma_power_begin(dev, false)) {
		REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
		REG_WRITE(BLC_PWM_CTL, value | (value << 16));
		gma_power_end(dev);
	}
	return 0;
}

static const struct backlight_ops oaktrail_ops = {
	.get_brightness = oaktrail_get_brightness,
	.update_status  = oaktrail_set_brightness,
};

static int oaktrail_backlight_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	int ret;
	struct backlight_properties props;

	memset(&props, 0, sizeof(struct backlight_properties));
	props.max_brightness = 100;
	props.type = BACKLIGHT_PLATFORM;

	oaktrail_backlight_device = backlight_device_register("oaktrail-bl",
				NULL, (void *)dev, &oaktrail_ops, &props);

	if (IS_ERR(oaktrail_backlight_device))
		return PTR_ERR(oaktrail_backlight_device);

	ret = device_backlight_init(dev);
	if (ret < 0) {
		backlight_device_unregister(oaktrail_backlight_device);
		return ret;
	}
	oaktrail_backlight_device->props.brightness = 100;
	oaktrail_backlight_device->props.max_brightness = 100;
	backlight_update_status(oaktrail_backlight_device);
	dev_priv->backlight_device = oaktrail_backlight_device;
	return 0;
}

#endif

/*
 *	Provide the Moorestown specific chip logic and low level methods
 *	for power management
 */

/**
 *	oaktrail_save_display_registers	-	save registers lost on suspend
 *	@dev: our DRM device
 *
 *	Save the state we need in order to be able to restore the interface
 *	upon resume from suspend
 */
static int oaktrail_save_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct psb_save_area *regs = &dev_priv->regs;
	struct psb_pipe *p = &regs->pipe[0];
	int i;
	u32 pp_stat;

	/* Display arbitration control + watermarks */
	regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
	regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
	regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
	regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
	regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
	regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
	regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
	regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);

	/* Pipe & plane A info */
	p->conf = PSB_RVDC32(PIPEACONF);
	p->src = PSB_RVDC32(PIPEASRC);
	p->fp0 = PSB_RVDC32(MRST_FPA0);
	p->fp1 = PSB_RVDC32(MRST_FPA1);
	p->dpll = PSB_RVDC32(MRST_DPLL_A);
	p->htotal = PSB_RVDC32(HTOTAL_A);
	p->hblank = PSB_RVDC32(HBLANK_A);
	p->hsync = PSB_RVDC32(HSYNC_A);
	p->vtotal = PSB_RVDC32(VTOTAL_A);
	p->vblank = PSB_RVDC32(VBLANK_A);
	p->vsync = PSB_RVDC32(VSYNC_A);
	regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
	p->cntr = PSB_RVDC32(DSPACNTR);
	p->stride = PSB_RVDC32(DSPASTRIDE);
	p->addr = PSB_RVDC32(DSPABASE);
	p->surf = PSB_RVDC32(DSPASURF);
	p->linoff = PSB_RVDC32(DSPALINOFF);
	p->tileoff = PSB_RVDC32(DSPATILEOFF);

	/* Save cursor regs */
	regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
	regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
	regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);

	/* Save palette (gamma) */
	for (i = 0; i < 256; i++)
		p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));

	if (dev_priv->hdmi_priv)
		oaktrail_hdmi_save(dev);

	/* Save performance state */
	regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);

	/* LVDS state */
	regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
	regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
	regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
	regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
	regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
	regs->psb.saveLVDS = PSB_RVDC32(LVDS);
	regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
	regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
	regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
	regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);

	/* HW overlay */
	regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
	regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
	regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
	regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
	regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
	regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
	regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);

	/* DPST registers */
	regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
					PSB_RVDC32(HISTOGRAM_INT_CONTROL);
	regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
					PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
	regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);

	if (dev_priv->iLVDS_enable) {
		/* Shut down the panel */
		PSB_WVDC32(0, PP_CONTROL);

		do {
			pp_stat = PSB_RVDC32(PP_STATUS);
		} while (pp_stat & 0x80000000);

		/* Turn off the plane */
		PSB_WVDC32(0x58000000, DSPACNTR);
		/* Trigger the plane disable */
		PSB_WVDC32(0, DSPASURF);

		/* Wait ~4 ticks */
		msleep(4);

		/* Turn off pipe */
		PSB_WVDC32(0x0, PIPEACONF);
		/* Wait ~8 ticks */
		msleep(8);

		/* Turn off PLLs */
		PSB_WVDC32(0, MRST_DPLL_A);
	}
	return 0;
}

/**
 *	oaktrail_restore_display_registers	-	restore lost register state
 *	@dev: our DRM device
 *
 *	Restore register state that was lost during suspend and resume.
 */
static int oaktrail_restore_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct psb_save_area *regs = &dev_priv->regs;
	struct psb_pipe *p = &regs->pipe[0];
	u32 pp_stat;
	int i;

	/* Display arbitration + watermarks */
	PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
	PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
	PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
	PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
	PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
	PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
	PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
	PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);

	/* Make sure VGA plane is off. it initializes to on after reset!*/
	PSB_WVDC32(0x80000000, VGACNTRL);

	/* set the plls */
	PSB_WVDC32(p->fp0, MRST_FPA0);
	PSB_WVDC32(p->fp1, MRST_FPA1);

	/* Actually enable it */
	PSB_WVDC32(p->dpll, MRST_DPLL_A);
	DRM_UDELAY(150);

	/* Restore mode */
	PSB_WVDC32(p->htotal, HTOTAL_A);
	PSB_WVDC32(p->hblank, HBLANK_A);
	PSB_WVDC32(p->hsync, HSYNC_A);
	PSB_WVDC32(p->vtotal, VTOTAL_A);
	PSB_WVDC32(p->vblank, VBLANK_A);
	PSB_WVDC32(p->vsync, VSYNC_A);
	PSB_WVDC32(p->src, PIPEASRC);
	PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);

	/* Restore performance mode*/
	PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);

	/* Enable the pipe*/
	if (dev_priv->iLVDS_enable)
		PSB_WVDC32(p->conf, PIPEACONF);

	/* Set up the plane*/
	PSB_WVDC32(p->linoff, DSPALINOFF);
	PSB_WVDC32(p->stride, DSPASTRIDE);
	PSB_WVDC32(p->tileoff, DSPATILEOFF);

	/* Enable the plane */
	PSB_WVDC32(p->cntr, DSPACNTR);
	PSB_WVDC32(p->surf, DSPASURF);

	/* Enable Cursor A */
	PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
	PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
	PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);

	/* Restore palette (gamma) */
	for (i = 0; i < 256; i++)
		PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));

	if (dev_priv->hdmi_priv)
		oaktrail_hdmi_restore(dev);

	if (dev_priv->iLVDS_enable) {
		PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
		PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/
		PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
		PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
		PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
		PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
		PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
		PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
		PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
		PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
	}

	/* Wait for cycle delay */
	do {
		pp_stat = PSB_RVDC32(PP_STATUS);
	} while (pp_stat & 0x08000000);

	/* Wait for panel power up */
	do {
		pp_stat = PSB_RVDC32(PP_STATUS);
	} while (pp_stat & 0x10000000);

	/* Restore HW overlay */
	PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
	PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
	PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
	PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
	PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
	PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
	PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);

	/* DPST registers */
	PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
						HISTOGRAM_INT_CONTROL);
	PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
						HISTOGRAM_LOGIC_CONTROL);
	PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);

	return 0;
}

/**
 *	oaktrail_power_down	-	power down the display island
 *	@dev: our DRM device
 *
 *	Power down the display interface of our device
 */
static int oaktrail_power_down(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	u32 pwr_mask ;
	u32 pwr_sts;

	pwr_mask = PSB_PWRGT_DISPLAY_MASK;
	outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);

	while (true) {
		pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
		if ((pwr_sts & pwr_mask) == pwr_mask)
			break;
		else
			udelay(10);
	}
	return 0;
}

/*
 * oaktrail_power_up
 *
 * Restore power to the specified island(s) (powergating)
 */
static int oaktrail_power_up(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
	u32 pwr_sts, pwr_cnt;

	pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
	pwr_cnt &= ~pwr_mask;
	outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));

	while (true) {
		pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
		if ((pwr_sts & pwr_mask) == 0)
			break;
		else
			udelay(10);
	}
	return 0;
}

/* Oaktrail */
static const struct psb_offset oaktrail_regmap[2] = {
	{
		.fp0 = MRST_FPA0,
		.fp1 = MRST_FPA1,
		.cntr = DSPACNTR,
		.conf = PIPEACONF,
		.src = PIPEASRC,
		.dpll = MRST_DPLL_A,
		.htotal = HTOTAL_A,
		.hblank = HBLANK_A,
		.hsync = HSYNC_A,
		.vtotal = VTOTAL_A,
		.vblank = VBLANK_A,
		.vsync = VSYNC_A,
		.stride = DSPASTRIDE,
		.size = DSPASIZE,
		.pos = DSPAPOS,
		.surf = DSPASURF,
		.addr = MRST_DSPABASE,
		.base = MRST_DSPABASE,
		.status = PIPEASTAT,
		.linoff = DSPALINOFF,
		.tileoff = DSPATILEOFF,
		.palette = PALETTE_A,
	},
	{
		.fp0 = FPB0,
		.fp1 = FPB1,
		.cntr = DSPBCNTR,
		.conf = PIPEBCONF,
		.src = PIPEBSRC,
		.dpll = DPLL_B,
		.htotal = HTOTAL_B,
		.hblank = HBLANK_B,
		.hsync = HSYNC_B,
		.vtotal = VTOTAL_B,
		.vblank = VBLANK_B,
		.vsync = VSYNC_B,
		.stride = DSPBSTRIDE,
		.size = DSPBSIZE,
		.pos = DSPBPOS,
		.surf = DSPBSURF,
		.addr = DSPBBASE,
		.base = DSPBBASE,
		.status = PIPEBSTAT,
		.linoff = DSPBLINOFF,
		.tileoff = DSPBTILEOFF,
		.palette = PALETTE_B,
	},
};

static int oaktrail_chip_setup(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	int ret;
	
	if (pci_enable_msi(dev->pdev))
		dev_warn(dev->dev, "Enabling MSI failed!\n");

	dev_priv->regmap = oaktrail_regmap;

	ret = mid_chip_setup(dev);
	if (ret < 0)
		return ret;
	if (!dev_priv->has_gct) {
		/* Now pull the BIOS data */
		psb_intel_opregion_init(dev);
		psb_intel_init_bios(dev);
	}
	gma_intel_setup_gmbus(dev);
	oaktrail_hdmi_setup(dev);
	return 0;
}

static void oaktrail_teardown(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;

	gma_intel_teardown_gmbus(dev);
	oaktrail_hdmi_teardown(dev);
	if (!dev_priv->has_gct)
		psb_intel_destroy_bios(dev);
}

const struct psb_ops oaktrail_chip_ops = {
	.name = "Oaktrail",
	.accel_2d = 1,
	.pipes = 2,
	.crtcs = 2,
	.hdmi_mask = (1 << 1),
	.lvds_mask = (1 << 0),
	.sdvo_mask = (1 << 1),
	.cursor_needs_phys = 0,
	.sgx_offset = MRST_SGX_OFFSET,

	.chip_setup = oaktrail_chip_setup,
	.chip_teardown = oaktrail_teardown,
	.crtc_helper = &oaktrail_helper_funcs,
	.crtc_funcs = &psb_intel_crtc_funcs,

	.output_init = oaktrail_output_init,

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	.backlight_init = oaktrail_backlight_init,
#endif

	.save_regs = oaktrail_save_display_registers,
	.restore_regs = oaktrail_restore_display_registers,
	.save_crtc = gma_crtc_save,
	.restore_crtc = gma_crtc_restore,
	.power_down = oaktrail_power_down,
	.power_up = oaktrail_power_up,

	.i2c_bus = 1,
};
Commit	Line	Data
1b082ccf AC	1	/**************************************************************************
	2	* Copyright (c) 2011, Intel Corporation.
	3	* All Rights Reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	17	*
	18	**************************************************************************/
	19
	20	#include <linux/backlight.h>
	21	#include <linux/module.h>
	22	#include <linux/dmi.h>
	23	#include <drm/drmP.h>
	24	#include <drm/drm.h>
760285e7	25	#include <drm/gma_drm.h>
1b082ccf AC	26	#include "psb_drv.h"
	27	#include "psb_reg.h"
	28	#include "psb_intel_reg.h"
05454c26	29	#include <asm/intel-mid.h>
1b082ccf AC	30	#include <asm/intel_scu_ipc.h>
1b082ccf AC	31	#include "mid_bios.h"
aa0c45fd	32	#include "intel_bios.h"
1b082ccf AC	33
	34	static int oaktrail_output_init(struct drm_device *dev)
	35	{
	36	struct drm_psb_private *dev_priv = dev->dev_private;
	37	if (dev_priv->iLVDS_enable)
	38	oaktrail_lvds_init(dev, &dev_priv->mode_dev);
	39	else
	40	dev_err(dev->dev, "DSI is not supported\n");
	41	if (dev_priv->hdmi_priv)
	42	oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
cd3fdbe8 PJ	43
	44	psb_intel_sdvo_init(dev, SDVOB);
	45
1b082ccf AC	46	return 0;
	47	}
	48
	49	/*
	50	* Provide the low level interfaces for the Moorestown backlight
	51	*/
	52
	53	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	54
	55	#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
	56	#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
	57	#define BLC_PWM_FREQ_CALC_CONSTANT 32
	58	#define MHz 1000000
	59	#define BLC_ADJUSTMENT_MAX 100
	60
	61	static struct backlight_device *oaktrail_backlight_device;
	62	static int oaktrail_brightness;
	63
	64	static int oaktrail_set_brightness(struct backlight_device *bd)
	65	{
	66	struct drm_device *dev = bl_get_data(oaktrail_backlight_device);
	67	struct drm_psb_private *dev_priv = dev->dev_private;
	68	int level = bd->props.brightness;
	69	u32 blc_pwm_ctl;
	70	u32 max_pwm_blc;
	71
	72	/* Percentage 1-100% being valid */
	73	if (level < 1)
	74	level = 1;
	75
	76	if (gma_power_begin(dev, 0)) {
	77	/* Calculate and set the brightness value */
	78	max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
	79	blc_pwm_ctl = level * max_pwm_blc / 100;
	80
	81	/* Adjust the backlight level with the percent in
	82	* dev_priv->blc_adj1;
	83	*/
	84	blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
	85	blc_pwm_ctl = blc_pwm_ctl / 100;
	86
	87	/* Adjust the backlight level with the percent in
	88	* dev_priv->blc_adj2;
	89	*/
	90	blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
	91	blc_pwm_ctl = blc_pwm_ctl / 100;
	92
	93	/* force PWM bit on */
	94	REG_WRITE(BLC_PWM_CTL2, (0x80000000 \| REG_READ(BLC_PWM_CTL2)));
	95	REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) \| blc_pwm_ctl);
	96	gma_power_end(dev);
	97	}
	98	oaktrail_brightness = level;
	99	return 0;
	100	}
	101
	102	static int oaktrail_get_brightness(struct backlight_device *bd)
	103	{
	104	/* return locally cached var instead of HW read (due to DPST etc.) */
	105	/* FIXME: ideally return actual value in case firmware fiddled with
	106	it */
	107	return oaktrail_brightness;
	108	}
	109
110	static int device_backlight_init(struct drm_device *dev)
111	{
112	struct drm_psb_private *dev_priv = dev->dev_private;
113	unsigned long core_clock;
114	u16 bl_max_freq;
115	uint32_t value;
116	uint32_t blc_pwm_precision_factor;
117
118	dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
119	dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
120	bl_max_freq = 256;
121	/* this needs to be set elsewhere */
122	blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
123
124	core_clock = dev_priv->core_freq;
125
126	value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
127	value *= blc_pwm_precision_factor;
128	value /= bl_max_freq;
129	value /= blc_pwm_precision_factor;
130
131	if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
132	return -ERANGE;
133
134	if (gma_power_begin(dev, false)) {
135	REG_WRITE(BLC_PWM_CTL2, (0x80000000 \| REG_READ(BLC_PWM_CTL2)));
136	REG_WRITE(BLC_PWM_CTL, value \| (value << 16));
137	gma_power_end(dev);
138	}
139	return 0;
140	}
141
142	static const struct backlight_ops oaktrail_ops = {
143	.get_brightness = oaktrail_get_brightness,
144	.update_status = oaktrail_set_brightness,
145	};
146
771f64d0	147	static int oaktrail_backlight_init(struct drm_device *dev)
1b082ccf AC	148	{
	149	struct drm_psb_private *dev_priv = dev->dev_private;
	150	int ret;
	151	struct backlight_properties props;
	152
	153	memset(&props, 0, sizeof(struct backlight_properties));
	154	props.max_brightness = 100;
	155	props.type = BACKLIGHT_PLATFORM;
	156
	157	oaktrail_backlight_device = backlight_device_register("oaktrail-bl",
	158	NULL, (void *)dev, &oaktrail_ops, &props);
	159
	160	if (IS_ERR(oaktrail_backlight_device))
	161	return PTR_ERR(oaktrail_backlight_device);
	162
	163	ret = device_backlight_init(dev);
	164	if (ret < 0) {
	165	backlight_device_unregister(oaktrail_backlight_device);
	166	return ret;
	167	}
	168	oaktrail_backlight_device->props.brightness = 100;
	169	oaktrail_backlight_device->props.max_brightness = 100;
	170	backlight_update_status(oaktrail_backlight_device);
	171	dev_priv->backlight_device = oaktrail_backlight_device;
	172	return 0;
	173	}
	174
	175	#endif
	176
	177	/*
	178	* Provide the Moorestown specific chip logic and low level methods
	179	* for power management
	180	*/
	181
1b082ccf AC	182	/**
	183	* oaktrail_save_display_registers - save registers lost on suspend
	184	* @dev: our DRM device
	185	*
	186	* Save the state we need in order to be able to restore the interface
	187	* upon resume from suspend
	188	*/
	189	static int oaktrail_save_display_registers(struct drm_device *dev)
	190	{
	191	struct drm_psb_private *dev_priv = dev->dev_private;
c6265ff5	192	struct psb_save_area *regs = &dev_priv->regs;
6256304b	193	struct psb_pipe *p = &regs->pipe[0];
1b082ccf AC	194	int i;
	195	u32 pp_stat;
	196
	197	/* Display arbitration control + watermarks */
c6265ff5 AC	198	regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
	199	regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
	200	regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
	201	regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
	202	regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
	203	regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
	204	regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
	205	regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
1b082ccf AC	206
1b082ccf AC	207	/* Pipe & plane A info */
6256304b AC	208	p->conf = PSB_RVDC32(PIPEACONF);
	209	p->src = PSB_RVDC32(PIPEASRC);
	210	p->fp0 = PSB_RVDC32(MRST_FPA0);
	211	p->fp1 = PSB_RVDC32(MRST_FPA1);
	212	p->dpll = PSB_RVDC32(MRST_DPLL_A);
	213	p->htotal = PSB_RVDC32(HTOTAL_A);
	214	p->hblank = PSB_RVDC32(HBLANK_A);
	215	p->hsync = PSB_RVDC32(HSYNC_A);
	216	p->vtotal = PSB_RVDC32(VTOTAL_A);
	217	p->vblank = PSB_RVDC32(VBLANK_A);
	218	p->vsync = PSB_RVDC32(VSYNC_A);
c6265ff5	219	regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
6256304b AC	220	p->cntr = PSB_RVDC32(DSPACNTR);
	221	p->stride = PSB_RVDC32(DSPASTRIDE);
	222	p->addr = PSB_RVDC32(DSPABASE);
	223	p->surf = PSB_RVDC32(DSPASURF);
	224	p->linoff = PSB_RVDC32(DSPALINOFF);
	225	p->tileoff = PSB_RVDC32(DSPATILEOFF);
1b082ccf AC	226
1b082ccf AC	227	/* Save cursor regs */
c6265ff5 AC	228	regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
	229	regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
	230	regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
1b082ccf AC	231
	232	/* Save palette (gamma) */
	233	for (i = 0; i < 256; i++)
6256304b	234	p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));
1b082ccf AC	235
	236	if (dev_priv->hdmi_priv)
	237	oaktrail_hdmi_save(dev);
	238
	239	/* Save performance state */
c6265ff5	240	regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
1b082ccf AC	241
1b082ccf AC	242	/* LVDS state */
c6265ff5 AC	243	regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
	244	regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
	245	regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
648a8e34 AC	246	regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
648a8e34 AC	247	regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
c6265ff5 AC	248	regs->psb.saveLVDS = PSB_RVDC32(LVDS);
	249	regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
	250	regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
	251	regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
	252	regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
1b082ccf AC	253
1b082ccf AC	254	/* HW overlay */
c6265ff5 AC	255	regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
	256	regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
	257	regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
	258	regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
	259	regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
	260	regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
	261	regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
1b082ccf AC	262
1b082ccf AC	263	/* DPST registers */
c6265ff5	264	regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
1b082ccf	265	PSB_RVDC32(HISTOGRAM_INT_CONTROL);
c6265ff5	266	regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
1b082ccf	267	PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
c6265ff5	268	regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
1b082ccf AC	269
	270	if (dev_priv->iLVDS_enable) {
	271	/* Shut down the panel */
	272	PSB_WVDC32(0, PP_CONTROL);
	273
	274	do {
	275	pp_stat = PSB_RVDC32(PP_STATUS);
	276	} while (pp_stat & 0x80000000);
	277
	278	/* Turn off the plane */
	279	PSB_WVDC32(0x58000000, DSPACNTR);
	280	/* Trigger the plane disable */
	281	PSB_WVDC32(0, DSPASURF);
	282
	283	/* Wait ~4 ticks */
	284	msleep(4);
	285
	286	/* Turn off pipe */
	287	PSB_WVDC32(0x0, PIPEACONF);
	288	/* Wait ~8 ticks */
	289	msleep(8);
	290
	291	/* Turn off PLLs */
	292	PSB_WVDC32(0, MRST_DPLL_A);
	293	}
	294	return 0;
	295	}
	296
	297	/**
	298	* oaktrail_restore_display_registers - restore lost register state
	299	* @dev: our DRM device
	300	*
	301	* Restore register state that was lost during suspend and resume.
	302	*/
	303	static int oaktrail_restore_display_registers(struct drm_device *dev)
	304	{
	305	struct drm_psb_private *dev_priv = dev->dev_private;
c6265ff5	306	struct psb_save_area *regs = &dev_priv->regs;
6256304b	307	struct psb_pipe *p = &regs->pipe[0];
1b082ccf AC	308	u32 pp_stat;
	309	int i;
	310
	311	/* Display arbitration + watermarks */
c6265ff5 AC	312	PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
	313	PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
	314	PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
	315	PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
	316	PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
	317	PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
	318	PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
	319	PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);
1b082ccf AC	320
	321	/* Make sure VGA plane is off. it initializes to on after reset!*/
	322	PSB_WVDC32(0x80000000, VGACNTRL);
	323
	324	/* set the plls */
6256304b AC	325	PSB_WVDC32(p->fp0, MRST_FPA0);
6256304b AC	326	PSB_WVDC32(p->fp1, MRST_FPA1);
1b082ccf AC	327
1b082ccf AC	328	/* Actually enable it */
6256304b	329	PSB_WVDC32(p->dpll, MRST_DPLL_A);
1b082ccf AC	330	DRM_UDELAY(150);
	331
	332	/* Restore mode */
6256304b AC	333	PSB_WVDC32(p->htotal, HTOTAL_A);
	334	PSB_WVDC32(p->hblank, HBLANK_A);
	335	PSB_WVDC32(p->hsync, HSYNC_A);
	336	PSB_WVDC32(p->vtotal, VTOTAL_A);
	337	PSB_WVDC32(p->vblank, VBLANK_A);
	338	PSB_WVDC32(p->vsync, VSYNC_A);
	339	PSB_WVDC32(p->src, PIPEASRC);
c6265ff5	340	PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
1b082ccf AC	341
1b082ccf AC	342	/* Restore performance mode*/
c6265ff5	343	PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);
1b082ccf AC	344
	345	/* Enable the pipe*/
	346	if (dev_priv->iLVDS_enable)
6256304b	347	PSB_WVDC32(p->conf, PIPEACONF);
1b082ccf AC	348
1b082ccf AC	349	/* Set up the plane*/
6256304b AC	350	PSB_WVDC32(p->linoff, DSPALINOFF);
	351	PSB_WVDC32(p->stride, DSPASTRIDE);
	352	PSB_WVDC32(p->tileoff, DSPATILEOFF);
1b082ccf AC	353
1b082ccf AC	354	/* Enable the plane */
6256304b AC	355	PSB_WVDC32(p->cntr, DSPACNTR);
6256304b AC	356	PSB_WVDC32(p->surf, DSPASURF);
1b082ccf AC	357
1b082ccf AC	358	/* Enable Cursor A */
c6265ff5 AC	359	PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
	360	PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
	361	PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);
1b082ccf AC	362
	363	/* Restore palette (gamma) */
	364	for (i = 0; i < 256; i++)
6256304b	365	PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));
1b082ccf AC	366
	367	if (dev_priv->hdmi_priv)
	368	oaktrail_hdmi_restore(dev);
	369
	370	if (dev_priv->iLVDS_enable) {
648a8e34	371	PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
c6265ff5 AC	372	PSB_WVDC32(regs->psb.saveLVDS, LVDS); /port 61180h/
	373	PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
	374	PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
	375	PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
648a8e34	376	PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
c6265ff5 AC	377	PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
	378	PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
	379	PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
	380	PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
1b082ccf AC	381	}
	382
	383	/* Wait for cycle delay */
	384	do {
	385	pp_stat = PSB_RVDC32(PP_STATUS);
	386	} while (pp_stat & 0x08000000);
	387
	388	/* Wait for panel power up */
	389	do {
	390	pp_stat = PSB_RVDC32(PP_STATUS);
	391	} while (pp_stat & 0x10000000);
	392
	393	/* Restore HW overlay */
c6265ff5 AC	394	PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
	395	PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
	396	PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
	397	PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
	398	PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
	399	PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
	400	PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);
1b082ccf AC	401
1b082ccf AC	402	/* DPST registers */
c6265ff5	403	PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
1b082ccf	404	HISTOGRAM_INT_CONTROL);
c6265ff5	405	PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
1b082ccf	406	HISTOGRAM_LOGIC_CONTROL);
c6265ff5	407	PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);
1b082ccf AC	408
	409	return 0;
	410	}
	411
	412	/**
	413	* oaktrail_power_down - power down the display island
	414	* @dev: our DRM device
	415	*
	416	* Power down the display interface of our device
	417	*/
	418	static int oaktrail_power_down(struct drm_device *dev)
	419	{
	420	struct drm_psb_private *dev_priv = dev->dev_private;
	421	u32 pwr_mask ;
	422	u32 pwr_sts;
	423
	424	pwr_mask = PSB_PWRGT_DISPLAY_MASK;
	425	outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
	426
	427	while (true) {
	428	pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
	429	if ((pwr_sts & pwr_mask) == pwr_mask)
	430	break;
	431	else
	432	udelay(10);
	433	}
	434	return 0;
	435	}
	436
	437	/*
	438	* oaktrail_power_up
	439	*
	440	* Restore power to the specified island(s) (powergating)
	441	*/
	442	static int oaktrail_power_up(struct drm_device *dev)
	443	{
	444	struct drm_psb_private *dev_priv = dev->dev_private;
	445	u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
	446	u32 pwr_sts, pwr_cnt;
	447
	448	pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
	449	pwr_cnt &= ~pwr_mask;
	450	outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
	451
	452	while (true) {
	453	pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
	454	if ((pwr_sts & pwr_mask) == 0)
	455	break;
	456	else
	457	udelay(10);
	458	}
	459	return 0;
	460	}
	461
8512e074 AC	462	/* Oaktrail */
	463	static const struct psb_offset oaktrail_regmap[2] = {
	464	{
	465	.fp0 = MRST_FPA0,
	466	.fp1 = MRST_FPA1,
	467	.cntr = DSPACNTR,
	468	.conf = PIPEACONF,
	469	.src = PIPEASRC,
	470	.dpll = MRST_DPLL_A,
	471	.htotal = HTOTAL_A,
	472	.hblank = HBLANK_A,
	473	.hsync = HSYNC_A,
	474	.vtotal = VTOTAL_A,
	475	.vblank = VBLANK_A,
	476	.vsync = VSYNC_A,
	477	.stride = DSPASTRIDE,
	478	.size = DSPASIZE,
	479	.pos = DSPAPOS,
	480	.surf = DSPASURF,
213a8434	481	.addr = MRST_DSPABASE,
26df641e	482	.base = MRST_DSPABASE,
8512e074 AC	483	.status = PIPEASTAT,
	484	.linoff = DSPALINOFF,
	485	.tileoff = DSPATILEOFF,
	486	.palette = PALETTE_A,
	487	},
	488	{
	489	.fp0 = FPB0,
	490	.fp1 = FPB1,
	491	.cntr = DSPBCNTR,
	492	.conf = PIPEBCONF,
	493	.src = PIPEBSRC,
	494	.dpll = DPLL_B,
	495	.htotal = HTOTAL_B,
	496	.hblank = HBLANK_B,
	497	.hsync = HSYNC_B,
	498	.vtotal = VTOTAL_B,
	499	.vblank = VBLANK_B,
	500	.vsync = VSYNC_B,
	501	.stride = DSPBSTRIDE,
	502	.size = DSPBSIZE,
	503	.pos = DSPBPOS,
	504	.surf = DSPBSURF,
	505	.addr = DSPBBASE,
26df641e	506	.base = DSPBBASE,
8512e074 AC	507	.status = PIPEBSTAT,
	508	.linoff = DSPBLINOFF,
	509	.tileoff = DSPBTILEOFF,
	510	.palette = PALETTE_B,
	511	},
	512	};
1b082ccf	513
1b22edfd	514	static int oaktrail_chip_setup(struct drm_device *dev)
aa0c45fd	515	{
1b22edfd	516	struct drm_psb_private *dev_priv = dev->dev_private;
1b22edfd	517	int ret;
8512e074	518
9c0b6fcd AC	519	if (pci_enable_msi(dev->pdev))
	520	dev_warn(dev->dev, "Enabling MSI failed!\n");
	521
8512e074	522	dev_priv->regmap = oaktrail_regmap;
4086b1e2	523
1b22edfd	524	ret = mid_chip_setup(dev);
aa0c45fd AC	525	if (ret < 0)
aa0c45fd AC	526	return ret;
4086b1e2	527	if (!dev_priv->has_gct) {
aa0c45fd	528	/* Now pull the BIOS data */
d839ede4	529	psb_intel_opregion_init(dev);
aa0c45fd AC	530	psb_intel_init_bios(dev);
aa0c45fd AC	531	}
6528c897	532	gma_intel_setup_gmbus(dev);
5f503148	533	oaktrail_hdmi_setup(dev);
aa0c45fd AC	534	return 0;
	535	}
	536
1b082ccf AC	537	static void oaktrail_teardown(struct drm_device *dev)
1b082ccf AC	538	{
1b22edfd	539	struct drm_psb_private *dev_priv = dev->dev_private;
1b22edfd	540
6528c897	541	gma_intel_teardown_gmbus(dev);
1b082ccf	542	oaktrail_hdmi_teardown(dev);
4086b1e2	543	if (!dev_priv->has_gct)
aa0c45fd	544	psb_intel_destroy_bios(dev);
1b082ccf AC	545	}
	546
	547	const struct psb_ops oaktrail_chip_ops = {
	548	.name = "Oaktrail",
	549	.accel_2d = 1,
	550	.pipes = 2,
	551	.crtcs = 2,
39ec748f	552	.hdmi_mask = (1 << 1),
d235e64a	553	.lvds_mask = (1 << 0),
cf8efd3a	554	.sdvo_mask = (1 << 1),
bc794829	555	.cursor_needs_phys = 0,
1b082ccf AC	556	.sgx_offset = MRST_SGX_OFFSET,
1b082ccf AC	557
aa0c45fd	558	.chip_setup = oaktrail_chip_setup,
1b082ccf AC	559	.chip_teardown = oaktrail_teardown,
	560	.crtc_helper = &oaktrail_helper_funcs,
	561	.crtc_funcs = &psb_intel_crtc_funcs,
	562
	563	.output_init = oaktrail_output_init,
	564
	565	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	566	.backlight_init = oaktrail_backlight_init,
	567	#endif
	568
1b082ccf AC	569	.save_regs = oaktrail_save_display_registers,
1b082ccf AC	570	.restore_regs = oaktrail_restore_display_registers,
d56f57ac DV	571	.save_crtc = gma_crtc_save,
d56f57ac DV	572	.restore_crtc = gma_crtc_restore,
1b082ccf AC	573	.power_down = oaktrail_power_down,
	574	.power_up = oaktrail_power_up,
	575
	576	.i2c_bus = 1,
	577	};