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drm: Redefine pixel formats
[deliverable/linux.git] / drivers / gpu / drm / gma500 / psb_drv.c
CommitLineData
5c49fd3a
AC		 1/**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
5 * All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 **************************************************************************/
21
22#include <drm/drmP.h>
23#include <drm/drm.h>
24#include "psb_drm.h"
25#include "psb_drv.h"
26#include "framebuffer.h"
27#include "psb_reg.h"
28#include "psb_intel_reg.h"
29#include "intel_bios.h"
30#include "mid_bios.h"
31#include <drm/drm_pciids.h>
32#include "power.h"
33#include <linux/cpu.h>
34#include <linux/notifier.h>
35#include <linux/spinlock.h>
36#include <linux/pm_runtime.h>
37#include <acpi/video.h>
af3a2cfb 38#include <linux/module.h>
5c49fd3a
AC		 39
40static int drm_psb_trap_pagefaults;
41
42int drm_psb_no_fb;
43
44static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
45
46MODULE_PARM_DESC(no_fb, "Disable FBdev");
47MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
48module_param_named(no_fb, drm_psb_no_fb, int, 0600);
49module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
50
51
52static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
53 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
54 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops },
55#if defined(CONFIG_DRM_OAKTRAIL)
56 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops},
57 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops},
58 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops},
59 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops},
60 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops},
61 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops},
62 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops},
63 { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops},
64#endif
65#if defined(CONFIG_DRM_CDV)
66 { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
67 { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
68 { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
69 { 0x8086, 0x0be3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
70 { 0x8086, 0x0be4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
71 { 0x8086, 0x0be5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
72 { 0x8086, 0x0be6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
73 { 0x8086, 0x0be7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops},
74#endif
75 { 0, 0, 0}
76};
77MODULE_DEVICE_TABLE(pci, pciidlist);
78
79/*
80 * Standard IOCTLs.
81 */
82
83#define DRM_IOCTL_PSB_SIZES \
84 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
85 struct drm_psb_sizes_arg)
86#define DRM_IOCTL_PSB_FUSE_REG \
87 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
88#define DRM_IOCTL_PSB_DC_STATE \
89 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
90 struct drm_psb_dc_state_arg)
91#define DRM_IOCTL_PSB_ADB \
92 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
93#define DRM_IOCTL_PSB_MODE_OPERATION \
94 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
95 struct drm_psb_mode_operation_arg)
96#define DRM_IOCTL_PSB_STOLEN_MEMORY \
97 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
98 struct drm_psb_stolen_memory_arg)
99#define DRM_IOCTL_PSB_REGISTER_RW \
100 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
101 struct drm_psb_register_rw_arg)
102#define DRM_IOCTL_PSB_DPST \
103 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
104 uint32_t)
105#define DRM_IOCTL_PSB_GAMMA \
106 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
107 struct drm_psb_dpst_lut_arg)
108#define DRM_IOCTL_PSB_DPST_BL \
109 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
110 uint32_t)
111#define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID \
112 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
113 struct drm_psb_get_pipe_from_crtc_id_arg)
114#define DRM_IOCTL_PSB_GEM_CREATE \
115 DRM_IOWR(DRM_PSB_GEM_CREATE + DRM_COMMAND_BASE, \
116 struct drm_psb_gem_create)
117#define DRM_IOCTL_PSB_GEM_MMAP \
118 DRM_IOWR(DRM_PSB_GEM_MMAP + DRM_COMMAND_BASE, \
119 struct drm_psb_gem_mmap)
120
121static int psb_sizes_ioctl(struct drm_device *dev, void *data,
122 struct drm_file *file_priv);
123static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
124 struct drm_file *file_priv);
125static int psb_adb_ioctl(struct drm_device *dev, void *data,
126 struct drm_file *file_priv);
127static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
128 struct drm_file *file_priv);
129static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
130 struct drm_file *file_priv);
131static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
132 struct drm_file *file_priv);
133static int psb_dpst_ioctl(struct drm_device *dev, void *data,
134 struct drm_file *file_priv);
135static int psb_gamma_ioctl(struct drm_device *dev, void *data,
136 struct drm_file *file_priv);
137static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
138 struct drm_file *file_priv);
139
140#define PSB_IOCTL_DEF(ioctl, func, flags) \
141 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
142
143static struct drm_ioctl_desc psb_ioctls[] = {
144 PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
145 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
146 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
147 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
148 DRM_AUTH),
149 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
150 DRM_AUTH),
151 PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
152 DRM_AUTH),
153 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
154 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
155 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
156 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
157 psb_intel_get_pipe_from_crtc_id, 0),
158 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GEM_CREATE, psb_gem_create_ioctl,
159 DRM_UNLOCKED | DRM_AUTH),
160 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GEM_MMAP, psb_gem_mmap_ioctl,
161 DRM_UNLOCKED | DRM_AUTH),
162};
163
164static void psb_lastclose(struct drm_device *dev)
165{
166 return;
167}
168
169static void psb_do_takedown(struct drm_device *dev)
170{
171 /* FIXME: do we need to clean up the gtt here ? */
172}
173
174static int psb_do_init(struct drm_device *dev)
175{
176 struct drm_psb_private *dev_priv = dev->dev_private;
177 struct psb_gtt *pg = &dev_priv->gtt;
178
179 uint32_t stolen_gtt;
180
181 int ret = -ENOMEM;
182
183 if (pg->mmu_gatt_start & 0x0FFFFFFF) {
184 dev_err(dev->dev, "Gatt must be 256M aligned. This is a bug.\n");
185 ret = -EINVAL;
186 goto out_err;
187 }
188
189
190 stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
191 stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
192 stolen_gtt =
193 (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
194
195 dev_priv->gatt_free_offset = pg->mmu_gatt_start +
196 (stolen_gtt << PAGE_SHIFT) * 1024;
197
198 if (1 || drm_debug) {
199 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
200 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
201 DRM_INFO("SGX core id = 0x%08x\n", core_id);
202 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
203 (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
204 _PSB_CC_REVISION_MAJOR_SHIFT,
205 (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
206 _PSB_CC_REVISION_MINOR_SHIFT);
207 DRM_INFO
208 ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
209 (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
210 _PSB_CC_REVISION_MAINTENANCE_SHIFT,
211 (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
212 _PSB_CC_REVISION_DESIGNER_SHIFT);
213 }
214
215
216 spin_lock_init(&dev_priv->irqmask_lock);
217 mutex_init(&dev_priv->mutex_2d);
218
219 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
220 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
221 PSB_RSGX32(PSB_CR_BIF_BANK1);
222 PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
223 PSB_CR_BIF_CTRL);
224 psb_spank(dev_priv);
225
226 /* mmu_gatt ?? */
227 PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
228 return 0;
229out_err:
230 psb_do_takedown(dev);
231 return ret;
232}
233
234static int psb_driver_unload(struct drm_device *dev)
235{
236 struct drm_psb_private *dev_priv = dev->dev_private;
237
238 /* Kill vblank etc here */
239
240 gma_backlight_exit(dev);
241
242 if (drm_psb_no_fb == 0)
243 psb_modeset_cleanup(dev);
244
245 if (dev_priv) {
246 psb_lid_timer_takedown(dev_priv);
247 gma_intel_opregion_exit(dev);
248
249 if (dev_priv->ops->chip_teardown)
250 dev_priv->ops->chip_teardown(dev);
251 psb_do_takedown(dev);
252
253
254 if (dev_priv->pf_pd) {
255 psb_mmu_free_pagedir(dev_priv->pf_pd);
256 dev_priv->pf_pd = NULL;
257 }
258 if (dev_priv->mmu) {
259 struct psb_gtt *pg = &dev_priv->gtt;
260
261 down_read(&pg->sem);
262 psb_mmu_remove_pfn_sequence(
263 psb_mmu_get_default_pd
264 (dev_priv->mmu),
265 pg->mmu_gatt_start,
266 dev_priv->vram_stolen_size >> PAGE_SHIFT);
267 up_read(&pg->sem);
268 psb_mmu_driver_takedown(dev_priv->mmu);
269 dev_priv->mmu = NULL;
270 }
271 psb_gtt_takedown(dev);
272 if (dev_priv->scratch_page) {
273 __free_page(dev_priv->scratch_page);
274 dev_priv->scratch_page = NULL;
275 }
276 if (dev_priv->vdc_reg) {
277 iounmap(dev_priv->vdc_reg);
278 dev_priv->vdc_reg = NULL;
279 }
280 if (dev_priv->sgx_reg) {
281 iounmap(dev_priv->sgx_reg);
282 dev_priv->sgx_reg = NULL;
283 }
284
285 kfree(dev_priv);
286 dev->dev_private = NULL;
287
288 /*destroy VBT data*/
289 psb_intel_destroy_bios(dev);
290 }
291
292 gma_power_uninit(dev);
293
294 return 0;
295}
296
297
298static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
299{
300 struct drm_psb_private *dev_priv;
301 unsigned long resource_start;
302 struct psb_gtt *pg;
303 unsigned long irqflags;
304 int ret = -ENOMEM;
305 uint32_t tt_pages;
306 struct drm_connector *connector;
307 struct psb_intel_output *psb_intel_output;
308
309 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
310 if (dev_priv == NULL)
311 return -ENOMEM;
312
313 dev_priv->ops = (struct psb_ops *)chipset;
314 dev_priv->dev = dev;
315 dev->dev_private = (void *) dev_priv;
316
317 dev_priv->num_pipe = dev_priv->ops->pipes;
318
319 resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
320
321 dev_priv->vdc_reg =
322 ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
323 if (!dev_priv->vdc_reg)
324 goto out_err;
325
326 dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset,
327 PSB_SGX_SIZE);
328 if (!dev_priv->sgx_reg)
329 goto out_err;
330
331 ret = dev_priv->ops->chip_setup(dev);
332 if (ret)
333 goto out_err;
334
335 /* Init OSPM support */
336 gma_power_init(dev);
337
338 ret = -ENOMEM;
339
340 dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
341 if (!dev_priv->scratch_page)
342 goto out_err;
343
344 set_pages_uc(dev_priv->scratch_page, 1);
345
346 ret = psb_gtt_init(dev, 0);
347 if (ret)
348 goto out_err;
349
350 dev_priv->mmu = psb_mmu_driver_init((void *)0,
351 drm_psb_trap_pagefaults, 0,
352 dev_priv);
353 if (!dev_priv->mmu)
354 goto out_err;
355
356 pg = &dev_priv->gtt;
357
358 tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
359 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
360
361
362 dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
363 if (!dev_priv->pf_pd)
364 goto out_err;
365
366 psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
367 psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
368
369 ret = psb_do_init(dev);
370 if (ret)
371 return ret;
372
373 PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
374 PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
375
376/* igd_opregion_init(&dev_priv->opregion_dev); */
377 acpi_video_register();
378 if (dev_priv->lid_state)
379 psb_lid_timer_init(dev_priv);
380
381 ret = drm_vblank_init(dev, dev_priv->num_pipe);
382 if (ret)
383 goto out_err;
384
385 /*
386 * Install interrupt handlers prior to powering off SGX or else we will
387 * crash.
388 */
389 dev_priv->vdc_irq_mask = 0;
390 dev_priv->pipestat[0] = 0;
391 dev_priv->pipestat[1] = 0;
392 dev_priv->pipestat[2] = 0;
393 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
394 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
395 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
396 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
397 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
398 if (drm_core_check_feature(dev, DRIVER_MODESET))
399 drm_irq_install(dev);
400
401 dev->vblank_disable_allowed = 1;
402
403 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
404
405 dev->driver->get_vblank_counter = psb_get_vblank_counter;
406
407 if (drm_psb_no_fb == 0) {
408 psb_modeset_init(dev);
409 psb_fbdev_init(dev);
410 drm_kms_helper_poll_init(dev);
411 }
412
413 /* Only add backlight support if we have LVDS output */
414 list_for_each_entry(connector, &dev->mode_config.connector_list,
415 head) {
416 psb_intel_output = to_psb_intel_output(connector);
417
418 switch (psb_intel_output->type) {
419 case INTEL_OUTPUT_LVDS:
420 case INTEL_OUTPUT_MIPI:
421 ret = gma_backlight_init(dev);
422 break;
423 }
424 }
425
426 if (ret)
427 return ret;
428#if 0
429 /*enable runtime pm at last*/
430 pm_runtime_enable(&dev->pdev->dev);
431 pm_runtime_set_active(&dev->pdev->dev);
432#endif
433 /*Intel drm driver load is done, continue doing pvr load*/
434 return 0;
435out_err:
436 psb_driver_unload(dev);
437 return ret;
438}
439
440int psb_driver_device_is_agp(struct drm_device *dev)
441{
442 return 0;
443}
444
445
446static int psb_sizes_ioctl(struct drm_device *dev, void *data,
447 struct drm_file *file_priv)
448{
449 struct drm_psb_private *dev_priv = psb_priv(dev);
450 struct drm_psb_sizes_arg *arg =
451 (struct drm_psb_sizes_arg *) data;
452
453 *arg = dev_priv->sizes;
454 return 0;
455}
456
457static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
458 struct drm_file *file_priv)
459{
460 uint32_t flags;
461 uint32_t obj_id;
462 struct drm_mode_object *obj;
463 struct drm_connector *connector;
464 struct drm_crtc *crtc;
465 struct drm_psb_dc_state_arg *arg = data;
466
467
468 /* Double check MRST case */
469 if (IS_MRST(dev) || IS_MFLD(dev))
470 return -EOPNOTSUPP;
471
472 flags = arg->flags;
473 obj_id = arg->obj_id;
474
475 if (flags & PSB_DC_CRTC_MASK) {
476 obj = drm_mode_object_find(dev, obj_id,
477 DRM_MODE_OBJECT_CRTC);
478 if (!obj) {
479 dev_dbg(dev->dev, "Invalid CRTC object.\n");
480 return -EINVAL;
481 }
482
483 crtc = obj_to_crtc(obj);
484
485 mutex_lock(&dev->mode_config.mutex);
486 if (drm_helper_crtc_in_use(crtc)) {
487 if (flags & PSB_DC_CRTC_SAVE)
488 crtc->funcs->save(crtc);
489 else
490 crtc->funcs->restore(crtc);
491 }
492 mutex_unlock(&dev->mode_config.mutex);
493
494 return 0;
495 } else if (flags & PSB_DC_OUTPUT_MASK) {
496 obj = drm_mode_object_find(dev, obj_id,
497 DRM_MODE_OBJECT_CONNECTOR);
498 if (!obj) {
499 dev_dbg(dev->dev, "Invalid connector id.\n");
500 return -EINVAL;
501 }
502
503 connector = obj_to_connector(obj);
504 if (flags & PSB_DC_OUTPUT_SAVE)
505 connector->funcs->save(connector);
506 else
507 connector->funcs->restore(connector);
508
509 return 0;
510 }
511 return -EINVAL;
512}
513
514static inline void get_brightness(struct backlight_device *bd)
515{
516#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
517 if (bd) {
518 bd->props.brightness = bd->ops->get_brightness(bd);
519 backlight_update_status(bd);
520 }
521#endif
522}
523
524static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
525 struct drm_file *file_priv)
526{
527 struct drm_psb_private *dev_priv = psb_priv(dev);
528 uint32_t *arg = data;
529
530 dev_priv->blc_adj2 = *arg;
531 get_brightness(dev_priv->backlight_device);
532 return 0;
533}
534
535static int psb_adb_ioctl(struct drm_device *dev, void *data,
536 struct drm_file *file_priv)
537{
538 struct drm_psb_private *dev_priv = psb_priv(dev);
539 uint32_t *arg = data;
540
541 dev_priv->blc_adj1 = *arg;
542 get_brightness(dev_priv->backlight_device);
543 return 0;
544}
545
546/* return the current mode to the dpst module */
547static int psb_dpst_ioctl(struct drm_device *dev, void *data,
548 struct drm_file *file_priv)
549{
550 struct drm_psb_private *dev_priv = psb_priv(dev);
551 uint32_t *arg = data;
552 uint32_t x;
553 uint32_t y;
554 uint32_t reg;
555
556 if (!gma_power_begin(dev, 0))
557 return -EIO;
558
559 reg = PSB_RVDC32(PIPEASRC);
560
561 gma_power_end(dev);
562
563 /* horizontal is the left 16 bits */
564 x = reg >> 16;
565 /* vertical is the right 16 bits */
566 y = reg & 0x0000ffff;
567
568 /* the values are the image size minus one */
569 x++;
570 y++;
571
572 *arg = (x << 16) | y;
573
574 return 0;
575}
576static int psb_gamma_ioctl(struct drm_device *dev, void *data,
577 struct drm_file *file_priv)
578{
579 struct drm_psb_dpst_lut_arg *lut_arg = data;
580 struct drm_mode_object *obj;
581 struct drm_crtc *crtc;
582 struct drm_connector *connector;
583 struct psb_intel_crtc *psb_intel_crtc;
584 int i = 0;
585 int32_t obj_id;
586
587 obj_id = lut_arg->output_id;
588 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
589 if (!obj) {
590 dev_dbg(dev->dev, "Invalid Connector object.\n");
591 return -EINVAL;
592 }
593
594 connector = obj_to_connector(obj);
595 crtc = connector->encoder->crtc;
596 psb_intel_crtc = to_psb_intel_crtc(crtc);
597
598 for (i = 0; i < 256; i++)
599 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
600
601 psb_intel_crtc_load_lut(crtc);
602
603 return 0;
604}
605
606static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
607 struct drm_file *file_priv)
608{
609 uint32_t obj_id;
610 uint16_t op;
611 struct drm_mode_modeinfo *umode;
612 struct drm_display_mode *mode = NULL;
613 struct drm_psb_mode_operation_arg *arg;
614 struct drm_mode_object *obj;
615 struct drm_connector *connector;
616 struct drm_framebuffer *drm_fb;
617 struct psb_framebuffer *psb_fb;
618 struct drm_connector_helper_funcs *connector_funcs;
619 int ret = 0;
620 int resp = MODE_OK;
621 struct drm_psb_private *dev_priv = psb_priv(dev);
622
623 arg = (struct drm_psb_mode_operation_arg *)data;
624 obj_id = arg->obj_id;
625 op = arg->operation;
626
627 switch (op) {
628 case PSB_MODE_OPERATION_SET_DC_BASE:
629 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
630 if (!obj) {
631 dev_dbg(dev->dev, "Invalid FB id %d\n", obj_id);
632 return -EINVAL;
633 }
634
635 drm_fb = obj_to_fb(obj);
636 psb_fb = to_psb_fb(drm_fb);
637
638 if (gma_power_begin(dev, 0)) {
639 REG_WRITE(DSPASURF, psb_fb->gtt->offset);
640 REG_READ(DSPASURF);
641 gma_power_end(dev);
642 } else {
643 dev_priv->saveDSPASURF = psb_fb->gtt->offset;
644 }
645
646 return 0;
647 case PSB_MODE_OPERATION_MODE_VALID:
648 umode = &arg->mode;
649
650 mutex_lock(&dev->mode_config.mutex);
651
652 obj = drm_mode_object_find(dev, obj_id,
653 DRM_MODE_OBJECT_CONNECTOR);
654 if (!obj) {
655 ret = -EINVAL;
656 goto mode_op_out;
657 }
658
659 connector = obj_to_connector(obj);
660
661 mode = drm_mode_create(dev);
662 if (!mode) {
663 ret = -ENOMEM;
664 goto mode_op_out;
665 }
666
667 /* drm_crtc_convert_umode(mode, umode); */
668 {
669 mode->clock = umode->clock;
670 mode->hdisplay = umode->hdisplay;
671 mode->hsync_start = umode->hsync_start;
672 mode->hsync_end = umode->hsync_end;
673 mode->htotal = umode->htotal;
674 mode->hskew = umode->hskew;
675 mode->vdisplay = umode->vdisplay;
676 mode->vsync_start = umode->vsync_start;
677 mode->vsync_end = umode->vsync_end;
678 mode->vtotal = umode->vtotal;
679 mode->vscan = umode->vscan;
680 mode->vrefresh = umode->vrefresh;
681 mode->flags = umode->flags;
682 mode->type = umode->type;
683 strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
684 mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
685 }
686
687 connector_funcs = (struct drm_connector_helper_funcs *)
688 connector->helper_private;
689
690 if (connector_funcs->mode_valid) {
691 resp = connector_funcs->mode_valid(connector, mode);
692 arg->data = (void *)resp;
693 }
694
695 /*do some clean up work*/
696 if (mode)
697 drm_mode_destroy(dev, mode);
698mode_op_out:
699 mutex_unlock(&dev->mode_config.mutex);
700 return ret;
701
702 default:
703 dev_dbg(dev->dev, "Unsupported psb mode operation\n");
704 return -EOPNOTSUPP;
705 }
706
707 return 0;
708}
709
710static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
711 struct drm_file *file_priv)
712{
713 struct drm_psb_private *dev_priv = psb_priv(dev);
714 struct drm_psb_stolen_memory_arg *arg = data;
715
716 arg->base = dev_priv->stolen_base;
717 arg->size = dev_priv->vram_stolen_size;
718
719 return 0;
720}
721
722/* FIXME: needs Medfield changes */
723static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
724 struct drm_file *file_priv)
725{
726 struct drm_psb_private *dev_priv = psb_priv(dev);
727 struct drm_psb_register_rw_arg *arg = data;
728 bool usage = arg->b_force_hw_on ? true : false;
729
730 if (arg->display_write_mask != 0) {
731 if (gma_power_begin(dev, usage)) {
732 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
733 PSB_WVDC32(arg->display.pfit_controls,
734 PFIT_CONTROL);
735 if (arg->display_write_mask &
736 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
737 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
738 PFIT_AUTO_RATIOS);
739 if (arg->display_write_mask &
740 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
741 PSB_WVDC32(
742 arg->display.pfit_programmed_scale_ratios,
743 PFIT_PGM_RATIOS);
744 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
745 PSB_WVDC32(arg->display.pipeasrc,
746 PIPEASRC);
747 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
748 PSB_WVDC32(arg->display.pipebsrc,
749 PIPEBSRC);
750 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
751 PSB_WVDC32(arg->display.vtotal_a,
752 VTOTAL_A);
753 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
754 PSB_WVDC32(arg->display.vtotal_b,
755 VTOTAL_B);
756 gma_power_end(dev);
757 } else {
758 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
759 dev_priv->savePFIT_CONTROL =
760 arg->display.pfit_controls;
761 if (arg->display_write_mask &
762 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
763 dev_priv->savePFIT_AUTO_RATIOS =
764 arg->display.pfit_autoscale_ratios;
765 if (arg->display_write_mask &
766 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
767 dev_priv->savePFIT_PGM_RATIOS =
768 arg->display.pfit_programmed_scale_ratios;
769 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
770 dev_priv->savePIPEASRC = arg->display.pipeasrc;
771 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
772 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
773 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
774 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
775 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
776 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
777 }
778 }
779
780 if (arg->display_read_mask != 0) {
781 if (gma_power_begin(dev, usage)) {
782 if (arg->display_read_mask &
783 REGRWBITS_PFIT_CONTROLS)
784 arg->display.pfit_controls =
785 PSB_RVDC32(PFIT_CONTROL);
786 if (arg->display_read_mask &
787 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
788 arg->display.pfit_autoscale_ratios =
789 PSB_RVDC32(PFIT_AUTO_RATIOS);
790 if (arg->display_read_mask &
791 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
792 arg->display.pfit_programmed_scale_ratios =
793 PSB_RVDC32(PFIT_PGM_RATIOS);
794 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
795 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
796 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
797 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
798 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
799 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
800 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
801 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
802 gma_power_end(dev);
803 } else {
804 if (arg->display_read_mask &
805 REGRWBITS_PFIT_CONTROLS)
806 arg->display.pfit_controls =
807 dev_priv->savePFIT_CONTROL;
808 if (arg->display_read_mask &
809 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
810 arg->display.pfit_autoscale_ratios =
811 dev_priv->savePFIT_AUTO_RATIOS;
812 if (arg->display_read_mask &
813 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
814 arg->display.pfit_programmed_scale_ratios =
815 dev_priv->savePFIT_PGM_RATIOS;
816 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
817 arg->display.pipeasrc = dev_priv->savePIPEASRC;
818 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
819 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
820 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
821 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
822 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
823 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
824 }
825 }
826
827 if (arg->overlay_write_mask != 0) {
828 if (gma_power_begin(dev, usage)) {
829 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
830 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
831 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
832 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
833 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
834 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
835 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
836 }
837 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
838 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
839 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
840 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
841 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
842 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
843 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
844 }
845
846 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
847 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
848
849 if (arg->overlay.b_wait_vblank) {
850 /* Wait for 20ms.*/
851 unsigned long vblank_timeout = jiffies
852 + HZ/50;
853 uint32_t temp;
854 while (time_before_eq(jiffies,
855 vblank_timeout)) {
856 temp = PSB_RVDC32(OV_DOVASTA);
857 if ((temp & (0x1 << 31)) != 0)
858 break;
859 cpu_relax();
860 }
861 }
862 }
863 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
864 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
865 if (arg->overlay.b_wait_vblank) {
866 /* Wait for 20ms.*/
867 unsigned long vblank_timeout =
868 jiffies + HZ/50;
869 uint32_t temp;
870 while (time_before_eq(jiffies,
871 vblank_timeout)) {
872 temp = PSB_RVDC32(OVC_DOVCSTA);
873 if ((temp & (0x1 << 31)) != 0)
874 break;
875 cpu_relax();
876 }
877 }
878 }
879 gma_power_end(dev);
880 } else {
881 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
882 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
883 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
884 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
885 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
886 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
887 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
888 }
889 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
890 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
891 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
892 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
893 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
894 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
895 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
896 }
897 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
898 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
899 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
900 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
901 }
902 }
903
904 if (arg->overlay_read_mask != 0) {
905 if (gma_power_begin(dev, usage)) {
906 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
907 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
908 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
909 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
910 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
911 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
912 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
913 }
914 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
915 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
916 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
917 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
918 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
919 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
920 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
921 }
922 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
923 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
924 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
925 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
926 gma_power_end(dev);
927 } else {
928 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
929 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
930 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
931 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
932 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
933 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
934 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
935 }
936 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
937 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
938 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
939 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
940 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
941 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
942 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
943 }
944 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
945 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
946 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
947 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
948 }
949 }
950
951 if (arg->sprite_enable_mask != 0) {
952 if (gma_power_begin(dev, usage)) {
953 PSB_WVDC32(0x1F3E, DSPARB);
954 PSB_WVDC32(arg->sprite.dspa_control
955 | PSB_RVDC32(DSPACNTR), DSPACNTR);
956 PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
957 PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
958 PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
959 PSB_RVDC32(DSPASURF);
960 PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
961 PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
962 PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
963 PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
964 PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
965 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
966 PSB_RVDC32(DSPCSURF);
967 gma_power_end(dev);
968 }
969 }
970
971 if (arg->sprite_disable_mask != 0) {
972 if (gma_power_begin(dev, usage)) {
973 PSB_WVDC32(0x3F3E, DSPARB);
974 PSB_WVDC32(0x0, DSPCCNTR);
975 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
976 PSB_RVDC32(DSPCSURF);
977 gma_power_end(dev);
978 }
979 }
980
981 if (arg->subpicture_enable_mask != 0) {
982 if (gma_power_begin(dev, usage)) {
983 uint32_t temp;
984 if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
985 temp = PSB_RVDC32(DSPACNTR);
986 temp &= ~DISPPLANE_PIXFORMAT_MASK;
987 temp &= ~DISPPLANE_BOTTOM;
988 temp |= DISPPLANE_32BPP;
989 PSB_WVDC32(temp, DSPACNTR);
990
991 temp = PSB_RVDC32(DSPABASE);
992 PSB_WVDC32(temp, DSPABASE);
993 PSB_RVDC32(DSPABASE);
994 temp = PSB_RVDC32(DSPASURF);
995 PSB_WVDC32(temp, DSPASURF);
996 PSB_RVDC32(DSPASURF);
997 }
998 if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
999 temp = PSB_RVDC32(DSPBCNTR);
1000 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1001 temp &= ~DISPPLANE_BOTTOM;
1002 temp |= DISPPLANE_32BPP;
1003 PSB_WVDC32(temp, DSPBCNTR);
1004
1005 temp = PSB_RVDC32(DSPBBASE);
1006 PSB_WVDC32(temp, DSPBBASE);
1007 PSB_RVDC32(DSPBBASE);
1008 temp = PSB_RVDC32(DSPBSURF);
1009 PSB_WVDC32(temp, DSPBSURF);
1010 PSB_RVDC32(DSPBSURF);
1011 }
1012 if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1013 temp = PSB_RVDC32(DSPCCNTR);
1014 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1015 temp &= ~DISPPLANE_BOTTOM;
1016 temp |= DISPPLANE_32BPP;
1017 PSB_WVDC32(temp, DSPCCNTR);
1018
1019 temp = PSB_RVDC32(DSPCBASE);
1020 PSB_WVDC32(temp, DSPCBASE);
1021 PSB_RVDC32(DSPCBASE);
1022 temp = PSB_RVDC32(DSPCSURF);
1023 PSB_WVDC32(temp, DSPCSURF);
1024 PSB_RVDC32(DSPCSURF);
1025 }
1026 gma_power_end(dev);
1027 }
1028 }
1029
1030 if (arg->subpicture_disable_mask != 0) {
1031 if (gma_power_begin(dev, usage)) {
1032 uint32_t temp;
1033 if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1034 temp = PSB_RVDC32(DSPACNTR);
1035 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1036 temp |= DISPPLANE_32BPP_NO_ALPHA;
1037 PSB_WVDC32(temp, DSPACNTR);
1038
1039 temp = PSB_RVDC32(DSPABASE);
1040 PSB_WVDC32(temp, DSPABASE);
1041 PSB_RVDC32(DSPABASE);
1042 temp = PSB_RVDC32(DSPASURF);
1043 PSB_WVDC32(temp, DSPASURF);
1044 PSB_RVDC32(DSPASURF);
1045 }
1046 if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1047 temp = PSB_RVDC32(DSPBCNTR);
1048 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1049 temp |= DISPPLANE_32BPP_NO_ALPHA;
1050 PSB_WVDC32(temp, DSPBCNTR);
1051
1052 temp = PSB_RVDC32(DSPBBASE);
1053 PSB_WVDC32(temp, DSPBBASE);
1054 PSB_RVDC32(DSPBBASE);
1055 temp = PSB_RVDC32(DSPBSURF);
1056 PSB_WVDC32(temp, DSPBSURF);
1057 PSB_RVDC32(DSPBSURF);
1058 }
1059 if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1060 temp = PSB_RVDC32(DSPCCNTR);
1061 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1062 temp |= DISPPLANE_32BPP_NO_ALPHA;
1063 PSB_WVDC32(temp, DSPCCNTR);
1064
1065 temp = PSB_RVDC32(DSPCBASE);
1066 PSB_WVDC32(temp, DSPCBASE);
1067 PSB_RVDC32(DSPCBASE);
1068 temp = PSB_RVDC32(DSPCSURF);
1069 PSB_WVDC32(temp, DSPCSURF);
1070 PSB_RVDC32(DSPCSURF);
1071 }
1072 gma_power_end(dev);
1073 }
1074 }
1075
1076 return 0;
1077}
1078
1079static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1080{
1081 return 0;
1082}
1083
1084static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1085{
1086}
1087
1088static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1089 unsigned long arg)
1090{
1091 struct drm_file *file_priv = filp->private_data;
1092 struct drm_device *dev = file_priv->minor->dev;
1093 struct drm_psb_private *dev_priv = dev->dev_private;
1094 static unsigned int runtime_allowed;
1095
1096 if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1097 runtime_allowed++;
1098 pm_runtime_allow(&dev->pdev->dev);
1099 dev_priv->rpm_enabled = 1;
1100 }
1101 return drm_ioctl(filp, cmd, arg);
1102 /* FIXME: do we need to wrap the other side of this */
1103}
1104
1105
1106/* When a client dies:
1107 * - Check for and clean up flipped page state
1108 */
1109void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1110{
1111}
1112
1113static void psb_remove(struct pci_dev *pdev)
1114{
1115 struct drm_device *dev = pci_get_drvdata(pdev);
1116 drm_put_dev(dev);
1117}
1118
1119static const struct dev_pm_ops psb_pm_ops = {
1120 .resume = gma_power_resume,
1121 .suspend = gma_power_suspend,
1122 .runtime_suspend = psb_runtime_suspend,
1123 .runtime_resume = psb_runtime_resume,
1124 .runtime_idle = psb_runtime_idle,
1125};
1126
1127static struct vm_operations_struct psb_gem_vm_ops = {
1128 .fault = psb_gem_fault,
1129 .open = drm_gem_vm_open,
1130 .close = drm_gem_vm_close,
1131};
1132
1595c568
IH		 1133static const struct file_operations psb_gem_fops = {
1134 .owner = THIS_MODULE,
1135 .open = drm_open,
1136 .release = drm_release,
1137 .unlocked_ioctl = psb_unlocked_ioctl,
1138 .mmap = drm_gem_mmap,
1139 .poll = drm_poll,
1140 .fasync = drm_fasync,
1141 .read = drm_read,
1142};
1143
5c49fd3a
AC		 1144static struct drm_driver driver = {
1145 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1146 DRIVER_IRQ_VBL | DRIVER_MODESET | DRIVER_GEM ,
1147 .load = psb_driver_load,
1148 .unload = psb_driver_unload,
1149
1150 .ioctls = psb_ioctls,
1151 .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1152 .device_is_agp = psb_driver_device_is_agp,
1153 .irq_preinstall = psb_irq_preinstall,
1154 .irq_postinstall = psb_irq_postinstall,
1155 .irq_uninstall = psb_irq_uninstall,
1156 .irq_handler = psb_irq_handler,
1157 .enable_vblank = psb_enable_vblank,
1158 .disable_vblank = psb_disable_vblank,
1159 .get_vblank_counter = psb_get_vblank_counter,
1160 .lastclose = psb_lastclose,
1161 .open = psb_driver_open,
1162 .preclose = psb_driver_preclose,
1163 .postclose = psb_driver_close,
1164 .reclaim_buffers = drm_core_reclaim_buffers,
1165
1166 .gem_init_object = psb_gem_init_object,
1167 .gem_free_object = psb_gem_free_object,
1168 .gem_vm_ops = &psb_gem_vm_ops,
1169 .dumb_create = psb_gem_dumb_create,
1170 .dumb_map_offset = psb_gem_dumb_map_gtt,
1171 .dumb_destroy = psb_gem_dumb_destroy,
1595c568 1172 .fops = &psb_gem_fops,
5c49fd3a
AC		 1173 .name = DRIVER_NAME,
1174 .desc = DRIVER_DESC,
1175 .date = PSB_DRM_DRIVER_DATE,
1176 .major = PSB_DRM_DRIVER_MAJOR,
1177 .minor = PSB_DRM_DRIVER_MINOR,
1178 .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1179};
1180
1181static struct pci_driver psb_pci_driver = {
1182 .name = DRIVER_NAME,
1183 .id_table = pciidlist,
1184 .probe = psb_probe,
1185 .remove = psb_remove,
1186 .driver.pm = &psb_pm_ops,
1187};
1188
1189static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1190{
1191 /* MLD Added this from Inaky's patch */
1192 if (pci_enable_msi(pdev))
1193 dev_warn(&pdev->dev, "Enable MSI failed!\n");
1194 return drm_get_pci_dev(pdev, ent, &driver);
1195}
1196
1197static int __init psb_init(void)
1198{
1199 return drm_pci_init(&driver, &psb_pci_driver);
1200}
1201
1202static void __exit psb_exit(void)
1203{
1204 drm_pci_exit(&driver, &psb_pci_driver);
1205}
1206
1207late_initcall(psb_init);
1208module_exit(psb_exit);
1209
1210MODULE_AUTHOR("Alan Cox <alan@linux.intel.com> and others");
1211MODULE_DESCRIPTION(DRIVER_DESC);
1212MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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