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gma500: fix -Wmissing-include-dirs warnings
[deliverable/linux.git] / drivers / gpu / drm / gma500 / psb_drv.h
CommitLineData
5c49fd3a
AC		 1/**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20#ifndef _PSB_DRV_H_
21#define _PSB_DRV_H_
22
23#include <linux/kref.h>
24
25#include <drm/drmP.h>
26#include "drm_global.h"
27#include "gem_glue.h"
838fa588 28#include "gma_drm.h"
5c49fd3a
AC		 29#include "psb_reg.h"
30#include "psb_intel_drv.h"
31#include "gtt.h"
32#include "power.h"
d839ede4 33#include "opregion.h"
5c49fd3a
AC		 34#include "oaktrail.h"
35
36/* Append new drm mode definition here, align with libdrm definition */
37#define DRM_MODE_SCALE_NO_SCALE 2
38
39enum {
40 CHIP_PSB_8108 = 0, /* Poulsbo */
41 CHIP_PSB_8109 = 1, /* Poulsbo */
42 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
43 CHIP_MFLD_0130 = 3, /* Medfield */
44};
45
e036ba59 46#define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
5c49fd3a
AC		 47#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
48#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
49
50/*
51 * Driver definitions
52 */
53
54#define DRIVER_NAME "gma500"
55#define DRIVER_DESC "DRM driver for the Intel GMA500"
56
57#define PSB_DRM_DRIVER_DATE "2011-06-06"
58#define PSB_DRM_DRIVER_MAJOR 1
59#define PSB_DRM_DRIVER_MINOR 0
60#define PSB_DRM_DRIVER_PATCHLEVEL 0
61
62/*
63 * Hardware offsets
64 */
65#define PSB_VDC_OFFSET 0x00000000
66#define PSB_VDC_SIZE 0x000080000
67#define MRST_MMIO_SIZE 0x0000C0000
68#define MDFLD_MMIO_SIZE 0x000100000
69#define PSB_SGX_SIZE 0x8000
70#define PSB_SGX_OFFSET 0x00040000
71#define MRST_SGX_OFFSET 0x00080000
72/*
73 * PCI resource identifiers
74 */
75#define PSB_MMIO_RESOURCE 0
76#define PSB_GATT_RESOURCE 2
77#define PSB_GTT_RESOURCE 3
78/*
79 * PCI configuration
80 */
81#define PSB_GMCH_CTRL 0x52
82#define PSB_BSM 0x5C
83#define _PSB_GMCH_ENABLED 0x4
84#define PSB_PGETBL_CTL 0x2020
85#define _PSB_PGETBL_ENABLED 0x00000001
86#define PSB_SGX_2D_SLAVE_PORT 0x4000
87
88/* To get rid of */
89#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
90#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
91
92/*
93 * SGX side MMU definitions (these can probably go)
94 */
95
96/*
97 * Flags for external memory type field.
98 */
99#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
100#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
101#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
102/*
103 * PTE's and PDE's
104 */
105#define PSB_PDE_MASK 0x003FFFFF
106#define PSB_PDE_SHIFT 22
107#define PSB_PTE_SHIFT 12
108/*
109 * Cache control
110 */
111#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
112#define PSB_PTE_WO 0x0002 /* Write only */
113#define PSB_PTE_RO 0x0004 /* Read only */
114#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
115
116/*
117 * VDC registers and bits
118 */
119#define PSB_MSVDX_CLOCKGATING 0x2064
120#define PSB_TOPAZ_CLOCKGATING 0x2068
121#define PSB_HWSTAM 0x2098
122#define PSB_INSTPM 0x20C0
123#define PSB_INT_IDENTITY_R 0x20A4
d839ede4 124#define _PSB_IRQ_ASLE (1<<0)
5c49fd3a
AC		 125#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
126#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
127#define _PSB_DPST_PIPEB_FLAG (1<<4)
128#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
129#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
130#define _PSB_DPST_PIPEA_FLAG (1<<6)
131#define _PSB_PIPEA_EVENT_FLAG (1<<6)
132#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
133#define _MDFLD_MIPIA_FLAG (1<<16)
134#define _MDFLD_MIPIC_FLAG (1<<17)
68cb638f 135#define _PSB_IRQ_DISP_HOTSYNC (1<<17)
5c49fd3a
AC		 136#define _PSB_IRQ_SGX_FLAG (1<<18)
137#define _PSB_IRQ_MSVDX_FLAG (1<<19)
138#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
139
700e59f6
PJ		 140#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
141 _PSB_VSYNC_PIPEB_FLAG)
142
5c49fd3a
AC		 143/* This flag includes all the display IRQ bits excepts the vblank irqs. */
144#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
145 _MDFLD_PIPEB_EVENT_FLAG | \
146 _PSB_PIPEA_EVENT_FLAG | \
147 _PSB_VSYNC_PIPEA_FLAG | \
148 _MDFLD_MIPIA_FLAG | \
149 _MDFLD_MIPIC_FLAG)
150#define PSB_INT_IDENTITY_R 0x20A4
151#define PSB_INT_MASK_R 0x20A8
152#define PSB_INT_ENABLE_R 0x20A0
153
154#define _PSB_MMU_ER_MASK 0x0001FF00
155#define _PSB_MMU_ER_HOST (1 << 16)
156#define GPIOA 0x5010
157#define GPIOB 0x5014
158#define GPIOC 0x5018
159#define GPIOD 0x501c
160#define GPIOE 0x5020
161#define GPIOF 0x5024
162#define GPIOG 0x5028
163#define GPIOH 0x502c
164#define GPIO_CLOCK_DIR_MASK (1 << 0)
165#define GPIO_CLOCK_DIR_IN (0 << 1)
166#define GPIO_CLOCK_DIR_OUT (1 << 1)
167#define GPIO_CLOCK_VAL_MASK (1 << 2)
168#define GPIO_CLOCK_VAL_OUT (1 << 3)
169#define GPIO_CLOCK_VAL_IN (1 << 4)
170#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
171#define GPIO_DATA_DIR_MASK (1 << 8)
172#define GPIO_DATA_DIR_IN (0 << 9)
173#define GPIO_DATA_DIR_OUT (1 << 9)
174#define GPIO_DATA_VAL_MASK (1 << 10)
175#define GPIO_DATA_VAL_OUT (1 << 11)
176#define GPIO_DATA_VAL_IN (1 << 12)
177#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
178
179#define VCLK_DIVISOR_VGA0 0x6000
180#define VCLK_DIVISOR_VGA1 0x6004
181#define VCLK_POST_DIV 0x6010
182
183#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
184#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
185#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
186#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
187#define PSB_COMM_USER_IRQ (1024 >> 2)
188#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
189#define PSB_COMM_FW (2048 >> 2)
190
191#define PSB_UIRQ_VISTEST 1
192#define PSB_UIRQ_OOM_REPLY 2
193#define PSB_UIRQ_FIRE_TA_REPLY 3
194#define PSB_UIRQ_FIRE_RASTER_REPLY 4
195
196#define PSB_2D_SIZE (256*1024*1024)
197#define PSB_MAX_RELOC_PAGES 1024
198
199#define PSB_LOW_REG_OFFS 0x0204
200#define PSB_HIGH_REG_OFFS 0x0600
201
202#define PSB_NUM_VBLANKS 2
203
204
205#define PSB_2D_SIZE (256*1024*1024)
206#define PSB_MAX_RELOC_PAGES 1024
207
208#define PSB_LOW_REG_OFFS 0x0204
209#define PSB_HIGH_REG_OFFS 0x0600
210
211#define PSB_NUM_VBLANKS 2
212#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
213#define PSB_LID_DELAY (DRM_HZ / 10)
214
215#define MDFLD_PNW_B0 0x04
216#define MDFLD_PNW_C0 0x08
217
218#define MDFLD_DSR_2D_3D_0 (1 << 0)
219#define MDFLD_DSR_2D_3D_2 (1 << 1)
220#define MDFLD_DSR_CURSOR_0 (1 << 2)
221#define MDFLD_DSR_CURSOR_2 (1 << 3)
222#define MDFLD_DSR_OVERLAY_0 (1 << 4)
223#define MDFLD_DSR_OVERLAY_2 (1 << 5)
224#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
225#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
226#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
227#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
228
229#define MDFLD_DSR_RR 45
230#define MDFLD_DPU_ENABLE (1 << 31)
231#define MDFLD_DSR_FULLSCREEN (1 << 30)
232#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
233
234#define PSB_PWR_STATE_ON 1
235#define PSB_PWR_STATE_OFF 2
236
237#define PSB_PMPOLICY_NOPM 0
238#define PSB_PMPOLICY_CLOCKGATING 1
239#define PSB_PMPOLICY_POWERDOWN 2
240
241#define PSB_PMSTATE_POWERUP 0
242#define PSB_PMSTATE_CLOCKGATED 1
243#define PSB_PMSTATE_POWERDOWN 2
244#define PSB_PCIx_MSI_ADDR_LOC 0x94
245#define PSB_PCIx_MSI_DATA_LOC 0x98
246
247/* Medfield crystal settings */
248#define KSEL_CRYSTAL_19 1
249#define KSEL_BYPASS_19 5
250#define KSEL_BYPASS_25 6
251#define KSEL_BYPASS_83_100 7
252
253struct opregion_header;
254struct opregion_acpi;
255struct opregion_swsci;
256struct opregion_asle;
257
258struct psb_intel_opregion {
259 struct opregion_header *header;
260 struct opregion_acpi *acpi;
261 struct opregion_swsci *swsci;
262 struct opregion_asle *asle;
1fb28e9e 263 void *vbt;
d839ede4 264 u32 __iomem *lid_state;
5c49fd3a
AC		 265};
266
5736995b
PJ		 267struct sdvo_device_mapping {
268 u8 initialized;
269 u8 dvo_port;
270 u8 slave_addr;
271 u8 dvo_wiring;
272 u8 i2c_pin;
273 u8 i2c_speed;
274 u8 ddc_pin;
275};
276
5c0c1d50
PJ		 277struct intel_gmbus {
278 struct i2c_adapter adapter;
279 struct i2c_adapter *force_bit;
280 u32 reg0;
281};
282
648a8e34
AC		 283/*
284 * Register save state. This is used to hold the context when the
285 * device is powered off. In the case of Oaktrail this can (but does not
286 * yet) include screen blank. Operations occuring during the save
287 * update the register cache instead.
288 */
289struct psb_state {
290 uint32_t saveDSPACNTR;
291 uint32_t saveDSPBCNTR;
292 uint32_t savePIPEACONF;
293 uint32_t savePIPEBCONF;
294 uint32_t savePIPEASRC;
295 uint32_t savePIPEBSRC;
296 uint32_t saveFPA0;
297 uint32_t saveFPA1;
298 uint32_t saveDPLL_A;
299 uint32_t saveDPLL_A_MD;
300 uint32_t saveHTOTAL_A;
301 uint32_t saveHBLANK_A;
302 uint32_t saveHSYNC_A;
303 uint32_t saveVTOTAL_A;
304 uint32_t saveVBLANK_A;
305 uint32_t saveVSYNC_A;
306 uint32_t saveDSPASTRIDE;
307 uint32_t saveDSPASIZE;
308 uint32_t saveDSPAPOS;
309 uint32_t saveDSPABASE;
310 uint32_t saveDSPASURF;
311 uint32_t saveDSPASTATUS;
312 uint32_t saveFPB0;
313 uint32_t saveFPB1;
314 uint32_t saveDPLL_B;
315 uint32_t saveDPLL_B_MD;
316 uint32_t saveHTOTAL_B;
317 uint32_t saveHBLANK_B;
318 uint32_t saveHSYNC_B;
319 uint32_t saveVTOTAL_B;
320 uint32_t saveVBLANK_B;
321 uint32_t saveVSYNC_B;
322 uint32_t saveDSPBSTRIDE;
323 uint32_t saveDSPBSIZE;
324 uint32_t saveDSPBPOS;
325 uint32_t saveDSPBBASE;
326 uint32_t saveDSPBSURF;
327 uint32_t saveDSPBSTATUS;
328 uint32_t saveVCLK_DIVISOR_VGA0;
329 uint32_t saveVCLK_DIVISOR_VGA1;
330 uint32_t saveVCLK_POST_DIV;
331 uint32_t saveVGACNTRL;
332 uint32_t saveADPA;
333 uint32_t saveLVDS;
334 uint32_t saveDVOA;
335 uint32_t saveDVOB;
336 uint32_t saveDVOC;
337 uint32_t savePP_ON;
338 uint32_t savePP_OFF;
339 uint32_t savePP_CONTROL;
340 uint32_t savePP_CYCLE;
341 uint32_t savePFIT_CONTROL;
342 uint32_t savePaletteA[256];
343 uint32_t savePaletteB[256];
648a8e34
AC		 344 uint32_t saveCLOCKGATING;
345 uint32_t saveDSPARB;
346 uint32_t saveDSPATILEOFF;
347 uint32_t saveDSPBTILEOFF;
348 uint32_t saveDSPAADDR;
349 uint32_t saveDSPBADDR;
350 uint32_t savePFIT_AUTO_RATIOS;
351 uint32_t savePFIT_PGM_RATIOS;
352 uint32_t savePP_ON_DELAYS;
353 uint32_t savePP_OFF_DELAYS;
354 uint32_t savePP_DIVISOR;
648a8e34
AC		 355 uint32_t saveBCLRPAT_A;
356 uint32_t saveBCLRPAT_B;
357 uint32_t saveDSPALINOFF;
358 uint32_t saveDSPBLINOFF;
359 uint32_t savePERF_MODE;
360 uint32_t saveDSPFW1;
361 uint32_t saveDSPFW2;
362 uint32_t saveDSPFW3;
363 uint32_t saveDSPFW4;
364 uint32_t saveDSPFW5;
365 uint32_t saveDSPFW6;
366 uint32_t saveCHICKENBIT;
367 uint32_t saveDSPACURSOR_CTRL;
368 uint32_t saveDSPBCURSOR_CTRL;
369 uint32_t saveDSPACURSOR_BASE;
370 uint32_t saveDSPBCURSOR_BASE;
371 uint32_t saveDSPACURSOR_POS;
372 uint32_t saveDSPBCURSOR_POS;
373 uint32_t save_palette_a[256];
374 uint32_t save_palette_b[256];
375 uint32_t saveOV_OVADD;
376 uint32_t saveOV_OGAMC0;
377 uint32_t saveOV_OGAMC1;
378 uint32_t saveOV_OGAMC2;
379 uint32_t saveOV_OGAMC3;
380 uint32_t saveOV_OGAMC4;
381 uint32_t saveOV_OGAMC5;
382 uint32_t saveOVC_OVADD;
383 uint32_t saveOVC_OGAMC0;
384 uint32_t saveOVC_OGAMC1;
385 uint32_t saveOVC_OGAMC2;
386 uint32_t saveOVC_OGAMC3;
387 uint32_t saveOVC_OGAMC4;
388 uint32_t saveOVC_OGAMC5;
389
390 /* DPST register save */
391 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
392 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
393 uint32_t savePWM_CONTROL_LOGIC;
394};
395
026abc33
KS		 396struct medfield_state {
397 uint32_t saveDPLL_A;
398 uint32_t saveFPA0;
399 uint32_t savePIPEACONF;
400 uint32_t saveHTOTAL_A;
401 uint32_t saveHBLANK_A;
402 uint32_t saveHSYNC_A;
403 uint32_t saveVTOTAL_A;
404 uint32_t saveVBLANK_A;
405 uint32_t saveVSYNC_A;
406 uint32_t savePIPEASRC;
407 uint32_t saveDSPASTRIDE;
408 uint32_t saveDSPALINOFF;
409 uint32_t saveDSPATILEOFF;
410 uint32_t saveDSPASIZE;
411 uint32_t saveDSPAPOS;
412 uint32_t saveDSPASURF;
413 uint32_t saveDSPACNTR;
414 uint32_t saveDSPASTATUS;
415 uint32_t save_palette_a[256];
416 uint32_t saveMIPI;
417
418 uint32_t saveDPLL_B;
419 uint32_t saveFPB0;
420 uint32_t savePIPEBCONF;
421 uint32_t saveHTOTAL_B;
422 uint32_t saveHBLANK_B;
423 uint32_t saveHSYNC_B;
424 uint32_t saveVTOTAL_B;
425 uint32_t saveVBLANK_B;
426 uint32_t saveVSYNC_B;
427 uint32_t savePIPEBSRC;
428 uint32_t saveDSPBSTRIDE;
429 uint32_t saveDSPBLINOFF;
430 uint32_t saveDSPBTILEOFF;
431 uint32_t saveDSPBSIZE;
432 uint32_t saveDSPBPOS;
433 uint32_t saveDSPBSURF;
434 uint32_t saveDSPBCNTR;
435 uint32_t saveDSPBSTATUS;
436 uint32_t save_palette_b[256];
437
438 uint32_t savePIPECCONF;
439 uint32_t saveHTOTAL_C;
440 uint32_t saveHBLANK_C;
441 uint32_t saveHSYNC_C;
442 uint32_t saveVTOTAL_C;
443 uint32_t saveVBLANK_C;
444 uint32_t saveVSYNC_C;
445 uint32_t savePIPECSRC;
446 uint32_t saveDSPCSTRIDE;
447 uint32_t saveDSPCLINOFF;
448 uint32_t saveDSPCTILEOFF;
449 uint32_t saveDSPCSIZE;
450 uint32_t saveDSPCPOS;
451 uint32_t saveDSPCSURF;
452 uint32_t saveDSPCCNTR;
453 uint32_t saveDSPCSTATUS;
454 uint32_t save_palette_c[256];
455 uint32_t saveMIPI_C;
456
457 uint32_t savePFIT_CONTROL;
458 uint32_t savePFIT_PGM_RATIOS;
459 uint32_t saveHDMIPHYMISCCTL;
460 uint32_t saveHDMIB_CONTROL;
461};
462
09016a11
AC		 463struct cdv_state {
464 uint32_t saveDSPCLK_GATE_D;
465 uint32_t saveRAMCLK_GATE_D;
466 uint32_t saveDSPARB;
467 uint32_t saveDSPFW[6];
468 uint32_t saveADPA;
469 uint32_t savePP_CONTROL;
470 uint32_t savePFIT_PGM_RATIOS;
471 uint32_t saveLVDS;
472 uint32_t savePFIT_CONTROL;
473 uint32_t savePP_ON_DELAYS;
474 uint32_t savePP_OFF_DELAYS;
475 uint32_t savePP_CYCLE;
476 uint32_t saveVGACNTRL;
477 uint32_t saveIER;
478 uint32_t saveIMR;
479 u8 saveLBB;
480};
481
c6265ff5
AC		 482struct psb_save_area {
483 uint32_t saveBSM;
484 uint32_t saveVBT;
485 union {
486 struct psb_state psb;
026abc33 487 struct medfield_state mdfld;
09016a11 488 struct cdv_state cdv;
c6265ff5
AC		 489 };
490 uint32_t saveBLC_PWM_CTL2;
491 uint32_t saveBLC_PWM_CTL;
492};
493
5c49fd3a
AC		 494struct psb_ops;
495
04bd564f
AC		 496#define PSB_NUM_PIPE 3
497
5c49fd3a
AC		 498struct drm_psb_private {
499 struct drm_device *dev;
500 const struct psb_ops *ops;
1fb28e9e
AC		 501
502 struct child_device_config *child_dev;
503 int child_dev_num;
5c49fd3a
AC		 504
505 struct psb_gtt gtt;
506
507 /* GTT Memory manager */
508 struct psb_gtt_mm *gtt_mm;
509 struct page *scratch_page;
eab37607 510 u32 __iomem *gtt_map;
5c49fd3a 511 uint32_t stolen_base;
37214ca0 512 u8 __iomem *vram_addr;
5c49fd3a
AC		 513 unsigned long vram_stolen_size;
514 int gtt_initialized;
515 u16 gmch_ctrl; /* Saved GTT setup */
516 u32 pge_ctl;
517
518 struct mutex gtt_mutex;
519 struct resource *gtt_mem; /* Our PCI resource */
520
521 struct psb_mmu_driver *mmu;
522 struct psb_mmu_pd *pf_pd;
523
524 /*
525 * Register base
526 */
527
846a6038
KS		 528 uint8_t __iomem *sgx_reg;
529 uint8_t __iomem *vdc_reg;
5c49fd3a
AC		 530 uint32_t gatt_free_offset;
531
532 /*
533 * Fencing / irq.
534 */
535
536 uint32_t vdc_irq_mask;
537 uint32_t pipestat[PSB_NUM_PIPE];
538
539 spinlock_t irqmask_lock;
540
541 /*
542 * Power
543 */
544
545 bool suspended;
546 bool display_power;
547 int display_count;
548
549 /*
550 * Modesetting
551 */
552 struct psb_intel_mode_device mode_dev;
553
554 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
555 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
556 uint32_t num_pipe;
557
558 /*
559 * OSPM info (Power management base) (can go ?)
560 */
561 uint32_t ospm_base;
562
563 /*
564 * Sizes info
565 */
566
5c49fd3a
AC		 567 u32 fuse_reg_value;
568 u32 video_device_fuse;
569
570 /* PCI revision ID for B0:D2:F0 */
571 uint8_t platform_rev_id;
572
5c0c1d50
PJ		 573 /* gmbus */
574 struct intel_gmbus *gmbus;
575
5736995b
PJ		 576 /* Used by SDVO */
577 int crt_ddc_pin;
578 /* FIXME: The mappings should be parsed from bios but for now we can
579 pretend there are no mappings available */
580 struct sdvo_device_mapping sdvo_mappings[2];
581 u32 hotplug_supported_mask;
582 struct drm_property *broadcast_rgb_property;
583 struct drm_property *force_audio_property;
584
5c49fd3a
AC		 585 /*
586 * LVDS info
587 */
588 int backlight_duty_cycle; /* restore backlight to this value */
589 bool panel_wants_dither;
590 struct drm_display_mode *panel_fixed_mode;
591 struct drm_display_mode *lfp_lvds_vbt_mode;
592 struct drm_display_mode *sdvo_lvds_vbt_mode;
593
594 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
a12d6a07 595 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
5c49fd3a
AC		 596
597 /* Feature bits from the VBIOS */
598 unsigned int int_tv_support:1;
599 unsigned int lvds_dither:1;
600 unsigned int lvds_vbt:1;
601 unsigned int int_crt_support:1;
602 unsigned int lvds_use_ssc:1;
603 int lvds_ssc_freq;
604 bool is_lvds_on;
605 bool is_mipi_on;
606 u32 mipi_ctrl_display;
607
608 unsigned int core_freq;
609 uint32_t iLVDS_enable;
610
611 /* Runtime PM state */
612 int rpm_enabled;
613
614 /* MID specific */
615 struct oaktrail_vbt vbt_data;
616 struct oaktrail_gct_data gct_data;
617
933315ac 618 /* Oaktrail HDMI state */
5c49fd3a 619 struct oaktrail_hdmi_dev *hdmi_priv;
933315ac 620
5c49fd3a
AC		 621 /*
622 * Register state
623 */
c6265ff5
AC		 624
625 struct psb_save_area regs;
626
5c49fd3a
AC		 627 /* MSI reg save */
628 uint32_t msi_addr;
629 uint32_t msi_data;
630
ae0a246a
AC		 631 /*
632 * Hotplug handling
633 */
634
635 struct work_struct hotplug_work;
5c49fd3a 636
5c49fd3a
AC		 637 /*
638 * LID-Switch
639 */
640 spinlock_t lid_lock;
641 struct timer_list lid_timer;
642 struct psb_intel_opregion opregion;
5c49fd3a
AC		 643 u32 lid_last_state;
644
645 /*
646 * Watchdog
647 */
648
649 uint32_t apm_reg;
650 uint16_t apm_base;
651
652 /*
653 * Used for modifying backlight from
654 * xrandr -- consider removing and using HAL instead
655 */
656 struct backlight_device *backlight_device;
657 struct drm_property *backlight_property;
658 uint32_t blc_adj1;
659 uint32_t blc_adj2;
660
661 void *fbdev;
662
663 /* 2D acceleration */
9242fe23 664 spinlock_t lock_2d;
026abc33
KS		 665
666 /*
667 * Panel brightness
668 */
669 int brightness;
670 int brightness_adjusted;
671
672 bool dsr_enable;
673 u32 dsr_fb_update;
674 bool dpi_panel_on[3];
675 void *dsi_configs[2];
676 u32 bpp;
677 u32 bpp2;
678
679 u32 pipeconf[3];
680 u32 dspcntr[3];
681
682 int mdfld_panel_id;
642c52fc
AC		 683
684 bool dplla_96mhz; /* DPLL data from the VBT */
5c49fd3a
AC		 685};
686
687
688/*
689 * Operations for each board type
690 */
691
692struct psb_ops {
693 const char *name;
694 unsigned int accel_2d:1;
695 int pipes; /* Number of output pipes */
696 int crtcs; /* Number of CRTCs */
697 int sgx_offset; /* Base offset of SGX device */
d235e64a
AC		 698 int hdmi_mask; /* Mask of HDMI CRTCs */
699 int lvds_mask; /* Mask of LVDS CRTCs */
5c49fd3a
AC		 700
701 /* Sub functions */
702 struct drm_crtc_helper_funcs const *crtc_helper;
703 struct drm_crtc_funcs const *crtc_funcs;
704
705 /* Setup hooks */
706 int (*chip_setup)(struct drm_device *dev);
707 void (*chip_teardown)(struct drm_device *dev);
d235e64a
AC		 708 /* Optional helper caller after modeset */
709 void (*errata)(struct drm_device *dev);
5c49fd3a
AC		 710
711 /* Display management hooks */
712 int (*output_init)(struct drm_device *dev);
68cb638f
AC		 713 int (*hotplug)(struct drm_device *dev);
714 void (*hotplug_enable)(struct drm_device *dev, bool on);
5c49fd3a
AC		 715 /* Power management hooks */
716 void (*init_pm)(struct drm_device *dev);
717 int (*save_regs)(struct drm_device *dev);
718 int (*restore_regs)(struct drm_device *dev);
719 int (*power_up)(struct drm_device *dev);
720 int (*power_down)(struct drm_device *dev);
721
722 void (*lvds_bl_power)(struct drm_device *dev, bool on);
723#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
724 /* Backlight */
725 int (*backlight_init)(struct drm_device *dev);
726#endif
727 int i2c_bus; /* I2C bus identifier for Moorestown */
728};
729
730
731
732struct psb_mmu_driver;
733
734extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
735extern int drm_pick_crtcs(struct drm_device *dev);
736
737static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
738{
739 return (struct drm_psb_private *) dev->dev_private;
740}
741
742/*
743 * MMU stuff.
744 */
745
746extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
747 int trap_pagefaults,
748 int invalid_type,
749 struct drm_psb_private *dev_priv);
750extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
751extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
752 *driver);
753extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
754 uint32_t gtt_start, uint32_t gtt_pages);
755extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
756 int trap_pagefaults,
757 int invalid_type);
758extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
759extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
760extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
761 unsigned long address,
762 uint32_t num_pages);
763extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
764 uint32_t start_pfn,
765 unsigned long address,
766 uint32_t num_pages, int type);
767extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
768 unsigned long *pfn);
769
770/*
771 * Enable / disable MMU for different requestors.
772 */
773
774
775extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
776extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
777 unsigned long address, uint32_t num_pages,
778 uint32_t desired_tile_stride,
779 uint32_t hw_tile_stride, int type);
780extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
781 unsigned long address, uint32_t num_pages,
782 uint32_t desired_tile_stride,
783 uint32_t hw_tile_stride);
784/*
785 *psb_irq.c
786 */
787
788extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
789extern int psb_irq_enable_dpst(struct drm_device *dev);
790extern int psb_irq_disable_dpst(struct drm_device *dev);
791extern void psb_irq_preinstall(struct drm_device *dev);
792extern int psb_irq_postinstall(struct drm_device *dev);
793extern void psb_irq_uninstall(struct drm_device *dev);
794extern void psb_irq_turn_on_dpst(struct drm_device *dev);
795extern void psb_irq_turn_off_dpst(struct drm_device *dev);
796
797extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
798extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
799extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
800extern int psb_enable_vblank(struct drm_device *dev, int crtc);
801extern void psb_disable_vblank(struct drm_device *dev, int crtc);
802void
803psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
804
805void
806psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
807
808extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
809
810/*
811 * intel_opregion.c
812 */
813extern int gma_intel_opregion_init(struct drm_device *dev);
814extern int gma_intel_opregion_exit(struct drm_device *dev);
815
816/*
817 * framebuffer.c
818 */
819extern int psbfb_probed(struct drm_device *dev);
820extern int psbfb_remove(struct drm_device *dev,
821 struct drm_framebuffer *fb);
822/*
823 * accel_2d.c
824 */
825extern void psbfb_copyarea(struct fb_info *info,
826 const struct fb_copyarea *region);
827extern int psbfb_sync(struct fb_info *info);
828extern void psb_spank(struct drm_psb_private *dev_priv);
829
830/*
831 * psb_reset.c
832 */
833
834extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
835extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
836extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
837
838/* modesetting */
839extern void psb_modeset_init(struct drm_device *dev);
840extern void psb_modeset_cleanup(struct drm_device *dev);
841extern int psb_fbdev_init(struct drm_device *dev);
842
843/* backlight.c */
844int gma_backlight_init(struct drm_device *dev);
845void gma_backlight_exit(struct drm_device *dev);
846
847/* oaktrail_crtc.c */
848extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
849
850/* oaktrail_lvds.c */
851extern void oaktrail_lvds_init(struct drm_device *dev,
852 struct psb_intel_mode_device *mode_dev);
853
854/* psb_intel_display.c */
855extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
856extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
857
858/* psb_intel_lvds.c */
859extern const struct drm_connector_helper_funcs
860 psb_intel_lvds_connector_helper_funcs;
861extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
862
863/* gem.c */
864extern int psb_gem_init_object(struct drm_gem_object *obj);
865extern void psb_gem_free_object(struct drm_gem_object *obj);
866extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
867 struct drm_file *file);
868extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
869 struct drm_mode_create_dumb *args);
870extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
871 uint32_t handle);
872extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
873 uint32_t handle, uint64_t *offset);
874extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
875extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
876 struct drm_file *file);
877extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
878 struct drm_file *file);
879
880/* psb_device.c */
881extern const struct psb_ops psb_chip_ops;
882
883/* oaktrail_device.c */
884extern const struct psb_ops oaktrail_chip_ops;
885
026abc33
KS		 886/* mdlfd_device.c */
887extern const struct psb_ops mdfld_chip_ops;
888
5c49fd3a
AC		 889/* cdv_device.c */
890extern const struct psb_ops cdv_chip_ops;
891
892/*
893 * Debug print bits setting
894 */
895#define PSB_D_GENERAL (1 << 0)
896#define PSB_D_INIT (1 << 1)
897#define PSB_D_IRQ (1 << 2)
898#define PSB_D_ENTRY (1 << 3)
899/* debug the get H/V BP/FP count */
900#define PSB_D_HV (1 << 4)
901#define PSB_D_DBI_BF (1 << 5)
902#define PSB_D_PM (1 << 6)
903#define PSB_D_RENDER (1 << 7)
904#define PSB_D_REG (1 << 8)
905#define PSB_D_MSVDX (1 << 9)
906#define PSB_D_TOPAZ (1 << 10)
907
908extern int drm_psb_no_fb;
909extern int drm_idle_check_interval;
910
911/*
912 * Utilities
913 */
914
915static inline u32 MRST_MSG_READ32(uint port, uint offset)
916{
917 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
918 uint32_t ret_val = 0;
919 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
920 pci_write_config_dword(pci_root, 0xD0, mcr);
921 pci_read_config_dword(pci_root, 0xD4, &ret_val);
922 pci_dev_put(pci_root);
923 return ret_val;
924}
925static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
926{
927 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
928 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
929 pci_write_config_dword(pci_root, 0xD4, value);
930 pci_write_config_dword(pci_root, 0xD0, mcr);
931 pci_dev_put(pci_root);
932}
933static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
934{
935 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
936 uint32_t ret_val = 0;
937 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
938 pci_write_config_dword(pci_root, 0xD0, mcr);
939 pci_read_config_dword(pci_root, 0xD4, &ret_val);
940 pci_dev_put(pci_root);
941 return ret_val;
942}
943static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
944{
945 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
946 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
947 pci_write_config_dword(pci_root, 0xD4, value);
948 pci_write_config_dword(pci_root, 0xD0, mcr);
949 pci_dev_put(pci_root);
950}
951
952static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
953{
954 struct drm_psb_private *dev_priv = dev->dev_private;
955 return ioread32(dev_priv->vdc_reg + reg);
956}
957
958#define REG_READ(reg) REGISTER_READ(dev, (reg))
959
960static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
961 uint32_t val)
962{
963 struct drm_psb_private *dev_priv = dev->dev_private;
964 iowrite32((val), dev_priv->vdc_reg + (reg));
965}
966
967#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
968
969static inline void REGISTER_WRITE16(struct drm_device *dev,
970 uint32_t reg, uint32_t val)
971{
972 struct drm_psb_private *dev_priv = dev->dev_private;
973 iowrite16((val), dev_priv->vdc_reg + (reg));
974}
975
976#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
977
978static inline void REGISTER_WRITE8(struct drm_device *dev,
979 uint32_t reg, uint32_t val)
980{
981 struct drm_psb_private *dev_priv = dev->dev_private;
982 iowrite8((val), dev_priv->vdc_reg + (reg));
983}
984
985#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
986
987#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
988#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
989
990/* #define TRAP_SGX_PM_FAULT 1 */
991#ifdef TRAP_SGX_PM_FAULT
992#define PSB_RSGX32(_offs) \
993({ \
994 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
995 printk(KERN_ERR \
996 "access sgx when it's off!! (READ) %s, %d\n", \
997 __FILE__, __LINE__); \
998 melay(1000); \
999 } \
1000 ioread32(dev_priv->sgx_reg + (_offs)); \
1001})
1002#else
1003#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
1004#endif
1005#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
1006
1007#define MSVDX_REG_DUMP 0
1008
1009#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1010#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
1011
1012#endif
Linux kernel - Deliverables
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