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gma500: clean up some of the struct fields we no longer use
[deliverable/linux.git] / drivers / gpu / drm / gma500 / psb_drv.h
CommitLineData
5c49fd3a
AC		 1/**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20#ifndef _PSB_DRV_H_
21#define _PSB_DRV_H_
22
23#include <linux/kref.h>
24
25#include <drm/drmP.h>
26#include "drm_global.h"
27#include "gem_glue.h"
838fa588 28#include "gma_drm.h"
5c49fd3a
AC		 29#include "psb_reg.h"
30#include "psb_intel_drv.h"
31#include "gtt.h"
32#include "power.h"
33#include "oaktrail.h"
34
35/* Append new drm mode definition here, align with libdrm definition */
36#define DRM_MODE_SCALE_NO_SCALE 2
37
38enum {
39 CHIP_PSB_8108 = 0, /* Poulsbo */
40 CHIP_PSB_8109 = 1, /* Poulsbo */
41 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
42 CHIP_MFLD_0130 = 3, /* Medfield */
43};
44
e036ba59 45#define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
5c49fd3a
AC		 46#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
47#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
48
49/*
50 * Driver definitions
51 */
52
53#define DRIVER_NAME "gma500"
54#define DRIVER_DESC "DRM driver for the Intel GMA500"
55
56#define PSB_DRM_DRIVER_DATE "2011-06-06"
57#define PSB_DRM_DRIVER_MAJOR 1
58#define PSB_DRM_DRIVER_MINOR 0
59#define PSB_DRM_DRIVER_PATCHLEVEL 0
60
61/*
62 * Hardware offsets
63 */
64#define PSB_VDC_OFFSET 0x00000000
65#define PSB_VDC_SIZE 0x000080000
66#define MRST_MMIO_SIZE 0x0000C0000
67#define MDFLD_MMIO_SIZE 0x000100000
68#define PSB_SGX_SIZE 0x8000
69#define PSB_SGX_OFFSET 0x00040000
70#define MRST_SGX_OFFSET 0x00080000
71/*
72 * PCI resource identifiers
73 */
74#define PSB_MMIO_RESOURCE 0
75#define PSB_GATT_RESOURCE 2
76#define PSB_GTT_RESOURCE 3
77/*
78 * PCI configuration
79 */
80#define PSB_GMCH_CTRL 0x52
81#define PSB_BSM 0x5C
82#define _PSB_GMCH_ENABLED 0x4
83#define PSB_PGETBL_CTL 0x2020
84#define _PSB_PGETBL_ENABLED 0x00000001
85#define PSB_SGX_2D_SLAVE_PORT 0x4000
86
87/* To get rid of */
88#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
89#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
90
91/*
92 * SGX side MMU definitions (these can probably go)
93 */
94
95/*
96 * Flags for external memory type field.
97 */
98#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
99#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
100#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
101/*
102 * PTE's and PDE's
103 */
104#define PSB_PDE_MASK 0x003FFFFF
105#define PSB_PDE_SHIFT 22
106#define PSB_PTE_SHIFT 12
107/*
108 * Cache control
109 */
110#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
111#define PSB_PTE_WO 0x0002 /* Write only */
112#define PSB_PTE_RO 0x0004 /* Read only */
113#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
114
115/*
116 * VDC registers and bits
117 */
118#define PSB_MSVDX_CLOCKGATING 0x2064
119#define PSB_TOPAZ_CLOCKGATING 0x2068
120#define PSB_HWSTAM 0x2098
121#define PSB_INSTPM 0x20C0
122#define PSB_INT_IDENTITY_R 0x20A4
123#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
124#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
125#define _PSB_DPST_PIPEB_FLAG (1<<4)
126#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
127#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
128#define _PSB_DPST_PIPEA_FLAG (1<<6)
129#define _PSB_PIPEA_EVENT_FLAG (1<<6)
130#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
131#define _MDFLD_MIPIA_FLAG (1<<16)
132#define _MDFLD_MIPIC_FLAG (1<<17)
133#define _PSB_IRQ_SGX_FLAG (1<<18)
134#define _PSB_IRQ_MSVDX_FLAG (1<<19)
135#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
136
700e59f6
PJ		 137#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
138 _PSB_VSYNC_PIPEB_FLAG)
139
5c49fd3a
AC		 140/* This flag includes all the display IRQ bits excepts the vblank irqs. */
141#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
142 _MDFLD_PIPEB_EVENT_FLAG | \
143 _PSB_PIPEA_EVENT_FLAG | \
144 _PSB_VSYNC_PIPEA_FLAG | \
145 _MDFLD_MIPIA_FLAG | \
146 _MDFLD_MIPIC_FLAG)
147#define PSB_INT_IDENTITY_R 0x20A4
148#define PSB_INT_MASK_R 0x20A8
149#define PSB_INT_ENABLE_R 0x20A0
150
151#define _PSB_MMU_ER_MASK 0x0001FF00
152#define _PSB_MMU_ER_HOST (1 << 16)
153#define GPIOA 0x5010
154#define GPIOB 0x5014
155#define GPIOC 0x5018
156#define GPIOD 0x501c
157#define GPIOE 0x5020
158#define GPIOF 0x5024
159#define GPIOG 0x5028
160#define GPIOH 0x502c
161#define GPIO_CLOCK_DIR_MASK (1 << 0)
162#define GPIO_CLOCK_DIR_IN (0 << 1)
163#define GPIO_CLOCK_DIR_OUT (1 << 1)
164#define GPIO_CLOCK_VAL_MASK (1 << 2)
165#define GPIO_CLOCK_VAL_OUT (1 << 3)
166#define GPIO_CLOCK_VAL_IN (1 << 4)
167#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
168#define GPIO_DATA_DIR_MASK (1 << 8)
169#define GPIO_DATA_DIR_IN (0 << 9)
170#define GPIO_DATA_DIR_OUT (1 << 9)
171#define GPIO_DATA_VAL_MASK (1 << 10)
172#define GPIO_DATA_VAL_OUT (1 << 11)
173#define GPIO_DATA_VAL_IN (1 << 12)
174#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
175
176#define VCLK_DIVISOR_VGA0 0x6000
177#define VCLK_DIVISOR_VGA1 0x6004
178#define VCLK_POST_DIV 0x6010
179
180#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
181#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
182#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
183#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
184#define PSB_COMM_USER_IRQ (1024 >> 2)
185#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
186#define PSB_COMM_FW (2048 >> 2)
187
188#define PSB_UIRQ_VISTEST 1
189#define PSB_UIRQ_OOM_REPLY 2
190#define PSB_UIRQ_FIRE_TA_REPLY 3
191#define PSB_UIRQ_FIRE_RASTER_REPLY 4
192
193#define PSB_2D_SIZE (256*1024*1024)
194#define PSB_MAX_RELOC_PAGES 1024
195
196#define PSB_LOW_REG_OFFS 0x0204
197#define PSB_HIGH_REG_OFFS 0x0600
198
199#define PSB_NUM_VBLANKS 2
200
201
202#define PSB_2D_SIZE (256*1024*1024)
203#define PSB_MAX_RELOC_PAGES 1024
204
205#define PSB_LOW_REG_OFFS 0x0204
206#define PSB_HIGH_REG_OFFS 0x0600
207
208#define PSB_NUM_VBLANKS 2
209#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
210#define PSB_LID_DELAY (DRM_HZ / 10)
211
212#define MDFLD_PNW_B0 0x04
213#define MDFLD_PNW_C0 0x08
214
215#define MDFLD_DSR_2D_3D_0 (1 << 0)
216#define MDFLD_DSR_2D_3D_2 (1 << 1)
217#define MDFLD_DSR_CURSOR_0 (1 << 2)
218#define MDFLD_DSR_CURSOR_2 (1 << 3)
219#define MDFLD_DSR_OVERLAY_0 (1 << 4)
220#define MDFLD_DSR_OVERLAY_2 (1 << 5)
221#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
222#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
223#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
224#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
225
226#define MDFLD_DSR_RR 45
227#define MDFLD_DPU_ENABLE (1 << 31)
228#define MDFLD_DSR_FULLSCREEN (1 << 30)
229#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
230
231#define PSB_PWR_STATE_ON 1
232#define PSB_PWR_STATE_OFF 2
233
234#define PSB_PMPOLICY_NOPM 0
235#define PSB_PMPOLICY_CLOCKGATING 1
236#define PSB_PMPOLICY_POWERDOWN 2
237
238#define PSB_PMSTATE_POWERUP 0
239#define PSB_PMSTATE_CLOCKGATED 1
240#define PSB_PMSTATE_POWERDOWN 2
241#define PSB_PCIx_MSI_ADDR_LOC 0x94
242#define PSB_PCIx_MSI_DATA_LOC 0x98
243
244/* Medfield crystal settings */
245#define KSEL_CRYSTAL_19 1
246#define KSEL_BYPASS_19 5
247#define KSEL_BYPASS_25 6
248#define KSEL_BYPASS_83_100 7
249
250struct opregion_header;
251struct opregion_acpi;
252struct opregion_swsci;
253struct opregion_asle;
254
255struct psb_intel_opregion {
256 struct opregion_header *header;
257 struct opregion_acpi *acpi;
258 struct opregion_swsci *swsci;
259 struct opregion_asle *asle;
260 int enabled;
261};
262
5736995b
PJ		 263struct sdvo_device_mapping {
264 u8 initialized;
265 u8 dvo_port;
266 u8 slave_addr;
267 u8 dvo_wiring;
268 u8 i2c_pin;
269 u8 i2c_speed;
270 u8 ddc_pin;
271};
272
5c0c1d50
PJ		 273struct intel_gmbus {
274 struct i2c_adapter adapter;
275 struct i2c_adapter *force_bit;
276 u32 reg0;
277};
278
5c49fd3a
AC		 279struct psb_ops;
280
04bd564f
AC		 281#define PSB_NUM_PIPE 3
282
5c49fd3a
AC		 283struct drm_psb_private {
284 struct drm_device *dev;
285 const struct psb_ops *ops;
286
287 struct psb_gtt gtt;
288
289 /* GTT Memory manager */
290 struct psb_gtt_mm *gtt_mm;
291 struct page *scratch_page;
292 u32 *gtt_map;
293 uint32_t stolen_base;
294 void *vram_addr;
295 unsigned long vram_stolen_size;
296 int gtt_initialized;
297 u16 gmch_ctrl; /* Saved GTT setup */
298 u32 pge_ctl;
299
300 struct mutex gtt_mutex;
301 struct resource *gtt_mem; /* Our PCI resource */
302
303 struct psb_mmu_driver *mmu;
304 struct psb_mmu_pd *pf_pd;
305
306 /*
307 * Register base
308 */
309
310 uint8_t *sgx_reg;
311 uint8_t *vdc_reg;
312 uint32_t gatt_free_offset;
313
314 /*
315 * Fencing / irq.
316 */
317
318 uint32_t vdc_irq_mask;
319 uint32_t pipestat[PSB_NUM_PIPE];
320
321 spinlock_t irqmask_lock;
322
323 /*
324 * Power
325 */
326
327 bool suspended;
328 bool display_power;
329 int display_count;
330
331 /*
332 * Modesetting
333 */
334 struct psb_intel_mode_device mode_dev;
335
336 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
337 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
338 uint32_t num_pipe;
339
340 /*
341 * OSPM info (Power management base) (can go ?)
342 */
343 uint32_t ospm_base;
344
345 /*
346 * Sizes info
347 */
348
5c49fd3a
AC		 349 u32 fuse_reg_value;
350 u32 video_device_fuse;
351
352 /* PCI revision ID for B0:D2:F0 */
353 uint8_t platform_rev_id;
354
5c0c1d50
PJ		 355 /* gmbus */
356 struct intel_gmbus *gmbus;
357
5736995b
PJ		 358 /* Used by SDVO */
359 int crt_ddc_pin;
360 /* FIXME: The mappings should be parsed from bios but for now we can
361 pretend there are no mappings available */
362 struct sdvo_device_mapping sdvo_mappings[2];
363 u32 hotplug_supported_mask;
364 struct drm_property *broadcast_rgb_property;
365 struct drm_property *force_audio_property;
366
5c49fd3a
AC		 367 /*
368 * LVDS info
369 */
370 int backlight_duty_cycle; /* restore backlight to this value */
371 bool panel_wants_dither;
372 struct drm_display_mode *panel_fixed_mode;
373 struct drm_display_mode *lfp_lvds_vbt_mode;
374 struct drm_display_mode *sdvo_lvds_vbt_mode;
375
376 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
a12d6a07 377 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
5c49fd3a
AC		 378
379 /* Feature bits from the VBIOS */
380 unsigned int int_tv_support:1;
381 unsigned int lvds_dither:1;
382 unsigned int lvds_vbt:1;
383 unsigned int int_crt_support:1;
384 unsigned int lvds_use_ssc:1;
385 int lvds_ssc_freq;
386 bool is_lvds_on;
387 bool is_mipi_on;
388 u32 mipi_ctrl_display;
389
390 unsigned int core_freq;
391 uint32_t iLVDS_enable;
392
393 /* Runtime PM state */
394 int rpm_enabled;
395
396 /* MID specific */
397 struct oaktrail_vbt vbt_data;
398 struct oaktrail_gct_data gct_data;
399
933315ac 400 /* Oaktrail HDMI state */
5c49fd3a 401 struct oaktrail_hdmi_dev *hdmi_priv;
933315ac 402
5c49fd3a
AC		 403 /*
404 * Register state
405 */
406 uint32_t saveDSPACNTR;
407 uint32_t saveDSPBCNTR;
408 uint32_t savePIPEACONF;
409 uint32_t savePIPEBCONF;
410 uint32_t savePIPEASRC;
411 uint32_t savePIPEBSRC;
412 uint32_t saveFPA0;
413 uint32_t saveFPA1;
414 uint32_t saveDPLL_A;
415 uint32_t saveDPLL_A_MD;
416 uint32_t saveHTOTAL_A;
417 uint32_t saveHBLANK_A;
418 uint32_t saveHSYNC_A;
419 uint32_t saveVTOTAL_A;
420 uint32_t saveVBLANK_A;
421 uint32_t saveVSYNC_A;
422 uint32_t saveDSPASTRIDE;
423 uint32_t saveDSPASIZE;
424 uint32_t saveDSPAPOS;
425 uint32_t saveDSPABASE;
426 uint32_t saveDSPASURF;
427 uint32_t saveDSPASTATUS;
428 uint32_t saveFPB0;
429 uint32_t saveFPB1;
430 uint32_t saveDPLL_B;
431 uint32_t saveDPLL_B_MD;
432 uint32_t saveHTOTAL_B;
433 uint32_t saveHBLANK_B;
434 uint32_t saveHSYNC_B;
435 uint32_t saveVTOTAL_B;
436 uint32_t saveVBLANK_B;
437 uint32_t saveVSYNC_B;
438 uint32_t saveDSPBSTRIDE;
439 uint32_t saveDSPBSIZE;
440 uint32_t saveDSPBPOS;
441 uint32_t saveDSPBBASE;
442 uint32_t saveDSPBSURF;
443 uint32_t saveDSPBSTATUS;
444 uint32_t saveVCLK_DIVISOR_VGA0;
445 uint32_t saveVCLK_DIVISOR_VGA1;
446 uint32_t saveVCLK_POST_DIV;
447 uint32_t saveVGACNTRL;
448 uint32_t saveADPA;
449 uint32_t saveLVDS;
450 uint32_t saveDVOA;
451 uint32_t saveDVOB;
452 uint32_t saveDVOC;
453 uint32_t savePP_ON;
454 uint32_t savePP_OFF;
455 uint32_t savePP_CONTROL;
456 uint32_t savePP_CYCLE;
457 uint32_t savePFIT_CONTROL;
458 uint32_t savePaletteA[256];
459 uint32_t savePaletteB[256];
460 uint32_t saveBLC_PWM_CTL2;
461 uint32_t saveBLC_PWM_CTL;
462 uint32_t saveCLOCKGATING;
463 uint32_t saveDSPARB;
464 uint32_t saveDSPATILEOFF;
465 uint32_t saveDSPBTILEOFF;
466 uint32_t saveDSPAADDR;
467 uint32_t saveDSPBADDR;
468 uint32_t savePFIT_AUTO_RATIOS;
469 uint32_t savePFIT_PGM_RATIOS;
470 uint32_t savePP_ON_DELAYS;
471 uint32_t savePP_OFF_DELAYS;
472 uint32_t savePP_DIVISOR;
473 uint32_t saveBSM;
474 uint32_t saveVBT;
475 uint32_t saveBCLRPAT_A;
476 uint32_t saveBCLRPAT_B;
477 uint32_t saveDSPALINOFF;
478 uint32_t saveDSPBLINOFF;
479 uint32_t savePERF_MODE;
480 uint32_t saveDSPFW1;
481 uint32_t saveDSPFW2;
482 uint32_t saveDSPFW3;
483 uint32_t saveDSPFW4;
484 uint32_t saveDSPFW5;
485 uint32_t saveDSPFW6;
486 uint32_t saveCHICKENBIT;
487 uint32_t saveDSPACURSOR_CTRL;
488 uint32_t saveDSPBCURSOR_CTRL;
489 uint32_t saveDSPACURSOR_BASE;
490 uint32_t saveDSPBCURSOR_BASE;
491 uint32_t saveDSPACURSOR_POS;
492 uint32_t saveDSPBCURSOR_POS;
493 uint32_t save_palette_a[256];
494 uint32_t save_palette_b[256];
495 uint32_t saveOV_OVADD;
496 uint32_t saveOV_OGAMC0;
497 uint32_t saveOV_OGAMC1;
498 uint32_t saveOV_OGAMC2;
499 uint32_t saveOV_OGAMC3;
500 uint32_t saveOV_OGAMC4;
501 uint32_t saveOV_OGAMC5;
502 uint32_t saveOVC_OVADD;
503 uint32_t saveOVC_OGAMC0;
504 uint32_t saveOVC_OGAMC1;
505 uint32_t saveOVC_OGAMC2;
506 uint32_t saveOVC_OGAMC3;
507 uint32_t saveOVC_OGAMC4;
508 uint32_t saveOVC_OGAMC5;
509
510 /* MSI reg save */
511 uint32_t msi_addr;
512 uint32_t msi_data;
513
5c49fd3a
AC		 514 /* DPST register save */
515 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
516 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
517 uint32_t savePWM_CONTROL_LOGIC;
518
5c49fd3a
AC		 519 /*
520 * LID-Switch
521 */
522 spinlock_t lid_lock;
523 struct timer_list lid_timer;
524 struct psb_intel_opregion opregion;
525 u32 *lid_state;
526 u32 lid_last_state;
527
528 /*
529 * Watchdog
530 */
531
532 uint32_t apm_reg;
533 uint16_t apm_base;
534
535 /*
536 * Used for modifying backlight from
537 * xrandr -- consider removing and using HAL instead
538 */
539 struct backlight_device *backlight_device;
540 struct drm_property *backlight_property;
541 uint32_t blc_adj1;
542 uint32_t blc_adj2;
543
544 void *fbdev;
545
546 /* 2D acceleration */
9242fe23 547 spinlock_t lock_2d;
5c49fd3a
AC		 548};
549
550
551/*
552 * Operations for each board type
553 */
554
555struct psb_ops {
556 const char *name;
557 unsigned int accel_2d:1;
558 int pipes; /* Number of output pipes */
559 int crtcs; /* Number of CRTCs */
560 int sgx_offset; /* Base offset of SGX device */
561
562 /* Sub functions */
563 struct drm_crtc_helper_funcs const *crtc_helper;
564 struct drm_crtc_funcs const *crtc_funcs;
565
566 /* Setup hooks */
567 int (*chip_setup)(struct drm_device *dev);
568 void (*chip_teardown)(struct drm_device *dev);
569
570 /* Display management hooks */
571 int (*output_init)(struct drm_device *dev);
572 /* Power management hooks */
573 void (*init_pm)(struct drm_device *dev);
574 int (*save_regs)(struct drm_device *dev);
575 int (*restore_regs)(struct drm_device *dev);
576 int (*power_up)(struct drm_device *dev);
577 int (*power_down)(struct drm_device *dev);
578
579 void (*lvds_bl_power)(struct drm_device *dev, bool on);
580#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
581 /* Backlight */
582 int (*backlight_init)(struct drm_device *dev);
583#endif
584 int i2c_bus; /* I2C bus identifier for Moorestown */
585};
586
587
588
589struct psb_mmu_driver;
590
591extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
592extern int drm_pick_crtcs(struct drm_device *dev);
593
594static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
595{
596 return (struct drm_psb_private *) dev->dev_private;
597}
598
599/*
600 * MMU stuff.
601 */
602
603extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
604 int trap_pagefaults,
605 int invalid_type,
606 struct drm_psb_private *dev_priv);
607extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
608extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
609 *driver);
610extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
611 uint32_t gtt_start, uint32_t gtt_pages);
612extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
613 int trap_pagefaults,
614 int invalid_type);
615extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
616extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
617extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
618 unsigned long address,
619 uint32_t num_pages);
620extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
621 uint32_t start_pfn,
622 unsigned long address,
623 uint32_t num_pages, int type);
624extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
625 unsigned long *pfn);
626
627/*
628 * Enable / disable MMU for different requestors.
629 */
630
631
632extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
633extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
634 unsigned long address, uint32_t num_pages,
635 uint32_t desired_tile_stride,
636 uint32_t hw_tile_stride, int type);
637extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
638 unsigned long address, uint32_t num_pages,
639 uint32_t desired_tile_stride,
640 uint32_t hw_tile_stride);
641/*
642 *psb_irq.c
643 */
644
645extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
646extern int psb_irq_enable_dpst(struct drm_device *dev);
647extern int psb_irq_disable_dpst(struct drm_device *dev);
648extern void psb_irq_preinstall(struct drm_device *dev);
649extern int psb_irq_postinstall(struct drm_device *dev);
650extern void psb_irq_uninstall(struct drm_device *dev);
651extern void psb_irq_turn_on_dpst(struct drm_device *dev);
652extern void psb_irq_turn_off_dpst(struct drm_device *dev);
653
654extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
655extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
656extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
657extern int psb_enable_vblank(struct drm_device *dev, int crtc);
658extern void psb_disable_vblank(struct drm_device *dev, int crtc);
659void
660psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
661
662void
663psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
664
665extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
666
667/*
668 * intel_opregion.c
669 */
670extern int gma_intel_opregion_init(struct drm_device *dev);
671extern int gma_intel_opregion_exit(struct drm_device *dev);
672
673/*
674 * framebuffer.c
675 */
676extern int psbfb_probed(struct drm_device *dev);
677extern int psbfb_remove(struct drm_device *dev,
678 struct drm_framebuffer *fb);
679/*
680 * accel_2d.c
681 */
682extern void psbfb_copyarea(struct fb_info *info,
683 const struct fb_copyarea *region);
684extern int psbfb_sync(struct fb_info *info);
685extern void psb_spank(struct drm_psb_private *dev_priv);
686
687/*
688 * psb_reset.c
689 */
690
691extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
692extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
693extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
694
695/* modesetting */
696extern void psb_modeset_init(struct drm_device *dev);
697extern void psb_modeset_cleanup(struct drm_device *dev);
698extern int psb_fbdev_init(struct drm_device *dev);
699
700/* backlight.c */
701int gma_backlight_init(struct drm_device *dev);
702void gma_backlight_exit(struct drm_device *dev);
703
704/* oaktrail_crtc.c */
705extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
706
707/* oaktrail_lvds.c */
708extern void oaktrail_lvds_init(struct drm_device *dev,
709 struct psb_intel_mode_device *mode_dev);
710
711/* psb_intel_display.c */
712extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
713extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
714
715/* psb_intel_lvds.c */
716extern const struct drm_connector_helper_funcs
717 psb_intel_lvds_connector_helper_funcs;
718extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
719
720/* gem.c */
721extern int psb_gem_init_object(struct drm_gem_object *obj);
722extern void psb_gem_free_object(struct drm_gem_object *obj);
723extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
724 struct drm_file *file);
725extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
726 struct drm_mode_create_dumb *args);
727extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
728 uint32_t handle);
729extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
730 uint32_t handle, uint64_t *offset);
731extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
732extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
733 struct drm_file *file);
734extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
735 struct drm_file *file);
736
737/* psb_device.c */
738extern const struct psb_ops psb_chip_ops;
739
740/* oaktrail_device.c */
741extern const struct psb_ops oaktrail_chip_ops;
742
743/* cdv_device.c */
744extern const struct psb_ops cdv_chip_ops;
745
746/*
747 * Debug print bits setting
748 */
749#define PSB_D_GENERAL (1 << 0)
750#define PSB_D_INIT (1 << 1)
751#define PSB_D_IRQ (1 << 2)
752#define PSB_D_ENTRY (1 << 3)
753/* debug the get H/V BP/FP count */
754#define PSB_D_HV (1 << 4)
755#define PSB_D_DBI_BF (1 << 5)
756#define PSB_D_PM (1 << 6)
757#define PSB_D_RENDER (1 << 7)
758#define PSB_D_REG (1 << 8)
759#define PSB_D_MSVDX (1 << 9)
760#define PSB_D_TOPAZ (1 << 10)
761
762extern int drm_psb_no_fb;
763extern int drm_idle_check_interval;
764
765/*
766 * Utilities
767 */
768
769static inline u32 MRST_MSG_READ32(uint port, uint offset)
770{
771 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
772 uint32_t ret_val = 0;
773 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
774 pci_write_config_dword(pci_root, 0xD0, mcr);
775 pci_read_config_dword(pci_root, 0xD4, &ret_val);
776 pci_dev_put(pci_root);
777 return ret_val;
778}
779static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
780{
781 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
782 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
783 pci_write_config_dword(pci_root, 0xD4, value);
784 pci_write_config_dword(pci_root, 0xD0, mcr);
785 pci_dev_put(pci_root);
786}
787static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
788{
789 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
790 uint32_t ret_val = 0;
791 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
792 pci_write_config_dword(pci_root, 0xD0, mcr);
793 pci_read_config_dword(pci_root, 0xD4, &ret_val);
794 pci_dev_put(pci_root);
795 return ret_val;
796}
797static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
798{
799 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
800 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
801 pci_write_config_dword(pci_root, 0xD4, value);
802 pci_write_config_dword(pci_root, 0xD0, mcr);
803 pci_dev_put(pci_root);
804}
805
806static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
807{
808 struct drm_psb_private *dev_priv = dev->dev_private;
809 return ioread32(dev_priv->vdc_reg + reg);
810}
811
812#define REG_READ(reg) REGISTER_READ(dev, (reg))
813
814static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
815 uint32_t val)
816{
817 struct drm_psb_private *dev_priv = dev->dev_private;
818 iowrite32((val), dev_priv->vdc_reg + (reg));
819}
820
821#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
822
823static inline void REGISTER_WRITE16(struct drm_device *dev,
824 uint32_t reg, uint32_t val)
825{
826 struct drm_psb_private *dev_priv = dev->dev_private;
827 iowrite16((val), dev_priv->vdc_reg + (reg));
828}
829
830#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
831
832static inline void REGISTER_WRITE8(struct drm_device *dev,
833 uint32_t reg, uint32_t val)
834{
835 struct drm_psb_private *dev_priv = dev->dev_private;
836 iowrite8((val), dev_priv->vdc_reg + (reg));
837}
838
839#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
840
841#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
842#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
843
844/* #define TRAP_SGX_PM_FAULT 1 */
845#ifdef TRAP_SGX_PM_FAULT
846#define PSB_RSGX32(_offs) \
847({ \
848 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
849 printk(KERN_ERR \
850 "access sgx when it's off!! (READ) %s, %d\n", \
851 __FILE__, __LINE__); \
852 melay(1000); \
853 } \
854 ioread32(dev_priv->sgx_reg + (_offs)); \
855})
856#else
857#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
858#endif
859#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
860
861#define MSVDX_REG_DUMP 0
862
863#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
864#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
865
866#endif
Linux kernel - Deliverables
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