Commit | Line | Data |
---|---|---|
5c49fd3a AC |
1 | /************************************************************************** |
2 | * Copyright (c) 2007-2011, Intel Corporation. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | **************************************************************************/ | |
19 | ||
20 | #ifndef _PSB_DRV_H_ | |
21 | #define _PSB_DRV_H_ | |
22 | ||
23 | #include <linux/kref.h> | |
24 | ||
25 | #include <drm/drmP.h> | |
26 | #include "drm_global.h" | |
27 | #include "gem_glue.h" | |
838fa588 | 28 | #include "gma_drm.h" |
5c49fd3a AC |
29 | #include "psb_reg.h" |
30 | #include "psb_intel_drv.h" | |
31 | #include "gtt.h" | |
32 | #include "power.h" | |
33 | #include "oaktrail.h" | |
34 | ||
35 | /* Append new drm mode definition here, align with libdrm definition */ | |
36 | #define DRM_MODE_SCALE_NO_SCALE 2 | |
37 | ||
38 | enum { | |
39 | CHIP_PSB_8108 = 0, /* Poulsbo */ | |
40 | CHIP_PSB_8109 = 1, /* Poulsbo */ | |
41 | CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */ | |
42 | CHIP_MFLD_0130 = 3, /* Medfield */ | |
43 | }; | |
44 | ||
e036ba59 | 45 | #define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108) |
5c49fd3a AC |
46 | #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100) |
47 | #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130) | |
48 | ||
49 | /* | |
50 | * Driver definitions | |
51 | */ | |
52 | ||
53 | #define DRIVER_NAME "gma500" | |
54 | #define DRIVER_DESC "DRM driver for the Intel GMA500" | |
55 | ||
56 | #define PSB_DRM_DRIVER_DATE "2011-06-06" | |
57 | #define PSB_DRM_DRIVER_MAJOR 1 | |
58 | #define PSB_DRM_DRIVER_MINOR 0 | |
59 | #define PSB_DRM_DRIVER_PATCHLEVEL 0 | |
60 | ||
61 | /* | |
62 | * Hardware offsets | |
63 | */ | |
64 | #define PSB_VDC_OFFSET 0x00000000 | |
65 | #define PSB_VDC_SIZE 0x000080000 | |
66 | #define MRST_MMIO_SIZE 0x0000C0000 | |
67 | #define MDFLD_MMIO_SIZE 0x000100000 | |
68 | #define PSB_SGX_SIZE 0x8000 | |
69 | #define PSB_SGX_OFFSET 0x00040000 | |
70 | #define MRST_SGX_OFFSET 0x00080000 | |
71 | /* | |
72 | * PCI resource identifiers | |
73 | */ | |
74 | #define PSB_MMIO_RESOURCE 0 | |
75 | #define PSB_GATT_RESOURCE 2 | |
76 | #define PSB_GTT_RESOURCE 3 | |
77 | /* | |
78 | * PCI configuration | |
79 | */ | |
80 | #define PSB_GMCH_CTRL 0x52 | |
81 | #define PSB_BSM 0x5C | |
82 | #define _PSB_GMCH_ENABLED 0x4 | |
83 | #define PSB_PGETBL_CTL 0x2020 | |
84 | #define _PSB_PGETBL_ENABLED 0x00000001 | |
85 | #define PSB_SGX_2D_SLAVE_PORT 0x4000 | |
86 | ||
87 | /* To get rid of */ | |
88 | #define PSB_TT_PRIV0_LIMIT (256*1024*1024) | |
89 | #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT) | |
90 | ||
91 | /* | |
92 | * SGX side MMU definitions (these can probably go) | |
93 | */ | |
94 | ||
95 | /* | |
96 | * Flags for external memory type field. | |
97 | */ | |
98 | #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */ | |
99 | #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */ | |
100 | #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */ | |
101 | /* | |
102 | * PTE's and PDE's | |
103 | */ | |
104 | #define PSB_PDE_MASK 0x003FFFFF | |
105 | #define PSB_PDE_SHIFT 22 | |
106 | #define PSB_PTE_SHIFT 12 | |
107 | /* | |
108 | * Cache control | |
109 | */ | |
110 | #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */ | |
111 | #define PSB_PTE_WO 0x0002 /* Write only */ | |
112 | #define PSB_PTE_RO 0x0004 /* Read only */ | |
113 | #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */ | |
114 | ||
115 | /* | |
116 | * VDC registers and bits | |
117 | */ | |
118 | #define PSB_MSVDX_CLOCKGATING 0x2064 | |
119 | #define PSB_TOPAZ_CLOCKGATING 0x2068 | |
120 | #define PSB_HWSTAM 0x2098 | |
121 | #define PSB_INSTPM 0x20C0 | |
122 | #define PSB_INT_IDENTITY_R 0x20A4 | |
123 | #define _MDFLD_PIPEC_EVENT_FLAG (1<<2) | |
124 | #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3) | |
125 | #define _PSB_DPST_PIPEB_FLAG (1<<4) | |
126 | #define _MDFLD_PIPEB_EVENT_FLAG (1<<4) | |
127 | #define _PSB_VSYNC_PIPEB_FLAG (1<<5) | |
128 | #define _PSB_DPST_PIPEA_FLAG (1<<6) | |
129 | #define _PSB_PIPEA_EVENT_FLAG (1<<6) | |
130 | #define _PSB_VSYNC_PIPEA_FLAG (1<<7) | |
131 | #define _MDFLD_MIPIA_FLAG (1<<16) | |
132 | #define _MDFLD_MIPIC_FLAG (1<<17) | |
133 | #define _PSB_IRQ_SGX_FLAG (1<<18) | |
134 | #define _PSB_IRQ_MSVDX_FLAG (1<<19) | |
135 | #define _LNC_IRQ_TOPAZ_FLAG (1<<20) | |
136 | ||
700e59f6 PJ |
137 | #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \ |
138 | _PSB_VSYNC_PIPEB_FLAG) | |
139 | ||
5c49fd3a AC |
140 | /* This flag includes all the display IRQ bits excepts the vblank irqs. */ |
141 | #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \ | |
142 | _MDFLD_PIPEB_EVENT_FLAG | \ | |
143 | _PSB_PIPEA_EVENT_FLAG | \ | |
144 | _PSB_VSYNC_PIPEA_FLAG | \ | |
145 | _MDFLD_MIPIA_FLAG | \ | |
146 | _MDFLD_MIPIC_FLAG) | |
147 | #define PSB_INT_IDENTITY_R 0x20A4 | |
148 | #define PSB_INT_MASK_R 0x20A8 | |
149 | #define PSB_INT_ENABLE_R 0x20A0 | |
150 | ||
151 | #define _PSB_MMU_ER_MASK 0x0001FF00 | |
152 | #define _PSB_MMU_ER_HOST (1 << 16) | |
153 | #define GPIOA 0x5010 | |
154 | #define GPIOB 0x5014 | |
155 | #define GPIOC 0x5018 | |
156 | #define GPIOD 0x501c | |
157 | #define GPIOE 0x5020 | |
158 | #define GPIOF 0x5024 | |
159 | #define GPIOG 0x5028 | |
160 | #define GPIOH 0x502c | |
161 | #define GPIO_CLOCK_DIR_MASK (1 << 0) | |
162 | #define GPIO_CLOCK_DIR_IN (0 << 1) | |
163 | #define GPIO_CLOCK_DIR_OUT (1 << 1) | |
164 | #define GPIO_CLOCK_VAL_MASK (1 << 2) | |
165 | #define GPIO_CLOCK_VAL_OUT (1 << 3) | |
166 | #define GPIO_CLOCK_VAL_IN (1 << 4) | |
167 | #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) | |
168 | #define GPIO_DATA_DIR_MASK (1 << 8) | |
169 | #define GPIO_DATA_DIR_IN (0 << 9) | |
170 | #define GPIO_DATA_DIR_OUT (1 << 9) | |
171 | #define GPIO_DATA_VAL_MASK (1 << 10) | |
172 | #define GPIO_DATA_VAL_OUT (1 << 11) | |
173 | #define GPIO_DATA_VAL_IN (1 << 12) | |
174 | #define GPIO_DATA_PULLUP_DISABLE (1 << 13) | |
175 | ||
176 | #define VCLK_DIVISOR_VGA0 0x6000 | |
177 | #define VCLK_DIVISOR_VGA1 0x6004 | |
178 | #define VCLK_POST_DIV 0x6010 | |
179 | ||
180 | #define PSB_COMM_2D (PSB_ENGINE_2D << 4) | |
181 | #define PSB_COMM_3D (PSB_ENGINE_3D << 4) | |
182 | #define PSB_COMM_TA (PSB_ENGINE_TA << 4) | |
183 | #define PSB_COMM_HP (PSB_ENGINE_HP << 4) | |
184 | #define PSB_COMM_USER_IRQ (1024 >> 2) | |
185 | #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1) | |
186 | #define PSB_COMM_FW (2048 >> 2) | |
187 | ||
188 | #define PSB_UIRQ_VISTEST 1 | |
189 | #define PSB_UIRQ_OOM_REPLY 2 | |
190 | #define PSB_UIRQ_FIRE_TA_REPLY 3 | |
191 | #define PSB_UIRQ_FIRE_RASTER_REPLY 4 | |
192 | ||
193 | #define PSB_2D_SIZE (256*1024*1024) | |
194 | #define PSB_MAX_RELOC_PAGES 1024 | |
195 | ||
196 | #define PSB_LOW_REG_OFFS 0x0204 | |
197 | #define PSB_HIGH_REG_OFFS 0x0600 | |
198 | ||
199 | #define PSB_NUM_VBLANKS 2 | |
200 | ||
201 | ||
202 | #define PSB_2D_SIZE (256*1024*1024) | |
203 | #define PSB_MAX_RELOC_PAGES 1024 | |
204 | ||
205 | #define PSB_LOW_REG_OFFS 0x0204 | |
206 | #define PSB_HIGH_REG_OFFS 0x0600 | |
207 | ||
208 | #define PSB_NUM_VBLANKS 2 | |
209 | #define PSB_WATCHDOG_DELAY (DRM_HZ * 2) | |
210 | #define PSB_LID_DELAY (DRM_HZ / 10) | |
211 | ||
212 | #define MDFLD_PNW_B0 0x04 | |
213 | #define MDFLD_PNW_C0 0x08 | |
214 | ||
215 | #define MDFLD_DSR_2D_3D_0 (1 << 0) | |
216 | #define MDFLD_DSR_2D_3D_2 (1 << 1) | |
217 | #define MDFLD_DSR_CURSOR_0 (1 << 2) | |
218 | #define MDFLD_DSR_CURSOR_2 (1 << 3) | |
219 | #define MDFLD_DSR_OVERLAY_0 (1 << 4) | |
220 | #define MDFLD_DSR_OVERLAY_2 (1 << 5) | |
221 | #define MDFLD_DSR_MIPI_CONTROL (1 << 6) | |
222 | #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4)) | |
223 | #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5)) | |
224 | #define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2) | |
225 | ||
226 | #define MDFLD_DSR_RR 45 | |
227 | #define MDFLD_DPU_ENABLE (1 << 31) | |
228 | #define MDFLD_DSR_FULLSCREEN (1 << 30) | |
229 | #define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR) | |
230 | ||
231 | #define PSB_PWR_STATE_ON 1 | |
232 | #define PSB_PWR_STATE_OFF 2 | |
233 | ||
234 | #define PSB_PMPOLICY_NOPM 0 | |
235 | #define PSB_PMPOLICY_CLOCKGATING 1 | |
236 | #define PSB_PMPOLICY_POWERDOWN 2 | |
237 | ||
238 | #define PSB_PMSTATE_POWERUP 0 | |
239 | #define PSB_PMSTATE_CLOCKGATED 1 | |
240 | #define PSB_PMSTATE_POWERDOWN 2 | |
241 | #define PSB_PCIx_MSI_ADDR_LOC 0x94 | |
242 | #define PSB_PCIx_MSI_DATA_LOC 0x98 | |
243 | ||
244 | /* Medfield crystal settings */ | |
245 | #define KSEL_CRYSTAL_19 1 | |
246 | #define KSEL_BYPASS_19 5 | |
247 | #define KSEL_BYPASS_25 6 | |
248 | #define KSEL_BYPASS_83_100 7 | |
249 | ||
250 | struct opregion_header; | |
251 | struct opregion_acpi; | |
252 | struct opregion_swsci; | |
253 | struct opregion_asle; | |
254 | ||
255 | struct psb_intel_opregion { | |
256 | struct opregion_header *header; | |
257 | struct opregion_acpi *acpi; | |
258 | struct opregion_swsci *swsci; | |
259 | struct opregion_asle *asle; | |
260 | int enabled; | |
261 | }; | |
262 | ||
263 | struct psb_ops; | |
264 | ||
04bd564f AC |
265 | #define PSB_NUM_PIPE 3 |
266 | ||
5c49fd3a AC |
267 | struct drm_psb_private { |
268 | struct drm_device *dev; | |
269 | const struct psb_ops *ops; | |
270 | ||
271 | struct psb_gtt gtt; | |
272 | ||
273 | /* GTT Memory manager */ | |
274 | struct psb_gtt_mm *gtt_mm; | |
275 | struct page *scratch_page; | |
276 | u32 *gtt_map; | |
277 | uint32_t stolen_base; | |
278 | void *vram_addr; | |
279 | unsigned long vram_stolen_size; | |
280 | int gtt_initialized; | |
281 | u16 gmch_ctrl; /* Saved GTT setup */ | |
282 | u32 pge_ctl; | |
283 | ||
284 | struct mutex gtt_mutex; | |
285 | struct resource *gtt_mem; /* Our PCI resource */ | |
286 | ||
287 | struct psb_mmu_driver *mmu; | |
288 | struct psb_mmu_pd *pf_pd; | |
289 | ||
290 | /* | |
291 | * Register base | |
292 | */ | |
293 | ||
294 | uint8_t *sgx_reg; | |
295 | uint8_t *vdc_reg; | |
296 | uint32_t gatt_free_offset; | |
297 | ||
298 | /* | |
299 | * Fencing / irq. | |
300 | */ | |
301 | ||
302 | uint32_t vdc_irq_mask; | |
303 | uint32_t pipestat[PSB_NUM_PIPE]; | |
304 | ||
305 | spinlock_t irqmask_lock; | |
306 | ||
307 | /* | |
308 | * Power | |
309 | */ | |
310 | ||
311 | bool suspended; | |
312 | bool display_power; | |
313 | int display_count; | |
314 | ||
315 | /* | |
316 | * Modesetting | |
317 | */ | |
318 | struct psb_intel_mode_device mode_dev; | |
319 | ||
320 | struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE]; | |
321 | struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE]; | |
322 | uint32_t num_pipe; | |
323 | ||
324 | /* | |
325 | * OSPM info (Power management base) (can go ?) | |
326 | */ | |
327 | uint32_t ospm_base; | |
328 | ||
329 | /* | |
330 | * Sizes info | |
331 | */ | |
332 | ||
5c49fd3a AC |
333 | u32 fuse_reg_value; |
334 | u32 video_device_fuse; | |
335 | ||
336 | /* PCI revision ID for B0:D2:F0 */ | |
337 | uint8_t platform_rev_id; | |
338 | ||
339 | /* | |
340 | * LVDS info | |
341 | */ | |
342 | int backlight_duty_cycle; /* restore backlight to this value */ | |
343 | bool panel_wants_dither; | |
344 | struct drm_display_mode *panel_fixed_mode; | |
345 | struct drm_display_mode *lfp_lvds_vbt_mode; | |
346 | struct drm_display_mode *sdvo_lvds_vbt_mode; | |
347 | ||
348 | struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */ | |
349 | struct psb_intel_i2c_chan *lvds_i2c_bus; | |
350 | ||
351 | /* Feature bits from the VBIOS */ | |
352 | unsigned int int_tv_support:1; | |
353 | unsigned int lvds_dither:1; | |
354 | unsigned int lvds_vbt:1; | |
355 | unsigned int int_crt_support:1; | |
356 | unsigned int lvds_use_ssc:1; | |
357 | int lvds_ssc_freq; | |
358 | bool is_lvds_on; | |
359 | bool is_mipi_on; | |
360 | u32 mipi_ctrl_display; | |
361 | ||
362 | unsigned int core_freq; | |
363 | uint32_t iLVDS_enable; | |
364 | ||
365 | /* Runtime PM state */ | |
366 | int rpm_enabled; | |
367 | ||
368 | /* MID specific */ | |
369 | struct oaktrail_vbt vbt_data; | |
370 | struct oaktrail_gct_data gct_data; | |
371 | ||
372 | /* MIPI Panel type etc */ | |
373 | int panel_id; | |
374 | bool dual_mipi; /* dual display - DPI & DBI */ | |
375 | bool dpi_panel_on; /* The DPI panel power is on */ | |
376 | bool dpi_panel_on2; /* The DPI panel power is on */ | |
377 | bool dbi_panel_on; /* The DBI panel power is on */ | |
378 | bool dbi_panel_on2; /* The DBI panel power is on */ | |
379 | u32 dsr_fb_update; /* DSR FB update counter */ | |
380 | ||
381 | /* Moorestown HDMI state */ | |
382 | struct oaktrail_hdmi_dev *hdmi_priv; | |
383 | ||
384 | /* Moorestown pipe config register value cache */ | |
385 | uint32_t pipeconf; | |
386 | uint32_t pipeconf1; | |
387 | uint32_t pipeconf2; | |
388 | ||
389 | /* Moorestown plane control register value cache */ | |
390 | uint32_t dspcntr; | |
391 | uint32_t dspcntr1; | |
392 | uint32_t dspcntr2; | |
393 | ||
394 | /* Moorestown MM backlight cache */ | |
395 | uint8_t saveBKLTCNT; | |
396 | uint8_t saveBKLTREQ; | |
397 | uint8_t saveBKLTBRTL; | |
398 | ||
399 | /* | |
400 | * Register state | |
401 | */ | |
402 | uint32_t saveDSPACNTR; | |
403 | uint32_t saveDSPBCNTR; | |
404 | uint32_t savePIPEACONF; | |
405 | uint32_t savePIPEBCONF; | |
406 | uint32_t savePIPEASRC; | |
407 | uint32_t savePIPEBSRC; | |
408 | uint32_t saveFPA0; | |
409 | uint32_t saveFPA1; | |
410 | uint32_t saveDPLL_A; | |
411 | uint32_t saveDPLL_A_MD; | |
412 | uint32_t saveHTOTAL_A; | |
413 | uint32_t saveHBLANK_A; | |
414 | uint32_t saveHSYNC_A; | |
415 | uint32_t saveVTOTAL_A; | |
416 | uint32_t saveVBLANK_A; | |
417 | uint32_t saveVSYNC_A; | |
418 | uint32_t saveDSPASTRIDE; | |
419 | uint32_t saveDSPASIZE; | |
420 | uint32_t saveDSPAPOS; | |
421 | uint32_t saveDSPABASE; | |
422 | uint32_t saveDSPASURF; | |
423 | uint32_t saveDSPASTATUS; | |
424 | uint32_t saveFPB0; | |
425 | uint32_t saveFPB1; | |
426 | uint32_t saveDPLL_B; | |
427 | uint32_t saveDPLL_B_MD; | |
428 | uint32_t saveHTOTAL_B; | |
429 | uint32_t saveHBLANK_B; | |
430 | uint32_t saveHSYNC_B; | |
431 | uint32_t saveVTOTAL_B; | |
432 | uint32_t saveVBLANK_B; | |
433 | uint32_t saveVSYNC_B; | |
434 | uint32_t saveDSPBSTRIDE; | |
435 | uint32_t saveDSPBSIZE; | |
436 | uint32_t saveDSPBPOS; | |
437 | uint32_t saveDSPBBASE; | |
438 | uint32_t saveDSPBSURF; | |
439 | uint32_t saveDSPBSTATUS; | |
440 | uint32_t saveVCLK_DIVISOR_VGA0; | |
441 | uint32_t saveVCLK_DIVISOR_VGA1; | |
442 | uint32_t saveVCLK_POST_DIV; | |
443 | uint32_t saveVGACNTRL; | |
444 | uint32_t saveADPA; | |
445 | uint32_t saveLVDS; | |
446 | uint32_t saveDVOA; | |
447 | uint32_t saveDVOB; | |
448 | uint32_t saveDVOC; | |
449 | uint32_t savePP_ON; | |
450 | uint32_t savePP_OFF; | |
451 | uint32_t savePP_CONTROL; | |
452 | uint32_t savePP_CYCLE; | |
453 | uint32_t savePFIT_CONTROL; | |
454 | uint32_t savePaletteA[256]; | |
455 | uint32_t savePaletteB[256]; | |
456 | uint32_t saveBLC_PWM_CTL2; | |
457 | uint32_t saveBLC_PWM_CTL; | |
458 | uint32_t saveCLOCKGATING; | |
459 | uint32_t saveDSPARB; | |
460 | uint32_t saveDSPATILEOFF; | |
461 | uint32_t saveDSPBTILEOFF; | |
462 | uint32_t saveDSPAADDR; | |
463 | uint32_t saveDSPBADDR; | |
464 | uint32_t savePFIT_AUTO_RATIOS; | |
465 | uint32_t savePFIT_PGM_RATIOS; | |
466 | uint32_t savePP_ON_DELAYS; | |
467 | uint32_t savePP_OFF_DELAYS; | |
468 | uint32_t savePP_DIVISOR; | |
469 | uint32_t saveBSM; | |
470 | uint32_t saveVBT; | |
471 | uint32_t saveBCLRPAT_A; | |
472 | uint32_t saveBCLRPAT_B; | |
473 | uint32_t saveDSPALINOFF; | |
474 | uint32_t saveDSPBLINOFF; | |
475 | uint32_t savePERF_MODE; | |
476 | uint32_t saveDSPFW1; | |
477 | uint32_t saveDSPFW2; | |
478 | uint32_t saveDSPFW3; | |
479 | uint32_t saveDSPFW4; | |
480 | uint32_t saveDSPFW5; | |
481 | uint32_t saveDSPFW6; | |
482 | uint32_t saveCHICKENBIT; | |
483 | uint32_t saveDSPACURSOR_CTRL; | |
484 | uint32_t saveDSPBCURSOR_CTRL; | |
485 | uint32_t saveDSPACURSOR_BASE; | |
486 | uint32_t saveDSPBCURSOR_BASE; | |
487 | uint32_t saveDSPACURSOR_POS; | |
488 | uint32_t saveDSPBCURSOR_POS; | |
489 | uint32_t save_palette_a[256]; | |
490 | uint32_t save_palette_b[256]; | |
491 | uint32_t saveOV_OVADD; | |
492 | uint32_t saveOV_OGAMC0; | |
493 | uint32_t saveOV_OGAMC1; | |
494 | uint32_t saveOV_OGAMC2; | |
495 | uint32_t saveOV_OGAMC3; | |
496 | uint32_t saveOV_OGAMC4; | |
497 | uint32_t saveOV_OGAMC5; | |
498 | uint32_t saveOVC_OVADD; | |
499 | uint32_t saveOVC_OGAMC0; | |
500 | uint32_t saveOVC_OGAMC1; | |
501 | uint32_t saveOVC_OGAMC2; | |
502 | uint32_t saveOVC_OGAMC3; | |
503 | uint32_t saveOVC_OGAMC4; | |
504 | uint32_t saveOVC_OGAMC5; | |
505 | ||
506 | /* MSI reg save */ | |
507 | uint32_t msi_addr; | |
508 | uint32_t msi_data; | |
509 | ||
510 | /* Medfield specific register save state */ | |
511 | uint32_t saveHDMIPHYMISCCTL; | |
512 | uint32_t saveHDMIB_CONTROL; | |
513 | uint32_t saveDSPCCNTR; | |
514 | uint32_t savePIPECCONF; | |
515 | uint32_t savePIPECSRC; | |
516 | uint32_t saveHTOTAL_C; | |
517 | uint32_t saveHBLANK_C; | |
518 | uint32_t saveHSYNC_C; | |
519 | uint32_t saveVTOTAL_C; | |
520 | uint32_t saveVBLANK_C; | |
521 | uint32_t saveVSYNC_C; | |
522 | uint32_t saveDSPCSTRIDE; | |
523 | uint32_t saveDSPCSIZE; | |
524 | uint32_t saveDSPCPOS; | |
525 | uint32_t saveDSPCSURF; | |
526 | uint32_t saveDSPCSTATUS; | |
527 | uint32_t saveDSPCLINOFF; | |
528 | uint32_t saveDSPCTILEOFF; | |
529 | uint32_t saveDSPCCURSOR_CTRL; | |
530 | uint32_t saveDSPCCURSOR_BASE; | |
531 | uint32_t saveDSPCCURSOR_POS; | |
532 | uint32_t save_palette_c[256]; | |
533 | uint32_t saveOV_OVADD_C; | |
534 | uint32_t saveOV_OGAMC0_C; | |
535 | uint32_t saveOV_OGAMC1_C; | |
536 | uint32_t saveOV_OGAMC2_C; | |
537 | uint32_t saveOV_OGAMC3_C; | |
538 | uint32_t saveOV_OGAMC4_C; | |
539 | uint32_t saveOV_OGAMC5_C; | |
540 | ||
541 | /* DSI register save */ | |
542 | uint32_t saveDEVICE_READY_REG; | |
543 | uint32_t saveINTR_EN_REG; | |
544 | uint32_t saveDSI_FUNC_PRG_REG; | |
545 | uint32_t saveHS_TX_TIMEOUT_REG; | |
546 | uint32_t saveLP_RX_TIMEOUT_REG; | |
547 | uint32_t saveTURN_AROUND_TIMEOUT_REG; | |
548 | uint32_t saveDEVICE_RESET_REG; | |
549 | uint32_t saveDPI_RESOLUTION_REG; | |
550 | uint32_t saveHORIZ_SYNC_PAD_COUNT_REG; | |
551 | uint32_t saveHORIZ_BACK_PORCH_COUNT_REG; | |
552 | uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG; | |
553 | uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG; | |
554 | uint32_t saveVERT_SYNC_PAD_COUNT_REG; | |
555 | uint32_t saveVERT_BACK_PORCH_COUNT_REG; | |
556 | uint32_t saveVERT_FRONT_PORCH_COUNT_REG; | |
557 | uint32_t saveHIGH_LOW_SWITCH_COUNT_REG; | |
558 | uint32_t saveINIT_COUNT_REG; | |
559 | uint32_t saveMAX_RET_PAK_REG; | |
560 | uint32_t saveVIDEO_FMT_REG; | |
561 | uint32_t saveEOT_DISABLE_REG; | |
562 | uint32_t saveLP_BYTECLK_REG; | |
563 | uint32_t saveHS_LS_DBI_ENABLE_REG; | |
564 | uint32_t saveTXCLKESC_REG; | |
565 | uint32_t saveDPHY_PARAM_REG; | |
566 | uint32_t saveMIPI_CONTROL_REG; | |
567 | uint32_t saveMIPI; | |
568 | uint32_t saveMIPI_C; | |
569 | ||
570 | /* DPST register save */ | |
571 | uint32_t saveHISTOGRAM_INT_CONTROL_REG; | |
572 | uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG; | |
573 | uint32_t savePWM_CONTROL_LOGIC; | |
574 | ||
575 | /* | |
576 | * DSI info. | |
577 | */ | |
578 | void * dbi_dsr_info; | |
579 | void * dbi_dpu_info; | |
580 | void * dsi_configs[2]; | |
581 | /* | |
582 | * LID-Switch | |
583 | */ | |
584 | spinlock_t lid_lock; | |
585 | struct timer_list lid_timer; | |
586 | struct psb_intel_opregion opregion; | |
587 | u32 *lid_state; | |
588 | u32 lid_last_state; | |
589 | ||
590 | /* | |
591 | * Watchdog | |
592 | */ | |
593 | ||
594 | uint32_t apm_reg; | |
595 | uint16_t apm_base; | |
596 | ||
597 | /* | |
598 | * Used for modifying backlight from | |
599 | * xrandr -- consider removing and using HAL instead | |
600 | */ | |
601 | struct backlight_device *backlight_device; | |
602 | struct drm_property *backlight_property; | |
603 | uint32_t blc_adj1; | |
604 | uint32_t blc_adj2; | |
605 | ||
606 | void *fbdev; | |
607 | ||
608 | /* 2D acceleration */ | |
9242fe23 | 609 | spinlock_t lock_2d; |
5c49fd3a AC |
610 | }; |
611 | ||
612 | ||
613 | /* | |
614 | * Operations for each board type | |
615 | */ | |
616 | ||
617 | struct psb_ops { | |
618 | const char *name; | |
619 | unsigned int accel_2d:1; | |
620 | int pipes; /* Number of output pipes */ | |
621 | int crtcs; /* Number of CRTCs */ | |
622 | int sgx_offset; /* Base offset of SGX device */ | |
623 | ||
624 | /* Sub functions */ | |
625 | struct drm_crtc_helper_funcs const *crtc_helper; | |
626 | struct drm_crtc_funcs const *crtc_funcs; | |
627 | ||
628 | /* Setup hooks */ | |
629 | int (*chip_setup)(struct drm_device *dev); | |
630 | void (*chip_teardown)(struct drm_device *dev); | |
631 | ||
632 | /* Display management hooks */ | |
633 | int (*output_init)(struct drm_device *dev); | |
634 | /* Power management hooks */ | |
635 | void (*init_pm)(struct drm_device *dev); | |
636 | int (*save_regs)(struct drm_device *dev); | |
637 | int (*restore_regs)(struct drm_device *dev); | |
638 | int (*power_up)(struct drm_device *dev); | |
639 | int (*power_down)(struct drm_device *dev); | |
640 | ||
641 | void (*lvds_bl_power)(struct drm_device *dev, bool on); | |
642 | #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE | |
643 | /* Backlight */ | |
644 | int (*backlight_init)(struct drm_device *dev); | |
645 | #endif | |
646 | int i2c_bus; /* I2C bus identifier for Moorestown */ | |
647 | }; | |
648 | ||
649 | ||
650 | ||
651 | struct psb_mmu_driver; | |
652 | ||
653 | extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int); | |
654 | extern int drm_pick_crtcs(struct drm_device *dev); | |
655 | ||
656 | static inline struct drm_psb_private *psb_priv(struct drm_device *dev) | |
657 | { | |
658 | return (struct drm_psb_private *) dev->dev_private; | |
659 | } | |
660 | ||
661 | /* | |
662 | * MMU stuff. | |
663 | */ | |
664 | ||
665 | extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers, | |
666 | int trap_pagefaults, | |
667 | int invalid_type, | |
668 | struct drm_psb_private *dev_priv); | |
669 | extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver); | |
670 | extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver | |
671 | *driver); | |
672 | extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset, | |
673 | uint32_t gtt_start, uint32_t gtt_pages); | |
674 | extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver, | |
675 | int trap_pagefaults, | |
676 | int invalid_type); | |
677 | extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd); | |
678 | extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot); | |
679 | extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd, | |
680 | unsigned long address, | |
681 | uint32_t num_pages); | |
682 | extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, | |
683 | uint32_t start_pfn, | |
684 | unsigned long address, | |
685 | uint32_t num_pages, int type); | |
686 | extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual, | |
687 | unsigned long *pfn); | |
688 | ||
689 | /* | |
690 | * Enable / disable MMU for different requestors. | |
691 | */ | |
692 | ||
693 | ||
694 | extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context); | |
695 | extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages, | |
696 | unsigned long address, uint32_t num_pages, | |
697 | uint32_t desired_tile_stride, | |
698 | uint32_t hw_tile_stride, int type); | |
699 | extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, | |
700 | unsigned long address, uint32_t num_pages, | |
701 | uint32_t desired_tile_stride, | |
702 | uint32_t hw_tile_stride); | |
703 | /* | |
704 | *psb_irq.c | |
705 | */ | |
706 | ||
707 | extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS); | |
708 | extern int psb_irq_enable_dpst(struct drm_device *dev); | |
709 | extern int psb_irq_disable_dpst(struct drm_device *dev); | |
710 | extern void psb_irq_preinstall(struct drm_device *dev); | |
711 | extern int psb_irq_postinstall(struct drm_device *dev); | |
712 | extern void psb_irq_uninstall(struct drm_device *dev); | |
713 | extern void psb_irq_turn_on_dpst(struct drm_device *dev); | |
714 | extern void psb_irq_turn_off_dpst(struct drm_device *dev); | |
715 | ||
716 | extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands); | |
717 | extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence); | |
718 | extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence); | |
719 | extern int psb_enable_vblank(struct drm_device *dev, int crtc); | |
720 | extern void psb_disable_vblank(struct drm_device *dev, int crtc); | |
721 | void | |
722 | psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); | |
723 | ||
724 | void | |
725 | psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); | |
726 | ||
727 | extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc); | |
728 | ||
729 | /* | |
730 | * intel_opregion.c | |
731 | */ | |
732 | extern int gma_intel_opregion_init(struct drm_device *dev); | |
733 | extern int gma_intel_opregion_exit(struct drm_device *dev); | |
734 | ||
735 | /* | |
736 | * framebuffer.c | |
737 | */ | |
738 | extern int psbfb_probed(struct drm_device *dev); | |
739 | extern int psbfb_remove(struct drm_device *dev, | |
740 | struct drm_framebuffer *fb); | |
741 | /* | |
742 | * accel_2d.c | |
743 | */ | |
744 | extern void psbfb_copyarea(struct fb_info *info, | |
745 | const struct fb_copyarea *region); | |
746 | extern int psbfb_sync(struct fb_info *info); | |
747 | extern void psb_spank(struct drm_psb_private *dev_priv); | |
748 | ||
749 | /* | |
750 | * psb_reset.c | |
751 | */ | |
752 | ||
753 | extern void psb_lid_timer_init(struct drm_psb_private *dev_priv); | |
754 | extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv); | |
755 | extern void psb_print_pagefault(struct drm_psb_private *dev_priv); | |
756 | ||
757 | /* modesetting */ | |
758 | extern void psb_modeset_init(struct drm_device *dev); | |
759 | extern void psb_modeset_cleanup(struct drm_device *dev); | |
760 | extern int psb_fbdev_init(struct drm_device *dev); | |
761 | ||
762 | /* backlight.c */ | |
763 | int gma_backlight_init(struct drm_device *dev); | |
764 | void gma_backlight_exit(struct drm_device *dev); | |
765 | ||
766 | /* oaktrail_crtc.c */ | |
767 | extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs; | |
768 | ||
769 | /* oaktrail_lvds.c */ | |
770 | extern void oaktrail_lvds_init(struct drm_device *dev, | |
771 | struct psb_intel_mode_device *mode_dev); | |
772 | ||
773 | /* psb_intel_display.c */ | |
774 | extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs; | |
775 | extern const struct drm_crtc_funcs psb_intel_crtc_funcs; | |
776 | ||
777 | /* psb_intel_lvds.c */ | |
778 | extern const struct drm_connector_helper_funcs | |
779 | psb_intel_lvds_connector_helper_funcs; | |
780 | extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs; | |
781 | ||
782 | /* gem.c */ | |
783 | extern int psb_gem_init_object(struct drm_gem_object *obj); | |
784 | extern void psb_gem_free_object(struct drm_gem_object *obj); | |
785 | extern int psb_gem_get_aperture(struct drm_device *dev, void *data, | |
786 | struct drm_file *file); | |
787 | extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev, | |
788 | struct drm_mode_create_dumb *args); | |
789 | extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev, | |
790 | uint32_t handle); | |
791 | extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev, | |
792 | uint32_t handle, uint64_t *offset); | |
793 | extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); | |
794 | extern int psb_gem_create_ioctl(struct drm_device *dev, void *data, | |
795 | struct drm_file *file); | |
796 | extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
797 | struct drm_file *file); | |
798 | ||
799 | /* psb_device.c */ | |
800 | extern const struct psb_ops psb_chip_ops; | |
801 | ||
802 | /* oaktrail_device.c */ | |
803 | extern const struct psb_ops oaktrail_chip_ops; | |
804 | ||
805 | /* cdv_device.c */ | |
806 | extern const struct psb_ops cdv_chip_ops; | |
807 | ||
808 | /* | |
809 | * Debug print bits setting | |
810 | */ | |
811 | #define PSB_D_GENERAL (1 << 0) | |
812 | #define PSB_D_INIT (1 << 1) | |
813 | #define PSB_D_IRQ (1 << 2) | |
814 | #define PSB_D_ENTRY (1 << 3) | |
815 | /* debug the get H/V BP/FP count */ | |
816 | #define PSB_D_HV (1 << 4) | |
817 | #define PSB_D_DBI_BF (1 << 5) | |
818 | #define PSB_D_PM (1 << 6) | |
819 | #define PSB_D_RENDER (1 << 7) | |
820 | #define PSB_D_REG (1 << 8) | |
821 | #define PSB_D_MSVDX (1 << 9) | |
822 | #define PSB_D_TOPAZ (1 << 10) | |
823 | ||
824 | extern int drm_psb_no_fb; | |
825 | extern int drm_idle_check_interval; | |
826 | ||
827 | /* | |
828 | * Utilities | |
829 | */ | |
830 | ||
831 | static inline u32 MRST_MSG_READ32(uint port, uint offset) | |
832 | { | |
833 | int mcr = (0xD0<<24) | (port << 16) | (offset << 8); | |
834 | uint32_t ret_val = 0; | |
835 | struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); | |
836 | pci_write_config_dword(pci_root, 0xD0, mcr); | |
837 | pci_read_config_dword(pci_root, 0xD4, &ret_val); | |
838 | pci_dev_put(pci_root); | |
839 | return ret_val; | |
840 | } | |
841 | static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value) | |
842 | { | |
843 | int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0; | |
844 | struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); | |
845 | pci_write_config_dword(pci_root, 0xD4, value); | |
846 | pci_write_config_dword(pci_root, 0xD0, mcr); | |
847 | pci_dev_put(pci_root); | |
848 | } | |
849 | static inline u32 MDFLD_MSG_READ32(uint port, uint offset) | |
850 | { | |
851 | int mcr = (0x10<<24) | (port << 16) | (offset << 8); | |
852 | uint32_t ret_val = 0; | |
853 | struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); | |
854 | pci_write_config_dword(pci_root, 0xD0, mcr); | |
855 | pci_read_config_dword(pci_root, 0xD4, &ret_val); | |
856 | pci_dev_put(pci_root); | |
857 | return ret_val; | |
858 | } | |
859 | static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value) | |
860 | { | |
861 | int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; | |
862 | struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); | |
863 | pci_write_config_dword(pci_root, 0xD4, value); | |
864 | pci_write_config_dword(pci_root, 0xD0, mcr); | |
865 | pci_dev_put(pci_root); | |
866 | } | |
867 | ||
868 | static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) | |
869 | { | |
870 | struct drm_psb_private *dev_priv = dev->dev_private; | |
871 | return ioread32(dev_priv->vdc_reg + reg); | |
872 | } | |
873 | ||
874 | #define REG_READ(reg) REGISTER_READ(dev, (reg)) | |
875 | ||
876 | static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, | |
877 | uint32_t val) | |
878 | { | |
879 | struct drm_psb_private *dev_priv = dev->dev_private; | |
880 | iowrite32((val), dev_priv->vdc_reg + (reg)); | |
881 | } | |
882 | ||
883 | #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) | |
884 | ||
885 | static inline void REGISTER_WRITE16(struct drm_device *dev, | |
886 | uint32_t reg, uint32_t val) | |
887 | { | |
888 | struct drm_psb_private *dev_priv = dev->dev_private; | |
889 | iowrite16((val), dev_priv->vdc_reg + (reg)); | |
890 | } | |
891 | ||
892 | #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val)) | |
893 | ||
894 | static inline void REGISTER_WRITE8(struct drm_device *dev, | |
895 | uint32_t reg, uint32_t val) | |
896 | { | |
897 | struct drm_psb_private *dev_priv = dev->dev_private; | |
898 | iowrite8((val), dev_priv->vdc_reg + (reg)); | |
899 | } | |
900 | ||
901 | #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) | |
902 | ||
903 | #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) | |
904 | #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs)) | |
905 | ||
906 | /* #define TRAP_SGX_PM_FAULT 1 */ | |
907 | #ifdef TRAP_SGX_PM_FAULT | |
908 | #define PSB_RSGX32(_offs) \ | |
909 | ({ \ | |
910 | if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \ | |
911 | printk(KERN_ERR \ | |
912 | "access sgx when it's off!! (READ) %s, %d\n", \ | |
913 | __FILE__, __LINE__); \ | |
914 | melay(1000); \ | |
915 | } \ | |
916 | ioread32(dev_priv->sgx_reg + (_offs)); \ | |
917 | }) | |
918 | #else | |
919 | #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs)) | |
920 | #endif | |
921 | #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs)) | |
922 | ||
923 | #define MSVDX_REG_DUMP 0 | |
924 | ||
925 | #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs)) | |
926 | #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs)) | |
927 | ||
928 | #endif |