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gma500: Convert Cedarview to work with new output handling
[deliverable/linux.git] / drivers / gpu / drm / gma500 / psb_drv.h
CommitLineData
5c49fd3a
AC		 1/**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20#ifndef _PSB_DRV_H_
21#define _PSB_DRV_H_
22
23#include <linux/kref.h>
24
25#include <drm/drmP.h>
26#include "drm_global.h"
27#include "gem_glue.h"
838fa588 28#include "gma_drm.h"
5c49fd3a
AC		 29#include "psb_reg.h"
30#include "psb_intel_drv.h"
31#include "gtt.h"
32#include "power.h"
33#include "oaktrail.h"
34
35/* Append new drm mode definition here, align with libdrm definition */
36#define DRM_MODE_SCALE_NO_SCALE 2
37
38enum {
39 CHIP_PSB_8108 = 0, /* Poulsbo */
40 CHIP_PSB_8109 = 1, /* Poulsbo */
41 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
42 CHIP_MFLD_0130 = 3, /* Medfield */
43};
44
e036ba59 45#define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
5c49fd3a
AC		 46#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
47#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
48
49/*
50 * Driver definitions
51 */
52
53#define DRIVER_NAME "gma500"
54#define DRIVER_DESC "DRM driver for the Intel GMA500"
55
56#define PSB_DRM_DRIVER_DATE "2011-06-06"
57#define PSB_DRM_DRIVER_MAJOR 1
58#define PSB_DRM_DRIVER_MINOR 0
59#define PSB_DRM_DRIVER_PATCHLEVEL 0
60
61/*
62 * Hardware offsets
63 */
64#define PSB_VDC_OFFSET 0x00000000
65#define PSB_VDC_SIZE 0x000080000
66#define MRST_MMIO_SIZE 0x0000C0000
67#define MDFLD_MMIO_SIZE 0x000100000
68#define PSB_SGX_SIZE 0x8000
69#define PSB_SGX_OFFSET 0x00040000
70#define MRST_SGX_OFFSET 0x00080000
71/*
72 * PCI resource identifiers
73 */
74#define PSB_MMIO_RESOURCE 0
75#define PSB_GATT_RESOURCE 2
76#define PSB_GTT_RESOURCE 3
77/*
78 * PCI configuration
79 */
80#define PSB_GMCH_CTRL 0x52
81#define PSB_BSM 0x5C
82#define _PSB_GMCH_ENABLED 0x4
83#define PSB_PGETBL_CTL 0x2020
84#define _PSB_PGETBL_ENABLED 0x00000001
85#define PSB_SGX_2D_SLAVE_PORT 0x4000
86
87/* To get rid of */
88#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
89#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
90
91/*
92 * SGX side MMU definitions (these can probably go)
93 */
94
95/*
96 * Flags for external memory type field.
97 */
98#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
99#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
100#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
101/*
102 * PTE's and PDE's
103 */
104#define PSB_PDE_MASK 0x003FFFFF
105#define PSB_PDE_SHIFT 22
106#define PSB_PTE_SHIFT 12
107/*
108 * Cache control
109 */
110#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
111#define PSB_PTE_WO 0x0002 /* Write only */
112#define PSB_PTE_RO 0x0004 /* Read only */
113#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
114
115/*
116 * VDC registers and bits
117 */
118#define PSB_MSVDX_CLOCKGATING 0x2064
119#define PSB_TOPAZ_CLOCKGATING 0x2068
120#define PSB_HWSTAM 0x2098
121#define PSB_INSTPM 0x20C0
122#define PSB_INT_IDENTITY_R 0x20A4
123#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
124#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
125#define _PSB_DPST_PIPEB_FLAG (1<<4)
126#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
127#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
128#define _PSB_DPST_PIPEA_FLAG (1<<6)
129#define _PSB_PIPEA_EVENT_FLAG (1<<6)
130#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
131#define _MDFLD_MIPIA_FLAG (1<<16)
132#define _MDFLD_MIPIC_FLAG (1<<17)
133#define _PSB_IRQ_SGX_FLAG (1<<18)
134#define _PSB_IRQ_MSVDX_FLAG (1<<19)
135#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
136
700e59f6
PJ		 137#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
138 _PSB_VSYNC_PIPEB_FLAG)
139
5c49fd3a
AC		 140/* This flag includes all the display IRQ bits excepts the vblank irqs. */
141#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
142 _MDFLD_PIPEB_EVENT_FLAG | \
143 _PSB_PIPEA_EVENT_FLAG | \
144 _PSB_VSYNC_PIPEA_FLAG | \
145 _MDFLD_MIPIA_FLAG | \
146 _MDFLD_MIPIC_FLAG)
147#define PSB_INT_IDENTITY_R 0x20A4
148#define PSB_INT_MASK_R 0x20A8
149#define PSB_INT_ENABLE_R 0x20A0
150
151#define _PSB_MMU_ER_MASK 0x0001FF00
152#define _PSB_MMU_ER_HOST (1 << 16)
153#define GPIOA 0x5010
154#define GPIOB 0x5014
155#define GPIOC 0x5018
156#define GPIOD 0x501c
157#define GPIOE 0x5020
158#define GPIOF 0x5024
159#define GPIOG 0x5028
160#define GPIOH 0x502c
161#define GPIO_CLOCK_DIR_MASK (1 << 0)
162#define GPIO_CLOCK_DIR_IN (0 << 1)
163#define GPIO_CLOCK_DIR_OUT (1 << 1)
164#define GPIO_CLOCK_VAL_MASK (1 << 2)
165#define GPIO_CLOCK_VAL_OUT (1 << 3)
166#define GPIO_CLOCK_VAL_IN (1 << 4)
167#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
168#define GPIO_DATA_DIR_MASK (1 << 8)
169#define GPIO_DATA_DIR_IN (0 << 9)
170#define GPIO_DATA_DIR_OUT (1 << 9)
171#define GPIO_DATA_VAL_MASK (1 << 10)
172#define GPIO_DATA_VAL_OUT (1 << 11)
173#define GPIO_DATA_VAL_IN (1 << 12)
174#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
175
176#define VCLK_DIVISOR_VGA0 0x6000
177#define VCLK_DIVISOR_VGA1 0x6004
178#define VCLK_POST_DIV 0x6010
179
180#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
181#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
182#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
183#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
184#define PSB_COMM_USER_IRQ (1024 >> 2)
185#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
186#define PSB_COMM_FW (2048 >> 2)
187
188#define PSB_UIRQ_VISTEST 1
189#define PSB_UIRQ_OOM_REPLY 2
190#define PSB_UIRQ_FIRE_TA_REPLY 3
191#define PSB_UIRQ_FIRE_RASTER_REPLY 4
192
193#define PSB_2D_SIZE (256*1024*1024)
194#define PSB_MAX_RELOC_PAGES 1024
195
196#define PSB_LOW_REG_OFFS 0x0204
197#define PSB_HIGH_REG_OFFS 0x0600
198
199#define PSB_NUM_VBLANKS 2
200
201
202#define PSB_2D_SIZE (256*1024*1024)
203#define PSB_MAX_RELOC_PAGES 1024
204
205#define PSB_LOW_REG_OFFS 0x0204
206#define PSB_HIGH_REG_OFFS 0x0600
207
208#define PSB_NUM_VBLANKS 2
209#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
210#define PSB_LID_DELAY (DRM_HZ / 10)
211
212#define MDFLD_PNW_B0 0x04
213#define MDFLD_PNW_C0 0x08
214
215#define MDFLD_DSR_2D_3D_0 (1 << 0)
216#define MDFLD_DSR_2D_3D_2 (1 << 1)
217#define MDFLD_DSR_CURSOR_0 (1 << 2)
218#define MDFLD_DSR_CURSOR_2 (1 << 3)
219#define MDFLD_DSR_OVERLAY_0 (1 << 4)
220#define MDFLD_DSR_OVERLAY_2 (1 << 5)
221#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
222#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
223#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
224#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
225
226#define MDFLD_DSR_RR 45
227#define MDFLD_DPU_ENABLE (1 << 31)
228#define MDFLD_DSR_FULLSCREEN (1 << 30)
229#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
230
231#define PSB_PWR_STATE_ON 1
232#define PSB_PWR_STATE_OFF 2
233
234#define PSB_PMPOLICY_NOPM 0
235#define PSB_PMPOLICY_CLOCKGATING 1
236#define PSB_PMPOLICY_POWERDOWN 2
237
238#define PSB_PMSTATE_POWERUP 0
239#define PSB_PMSTATE_CLOCKGATED 1
240#define PSB_PMSTATE_POWERDOWN 2
241#define PSB_PCIx_MSI_ADDR_LOC 0x94
242#define PSB_PCIx_MSI_DATA_LOC 0x98
243
244/* Medfield crystal settings */
245#define KSEL_CRYSTAL_19 1
246#define KSEL_BYPASS_19 5
247#define KSEL_BYPASS_25 6
248#define KSEL_BYPASS_83_100 7
249
250struct opregion_header;
251struct opregion_acpi;
252struct opregion_swsci;
253struct opregion_asle;
254
255struct psb_intel_opregion {
256 struct opregion_header *header;
257 struct opregion_acpi *acpi;
258 struct opregion_swsci *swsci;
259 struct opregion_asle *asle;
260 int enabled;
261};
262
5736995b
PJ		 263struct sdvo_device_mapping {
264 u8 initialized;
265 u8 dvo_port;
266 u8 slave_addr;
267 u8 dvo_wiring;
268 u8 i2c_pin;
269 u8 i2c_speed;
270 u8 ddc_pin;
271};
272
5c0c1d50
PJ		 273struct intel_gmbus {
274 struct i2c_adapter adapter;
275 struct i2c_adapter *force_bit;
276 u32 reg0;
277};
278
5c49fd3a
AC		 279struct psb_ops;
280
04bd564f
AC		 281#define PSB_NUM_PIPE 3
282
5c49fd3a
AC		 283struct drm_psb_private {
284 struct drm_device *dev;
285 const struct psb_ops *ops;
286
287 struct psb_gtt gtt;
288
289 /* GTT Memory manager */
290 struct psb_gtt_mm *gtt_mm;
291 struct page *scratch_page;
292 u32 *gtt_map;
293 uint32_t stolen_base;
294 void *vram_addr;
295 unsigned long vram_stolen_size;
296 int gtt_initialized;
297 u16 gmch_ctrl; /* Saved GTT setup */
298 u32 pge_ctl;
299
300 struct mutex gtt_mutex;
301 struct resource *gtt_mem; /* Our PCI resource */
302
303 struct psb_mmu_driver *mmu;
304 struct psb_mmu_pd *pf_pd;
305
306 /*
307 * Register base
308 */
309
310 uint8_t *sgx_reg;
311 uint8_t *vdc_reg;
312 uint32_t gatt_free_offset;
313
314 /*
315 * Fencing / irq.
316 */
317
318 uint32_t vdc_irq_mask;
319 uint32_t pipestat[PSB_NUM_PIPE];
320
321 spinlock_t irqmask_lock;
322
323 /*
324 * Power
325 */
326
327 bool suspended;
328 bool display_power;
329 int display_count;
330
331 /*
332 * Modesetting
333 */
334 struct psb_intel_mode_device mode_dev;
335
336 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
337 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
338 uint32_t num_pipe;
339
340 /*
341 * OSPM info (Power management base) (can go ?)
342 */
343 uint32_t ospm_base;
344
345 /*
346 * Sizes info
347 */
348
5c49fd3a
AC		 349 u32 fuse_reg_value;
350 u32 video_device_fuse;
351
352 /* PCI revision ID for B0:D2:F0 */
353 uint8_t platform_rev_id;
354
5c0c1d50
PJ		 355 /* gmbus */
356 struct intel_gmbus *gmbus;
357
5736995b
PJ		 358 /* Used by SDVO */
359 int crt_ddc_pin;
360 /* FIXME: The mappings should be parsed from bios but for now we can
361 pretend there are no mappings available */
362 struct sdvo_device_mapping sdvo_mappings[2];
363 u32 hotplug_supported_mask;
364 struct drm_property *broadcast_rgb_property;
365 struct drm_property *force_audio_property;
366
5c49fd3a
AC		 367 /*
368 * LVDS info
369 */
370 int backlight_duty_cycle; /* restore backlight to this value */
371 bool panel_wants_dither;
372 struct drm_display_mode *panel_fixed_mode;
373 struct drm_display_mode *lfp_lvds_vbt_mode;
374 struct drm_display_mode *sdvo_lvds_vbt_mode;
375
376 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
a12d6a07 377 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
5c49fd3a
AC		 378
379 /* Feature bits from the VBIOS */
380 unsigned int int_tv_support:1;
381 unsigned int lvds_dither:1;
382 unsigned int lvds_vbt:1;
383 unsigned int int_crt_support:1;
384 unsigned int lvds_use_ssc:1;
385 int lvds_ssc_freq;
386 bool is_lvds_on;
387 bool is_mipi_on;
388 u32 mipi_ctrl_display;
389
390 unsigned int core_freq;
391 uint32_t iLVDS_enable;
392
393 /* Runtime PM state */
394 int rpm_enabled;
395
396 /* MID specific */
397 struct oaktrail_vbt vbt_data;
398 struct oaktrail_gct_data gct_data;
399
400 /* MIPI Panel type etc */
401 int panel_id;
402 bool dual_mipi; /* dual display - DPI & DBI */
403 bool dpi_panel_on; /* The DPI panel power is on */
404 bool dpi_panel_on2; /* The DPI panel power is on */
405 bool dbi_panel_on; /* The DBI panel power is on */
406 bool dbi_panel_on2; /* The DBI panel power is on */
407 u32 dsr_fb_update; /* DSR FB update counter */
408
409 /* Moorestown HDMI state */
410 struct oaktrail_hdmi_dev *hdmi_priv;
411
412 /* Moorestown pipe config register value cache */
413 uint32_t pipeconf;
414 uint32_t pipeconf1;
415 uint32_t pipeconf2;
416
417 /* Moorestown plane control register value cache */
418 uint32_t dspcntr;
419 uint32_t dspcntr1;
420 uint32_t dspcntr2;
421
422 /* Moorestown MM backlight cache */
423 uint8_t saveBKLTCNT;
424 uint8_t saveBKLTREQ;
425 uint8_t saveBKLTBRTL;
426
427 /*
428 * Register state
429 */
430 uint32_t saveDSPACNTR;
431 uint32_t saveDSPBCNTR;
432 uint32_t savePIPEACONF;
433 uint32_t savePIPEBCONF;
434 uint32_t savePIPEASRC;
435 uint32_t savePIPEBSRC;
436 uint32_t saveFPA0;
437 uint32_t saveFPA1;
438 uint32_t saveDPLL_A;
439 uint32_t saveDPLL_A_MD;
440 uint32_t saveHTOTAL_A;
441 uint32_t saveHBLANK_A;
442 uint32_t saveHSYNC_A;
443 uint32_t saveVTOTAL_A;
444 uint32_t saveVBLANK_A;
445 uint32_t saveVSYNC_A;
446 uint32_t saveDSPASTRIDE;
447 uint32_t saveDSPASIZE;
448 uint32_t saveDSPAPOS;
449 uint32_t saveDSPABASE;
450 uint32_t saveDSPASURF;
451 uint32_t saveDSPASTATUS;
452 uint32_t saveFPB0;
453 uint32_t saveFPB1;
454 uint32_t saveDPLL_B;
455 uint32_t saveDPLL_B_MD;
456 uint32_t saveHTOTAL_B;
457 uint32_t saveHBLANK_B;
458 uint32_t saveHSYNC_B;
459 uint32_t saveVTOTAL_B;
460 uint32_t saveVBLANK_B;
461 uint32_t saveVSYNC_B;
462 uint32_t saveDSPBSTRIDE;
463 uint32_t saveDSPBSIZE;
464 uint32_t saveDSPBPOS;
465 uint32_t saveDSPBBASE;
466 uint32_t saveDSPBSURF;
467 uint32_t saveDSPBSTATUS;
468 uint32_t saveVCLK_DIVISOR_VGA0;
469 uint32_t saveVCLK_DIVISOR_VGA1;
470 uint32_t saveVCLK_POST_DIV;
471 uint32_t saveVGACNTRL;
472 uint32_t saveADPA;
473 uint32_t saveLVDS;
474 uint32_t saveDVOA;
475 uint32_t saveDVOB;
476 uint32_t saveDVOC;
477 uint32_t savePP_ON;
478 uint32_t savePP_OFF;
479 uint32_t savePP_CONTROL;
480 uint32_t savePP_CYCLE;
481 uint32_t savePFIT_CONTROL;
482 uint32_t savePaletteA[256];
483 uint32_t savePaletteB[256];
484 uint32_t saveBLC_PWM_CTL2;
485 uint32_t saveBLC_PWM_CTL;
486 uint32_t saveCLOCKGATING;
487 uint32_t saveDSPARB;
488 uint32_t saveDSPATILEOFF;
489 uint32_t saveDSPBTILEOFF;
490 uint32_t saveDSPAADDR;
491 uint32_t saveDSPBADDR;
492 uint32_t savePFIT_AUTO_RATIOS;
493 uint32_t savePFIT_PGM_RATIOS;
494 uint32_t savePP_ON_DELAYS;
495 uint32_t savePP_OFF_DELAYS;
496 uint32_t savePP_DIVISOR;
497 uint32_t saveBSM;
498 uint32_t saveVBT;
499 uint32_t saveBCLRPAT_A;
500 uint32_t saveBCLRPAT_B;
501 uint32_t saveDSPALINOFF;
502 uint32_t saveDSPBLINOFF;
503 uint32_t savePERF_MODE;
504 uint32_t saveDSPFW1;
505 uint32_t saveDSPFW2;
506 uint32_t saveDSPFW3;
507 uint32_t saveDSPFW4;
508 uint32_t saveDSPFW5;
509 uint32_t saveDSPFW6;
510 uint32_t saveCHICKENBIT;
511 uint32_t saveDSPACURSOR_CTRL;
512 uint32_t saveDSPBCURSOR_CTRL;
513 uint32_t saveDSPACURSOR_BASE;
514 uint32_t saveDSPBCURSOR_BASE;
515 uint32_t saveDSPACURSOR_POS;
516 uint32_t saveDSPBCURSOR_POS;
517 uint32_t save_palette_a[256];
518 uint32_t save_palette_b[256];
519 uint32_t saveOV_OVADD;
520 uint32_t saveOV_OGAMC0;
521 uint32_t saveOV_OGAMC1;
522 uint32_t saveOV_OGAMC2;
523 uint32_t saveOV_OGAMC3;
524 uint32_t saveOV_OGAMC4;
525 uint32_t saveOV_OGAMC5;
526 uint32_t saveOVC_OVADD;
527 uint32_t saveOVC_OGAMC0;
528 uint32_t saveOVC_OGAMC1;
529 uint32_t saveOVC_OGAMC2;
530 uint32_t saveOVC_OGAMC3;
531 uint32_t saveOVC_OGAMC4;
532 uint32_t saveOVC_OGAMC5;
533
534 /* MSI reg save */
535 uint32_t msi_addr;
536 uint32_t msi_data;
537
538 /* Medfield specific register save state */
539 uint32_t saveHDMIPHYMISCCTL;
540 uint32_t saveHDMIB_CONTROL;
541 uint32_t saveDSPCCNTR;
542 uint32_t savePIPECCONF;
543 uint32_t savePIPECSRC;
544 uint32_t saveHTOTAL_C;
545 uint32_t saveHBLANK_C;
546 uint32_t saveHSYNC_C;
547 uint32_t saveVTOTAL_C;
548 uint32_t saveVBLANK_C;
549 uint32_t saveVSYNC_C;
550 uint32_t saveDSPCSTRIDE;
551 uint32_t saveDSPCSIZE;
552 uint32_t saveDSPCPOS;
553 uint32_t saveDSPCSURF;
554 uint32_t saveDSPCSTATUS;
555 uint32_t saveDSPCLINOFF;
556 uint32_t saveDSPCTILEOFF;
557 uint32_t saveDSPCCURSOR_CTRL;
558 uint32_t saveDSPCCURSOR_BASE;
559 uint32_t saveDSPCCURSOR_POS;
560 uint32_t save_palette_c[256];
561 uint32_t saveOV_OVADD_C;
562 uint32_t saveOV_OGAMC0_C;
563 uint32_t saveOV_OGAMC1_C;
564 uint32_t saveOV_OGAMC2_C;
565 uint32_t saveOV_OGAMC3_C;
566 uint32_t saveOV_OGAMC4_C;
567 uint32_t saveOV_OGAMC5_C;
568
569 /* DSI register save */
570 uint32_t saveDEVICE_READY_REG;
571 uint32_t saveINTR_EN_REG;
572 uint32_t saveDSI_FUNC_PRG_REG;
573 uint32_t saveHS_TX_TIMEOUT_REG;
574 uint32_t saveLP_RX_TIMEOUT_REG;
575 uint32_t saveTURN_AROUND_TIMEOUT_REG;
576 uint32_t saveDEVICE_RESET_REG;
577 uint32_t saveDPI_RESOLUTION_REG;
578 uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
579 uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
580 uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
581 uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
582 uint32_t saveVERT_SYNC_PAD_COUNT_REG;
583 uint32_t saveVERT_BACK_PORCH_COUNT_REG;
584 uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
585 uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
586 uint32_t saveINIT_COUNT_REG;
587 uint32_t saveMAX_RET_PAK_REG;
588 uint32_t saveVIDEO_FMT_REG;
589 uint32_t saveEOT_DISABLE_REG;
590 uint32_t saveLP_BYTECLK_REG;
591 uint32_t saveHS_LS_DBI_ENABLE_REG;
592 uint32_t saveTXCLKESC_REG;
593 uint32_t saveDPHY_PARAM_REG;
594 uint32_t saveMIPI_CONTROL_REG;
595 uint32_t saveMIPI;
596 uint32_t saveMIPI_C;
597
598 /* DPST register save */
599 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
600 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
601 uint32_t savePWM_CONTROL_LOGIC;
602
603 /*
604 * DSI info.
605 */
606 void * dbi_dsr_info;
607 void * dbi_dpu_info;
608 void * dsi_configs[2];
609 /*
610 * LID-Switch
611 */
612 spinlock_t lid_lock;
613 struct timer_list lid_timer;
614 struct psb_intel_opregion opregion;
615 u32 *lid_state;
616 u32 lid_last_state;
617
618 /*
619 * Watchdog
620 */
621
622 uint32_t apm_reg;
623 uint16_t apm_base;
624
625 /*
626 * Used for modifying backlight from
627 * xrandr -- consider removing and using HAL instead
628 */
629 struct backlight_device *backlight_device;
630 struct drm_property *backlight_property;
631 uint32_t blc_adj1;
632 uint32_t blc_adj2;
633
634 void *fbdev;
635
636 /* 2D acceleration */
9242fe23 637 spinlock_t lock_2d;
5c49fd3a
AC		 638};
639
640
641/*
642 * Operations for each board type
643 */
644
645struct psb_ops {
646 const char *name;
647 unsigned int accel_2d:1;
648 int pipes; /* Number of output pipes */
649 int crtcs; /* Number of CRTCs */
650 int sgx_offset; /* Base offset of SGX device */
651
652 /* Sub functions */
653 struct drm_crtc_helper_funcs const *crtc_helper;
654 struct drm_crtc_funcs const *crtc_funcs;
655
656 /* Setup hooks */
657 int (*chip_setup)(struct drm_device *dev);
658 void (*chip_teardown)(struct drm_device *dev);
659
660 /* Display management hooks */
661 int (*output_init)(struct drm_device *dev);
662 /* Power management hooks */
663 void (*init_pm)(struct drm_device *dev);
664 int (*save_regs)(struct drm_device *dev);
665 int (*restore_regs)(struct drm_device *dev);
666 int (*power_up)(struct drm_device *dev);
667 int (*power_down)(struct drm_device *dev);
668
669 void (*lvds_bl_power)(struct drm_device *dev, bool on);
670#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
671 /* Backlight */
672 int (*backlight_init)(struct drm_device *dev);
673#endif
674 int i2c_bus; /* I2C bus identifier for Moorestown */
675};
676
677
678
679struct psb_mmu_driver;
680
681extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
682extern int drm_pick_crtcs(struct drm_device *dev);
683
684static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
685{
686 return (struct drm_psb_private *) dev->dev_private;
687}
688
689/*
690 * MMU stuff.
691 */
692
693extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
694 int trap_pagefaults,
695 int invalid_type,
696 struct drm_psb_private *dev_priv);
697extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
698extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
699 *driver);
700extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
701 uint32_t gtt_start, uint32_t gtt_pages);
702extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
703 int trap_pagefaults,
704 int invalid_type);
705extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
706extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
707extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
708 unsigned long address,
709 uint32_t num_pages);
710extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
711 uint32_t start_pfn,
712 unsigned long address,
713 uint32_t num_pages, int type);
714extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
715 unsigned long *pfn);
716
717/*
718 * Enable / disable MMU for different requestors.
719 */
720
721
722extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
723extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
724 unsigned long address, uint32_t num_pages,
725 uint32_t desired_tile_stride,
726 uint32_t hw_tile_stride, int type);
727extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
728 unsigned long address, uint32_t num_pages,
729 uint32_t desired_tile_stride,
730 uint32_t hw_tile_stride);
731/*
732 *psb_irq.c
733 */
734
735extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
736extern int psb_irq_enable_dpst(struct drm_device *dev);
737extern int psb_irq_disable_dpst(struct drm_device *dev);
738extern void psb_irq_preinstall(struct drm_device *dev);
739extern int psb_irq_postinstall(struct drm_device *dev);
740extern void psb_irq_uninstall(struct drm_device *dev);
741extern void psb_irq_turn_on_dpst(struct drm_device *dev);
742extern void psb_irq_turn_off_dpst(struct drm_device *dev);
743
744extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
745extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
746extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
747extern int psb_enable_vblank(struct drm_device *dev, int crtc);
748extern void psb_disable_vblank(struct drm_device *dev, int crtc);
749void
750psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
751
752void
753psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
754
755extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
756
757/*
758 * intel_opregion.c
759 */
760extern int gma_intel_opregion_init(struct drm_device *dev);
761extern int gma_intel_opregion_exit(struct drm_device *dev);
762
763/*
764 * framebuffer.c
765 */
766extern int psbfb_probed(struct drm_device *dev);
767extern int psbfb_remove(struct drm_device *dev,
768 struct drm_framebuffer *fb);
769/*
770 * accel_2d.c
771 */
772extern void psbfb_copyarea(struct fb_info *info,
773 const struct fb_copyarea *region);
774extern int psbfb_sync(struct fb_info *info);
775extern void psb_spank(struct drm_psb_private *dev_priv);
776
777/*
778 * psb_reset.c
779 */
780
781extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
782extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
783extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
784
785/* modesetting */
786extern void psb_modeset_init(struct drm_device *dev);
787extern void psb_modeset_cleanup(struct drm_device *dev);
788extern int psb_fbdev_init(struct drm_device *dev);
789
790/* backlight.c */
791int gma_backlight_init(struct drm_device *dev);
792void gma_backlight_exit(struct drm_device *dev);
793
794/* oaktrail_crtc.c */
795extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
796
797/* oaktrail_lvds.c */
798extern void oaktrail_lvds_init(struct drm_device *dev,
799 struct psb_intel_mode_device *mode_dev);
800
801/* psb_intel_display.c */
802extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
803extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
804
805/* psb_intel_lvds.c */
806extern const struct drm_connector_helper_funcs
807 psb_intel_lvds_connector_helper_funcs;
808extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
809
810/* gem.c */
811extern int psb_gem_init_object(struct drm_gem_object *obj);
812extern void psb_gem_free_object(struct drm_gem_object *obj);
813extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
814 struct drm_file *file);
815extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
816 struct drm_mode_create_dumb *args);
817extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
818 uint32_t handle);
819extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
820 uint32_t handle, uint64_t *offset);
821extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
822extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
823 struct drm_file *file);
824extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
825 struct drm_file *file);
826
827/* psb_device.c */
828extern const struct psb_ops psb_chip_ops;
829
830/* oaktrail_device.c */
831extern const struct psb_ops oaktrail_chip_ops;
832
833/* cdv_device.c */
834extern const struct psb_ops cdv_chip_ops;
835
836/*
837 * Debug print bits setting
838 */
839#define PSB_D_GENERAL (1 << 0)
840#define PSB_D_INIT (1 << 1)
841#define PSB_D_IRQ (1 << 2)
842#define PSB_D_ENTRY (1 << 3)
843/* debug the get H/V BP/FP count */
844#define PSB_D_HV (1 << 4)
845#define PSB_D_DBI_BF (1 << 5)
846#define PSB_D_PM (1 << 6)
847#define PSB_D_RENDER (1 << 7)
848#define PSB_D_REG (1 << 8)
849#define PSB_D_MSVDX (1 << 9)
850#define PSB_D_TOPAZ (1 << 10)
851
852extern int drm_psb_no_fb;
853extern int drm_idle_check_interval;
854
855/*
856 * Utilities
857 */
858
859static inline u32 MRST_MSG_READ32(uint port, uint offset)
860{
861 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
862 uint32_t ret_val = 0;
863 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
864 pci_write_config_dword(pci_root, 0xD0, mcr);
865 pci_read_config_dword(pci_root, 0xD4, &ret_val);
866 pci_dev_put(pci_root);
867 return ret_val;
868}
869static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
870{
871 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
872 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
873 pci_write_config_dword(pci_root, 0xD4, value);
874 pci_write_config_dword(pci_root, 0xD0, mcr);
875 pci_dev_put(pci_root);
876}
877static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
878{
879 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
880 uint32_t ret_val = 0;
881 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
882 pci_write_config_dword(pci_root, 0xD0, mcr);
883 pci_read_config_dword(pci_root, 0xD4, &ret_val);
884 pci_dev_put(pci_root);
885 return ret_val;
886}
887static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
888{
889 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
890 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
891 pci_write_config_dword(pci_root, 0xD4, value);
892 pci_write_config_dword(pci_root, 0xD0, mcr);
893 pci_dev_put(pci_root);
894}
895
896static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
897{
898 struct drm_psb_private *dev_priv = dev->dev_private;
899 return ioread32(dev_priv->vdc_reg + reg);
900}
901
902#define REG_READ(reg) REGISTER_READ(dev, (reg))
903
904static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
905 uint32_t val)
906{
907 struct drm_psb_private *dev_priv = dev->dev_private;
908 iowrite32((val), dev_priv->vdc_reg + (reg));
909}
910
911#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
912
913static inline void REGISTER_WRITE16(struct drm_device *dev,
914 uint32_t reg, uint32_t val)
915{
916 struct drm_psb_private *dev_priv = dev->dev_private;
917 iowrite16((val), dev_priv->vdc_reg + (reg));
918}
919
920#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
921
922static inline void REGISTER_WRITE8(struct drm_device *dev,
923 uint32_t reg, uint32_t val)
924{
925 struct drm_psb_private *dev_priv = dev->dev_private;
926 iowrite8((val), dev_priv->vdc_reg + (reg));
927}
928
929#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
930
931#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
932#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
933
934/* #define TRAP_SGX_PM_FAULT 1 */
935#ifdef TRAP_SGX_PM_FAULT
936#define PSB_RSGX32(_offs) \
937({ \
938 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
939 printk(KERN_ERR \
940 "access sgx when it's off!! (READ) %s, %d\n", \
941 __FILE__, __LINE__); \
942 melay(1000); \
943 } \
944 ioread32(dev_priv->sgx_reg + (_offs)); \
945})
946#else
947#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
948#endif
949#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
950
951#define MSVDX_REG_DUMP 0
952
953#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
954#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
955
956#endif
Linux kernel - Deliverables
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