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gma500: Prevent endless loop in panel power up sequence
[deliverable/linux.git] / drivers / gpu / drm / gma500 / psb_drv.h
CommitLineData
5c49fd3a
AC		 1/**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20#ifndef _PSB_DRV_H_
21#define _PSB_DRV_H_
22
23#include <linux/kref.h>
24
25#include <drm/drmP.h>
26#include "drm_global.h"
27#include "gem_glue.h"
838fa588 28#include "gma_drm.h"
5c49fd3a
AC		 29#include "psb_reg.h"
30#include "psb_intel_drv.h"
31#include "gtt.h"
32#include "power.h"
d839ede4 33#include "opregion.h"
5c49fd3a
AC		 34#include "oaktrail.h"
35
36/* Append new drm mode definition here, align with libdrm definition */
37#define DRM_MODE_SCALE_NO_SCALE 2
38
39enum {
40 CHIP_PSB_8108 = 0, /* Poulsbo */
41 CHIP_PSB_8109 = 1, /* Poulsbo */
42 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
43 CHIP_MFLD_0130 = 3, /* Medfield */
44};
45
e036ba59 46#define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
5c49fd3a
AC		 47#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
48#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
49
50/*
51 * Driver definitions
52 */
53
54#define DRIVER_NAME "gma500"
55#define DRIVER_DESC "DRM driver for the Intel GMA500"
56
57#define PSB_DRM_DRIVER_DATE "2011-06-06"
58#define PSB_DRM_DRIVER_MAJOR 1
59#define PSB_DRM_DRIVER_MINOR 0
60#define PSB_DRM_DRIVER_PATCHLEVEL 0
61
62/*
63 * Hardware offsets
64 */
65#define PSB_VDC_OFFSET 0x00000000
66#define PSB_VDC_SIZE 0x000080000
67#define MRST_MMIO_SIZE 0x0000C0000
68#define MDFLD_MMIO_SIZE 0x000100000
69#define PSB_SGX_SIZE 0x8000
70#define PSB_SGX_OFFSET 0x00040000
71#define MRST_SGX_OFFSET 0x00080000
72/*
73 * PCI resource identifiers
74 */
75#define PSB_MMIO_RESOURCE 0
76#define PSB_GATT_RESOURCE 2
77#define PSB_GTT_RESOURCE 3
78/*
79 * PCI configuration
80 */
81#define PSB_GMCH_CTRL 0x52
82#define PSB_BSM 0x5C
83#define _PSB_GMCH_ENABLED 0x4
84#define PSB_PGETBL_CTL 0x2020
85#define _PSB_PGETBL_ENABLED 0x00000001
86#define PSB_SGX_2D_SLAVE_PORT 0x4000
87
88/* To get rid of */
89#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
90#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
91
92/*
93 * SGX side MMU definitions (these can probably go)
94 */
95
96/*
97 * Flags for external memory type field.
98 */
99#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
100#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
101#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
102/*
103 * PTE's and PDE's
104 */
105#define PSB_PDE_MASK 0x003FFFFF
106#define PSB_PDE_SHIFT 22
107#define PSB_PTE_SHIFT 12
108/*
109 * Cache control
110 */
111#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
112#define PSB_PTE_WO 0x0002 /* Write only */
113#define PSB_PTE_RO 0x0004 /* Read only */
114#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
115
116/*
117 * VDC registers and bits
118 */
119#define PSB_MSVDX_CLOCKGATING 0x2064
120#define PSB_TOPAZ_CLOCKGATING 0x2068
121#define PSB_HWSTAM 0x2098
122#define PSB_INSTPM 0x20C0
123#define PSB_INT_IDENTITY_R 0x20A4
d839ede4 124#define _PSB_IRQ_ASLE (1<<0)
5c49fd3a
AC		 125#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
126#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
127#define _PSB_DPST_PIPEB_FLAG (1<<4)
128#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
129#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
130#define _PSB_DPST_PIPEA_FLAG (1<<6)
131#define _PSB_PIPEA_EVENT_FLAG (1<<6)
132#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
133#define _MDFLD_MIPIA_FLAG (1<<16)
134#define _MDFLD_MIPIC_FLAG (1<<17)
68cb638f 135#define _PSB_IRQ_DISP_HOTSYNC (1<<17)
5c49fd3a
AC		 136#define _PSB_IRQ_SGX_FLAG (1<<18)
137#define _PSB_IRQ_MSVDX_FLAG (1<<19)
138#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
139
700e59f6
PJ		 140#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
141 _PSB_VSYNC_PIPEB_FLAG)
142
5c49fd3a
AC		 143/* This flag includes all the display IRQ bits excepts the vblank irqs. */
144#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
145 _MDFLD_PIPEB_EVENT_FLAG | \
146 _PSB_PIPEA_EVENT_FLAG | \
147 _PSB_VSYNC_PIPEA_FLAG | \
148 _MDFLD_MIPIA_FLAG | \
149 _MDFLD_MIPIC_FLAG)
150#define PSB_INT_IDENTITY_R 0x20A4
151#define PSB_INT_MASK_R 0x20A8
152#define PSB_INT_ENABLE_R 0x20A0
153
154#define _PSB_MMU_ER_MASK 0x0001FF00
155#define _PSB_MMU_ER_HOST (1 << 16)
156#define GPIOA 0x5010
157#define GPIOB 0x5014
158#define GPIOC 0x5018
159#define GPIOD 0x501c
160#define GPIOE 0x5020
161#define GPIOF 0x5024
162#define GPIOG 0x5028
163#define GPIOH 0x502c
164#define GPIO_CLOCK_DIR_MASK (1 << 0)
165#define GPIO_CLOCK_DIR_IN (0 << 1)
166#define GPIO_CLOCK_DIR_OUT (1 << 1)
167#define GPIO_CLOCK_VAL_MASK (1 << 2)
168#define GPIO_CLOCK_VAL_OUT (1 << 3)
169#define GPIO_CLOCK_VAL_IN (1 << 4)
170#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
171#define GPIO_DATA_DIR_MASK (1 << 8)
172#define GPIO_DATA_DIR_IN (0 << 9)
173#define GPIO_DATA_DIR_OUT (1 << 9)
174#define GPIO_DATA_VAL_MASK (1 << 10)
175#define GPIO_DATA_VAL_OUT (1 << 11)
176#define GPIO_DATA_VAL_IN (1 << 12)
177#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
178
179#define VCLK_DIVISOR_VGA0 0x6000
180#define VCLK_DIVISOR_VGA1 0x6004
181#define VCLK_POST_DIV 0x6010
182
183#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
184#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
185#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
186#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
187#define PSB_COMM_USER_IRQ (1024 >> 2)
188#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
189#define PSB_COMM_FW (2048 >> 2)
190
191#define PSB_UIRQ_VISTEST 1
192#define PSB_UIRQ_OOM_REPLY 2
193#define PSB_UIRQ_FIRE_TA_REPLY 3
194#define PSB_UIRQ_FIRE_RASTER_REPLY 4
195
196#define PSB_2D_SIZE (256*1024*1024)
197#define PSB_MAX_RELOC_PAGES 1024
198
199#define PSB_LOW_REG_OFFS 0x0204
200#define PSB_HIGH_REG_OFFS 0x0600
201
202#define PSB_NUM_VBLANKS 2
203
204
205#define PSB_2D_SIZE (256*1024*1024)
206#define PSB_MAX_RELOC_PAGES 1024
207
208#define PSB_LOW_REG_OFFS 0x0204
209#define PSB_HIGH_REG_OFFS 0x0600
210
211#define PSB_NUM_VBLANKS 2
212#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
213#define PSB_LID_DELAY (DRM_HZ / 10)
214
215#define MDFLD_PNW_B0 0x04
216#define MDFLD_PNW_C0 0x08
217
218#define MDFLD_DSR_2D_3D_0 (1 << 0)
219#define MDFLD_DSR_2D_3D_2 (1 << 1)
220#define MDFLD_DSR_CURSOR_0 (1 << 2)
221#define MDFLD_DSR_CURSOR_2 (1 << 3)
222#define MDFLD_DSR_OVERLAY_0 (1 << 4)
223#define MDFLD_DSR_OVERLAY_2 (1 << 5)
224#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
225#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
226#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
227#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
228
229#define MDFLD_DSR_RR 45
230#define MDFLD_DPU_ENABLE (1 << 31)
231#define MDFLD_DSR_FULLSCREEN (1 << 30)
232#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
233
234#define PSB_PWR_STATE_ON 1
235#define PSB_PWR_STATE_OFF 2
236
237#define PSB_PMPOLICY_NOPM 0
238#define PSB_PMPOLICY_CLOCKGATING 1
239#define PSB_PMPOLICY_POWERDOWN 2
240
241#define PSB_PMSTATE_POWERUP 0
242#define PSB_PMSTATE_CLOCKGATED 1
243#define PSB_PMSTATE_POWERDOWN 2
244#define PSB_PCIx_MSI_ADDR_LOC 0x94
245#define PSB_PCIx_MSI_DATA_LOC 0x98
246
247/* Medfield crystal settings */
248#define KSEL_CRYSTAL_19 1
249#define KSEL_BYPASS_19 5
250#define KSEL_BYPASS_25 6
251#define KSEL_BYPASS_83_100 7
252
253struct opregion_header;
254struct opregion_acpi;
255struct opregion_swsci;
256struct opregion_asle;
257
258struct psb_intel_opregion {
259 struct opregion_header *header;
260 struct opregion_acpi *acpi;
261 struct opregion_swsci *swsci;
262 struct opregion_asle *asle;
1fb28e9e 263 void *vbt;
d839ede4 264 u32 __iomem *lid_state;
5c49fd3a
AC		 265};
266
5736995b
PJ		 267struct sdvo_device_mapping {
268 u8 initialized;
269 u8 dvo_port;
270 u8 slave_addr;
271 u8 dvo_wiring;
272 u8 i2c_pin;
273 u8 i2c_speed;
274 u8 ddc_pin;
275};
276
5c0c1d50
PJ		 277struct intel_gmbus {
278 struct i2c_adapter adapter;
279 struct i2c_adapter *force_bit;
280 u32 reg0;
281};
282
8512e074
AC		 283/*
284 * Register offset maps
285 */
286
287struct psb_offset {
288 u32 fp0;
289 u32 fp1;
290 u32 cntr;
291 u32 conf;
292 u32 src;
293 u32 dpll;
294 u32 dpll_md;
295 u32 htotal;
296 u32 hblank;
297 u32 hsync;
298 u32 vtotal;
299 u32 vblank;
300 u32 vsync;
301 u32 stride;
302 u32 size;
303 u32 pos;
304 u32 surf;
305 u32 addr;
306 u32 base;
307 u32 status;
308 u32 linoff;
309 u32 tileoff;
310 u32 palette;
311};
312
648a8e34
AC		 313/*
314 * Register save state. This is used to hold the context when the
315 * device is powered off. In the case of Oaktrail this can (but does not
316 * yet) include screen blank. Operations occuring during the save
317 * update the register cache instead.
318 */
6256304b
AC		 319
320/*
321 * Common status for pipes.
322 */
323struct psb_pipe {
324 u32 fp0;
325 u32 fp1;
326 u32 cntr;
327 u32 conf;
328 u32 src;
329 u32 dpll;
330 u32 dpll_md;
331 u32 htotal;
332 u32 hblank;
333 u32 hsync;
334 u32 vtotal;
335 u32 vblank;
336 u32 vsync;
337 u32 stride;
338 u32 size;
339 u32 pos;
340 u32 base;
341 u32 surf;
342 u32 addr;
343 u32 status;
344 u32 linoff;
345 u32 tileoff;
346 u32 palette[256];
347};
348
648a8e34 349struct psb_state {
648a8e34
AC		 350 uint32_t saveVCLK_DIVISOR_VGA0;
351 uint32_t saveVCLK_DIVISOR_VGA1;
352 uint32_t saveVCLK_POST_DIV;
353 uint32_t saveVGACNTRL;
354 uint32_t saveADPA;
355 uint32_t saveLVDS;
356 uint32_t saveDVOA;
357 uint32_t saveDVOB;
358 uint32_t saveDVOC;
359 uint32_t savePP_ON;
360 uint32_t savePP_OFF;
361 uint32_t savePP_CONTROL;
362 uint32_t savePP_CYCLE;
363 uint32_t savePFIT_CONTROL;
648a8e34
AC		 364 uint32_t saveCLOCKGATING;
365 uint32_t saveDSPARB;
648a8e34
AC		 366 uint32_t savePFIT_AUTO_RATIOS;
367 uint32_t savePFIT_PGM_RATIOS;
368 uint32_t savePP_ON_DELAYS;
369 uint32_t savePP_OFF_DELAYS;
370 uint32_t savePP_DIVISOR;
648a8e34
AC		 371 uint32_t saveBCLRPAT_A;
372 uint32_t saveBCLRPAT_B;
648a8e34
AC		 373 uint32_t savePERF_MODE;
374 uint32_t saveDSPFW1;
375 uint32_t saveDSPFW2;
376 uint32_t saveDSPFW3;
377 uint32_t saveDSPFW4;
378 uint32_t saveDSPFW5;
379 uint32_t saveDSPFW6;
380 uint32_t saveCHICKENBIT;
381 uint32_t saveDSPACURSOR_CTRL;
382 uint32_t saveDSPBCURSOR_CTRL;
383 uint32_t saveDSPACURSOR_BASE;
384 uint32_t saveDSPBCURSOR_BASE;
385 uint32_t saveDSPACURSOR_POS;
386 uint32_t saveDSPBCURSOR_POS;
648a8e34
AC		 387 uint32_t saveOV_OVADD;
388 uint32_t saveOV_OGAMC0;
389 uint32_t saveOV_OGAMC1;
390 uint32_t saveOV_OGAMC2;
391 uint32_t saveOV_OGAMC3;
392 uint32_t saveOV_OGAMC4;
393 uint32_t saveOV_OGAMC5;
394 uint32_t saveOVC_OVADD;
395 uint32_t saveOVC_OGAMC0;
396 uint32_t saveOVC_OGAMC1;
397 uint32_t saveOVC_OGAMC2;
398 uint32_t saveOVC_OGAMC3;
399 uint32_t saveOVC_OGAMC4;
400 uint32_t saveOVC_OGAMC5;
401
402 /* DPST register save */
403 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
404 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
405 uint32_t savePWM_CONTROL_LOGIC;
406};
407
026abc33 408struct medfield_state {
026abc33 409 uint32_t saveMIPI;
026abc33
KS		 410 uint32_t saveMIPI_C;
411
412 uint32_t savePFIT_CONTROL;
413 uint32_t savePFIT_PGM_RATIOS;
414 uint32_t saveHDMIPHYMISCCTL;
415 uint32_t saveHDMIB_CONTROL;
416};
417
09016a11
AC		 418struct cdv_state {
419 uint32_t saveDSPCLK_GATE_D;
420 uint32_t saveRAMCLK_GATE_D;
421 uint32_t saveDSPARB;
422 uint32_t saveDSPFW[6];
423 uint32_t saveADPA;
424 uint32_t savePP_CONTROL;
425 uint32_t savePFIT_PGM_RATIOS;
426 uint32_t saveLVDS;
427 uint32_t savePFIT_CONTROL;
428 uint32_t savePP_ON_DELAYS;
429 uint32_t savePP_OFF_DELAYS;
430 uint32_t savePP_CYCLE;
431 uint32_t saveVGACNTRL;
432 uint32_t saveIER;
433 uint32_t saveIMR;
434 u8 saveLBB;
435};
436
c6265ff5 437struct psb_save_area {
6256304b 438 struct psb_pipe pipe[3];
c6265ff5
AC		 439 uint32_t saveBSM;
440 uint32_t saveVBT;
441 union {
442 struct psb_state psb;
026abc33 443 struct medfield_state mdfld;
09016a11 444 struct cdv_state cdv;
c6265ff5
AC		 445 };
446 uint32_t saveBLC_PWM_CTL2;
447 uint32_t saveBLC_PWM_CTL;
448};
449
5c49fd3a
AC		 450struct psb_ops;
451
04bd564f
AC		 452#define PSB_NUM_PIPE 3
453
5c49fd3a
AC		 454struct drm_psb_private {
455 struct drm_device *dev;
456 const struct psb_ops *ops;
8512e074 457 const struct psb_offset *regmap;
1fb28e9e
AC		 458
459 struct child_device_config *child_dev;
460 int child_dev_num;
5c49fd3a
AC		 461
462 struct psb_gtt gtt;
463
464 /* GTT Memory manager */
465 struct psb_gtt_mm *gtt_mm;
466 struct page *scratch_page;
eab37607 467 u32 __iomem *gtt_map;
5c49fd3a 468 uint32_t stolen_base;
37214ca0 469 u8 __iomem *vram_addr;
5c49fd3a
AC		 470 unsigned long vram_stolen_size;
471 int gtt_initialized;
472 u16 gmch_ctrl; /* Saved GTT setup */
473 u32 pge_ctl;
474
475 struct mutex gtt_mutex;
476 struct resource *gtt_mem; /* Our PCI resource */
477
478 struct psb_mmu_driver *mmu;
479 struct psb_mmu_pd *pf_pd;
480
481 /*
482 * Register base
483 */
484
846a6038
KS		 485 uint8_t __iomem *sgx_reg;
486 uint8_t __iomem *vdc_reg;
5c49fd3a
AC		 487 uint32_t gatt_free_offset;
488
489 /*
490 * Fencing / irq.
491 */
492
493 uint32_t vdc_irq_mask;
494 uint32_t pipestat[PSB_NUM_PIPE];
495
496 spinlock_t irqmask_lock;
497
498 /*
499 * Power
500 */
501
502 bool suspended;
503 bool display_power;
504 int display_count;
505
506 /*
507 * Modesetting
508 */
509 struct psb_intel_mode_device mode_dev;
4ab2c7f1 510 bool modeset; /* true if we have done the mode_device setup */
5c49fd3a
AC		 511
512 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
513 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
514 uint32_t num_pipe;
515
516 /*
517 * OSPM info (Power management base) (can go ?)
518 */
519 uint32_t ospm_base;
520
521 /*
522 * Sizes info
523 */
524
5c49fd3a
AC		 525 u32 fuse_reg_value;
526 u32 video_device_fuse;
527
528 /* PCI revision ID for B0:D2:F0 */
529 uint8_t platform_rev_id;
530
5c0c1d50
PJ		 531 /* gmbus */
532 struct intel_gmbus *gmbus;
533
5736995b
PJ		 534 /* Used by SDVO */
535 int crt_ddc_pin;
536 /* FIXME: The mappings should be parsed from bios but for now we can
537 pretend there are no mappings available */
538 struct sdvo_device_mapping sdvo_mappings[2];
539 u32 hotplug_supported_mask;
540 struct drm_property *broadcast_rgb_property;
541 struct drm_property *force_audio_property;
542
5c49fd3a
AC		 543 /*
544 * LVDS info
545 */
546 int backlight_duty_cycle; /* restore backlight to this value */
547 bool panel_wants_dither;
548 struct drm_display_mode *panel_fixed_mode;
549 struct drm_display_mode *lfp_lvds_vbt_mode;
550 struct drm_display_mode *sdvo_lvds_vbt_mode;
551
552 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
a12d6a07 553 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
5c49fd3a
AC		 554
555 /* Feature bits from the VBIOS */
556 unsigned int int_tv_support:1;
557 unsigned int lvds_dither:1;
558 unsigned int lvds_vbt:1;
559 unsigned int int_crt_support:1;
560 unsigned int lvds_use_ssc:1;
561 int lvds_ssc_freq;
562 bool is_lvds_on;
563 bool is_mipi_on;
564 u32 mipi_ctrl_display;
565
566 unsigned int core_freq;
567 uint32_t iLVDS_enable;
568
569 /* Runtime PM state */
570 int rpm_enabled;
571
572 /* MID specific */
4086b1e2 573 bool has_gct;
5c49fd3a
AC		 574 struct oaktrail_gct_data gct_data;
575
933315ac 576 /* Oaktrail HDMI state */
5c49fd3a 577 struct oaktrail_hdmi_dev *hdmi_priv;
933315ac 578
5c49fd3a
AC		 579 /*
580 * Register state
581 */
c6265ff5
AC		 582
583 struct psb_save_area regs;
584
5c49fd3a
AC		 585 /* MSI reg save */
586 uint32_t msi_addr;
587 uint32_t msi_data;
588
ae0a246a
AC		 589 /*
590 * Hotplug handling
591 */
592
593 struct work_struct hotplug_work;
5c49fd3a 594
5c49fd3a
AC		 595 /*
596 * LID-Switch
597 */
598 spinlock_t lid_lock;
599 struct timer_list lid_timer;
600 struct psb_intel_opregion opregion;
5c49fd3a
AC		 601 u32 lid_last_state;
602
603 /*
604 * Watchdog
605 */
606
607 uint32_t apm_reg;
608 uint16_t apm_base;
609
610 /*
611 * Used for modifying backlight from
612 * xrandr -- consider removing and using HAL instead
613 */
614 struct backlight_device *backlight_device;
615 struct drm_property *backlight_property;
616 uint32_t blc_adj1;
617 uint32_t blc_adj2;
618
619 void *fbdev;
620
621 /* 2D acceleration */
9242fe23 622 spinlock_t lock_2d;
026abc33
KS		 623
624 /*
625 * Panel brightness
626 */
627 int brightness;
628 int brightness_adjusted;
629
630 bool dsr_enable;
631 u32 dsr_fb_update;
632 bool dpi_panel_on[3];
633 void *dsi_configs[2];
634 u32 bpp;
635 u32 bpp2;
636
637 u32 pipeconf[3];
638 u32 dspcntr[3];
639
640 int mdfld_panel_id;
642c52fc
AC		 641
642 bool dplla_96mhz; /* DPLL data from the VBT */
5c49fd3a
AC		 643};
644
645
646/*
647 * Operations for each board type
648 */
649
650struct psb_ops {
651 const char *name;
652 unsigned int accel_2d:1;
653 int pipes; /* Number of output pipes */
654 int crtcs; /* Number of CRTCs */
655 int sgx_offset; /* Base offset of SGX device */
d235e64a
AC		 656 int hdmi_mask; /* Mask of HDMI CRTCs */
657 int lvds_mask; /* Mask of LVDS CRTCs */
5c49fd3a
AC		 658
659 /* Sub functions */
660 struct drm_crtc_helper_funcs const *crtc_helper;
661 struct drm_crtc_funcs const *crtc_funcs;
662
663 /* Setup hooks */
664 int (*chip_setup)(struct drm_device *dev);
665 void (*chip_teardown)(struct drm_device *dev);
d235e64a
AC		 666 /* Optional helper caller after modeset */
667 void (*errata)(struct drm_device *dev);
5c49fd3a
AC		 668
669 /* Display management hooks */
670 int (*output_init)(struct drm_device *dev);
68cb638f
AC		 671 int (*hotplug)(struct drm_device *dev);
672 void (*hotplug_enable)(struct drm_device *dev, bool on);
5c49fd3a
AC		 673 /* Power management hooks */
674 void (*init_pm)(struct drm_device *dev);
675 int (*save_regs)(struct drm_device *dev);
676 int (*restore_regs)(struct drm_device *dev);
677 int (*power_up)(struct drm_device *dev);
678 int (*power_down)(struct drm_device *dev);
679
680 void (*lvds_bl_power)(struct drm_device *dev, bool on);
681#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
682 /* Backlight */
683 int (*backlight_init)(struct drm_device *dev);
684#endif
685 int i2c_bus; /* I2C bus identifier for Moorestown */
686};
687
688
689
690struct psb_mmu_driver;
691
692extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
693extern int drm_pick_crtcs(struct drm_device *dev);
694
695static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
696{
697 return (struct drm_psb_private *) dev->dev_private;
698}
699
700/*
701 * MMU stuff.
702 */
703
704extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
705 int trap_pagefaults,
706 int invalid_type,
707 struct drm_psb_private *dev_priv);
708extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
709extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
710 *driver);
711extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
712 uint32_t gtt_start, uint32_t gtt_pages);
713extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
714 int trap_pagefaults,
715 int invalid_type);
716extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
717extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
718extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
719 unsigned long address,
720 uint32_t num_pages);
721extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
722 uint32_t start_pfn,
723 unsigned long address,
724 uint32_t num_pages, int type);
725extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
726 unsigned long *pfn);
727
728/*
729 * Enable / disable MMU for different requestors.
730 */
731
732
733extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
734extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
735 unsigned long address, uint32_t num_pages,
736 uint32_t desired_tile_stride,
737 uint32_t hw_tile_stride, int type);
738extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
739 unsigned long address, uint32_t num_pages,
740 uint32_t desired_tile_stride,
741 uint32_t hw_tile_stride);
742/*
743 *psb_irq.c
744 */
745
746extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
747extern int psb_irq_enable_dpst(struct drm_device *dev);
748extern int psb_irq_disable_dpst(struct drm_device *dev);
749extern void psb_irq_preinstall(struct drm_device *dev);
750extern int psb_irq_postinstall(struct drm_device *dev);
751extern void psb_irq_uninstall(struct drm_device *dev);
752extern void psb_irq_turn_on_dpst(struct drm_device *dev);
753extern void psb_irq_turn_off_dpst(struct drm_device *dev);
754
755extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
756extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
757extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
758extern int psb_enable_vblank(struct drm_device *dev, int crtc);
759extern void psb_disable_vblank(struct drm_device *dev, int crtc);
760void
761psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
762
763void
764psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
765
766extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
767
5c49fd3a
AC		 768/*
769 * framebuffer.c
770 */
771extern int psbfb_probed(struct drm_device *dev);
772extern int psbfb_remove(struct drm_device *dev,
773 struct drm_framebuffer *fb);
774/*
775 * accel_2d.c
776 */
777extern void psbfb_copyarea(struct fb_info *info,
778 const struct fb_copyarea *region);
779extern int psbfb_sync(struct fb_info *info);
780extern void psb_spank(struct drm_psb_private *dev_priv);
781
782/*
783 * psb_reset.c
784 */
785
786extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
787extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
788extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
789
790/* modesetting */
791extern void psb_modeset_init(struct drm_device *dev);
792extern void psb_modeset_cleanup(struct drm_device *dev);
793extern int psb_fbdev_init(struct drm_device *dev);
794
795/* backlight.c */
796int gma_backlight_init(struct drm_device *dev);
797void gma_backlight_exit(struct drm_device *dev);
798
799/* oaktrail_crtc.c */
800extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
801
802/* oaktrail_lvds.c */
803extern void oaktrail_lvds_init(struct drm_device *dev,
804 struct psb_intel_mode_device *mode_dev);
805
806/* psb_intel_display.c */
807extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
808extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
809
810/* psb_intel_lvds.c */
811extern const struct drm_connector_helper_funcs
812 psb_intel_lvds_connector_helper_funcs;
813extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
814
815/* gem.c */
816extern int psb_gem_init_object(struct drm_gem_object *obj);
817extern void psb_gem_free_object(struct drm_gem_object *obj);
818extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
819 struct drm_file *file);
820extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
821 struct drm_mode_create_dumb *args);
822extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
823 uint32_t handle);
824extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
825 uint32_t handle, uint64_t *offset);
826extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
827extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
828 struct drm_file *file);
829extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
830 struct drm_file *file);
831
832/* psb_device.c */
833extern const struct psb_ops psb_chip_ops;
834
835/* oaktrail_device.c */
836extern const struct psb_ops oaktrail_chip_ops;
837
026abc33
KS		 838/* mdlfd_device.c */
839extern const struct psb_ops mdfld_chip_ops;
840
5c49fd3a
AC		 841/* cdv_device.c */
842extern const struct psb_ops cdv_chip_ops;
843
844/*
845 * Debug print bits setting
846 */
847#define PSB_D_GENERAL (1 << 0)
848#define PSB_D_INIT (1 << 1)
849#define PSB_D_IRQ (1 << 2)
850#define PSB_D_ENTRY (1 << 3)
851/* debug the get H/V BP/FP count */
852#define PSB_D_HV (1 << 4)
853#define PSB_D_DBI_BF (1 << 5)
854#define PSB_D_PM (1 << 6)
855#define PSB_D_RENDER (1 << 7)
856#define PSB_D_REG (1 << 8)
857#define PSB_D_MSVDX (1 << 9)
858#define PSB_D_TOPAZ (1 << 10)
859
860extern int drm_psb_no_fb;
861extern int drm_idle_check_interval;
862
863/*
864 * Utilities
865 */
866
867static inline u32 MRST_MSG_READ32(uint port, uint offset)
868{
869 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
870 uint32_t ret_val = 0;
871 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
872 pci_write_config_dword(pci_root, 0xD0, mcr);
873 pci_read_config_dword(pci_root, 0xD4, &ret_val);
874 pci_dev_put(pci_root);
875 return ret_val;
876}
877static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
878{
879 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
880 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
881 pci_write_config_dword(pci_root, 0xD4, value);
882 pci_write_config_dword(pci_root, 0xD0, mcr);
883 pci_dev_put(pci_root);
884}
885static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
886{
887 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
888 uint32_t ret_val = 0;
889 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
890 pci_write_config_dword(pci_root, 0xD0, mcr);
891 pci_read_config_dword(pci_root, 0xD4, &ret_val);
892 pci_dev_put(pci_root);
893 return ret_val;
894}
895static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
896{
897 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
898 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
899 pci_write_config_dword(pci_root, 0xD4, value);
900 pci_write_config_dword(pci_root, 0xD0, mcr);
901 pci_dev_put(pci_root);
902}
903
904static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
905{
906 struct drm_psb_private *dev_priv = dev->dev_private;
907 return ioread32(dev_priv->vdc_reg + reg);
908}
909
910#define REG_READ(reg) REGISTER_READ(dev, (reg))
911
912static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
913 uint32_t val)
914{
915 struct drm_psb_private *dev_priv = dev->dev_private;
916 iowrite32((val), dev_priv->vdc_reg + (reg));
917}
918
919#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
920
921static inline void REGISTER_WRITE16(struct drm_device *dev,
922 uint32_t reg, uint32_t val)
923{
924 struct drm_psb_private *dev_priv = dev->dev_private;
925 iowrite16((val), dev_priv->vdc_reg + (reg));
926}
927
928#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
929
930static inline void REGISTER_WRITE8(struct drm_device *dev,
931 uint32_t reg, uint32_t val)
932{
933 struct drm_psb_private *dev_priv = dev->dev_private;
934 iowrite8((val), dev_priv->vdc_reg + (reg));
935}
936
937#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
938
939#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
940#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
941
942/* #define TRAP_SGX_PM_FAULT 1 */
943#ifdef TRAP_SGX_PM_FAULT
944#define PSB_RSGX32(_offs) \
945({ \
946 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
947 printk(KERN_ERR \
948 "access sgx when it's off!! (READ) %s, %d\n", \
949 __FILE__, __LINE__); \
950 melay(1000); \
951 } \
952 ioread32(dev_priv->sgx_reg + (_offs)); \
953})
954#else
955#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
956#endif
957#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
958
959#define MSVDX_REG_DUMP 0
960
961#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
962#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
963
964#endif
Linux kernel - Deliverables
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