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gma500: Clean up weirdness in the cdv mode test code
[deliverable/linux.git] / drivers / gpu / drm / gma500 / psb_drv.h
CommitLineData
5c49fd3a
AC		 1/**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20#ifndef _PSB_DRV_H_
21#define _PSB_DRV_H_
22
23#include <linux/kref.h>
24
25#include <drm/drmP.h>
26#include "drm_global.h"
27#include "gem_glue.h"
838fa588 28#include "gma_drm.h"
5c49fd3a
AC		 29#include "psb_reg.h"
30#include "psb_intel_drv.h"
31#include "gtt.h"
32#include "power.h"
33#include "oaktrail.h"
34
35/* Append new drm mode definition here, align with libdrm definition */
36#define DRM_MODE_SCALE_NO_SCALE 2
37
38enum {
39 CHIP_PSB_8108 = 0, /* Poulsbo */
40 CHIP_PSB_8109 = 1, /* Poulsbo */
41 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
42 CHIP_MFLD_0130 = 3, /* Medfield */
43};
44
e036ba59 45#define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
5c49fd3a
AC		 46#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
47#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
48
49/*
50 * Driver definitions
51 */
52
53#define DRIVER_NAME "gma500"
54#define DRIVER_DESC "DRM driver for the Intel GMA500"
55
56#define PSB_DRM_DRIVER_DATE "2011-06-06"
57#define PSB_DRM_DRIVER_MAJOR 1
58#define PSB_DRM_DRIVER_MINOR 0
59#define PSB_DRM_DRIVER_PATCHLEVEL 0
60
61/*
62 * Hardware offsets
63 */
64#define PSB_VDC_OFFSET 0x00000000
65#define PSB_VDC_SIZE 0x000080000
66#define MRST_MMIO_SIZE 0x0000C0000
67#define MDFLD_MMIO_SIZE 0x000100000
68#define PSB_SGX_SIZE 0x8000
69#define PSB_SGX_OFFSET 0x00040000
70#define MRST_SGX_OFFSET 0x00080000
71/*
72 * PCI resource identifiers
73 */
74#define PSB_MMIO_RESOURCE 0
75#define PSB_GATT_RESOURCE 2
76#define PSB_GTT_RESOURCE 3
77/*
78 * PCI configuration
79 */
80#define PSB_GMCH_CTRL 0x52
81#define PSB_BSM 0x5C
82#define _PSB_GMCH_ENABLED 0x4
83#define PSB_PGETBL_CTL 0x2020
84#define _PSB_PGETBL_ENABLED 0x00000001
85#define PSB_SGX_2D_SLAVE_PORT 0x4000
86
87/* To get rid of */
88#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
89#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
90
91/*
92 * SGX side MMU definitions (these can probably go)
93 */
94
95/*
96 * Flags for external memory type field.
97 */
98#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
99#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
100#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
101/*
102 * PTE's and PDE's
103 */
104#define PSB_PDE_MASK 0x003FFFFF
105#define PSB_PDE_SHIFT 22
106#define PSB_PTE_SHIFT 12
107/*
108 * Cache control
109 */
110#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
111#define PSB_PTE_WO 0x0002 /* Write only */
112#define PSB_PTE_RO 0x0004 /* Read only */
113#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
114
115/*
116 * VDC registers and bits
117 */
118#define PSB_MSVDX_CLOCKGATING 0x2064
119#define PSB_TOPAZ_CLOCKGATING 0x2068
120#define PSB_HWSTAM 0x2098
121#define PSB_INSTPM 0x20C0
122#define PSB_INT_IDENTITY_R 0x20A4
123#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
124#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
125#define _PSB_DPST_PIPEB_FLAG (1<<4)
126#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
127#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
128#define _PSB_DPST_PIPEA_FLAG (1<<6)
129#define _PSB_PIPEA_EVENT_FLAG (1<<6)
130#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
131#define _MDFLD_MIPIA_FLAG (1<<16)
132#define _MDFLD_MIPIC_FLAG (1<<17)
133#define _PSB_IRQ_SGX_FLAG (1<<18)
134#define _PSB_IRQ_MSVDX_FLAG (1<<19)
135#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
136
700e59f6
PJ		 137#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
138 _PSB_VSYNC_PIPEB_FLAG)
139
5c49fd3a
AC		 140/* This flag includes all the display IRQ bits excepts the vblank irqs. */
141#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
142 _MDFLD_PIPEB_EVENT_FLAG | \
143 _PSB_PIPEA_EVENT_FLAG | \
144 _PSB_VSYNC_PIPEA_FLAG | \
145 _MDFLD_MIPIA_FLAG | \
146 _MDFLD_MIPIC_FLAG)
147#define PSB_INT_IDENTITY_R 0x20A4
148#define PSB_INT_MASK_R 0x20A8
149#define PSB_INT_ENABLE_R 0x20A0
150
151#define _PSB_MMU_ER_MASK 0x0001FF00
152#define _PSB_MMU_ER_HOST (1 << 16)
153#define GPIOA 0x5010
154#define GPIOB 0x5014
155#define GPIOC 0x5018
156#define GPIOD 0x501c
157#define GPIOE 0x5020
158#define GPIOF 0x5024
159#define GPIOG 0x5028
160#define GPIOH 0x502c
161#define GPIO_CLOCK_DIR_MASK (1 << 0)
162#define GPIO_CLOCK_DIR_IN (0 << 1)
163#define GPIO_CLOCK_DIR_OUT (1 << 1)
164#define GPIO_CLOCK_VAL_MASK (1 << 2)
165#define GPIO_CLOCK_VAL_OUT (1 << 3)
166#define GPIO_CLOCK_VAL_IN (1 << 4)
167#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
168#define GPIO_DATA_DIR_MASK (1 << 8)
169#define GPIO_DATA_DIR_IN (0 << 9)
170#define GPIO_DATA_DIR_OUT (1 << 9)
171#define GPIO_DATA_VAL_MASK (1 << 10)
172#define GPIO_DATA_VAL_OUT (1 << 11)
173#define GPIO_DATA_VAL_IN (1 << 12)
174#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
175
176#define VCLK_DIVISOR_VGA0 0x6000
177#define VCLK_DIVISOR_VGA1 0x6004
178#define VCLK_POST_DIV 0x6010
179
180#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
181#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
182#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
183#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
184#define PSB_COMM_USER_IRQ (1024 >> 2)
185#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
186#define PSB_COMM_FW (2048 >> 2)
187
188#define PSB_UIRQ_VISTEST 1
189#define PSB_UIRQ_OOM_REPLY 2
190#define PSB_UIRQ_FIRE_TA_REPLY 3
191#define PSB_UIRQ_FIRE_RASTER_REPLY 4
192
193#define PSB_2D_SIZE (256*1024*1024)
194#define PSB_MAX_RELOC_PAGES 1024
195
196#define PSB_LOW_REG_OFFS 0x0204
197#define PSB_HIGH_REG_OFFS 0x0600
198
199#define PSB_NUM_VBLANKS 2
200
201
202#define PSB_2D_SIZE (256*1024*1024)
203#define PSB_MAX_RELOC_PAGES 1024
204
205#define PSB_LOW_REG_OFFS 0x0204
206#define PSB_HIGH_REG_OFFS 0x0600
207
208#define PSB_NUM_VBLANKS 2
209#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
210#define PSB_LID_DELAY (DRM_HZ / 10)
211
212#define MDFLD_PNW_B0 0x04
213#define MDFLD_PNW_C0 0x08
214
215#define MDFLD_DSR_2D_3D_0 (1 << 0)
216#define MDFLD_DSR_2D_3D_2 (1 << 1)
217#define MDFLD_DSR_CURSOR_0 (1 << 2)
218#define MDFLD_DSR_CURSOR_2 (1 << 3)
219#define MDFLD_DSR_OVERLAY_0 (1 << 4)
220#define MDFLD_DSR_OVERLAY_2 (1 << 5)
221#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
222#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
223#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
224#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
225
226#define MDFLD_DSR_RR 45
227#define MDFLD_DPU_ENABLE (1 << 31)
228#define MDFLD_DSR_FULLSCREEN (1 << 30)
229#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
230
231#define PSB_PWR_STATE_ON 1
232#define PSB_PWR_STATE_OFF 2
233
234#define PSB_PMPOLICY_NOPM 0
235#define PSB_PMPOLICY_CLOCKGATING 1
236#define PSB_PMPOLICY_POWERDOWN 2
237
238#define PSB_PMSTATE_POWERUP 0
239#define PSB_PMSTATE_CLOCKGATED 1
240#define PSB_PMSTATE_POWERDOWN 2
241#define PSB_PCIx_MSI_ADDR_LOC 0x94
242#define PSB_PCIx_MSI_DATA_LOC 0x98
243
244/* Medfield crystal settings */
245#define KSEL_CRYSTAL_19 1
246#define KSEL_BYPASS_19 5
247#define KSEL_BYPASS_25 6
248#define KSEL_BYPASS_83_100 7
249
250struct opregion_header;
251struct opregion_acpi;
252struct opregion_swsci;
253struct opregion_asle;
254
255struct psb_intel_opregion {
256 struct opregion_header *header;
257 struct opregion_acpi *acpi;
258 struct opregion_swsci *swsci;
259 struct opregion_asle *asle;
1fb28e9e 260 void *vbt;
5c49fd3a
AC		 261 int enabled;
262};
263
5736995b
PJ		 264struct sdvo_device_mapping {
265 u8 initialized;
266 u8 dvo_port;
267 u8 slave_addr;
268 u8 dvo_wiring;
269 u8 i2c_pin;
270 u8 i2c_speed;
271 u8 ddc_pin;
272};
273
5c0c1d50
PJ		 274struct intel_gmbus {
275 struct i2c_adapter adapter;
276 struct i2c_adapter *force_bit;
277 u32 reg0;
278};
279
648a8e34
AC		 280/*
281 * Register save state. This is used to hold the context when the
282 * device is powered off. In the case of Oaktrail this can (but does not
283 * yet) include screen blank. Operations occuring during the save
284 * update the register cache instead.
285 */
286struct psb_state {
287 uint32_t saveDSPACNTR;
288 uint32_t saveDSPBCNTR;
289 uint32_t savePIPEACONF;
290 uint32_t savePIPEBCONF;
291 uint32_t savePIPEASRC;
292 uint32_t savePIPEBSRC;
293 uint32_t saveFPA0;
294 uint32_t saveFPA1;
295 uint32_t saveDPLL_A;
296 uint32_t saveDPLL_A_MD;
297 uint32_t saveHTOTAL_A;
298 uint32_t saveHBLANK_A;
299 uint32_t saveHSYNC_A;
300 uint32_t saveVTOTAL_A;
301 uint32_t saveVBLANK_A;
302 uint32_t saveVSYNC_A;
303 uint32_t saveDSPASTRIDE;
304 uint32_t saveDSPASIZE;
305 uint32_t saveDSPAPOS;
306 uint32_t saveDSPABASE;
307 uint32_t saveDSPASURF;
308 uint32_t saveDSPASTATUS;
309 uint32_t saveFPB0;
310 uint32_t saveFPB1;
311 uint32_t saveDPLL_B;
312 uint32_t saveDPLL_B_MD;
313 uint32_t saveHTOTAL_B;
314 uint32_t saveHBLANK_B;
315 uint32_t saveHSYNC_B;
316 uint32_t saveVTOTAL_B;
317 uint32_t saveVBLANK_B;
318 uint32_t saveVSYNC_B;
319 uint32_t saveDSPBSTRIDE;
320 uint32_t saveDSPBSIZE;
321 uint32_t saveDSPBPOS;
322 uint32_t saveDSPBBASE;
323 uint32_t saveDSPBSURF;
324 uint32_t saveDSPBSTATUS;
325 uint32_t saveVCLK_DIVISOR_VGA0;
326 uint32_t saveVCLK_DIVISOR_VGA1;
327 uint32_t saveVCLK_POST_DIV;
328 uint32_t saveVGACNTRL;
329 uint32_t saveADPA;
330 uint32_t saveLVDS;
331 uint32_t saveDVOA;
332 uint32_t saveDVOB;
333 uint32_t saveDVOC;
334 uint32_t savePP_ON;
335 uint32_t savePP_OFF;
336 uint32_t savePP_CONTROL;
337 uint32_t savePP_CYCLE;
338 uint32_t savePFIT_CONTROL;
339 uint32_t savePaletteA[256];
340 uint32_t savePaletteB[256];
648a8e34
AC		 341 uint32_t saveCLOCKGATING;
342 uint32_t saveDSPARB;
343 uint32_t saveDSPATILEOFF;
344 uint32_t saveDSPBTILEOFF;
345 uint32_t saveDSPAADDR;
346 uint32_t saveDSPBADDR;
347 uint32_t savePFIT_AUTO_RATIOS;
348 uint32_t savePFIT_PGM_RATIOS;
349 uint32_t savePP_ON_DELAYS;
350 uint32_t savePP_OFF_DELAYS;
351 uint32_t savePP_DIVISOR;
648a8e34
AC		 352 uint32_t saveBCLRPAT_A;
353 uint32_t saveBCLRPAT_B;
354 uint32_t saveDSPALINOFF;
355 uint32_t saveDSPBLINOFF;
356 uint32_t savePERF_MODE;
357 uint32_t saveDSPFW1;
358 uint32_t saveDSPFW2;
359 uint32_t saveDSPFW3;
360 uint32_t saveDSPFW4;
361 uint32_t saveDSPFW5;
362 uint32_t saveDSPFW6;
363 uint32_t saveCHICKENBIT;
364 uint32_t saveDSPACURSOR_CTRL;
365 uint32_t saveDSPBCURSOR_CTRL;
366 uint32_t saveDSPACURSOR_BASE;
367 uint32_t saveDSPBCURSOR_BASE;
368 uint32_t saveDSPACURSOR_POS;
369 uint32_t saveDSPBCURSOR_POS;
370 uint32_t save_palette_a[256];
371 uint32_t save_palette_b[256];
372 uint32_t saveOV_OVADD;
373 uint32_t saveOV_OGAMC0;
374 uint32_t saveOV_OGAMC1;
375 uint32_t saveOV_OGAMC2;
376 uint32_t saveOV_OGAMC3;
377 uint32_t saveOV_OGAMC4;
378 uint32_t saveOV_OGAMC5;
379 uint32_t saveOVC_OVADD;
380 uint32_t saveOVC_OGAMC0;
381 uint32_t saveOVC_OGAMC1;
382 uint32_t saveOVC_OGAMC2;
383 uint32_t saveOVC_OGAMC3;
384 uint32_t saveOVC_OGAMC4;
385 uint32_t saveOVC_OGAMC5;
386
387 /* DPST register save */
388 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
389 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
390 uint32_t savePWM_CONTROL_LOGIC;
391};
392
026abc33
KS		 393struct medfield_state {
394 uint32_t saveDPLL_A;
395 uint32_t saveFPA0;
396 uint32_t savePIPEACONF;
397 uint32_t saveHTOTAL_A;
398 uint32_t saveHBLANK_A;
399 uint32_t saveHSYNC_A;
400 uint32_t saveVTOTAL_A;
401 uint32_t saveVBLANK_A;
402 uint32_t saveVSYNC_A;
403 uint32_t savePIPEASRC;
404 uint32_t saveDSPASTRIDE;
405 uint32_t saveDSPALINOFF;
406 uint32_t saveDSPATILEOFF;
407 uint32_t saveDSPASIZE;
408 uint32_t saveDSPAPOS;
409 uint32_t saveDSPASURF;
410 uint32_t saveDSPACNTR;
411 uint32_t saveDSPASTATUS;
412 uint32_t save_palette_a[256];
413 uint32_t saveMIPI;
414
415 uint32_t saveDPLL_B;
416 uint32_t saveFPB0;
417 uint32_t savePIPEBCONF;
418 uint32_t saveHTOTAL_B;
419 uint32_t saveHBLANK_B;
420 uint32_t saveHSYNC_B;
421 uint32_t saveVTOTAL_B;
422 uint32_t saveVBLANK_B;
423 uint32_t saveVSYNC_B;
424 uint32_t savePIPEBSRC;
425 uint32_t saveDSPBSTRIDE;
426 uint32_t saveDSPBLINOFF;
427 uint32_t saveDSPBTILEOFF;
428 uint32_t saveDSPBSIZE;
429 uint32_t saveDSPBPOS;
430 uint32_t saveDSPBSURF;
431 uint32_t saveDSPBCNTR;
432 uint32_t saveDSPBSTATUS;
433 uint32_t save_palette_b[256];
434
435 uint32_t savePIPECCONF;
436 uint32_t saveHTOTAL_C;
437 uint32_t saveHBLANK_C;
438 uint32_t saveHSYNC_C;
439 uint32_t saveVTOTAL_C;
440 uint32_t saveVBLANK_C;
441 uint32_t saveVSYNC_C;
442 uint32_t savePIPECSRC;
443 uint32_t saveDSPCSTRIDE;
444 uint32_t saveDSPCLINOFF;
445 uint32_t saveDSPCTILEOFF;
446 uint32_t saveDSPCSIZE;
447 uint32_t saveDSPCPOS;
448 uint32_t saveDSPCSURF;
449 uint32_t saveDSPCCNTR;
450 uint32_t saveDSPCSTATUS;
451 uint32_t save_palette_c[256];
452 uint32_t saveMIPI_C;
453
454 uint32_t savePFIT_CONTROL;
455 uint32_t savePFIT_PGM_RATIOS;
456 uint32_t saveHDMIPHYMISCCTL;
457 uint32_t saveHDMIB_CONTROL;
458};
459
09016a11
AC		 460struct cdv_state {
461 uint32_t saveDSPCLK_GATE_D;
462 uint32_t saveRAMCLK_GATE_D;
463 uint32_t saveDSPARB;
464 uint32_t saveDSPFW[6];
465 uint32_t saveADPA;
466 uint32_t savePP_CONTROL;
467 uint32_t savePFIT_PGM_RATIOS;
468 uint32_t saveLVDS;
469 uint32_t savePFIT_CONTROL;
470 uint32_t savePP_ON_DELAYS;
471 uint32_t savePP_OFF_DELAYS;
472 uint32_t savePP_CYCLE;
473 uint32_t saveVGACNTRL;
474 uint32_t saveIER;
475 uint32_t saveIMR;
476 u8 saveLBB;
477};
478
c6265ff5
AC		 479struct psb_save_area {
480 uint32_t saveBSM;
481 uint32_t saveVBT;
482 union {
483 struct psb_state psb;
026abc33 484 struct medfield_state mdfld;
09016a11 485 struct cdv_state cdv;
c6265ff5
AC		 486 };
487 uint32_t saveBLC_PWM_CTL2;
488 uint32_t saveBLC_PWM_CTL;
489};
490
5c49fd3a
AC		 491struct psb_ops;
492
04bd564f
AC		 493#define PSB_NUM_PIPE 3
494
5c49fd3a
AC		 495struct drm_psb_private {
496 struct drm_device *dev;
497 const struct psb_ops *ops;
1fb28e9e
AC		 498
499 struct child_device_config *child_dev;
500 int child_dev_num;
5c49fd3a
AC		 501
502 struct psb_gtt gtt;
503
504 /* GTT Memory manager */
505 struct psb_gtt_mm *gtt_mm;
506 struct page *scratch_page;
507 u32 *gtt_map;
508 uint32_t stolen_base;
509 void *vram_addr;
510 unsigned long vram_stolen_size;
511 int gtt_initialized;
512 u16 gmch_ctrl; /* Saved GTT setup */
513 u32 pge_ctl;
514
515 struct mutex gtt_mutex;
516 struct resource *gtt_mem; /* Our PCI resource */
517
518 struct psb_mmu_driver *mmu;
519 struct psb_mmu_pd *pf_pd;
520
521 /*
522 * Register base
523 */
524
525 uint8_t *sgx_reg;
526 uint8_t *vdc_reg;
527 uint32_t gatt_free_offset;
528
529 /*
530 * Fencing / irq.
531 */
532
533 uint32_t vdc_irq_mask;
534 uint32_t pipestat[PSB_NUM_PIPE];
535
536 spinlock_t irqmask_lock;
537
538 /*
539 * Power
540 */
541
542 bool suspended;
543 bool display_power;
544 int display_count;
545
546 /*
547 * Modesetting
548 */
549 struct psb_intel_mode_device mode_dev;
550
551 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
552 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
553 uint32_t num_pipe;
554
555 /*
556 * OSPM info (Power management base) (can go ?)
557 */
558 uint32_t ospm_base;
559
560 /*
561 * Sizes info
562 */
563
5c49fd3a
AC		 564 u32 fuse_reg_value;
565 u32 video_device_fuse;
566
567 /* PCI revision ID for B0:D2:F0 */
568 uint8_t platform_rev_id;
569
5c0c1d50
PJ		 570 /* gmbus */
571 struct intel_gmbus *gmbus;
572
5736995b
PJ		 573 /* Used by SDVO */
574 int crt_ddc_pin;
575 /* FIXME: The mappings should be parsed from bios but for now we can
576 pretend there are no mappings available */
577 struct sdvo_device_mapping sdvo_mappings[2];
578 u32 hotplug_supported_mask;
579 struct drm_property *broadcast_rgb_property;
580 struct drm_property *force_audio_property;
581
5c49fd3a
AC		 582 /*
583 * LVDS info
584 */
585 int backlight_duty_cycle; /* restore backlight to this value */
586 bool panel_wants_dither;
587 struct drm_display_mode *panel_fixed_mode;
588 struct drm_display_mode *lfp_lvds_vbt_mode;
589 struct drm_display_mode *sdvo_lvds_vbt_mode;
590
591 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
a12d6a07 592 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
5c49fd3a
AC		 593
594 /* Feature bits from the VBIOS */
595 unsigned int int_tv_support:1;
596 unsigned int lvds_dither:1;
597 unsigned int lvds_vbt:1;
598 unsigned int int_crt_support:1;
599 unsigned int lvds_use_ssc:1;
600 int lvds_ssc_freq;
601 bool is_lvds_on;
602 bool is_mipi_on;
603 u32 mipi_ctrl_display;
604
605 unsigned int core_freq;
606 uint32_t iLVDS_enable;
607
608 /* Runtime PM state */
609 int rpm_enabled;
610
611 /* MID specific */
612 struct oaktrail_vbt vbt_data;
613 struct oaktrail_gct_data gct_data;
614
933315ac 615 /* Oaktrail HDMI state */
5c49fd3a 616 struct oaktrail_hdmi_dev *hdmi_priv;
933315ac 617
5c49fd3a
AC		 618 /*
619 * Register state
620 */
c6265ff5
AC		 621
622 struct psb_save_area regs;
623
5c49fd3a
AC		 624 /* MSI reg save */
625 uint32_t msi_addr;
626 uint32_t msi_data;
627
5c49fd3a 628
5c49fd3a
AC		 629 /*
630 * LID-Switch
631 */
632 spinlock_t lid_lock;
633 struct timer_list lid_timer;
634 struct psb_intel_opregion opregion;
635 u32 *lid_state;
636 u32 lid_last_state;
637
638 /*
639 * Watchdog
640 */
641
642 uint32_t apm_reg;
643 uint16_t apm_base;
644
645 /*
646 * Used for modifying backlight from
647 * xrandr -- consider removing and using HAL instead
648 */
649 struct backlight_device *backlight_device;
650 struct drm_property *backlight_property;
651 uint32_t blc_adj1;
652 uint32_t blc_adj2;
653
654 void *fbdev;
655
656 /* 2D acceleration */
9242fe23 657 spinlock_t lock_2d;
026abc33
KS		 658
659 /*
660 * Panel brightness
661 */
662 int brightness;
663 int brightness_adjusted;
664
665 bool dsr_enable;
666 u32 dsr_fb_update;
667 bool dpi_panel_on[3];
668 void *dsi_configs[2];
669 u32 bpp;
670 u32 bpp2;
671
672 u32 pipeconf[3];
673 u32 dspcntr[3];
674
675 int mdfld_panel_id;
642c52fc
AC		 676
677 bool dplla_96mhz; /* DPLL data from the VBT */
5c49fd3a
AC		 678};
679
680
681/*
682 * Operations for each board type
683 */
684
685struct psb_ops {
686 const char *name;
687 unsigned int accel_2d:1;
688 int pipes; /* Number of output pipes */
689 int crtcs; /* Number of CRTCs */
690 int sgx_offset; /* Base offset of SGX device */
691
692 /* Sub functions */
693 struct drm_crtc_helper_funcs const *crtc_helper;
694 struct drm_crtc_funcs const *crtc_funcs;
695
696 /* Setup hooks */
697 int (*chip_setup)(struct drm_device *dev);
698 void (*chip_teardown)(struct drm_device *dev);
699
700 /* Display management hooks */
701 int (*output_init)(struct drm_device *dev);
702 /* Power management hooks */
703 void (*init_pm)(struct drm_device *dev);
704 int (*save_regs)(struct drm_device *dev);
705 int (*restore_regs)(struct drm_device *dev);
706 int (*power_up)(struct drm_device *dev);
707 int (*power_down)(struct drm_device *dev);
708
709 void (*lvds_bl_power)(struct drm_device *dev, bool on);
710#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
711 /* Backlight */
712 int (*backlight_init)(struct drm_device *dev);
713#endif
714 int i2c_bus; /* I2C bus identifier for Moorestown */
715};
716
717
718
719struct psb_mmu_driver;
720
721extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
722extern int drm_pick_crtcs(struct drm_device *dev);
723
724static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
725{
726 return (struct drm_psb_private *) dev->dev_private;
727}
728
729/*
730 * MMU stuff.
731 */
732
733extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
734 int trap_pagefaults,
735 int invalid_type,
736 struct drm_psb_private *dev_priv);
737extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
738extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
739 *driver);
740extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
741 uint32_t gtt_start, uint32_t gtt_pages);
742extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
743 int trap_pagefaults,
744 int invalid_type);
745extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
746extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
747extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
748 unsigned long address,
749 uint32_t num_pages);
750extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
751 uint32_t start_pfn,
752 unsigned long address,
753 uint32_t num_pages, int type);
754extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
755 unsigned long *pfn);
756
757/*
758 * Enable / disable MMU for different requestors.
759 */
760
761
762extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
763extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
764 unsigned long address, uint32_t num_pages,
765 uint32_t desired_tile_stride,
766 uint32_t hw_tile_stride, int type);
767extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
768 unsigned long address, uint32_t num_pages,
769 uint32_t desired_tile_stride,
770 uint32_t hw_tile_stride);
771/*
772 *psb_irq.c
773 */
774
775extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
776extern int psb_irq_enable_dpst(struct drm_device *dev);
777extern int psb_irq_disable_dpst(struct drm_device *dev);
778extern void psb_irq_preinstall(struct drm_device *dev);
779extern int psb_irq_postinstall(struct drm_device *dev);
780extern void psb_irq_uninstall(struct drm_device *dev);
781extern void psb_irq_turn_on_dpst(struct drm_device *dev);
782extern void psb_irq_turn_off_dpst(struct drm_device *dev);
783
784extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
785extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
786extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
787extern int psb_enable_vblank(struct drm_device *dev, int crtc);
788extern void psb_disable_vblank(struct drm_device *dev, int crtc);
789void
790psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
791
792void
793psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
794
795extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
796
797/*
798 * intel_opregion.c
799 */
800extern int gma_intel_opregion_init(struct drm_device *dev);
801extern int gma_intel_opregion_exit(struct drm_device *dev);
802
803/*
804 * framebuffer.c
805 */
806extern int psbfb_probed(struct drm_device *dev);
807extern int psbfb_remove(struct drm_device *dev,
808 struct drm_framebuffer *fb);
809/*
810 * accel_2d.c
811 */
812extern void psbfb_copyarea(struct fb_info *info,
813 const struct fb_copyarea *region);
814extern int psbfb_sync(struct fb_info *info);
815extern void psb_spank(struct drm_psb_private *dev_priv);
816
817/*
818 * psb_reset.c
819 */
820
821extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
822extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
823extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
824
825/* modesetting */
826extern void psb_modeset_init(struct drm_device *dev);
827extern void psb_modeset_cleanup(struct drm_device *dev);
828extern int psb_fbdev_init(struct drm_device *dev);
829
830/* backlight.c */
831int gma_backlight_init(struct drm_device *dev);
832void gma_backlight_exit(struct drm_device *dev);
833
834/* oaktrail_crtc.c */
835extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
836
837/* oaktrail_lvds.c */
838extern void oaktrail_lvds_init(struct drm_device *dev,
839 struct psb_intel_mode_device *mode_dev);
840
841/* psb_intel_display.c */
842extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
843extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
844
845/* psb_intel_lvds.c */
846extern const struct drm_connector_helper_funcs
847 psb_intel_lvds_connector_helper_funcs;
848extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
849
850/* gem.c */
851extern int psb_gem_init_object(struct drm_gem_object *obj);
852extern void psb_gem_free_object(struct drm_gem_object *obj);
853extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
854 struct drm_file *file);
855extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
856 struct drm_mode_create_dumb *args);
857extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
858 uint32_t handle);
859extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
860 uint32_t handle, uint64_t *offset);
861extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
862extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
863 struct drm_file *file);
864extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
865 struct drm_file *file);
866
867/* psb_device.c */
868extern const struct psb_ops psb_chip_ops;
869
870/* oaktrail_device.c */
871extern const struct psb_ops oaktrail_chip_ops;
872
026abc33
KS		 873/* mdlfd_device.c */
874extern const struct psb_ops mdfld_chip_ops;
875
5c49fd3a
AC		 876/* cdv_device.c */
877extern const struct psb_ops cdv_chip_ops;
878
879/*
880 * Debug print bits setting
881 */
882#define PSB_D_GENERAL (1 << 0)
883#define PSB_D_INIT (1 << 1)
884#define PSB_D_IRQ (1 << 2)
885#define PSB_D_ENTRY (1 << 3)
886/* debug the get H/V BP/FP count */
887#define PSB_D_HV (1 << 4)
888#define PSB_D_DBI_BF (1 << 5)
889#define PSB_D_PM (1 << 6)
890#define PSB_D_RENDER (1 << 7)
891#define PSB_D_REG (1 << 8)
892#define PSB_D_MSVDX (1 << 9)
893#define PSB_D_TOPAZ (1 << 10)
894
895extern int drm_psb_no_fb;
896extern int drm_idle_check_interval;
897
898/*
899 * Utilities
900 */
901
902static inline u32 MRST_MSG_READ32(uint port, uint offset)
903{
904 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
905 uint32_t ret_val = 0;
906 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
907 pci_write_config_dword(pci_root, 0xD0, mcr);
908 pci_read_config_dword(pci_root, 0xD4, &ret_val);
909 pci_dev_put(pci_root);
910 return ret_val;
911}
912static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
913{
914 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
915 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
916 pci_write_config_dword(pci_root, 0xD4, value);
917 pci_write_config_dword(pci_root, 0xD0, mcr);
918 pci_dev_put(pci_root);
919}
920static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
921{
922 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
923 uint32_t ret_val = 0;
924 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
925 pci_write_config_dword(pci_root, 0xD0, mcr);
926 pci_read_config_dword(pci_root, 0xD4, &ret_val);
927 pci_dev_put(pci_root);
928 return ret_val;
929}
930static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
931{
932 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
933 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
934 pci_write_config_dword(pci_root, 0xD4, value);
935 pci_write_config_dword(pci_root, 0xD0, mcr);
936 pci_dev_put(pci_root);
937}
938
939static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
940{
941 struct drm_psb_private *dev_priv = dev->dev_private;
942 return ioread32(dev_priv->vdc_reg + reg);
943}
944
945#define REG_READ(reg) REGISTER_READ(dev, (reg))
946
947static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
948 uint32_t val)
949{
950 struct drm_psb_private *dev_priv = dev->dev_private;
951 iowrite32((val), dev_priv->vdc_reg + (reg));
952}
953
954#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
955
956static inline void REGISTER_WRITE16(struct drm_device *dev,
957 uint32_t reg, uint32_t val)
958{
959 struct drm_psb_private *dev_priv = dev->dev_private;
960 iowrite16((val), dev_priv->vdc_reg + (reg));
961}
962
963#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
964
965static inline void REGISTER_WRITE8(struct drm_device *dev,
966 uint32_t reg, uint32_t val)
967{
968 struct drm_psb_private *dev_priv = dev->dev_private;
969 iowrite8((val), dev_priv->vdc_reg + (reg));
970}
971
972#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
973
974#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
975#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
976
977/* #define TRAP_SGX_PM_FAULT 1 */
978#ifdef TRAP_SGX_PM_FAULT
979#define PSB_RSGX32(_offs) \
980({ \
981 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
982 printk(KERN_ERR \
983 "access sgx when it's off!! (READ) %s, %d\n", \
984 __FILE__, __LINE__); \
985 melay(1000); \
986 } \
987 ioread32(dev_priv->sgx_reg + (_offs)); \
988})
989#else
990#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
991#endif
992#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
993
994#define MSVDX_REG_DUMP 0
995
996#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
997#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
998
999#endif
Linux kernel - Deliverables
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