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gma500: kill virtual mapping support
[deliverable/linux.git] / drivers / gpu / drm / gma500 / psb_drv.h
CommitLineData
5c49fd3a
AC		 1/**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20#ifndef _PSB_DRV_H_
21#define _PSB_DRV_H_
22
23#include <linux/kref.h>
24
25#include <drm/drmP.h>
26#include "drm_global.h"
27#include "gem_glue.h"
838fa588 28#include "gma_drm.h"
5c49fd3a
AC		 29#include "psb_reg.h"
30#include "psb_intel_drv.h"
31#include "gtt.h"
32#include "power.h"
33#include "oaktrail.h"
34
35/* Append new drm mode definition here, align with libdrm definition */
36#define DRM_MODE_SCALE_NO_SCALE 2
37
38enum {
39 CHIP_PSB_8108 = 0, /* Poulsbo */
40 CHIP_PSB_8109 = 1, /* Poulsbo */
41 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
42 CHIP_MFLD_0130 = 3, /* Medfield */
43};
44
45#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
46#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
47
48/*
49 * Driver definitions
50 */
51
52#define DRIVER_NAME "gma500"
53#define DRIVER_DESC "DRM driver for the Intel GMA500"
54
55#define PSB_DRM_DRIVER_DATE "2011-06-06"
56#define PSB_DRM_DRIVER_MAJOR 1
57#define PSB_DRM_DRIVER_MINOR 0
58#define PSB_DRM_DRIVER_PATCHLEVEL 0
59
60/*
61 * Hardware offsets
62 */
63#define PSB_VDC_OFFSET 0x00000000
64#define PSB_VDC_SIZE 0x000080000
65#define MRST_MMIO_SIZE 0x0000C0000
66#define MDFLD_MMIO_SIZE 0x000100000
67#define PSB_SGX_SIZE 0x8000
68#define PSB_SGX_OFFSET 0x00040000
69#define MRST_SGX_OFFSET 0x00080000
70/*
71 * PCI resource identifiers
72 */
73#define PSB_MMIO_RESOURCE 0
74#define PSB_GATT_RESOURCE 2
75#define PSB_GTT_RESOURCE 3
76/*
77 * PCI configuration
78 */
79#define PSB_GMCH_CTRL 0x52
80#define PSB_BSM 0x5C
81#define _PSB_GMCH_ENABLED 0x4
82#define PSB_PGETBL_CTL 0x2020
83#define _PSB_PGETBL_ENABLED 0x00000001
84#define PSB_SGX_2D_SLAVE_PORT 0x4000
85
86/* To get rid of */
87#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
88#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
89
90/*
91 * SGX side MMU definitions (these can probably go)
92 */
93
94/*
95 * Flags for external memory type field.
96 */
97#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
98#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
99#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
100/*
101 * PTE's and PDE's
102 */
103#define PSB_PDE_MASK 0x003FFFFF
104#define PSB_PDE_SHIFT 22
105#define PSB_PTE_SHIFT 12
106/*
107 * Cache control
108 */
109#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
110#define PSB_PTE_WO 0x0002 /* Write only */
111#define PSB_PTE_RO 0x0004 /* Read only */
112#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
113
114/*
115 * VDC registers and bits
116 */
117#define PSB_MSVDX_CLOCKGATING 0x2064
118#define PSB_TOPAZ_CLOCKGATING 0x2068
119#define PSB_HWSTAM 0x2098
120#define PSB_INSTPM 0x20C0
121#define PSB_INT_IDENTITY_R 0x20A4
122#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
123#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
124#define _PSB_DPST_PIPEB_FLAG (1<<4)
125#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
126#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
127#define _PSB_DPST_PIPEA_FLAG (1<<6)
128#define _PSB_PIPEA_EVENT_FLAG (1<<6)
129#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
130#define _MDFLD_MIPIA_FLAG (1<<16)
131#define _MDFLD_MIPIC_FLAG (1<<17)
132#define _PSB_IRQ_SGX_FLAG (1<<18)
133#define _PSB_IRQ_MSVDX_FLAG (1<<19)
134#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
135
136/* This flag includes all the display IRQ bits excepts the vblank irqs. */
137#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
138 _MDFLD_PIPEB_EVENT_FLAG | \
139 _PSB_PIPEA_EVENT_FLAG | \
140 _PSB_VSYNC_PIPEA_FLAG | \
141 _MDFLD_MIPIA_FLAG | \
142 _MDFLD_MIPIC_FLAG)
143#define PSB_INT_IDENTITY_R 0x20A4
144#define PSB_INT_MASK_R 0x20A8
145#define PSB_INT_ENABLE_R 0x20A0
146
147#define _PSB_MMU_ER_MASK 0x0001FF00
148#define _PSB_MMU_ER_HOST (1 << 16)
149#define GPIOA 0x5010
150#define GPIOB 0x5014
151#define GPIOC 0x5018
152#define GPIOD 0x501c
153#define GPIOE 0x5020
154#define GPIOF 0x5024
155#define GPIOG 0x5028
156#define GPIOH 0x502c
157#define GPIO_CLOCK_DIR_MASK (1 << 0)
158#define GPIO_CLOCK_DIR_IN (0 << 1)
159#define GPIO_CLOCK_DIR_OUT (1 << 1)
160#define GPIO_CLOCK_VAL_MASK (1 << 2)
161#define GPIO_CLOCK_VAL_OUT (1 << 3)
162#define GPIO_CLOCK_VAL_IN (1 << 4)
163#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
164#define GPIO_DATA_DIR_MASK (1 << 8)
165#define GPIO_DATA_DIR_IN (0 << 9)
166#define GPIO_DATA_DIR_OUT (1 << 9)
167#define GPIO_DATA_VAL_MASK (1 << 10)
168#define GPIO_DATA_VAL_OUT (1 << 11)
169#define GPIO_DATA_VAL_IN (1 << 12)
170#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
171
172#define VCLK_DIVISOR_VGA0 0x6000
173#define VCLK_DIVISOR_VGA1 0x6004
174#define VCLK_POST_DIV 0x6010
175
176#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
177#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
178#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
179#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
180#define PSB_COMM_USER_IRQ (1024 >> 2)
181#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
182#define PSB_COMM_FW (2048 >> 2)
183
184#define PSB_UIRQ_VISTEST 1
185#define PSB_UIRQ_OOM_REPLY 2
186#define PSB_UIRQ_FIRE_TA_REPLY 3
187#define PSB_UIRQ_FIRE_RASTER_REPLY 4
188
189#define PSB_2D_SIZE (256*1024*1024)
190#define PSB_MAX_RELOC_PAGES 1024
191
192#define PSB_LOW_REG_OFFS 0x0204
193#define PSB_HIGH_REG_OFFS 0x0600
194
195#define PSB_NUM_VBLANKS 2
196
197
198#define PSB_2D_SIZE (256*1024*1024)
199#define PSB_MAX_RELOC_PAGES 1024
200
201#define PSB_LOW_REG_OFFS 0x0204
202#define PSB_HIGH_REG_OFFS 0x0600
203
204#define PSB_NUM_VBLANKS 2
205#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
206#define PSB_LID_DELAY (DRM_HZ / 10)
207
208#define MDFLD_PNW_B0 0x04
209#define MDFLD_PNW_C0 0x08
210
211#define MDFLD_DSR_2D_3D_0 (1 << 0)
212#define MDFLD_DSR_2D_3D_2 (1 << 1)
213#define MDFLD_DSR_CURSOR_0 (1 << 2)
214#define MDFLD_DSR_CURSOR_2 (1 << 3)
215#define MDFLD_DSR_OVERLAY_0 (1 << 4)
216#define MDFLD_DSR_OVERLAY_2 (1 << 5)
217#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
218#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
219#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
220#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
221
222#define MDFLD_DSR_RR 45
223#define MDFLD_DPU_ENABLE (1 << 31)
224#define MDFLD_DSR_FULLSCREEN (1 << 30)
225#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
226
227#define PSB_PWR_STATE_ON 1
228#define PSB_PWR_STATE_OFF 2
229
230#define PSB_PMPOLICY_NOPM 0
231#define PSB_PMPOLICY_CLOCKGATING 1
232#define PSB_PMPOLICY_POWERDOWN 2
233
234#define PSB_PMSTATE_POWERUP 0
235#define PSB_PMSTATE_CLOCKGATED 1
236#define PSB_PMSTATE_POWERDOWN 2
237#define PSB_PCIx_MSI_ADDR_LOC 0x94
238#define PSB_PCIx_MSI_DATA_LOC 0x98
239
240/* Medfield crystal settings */
241#define KSEL_CRYSTAL_19 1
242#define KSEL_BYPASS_19 5
243#define KSEL_BYPASS_25 6
244#define KSEL_BYPASS_83_100 7
245
246struct opregion_header;
247struct opregion_acpi;
248struct opregion_swsci;
249struct opregion_asle;
250
251struct psb_intel_opregion {
252 struct opregion_header *header;
253 struct opregion_acpi *acpi;
254 struct opregion_swsci *swsci;
255 struct opregion_asle *asle;
256 int enabled;
257};
258
259struct psb_ops;
260
04bd564f
AC		 261#define PSB_NUM_PIPE 3
262
5c49fd3a
AC		 263struct drm_psb_private {
264 struct drm_device *dev;
265 const struct psb_ops *ops;
266
267 struct psb_gtt gtt;
268
269 /* GTT Memory manager */
270 struct psb_gtt_mm *gtt_mm;
271 struct page *scratch_page;
272 u32 *gtt_map;
273 uint32_t stolen_base;
274 void *vram_addr;
275 unsigned long vram_stolen_size;
276 int gtt_initialized;
277 u16 gmch_ctrl; /* Saved GTT setup */
278 u32 pge_ctl;
279
280 struct mutex gtt_mutex;
281 struct resource *gtt_mem; /* Our PCI resource */
282
283 struct psb_mmu_driver *mmu;
284 struct psb_mmu_pd *pf_pd;
285
286 /*
287 * Register base
288 */
289
290 uint8_t *sgx_reg;
291 uint8_t *vdc_reg;
292 uint32_t gatt_free_offset;
293
294 /*
295 * Fencing / irq.
296 */
297
298 uint32_t vdc_irq_mask;
299 uint32_t pipestat[PSB_NUM_PIPE];
300
301 spinlock_t irqmask_lock;
302
303 /*
304 * Power
305 */
306
307 bool suspended;
308 bool display_power;
309 int display_count;
310
311 /*
312 * Modesetting
313 */
314 struct psb_intel_mode_device mode_dev;
315
316 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
317 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
318 uint32_t num_pipe;
319
320 /*
321 * OSPM info (Power management base) (can go ?)
322 */
323 uint32_t ospm_base;
324
325 /*
326 * Sizes info
327 */
328
5c49fd3a
AC		 329 u32 fuse_reg_value;
330 u32 video_device_fuse;
331
332 /* PCI revision ID for B0:D2:F0 */
333 uint8_t platform_rev_id;
334
335 /*
336 * LVDS info
337 */
338 int backlight_duty_cycle; /* restore backlight to this value */
339 bool panel_wants_dither;
340 struct drm_display_mode *panel_fixed_mode;
341 struct drm_display_mode *lfp_lvds_vbt_mode;
342 struct drm_display_mode *sdvo_lvds_vbt_mode;
343
344 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
345 struct psb_intel_i2c_chan *lvds_i2c_bus;
346
347 /* Feature bits from the VBIOS */
348 unsigned int int_tv_support:1;
349 unsigned int lvds_dither:1;
350 unsigned int lvds_vbt:1;
351 unsigned int int_crt_support:1;
352 unsigned int lvds_use_ssc:1;
353 int lvds_ssc_freq;
354 bool is_lvds_on;
355 bool is_mipi_on;
356 u32 mipi_ctrl_display;
357
358 unsigned int core_freq;
359 uint32_t iLVDS_enable;
360
361 /* Runtime PM state */
362 int rpm_enabled;
363
364 /* MID specific */
365 struct oaktrail_vbt vbt_data;
366 struct oaktrail_gct_data gct_data;
367
368 /* MIPI Panel type etc */
369 int panel_id;
370 bool dual_mipi; /* dual display - DPI & DBI */
371 bool dpi_panel_on; /* The DPI panel power is on */
372 bool dpi_panel_on2; /* The DPI panel power is on */
373 bool dbi_panel_on; /* The DBI panel power is on */
374 bool dbi_panel_on2; /* The DBI panel power is on */
375 u32 dsr_fb_update; /* DSR FB update counter */
376
377 /* Moorestown HDMI state */
378 struct oaktrail_hdmi_dev *hdmi_priv;
379
380 /* Moorestown pipe config register value cache */
381 uint32_t pipeconf;
382 uint32_t pipeconf1;
383 uint32_t pipeconf2;
384
385 /* Moorestown plane control register value cache */
386 uint32_t dspcntr;
387 uint32_t dspcntr1;
388 uint32_t dspcntr2;
389
390 /* Moorestown MM backlight cache */
391 uint8_t saveBKLTCNT;
392 uint8_t saveBKLTREQ;
393 uint8_t saveBKLTBRTL;
394
395 /*
396 * Register state
397 */
398 uint32_t saveDSPACNTR;
399 uint32_t saveDSPBCNTR;
400 uint32_t savePIPEACONF;
401 uint32_t savePIPEBCONF;
402 uint32_t savePIPEASRC;
403 uint32_t savePIPEBSRC;
404 uint32_t saveFPA0;
405 uint32_t saveFPA1;
406 uint32_t saveDPLL_A;
407 uint32_t saveDPLL_A_MD;
408 uint32_t saveHTOTAL_A;
409 uint32_t saveHBLANK_A;
410 uint32_t saveHSYNC_A;
411 uint32_t saveVTOTAL_A;
412 uint32_t saveVBLANK_A;
413 uint32_t saveVSYNC_A;
414 uint32_t saveDSPASTRIDE;
415 uint32_t saveDSPASIZE;
416 uint32_t saveDSPAPOS;
417 uint32_t saveDSPABASE;
418 uint32_t saveDSPASURF;
419 uint32_t saveDSPASTATUS;
420 uint32_t saveFPB0;
421 uint32_t saveFPB1;
422 uint32_t saveDPLL_B;
423 uint32_t saveDPLL_B_MD;
424 uint32_t saveHTOTAL_B;
425 uint32_t saveHBLANK_B;
426 uint32_t saveHSYNC_B;
427 uint32_t saveVTOTAL_B;
428 uint32_t saveVBLANK_B;
429 uint32_t saveVSYNC_B;
430 uint32_t saveDSPBSTRIDE;
431 uint32_t saveDSPBSIZE;
432 uint32_t saveDSPBPOS;
433 uint32_t saveDSPBBASE;
434 uint32_t saveDSPBSURF;
435 uint32_t saveDSPBSTATUS;
436 uint32_t saveVCLK_DIVISOR_VGA0;
437 uint32_t saveVCLK_DIVISOR_VGA1;
438 uint32_t saveVCLK_POST_DIV;
439 uint32_t saveVGACNTRL;
440 uint32_t saveADPA;
441 uint32_t saveLVDS;
442 uint32_t saveDVOA;
443 uint32_t saveDVOB;
444 uint32_t saveDVOC;
445 uint32_t savePP_ON;
446 uint32_t savePP_OFF;
447 uint32_t savePP_CONTROL;
448 uint32_t savePP_CYCLE;
449 uint32_t savePFIT_CONTROL;
450 uint32_t savePaletteA[256];
451 uint32_t savePaletteB[256];
452 uint32_t saveBLC_PWM_CTL2;
453 uint32_t saveBLC_PWM_CTL;
454 uint32_t saveCLOCKGATING;
455 uint32_t saveDSPARB;
456 uint32_t saveDSPATILEOFF;
457 uint32_t saveDSPBTILEOFF;
458 uint32_t saveDSPAADDR;
459 uint32_t saveDSPBADDR;
460 uint32_t savePFIT_AUTO_RATIOS;
461 uint32_t savePFIT_PGM_RATIOS;
462 uint32_t savePP_ON_DELAYS;
463 uint32_t savePP_OFF_DELAYS;
464 uint32_t savePP_DIVISOR;
465 uint32_t saveBSM;
466 uint32_t saveVBT;
467 uint32_t saveBCLRPAT_A;
468 uint32_t saveBCLRPAT_B;
469 uint32_t saveDSPALINOFF;
470 uint32_t saveDSPBLINOFF;
471 uint32_t savePERF_MODE;
472 uint32_t saveDSPFW1;
473 uint32_t saveDSPFW2;
474 uint32_t saveDSPFW3;
475 uint32_t saveDSPFW4;
476 uint32_t saveDSPFW5;
477 uint32_t saveDSPFW6;
478 uint32_t saveCHICKENBIT;
479 uint32_t saveDSPACURSOR_CTRL;
480 uint32_t saveDSPBCURSOR_CTRL;
481 uint32_t saveDSPACURSOR_BASE;
482 uint32_t saveDSPBCURSOR_BASE;
483 uint32_t saveDSPACURSOR_POS;
484 uint32_t saveDSPBCURSOR_POS;
485 uint32_t save_palette_a[256];
486 uint32_t save_palette_b[256];
487 uint32_t saveOV_OVADD;
488 uint32_t saveOV_OGAMC0;
489 uint32_t saveOV_OGAMC1;
490 uint32_t saveOV_OGAMC2;
491 uint32_t saveOV_OGAMC3;
492 uint32_t saveOV_OGAMC4;
493 uint32_t saveOV_OGAMC5;
494 uint32_t saveOVC_OVADD;
495 uint32_t saveOVC_OGAMC0;
496 uint32_t saveOVC_OGAMC1;
497 uint32_t saveOVC_OGAMC2;
498 uint32_t saveOVC_OGAMC3;
499 uint32_t saveOVC_OGAMC4;
500 uint32_t saveOVC_OGAMC5;
501
502 /* MSI reg save */
503 uint32_t msi_addr;
504 uint32_t msi_data;
505
506 /* Medfield specific register save state */
507 uint32_t saveHDMIPHYMISCCTL;
508 uint32_t saveHDMIB_CONTROL;
509 uint32_t saveDSPCCNTR;
510 uint32_t savePIPECCONF;
511 uint32_t savePIPECSRC;
512 uint32_t saveHTOTAL_C;
513 uint32_t saveHBLANK_C;
514 uint32_t saveHSYNC_C;
515 uint32_t saveVTOTAL_C;
516 uint32_t saveVBLANK_C;
517 uint32_t saveVSYNC_C;
518 uint32_t saveDSPCSTRIDE;
519 uint32_t saveDSPCSIZE;
520 uint32_t saveDSPCPOS;
521 uint32_t saveDSPCSURF;
522 uint32_t saveDSPCSTATUS;
523 uint32_t saveDSPCLINOFF;
524 uint32_t saveDSPCTILEOFF;
525 uint32_t saveDSPCCURSOR_CTRL;
526 uint32_t saveDSPCCURSOR_BASE;
527 uint32_t saveDSPCCURSOR_POS;
528 uint32_t save_palette_c[256];
529 uint32_t saveOV_OVADD_C;
530 uint32_t saveOV_OGAMC0_C;
531 uint32_t saveOV_OGAMC1_C;
532 uint32_t saveOV_OGAMC2_C;
533 uint32_t saveOV_OGAMC3_C;
534 uint32_t saveOV_OGAMC4_C;
535 uint32_t saveOV_OGAMC5_C;
536
537 /* DSI register save */
538 uint32_t saveDEVICE_READY_REG;
539 uint32_t saveINTR_EN_REG;
540 uint32_t saveDSI_FUNC_PRG_REG;
541 uint32_t saveHS_TX_TIMEOUT_REG;
542 uint32_t saveLP_RX_TIMEOUT_REG;
543 uint32_t saveTURN_AROUND_TIMEOUT_REG;
544 uint32_t saveDEVICE_RESET_REG;
545 uint32_t saveDPI_RESOLUTION_REG;
546 uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
547 uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
548 uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
549 uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
550 uint32_t saveVERT_SYNC_PAD_COUNT_REG;
551 uint32_t saveVERT_BACK_PORCH_COUNT_REG;
552 uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
553 uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
554 uint32_t saveINIT_COUNT_REG;
555 uint32_t saveMAX_RET_PAK_REG;
556 uint32_t saveVIDEO_FMT_REG;
557 uint32_t saveEOT_DISABLE_REG;
558 uint32_t saveLP_BYTECLK_REG;
559 uint32_t saveHS_LS_DBI_ENABLE_REG;
560 uint32_t saveTXCLKESC_REG;
561 uint32_t saveDPHY_PARAM_REG;
562 uint32_t saveMIPI_CONTROL_REG;
563 uint32_t saveMIPI;
564 uint32_t saveMIPI_C;
565
566 /* DPST register save */
567 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
568 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
569 uint32_t savePWM_CONTROL_LOGIC;
570
571 /*
572 * DSI info.
573 */
574 void * dbi_dsr_info;
575 void * dbi_dpu_info;
576 void * dsi_configs[2];
577 /*
578 * LID-Switch
579 */
580 spinlock_t lid_lock;
581 struct timer_list lid_timer;
582 struct psb_intel_opregion opregion;
583 u32 *lid_state;
584 u32 lid_last_state;
585
586 /*
587 * Watchdog
588 */
589
590 uint32_t apm_reg;
591 uint16_t apm_base;
592
593 /*
594 * Used for modifying backlight from
595 * xrandr -- consider removing and using HAL instead
596 */
597 struct backlight_device *backlight_device;
598 struct drm_property *backlight_property;
599 uint32_t blc_adj1;
600 uint32_t blc_adj2;
601
602 void *fbdev;
603
604 /* 2D acceleration */
605 struct mutex mutex_2d;
606};
607
608
609/*
610 * Operations for each board type
611 */
612
613struct psb_ops {
614 const char *name;
615 unsigned int accel_2d:1;
616 int pipes; /* Number of output pipes */
617 int crtcs; /* Number of CRTCs */
618 int sgx_offset; /* Base offset of SGX device */
619
620 /* Sub functions */
621 struct drm_crtc_helper_funcs const *crtc_helper;
622 struct drm_crtc_funcs const *crtc_funcs;
623
624 /* Setup hooks */
625 int (*chip_setup)(struct drm_device *dev);
626 void (*chip_teardown)(struct drm_device *dev);
627
628 /* Display management hooks */
629 int (*output_init)(struct drm_device *dev);
630 /* Power management hooks */
631 void (*init_pm)(struct drm_device *dev);
632 int (*save_regs)(struct drm_device *dev);
633 int (*restore_regs)(struct drm_device *dev);
634 int (*power_up)(struct drm_device *dev);
635 int (*power_down)(struct drm_device *dev);
636
637 void (*lvds_bl_power)(struct drm_device *dev, bool on);
638#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
639 /* Backlight */
640 int (*backlight_init)(struct drm_device *dev);
641#endif
642 int i2c_bus; /* I2C bus identifier for Moorestown */
643};
644
645
646
647struct psb_mmu_driver;
648
649extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
650extern int drm_pick_crtcs(struct drm_device *dev);
651
652static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
653{
654 return (struct drm_psb_private *) dev->dev_private;
655}
656
657/*
658 * MMU stuff.
659 */
660
661extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
662 int trap_pagefaults,
663 int invalid_type,
664 struct drm_psb_private *dev_priv);
665extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
666extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
667 *driver);
668extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
669 uint32_t gtt_start, uint32_t gtt_pages);
670extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
671 int trap_pagefaults,
672 int invalid_type);
673extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
674extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
675extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
676 unsigned long address,
677 uint32_t num_pages);
678extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
679 uint32_t start_pfn,
680 unsigned long address,
681 uint32_t num_pages, int type);
682extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
683 unsigned long *pfn);
684
685/*
686 * Enable / disable MMU for different requestors.
687 */
688
689
690extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
691extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
692 unsigned long address, uint32_t num_pages,
693 uint32_t desired_tile_stride,
694 uint32_t hw_tile_stride, int type);
695extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
696 unsigned long address, uint32_t num_pages,
697 uint32_t desired_tile_stride,
698 uint32_t hw_tile_stride);
699/*
700 *psb_irq.c
701 */
702
703extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
704extern int psb_irq_enable_dpst(struct drm_device *dev);
705extern int psb_irq_disable_dpst(struct drm_device *dev);
706extern void psb_irq_preinstall(struct drm_device *dev);
707extern int psb_irq_postinstall(struct drm_device *dev);
708extern void psb_irq_uninstall(struct drm_device *dev);
709extern void psb_irq_turn_on_dpst(struct drm_device *dev);
710extern void psb_irq_turn_off_dpst(struct drm_device *dev);
711
712extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
713extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
714extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
715extern int psb_enable_vblank(struct drm_device *dev, int crtc);
716extern void psb_disable_vblank(struct drm_device *dev, int crtc);
717void
718psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
719
720void
721psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
722
723extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
724
725/*
726 * intel_opregion.c
727 */
728extern int gma_intel_opregion_init(struct drm_device *dev);
729extern int gma_intel_opregion_exit(struct drm_device *dev);
730
731/*
732 * framebuffer.c
733 */
734extern int psbfb_probed(struct drm_device *dev);
735extern int psbfb_remove(struct drm_device *dev,
736 struct drm_framebuffer *fb);
737/*
738 * accel_2d.c
739 */
740extern void psbfb_copyarea(struct fb_info *info,
741 const struct fb_copyarea *region);
742extern int psbfb_sync(struct fb_info *info);
743extern void psb_spank(struct drm_psb_private *dev_priv);
744
745/*
746 * psb_reset.c
747 */
748
749extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
750extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
751extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
752
753/* modesetting */
754extern void psb_modeset_init(struct drm_device *dev);
755extern void psb_modeset_cleanup(struct drm_device *dev);
756extern int psb_fbdev_init(struct drm_device *dev);
757
758/* backlight.c */
759int gma_backlight_init(struct drm_device *dev);
760void gma_backlight_exit(struct drm_device *dev);
761
762/* oaktrail_crtc.c */
763extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
764
765/* oaktrail_lvds.c */
766extern void oaktrail_lvds_init(struct drm_device *dev,
767 struct psb_intel_mode_device *mode_dev);
768
769/* psb_intel_display.c */
770extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
771extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
772
773/* psb_intel_lvds.c */
774extern const struct drm_connector_helper_funcs
775 psb_intel_lvds_connector_helper_funcs;
776extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
777
778/* gem.c */
779extern int psb_gem_init_object(struct drm_gem_object *obj);
780extern void psb_gem_free_object(struct drm_gem_object *obj);
781extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
782 struct drm_file *file);
783extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
784 struct drm_mode_create_dumb *args);
785extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
786 uint32_t handle);
787extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
788 uint32_t handle, uint64_t *offset);
789extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
790extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
791 struct drm_file *file);
792extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
793 struct drm_file *file);
794
795/* psb_device.c */
796extern const struct psb_ops psb_chip_ops;
797
798/* oaktrail_device.c */
799extern const struct psb_ops oaktrail_chip_ops;
800
801/* cdv_device.c */
802extern const struct psb_ops cdv_chip_ops;
803
804/*
805 * Debug print bits setting
806 */
807#define PSB_D_GENERAL (1 << 0)
808#define PSB_D_INIT (1 << 1)
809#define PSB_D_IRQ (1 << 2)
810#define PSB_D_ENTRY (1 << 3)
811/* debug the get H/V BP/FP count */
812#define PSB_D_HV (1 << 4)
813#define PSB_D_DBI_BF (1 << 5)
814#define PSB_D_PM (1 << 6)
815#define PSB_D_RENDER (1 << 7)
816#define PSB_D_REG (1 << 8)
817#define PSB_D_MSVDX (1 << 9)
818#define PSB_D_TOPAZ (1 << 10)
819
820extern int drm_psb_no_fb;
821extern int drm_idle_check_interval;
822
823/*
824 * Utilities
825 */
826
827static inline u32 MRST_MSG_READ32(uint port, uint offset)
828{
829 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
830 uint32_t ret_val = 0;
831 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
832 pci_write_config_dword(pci_root, 0xD0, mcr);
833 pci_read_config_dword(pci_root, 0xD4, &ret_val);
834 pci_dev_put(pci_root);
835 return ret_val;
836}
837static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
838{
839 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
840 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
841 pci_write_config_dword(pci_root, 0xD4, value);
842 pci_write_config_dword(pci_root, 0xD0, mcr);
843 pci_dev_put(pci_root);
844}
845static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
846{
847 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
848 uint32_t ret_val = 0;
849 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
850 pci_write_config_dword(pci_root, 0xD0, mcr);
851 pci_read_config_dword(pci_root, 0xD4, &ret_val);
852 pci_dev_put(pci_root);
853 return ret_val;
854}
855static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
856{
857 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
858 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
859 pci_write_config_dword(pci_root, 0xD4, value);
860 pci_write_config_dword(pci_root, 0xD0, mcr);
861 pci_dev_put(pci_root);
862}
863
864static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
865{
866 struct drm_psb_private *dev_priv = dev->dev_private;
867 return ioread32(dev_priv->vdc_reg + reg);
868}
869
870#define REG_READ(reg) REGISTER_READ(dev, (reg))
871
872static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
873 uint32_t val)
874{
875 struct drm_psb_private *dev_priv = dev->dev_private;
876 iowrite32((val), dev_priv->vdc_reg + (reg));
877}
878
879#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
880
881static inline void REGISTER_WRITE16(struct drm_device *dev,
882 uint32_t reg, uint32_t val)
883{
884 struct drm_psb_private *dev_priv = dev->dev_private;
885 iowrite16((val), dev_priv->vdc_reg + (reg));
886}
887
888#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
889
890static inline void REGISTER_WRITE8(struct drm_device *dev,
891 uint32_t reg, uint32_t val)
892{
893 struct drm_psb_private *dev_priv = dev->dev_private;
894 iowrite8((val), dev_priv->vdc_reg + (reg));
895}
896
897#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
898
899#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
900#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
901
902/* #define TRAP_SGX_PM_FAULT 1 */
903#ifdef TRAP_SGX_PM_FAULT
904#define PSB_RSGX32(_offs) \
905({ \
906 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
907 printk(KERN_ERR \
908 "access sgx when it's off!! (READ) %s, %d\n", \
909 __FILE__, __LINE__); \
910 melay(1000); \
911 } \
912 ioread32(dev_priv->sgx_reg + (_offs)); \
913})
914#else
915#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
916#endif
917#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
918
919#define MSVDX_REG_DUMP 0
920
921#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
922#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
923
924#endif
Linux kernel - Deliverables
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