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gma500: Clean up from the psb_pipe structure
[deliverable/linux.git] / drivers / gpu / drm / gma500 / psb_drv.h
CommitLineData
5c49fd3a
AC		 1/**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20#ifndef _PSB_DRV_H_
21#define _PSB_DRV_H_
22
23#include <linux/kref.h>
24
25#include <drm/drmP.h>
26#include "drm_global.h"
27#include "gem_glue.h"
838fa588 28#include "gma_drm.h"
5c49fd3a
AC		 29#include "psb_reg.h"
30#include "psb_intel_drv.h"
31#include "gtt.h"
32#include "power.h"
d839ede4 33#include "opregion.h"
5c49fd3a
AC		 34#include "oaktrail.h"
35
36/* Append new drm mode definition here, align with libdrm definition */
37#define DRM_MODE_SCALE_NO_SCALE 2
38
39enum {
40 CHIP_PSB_8108 = 0, /* Poulsbo */
41 CHIP_PSB_8109 = 1, /* Poulsbo */
42 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
43 CHIP_MFLD_0130 = 3, /* Medfield */
44};
45
e036ba59 46#define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
5c49fd3a
AC		 47#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
48#define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
49
50/*
51 * Driver definitions
52 */
53
54#define DRIVER_NAME "gma500"
55#define DRIVER_DESC "DRM driver for the Intel GMA500"
56
57#define PSB_DRM_DRIVER_DATE "2011-06-06"
58#define PSB_DRM_DRIVER_MAJOR 1
59#define PSB_DRM_DRIVER_MINOR 0
60#define PSB_DRM_DRIVER_PATCHLEVEL 0
61
62/*
63 * Hardware offsets
64 */
65#define PSB_VDC_OFFSET 0x00000000
66#define PSB_VDC_SIZE 0x000080000
67#define MRST_MMIO_SIZE 0x0000C0000
68#define MDFLD_MMIO_SIZE 0x000100000
69#define PSB_SGX_SIZE 0x8000
70#define PSB_SGX_OFFSET 0x00040000
71#define MRST_SGX_OFFSET 0x00080000
72/*
73 * PCI resource identifiers
74 */
75#define PSB_MMIO_RESOURCE 0
76#define PSB_GATT_RESOURCE 2
77#define PSB_GTT_RESOURCE 3
78/*
79 * PCI configuration
80 */
81#define PSB_GMCH_CTRL 0x52
82#define PSB_BSM 0x5C
83#define _PSB_GMCH_ENABLED 0x4
84#define PSB_PGETBL_CTL 0x2020
85#define _PSB_PGETBL_ENABLED 0x00000001
86#define PSB_SGX_2D_SLAVE_PORT 0x4000
87
88/* To get rid of */
89#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
90#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
91
92/*
93 * SGX side MMU definitions (these can probably go)
94 */
95
96/*
97 * Flags for external memory type field.
98 */
99#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
100#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
101#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
102/*
103 * PTE's and PDE's
104 */
105#define PSB_PDE_MASK 0x003FFFFF
106#define PSB_PDE_SHIFT 22
107#define PSB_PTE_SHIFT 12
108/*
109 * Cache control
110 */
111#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
112#define PSB_PTE_WO 0x0002 /* Write only */
113#define PSB_PTE_RO 0x0004 /* Read only */
114#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
115
116/*
117 * VDC registers and bits
118 */
119#define PSB_MSVDX_CLOCKGATING 0x2064
120#define PSB_TOPAZ_CLOCKGATING 0x2068
121#define PSB_HWSTAM 0x2098
122#define PSB_INSTPM 0x20C0
123#define PSB_INT_IDENTITY_R 0x20A4
d839ede4 124#define _PSB_IRQ_ASLE (1<<0)
5c49fd3a
AC		 125#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
126#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
127#define _PSB_DPST_PIPEB_FLAG (1<<4)
128#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
129#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
130#define _PSB_DPST_PIPEA_FLAG (1<<6)
131#define _PSB_PIPEA_EVENT_FLAG (1<<6)
132#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
133#define _MDFLD_MIPIA_FLAG (1<<16)
134#define _MDFLD_MIPIC_FLAG (1<<17)
68cb638f 135#define _PSB_IRQ_DISP_HOTSYNC (1<<17)
5c49fd3a
AC		 136#define _PSB_IRQ_SGX_FLAG (1<<18)
137#define _PSB_IRQ_MSVDX_FLAG (1<<19)
138#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
139
700e59f6
PJ		 140#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
141 _PSB_VSYNC_PIPEB_FLAG)
142
5c49fd3a
AC		 143/* This flag includes all the display IRQ bits excepts the vblank irqs. */
144#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
145 _MDFLD_PIPEB_EVENT_FLAG | \
146 _PSB_PIPEA_EVENT_FLAG | \
147 _PSB_VSYNC_PIPEA_FLAG | \
148 _MDFLD_MIPIA_FLAG | \
149 _MDFLD_MIPIC_FLAG)
150#define PSB_INT_IDENTITY_R 0x20A4
151#define PSB_INT_MASK_R 0x20A8
152#define PSB_INT_ENABLE_R 0x20A0
153
154#define _PSB_MMU_ER_MASK 0x0001FF00
155#define _PSB_MMU_ER_HOST (1 << 16)
156#define GPIOA 0x5010
157#define GPIOB 0x5014
158#define GPIOC 0x5018
159#define GPIOD 0x501c
160#define GPIOE 0x5020
161#define GPIOF 0x5024
162#define GPIOG 0x5028
163#define GPIOH 0x502c
164#define GPIO_CLOCK_DIR_MASK (1 << 0)
165#define GPIO_CLOCK_DIR_IN (0 << 1)
166#define GPIO_CLOCK_DIR_OUT (1 << 1)
167#define GPIO_CLOCK_VAL_MASK (1 << 2)
168#define GPIO_CLOCK_VAL_OUT (1 << 3)
169#define GPIO_CLOCK_VAL_IN (1 << 4)
170#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
171#define GPIO_DATA_DIR_MASK (1 << 8)
172#define GPIO_DATA_DIR_IN (0 << 9)
173#define GPIO_DATA_DIR_OUT (1 << 9)
174#define GPIO_DATA_VAL_MASK (1 << 10)
175#define GPIO_DATA_VAL_OUT (1 << 11)
176#define GPIO_DATA_VAL_IN (1 << 12)
177#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
178
179#define VCLK_DIVISOR_VGA0 0x6000
180#define VCLK_DIVISOR_VGA1 0x6004
181#define VCLK_POST_DIV 0x6010
182
183#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
184#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
185#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
186#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
187#define PSB_COMM_USER_IRQ (1024 >> 2)
188#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
189#define PSB_COMM_FW (2048 >> 2)
190
191#define PSB_UIRQ_VISTEST 1
192#define PSB_UIRQ_OOM_REPLY 2
193#define PSB_UIRQ_FIRE_TA_REPLY 3
194#define PSB_UIRQ_FIRE_RASTER_REPLY 4
195
196#define PSB_2D_SIZE (256*1024*1024)
197#define PSB_MAX_RELOC_PAGES 1024
198
199#define PSB_LOW_REG_OFFS 0x0204
200#define PSB_HIGH_REG_OFFS 0x0600
201
202#define PSB_NUM_VBLANKS 2
203
204
205#define PSB_2D_SIZE (256*1024*1024)
206#define PSB_MAX_RELOC_PAGES 1024
207
208#define PSB_LOW_REG_OFFS 0x0204
209#define PSB_HIGH_REG_OFFS 0x0600
210
211#define PSB_NUM_VBLANKS 2
212#define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
213#define PSB_LID_DELAY (DRM_HZ / 10)
214
215#define MDFLD_PNW_B0 0x04
216#define MDFLD_PNW_C0 0x08
217
218#define MDFLD_DSR_2D_3D_0 (1 << 0)
219#define MDFLD_DSR_2D_3D_2 (1 << 1)
220#define MDFLD_DSR_CURSOR_0 (1 << 2)
221#define MDFLD_DSR_CURSOR_2 (1 << 3)
222#define MDFLD_DSR_OVERLAY_0 (1 << 4)
223#define MDFLD_DSR_OVERLAY_2 (1 << 5)
224#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
225#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
226#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
227#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
228
229#define MDFLD_DSR_RR 45
230#define MDFLD_DPU_ENABLE (1 << 31)
231#define MDFLD_DSR_FULLSCREEN (1 << 30)
232#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
233
234#define PSB_PWR_STATE_ON 1
235#define PSB_PWR_STATE_OFF 2
236
237#define PSB_PMPOLICY_NOPM 0
238#define PSB_PMPOLICY_CLOCKGATING 1
239#define PSB_PMPOLICY_POWERDOWN 2
240
241#define PSB_PMSTATE_POWERUP 0
242#define PSB_PMSTATE_CLOCKGATED 1
243#define PSB_PMSTATE_POWERDOWN 2
244#define PSB_PCIx_MSI_ADDR_LOC 0x94
245#define PSB_PCIx_MSI_DATA_LOC 0x98
246
247/* Medfield crystal settings */
248#define KSEL_CRYSTAL_19 1
249#define KSEL_BYPASS_19 5
250#define KSEL_BYPASS_25 6
251#define KSEL_BYPASS_83_100 7
252
253struct opregion_header;
254struct opregion_acpi;
255struct opregion_swsci;
256struct opregion_asle;
257
258struct psb_intel_opregion {
259 struct opregion_header *header;
260 struct opregion_acpi *acpi;
261 struct opregion_swsci *swsci;
262 struct opregion_asle *asle;
1fb28e9e 263 void *vbt;
d839ede4 264 u32 __iomem *lid_state;
5c49fd3a
AC		 265};
266
5736995b
PJ		 267struct sdvo_device_mapping {
268 u8 initialized;
269 u8 dvo_port;
270 u8 slave_addr;
271 u8 dvo_wiring;
272 u8 i2c_pin;
273 u8 i2c_speed;
274 u8 ddc_pin;
275};
276
5c0c1d50
PJ		 277struct intel_gmbus {
278 struct i2c_adapter adapter;
279 struct i2c_adapter *force_bit;
280 u32 reg0;
281};
282
648a8e34
AC		 283/*
284 * Register save state. This is used to hold the context when the
285 * device is powered off. In the case of Oaktrail this can (but does not
286 * yet) include screen blank. Operations occuring during the save
287 * update the register cache instead.
288 */
6256304b
AC		 289
290/*
291 * Common status for pipes.
292 */
293struct psb_pipe {
294 u32 fp0;
295 u32 fp1;
296 u32 cntr;
297 u32 conf;
298 u32 src;
299 u32 dpll;
300 u32 dpll_md;
301 u32 htotal;
302 u32 hblank;
303 u32 hsync;
304 u32 vtotal;
305 u32 vblank;
306 u32 vsync;
307 u32 stride;
308 u32 size;
309 u32 pos;
310 u32 base;
311 u32 surf;
312 u32 addr;
313 u32 status;
314 u32 linoff;
315 u32 tileoff;
316 u32 palette[256];
317};
318
648a8e34 319struct psb_state {
648a8e34
AC		 320 uint32_t saveVCLK_DIVISOR_VGA0;
321 uint32_t saveVCLK_DIVISOR_VGA1;
322 uint32_t saveVCLK_POST_DIV;
323 uint32_t saveVGACNTRL;
324 uint32_t saveADPA;
325 uint32_t saveLVDS;
326 uint32_t saveDVOA;
327 uint32_t saveDVOB;
328 uint32_t saveDVOC;
329 uint32_t savePP_ON;
330 uint32_t savePP_OFF;
331 uint32_t savePP_CONTROL;
332 uint32_t savePP_CYCLE;
333 uint32_t savePFIT_CONTROL;
648a8e34
AC		 334 uint32_t saveCLOCKGATING;
335 uint32_t saveDSPARB;
648a8e34
AC		 336 uint32_t savePFIT_AUTO_RATIOS;
337 uint32_t savePFIT_PGM_RATIOS;
338 uint32_t savePP_ON_DELAYS;
339 uint32_t savePP_OFF_DELAYS;
340 uint32_t savePP_DIVISOR;
648a8e34
AC		 341 uint32_t saveBCLRPAT_A;
342 uint32_t saveBCLRPAT_B;
648a8e34
AC		 343 uint32_t savePERF_MODE;
344 uint32_t saveDSPFW1;
345 uint32_t saveDSPFW2;
346 uint32_t saveDSPFW3;
347 uint32_t saveDSPFW4;
348 uint32_t saveDSPFW5;
349 uint32_t saveDSPFW6;
350 uint32_t saveCHICKENBIT;
351 uint32_t saveDSPACURSOR_CTRL;
352 uint32_t saveDSPBCURSOR_CTRL;
353 uint32_t saveDSPACURSOR_BASE;
354 uint32_t saveDSPBCURSOR_BASE;
355 uint32_t saveDSPACURSOR_POS;
356 uint32_t saveDSPBCURSOR_POS;
648a8e34
AC		 357 uint32_t saveOV_OVADD;
358 uint32_t saveOV_OGAMC0;
359 uint32_t saveOV_OGAMC1;
360 uint32_t saveOV_OGAMC2;
361 uint32_t saveOV_OGAMC3;
362 uint32_t saveOV_OGAMC4;
363 uint32_t saveOV_OGAMC5;
364 uint32_t saveOVC_OVADD;
365 uint32_t saveOVC_OGAMC0;
366 uint32_t saveOVC_OGAMC1;
367 uint32_t saveOVC_OGAMC2;
368 uint32_t saveOVC_OGAMC3;
369 uint32_t saveOVC_OGAMC4;
370 uint32_t saveOVC_OGAMC5;
371
372 /* DPST register save */
373 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
374 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
375 uint32_t savePWM_CONTROL_LOGIC;
376};
377
026abc33 378struct medfield_state {
026abc33 379 uint32_t saveMIPI;
026abc33
KS		 380 uint32_t saveMIPI_C;
381
382 uint32_t savePFIT_CONTROL;
383 uint32_t savePFIT_PGM_RATIOS;
384 uint32_t saveHDMIPHYMISCCTL;
385 uint32_t saveHDMIB_CONTROL;
386};
387
09016a11
AC		 388struct cdv_state {
389 uint32_t saveDSPCLK_GATE_D;
390 uint32_t saveRAMCLK_GATE_D;
391 uint32_t saveDSPARB;
392 uint32_t saveDSPFW[6];
393 uint32_t saveADPA;
394 uint32_t savePP_CONTROL;
395 uint32_t savePFIT_PGM_RATIOS;
396 uint32_t saveLVDS;
397 uint32_t savePFIT_CONTROL;
398 uint32_t savePP_ON_DELAYS;
399 uint32_t savePP_OFF_DELAYS;
400 uint32_t savePP_CYCLE;
401 uint32_t saveVGACNTRL;
402 uint32_t saveIER;
403 uint32_t saveIMR;
404 u8 saveLBB;
405};
406
c6265ff5 407struct psb_save_area {
6256304b 408 struct psb_pipe pipe[3];
c6265ff5
AC		 409 uint32_t saveBSM;
410 uint32_t saveVBT;
411 union {
412 struct psb_state psb;
026abc33 413 struct medfield_state mdfld;
09016a11 414 struct cdv_state cdv;
c6265ff5
AC		 415 };
416 uint32_t saveBLC_PWM_CTL2;
417 uint32_t saveBLC_PWM_CTL;
418};
419
5c49fd3a
AC		 420struct psb_ops;
421
04bd564f
AC		 422#define PSB_NUM_PIPE 3
423
5c49fd3a
AC		 424struct drm_psb_private {
425 struct drm_device *dev;
426 const struct psb_ops *ops;
1fb28e9e
AC		 427
428 struct child_device_config *child_dev;
429 int child_dev_num;
5c49fd3a
AC		 430
431 struct psb_gtt gtt;
432
433 /* GTT Memory manager */
434 struct psb_gtt_mm *gtt_mm;
435 struct page *scratch_page;
eab37607 436 u32 __iomem *gtt_map;
5c49fd3a 437 uint32_t stolen_base;
37214ca0 438 u8 __iomem *vram_addr;
5c49fd3a
AC		 439 unsigned long vram_stolen_size;
440 int gtt_initialized;
441 u16 gmch_ctrl; /* Saved GTT setup */
442 u32 pge_ctl;
443
444 struct mutex gtt_mutex;
445 struct resource *gtt_mem; /* Our PCI resource */
446
447 struct psb_mmu_driver *mmu;
448 struct psb_mmu_pd *pf_pd;
449
450 /*
451 * Register base
452 */
453
846a6038
KS		 454 uint8_t __iomem *sgx_reg;
455 uint8_t __iomem *vdc_reg;
5c49fd3a
AC		 456 uint32_t gatt_free_offset;
457
458 /*
459 * Fencing / irq.
460 */
461
462 uint32_t vdc_irq_mask;
463 uint32_t pipestat[PSB_NUM_PIPE];
464
465 spinlock_t irqmask_lock;
466
467 /*
468 * Power
469 */
470
471 bool suspended;
472 bool display_power;
473 int display_count;
474
475 /*
476 * Modesetting
477 */
478 struct psb_intel_mode_device mode_dev;
479
480 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
481 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
482 uint32_t num_pipe;
483
484 /*
485 * OSPM info (Power management base) (can go ?)
486 */
487 uint32_t ospm_base;
488
489 /*
490 * Sizes info
491 */
492
5c49fd3a
AC		 493 u32 fuse_reg_value;
494 u32 video_device_fuse;
495
496 /* PCI revision ID for B0:D2:F0 */
497 uint8_t platform_rev_id;
498
5c0c1d50
PJ		 499 /* gmbus */
500 struct intel_gmbus *gmbus;
501
5736995b
PJ		 502 /* Used by SDVO */
503 int crt_ddc_pin;
504 /* FIXME: The mappings should be parsed from bios but for now we can
505 pretend there are no mappings available */
506 struct sdvo_device_mapping sdvo_mappings[2];
507 u32 hotplug_supported_mask;
508 struct drm_property *broadcast_rgb_property;
509 struct drm_property *force_audio_property;
510
5c49fd3a
AC		 511 /*
512 * LVDS info
513 */
514 int backlight_duty_cycle; /* restore backlight to this value */
515 bool panel_wants_dither;
516 struct drm_display_mode *panel_fixed_mode;
517 struct drm_display_mode *lfp_lvds_vbt_mode;
518 struct drm_display_mode *sdvo_lvds_vbt_mode;
519
520 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
a12d6a07 521 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
5c49fd3a
AC		 522
523 /* Feature bits from the VBIOS */
524 unsigned int int_tv_support:1;
525 unsigned int lvds_dither:1;
526 unsigned int lvds_vbt:1;
527 unsigned int int_crt_support:1;
528 unsigned int lvds_use_ssc:1;
529 int lvds_ssc_freq;
530 bool is_lvds_on;
531 bool is_mipi_on;
532 u32 mipi_ctrl_display;
533
534 unsigned int core_freq;
535 uint32_t iLVDS_enable;
536
537 /* Runtime PM state */
538 int rpm_enabled;
539
540 /* MID specific */
4086b1e2 541 bool has_gct;
5c49fd3a
AC		 542 struct oaktrail_gct_data gct_data;
543
933315ac 544 /* Oaktrail HDMI state */
5c49fd3a 545 struct oaktrail_hdmi_dev *hdmi_priv;
933315ac 546
5c49fd3a
AC		 547 /*
548 * Register state
549 */
c6265ff5
AC		 550
551 struct psb_save_area regs;
552
5c49fd3a
AC		 553 /* MSI reg save */
554 uint32_t msi_addr;
555 uint32_t msi_data;
556
ae0a246a
AC		 557 /*
558 * Hotplug handling
559 */
560
561 struct work_struct hotplug_work;
5c49fd3a 562
5c49fd3a
AC		 563 /*
564 * LID-Switch
565 */
566 spinlock_t lid_lock;
567 struct timer_list lid_timer;
568 struct psb_intel_opregion opregion;
5c49fd3a
AC		 569 u32 lid_last_state;
570
571 /*
572 * Watchdog
573 */
574
575 uint32_t apm_reg;
576 uint16_t apm_base;
577
578 /*
579 * Used for modifying backlight from
580 * xrandr -- consider removing and using HAL instead
581 */
582 struct backlight_device *backlight_device;
583 struct drm_property *backlight_property;
584 uint32_t blc_adj1;
585 uint32_t blc_adj2;
586
587 void *fbdev;
588
589 /* 2D acceleration */
9242fe23 590 spinlock_t lock_2d;
026abc33
KS		 591
592 /*
593 * Panel brightness
594 */
595 int brightness;
596 int brightness_adjusted;
597
598 bool dsr_enable;
599 u32 dsr_fb_update;
600 bool dpi_panel_on[3];
601 void *dsi_configs[2];
602 u32 bpp;
603 u32 bpp2;
604
605 u32 pipeconf[3];
606 u32 dspcntr[3];
607
608 int mdfld_panel_id;
642c52fc
AC		 609
610 bool dplla_96mhz; /* DPLL data from the VBT */
5c49fd3a
AC		 611};
612
613
614/*
615 * Operations for each board type
616 */
617
618struct psb_ops {
619 const char *name;
620 unsigned int accel_2d:1;
621 int pipes; /* Number of output pipes */
622 int crtcs; /* Number of CRTCs */
623 int sgx_offset; /* Base offset of SGX device */
d235e64a
AC		 624 int hdmi_mask; /* Mask of HDMI CRTCs */
625 int lvds_mask; /* Mask of LVDS CRTCs */
5c49fd3a
AC		 626
627 /* Sub functions */
628 struct drm_crtc_helper_funcs const *crtc_helper;
629 struct drm_crtc_funcs const *crtc_funcs;
630
631 /* Setup hooks */
632 int (*chip_setup)(struct drm_device *dev);
633 void (*chip_teardown)(struct drm_device *dev);
d235e64a
AC		 634 /* Optional helper caller after modeset */
635 void (*errata)(struct drm_device *dev);
5c49fd3a
AC		 636
637 /* Display management hooks */
638 int (*output_init)(struct drm_device *dev);
68cb638f
AC		 639 int (*hotplug)(struct drm_device *dev);
640 void (*hotplug_enable)(struct drm_device *dev, bool on);
5c49fd3a
AC		 641 /* Power management hooks */
642 void (*init_pm)(struct drm_device *dev);
643 int (*save_regs)(struct drm_device *dev);
644 int (*restore_regs)(struct drm_device *dev);
645 int (*power_up)(struct drm_device *dev);
646 int (*power_down)(struct drm_device *dev);
647
648 void (*lvds_bl_power)(struct drm_device *dev, bool on);
649#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
650 /* Backlight */
651 int (*backlight_init)(struct drm_device *dev);
652#endif
653 int i2c_bus; /* I2C bus identifier for Moorestown */
654};
655
656
657
658struct psb_mmu_driver;
659
660extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
661extern int drm_pick_crtcs(struct drm_device *dev);
662
663static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
664{
665 return (struct drm_psb_private *) dev->dev_private;
666}
667
668/*
669 * MMU stuff.
670 */
671
672extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
673 int trap_pagefaults,
674 int invalid_type,
675 struct drm_psb_private *dev_priv);
676extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
677extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
678 *driver);
679extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
680 uint32_t gtt_start, uint32_t gtt_pages);
681extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
682 int trap_pagefaults,
683 int invalid_type);
684extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
685extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
686extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
687 unsigned long address,
688 uint32_t num_pages);
689extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
690 uint32_t start_pfn,
691 unsigned long address,
692 uint32_t num_pages, int type);
693extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
694 unsigned long *pfn);
695
696/*
697 * Enable / disable MMU for different requestors.
698 */
699
700
701extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
702extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
703 unsigned long address, uint32_t num_pages,
704 uint32_t desired_tile_stride,
705 uint32_t hw_tile_stride, int type);
706extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
707 unsigned long address, uint32_t num_pages,
708 uint32_t desired_tile_stride,
709 uint32_t hw_tile_stride);
710/*
711 *psb_irq.c
712 */
713
714extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
715extern int psb_irq_enable_dpst(struct drm_device *dev);
716extern int psb_irq_disable_dpst(struct drm_device *dev);
717extern void psb_irq_preinstall(struct drm_device *dev);
718extern int psb_irq_postinstall(struct drm_device *dev);
719extern void psb_irq_uninstall(struct drm_device *dev);
720extern void psb_irq_turn_on_dpst(struct drm_device *dev);
721extern void psb_irq_turn_off_dpst(struct drm_device *dev);
722
723extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
724extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
725extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
726extern int psb_enable_vblank(struct drm_device *dev, int crtc);
727extern void psb_disable_vblank(struct drm_device *dev, int crtc);
728void
729psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
730
731void
732psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
733
734extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
735
5c49fd3a
AC		 736/*
737 * framebuffer.c
738 */
739extern int psbfb_probed(struct drm_device *dev);
740extern int psbfb_remove(struct drm_device *dev,
741 struct drm_framebuffer *fb);
742/*
743 * accel_2d.c
744 */
745extern void psbfb_copyarea(struct fb_info *info,
746 const struct fb_copyarea *region);
747extern int psbfb_sync(struct fb_info *info);
748extern void psb_spank(struct drm_psb_private *dev_priv);
749
750/*
751 * psb_reset.c
752 */
753
754extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
755extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
756extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
757
758/* modesetting */
759extern void psb_modeset_init(struct drm_device *dev);
760extern void psb_modeset_cleanup(struct drm_device *dev);
761extern int psb_fbdev_init(struct drm_device *dev);
762
763/* backlight.c */
764int gma_backlight_init(struct drm_device *dev);
765void gma_backlight_exit(struct drm_device *dev);
766
767/* oaktrail_crtc.c */
768extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
769
770/* oaktrail_lvds.c */
771extern void oaktrail_lvds_init(struct drm_device *dev,
772 struct psb_intel_mode_device *mode_dev);
773
774/* psb_intel_display.c */
775extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
776extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
777
778/* psb_intel_lvds.c */
779extern const struct drm_connector_helper_funcs
780 psb_intel_lvds_connector_helper_funcs;
781extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
782
783/* gem.c */
784extern int psb_gem_init_object(struct drm_gem_object *obj);
785extern void psb_gem_free_object(struct drm_gem_object *obj);
786extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
787 struct drm_file *file);
788extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
789 struct drm_mode_create_dumb *args);
790extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
791 uint32_t handle);
792extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
793 uint32_t handle, uint64_t *offset);
794extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
795extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
796 struct drm_file *file);
797extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
798 struct drm_file *file);
799
800/* psb_device.c */
801extern const struct psb_ops psb_chip_ops;
802
803/* oaktrail_device.c */
804extern const struct psb_ops oaktrail_chip_ops;
805
026abc33
KS		 806/* mdlfd_device.c */
807extern const struct psb_ops mdfld_chip_ops;
808
5c49fd3a
AC		 809/* cdv_device.c */
810extern const struct psb_ops cdv_chip_ops;
811
812/*
813 * Debug print bits setting
814 */
815#define PSB_D_GENERAL (1 << 0)
816#define PSB_D_INIT (1 << 1)
817#define PSB_D_IRQ (1 << 2)
818#define PSB_D_ENTRY (1 << 3)
819/* debug the get H/V BP/FP count */
820#define PSB_D_HV (1 << 4)
821#define PSB_D_DBI_BF (1 << 5)
822#define PSB_D_PM (1 << 6)
823#define PSB_D_RENDER (1 << 7)
824#define PSB_D_REG (1 << 8)
825#define PSB_D_MSVDX (1 << 9)
826#define PSB_D_TOPAZ (1 << 10)
827
828extern int drm_psb_no_fb;
829extern int drm_idle_check_interval;
830
831/*
832 * Utilities
833 */
834
835static inline u32 MRST_MSG_READ32(uint port, uint offset)
836{
837 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
838 uint32_t ret_val = 0;
839 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
840 pci_write_config_dword(pci_root, 0xD0, mcr);
841 pci_read_config_dword(pci_root, 0xD4, &ret_val);
842 pci_dev_put(pci_root);
843 return ret_val;
844}
845static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
846{
847 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
848 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
849 pci_write_config_dword(pci_root, 0xD4, value);
850 pci_write_config_dword(pci_root, 0xD0, mcr);
851 pci_dev_put(pci_root);
852}
853static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
854{
855 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
856 uint32_t ret_val = 0;
857 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
858 pci_write_config_dword(pci_root, 0xD0, mcr);
859 pci_read_config_dword(pci_root, 0xD4, &ret_val);
860 pci_dev_put(pci_root);
861 return ret_val;
862}
863static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
864{
865 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
866 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
867 pci_write_config_dword(pci_root, 0xD4, value);
868 pci_write_config_dword(pci_root, 0xD0, mcr);
869 pci_dev_put(pci_root);
870}
871
872static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
873{
874 struct drm_psb_private *dev_priv = dev->dev_private;
875 return ioread32(dev_priv->vdc_reg + reg);
876}
877
878#define REG_READ(reg) REGISTER_READ(dev, (reg))
879
880static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
881 uint32_t val)
882{
883 struct drm_psb_private *dev_priv = dev->dev_private;
884 iowrite32((val), dev_priv->vdc_reg + (reg));
885}
886
887#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
888
889static inline void REGISTER_WRITE16(struct drm_device *dev,
890 uint32_t reg, uint32_t val)
891{
892 struct drm_psb_private *dev_priv = dev->dev_private;
893 iowrite16((val), dev_priv->vdc_reg + (reg));
894}
895
896#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
897
898static inline void REGISTER_WRITE8(struct drm_device *dev,
899 uint32_t reg, uint32_t val)
900{
901 struct drm_psb_private *dev_priv = dev->dev_private;
902 iowrite8((val), dev_priv->vdc_reg + (reg));
903}
904
905#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
906
907#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
908#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
909
910/* #define TRAP_SGX_PM_FAULT 1 */
911#ifdef TRAP_SGX_PM_FAULT
912#define PSB_RSGX32(_offs) \
913({ \
914 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
915 printk(KERN_ERR \
916 "access sgx when it's off!! (READ) %s, %d\n", \
917 __FILE__, __LINE__); \
918 melay(1000); \
919 } \
920 ioread32(dev_priv->sgx_reg + (_offs)); \
921})
922#else
923#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
924#endif
925#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
926
927#define MSVDX_REG_DUMP 0
928
929#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
930#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
931
932#endif
Linux kernel - Deliverables
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