Merge tag 'nfs-for-4.5-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
[deliverable/linux.git] / drivers / gpu / drm / gma500 / psb_intel_display.c
CommitLineData
89c78134
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1/*
2 * Copyright © 2006-2011 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * Authors:
18 * Eric Anholt <eric@anholt.net>
19 */
20
21#include <linux/i2c.h>
89c78134
AC
22
23#include <drm/drmP.h>
3cb9ae4f 24#include <drm/drm_plane_helper.h>
89c78134
AC
25#include "framebuffer.h"
26#include "psb_drv.h"
27#include "psb_intel_drv.h"
28#include "psb_intel_reg.h"
7f67c067 29#include "gma_display.h"
89c78134
AC
30#include "power.h"
31
4e6bb70d
PJ
32#define INTEL_LIMIT_I9XX_SDVO_DAC 0
33#define INTEL_LIMIT_I9XX_LVDS 1
89c78134 34
7f67c067 35static const struct gma_limit_t psb_intel_limits[] = {
89c78134 36 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
06da4912
PJ
37 .dot = {.min = 20000, .max = 400000},
38 .vco = {.min = 1400000, .max = 2800000},
39 .n = {.min = 1, .max = 6},
40 .m = {.min = 70, .max = 120},
41 .m1 = {.min = 8, .max = 18},
42 .m2 = {.min = 3, .max = 7},
43 .p = {.min = 5, .max = 80},
44 .p1 = {.min = 1, .max = 8},
7f67c067
PJ
45 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
46 .find_pll = gma_find_best_pll,
89c78134
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47 },
48 { /* INTEL_LIMIT_I9XX_LVDS */
06da4912
PJ
49 .dot = {.min = 20000, .max = 400000},
50 .vco = {.min = 1400000, .max = 2800000},
51 .n = {.min = 1, .max = 6},
52 .m = {.min = 70, .max = 120},
53 .m1 = {.min = 8, .max = 18},
54 .m2 = {.min = 3, .max = 7},
55 .p = {.min = 7, .max = 98},
56 .p1 = {.min = 1, .max = 8},
89c78134
AC
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
59 */
7f67c067
PJ
60 .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
61 .find_pll = gma_find_best_pll,
89c78134
AC
62 },
63};
64
7f67c067
PJ
65static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
66 int refclk)
89c78134 67{
7f67c067 68 const struct gma_limit_t *limit;
89c78134 69
7f67c067 70 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
89c78134
AC
71 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
72 else
73 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
74 return limit;
75}
76
7f67c067 77static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
89c78134
AC
78{
79 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
80 clock->p = clock->p1 * clock->p2;
81 clock->vco = refclk * clock->m / (clock->n + 2);
82 clock->dot = clock->vco / clock->p;
83}
84
89c78134
AC
85/**
86 * Return the pipe currently connected to the panel fitter,
87 * or -1 if the panel fitter is not present or not in use
88 */
89static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
90{
91 u32 pfit_control;
92
93 pfit_control = REG_READ(PFIT_CONTROL);
94
95 /* See if the panel fitter is in use */
96 if ((pfit_control & PFIT_ENABLE) == 0)
97 return -1;
98 /* Must be on PIPE 1 for PSB */
99 return 1;
100}
101
102static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
103 struct drm_display_mode *mode,
104 struct drm_display_mode *adjusted_mode,
105 int x, int y,
106 struct drm_framebuffer *old_fb)
107{
108 struct drm_device *dev = crtc->dev;
213a8434 109 struct drm_psb_private *dev_priv = dev->dev_private;
6306865d 110 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
45fe734c 111 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6306865d 112 int pipe = gma_crtc->pipe;
213a8434 113 const struct psb_offset *map = &dev_priv->regmap[pipe];
89c78134 114 int refclk;
7f67c067 115 struct gma_clock_t clock;
89c78134 116 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
2e33d6b9
KS
117 bool ok, is_sdvo = false;
118 bool is_lvds = false, is_tv = false;
89c78134
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119 struct drm_mode_config *mode_config = &dev->mode_config;
120 struct drm_connector *connector;
7f67c067 121 const struct gma_limit_t *limit;
89c78134
AC
122
123 /* No scan out no play */
f4510a27 124 if (crtc->primary->fb == NULL) {
89c78134
AC
125 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
126 return 0;
127 }
128
129 list_for_each_entry(connector, &mode_config->connector_list, head) {
367e4408 130 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
89c78134
AC
131
132 if (!connector->encoder
133 || connector->encoder->crtc != crtc)
134 continue;
135
367e4408 136 switch (gma_encoder->type) {
89c78134
AC
137 case INTEL_OUTPUT_LVDS:
138 is_lvds = true;
139 break;
140 case INTEL_OUTPUT_SDVO:
141 is_sdvo = true;
142 break;
89c78134
AC
143 case INTEL_OUTPUT_TVOUT:
144 is_tv = true;
145 break;
89c78134
AC
146 }
147 }
148
149 refclk = 96000;
150
6306865d 151 limit = gma_crtc->clock_funcs->limit(crtc, refclk);
7f67c067
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152
153 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
89c78134
AC
154 &clock);
155 if (!ok) {
7f67c067
PJ
156 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
157 adjusted_mode->clock, clock.dot);
89c78134
AC
158 return 0;
159 }
160
161 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
162
163 dpll = DPLL_VGA_MODE_DIS;
164 if (is_lvds) {
165 dpll |= DPLLB_MODE_LVDS;
166 dpll |= DPLL_DVO_HIGH_SPEED;
167 } else
168 dpll |= DPLLB_MODE_DAC_SERIAL;
169 if (is_sdvo) {
170 int sdvo_pixel_multiply =
171 adjusted_mode->clock / mode->clock;
172 dpll |= DPLL_DVO_HIGH_SPEED;
173 dpll |=
174 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
175 }
176
177 /* compute bitmask from p1 value */
178 dpll |= (1 << (clock.p1 - 1)) << 16;
179 switch (clock.p2) {
180 case 5:
181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
182 break;
183 case 7:
184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
185 break;
186 case 10:
187 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
188 break;
189 case 14:
190 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
191 break;
192 }
193
194 if (is_tv) {
195 /* XXX: just matching BIOS for now */
196/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
197 dpll |= 3;
198 }
199 dpll |= PLL_REF_INPUT_DREFCLK;
200
201 /* setup pipeconf */
213a8434 202 pipeconf = REG_READ(map->conf);
89c78134
AC
203
204 /* Set up the display plane register */
205 dspcntr = DISPPLANE_GAMMA_ENABLE;
206
207 if (pipe == 0)
208 dspcntr |= DISPPLANE_SEL_PIPE_A;
209 else
210 dspcntr |= DISPPLANE_SEL_PIPE_B;
211
212 dspcntr |= DISPLAY_PLANE_ENABLE;
213 pipeconf |= PIPEACONF_ENABLE;
214 dpll |= DPLL_VCO_ENABLE;
215
216
217 /* Disable the panel fitter if it was on our pipe */
218 if (psb_intel_panel_fitter_pipe(dev) == pipe)
219 REG_WRITE(PFIT_CONTROL, 0);
220
221 drm_mode_debug_printmodeline(mode);
222
223 if (dpll & DPLL_VCO_ENABLE) {
213a8434
AC
224 REG_WRITE(map->fp0, fp);
225 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
226 REG_READ(map->dpll);
89c78134
AC
227 udelay(150);
228 }
229
230 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
231 * This is an exception to the general rule that mode_set doesn't turn
232 * things on.
233 */
234 if (is_lvds) {
235 u32 lvds = REG_READ(LVDS);
236
237 lvds &= ~LVDS_PIPEB_SELECT;
238 if (pipe == 1)
239 lvds |= LVDS_PIPEB_SELECT;
240
241 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
242 /* Set the B0-B3 data pairs corresponding to
243 * whether we're going to
244 * set the DPLLs for dual-channel mode or not.
245 */
246 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
247 if (clock.p2 == 7)
248 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
249
250 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
251 * appropriately here, but we need to look more
252 * thoroughly into how panels behave in the two modes.
253 */
254
255 REG_WRITE(LVDS, lvds);
256 REG_READ(LVDS);
257 }
258
213a8434
AC
259 REG_WRITE(map->fp0, fp);
260 REG_WRITE(map->dpll, dpll);
261 REG_READ(map->dpll);
89c78134
AC
262 /* Wait for the clocks to stabilize. */
263 udelay(150);
264
265 /* write it again -- the BIOS does, after all */
213a8434 266 REG_WRITE(map->dpll, dpll);
89c78134 267
213a8434 268 REG_READ(map->dpll);
89c78134
AC
269 /* Wait for the clocks to stabilize. */
270 udelay(150);
271
213a8434 272 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
89c78134 273 ((adjusted_mode->crtc_htotal - 1) << 16));
213a8434 274 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
89c78134 275 ((adjusted_mode->crtc_hblank_end - 1) << 16));
213a8434 276 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
89c78134 277 ((adjusted_mode->crtc_hsync_end - 1) << 16));
213a8434 278 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
89c78134 279 ((adjusted_mode->crtc_vtotal - 1) << 16));
213a8434 280 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
89c78134 281 ((adjusted_mode->crtc_vblank_end - 1) << 16));
213a8434 282 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
89c78134
AC
283 ((adjusted_mode->crtc_vsync_end - 1) << 16));
284 /* pipesrc and dspsize control the size that is scaled from,
285 * which should always be the user's requested size.
286 */
213a8434 287 REG_WRITE(map->size,
89c78134 288 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
213a8434
AC
289 REG_WRITE(map->pos, 0);
290 REG_WRITE(map->src,
89c78134 291 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
213a8434
AC
292 REG_WRITE(map->conf, pipeconf);
293 REG_READ(map->conf);
89c78134 294
d1fa08f3 295 gma_wait_for_vblank(dev);
89c78134 296
213a8434 297 REG_WRITE(map->cntr, dspcntr);
89c78134
AC
298
299 /* Flush the plane changes */
300 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
301
d1fa08f3 302 gma_wait_for_vblank(dev);
89c78134
AC
303
304 return 0;
305}
306
89c78134
AC
307/* Returns the clock of the currently programmed mode of the given pipe. */
308static int psb_intel_crtc_clock_get(struct drm_device *dev,
309 struct drm_crtc *crtc)
310{
6306865d 311 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
213a8434 312 struct drm_psb_private *dev_priv = dev->dev_private;
6306865d 313 int pipe = gma_crtc->pipe;
213a8434 314 const struct psb_offset *map = &dev_priv->regmap[pipe];
89c78134
AC
315 u32 dpll;
316 u32 fp;
7f67c067 317 struct gma_clock_t clock;
89c78134 318 bool is_lvds;
6256304b 319 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
89c78134
AC
320
321 if (gma_power_begin(dev, false)) {
213a8434 322 dpll = REG_READ(map->dpll);
89c78134 323 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
213a8434 324 fp = REG_READ(map->fp0);
89c78134 325 else
213a8434 326 fp = REG_READ(map->fp1);
89c78134
AC
327 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
328 gma_power_end(dev);
329 } else {
6256304b 330 dpll = p->dpll;
89c78134
AC
331
332 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6256304b 333 fp = p->fp0;
89c78134 334 else
6256304b 335 fp = p->fp1;
89c78134 336
c6265ff5 337 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
648a8e34 338 LVDS_PORT_EN);
89c78134
AC
339 }
340
341 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
342 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
343 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
344
345 if (is_lvds) {
346 clock.p1 =
347 ffs((dpll &
348 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
349 DPLL_FPA01_P1_POST_DIV_SHIFT);
350 clock.p2 = 14;
351
352 if ((dpll & PLL_REF_INPUT_MASK) ==
353 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
354 /* XXX: might not be 66MHz */
1548060f 355 psb_intel_clock(66000, &clock);
89c78134 356 } else
1548060f 357 psb_intel_clock(48000, &clock);
89c78134
AC
358 } else {
359 if (dpll & PLL_P1_DIVIDE_BY_TWO)
360 clock.p1 = 2;
361 else {
362 clock.p1 =
363 ((dpll &
364 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
365 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
366 }
367 if (dpll & PLL_P2_DIVIDE_BY_4)
368 clock.p2 = 4;
369 else
370 clock.p2 = 2;
371
1548060f 372 psb_intel_clock(48000, &clock);
89c78134
AC
373 }
374
375 /* XXX: It would be nice to validate the clocks, but we can't reuse
376 * i830PllIsValid() because it relies on the xf86_config connector
377 * configuration being accurate, which it isn't necessarily.
378 */
379
380 return clock.dot;
381}
382
383/** Returns the currently programmed mode of the given pipe. */
384struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
385 struct drm_crtc *crtc)
386{
6306865d
PJ
387 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
388 int pipe = gma_crtc->pipe;
89c78134
AC
389 struct drm_display_mode *mode;
390 int htot;
391 int hsync;
392 int vtot;
393 int vsync;
394 struct drm_psb_private *dev_priv = dev->dev_private;
6256304b 395 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
213a8434 396 const struct psb_offset *map = &dev_priv->regmap[pipe];
89c78134
AC
397
398 if (gma_power_begin(dev, false)) {
213a8434
AC
399 htot = REG_READ(map->htotal);
400 hsync = REG_READ(map->hsync);
401 vtot = REG_READ(map->vtotal);
402 vsync = REG_READ(map->vsync);
89c78134
AC
403 gma_power_end(dev);
404 } else {
6256304b
AC
405 htot = p->htotal;
406 hsync = p->hsync;
407 vtot = p->vtotal;
408 vsync = p->vsync;
89c78134
AC
409 }
410
411 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
412 if (!mode)
413 return NULL;
414
415 mode->clock = psb_intel_crtc_clock_get(dev, crtc);
416 mode->hdisplay = (htot & 0xffff) + 1;
417 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
418 mode->hsync_start = (hsync & 0xffff) + 1;
419 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
420 mode->vdisplay = (vtot & 0xffff) + 1;
421 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
422 mode->vsync_start = (vsync & 0xffff) + 1;
423 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
424
425 drm_mode_set_name(mode);
426 drm_mode_set_crtcinfo(mode, 0);
427
428 return mode;
429}
430
89c78134 431const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
42568dd5 432 .dpms = gma_crtc_dpms,
4855177e 433 .mode_fixup = gma_crtc_mode_fixup,
89c78134 434 .mode_set = psb_intel_crtc_mode_set,
00b1fe74 435 .mode_set_base = gma_pipe_set_base,
4855177e
PJ
436 .prepare = gma_crtc_prepare,
437 .commit = gma_crtc_commit,
438 .disable = gma_crtc_disable,
89c78134
AC
439};
440
441const struct drm_crtc_funcs psb_intel_crtc_funcs = {
561573bf
PJ
442 .cursor_set = gma_crtc_cursor_set,
443 .cursor_move = gma_crtc_cursor_move,
6443ea1a 444 .gamma_set = gma_crtc_gamma_set,
43a83027 445 .set_config = gma_crtc_set_config,
b1255b88 446 .destroy = gma_crtc_destroy,
89c78134
AC
447};
448
7f67c067
PJ
449const struct gma_clock_funcs psb_clock_funcs = {
450 .clock = psb_intel_clock,
451 .limit = psb_intel_limit,
452 .pll_is_valid = gma_pll_is_valid,
453};
454
89c78134
AC
455/*
456 * Set the default value of cursor control and base register
457 * to zero. This is a workaround for h/w defect on Oaktrail
458 */
bc794829 459static void psb_intel_cursor_init(struct drm_device *dev,
6306865d 460 struct gma_crtc *gma_crtc)
89c78134 461{
bc794829 462 struct drm_psb_private *dev_priv = dev->dev_private;
89c78134
AC
463 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
464 u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
bc794829
PJ
465 struct gtt_range *cursor_gt;
466
467 if (dev_priv->ops->cursor_needs_phys) {
468 /* Allocate 4 pages of stolen mem for a hardware cursor. That
469 * is enough for the 64 x 64 ARGB cursors we support.
470 */
c269c685
PJ
471 cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1,
472 PAGE_SIZE);
bc794829 473 if (!cursor_gt) {
6306865d 474 gma_crtc->cursor_gt = NULL;
bc794829
PJ
475 goto out;
476 }
6306865d
PJ
477 gma_crtc->cursor_gt = cursor_gt;
478 gma_crtc->cursor_addr = dev_priv->stolen_base +
bc794829
PJ
479 cursor_gt->offset;
480 } else {
6306865d 481 gma_crtc->cursor_gt = NULL;
bc794829 482 }
89c78134 483
bc794829 484out:
6306865d
PJ
485 REG_WRITE(control[gma_crtc->pipe], 0);
486 REG_WRITE(base[gma_crtc->pipe], 0);
89c78134
AC
487}
488
489void psb_intel_crtc_init(struct drm_device *dev, int pipe,
490 struct psb_intel_mode_device *mode_dev)
491{
492 struct drm_psb_private *dev_priv = dev->dev_private;
6306865d 493 struct gma_crtc *gma_crtc;
89c78134
AC
494 int i;
495 uint16_t *r_base, *g_base, *b_base;
496
497 /* We allocate a extra array of drm_connector pointers
498 * for fbdev after the crtc */
6306865d
PJ
499 gma_crtc = kzalloc(sizeof(struct gma_crtc) +
500 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
501 GFP_KERNEL);
502 if (gma_crtc == NULL)
89c78134
AC
503 return;
504
6306865d 505 gma_crtc->crtc_state =
89c78134 506 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
6306865d 507 if (!gma_crtc->crtc_state) {
89c78134 508 dev_err(dev->dev, "Crtc state error: No memory\n");
6306865d 509 kfree(gma_crtc);
89c78134
AC
510 return;
511 }
512
513 /* Set the CRTC operations from the chip specific data */
6306865d 514 drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs);
89c78134 515
5ea75e0f 516 /* Set the CRTC clock functions from chip specific data */
6306865d 517 gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;
5ea75e0f 518
6306865d
PJ
519 drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256);
520 gma_crtc->pipe = pipe;
521 gma_crtc->plane = pipe;
89c78134 522
6306865d 523 r_base = gma_crtc->base.gamma_store;
89c78134
AC
524 g_base = r_base + 256;
525 b_base = g_base + 256;
526 for (i = 0; i < 256; i++) {
6306865d
PJ
527 gma_crtc->lut_r[i] = i;
528 gma_crtc->lut_g[i] = i;
529 gma_crtc->lut_b[i] = i;
89c78134
AC
530 r_base[i] = i << 8;
531 g_base[i] = i << 8;
532 b_base[i] = i << 8;
533
6306865d 534 gma_crtc->lut_adj[i] = 0;
89c78134
AC
535 }
536
6306865d
PJ
537 gma_crtc->mode_dev = mode_dev;
538 gma_crtc->cursor_addr = 0;
89c78134 539
6306865d 540 drm_crtc_helper_add(&gma_crtc->base,
89c78134
AC
541 dev_priv->ops->crtc_helper);
542
543 /* Setup the array of drm_connector pointer array */
6306865d 544 gma_crtc->mode_set.crtc = &gma_crtc->base;
89c78134 545 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
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546 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);
547 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
548 dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;
549 gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1);
550 gma_crtc->mode_set.num_connectors = 0;
551 psb_intel_cursor_init(dev, gma_crtc);
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FB
552
553 /* Set to true so that the pipe is forced off on initial config. */
6306865d 554 gma_crtc->active = true;
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555}
556
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557struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
558{
559 struct drm_crtc *crtc = NULL;
560
561 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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562 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
563 if (gma_crtc->pipe == pipe)
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564 break;
565 }
566 return crtc;
567}
568
a3d5d75f 569int gma_connector_clones(struct drm_device *dev, int type_mask)
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570{
571 int index_mask = 0;
572 struct drm_connector *connector;
573 int entry = 0;
574
575 list_for_each_entry(connector, &dev->mode_config.connector_list,
576 head) {
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577 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
578 if (type_mask & (1 << gma_encoder->type))
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579 index_mask |= (1 << entry);
580 entry++;
581 }
582 return index_mask;
583}
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