projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 89c78134 AC |
1 | /* |
| 2 | * Copyright (c) 2009, Intel Corporation. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify it | |
| 5 | * under the terms and conditions of the GNU General Public License, | |
| 6 | * version 2, as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 11 | * more details. | |
| 12 | * | |
| 13 | * You should have received a copy of the GNU General Public License along with | |
| 14 | * this program; if not, write to the Free Software Foundation, Inc., | |
| 15 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
| 16 | */ | |
| 17 | #ifndef __PSB_INTEL_REG_H__ | |
| 18 | #define __PSB_INTEL_REG_H__ | |
| 19 | ||
| 5c0c1d50 PJ |
20 | /* |
| 21 | * GPIO regs | |
| 22 | */ | |
| 23 | #define GPIOA 0x5010 | |
| 24 | #define GPIOB 0x5014 | |
| 25 | #define GPIOC 0x5018 | |
| 26 | #define GPIOD 0x501c | |
| 27 | #define GPIOE 0x5020 | |
| 28 | #define GPIOF 0x5024 | |
| 29 | #define GPIOG 0x5028 | |
| 30 | #define GPIOH 0x502c | |
| 31 | # define GPIO_CLOCK_DIR_MASK (1 << 0) | |
| 32 | # define GPIO_CLOCK_DIR_IN (0 << 1) | |
| 33 | # define GPIO_CLOCK_DIR_OUT (1 << 1) | |
| 34 | # define GPIO_CLOCK_VAL_MASK (1 << 2) | |
| 35 | # define GPIO_CLOCK_VAL_OUT (1 << 3) | |
| 36 | # define GPIO_CLOCK_VAL_IN (1 << 4) | |
| 37 | # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) | |
| 38 | # define GPIO_DATA_DIR_MASK (1 << 8) | |
| 39 | # define GPIO_DATA_DIR_IN (0 << 9) | |
| 40 | # define GPIO_DATA_DIR_OUT (1 << 9) | |
| 41 | # define GPIO_DATA_VAL_MASK (1 << 10) | |
| 42 | # define GPIO_DATA_VAL_OUT (1 << 11) | |
| 43 | # define GPIO_DATA_VAL_IN (1 << 12) | |
| 44 | # define GPIO_DATA_PULLUP_DISABLE (1 << 13) | |
| 45 | ||
| 46 | #define GMBUS0 0x5100 /* clock/port select */ | |
| 47 | #define GMBUS_RATE_100KHZ (0<<8) | |
| 48 | #define GMBUS_RATE_50KHZ (1<<8) | |
| 49 | #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ | |
| 50 | #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ | |
| 51 | #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ | |
| 52 | #define GMBUS_PORT_DISABLED 0 | |
| 53 | #define GMBUS_PORT_SSC 1 | |
| 54 | #define GMBUS_PORT_VGADDC 2 | |
| 55 | #define GMBUS_PORT_PANEL 3 | |
| 56 | #define GMBUS_PORT_DPC 4 /* HDMIC */ | |
| 57 | #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ | |
| 58 | /* 6 reserved */ | |
| 59 | #define GMBUS_PORT_DPD 7 /* HDMID */ | |
| 60 | #define GMBUS_NUM_PORTS 8 | |
| 61 | #define GMBUS1 0x5104 /* command/status */ | |
| 62 | #define GMBUS_SW_CLR_INT (1<<31) | |
| 63 | #define GMBUS_SW_RDY (1<<30) | |
| 64 | #define GMBUS_ENT (1<<29) /* enable timeout */ | |
| 65 | #define GMBUS_CYCLE_NONE (0<<25) | |
| 66 | #define GMBUS_CYCLE_WAIT (1<<25) | |
| 67 | #define GMBUS_CYCLE_INDEX (2<<25) | |
| 68 | #define GMBUS_CYCLE_STOP (4<<25) | |
| 69 | #define GMBUS_BYTE_COUNT_SHIFT 16 | |
| 70 | #define GMBUS_SLAVE_INDEX_SHIFT 8 | |
| 71 | #define GMBUS_SLAVE_ADDR_SHIFT 1 | |
| 72 | #define GMBUS_SLAVE_READ (1<<0) | |
| 73 | #define GMBUS_SLAVE_WRITE (0<<0) | |
| 74 | #define GMBUS2 0x5108 /* status */ | |
| 75 | #define GMBUS_INUSE (1<<15) | |
| 76 | #define GMBUS_HW_WAIT_PHASE (1<<14) | |
| 77 | #define GMBUS_STALL_TIMEOUT (1<<13) | |
| 78 | #define GMBUS_INT (1<<12) | |
| 79 | #define GMBUS_HW_RDY (1<<11) | |
| 80 | #define GMBUS_SATOER (1<<10) | |
| 81 | #define GMBUS_ACTIVE (1<<9) | |
| 82 | #define GMBUS3 0x510c /* data buffer bytes 3-0 */ | |
| 83 | #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ | |
| 84 | #define GMBUS_SLAVE_TIMEOUT_EN (1<<4) | |
| 85 | #define GMBUS_NAK_EN (1<<3) | |
| 86 | #define GMBUS_IDLE_EN (1<<2) | |
| 87 | #define GMBUS_HW_WAIT_EN (1<<1) | |
| 88 | #define GMBUS_HW_RDY_EN (1<<0) | |
| 89 | #define GMBUS5 0x5120 /* byte index */ | |
| 90 | #define GMBUS_2BYTE_INDEX_EN (1<<31) | |
| 91 | ||
| 89c78134 AC |
92 | #define BLC_PWM_CTL 0x61254 |
| 93 | #define BLC_PWM_CTL2 0x61250 | |
| d235e64a AC |
94 | #define PWM_ENABLE (1 << 31) |
| 95 | #define PWM_LEGACY_MODE (1 << 30) | |
| 96 | #define PWM_PIPE_B (1 << 29) | |
| 89c78134 AC |
97 | #define BLC_PWM_CTL_C 0x62254 |
| 98 | #define BLC_PWM_CTL2_C 0x62250 | |
| 99 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) | |
| 100 | /* | |
| 101 | * This is the most significant 15 bits of the number of backlight cycles in a | |
| 102 | * complete cycle of the modulated backlight control. | |
| 103 | * | |
| 104 | * The actual value is this field multiplied by two. | |
| 105 | */ | |
| 106 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) | |
| 107 | #define BLM_LEGACY_MODE (1 << 16) | |
| 108 | /* | |
| 109 | * This is the number of cycles out of the backlight modulation cycle for which | |
| 110 | * the backlight is on. | |
| 111 | * | |
| 112 | * This field must be no greater than the number of cycles in the complete | |
| 113 | * backlight modulation cycle. | |
| 114 | */ | |
| 115 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) | |
| 116 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) | |
| 117 | ||
| 118 | #define I915_GCFGC 0xf0 | |
| 119 | #define I915_LOW_FREQUENCY_ENABLE (1 << 7) | |
| 120 | #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) | |
| 121 | #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) | |
| 122 | #define I915_DISPLAY_CLOCK_MASK (7 << 4) | |
| 123 | ||
| 124 | #define I855_HPLLCC 0xc0 | |
| 125 | #define I855_CLOCK_CONTROL_MASK (3 << 0) | |
| 126 | #define I855_CLOCK_133_200 (0 << 0) | |
| 127 | #define I855_CLOCK_100_200 (1 << 0) | |
| 128 | #define I855_CLOCK_100_133 (2 << 0) | |
| 129 | #define I855_CLOCK_166_250 (3 << 0) | |
| 130 | ||
| 131 | /* I830 CRTC registers */ | |
| 132 | #define HTOTAL_A 0x60000 | |
| 133 | #define HBLANK_A 0x60004 | |
| 134 | #define HSYNC_A 0x60008 | |
| 135 | #define VTOTAL_A 0x6000c | |
| 136 | #define VBLANK_A 0x60010 | |
| 137 | #define VSYNC_A 0x60014 | |
| 138 | #define PIPEASRC 0x6001c | |
| 139 | #define BCLRPAT_A 0x60020 | |
| 140 | #define VSYNCSHIFT_A 0x60028 | |
| 141 | ||
| 142 | #define HTOTAL_B 0x61000 | |
| 143 | #define HBLANK_B 0x61004 | |
| 144 | #define HSYNC_B 0x61008 | |
| 145 | #define VTOTAL_B 0x6100c | |
| 146 | #define VBLANK_B 0x61010 | |
| 147 | #define VSYNC_B 0x61014 | |
| 148 | #define PIPEBSRC 0x6101c | |
| 149 | #define BCLRPAT_B 0x61020 | |
| 150 | #define VSYNCSHIFT_B 0x61028 | |
| 151 | ||
| 152 | #define HTOTAL_C 0x62000 | |
| 153 | #define HBLANK_C 0x62004 | |
| 154 | #define HSYNC_C 0x62008 | |
| 155 | #define VTOTAL_C 0x6200c | |
| 156 | #define VBLANK_C 0x62010 | |
| 157 | #define VSYNC_C 0x62014 | |
| 158 | #define PIPECSRC 0x6201c | |
| 159 | #define BCLRPAT_C 0x62020 | |
| 160 | #define VSYNCSHIFT_C 0x62028 | |
| 161 | ||
| 162 | #define PP_STATUS 0x61200 | |
| 163 | # define PP_ON (1 << 31) | |
| 164 | /* | |
| 165 | * Indicates that all dependencies of the panel are on: | |
| 166 | * | |
| 167 | * - PLL enabled | |
| 168 | * - pipe enabled | |
| 169 | * - LVDS/DVOB/DVOC on | |
| 170 | */ | |
| 171 | #define PP_READY (1 << 30) | |
| 172 | #define PP_SEQUENCE_NONE (0 << 28) | |
| 173 | #define PP_SEQUENCE_ON (1 << 28) | |
| 174 | #define PP_SEQUENCE_OFF (2 << 28) | |
| 175 | #define PP_SEQUENCE_MASK 0x30000000 | |
| d112a816 ZY |
176 | #define PP_CYCLE_DELAY_ACTIVE (1 << 27) |
| 177 | #define PP_SEQUENCE_STATE_ON_IDLE (1 << 3) | |
| 178 | #define PP_SEQUENCE_STATE_MASK 0x0000000f | |
| 179 | ||
| 89c78134 AC |
180 | #define PP_CONTROL 0x61204 |
| 181 | #define POWER_TARGET_ON (1 << 0) | |
| d112a816 ZY |
182 | #define PANEL_UNLOCK_REGS (0xabcd << 16) |
| 183 | #define PANEL_UNLOCK_MASK (0xffff << 16) | |
| 184 | #define EDP_FORCE_VDD (1 << 3) | |
| 185 | #define EDP_BLC_ENABLE (1 << 2) | |
| 186 | #define PANEL_POWER_RESET (1 << 1) | |
| 187 | #define PANEL_POWER_OFF (0 << 0) | |
| 188 | #define PANEL_POWER_ON (1 << 0) | |
| 189 | ||
| 190 | /* Poulsbo/Oaktrail */ | |
| 89c78134 AC |
191 | #define LVDSPP_ON 0x61208 |
| 192 | #define LVDSPP_OFF 0x6120c | |
| 193 | #define PP_CYCLE 0x61210 | |
| 194 | ||
| d112a816 | 195 | /* Cedartrail */ |
| 09016a11 | 196 | #define PP_ON_DELAYS 0x61208 /* Cedartrail */ |
| d112a816 ZY |
197 | #define PANEL_PORT_SELECT_MASK (3 << 30) |
| 198 | #define PANEL_PORT_SELECT_LVDS (0 << 30) | |
| 199 | #define PANEL_PORT_SELECT_EDP (1 << 30) | |
| 200 | #define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) | |
| 201 | #define PANEL_POWER_UP_DELAY_SHIFT 16 | |
| 202 | #define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) | |
| 203 | #define PANEL_LIGHT_ON_DELAY_SHIFT 0 | |
| 204 | ||
| 09016a11 | 205 | #define PP_OFF_DELAYS 0x6120c /* Cedartrail */ |
| d112a816 ZY |
206 | #define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) |
| 207 | #define PANEL_POWER_DOWN_DELAY_SHIFT 16 | |
| 208 | #define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) | |
| 209 | #define PANEL_LIGHT_OFF_DELAY_SHIFT 0 | |
| 210 | ||
| 211 | #define PP_DIVISOR 0x61210 /* Cedartrail */ | |
| 212 | #define PP_REFERENCE_DIVIDER_MASK (0xffffff00) | |
| 213 | #define PP_REFERENCE_DIVIDER_SHIFT 8 | |
| 214 | #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) | |
| 215 | #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 | |
| 09016a11 | 216 | |
| 89c78134 AC |
217 | #define PFIT_CONTROL 0x61230 |
| 218 | #define PFIT_ENABLE (1 << 31) | |
| 219 | #define PFIT_PIPE_MASK (3 << 29) | |
| 220 | #define PFIT_PIPE_SHIFT 29 | |
| 221 | #define PFIT_SCALING_MODE_PILLARBOX (1 << 27) | |
| 222 | #define PFIT_SCALING_MODE_LETTERBOX (3 << 26) | |
| 223 | #define VERT_INTERP_DISABLE (0 << 10) | |
| 224 | #define VERT_INTERP_BILINEAR (1 << 10) | |
| 225 | #define VERT_INTERP_MASK (3 << 10) | |
| 226 | #define VERT_AUTO_SCALE (1 << 9) | |
| 227 | #define HORIZ_INTERP_DISABLE (0 << 6) | |
| 228 | #define HORIZ_INTERP_BILINEAR (1 << 6) | |
| 229 | #define HORIZ_INTERP_MASK (3 << 6) | |
| 230 | #define HORIZ_AUTO_SCALE (1 << 5) | |
| 231 | #define PANEL_8TO6_DITHER_ENABLE (1 << 3) | |
| 232 | ||
| 233 | #define PFIT_PGM_RATIOS 0x61234 | |
| 234 | #define PFIT_VERT_SCALE_MASK 0xfff00000 | |
| 235 | #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 | |
| 236 | ||
| 237 | #define PFIT_AUTO_RATIOS 0x61238 | |
| 238 | ||
| 239 | #define DPLL_A 0x06014 | |
| 240 | #define DPLL_B 0x06018 | |
| 241 | #define DPLL_VCO_ENABLE (1 << 31) | |
| 242 | #define DPLL_DVO_HIGH_SPEED (1 << 30) | |
| 243 | #define DPLL_SYNCLOCK_ENABLE (1 << 29) | |
| 244 | #define DPLL_VGA_MODE_DIS (1 << 28) | |
| 245 | #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ | |
| 246 | #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ | |
| 247 | #define DPLL_MODE_MASK (3 << 26) | |
| 248 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ | |
| 249 | #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ | |
| 250 | #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ | |
| 251 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ | |
| 252 | #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ | |
| ae0a246a | 253 | #define DPLL_FPA0h1_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
| 89c78134 AC |
254 | #define DPLL_LOCK (1 << 15) /* CDV */ |
| 255 | ||
| 256 | /* | |
| 257 | * The i830 generation, in DAC/serial mode, defines p1 as two plus this | |
| 258 | * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. | |
| 259 | */ | |
| 260 | # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 | |
| 261 | /* | |
| 262 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within | |
| 263 | * this field (only one bit may be set). | |
| 264 | */ | |
| 265 | #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 | |
| 266 | #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 | |
| 267 | #define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required | |
| 268 | * in DVO non-gang */ | |
| 269 | # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ | |
| 270 | #define PLL_REF_INPUT_DREFCLK (0 << 13) | |
| 271 | #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ | |
| 272 | #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO | |
| 273 | * TVCLKIN */ | |
| 274 | #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) | |
| 275 | #define PLL_REF_INPUT_MASK (3 << 13) | |
| 276 | #define PLL_LOAD_PULSE_PHASE_SHIFT 9 | |
| 277 | /* | |
| 278 | * Parallel to Serial Load Pulse phase selection. | |
| 279 | * Selects the phase for the 10X DPLL clock for the PCIe | |
| 280 | * digital display port. The range is 4 to 13; 10 or more | |
| 281 | * is just a flip delay. The default is 6 | |
| 282 | */ | |
| 283 | #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) | |
| 284 | #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) | |
| 285 | ||
| 286 | /* | |
| 287 | * SDVO multiplier for 945G/GM. Not used on 965. | |
| 288 | * | |
| 289 | * DPLL_MD_UDI_MULTIPLIER_MASK | |
| 290 | */ | |
| 291 | #define SDVO_MULTIPLIER_MASK 0x000000ff | |
| 292 | #define SDVO_MULTIPLIER_SHIFT_HIRES 4 | |
| 293 | #define SDVO_MULTIPLIER_SHIFT_VGA 0 | |
| 294 | ||
| 295 | /* | |
| 296 | * PLL_MD | |
| 297 | */ | |
| 298 | /* Pipe A SDVO/UDI clock multiplier/divider register for G965. */ | |
| 299 | #define DPLL_A_MD 0x0601c | |
| 300 | /* Pipe B SDVO/UDI clock multiplier/divider register for G965. */ | |
| 301 | #define DPLL_B_MD 0x06020 | |
| 302 | /* | |
| 303 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. | |
| 304 | * | |
| 305 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. | |
| 306 | */ | |
| 307 | #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 | |
| 308 | #define DPLL_MD_UDI_DIVIDER_SHIFT 24 | |
| 309 | /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ | |
| 310 | #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 | |
| 311 | #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 | |
| 312 | /* | |
| 313 | * SDVO/UDI pixel multiplier. | |
| 314 | * | |
| 315 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus | |
| 316 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate | |
| 317 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing | |
| 318 | * dummy bytes in the datastream at an increased clock rate, with both sides of | |
| 319 | * the link knowing how many bytes are fill. | |
| 320 | * | |
| 321 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock | |
| 322 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be | |
| 323 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and | |
| 324 | * through an SDVO command. | |
| 325 | * | |
| 326 | * This register field has values of multiplication factor minus 1, with | |
| 327 | * a maximum multiplier of 5 for SDVO. | |
| 328 | */ | |
| 329 | #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 | |
| 330 | #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 | |
| 331 | /* | |
| 332 | * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. | |
| 333 | * This best be set to the default value (3) or the CRT won't work. No, | |
| 334 | * I don't entirely understand what this does... | |
| 335 | */ | |
| 336 | #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f | |
| 337 | #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 | |
| 338 | ||
| 339 | #define DPLL_TEST 0x606c | |
| 340 | #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) | |
| 341 | #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) | |
| 342 | #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) | |
| 343 | #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) | |
| 344 | #define DPLLB_TEST_N_BYPASS (1 << 19) | |
| 345 | #define DPLLB_TEST_M_BYPASS (1 << 18) | |
| 346 | #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) | |
| 347 | #define DPLLA_TEST_N_BYPASS (1 << 3) | |
| 348 | #define DPLLA_TEST_M_BYPASS (1 << 2) | |
| 349 | #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) | |
| 350 | ||
| 351 | #define ADPA 0x61100 | |
| 352 | #define ADPA_DAC_ENABLE (1 << 31) | |
| 353 | #define ADPA_DAC_DISABLE 0 | |
| 354 | #define ADPA_PIPE_SELECT_MASK (1 << 30) | |
| 355 | #define ADPA_PIPE_A_SELECT 0 | |
| 356 | #define ADPA_PIPE_B_SELECT (1 << 30) | |
| 357 | #define ADPA_USE_VGA_HVPOLARITY (1 << 15) | |
| 358 | #define ADPA_SETS_HVPOLARITY 0 | |
| 359 | #define ADPA_VSYNC_CNTL_DISABLE (1 << 11) | |
| 360 | #define ADPA_VSYNC_CNTL_ENABLE 0 | |
| 361 | #define ADPA_HSYNC_CNTL_DISABLE (1 << 10) | |
| 362 | #define ADPA_HSYNC_CNTL_ENABLE 0 | |
| 363 | #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) | |
| 364 | #define ADPA_VSYNC_ACTIVE_LOW 0 | |
| 365 | #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) | |
| 366 | #define ADPA_HSYNC_ACTIVE_LOW 0 | |
| 367 | ||
| 368 | #define FPA0 0x06040 | |
| 369 | #define FPA1 0x06044 | |
| 370 | #define FPB0 0x06048 | |
| 371 | #define FPB1 0x0604c | |
| 372 | #define FP_N_DIV_MASK 0x003f0000 | |
| 373 | #define FP_N_DIV_SHIFT 16 | |
| 374 | #define FP_M1_DIV_MASK 0x00003f00 | |
| 375 | #define FP_M1_DIV_SHIFT 8 | |
| 376 | #define FP_M2_DIV_MASK 0x0000003f | |
| 377 | #define FP_M2_DIV_SHIFT 0 | |
| 378 | ||
| 379 | #define PORT_HOTPLUG_EN 0x61110 | |
| ae0a246a AC |
380 | #define HDMIB_HOTPLUG_INT_EN (1 << 29) |
| 381 | #define HDMIC_HOTPLUG_INT_EN (1 << 28) | |
| 382 | #define HDMID_HOTPLUG_INT_EN (1 << 27) | |
| 89c78134 AC |
383 | #define SDVOB_HOTPLUG_INT_EN (1 << 26) |
| 384 | #define SDVOC_HOTPLUG_INT_EN (1 << 25) | |
| 385 | #define TV_HOTPLUG_INT_EN (1 << 18) | |
| 386 | #define CRT_HOTPLUG_INT_EN (1 << 9) | |
| 387 | #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) | |
| 388 | /* CDV.. */ | |
| 389 | #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) | |
| 390 | #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) | |
| 391 | #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) | |
| 392 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) | |
| 393 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) | |
| 394 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) | |
| 395 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) | |
| 396 | #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) | |
| 397 | #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) | |
| 398 | #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) | |
| 399 | #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) | |
| 400 | #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) | |
| 401 | #define CRT_HOTPLUG_DETECT_MASK 0x000000F8 | |
| 402 | ||
| 403 | #define PORT_HOTPLUG_STAT 0x61114 | |
| 404 | #define CRT_HOTPLUG_INT_STATUS (1 << 11) | |
| 405 | #define TV_HOTPLUG_INT_STATUS (1 << 10) | |
| 406 | #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) | |
| 407 | #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) | |
| 408 | #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) | |
| 409 | #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) | |
| 410 | #define SDVOC_HOTPLUG_INT_STATUS (1 << 7) | |
| 411 | #define SDVOB_HOTPLUG_INT_STATUS (1 << 6) | |
| 412 | ||
| 413 | #define SDVOB 0x61140 | |
| 414 | #define SDVOC 0x61160 | |
| 415 | #define SDVO_ENABLE (1 << 31) | |
| 416 | #define SDVO_PIPE_B_SELECT (1 << 30) | |
| 417 | #define SDVO_STALL_SELECT (1 << 29) | |
| 418 | #define SDVO_INTERRUPT_ENABLE (1 << 26) | |
| 5736995b PJ |
419 | #define SDVO_COLOR_RANGE_16_235 (1 << 8) |
| 420 | #define SDVO_AUDIO_ENABLE (1 << 6) | |
| 89c78134 AC |
421 | |
| 422 | /** | |
| 423 | * 915G/GM SDVO pixel multiplier. | |
| 424 | * | |
| 425 | * Programmed value is multiplier - 1, up to 5x. | |
| 426 | * | |
| 427 | * DPLL_MD_UDI_MULTIPLIER_MASK | |
| 428 | */ | |
| 429 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) | |
| 430 | #define SDVO_PORT_MULTIPLY_SHIFT 23 | |
| 431 | #define SDVO_PHASE_SELECT_MASK (15 << 19) | |
| 432 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) | |
| 433 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) | |
| 434 | #define SDVOC_GANG_MODE (1 << 16) | |
| 435 | #define SDVO_BORDER_ENABLE (1 << 7) | |
| 436 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) | |
| 437 | #define SDVO_DETECTED (1 << 2) | |
| 438 | /* Bits to be preserved when writing */ | |
| 439 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) | |
| 440 | #define SDVOC_PRESERVE_MASK (1 << 17) | |
| 441 | ||
| 442 | /* | |
| 443 | * This register controls the LVDS output enable, pipe selection, and data | |
| 444 | * format selection. | |
| 445 | * | |
| 446 | * All of the clock/data pairs are force powered down by power sequencing. | |
| 447 | */ | |
| 448 | #define LVDS 0x61180 | |
| 449 | /* | |
| 450 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as | |
| 451 | * the DPLL semantics change when the LVDS is assigned to that pipe. | |
| 452 | */ | |
| 453 | #define LVDS_PORT_EN (1 << 31) | |
| 454 | /* Selects pipe B for LVDS data. Must be set on pre-965. */ | |
| 455 | #define LVDS_PIPEB_SELECT (1 << 30) | |
| 456 | ||
| 457 | /* Turns on border drawing to allow centered display. */ | |
| 458 | #define LVDS_BORDER_EN (1 << 15) | |
| 459 | ||
| 460 | /* | |
| 461 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per | |
| 462 | * pixel. | |
| 463 | */ | |
| 464 | #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) | |
| 465 | #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) | |
| 466 | #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) | |
| 467 | /* | |
| 468 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit | |
| 469 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be | |
| 470 | * on. | |
| 471 | */ | |
| 472 | #define LVDS_A3_POWER_MASK (3 << 6) | |
| 473 | #define LVDS_A3_POWER_DOWN (0 << 6) | |
| 474 | #define LVDS_A3_POWER_UP (3 << 6) | |
| 475 | /* | |
| 476 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP | |
| 477 | * is set. | |
| 478 | */ | |
| 479 | #define LVDS_CLKB_POWER_MASK (3 << 4) | |
| 480 | #define LVDS_CLKB_POWER_DOWN (0 << 4) | |
| 481 | #define LVDS_CLKB_POWER_UP (3 << 4) | |
| 482 | /* | |
| 483 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 | |
| 484 | * setting for whether we are in dual-channel mode. The B3 pair will | |
| 485 | * additionally only be powered up when LVDS_A3_POWER_UP is set. | |
| 486 | */ | |
| 487 | #define LVDS_B0B3_POWER_MASK (3 << 2) | |
| 488 | #define LVDS_B0B3_POWER_DOWN (0 << 2) | |
| 489 | #define LVDS_B0B3_POWER_UP (3 << 2) | |
| 490 | ||
| 491 | #define PIPEACONF 0x70008 | |
| 492 | #define PIPEACONF_ENABLE (1 << 31) | |
| 493 | #define PIPEACONF_DISABLE 0 | |
| 494 | #define PIPEACONF_DOUBLE_WIDE (1 << 30) | |
| 495 | #define PIPECONF_ACTIVE (1 << 30) | |
| 89c78134 AC |
496 | #define PIPECONF_DSIPLL_LOCK (1 << 29) |
| 497 | #define PIPEACONF_SINGLE_WIDE 0 | |
| 498 | #define PIPEACONF_PIPE_UNLOCKED 0 | |
| 499 | #define PIPEACONF_DSR (1 << 26) | |
| 500 | #define PIPEACONF_PIPE_LOCKED (1 << 25) | |
| 501 | #define PIPEACONF_PALETTE 0 | |
| 502 | #define PIPECONF_FORCE_BORDER (1 << 25) | |
| 503 | #define PIPEACONF_GAMMA (1 << 24) | |
| 504 | #define PIPECONF_PROGRESSIVE (0 << 21) | |
| 505 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) | |
| 506 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) | |
| 507 | #define PIPECONF_PLANE_OFF (1 << 19) | |
| 508 | #define PIPECONF_CURSOR_OFF (1 << 18) | |
| 509 | ||
| 510 | #define PIPEBCONF 0x71008 | |
| 511 | #define PIPEBCONF_ENABLE (1 << 31) | |
| 512 | #define PIPEBCONF_DISABLE 0 | |
| 513 | #define PIPEBCONF_DOUBLE_WIDE (1 << 30) | |
| 514 | #define PIPEBCONF_DISABLE 0 | |
| 515 | #define PIPEBCONF_GAMMA (1 << 24) | |
| 516 | #define PIPEBCONF_PALETTE 0 | |
| 517 | ||
| 518 | #define PIPECCONF 0x72008 | |
| 519 | ||
| 520 | #define PIPEBGCMAXRED 0x71010 | |
| 521 | #define PIPEBGCMAXGREEN 0x71014 | |
| 522 | #define PIPEBGCMAXBLUE 0x71018 | |
| 523 | ||
| 524 | #define PIPEASTAT 0x70024 | |
| 525 | #define PIPEBSTAT 0x71024 | |
| 526 | #define PIPECSTAT 0x72024 | |
| 527 | #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) | |
| 528 | #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) | |
| 529 | #define PIPE_VBLANK_CLEAR (1 << 1) | |
| 530 | #define PIPE_VBLANK_STATUS (1 << 1) | |
| 531 | #define PIPE_TE_STATUS (1UL << 6) | |
| 532 | #define PIPE_DPST_EVENT_STATUS (1UL << 7) | |
| 533 | #define PIPE_VSYNC_CLEAR (1UL << 9) | |
| 534 | #define PIPE_VSYNC_STATUS (1UL << 9) | |
| 535 | #define PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL << 10) | |
| 536 | #define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL << 11) | |
| 537 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) | |
| 538 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) | |
| 539 | #define PIPE_TE_ENABLE (1UL << 22) | |
| d839ede4 | 540 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) |
| 89c78134 AC |
541 | #define PIPE_DPST_EVENT_ENABLE (1UL << 23) |
| 542 | #define PIPE_VSYNC_ENABL (1UL << 25) | |
| 543 | #define PIPE_HDMI_AUDIO_UNDERRUN (1UL << 26) | |
| 544 | #define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL << 27) | |
| acd7ef92 | 545 | #define PIPE_FIFO_UNDERRUN (1UL << 31) |
| 89c78134 AC |
546 | #define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | \ |
| 547 | PIPE_HDMI_AUDIO_BUFFER_DONE) | |
| 548 | #define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16)) | |
| 549 | #define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17)) | |
| 550 | #define HISTOGRAM_INT_CONTROL 0x61268 | |
| 551 | #define HISTOGRAM_BIN_DATA 0X61264 | |
| 552 | #define HISTOGRAM_LOGIC_CONTROL 0x61260 | |
| 553 | #define PWM_CONTROL_LOGIC 0x61250 | |
| 554 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) | |
| 555 | #define HISTOGRAM_INTERRUPT_ENABLE (1UL << 31) | |
| 556 | #define HISTOGRAM_LOGIC_ENABLE (1UL << 31) | |
| 557 | #define PWM_LOGIC_ENABLE (1UL << 31) | |
| 558 | #define PWM_PHASEIN_ENABLE (1UL << 25) | |
| 559 | #define PWM_PHASEIN_INT_ENABLE (1UL << 24) | |
| 560 | #define PWM_PHASEIN_VB_COUNT 0x00001f00 | |
| 561 | #define PWM_PHASEIN_INC 0x0000001f | |
| 562 | #define HISTOGRAM_INT_CTRL_CLEAR (1UL << 30) | |
| 563 | #define DPST_YUV_LUMA_MODE 0 | |
| 564 | ||
| 565 | struct dpst_ie_histogram_control { | |
| 566 | union { | |
| 567 | uint32_t data; | |
| 568 | struct { | |
| 569 | uint32_t bin_reg_index:7; | |
| 570 | uint32_t reserved:4; | |
| 571 | uint32_t bin_reg_func_select:1; | |
| 572 | uint32_t sync_to_phase_in:1; | |
| 573 | uint32_t alt_enhancement_mode:2; | |
| 574 | uint32_t reserved1:1; | |
| 575 | uint32_t sync_to_phase_in_count:8; | |
| 576 | uint32_t histogram_mode_select:1; | |
| 577 | uint32_t reserved2:4; | |
| 578 | uint32_t ie_pipe_assignment:1; | |
| 579 | uint32_t ie_mode_table_enabled:1; | |
| 580 | uint32_t ie_histogram_enable:1; | |
| 581 | }; | |
| 582 | }; | |
| 583 | }; | |
| 584 | ||
| 585 | struct dpst_guardband { | |
| 586 | union { | |
| 587 | uint32_t data; | |
| 588 | struct { | |
| 589 | uint32_t guardband:22; | |
| 590 | uint32_t guardband_interrupt_delay:8; | |
| 591 | uint32_t interrupt_status:1; | |
| 592 | uint32_t interrupt_enable:1; | |
| 593 | }; | |
| 594 | }; | |
| 595 | }; | |
| 596 | ||
| 597 | #define PIPEAFRAMEHIGH 0x70040 | |
| 598 | #define PIPEAFRAMEPIXEL 0x70044 | |
| 599 | #define PIPEBFRAMEHIGH 0x71040 | |
| 600 | #define PIPEBFRAMEPIXEL 0x71044 | |
| 601 | #define PIPECFRAMEHIGH 0x72040 | |
| 602 | #define PIPECFRAMEPIXEL 0x72044 | |
| 603 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff | |
| 604 | #define PIPE_FRAME_HIGH_SHIFT 0 | |
| 605 | #define PIPE_FRAME_LOW_MASK 0xff000000 | |
| 606 | #define PIPE_FRAME_LOW_SHIFT 24 | |
| 607 | #define PIPE_PIXEL_MASK 0x00ffffff | |
| 608 | #define PIPE_PIXEL_SHIFT 0 | |
| 609 | ||
| acd7ef92 AC |
610 | #define FW_BLC_SELF 0x20e0 |
| 611 | #define FW_BLC_SELF_EN (1<<15) | |
| 612 | ||
| 89c78134 AC |
613 | #define DSPARB 0x70030 |
| 614 | #define DSPFW1 0x70034 | |
| acd7ef92 AC |
615 | #define DSP_FIFO_SR_WM_MASK 0xFF800000 |
| 616 | #define DSP_FIFO_SR_WM_SHIFT 23 | |
| 617 | #define CURSOR_B_FIFO_WM_MASK 0x003F0000 | |
| 618 | #define CURSOR_B_FIFO_WM_SHIFT 16 | |
| 89c78134 | 619 | #define DSPFW2 0x70038 |
| acd7ef92 AC |
620 | #define CURSOR_A_FIFO_WM_MASK 0x3F00 |
| 621 | #define CURSOR_A_FIFO_WM_SHIFT 8 | |
| 622 | #define DSP_PLANE_C_FIFO_WM_MASK 0x7F | |
| 623 | #define DSP_PLANE_C_FIFO_WM_SHIFT 0 | |
| 89c78134 AC |
624 | #define DSPFW3 0x7003c |
| 625 | #define DSPFW4 0x70050 | |
| 626 | #define DSPFW5 0x70054 | |
| acd7ef92 AC |
627 | #define DSP_PLANE_B_FIFO_WM1_SHIFT 24 |
| 628 | #define DSP_PLANE_A_FIFO_WM1_SHIFT 16 | |
| 629 | #define CURSOR_B_FIFO_WM1_SHIFT 8 | |
| 630 | #define CURSOR_FIFO_SR_WM1_SHIFT 0 | |
| 89c78134 AC |
631 | #define DSPFW6 0x70058 |
| 632 | #define DSPCHICKENBIT 0x70400 | |
| 633 | #define DSPACNTR 0x70180 | |
| 634 | #define DSPBCNTR 0x71180 | |
| 635 | #define DSPCCNTR 0x72180 | |
| 636 | #define DISPLAY_PLANE_ENABLE (1 << 31) | |
| 637 | #define DISPLAY_PLANE_DISABLE 0 | |
| 638 | #define DISPPLANE_GAMMA_ENABLE (1 << 30) | |
| 639 | #define DISPPLANE_GAMMA_DISABLE 0 | |
| 640 | #define DISPPLANE_PIXFORMAT_MASK (0xf << 26) | |
| 641 | #define DISPPLANE_8BPP (0x2 << 26) | |
| 642 | #define DISPPLANE_15_16BPP (0x4 << 26) | |
| 643 | #define DISPPLANE_16BPP (0x5 << 26) | |
| 644 | #define DISPPLANE_32BPP_NO_ALPHA (0x6 << 26) | |
| 645 | #define DISPPLANE_32BPP (0x7 << 26) | |
| 646 | #define DISPPLANE_STEREO_ENABLE (1 << 25) | |
| 647 | #define DISPPLANE_STEREO_DISABLE 0 | |
| 648 | #define DISPPLANE_SEL_PIPE_MASK (1 << 24) | |
| 649 | #define DISPPLANE_SEL_PIPE_POS 24 | |
| 650 | #define DISPPLANE_SEL_PIPE_A 0 | |
| 651 | #define DISPPLANE_SEL_PIPE_B (1 << 24) | |
| 652 | #define DISPPLANE_SRC_KEY_ENABLE (1 << 22) | |
| 653 | #define DISPPLANE_SRC_KEY_DISABLE 0 | |
| 654 | #define DISPPLANE_LINE_DOUBLE (1 << 20) | |
| 655 | #define DISPPLANE_NO_LINE_DOUBLE 0 | |
| 656 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 | |
| 657 | #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18) | |
| 658 | /* plane B only */ | |
| 659 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) | |
| 660 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 | |
| 661 | #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 | |
| 662 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) | |
| 663 | #define DISPPLANE_BOTTOM (4) | |
| 664 | ||
| 665 | #define DSPABASE 0x70184 | |
| 666 | #define DSPALINOFF 0x70184 | |
| 667 | #define DSPASTRIDE 0x70188 | |
| 668 | ||
| 669 | #define DSPBBASE 0x71184 | |
| 670 | #define DSPBLINOFF 0X71184 | |
| 671 | #define DSPBADDR DSPBBASE | |
| 672 | #define DSPBSTRIDE 0x71188 | |
| 673 | ||
| 674 | #define DSPCBASE 0x72184 | |
| 675 | #define DSPCLINOFF 0x72184 | |
| 676 | #define DSPCSTRIDE 0x72188 | |
| 677 | ||
| 678 | #define DSPAKEYVAL 0x70194 | |
| 679 | #define DSPAKEYMASK 0x70198 | |
| 680 | ||
| 681 | #define DSPAPOS 0x7018C /* reserved */ | |
| 682 | #define DSPASIZE 0x70190 | |
| 683 | #define DSPBPOS 0x7118C | |
| 684 | #define DSPBSIZE 0x71190 | |
| 685 | #define DSPCPOS 0x7218C | |
| 686 | #define DSPCSIZE 0x72190 | |
| 687 | ||
| 688 | #define DSPASURF 0x7019C | |
| 689 | #define DSPATILEOFF 0x701A4 | |
| 690 | ||
| 691 | #define DSPBSURF 0x7119C | |
| 692 | #define DSPBTILEOFF 0x711A4 | |
| 693 | ||
| 694 | #define DSPCSURF 0x7219C | |
| 695 | #define DSPCTILEOFF 0x721A4 | |
| 696 | #define DSPCKEYMAXVAL 0x721A0 | |
| 697 | #define DSPCKEYMINVAL 0x72194 | |
| 698 | #define DSPCKEYMSK 0x72198 | |
| 699 | ||
| 700 | #define VGACNTRL 0x71400 | |
| 701 | #define VGA_DISP_DISABLE (1 << 31) | |
| 702 | #define VGA_2X_MODE (1 << 30) | |
| 703 | #define VGA_PIPE_B_SELECT (1 << 29) | |
| 704 | ||
| 705 | /* | |
| 706 | * Overlay registers | |
| 707 | */ | |
| 708 | #define OV_C_OFFSET 0x08000 | |
| 709 | #define OV_OVADD 0x30000 | |
| 710 | #define OV_DOVASTA 0x30008 | |
| 711 | # define OV_PIPE_SELECT ((1 << 6)|(1 << 7)) | |
| 712 | # define OV_PIPE_SELECT_POS 6 | |
| 713 | # define OV_PIPE_A 0 | |
| 714 | # define OV_PIPE_C 1 | |
| 715 | #define OV_OGAMC5 0x30010 | |
| 716 | #define OV_OGAMC4 0x30014 | |
| 717 | #define OV_OGAMC3 0x30018 | |
| 718 | #define OV_OGAMC2 0x3001C | |
| 719 | #define OV_OGAMC1 0x30020 | |
| 720 | #define OV_OGAMC0 0x30024 | |
| 721 | #define OVC_OVADD 0x38000 | |
| 722 | #define OVC_DOVCSTA 0x38008 | |
| 723 | #define OVC_OGAMC5 0x38010 | |
| 724 | #define OVC_OGAMC4 0x38014 | |
| 725 | #define OVC_OGAMC3 0x38018 | |
| 726 | #define OVC_OGAMC2 0x3801C | |
| 727 | #define OVC_OGAMC1 0x38020 | |
| 728 | #define OVC_OGAMC0 0x38024 | |
| 729 | ||
| 730 | /* | |
| 731 | * Some BIOS scratch area registers. The 845 (and 830?) store the amount | |
| 732 | * of video memory available to the BIOS in SWF1. | |
| 733 | */ | |
| 734 | #define SWF0 0x71410 | |
| 735 | #define SWF1 0x71414 | |
| 736 | #define SWF2 0x71418 | |
| 737 | #define SWF3 0x7141c | |
| 738 | #define SWF4 0x71420 | |
| 739 | #define SWF5 0x71424 | |
| 740 | #define SWF6 0x71428 | |
| 741 | ||
| 742 | /* | |
| 743 | * 855 scratch registers. | |
| 744 | */ | |
| 745 | #define SWF00 0x70410 | |
| 746 | #define SWF01 0x70414 | |
| 747 | #define SWF02 0x70418 | |
| 748 | #define SWF03 0x7041c | |
| 749 | #define SWF04 0x70420 | |
| 750 | #define SWF05 0x70424 | |
| 751 | #define SWF06 0x70428 | |
| 752 | ||
| 753 | #define SWF10 SWF0 | |
| 754 | #define SWF11 SWF1 | |
| 755 | #define SWF12 SWF2 | |
| 756 | #define SWF13 SWF3 | |
| 757 | #define SWF14 SWF4 | |
| 758 | #define SWF15 SWF5 | |
| 759 | #define SWF16 SWF6 | |
| 760 | ||
| 761 | #define SWF30 0x72414 | |
| 762 | #define SWF31 0x72418 | |
| 763 | #define SWF32 0x7241c | |
| 764 | ||
| 765 | ||
| 766 | /* | |
| 767 | * Palette registers | |
| 768 | */ | |
| 769 | #define PALETTE_A 0x0a000 | |
| 770 | #define PALETTE_B 0x0a800 | |
| 771 | #define PALETTE_C 0x0ac00 | |
| 772 | ||
| 773 | /* Cursor A & B regs */ | |
| 774 | #define CURACNTR 0x70080 | |
| 775 | #define CURSOR_MODE_DISABLE 0x00 | |
| 776 | #define CURSOR_MODE_64_32B_AX 0x07 | |
| 777 | #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) | |
| 778 | #define MCURSOR_GAMMA_ENABLE (1 << 26) | |
| 779 | #define CURABASE 0x70084 | |
| 780 | #define CURAPOS 0x70088 | |
| 781 | #define CURSOR_POS_MASK 0x007FF | |
| 782 | #define CURSOR_POS_SIGN 0x8000 | |
| 783 | #define CURSOR_X_SHIFT 0 | |
| 784 | #define CURSOR_Y_SHIFT 16 | |
| 785 | #define CURBCNTR 0x700c0 | |
| 786 | #define CURBBASE 0x700c4 | |
| 787 | #define CURBPOS 0x700c8 | |
| 788 | #define CURCCNTR 0x700e0 | |
| 789 | #define CURCBASE 0x700e4 | |
| 790 | #define CURCPOS 0x700e8 | |
| 791 | ||
| 792 | /* | |
| 793 | * Interrupt Registers | |
| 794 | */ | |
| 795 | #define IER 0x020a0 | |
| 796 | #define IIR 0x020a4 | |
| 797 | #define IMR 0x020a8 | |
| 798 | #define ISR 0x020ac | |
| 799 | ||
| 800 | /* | |
| 801 | * MOORESTOWN delta registers | |
| 802 | */ | |
| 803 | #define MRST_DPLL_A 0x0f014 | |
| 804 | #define MDFLD_DPLL_B 0x0f018 | |
| 805 | #define MDFLD_INPUT_REF_SEL (1 << 14) | |
| 806 | #define MDFLD_VCO_SEL (1 << 16) | |
| 807 | #define DPLLA_MODE_LVDS (2 << 26) /* mrst */ | |
| 808 | #define MDFLD_PLL_LATCHEN (1 << 28) | |
| 809 | #define MDFLD_PWR_GATE_EN (1 << 30) | |
| 810 | #define MDFLD_P1_MASK (0x1FF << 17) | |
| 811 | #define MRST_FPA0 0x0f040 | |
| 812 | #define MRST_FPA1 0x0f044 | |
| 813 | #define MDFLD_DPLL_DIV0 0x0f048 | |
| 814 | #define MDFLD_DPLL_DIV1 0x0f04c | |
| 815 | #define MRST_PERF_MODE 0x020f4 | |
| 816 | ||
| 817 | /* | |
| 818 | * MEDFIELD HDMI registers | |
| 819 | */ | |
| 820 | #define HDMIPHYMISCCTL 0x61134 | |
| 821 | #define HDMI_PHY_POWER_DOWN 0x7f | |
| 822 | #define HDMIB_CONTROL 0x61140 | |
| 823 | #define HDMIB_PORT_EN (1 << 31) | |
| 824 | #define HDMIB_PIPE_B_SELECT (1 << 30) | |
| 825 | #define HDMIB_NULL_PACKET (1 << 9) | |
| 826 | #define HDMIB_HDCP_PORT (1 << 5) | |
| 827 | ||
| 828 | /* #define LVDS 0x61180 */ | |
| 829 | #define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25) | |
| 830 | #define MRST_PANEL_24_DOT_1_FORMAT (1 << 24) | |
| 831 | #define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6) | |
| 832 | ||
| 833 | #define MIPI 0x61190 | |
| 834 | #define MIPI_C 0x62190 | |
| 835 | #define MIPI_PORT_EN (1 << 31) | |
| 836 | /* Turns on border drawing to allow centered display. */ | |
| 837 | #define SEL_FLOPPED_HSTX (1 << 23) | |
| 838 | #define PASS_FROM_SPHY_TO_AFE (1 << 16) | |
| 839 | #define MIPI_BORDER_EN (1 << 15) | |
| 840 | #define MIPIA_3LANE_MIPIC_1LANE 0x1 | |
| 841 | #define MIPIA_2LANE_MIPIC_2LANE 0x2 | |
| 842 | #define TE_TRIGGER_DSI_PROTOCOL (1 << 2) | |
| 843 | #define TE_TRIGGER_GPIO_PIN (1 << 3) | |
| 844 | #define MIPI_TE_COUNT 0x61194 | |
| 845 | ||
| 846 | /* #define PP_CONTROL 0x61204 */ | |
| 847 | #define POWER_DOWN_ON_RESET (1 << 1) | |
| 848 | ||
| 849 | /* #define PFIT_CONTROL 0x61230 */ | |
| 850 | #define PFIT_PIPE_SELECT (3 << 29) | |
| 851 | #define PFIT_PIPE_SELECT_SHIFT (29) | |
| 852 | ||
| 853 | /* #define BLC_PWM_CTL 0x61254 */ | |
| 854 | #define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16) | |
| 855 | #define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16) | |
| 856 | ||
| 857 | /* #define PIPEACONF 0x70008 */ | |
| 858 | #define PIPEACONF_PIPE_STATE (1 << 30) | |
| 859 | /* #define DSPACNTR 0x70180 */ | |
| 860 | ||
| 861 | #define MRST_DSPABASE 0x7019c | |
| 862 | #define MRST_DSPBBASE 0x7119c | |
| 863 | #define MDFLD_DSPCBASE 0x7219c | |
| 864 | ||
| 865 | /* | |
| 866 | * Moorestown registers. | |
| 867 | */ | |
| 868 | ||
| 869 | /* | |
| 870 | * MIPI IP registers | |
| 871 | */ | |
| 872 | #define MIPIC_REG_OFFSET 0x800 | |
| 873 | ||
| 874 | #define DEVICE_READY_REG 0xb000 | |
| 875 | #define LP_OUTPUT_HOLD (1 << 16) | |
| 876 | #define EXIT_ULPS_DEV_READY 0x3 | |
| 877 | #define LP_OUTPUT_HOLD_RELEASE 0x810000 | |
| 878 | # define ENTERING_ULPS (2 << 1) | |
| 879 | # define EXITING_ULPS (1 << 1) | |
| 880 | # define ULPS_MASK (3 << 1) | |
| 881 | # define BUS_POSSESSION (1 << 3) | |
| 882 | #define INTR_STAT_REG 0xb004 | |
| 883 | #define RX_SOT_ERROR (1 << 0) | |
| 884 | #define RX_SOT_SYNC_ERROR (1 << 1) | |
| 885 | #define RX_ESCAPE_MODE_ENTRY_ERROR (1 << 3) | |
| 886 | #define RX_LP_TX_SYNC_ERROR (1 << 4) | |
| 887 | #define RX_HS_RECEIVE_TIMEOUT_ERROR (1 << 5) | |
| 888 | #define RX_FALSE_CONTROL_ERROR (1 << 6) | |
| 889 | #define RX_ECC_SINGLE_BIT_ERROR (1 << 7) | |
| 890 | #define RX_ECC_MULTI_BIT_ERROR (1 << 8) | |
| 891 | #define RX_CHECKSUM_ERROR (1 << 9) | |
| 892 | #define RX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 10) | |
| 893 | #define RX_DSI_VC_ID_INVALID (1 << 11) | |
| 894 | #define TX_FALSE_CONTROL_ERROR (1 << 12) | |
| 895 | #define TX_ECC_SINGLE_BIT_ERROR (1 << 13) | |
| 896 | #define TX_ECC_MULTI_BIT_ERROR (1 << 14) | |
| 897 | #define TX_CHECKSUM_ERROR (1 << 15) | |
| 898 | #define TX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 16) | |
| 899 | #define TX_DSI_VC_ID_INVALID (1 << 17) | |
| 900 | #define HIGH_CONTENTION (1 << 18) | |
| 901 | #define LOW_CONTENTION (1 << 19) | |
| 902 | #define DPI_FIFO_UNDER_RUN (1 << 20) | |
| 903 | #define HS_TX_TIMEOUT (1 << 21) | |
| 904 | #define LP_RX_TIMEOUT (1 << 22) | |
| 905 | #define TURN_AROUND_ACK_TIMEOUT (1 << 23) | |
| 906 | #define ACK_WITH_NO_ERROR (1 << 24) | |
| 907 | #define HS_GENERIC_WR_FIFO_FULL (1 << 27) | |
| 908 | #define LP_GENERIC_WR_FIFO_FULL (1 << 28) | |
| 909 | #define SPL_PKT_SENT (1 << 30) | |
| 910 | #define INTR_EN_REG 0xb008 | |
| 911 | #define DSI_FUNC_PRG_REG 0xb00c | |
| 912 | #define DPI_CHANNEL_NUMBER_POS 0x03 | |
| 913 | #define DBI_CHANNEL_NUMBER_POS 0x05 | |
| 914 | #define FMT_DPI_POS 0x07 | |
| 915 | #define FMT_DBI_POS 0x0A | |
| 916 | #define DBI_DATA_WIDTH_POS 0x0D | |
| 917 | ||
| 918 | /* DPI PIXEL FORMATS */ | |
| 919 | #define RGB_565_FMT 0x01 /* RGB 565 FORMAT */ | |
| 920 | #define RGB_666_FMT 0x02 /* RGB 666 FORMAT */ | |
| 921 | #define LRGB_666_FMT 0x03 /* RGB LOOSELY PACKED | |
| 922 | * 666 FORMAT | |
| 923 | */ | |
| 924 | #define RGB_888_FMT 0x04 /* RGB 888 FORMAT */ | |
| 925 | #define VIRTUAL_CHANNEL_NUMBER_0 0x00 /* Virtual channel 0 */ | |
| 926 | #define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */ | |
| 927 | #define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */ | |
| 928 | #define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */ | |
| 929 | ||
| 930 | #define DBI_NOT_SUPPORTED 0x00 /* command mode | |
| 931 | * is not supported | |
| 932 | */ | |
| 933 | #define DBI_DATA_WIDTH_16BIT 0x01 /* 16 bit data */ | |
| 934 | #define DBI_DATA_WIDTH_9BIT 0x02 /* 9 bit data */ | |
| 935 | #define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */ | |
| 936 | #define DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */ | |
| 937 | #define DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */ | |
| 938 | ||
| 939 | #define HS_TX_TIMEOUT_REG 0xb010 | |
| 940 | #define LP_RX_TIMEOUT_REG 0xb014 | |
| 941 | #define TURN_AROUND_TIMEOUT_REG 0xb018 | |
| 942 | #define DEVICE_RESET_REG 0xb01C | |
| 943 | #define DPI_RESOLUTION_REG 0xb020 | |
| 944 | #define RES_V_POS 0x10 | |
| 945 | #define DBI_RESOLUTION_REG 0xb024 /* Reserved for MDFLD */ | |
| 946 | #define HORIZ_SYNC_PAD_COUNT_REG 0xb028 | |
| 947 | #define HORIZ_BACK_PORCH_COUNT_REG 0xb02C | |
| 948 | #define HORIZ_FRONT_PORCH_COUNT_REG 0xb030 | |
| 949 | #define HORIZ_ACTIVE_AREA_COUNT_REG 0xb034 | |
| 950 | #define VERT_SYNC_PAD_COUNT_REG 0xb038 | |
| 951 | #define VERT_BACK_PORCH_COUNT_REG 0xb03c | |
| 952 | #define VERT_FRONT_PORCH_COUNT_REG 0xb040 | |
| 953 | #define HIGH_LOW_SWITCH_COUNT_REG 0xb044 | |
| 954 | #define DPI_CONTROL_REG 0xb048 | |
| 955 | #define DPI_SHUT_DOWN (1 << 0) | |
| 956 | #define DPI_TURN_ON (1 << 1) | |
| 957 | #define DPI_COLOR_MODE_ON (1 << 2) | |
| 958 | #define DPI_COLOR_MODE_OFF (1 << 3) | |
| 959 | #define DPI_BACK_LIGHT_ON (1 << 4) | |
| 960 | #define DPI_BACK_LIGHT_OFF (1 << 5) | |
| 961 | #define DPI_LP (1 << 6) | |
| 962 | #define DPI_DATA_REG 0xb04c | |
| 963 | #define DPI_BACK_LIGHT_ON_DATA 0x07 | |
| 964 | #define DPI_BACK_LIGHT_OFF_DATA 0x17 | |
| 965 | #define INIT_COUNT_REG 0xb050 | |
| 966 | #define MAX_RET_PAK_REG 0xb054 | |
| 967 | #define VIDEO_FMT_REG 0xb058 | |
| 968 | #define COMPLETE_LAST_PCKT (1 << 2) | |
| 969 | #define EOT_DISABLE_REG 0xb05c | |
| 970 | #define ENABLE_CLOCK_STOPPING (1 << 1) | |
| 971 | #define LP_BYTECLK_REG 0xb060 | |
| 972 | #define LP_GEN_DATA_REG 0xb064 | |
| 973 | #define HS_GEN_DATA_REG 0xb068 | |
| 974 | #define LP_GEN_CTRL_REG 0xb06C | |
| 975 | #define HS_GEN_CTRL_REG 0xb070 | |
| 976 | #define DCS_CHANNEL_NUMBER_POS 0x6 | |
| 977 | #define MCS_COMMANDS_POS 0x8 | |
| 978 | #define WORD_COUNTS_POS 0x8 | |
| 979 | #define MCS_PARAMETER_POS 0x10 | |
| 980 | #define GEN_FIFO_STAT_REG 0xb074 | |
| 981 | #define HS_DATA_FIFO_FULL (1 << 0) | |
| 982 | #define HS_DATA_FIFO_HALF_EMPTY (1 << 1) | |
| 983 | #define HS_DATA_FIFO_EMPTY (1 << 2) | |
| 984 | #define LP_DATA_FIFO_FULL (1 << 8) | |
| 985 | #define LP_DATA_FIFO_HALF_EMPTY (1 << 9) | |
| 986 | #define LP_DATA_FIFO_EMPTY (1 << 10) | |
| 987 | #define HS_CTRL_FIFO_FULL (1 << 16) | |
| 988 | #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) | |
| 989 | #define HS_CTRL_FIFO_EMPTY (1 << 18) | |
| 990 | #define LP_CTRL_FIFO_FULL (1 << 24) | |
| 991 | #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) | |
| 992 | #define LP_CTRL_FIFO_EMPTY (1 << 26) | |
| 993 | #define DBI_FIFO_EMPTY (1 << 27) | |
| 994 | #define DPI_FIFO_EMPTY (1 << 28) | |
| 995 | #define HS_LS_DBI_ENABLE_REG 0xb078 | |
| 996 | #define TXCLKESC_REG 0xb07c | |
| 997 | #define DPHY_PARAM_REG 0xb080 | |
| 998 | #define DBI_BW_CTRL_REG 0xb084 | |
| 999 | #define CLK_LANE_SWT_REG 0xb088 | |
| 1000 | ||
| 1001 | /* | |
| 1002 | * MIPI Adapter registers | |
| 1003 | */ | |
| 1004 | #define MIPI_CONTROL_REG 0xb104 | |
| 1005 | #define MIPI_2X_CLOCK_BITS ((1 << 0) | (1 << 1)) | |
| 1006 | #define MIPI_DATA_ADDRESS_REG 0xb108 | |
| 1007 | #define MIPI_DATA_LENGTH_REG 0xb10C | |
| 1008 | #define MIPI_COMMAND_ADDRESS_REG 0xb110 | |
| 1009 | #define MIPI_COMMAND_LENGTH_REG 0xb114 | |
| 1010 | #define MIPI_READ_DATA_RETURN_REG0 0xb118 | |
| 1011 | #define MIPI_READ_DATA_RETURN_REG1 0xb11C | |
| 1012 | #define MIPI_READ_DATA_RETURN_REG2 0xb120 | |
| 1013 | #define MIPI_READ_DATA_RETURN_REG3 0xb124 | |
| 1014 | #define MIPI_READ_DATA_RETURN_REG4 0xb128 | |
| 1015 | #define MIPI_READ_DATA_RETURN_REG5 0xb12C | |
| 1016 | #define MIPI_READ_DATA_RETURN_REG6 0xb130 | |
| 1017 | #define MIPI_READ_DATA_RETURN_REG7 0xb134 | |
| 1018 | #define MIPI_READ_DATA_VALID_REG 0xb138 | |
| 1019 | ||
| 1020 | /* DBI COMMANDS */ | |
| 1021 | #define soft_reset 0x01 | |
| 1022 | /* | |
| 1023 | * The display module performs a software reset. | |
| 1024 | * Registers are written with their SW Reset default values. | |
| 1025 | */ | |
| 1026 | #define get_power_mode 0x0a | |
| 1027 | /* | |
| 1028 | * The display module returns the current power mode | |
| 1029 | */ | |
| 1030 | #define get_address_mode 0x0b | |
| 1031 | /* | |
| 1032 | * The display module returns the current status. | |
| 1033 | */ | |
| 1034 | #define get_pixel_format 0x0c | |
| 1035 | /* | |
| 1036 | * This command gets the pixel format for the RGB image data | |
| 1037 | * used by the interface. | |
| 1038 | */ | |
| 1039 | #define get_display_mode 0x0d | |
| 1040 | /* | |
| 1041 | * The display module returns the Display Image Mode status. | |
| 1042 | */ | |
| 1043 | #define get_signal_mode 0x0e | |
| 1044 | /* | |
| 1045 | * The display module returns the Display Signal Mode. | |
| 1046 | */ | |
| 1047 | #define get_diagnostic_result 0x0f | |
| 1048 | /* | |
| 1049 | * The display module returns the self-diagnostic results following | |
| 1050 | * a Sleep Out command. | |
| 1051 | */ | |
| 1052 | #define enter_sleep_mode 0x10 | |
| 1053 | /* | |
| 1054 | * This command causes the display module to enter the Sleep mode. | |
| 1055 | * In this mode, all unnecessary blocks inside the display module are | |
| 1056 | * disabled except interface communication. This is the lowest power | |
| 1057 | * mode the display module supports. | |
| 1058 | */ | |
| 1059 | #define exit_sleep_mode 0x11 | |
| 1060 | /* | |
| 1061 | * This command causes the display module to exit Sleep mode. | |
| 1062 | * All blocks inside the display module are enabled. | |
| 1063 | */ | |
| 1064 | #define enter_partial_mode 0x12 | |
| 1065 | /* | |
| 1066 | * This command causes the display module to enter the Partial Display | |
| 1067 | * Mode. The Partial Display Mode window is described by the | |
| 1068 | * set_partial_area command. | |
| 1069 | */ | |
| 1070 | #define enter_normal_mode 0x13 | |
| 1071 | /* | |
| 1072 | * This command causes the display module to enter the Normal mode. | |
| 1073 | * Normal Mode is defined as Partial Display mode and Scroll mode are off | |
| 1074 | */ | |
| 1075 | #define exit_invert_mode 0x20 | |
| 1076 | /* | |
| 1077 | * This command causes the display module to stop inverting the image | |
| 1078 | * data on the display device. The frame memory contents remain unchanged. | |
| 1079 | * No status bits are changed. | |
| 1080 | */ | |
| 1081 | #define enter_invert_mode 0x21 | |
| 1082 | /* | |
| 1083 | * This command causes the display module to invert the image data only on | |
| 1084 | * the display device. The frame memory contents remain unchanged. | |
| 1085 | * No status bits are changed. | |
| 1086 | */ | |
| 1087 | #define set_gamma_curve 0x26 | |
| 1088 | /* | |
| 1089 | * This command selects the desired gamma curve for the display device. | |
| 1090 | * Four fixed gamma curves are defined in section DCS spec. | |
| 1091 | */ | |
| 1092 | #define set_display_off 0x28 | |
| 1093 | /* ************************************************************************* *\ | |
| 1094 | This command causes the display module to stop displaying the image data | |
| 1095 | on the display device. The frame memory contents remain unchanged. | |
| 1096 | No status bits are changed. | |
| 1097 | \* ************************************************************************* */ | |
| 1098 | #define set_display_on 0x29 | |
| 1099 | /* ************************************************************************* *\ | |
| 1100 | This command causes the display module to start displaying the image data | |
| 1101 | on the display device. The frame memory contents remain unchanged. | |
| 1102 | No status bits are changed. | |
| 1103 | \* ************************************************************************* */ | |
| 1104 | #define set_column_address 0x2a | |
| 1105 | /* | |
| 1106 | * This command defines the column extent of the frame memory accessed by | |
| 1107 | * the hostprocessor with the read_memory_continue and | |
| 1108 | * write_memory_continue commands. | |
| 1109 | * No status bits are changed. | |
| 1110 | */ | |
| 1111 | #define set_page_addr 0x2b | |
| 1112 | /* | |
| 1113 | * This command defines the page extent of the frame memory accessed by | |
| 1114 | * the host processor with the write_memory_continue and | |
| 1115 | * read_memory_continue command. | |
| 1116 | * No status bits are changed. | |
| 1117 | */ | |
| 1118 | #define write_mem_start 0x2c | |
| 1119 | /* | |
| 1120 | * This command transfers image data from the host processor to the | |
| 1121 | * display modules frame memory starting at the pixel location specified | |
| 1122 | * by preceding set_column_address and set_page_address commands. | |
| 1123 | */ | |
| 1124 | #define set_partial_area 0x30 | |
| 1125 | /* | |
| 1126 | * This command defines the Partial Display mode s display area. | |
| 1127 | * There are two parameters associated with this command, the first | |
| 1128 | * defines the Start Row (SR) and the second the End Row (ER). SR and ER | |
| 1129 | * refer to the Frame Memory Line Pointer. | |
| 1130 | */ | |
| 1131 | #define set_scroll_area 0x33 | |
| 1132 | /* | |
| 1133 | * This command defines the display modules Vertical Scrolling Area. | |
| 1134 | */ | |
| 1135 | #define set_tear_off 0x34 | |
| 1136 | /* | |
| 1137 | * This command turns off the display modules Tearing Effect output | |
| 1138 | * signal on the TE signal line. | |
| 1139 | */ | |
| 1140 | #define set_tear_on 0x35 | |
| 1141 | /* | |
| 1142 | * This command turns on the display modules Tearing Effect output signal | |
| 1143 | * on the TE signal line. | |
| 1144 | */ | |
| 1145 | #define set_address_mode 0x36 | |
| 1146 | /* | |
| 1147 | * This command sets the data order for transfers from the host processor | |
| 1148 | * to display modules frame memory,bits B[7:5] and B3, and from the | |
| 1149 | * display modules frame memory to the display device, bits B[2:0] and B4. | |
| 1150 | */ | |
| 1151 | #define set_scroll_start 0x37 | |
| 1152 | /* | |
| 1153 | * This command sets the start of the vertical scrolling area in the frame | |
| 1154 | * memory. The vertical scrolling area is fully defined when this command | |
| 1155 | * is used with the set_scroll_area command The set_scroll_start command | |
| 1156 | * has one parameter, the Vertical Scroll Pointer. The VSP defines the | |
| 1157 | * line in the frame memory that is written to the display device as the | |
| 1158 | * first line of the vertical scroll area. | |
| 1159 | */ | |
| 1160 | #define exit_idle_mode 0x38 | |
| 1161 | /* | |
| 1162 | * This command causes the display module to exit Idle mode. | |
| 1163 | */ | |
| 1164 | #define enter_idle_mode 0x39 | |
| 1165 | /* | |
| 1166 | * This command causes the display module to enter Idle Mode. | |
| 1167 | * In Idle Mode, color expression is reduced. Colors are shown on the | |
| 1168 | * display device using the MSB of each of the R, G and B color | |
| 1169 | * components in the frame memory | |
| 1170 | */ | |
| 1171 | #define set_pixel_format 0x3a | |
| 1172 | /* | |
| 1173 | * This command sets the pixel format for the RGB image data used by the | |
| 1174 | * interface. | |
| 1175 | * Bits D[6:4] DPI Pixel Format Definition | |
| 1176 | * Bits D[2:0] DBI Pixel Format Definition | |
| 1177 | * Bits D7 and D3 are not used. | |
| 1178 | */ | |
| 1179 | #define DCS_PIXEL_FORMAT_3bpp 0x1 | |
| 1180 | #define DCS_PIXEL_FORMAT_8bpp 0x2 | |
| 1181 | #define DCS_PIXEL_FORMAT_12bpp 0x3 | |
| 1182 | #define DCS_PIXEL_FORMAT_16bpp 0x5 | |
| 1183 | #define DCS_PIXEL_FORMAT_18bpp 0x6 | |
| 1184 | #define DCS_PIXEL_FORMAT_24bpp 0x7 | |
| 1185 | ||
| 1186 | #define write_mem_cont 0x3c | |
| 1187 | ||
| 1188 | /* | |
| 1189 | * This command transfers image data from the host processor to the | |
| 1190 | * display module's frame memory continuing from the pixel location | |
| 1191 | * following the previous write_memory_continue or write_memory_start | |
| 1192 | * command. | |
| 1193 | */ | |
| 1194 | #define set_tear_scanline 0x44 | |
| 1195 | /* | |
| 1196 | * This command turns on the display modules Tearing Effect output signal | |
| 1197 | * on the TE signal line when the display module reaches line N. | |
| 1198 | */ | |
| 1199 | #define get_scanline 0x45 | |
| 1200 | /* | |
| 1201 | * The display module returns the current scanline, N, used to update the | |
| 1202 | * display device. The total number of scanlines on a display device is | |
| 1203 | * defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as | |
| 1204 | * the first line of V Sync and is denoted as Line 0. | |
| 1205 | * When in Sleep Mode, the value returned by get_scanline is undefined. | |
| 1206 | */ | |
| 1207 | ||
| 1208 | /* MCS or Generic COMMANDS */ | |
| 1209 | /* MCS/generic data type */ | |
| 1210 | #define GEN_SHORT_WRITE_0 0x03 /* generic short write, no parameters */ | |
| 1211 | #define GEN_SHORT_WRITE_1 0x13 /* generic short write, 1 parameters */ | |
| 1212 | #define GEN_SHORT_WRITE_2 0x23 /* generic short write, 2 parameters */ | |
| 1213 | #define GEN_READ_0 0x04 /* generic read, no parameters */ | |
| 1214 | #define GEN_READ_1 0x14 /* generic read, 1 parameters */ | |
| 1215 | #define GEN_READ_2 0x24 /* generic read, 2 parameters */ | |
| 1216 | #define GEN_LONG_WRITE 0x29 /* generic long write */ | |
| 1217 | #define MCS_SHORT_WRITE_0 0x05 /* MCS short write, no parameters */ | |
| 1218 | #define MCS_SHORT_WRITE_1 0x15 /* MCS short write, 1 parameters */ | |
| 1219 | #define MCS_READ 0x06 /* MCS read, no parameters */ | |
| 1220 | #define MCS_LONG_WRITE 0x39 /* MCS long write */ | |
| 1221 | /* MCS/generic commands */ | |
| 1222 | /* TPO MCS */ | |
| 1223 | #define write_display_profile 0x50 | |
| 1224 | #define write_display_brightness 0x51 | |
| 1225 | #define write_ctrl_display 0x53 | |
| 1226 | #define write_ctrl_cabc 0x55 | |
| 1227 | #define UI_IMAGE 0x01 | |
| 1228 | #define STILL_IMAGE 0x02 | |
| 1229 | #define MOVING_IMAGE 0x03 | |
| 1230 | #define write_hysteresis 0x57 | |
| 1231 | #define write_gamma_setting 0x58 | |
| 1232 | #define write_cabc_min_bright 0x5e | |
| 1233 | #define write_kbbc_profile 0x60 | |
| 1234 | /* TMD MCS */ | |
| 1235 | #define tmd_write_display_brightness 0x8c | |
| 1236 | ||
| 1237 | /* | |
| 1238 | * This command is used to control ambient light, panel backlight | |
| 1239 | * brightness and gamma settings. | |
| 1240 | */ | |
| 1241 | #define BRIGHT_CNTL_BLOCK_ON (1 << 5) | |
| 1242 | #define AMBIENT_LIGHT_SENSE_ON (1 << 4) | |
| 1243 | #define DISPLAY_DIMMING_ON (1 << 3) | |
| 1244 | #define BACKLIGHT_ON (1 << 2) | |
| 1245 | #define DISPLAY_BRIGHTNESS_AUTO (1 << 1) | |
| 1246 | #define GAMMA_AUTO (1 << 0) | |
| 1247 | ||
| 1248 | /* DCS Interface Pixel Formats */ | |
| 1249 | #define DCS_PIXEL_FORMAT_3BPP 0x1 | |
| 1250 | #define DCS_PIXEL_FORMAT_8BPP 0x2 | |
| 1251 | #define DCS_PIXEL_FORMAT_12BPP 0x3 | |
| 1252 | #define DCS_PIXEL_FORMAT_16BPP 0x5 | |
| 1253 | #define DCS_PIXEL_FORMAT_18BPP 0x6 | |
| 1254 | #define DCS_PIXEL_FORMAT_24BPP 0x7 | |
| 1255 | /* ONE PARAMETER READ DATA */ | |
| 1256 | #define addr_mode_data 0xfc | |
| 1257 | #define diag_res_data 0x00 | |
| 1258 | #define disp_mode_data 0x23 | |
| 1259 | #define pxl_fmt_data 0x77 | |
| 1260 | #define pwr_mode_data 0x74 | |
| 1261 | #define sig_mode_data 0x00 | |
| 1262 | /* TWO PARAMETERS READ DATA */ | |
| 1263 | #define scanline_data1 0xff | |
| 1264 | #define scanline_data2 0xff | |
| 1265 | #define NON_BURST_MODE_SYNC_PULSE 0x01 /* Non Burst Mode | |
| 1266 | * with Sync Pulse | |
| 1267 | */ | |
| 1268 | #define NON_BURST_MODE_SYNC_EVENTS 0x02 /* Non Burst Mode | |
| 1269 | * with Sync events | |
| 1270 | */ | |
| 1271 | #define BURST_MODE 0x03 /* Burst Mode */ | |
| 1272 | #define DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 */ /* 0x120 */ | |
| 1273 | /* Allocate at least | |
| 1274 | * 0x100 Byte with 32 | |
| 1275 | * byte alignment | |
| 1276 | */ | |
| 1277 | #define DBI_DATA_BUFFER_SIZE 0x120 /* Allocate at least | |
| 1278 | * 0x100 Byte with 32 | |
| 1279 | * byte alignment | |
| 1280 | */ | |
| 1281 | #define DBI_CB_TIME_OUT 0xFFFF | |
| 1282 | ||
| 1283 | #define GEN_FB_TIME_OUT 2000 | |
| 1284 | ||
| 1285 | #define SKU_83 0x01 | |
| 1286 | #define SKU_100 0x02 | |
| 1287 | #define SKU_100L 0x04 | |
| 1288 | #define SKU_BYPASS 0x08 | |
| 1289 | ||
| 1290 | /* Some handy macros for playing with bitfields. */ | |
| 1291 | #define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low)) | |
| 1292 | #define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK) | |
| 1293 | #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) | |
| 1294 | ||
| 1295 | #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) | |
| 1296 | ||
| 1297 | /* PCI config space */ | |
| 1298 | ||
| 1299 | #define SB_PCKT 0x02100 /* cedarview */ | |
| 1300 | # define SB_OPCODE_MASK PSB_MASK(31, 16) | |
| 1301 | # define SB_OPCODE_SHIFT 16 | |
| 1302 | # define SB_OPCODE_READ 0 | |
| 1303 | # define SB_OPCODE_WRITE 1 | |
| 1304 | # define SB_DEST_MASK PSB_MASK(15, 8) | |
| 1305 | # define SB_DEST_SHIFT 8 | |
| 1306 | # define SB_DEST_DPLL 0x88 | |
| 1307 | # define SB_BYTE_ENABLE_MASK PSB_MASK(7, 4) | |
| 1308 | # define SB_BYTE_ENABLE_SHIFT 4 | |
| 1309 | # define SB_BUSY (1 << 0) | |
| 1310 | ||
| 09016a11 AC |
1311 | #define DSPCLK_GATE_D 0x6200 |
| 1312 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */ | |
| 1313 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) | |
| 1314 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) | |
| 9a9f5786 ZY |
1315 | # define DPUNIT_PIPEB_GATE_DISABLE (1 << 30) |
| 1316 | # define DPUNIT_PIPEA_GATE_DISABLE (1 << 25) | |
| 1317 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) | |
| 1318 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) | |
| 09016a11 AC |
1319 | |
| 1320 | #define RAMCLK_GATE_D 0x6210 | |
| 89c78134 AC |
1321 | |
| 1322 | /* 32-bit value read/written from the DPIO reg. */ | |
| 1323 | #define SB_DATA 0x02104 /* cedarview */ | |
| 1324 | /* 32-bit address of the DPIO reg to be read/written. */ | |
| 1325 | #define SB_ADDR 0x02108 /* cedarview */ | |
| 1326 | #define DPIO_CFG 0x02110 /* cedarview */ | |
| 1327 | # define DPIO_MODE_SELECT_1 (1 << 3) | |
| 1328 | # define DPIO_MODE_SELECT_0 (1 << 2) | |
| 1329 | # define DPIO_SFR_BYPASS (1 << 1) | |
| 1330 | /* reset is active low */ | |
| 1331 | # define DPIO_CMN_RESET_N (1 << 0) | |
| 1332 | ||
| 1333 | /* Cedarview sideband registers */ | |
| 1334 | #define _SB_M_A 0x8008 | |
| 1335 | #define _SB_M_B 0x8028 | |
| 1336 | #define SB_M(pipe) _PIPE(pipe, _SB_M_A, _SB_M_B) | |
| 1337 | # define SB_M_DIVIDER_MASK (0xFF << 24) | |
| 1338 | # define SB_M_DIVIDER_SHIFT 24 | |
| 1339 | ||
| 1340 | #define _SB_N_VCO_A 0x8014 | |
| 1341 | #define _SB_N_VCO_B 0x8034 | |
| 1342 | #define SB_N_VCO(pipe) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B) | |
| 1343 | #define SB_N_VCO_SEL_MASK PSB_MASK(31, 30) | |
| 1344 | #define SB_N_VCO_SEL_SHIFT 30 | |
| 1345 | #define SB_N_DIVIDER_MASK PSB_MASK(29, 26) | |
| 1346 | #define SB_N_DIVIDER_SHIFT 26 | |
| 1347 | #define SB_N_CB_TUNE_MASK PSB_MASK(25, 24) | |
| 1348 | #define SB_N_CB_TUNE_SHIFT 24 | |
| 1349 | ||
| acd7ef92 AC |
1350 | /* the bit 14:13 is used to select between the different reference clock for Pipe A/B */ |
| 1351 | #define SB_REF_DPLLA 0x8010 | |
| 1352 | #define SB_REF_DPLLB 0x8030 | |
| 1353 | #define REF_CLK_MASK (0x3 << 13) | |
| 1354 | #define REF_CLK_CORE (0 << 13) | |
| 1355 | #define REF_CLK_DPLL (1 << 13) | |
| 1356 | #define REF_CLK_DPLLA (2 << 13) | |
| 1357 | /* For the DPLL B, it will use the reference clk from DPLL A when using (2 << 13) */ | |
| 1358 | ||
| 89c78134 AC |
1359 | #define _SB_REF_A 0x8018 |
| 1360 | #define _SB_REF_B 0x8038 | |
| 1361 | #define SB_REF_SFR(pipe) _PIPE(pipe, _SB_REF_A, _SB_REF_B) | |
| 1362 | ||
| 1363 | #define _SB_P_A 0x801c | |
| 1364 | #define _SB_P_B 0x803c | |
| 1365 | #define SB_P(pipe) _PIPE(pipe, _SB_P_A, _SB_P_B) | |
| 1366 | #define SB_P2_DIVIDER_MASK PSB_MASK(31, 30) | |
| 1367 | #define SB_P2_DIVIDER_SHIFT 30 | |
| 1368 | #define SB_P2_10 0 /* HDMI, DP, DAC */ | |
| 1369 | #define SB_P2_5 1 /* DAC */ | |
| 1370 | #define SB_P2_14 2 /* LVDS single */ | |
| 1371 | #define SB_P2_7 3 /* LVDS double */ | |
| 1372 | #define SB_P1_DIVIDER_MASK PSB_MASK(15, 12) | |
| 1373 | #define SB_P1_DIVIDER_SHIFT 12 | |
| 1374 | ||
| 1375 | #define PSB_LANE0 0x120 | |
| 1376 | #define PSB_LANE1 0x220 | |
| 1377 | #define PSB_LANE2 0x2320 | |
| 1378 | #define PSB_LANE3 0x2420 | |
| 1379 | ||
| 1380 | #define LANE_PLL_MASK (0x7 << 20) | |
| 1381 | #define LANE_PLL_ENABLE (0x3 << 20) | |
| d235e64a | 1382 | #define LANE_PLL_PIPE(p) (((p) == 0) ? (1 << 21) : (0 << 21)) |
| 89c78134 | 1383 | |
| 8695b612 AC |
1384 | #define DP_B 0x64100 |
| 1385 | #define DP_C 0x64200 | |
| 1386 | ||
| 1387 | #define DP_PORT_EN (1 << 31) | |
| 1388 | #define DP_PIPEB_SELECT (1 << 30) | |
| 1389 | #define DP_PIPE_MASK (1 << 30) | |
| 1390 | ||
| 1391 | /* Link training mode - select a suitable mode for each stage */ | |
| 1392 | #define DP_LINK_TRAIN_PAT_1 (0 << 28) | |
| 1393 | #define DP_LINK_TRAIN_PAT_2 (1 << 28) | |
| 1394 | #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) | |
| 1395 | #define DP_LINK_TRAIN_OFF (3 << 28) | |
| 1396 | #define DP_LINK_TRAIN_MASK (3 << 28) | |
| 1397 | #define DP_LINK_TRAIN_SHIFT 28 | |
| 1398 | ||
| 1399 | /* Signal voltages. These are mostly controlled by the other end */ | |
| 1400 | #define DP_VOLTAGE_0_4 (0 << 25) | |
| 1401 | #define DP_VOLTAGE_0_6 (1 << 25) | |
| 1402 | #define DP_VOLTAGE_0_8 (2 << 25) | |
| 1403 | #define DP_VOLTAGE_1_2 (3 << 25) | |
| 1404 | #define DP_VOLTAGE_MASK (7 << 25) | |
| 1405 | #define DP_VOLTAGE_SHIFT 25 | |
| 1406 | ||
| 1407 | /* Signal pre-emphasis levels, like voltages, the other end tells us what | |
| 1408 | * they want | |
| 1409 | */ | |
| 1410 | #define DP_PRE_EMPHASIS_0 (0 << 22) | |
| 1411 | #define DP_PRE_EMPHASIS_3_5 (1 << 22) | |
| 1412 | #define DP_PRE_EMPHASIS_6 (2 << 22) | |
| 1413 | #define DP_PRE_EMPHASIS_9_5 (3 << 22) | |
| 1414 | #define DP_PRE_EMPHASIS_MASK (7 << 22) | |
| 1415 | #define DP_PRE_EMPHASIS_SHIFT 22 | |
| 1416 | ||
| 1417 | /* How many wires to use. I guess 3 was too hard */ | |
| 1418 | #define DP_PORT_WIDTH_1 (0 << 19) | |
| 1419 | #define DP_PORT_WIDTH_2 (1 << 19) | |
| 1420 | #define DP_PORT_WIDTH_4 (3 << 19) | |
| 1421 | #define DP_PORT_WIDTH_MASK (7 << 19) | |
| 1422 | ||
| 1423 | /* Mystic DPCD version 1.1 special mode */ | |
| 1424 | #define DP_ENHANCED_FRAMING (1 << 18) | |
| 1425 | ||
| 1426 | /** locked once port is enabled */ | |
| 1427 | #define DP_PORT_REVERSAL (1 << 15) | |
| 1428 | ||
| 1429 | /** sends the clock on lane 15 of the PEG for debug */ | |
| 1430 | #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) | |
| 1431 | ||
| 1432 | #define DP_SCRAMBLING_DISABLE (1 << 12) | |
| 1433 | #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) | |
| 1434 | ||
| 1435 | /** limit RGB values to avoid confusing TVs */ | |
| 1436 | #define DP_COLOR_RANGE_16_235 (1 << 8) | |
| 1437 | ||
| 1438 | /** Turn on the audio link */ | |
| 1439 | #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) | |
| 1440 | ||
| 1441 | /** vs and hs sync polarity */ | |
| 1442 | #define DP_SYNC_VS_HIGH (1 << 4) | |
| 1443 | #define DP_SYNC_HS_HIGH (1 << 3) | |
| 1444 | ||
| 1445 | /** A fantasy */ | |
| 1446 | #define DP_DETECTED (1 << 2) | |
| 1447 | ||
| 1448 | /** The aux channel provides a way to talk to the | |
| 1449 | * signal sink for DDC etc. Max packet size supported | |
| 1450 | * is 20 bytes in each direction, hence the 5 fixed | |
| 1451 | * data registers | |
| 1452 | */ | |
| 1453 | #define DPB_AUX_CH_CTL 0x64110 | |
| 1454 | #define DPB_AUX_CH_DATA1 0x64114 | |
| 1455 | #define DPB_AUX_CH_DATA2 0x64118 | |
| 1456 | #define DPB_AUX_CH_DATA3 0x6411c | |
| 1457 | #define DPB_AUX_CH_DATA4 0x64120 | |
| 1458 | #define DPB_AUX_CH_DATA5 0x64124 | |
| 1459 | ||
| 1460 | #define DPC_AUX_CH_CTL 0x64210 | |
| 1461 | #define DPC_AUX_CH_DATA1 0x64214 | |
| 1462 | #define DPC_AUX_CH_DATA2 0x64218 | |
| 1463 | #define DPC_AUX_CH_DATA3 0x6421c | |
| 1464 | #define DPC_AUX_CH_DATA4 0x64220 | |
| 1465 | #define DPC_AUX_CH_DATA5 0x64224 | |
| 1466 | ||
| 1467 | #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) | |
| 1468 | #define DP_AUX_CH_CTL_DONE (1 << 30) | |
| 1469 | #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) | |
| 1470 | #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) | |
| 1471 | #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) | |
| 1472 | #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) | |
| 1473 | #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) | |
| 1474 | #define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) | |
| 1475 | #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) | |
| 1476 | #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) | |
| 1477 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) | |
| 1478 | #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 | |
| 1479 | #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) | |
| 1480 | #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 | |
| 1481 | #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) | |
| 1482 | #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) | |
| 1483 | #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) | |
| 1484 | #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) | |
| 1485 | #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) | |
| 1486 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) | |
| 1487 | #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 | |
| 1488 | ||
| 1489 | /* | |
| 1490 | * Computing GMCH M and N values for the Display Port link | |
| 1491 | * | |
| 1492 | * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes | |
| 1493 | * | |
| 1494 | * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) | |
| 1495 | * | |
| 1496 | * The GMCH value is used internally | |
| 1497 | * | |
| 1498 | * bytes_per_pixel is the number of bytes coming out of the plane, | |
| 1499 | * which is after the LUTs, so we want the bytes for our color format. | |
| 1500 | * For our current usage, this is always 3, one byte for R, G and B. | |
| 1501 | */ | |
| 1502 | ||
| 1503 | #define _PIPEA_GMCH_DATA_M 0x70050 | |
| 1504 | #define _PIPEB_GMCH_DATA_M 0x71050 | |
| 1505 | ||
| 1506 | /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ | |
| 1507 | #define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) | |
| 1508 | #define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 | |
| 1509 | ||
| 1510 | #define PIPE_GMCH_DATA_M_MASK (0xffffff) | |
| 1511 | ||
| 1512 | #define _PIPEA_GMCH_DATA_N 0x70054 | |
| 1513 | #define _PIPEB_GMCH_DATA_N 0x71054 | |
| 1514 | #define PIPE_GMCH_DATA_N_MASK (0xffffff) | |
| 1515 | ||
| 1516 | /* | |
| 1517 | * Computing Link M and N values for the Display Port link | |
| 1518 | * | |
| 1519 | * Link M / N = pixel_clock / ls_clk | |
| 1520 | * | |
| 1521 | * (the DP spec calls pixel_clock the 'strm_clk') | |
| 1522 | * | |
| 1523 | * The Link value is transmitted in the Main Stream | |
| 1524 | * Attributes and VB-ID. | |
| 1525 | */ | |
| 1526 | ||
| 1527 | #define _PIPEA_DP_LINK_M 0x70060 | |
| 1528 | #define _PIPEB_DP_LINK_M 0x71060 | |
| 1529 | #define PIPEA_DP_LINK_M_MASK (0xffffff) | |
| 1530 | ||
| 1531 | #define _PIPEA_DP_LINK_N 0x70064 | |
| 1532 | #define _PIPEB_DP_LINK_N 0x71064 | |
| 1533 | #define PIPEA_DP_LINK_N_MASK (0xffffff) | |
| 1534 | ||
| 1535 | #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) | |
| 1536 | #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) | |
| 1537 | #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M) | |
| 1538 | #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N) | |
| 89c78134 | 1539 | |
| d112a816 ZY |
1540 | #define PIPE_BPC_MASK (7 << 5) |
| 1541 | #define PIPE_8BPC (0 << 5) | |
| 1542 | #define PIPE_10BPC (1 << 5) | |
| 1543 | #define PIPE_6BPC (2 << 5) | |
| 1544 | ||
| 89c78134 | 1545 | #endif |