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e7792ce2 RC |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
c707c361 | 18 | #include <linux/component.h> |
893c3e53 | 19 | #include <linux/hdmi.h> |
e7792ce2 | 20 | #include <linux/module.h> |
12473b7d | 21 | #include <linux/irq.h> |
f0b33b28 | 22 | #include <sound/asoundef.h> |
e7792ce2 RC |
23 | |
24 | #include <drm/drmP.h> | |
25 | #include <drm/drm_crtc_helper.h> | |
26 | #include <drm/drm_encoder_slave.h> | |
27 | #include <drm/drm_edid.h> | |
c4c11dd1 | 28 | #include <drm/i2c/tda998x.h> |
e7792ce2 RC |
29 | |
30 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) | |
31 | ||
32 | struct tda998x_priv { | |
33 | struct i2c_client *cec; | |
2f7f730a | 34 | struct i2c_client *hdmi; |
e7792ce2 RC |
35 | uint16_t rev; |
36 | uint8_t current_page; | |
37 | int dpms; | |
c4c11dd1 | 38 | bool is_hdmi_sink; |
5e74c22c RK |
39 | u8 vip_cntrl_0; |
40 | u8 vip_cntrl_1; | |
41 | u8 vip_cntrl_2; | |
c4c11dd1 | 42 | struct tda998x_encoder_params params; |
12473b7d JFM |
43 | |
44 | wait_queue_head_t wq_edid; | |
45 | volatile int wq_edid_wait; | |
46 | struct drm_encoder *encoder; | |
e7792ce2 RC |
47 | }; |
48 | ||
49 | #define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) | |
50 | ||
51 | /* The TDA9988 series of devices use a paged register scheme.. to simplify | |
52 | * things we encode the page # in upper bits of the register #. To read/ | |
53 | * write a given register, we need to make sure CURPAGE register is set | |
54 | * appropriately. Which implies reads/writes are not atomic. Fun! | |
55 | */ | |
56 | ||
57 | #define REG(page, addr) (((page) << 8) | (addr)) | |
58 | #define REG2ADDR(reg) ((reg) & 0xff) | |
59 | #define REG2PAGE(reg) (((reg) >> 8) & 0xff) | |
60 | ||
61 | #define REG_CURPAGE 0xff /* write */ | |
62 | ||
63 | ||
64 | /* Page 00h: General Control */ | |
65 | #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ | |
66 | #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ | |
67 | # define MAIN_CNTRL0_SR (1 << 0) | |
68 | # define MAIN_CNTRL0_DECS (1 << 1) | |
69 | # define MAIN_CNTRL0_DEHS (1 << 2) | |
70 | # define MAIN_CNTRL0_CECS (1 << 3) | |
71 | # define MAIN_CNTRL0_CEHS (1 << 4) | |
72 | # define MAIN_CNTRL0_SCALER (1 << 7) | |
73 | #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ | |
74 | #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ | |
75 | # define SOFTRESET_AUDIO (1 << 0) | |
76 | # define SOFTRESET_I2C_MASTER (1 << 1) | |
77 | #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ | |
78 | #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ | |
79 | #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ | |
80 | # define I2C_MASTER_DIS_MM (1 << 0) | |
81 | # define I2C_MASTER_DIS_FILT (1 << 1) | |
82 | # define I2C_MASTER_APP_STRT_LAT (1 << 2) | |
c4c11dd1 RK |
83 | #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ |
84 | # define FEAT_POWERDOWN_SPDIF (1 << 3) | |
e7792ce2 RC |
85 | #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ |
86 | #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ | |
87 | #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ | |
88 | # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) | |
c4c11dd1 | 89 | #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ |
e7792ce2 RC |
90 | #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ |
91 | #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ | |
92 | #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ | |
93 | #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ | |
94 | #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ | |
95 | # define VIP_CNTRL_0_MIRR_A (1 << 7) | |
96 | # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) | |
97 | # define VIP_CNTRL_0_MIRR_B (1 << 3) | |
98 | # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) | |
99 | #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ | |
100 | # define VIP_CNTRL_1_MIRR_C (1 << 7) | |
101 | # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) | |
102 | # define VIP_CNTRL_1_MIRR_D (1 << 3) | |
103 | # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) | |
104 | #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ | |
105 | # define VIP_CNTRL_2_MIRR_E (1 << 7) | |
106 | # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) | |
107 | # define VIP_CNTRL_2_MIRR_F (1 << 3) | |
108 | # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) | |
109 | #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ | |
110 | # define VIP_CNTRL_3_X_TGL (1 << 0) | |
111 | # define VIP_CNTRL_3_H_TGL (1 << 1) | |
112 | # define VIP_CNTRL_3_V_TGL (1 << 2) | |
113 | # define VIP_CNTRL_3_EMB (1 << 3) | |
114 | # define VIP_CNTRL_3_SYNC_DE (1 << 4) | |
115 | # define VIP_CNTRL_3_SYNC_HS (1 << 5) | |
116 | # define VIP_CNTRL_3_DE_INT (1 << 6) | |
117 | # define VIP_CNTRL_3_EDGE (1 << 7) | |
118 | #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ | |
119 | # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) | |
120 | # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) | |
121 | # define VIP_CNTRL_4_CCIR656 (1 << 4) | |
122 | # define VIP_CNTRL_4_656_ALT (1 << 5) | |
123 | # define VIP_CNTRL_4_TST_656 (1 << 6) | |
124 | # define VIP_CNTRL_4_TST_PAT (1 << 7) | |
125 | #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ | |
126 | # define VIP_CNTRL_5_CKCASE (1 << 0) | |
127 | # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) | |
c4c11dd1 | 128 | #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ |
10df1a95 JFM |
129 | # define MUX_AP_SELECT_I2S 0x64 |
130 | # define MUX_AP_SELECT_SPDIF 0x40 | |
bcb2481d | 131 | #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ |
e7792ce2 RC |
132 | #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ |
133 | # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) | |
134 | # define MAT_CONTRL_MAT_BP (1 << 2) | |
135 | #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ | |
136 | #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ | |
137 | #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ | |
138 | #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ | |
139 | #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ | |
140 | #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ | |
141 | #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ | |
142 | #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ | |
143 | #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ | |
144 | #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ | |
145 | #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ | |
146 | #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ | |
147 | #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ | |
148 | #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ | |
149 | #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ | |
150 | #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ | |
151 | #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ | |
088d61d1 SH |
152 | #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ |
153 | #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ | |
e7792ce2 RC |
154 | #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ |
155 | #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ | |
088d61d1 SH |
156 | #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ |
157 | #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ | |
e7792ce2 RC |
158 | #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ |
159 | #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ | |
160 | #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ | |
161 | #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ | |
162 | #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ | |
163 | #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ | |
164 | #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ | |
165 | #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ | |
166 | #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ | |
167 | #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ | |
088d61d1 SH |
168 | #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ |
169 | #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ | |
170 | #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ | |
171 | #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ | |
e7792ce2 RC |
172 | #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ |
173 | #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ | |
174 | #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ | |
175 | #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ | |
176 | #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ | |
088d61d1 SH |
177 | # define TBG_CNTRL_0_TOP_TGL (1 << 0) |
178 | # define TBG_CNTRL_0_TOP_SEL (1 << 1) | |
179 | # define TBG_CNTRL_0_DE_EXT (1 << 2) | |
180 | # define TBG_CNTRL_0_TOP_EXT (1 << 3) | |
e7792ce2 RC |
181 | # define TBG_CNTRL_0_FRAME_DIS (1 << 5) |
182 | # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) | |
183 | # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) | |
184 | #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ | |
088d61d1 SH |
185 | # define TBG_CNTRL_1_H_TGL (1 << 0) |
186 | # define TBG_CNTRL_1_V_TGL (1 << 1) | |
187 | # define TBG_CNTRL_1_TGL_EN (1 << 2) | |
188 | # define TBG_CNTRL_1_X_EXT (1 << 3) | |
189 | # define TBG_CNTRL_1_H_EXT (1 << 4) | |
190 | # define TBG_CNTRL_1_V_EXT (1 << 5) | |
e7792ce2 RC |
191 | # define TBG_CNTRL_1_DWIN_DIS (1 << 6) |
192 | #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ | |
193 | #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ | |
194 | # define HVF_CNTRL_0_SM (1 << 7) | |
195 | # define HVF_CNTRL_0_RWB (1 << 6) | |
196 | # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) | |
197 | # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) | |
198 | #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ | |
199 | # define HVF_CNTRL_1_FOR (1 << 0) | |
200 | # define HVF_CNTRL_1_YUVBLK (1 << 1) | |
201 | # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) | |
202 | # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) | |
203 | # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) | |
204 | #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ | |
c4c11dd1 RK |
205 | #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ |
206 | # define I2S_FORMAT(x) (((x) & 3) << 0) | |
207 | #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ | |
10df1a95 JFM |
208 | # define AIP_CLKSEL_AIP_SPDIF (0 << 3) |
209 | # define AIP_CLKSEL_AIP_I2S (1 << 3) | |
210 | # define AIP_CLKSEL_FS_ACLK (0 << 0) | |
211 | # define AIP_CLKSEL_FS_MCLK (1 << 0) | |
212 | # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0) | |
e7792ce2 RC |
213 | |
214 | /* Page 02h: PLL settings */ | |
215 | #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ | |
216 | # define PLL_SERIAL_1_SRL_FDN (1 << 0) | |
217 | # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) | |
218 | # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) | |
219 | #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ | |
3ae471f7 | 220 | # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) |
e7792ce2 RC |
221 | # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) |
222 | #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ | |
223 | # define PLL_SERIAL_3_SRL_CCIR (1 << 0) | |
224 | # define PLL_SERIAL_3_SRL_DE (1 << 2) | |
225 | # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) | |
226 | #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ | |
227 | #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ | |
228 | #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ | |
229 | #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ | |
230 | #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ | |
231 | #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ | |
232 | #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ | |
233 | #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ | |
234 | #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ | |
c4c11dd1 RK |
235 | # define AUDIO_DIV_SERCLK_1 0 |
236 | # define AUDIO_DIV_SERCLK_2 1 | |
237 | # define AUDIO_DIV_SERCLK_4 2 | |
238 | # define AUDIO_DIV_SERCLK_8 3 | |
239 | # define AUDIO_DIV_SERCLK_16 4 | |
240 | # define AUDIO_DIV_SERCLK_32 5 | |
e7792ce2 RC |
241 | #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ |
242 | # define SEL_CLK_SEL_CLK1 (1 << 0) | |
243 | # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) | |
244 | # define SEL_CLK_ENA_SC_CLK (1 << 3) | |
245 | #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ | |
246 | ||
247 | ||
248 | /* Page 09h: EDID Control */ | |
249 | #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ | |
250 | /* next 127 successive registers are the EDID block */ | |
251 | #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ | |
252 | #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ | |
253 | #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ | |
254 | #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ | |
255 | #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ | |
256 | ||
257 | ||
258 | /* Page 10h: information frames and packets */ | |
c4c11dd1 RK |
259 | #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ |
260 | #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ | |
261 | #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ | |
262 | #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ | |
263 | #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ | |
e7792ce2 RC |
264 | |
265 | ||
266 | /* Page 11h: audio settings and content info packets */ | |
267 | #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ | |
268 | # define AIP_CNTRL_0_RST_FIFO (1 << 0) | |
269 | # define AIP_CNTRL_0_SWAP (1 << 1) | |
270 | # define AIP_CNTRL_0_LAYOUT (1 << 2) | |
271 | # define AIP_CNTRL_0_ACR_MAN (1 << 5) | |
272 | # define AIP_CNTRL_0_RST_CTS (1 << 6) | |
c4c11dd1 RK |
273 | #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ |
274 | # define CA_I2S_CA_I2S(x) (((x) & 31) << 0) | |
275 | # define CA_I2S_HBR_CHSTAT (1 << 6) | |
276 | #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ | |
277 | #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ | |
278 | #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ | |
279 | #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ | |
280 | #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ | |
281 | #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ | |
282 | #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ | |
283 | #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ | |
284 | # define CTS_N_K(x) (((x) & 7) << 0) | |
285 | # define CTS_N_M(x) (((x) & 3) << 4) | |
e7792ce2 RC |
286 | #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ |
287 | # define ENC_CNTRL_RST_ENC (1 << 0) | |
288 | # define ENC_CNTRL_RST_SEL (1 << 1) | |
289 | # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) | |
c4c11dd1 RK |
290 | #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ |
291 | # define DIP_FLAGS_ACR (1 << 0) | |
292 | # define DIP_FLAGS_GC (1 << 1) | |
293 | #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ | |
294 | # define DIP_IF_FLAGS_IF1 (1 << 1) | |
295 | # define DIP_IF_FLAGS_IF2 (1 << 2) | |
296 | # define DIP_IF_FLAGS_IF3 (1 << 3) | |
297 | # define DIP_IF_FLAGS_IF4 (1 << 4) | |
298 | # define DIP_IF_FLAGS_IF5 (1 << 5) | |
299 | #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ | |
e7792ce2 RC |
300 | |
301 | ||
302 | /* Page 12h: HDCP and OTP */ | |
303 | #define REG_TX3 REG(0x12, 0x9a) /* read/write */ | |
063b472f RK |
304 | #define REG_TX4 REG(0x12, 0x9b) /* read/write */ |
305 | # define TX4_PD_RAM (1 << 1) | |
e7792ce2 RC |
306 | #define REG_TX33 REG(0x12, 0xb8) /* read/write */ |
307 | # define TX33_HDMI (1 << 1) | |
308 | ||
309 | ||
310 | /* Page 13h: Gamut related metadata packets */ | |
311 | ||
312 | ||
313 | ||
314 | /* CEC registers: (not paged) | |
315 | */ | |
12473b7d JFM |
316 | #define REG_CEC_INTSTATUS 0xee /* read */ |
317 | # define CEC_INTSTATUS_CEC (1 << 0) | |
318 | # define CEC_INTSTATUS_HDMI (1 << 1) | |
e7792ce2 RC |
319 | #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ |
320 | # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) | |
321 | # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) | |
322 | # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) | |
323 | # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) | |
12473b7d JFM |
324 | #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */ |
325 | #define REG_CEC_RXSHPDINT 0xfd /* read */ | |
e7792ce2 RC |
326 | #define REG_CEC_RXSHPDLEV 0xfe /* read */ |
327 | # define CEC_RXSHPDLEV_RXSENS (1 << 0) | |
328 | # define CEC_RXSHPDLEV_HPD (1 << 1) | |
329 | ||
330 | #define REG_CEC_ENAMODS 0xff /* read/write */ | |
331 | # define CEC_ENAMODS_DIS_FRO (1 << 6) | |
332 | # define CEC_ENAMODS_DIS_CCLK (1 << 5) | |
333 | # define CEC_ENAMODS_EN_RXSENS (1 << 2) | |
334 | # define CEC_ENAMODS_EN_HDMI (1 << 1) | |
335 | # define CEC_ENAMODS_EN_CEC (1 << 0) | |
336 | ||
337 | ||
338 | /* Device versions: */ | |
339 | #define TDA9989N2 0x0101 | |
340 | #define TDA19989 0x0201 | |
341 | #define TDA19989N2 0x0202 | |
342 | #define TDA19988 0x0301 | |
343 | ||
344 | static void | |
2f7f730a | 345 | cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val) |
e7792ce2 | 346 | { |
2f7f730a | 347 | struct i2c_client *client = priv->cec; |
e7792ce2 RC |
348 | uint8_t buf[] = {addr, val}; |
349 | int ret; | |
350 | ||
704d63f5 | 351 | ret = i2c_master_send(client, buf, sizeof(buf)); |
e7792ce2 RC |
352 | if (ret < 0) |
353 | dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); | |
354 | } | |
355 | ||
356 | static uint8_t | |
2f7f730a | 357 | cec_read(struct tda998x_priv *priv, uint8_t addr) |
e7792ce2 | 358 | { |
2f7f730a | 359 | struct i2c_client *client = priv->cec; |
e7792ce2 RC |
360 | uint8_t val; |
361 | int ret; | |
362 | ||
363 | ret = i2c_master_send(client, &addr, sizeof(addr)); | |
364 | if (ret < 0) | |
365 | goto fail; | |
366 | ||
367 | ret = i2c_master_recv(client, &val, sizeof(val)); | |
368 | if (ret < 0) | |
369 | goto fail; | |
370 | ||
371 | return val; | |
372 | ||
373 | fail: | |
374 | dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); | |
375 | return 0; | |
376 | } | |
377 | ||
7d2eadc9 | 378 | static int |
2f7f730a | 379 | set_page(struct tda998x_priv *priv, uint16_t reg) |
e7792ce2 | 380 | { |
e7792ce2 | 381 | if (REG2PAGE(reg) != priv->current_page) { |
2f7f730a | 382 | struct i2c_client *client = priv->hdmi; |
e7792ce2 RC |
383 | uint8_t buf[] = { |
384 | REG_CURPAGE, REG2PAGE(reg) | |
385 | }; | |
386 | int ret = i2c_master_send(client, buf, sizeof(buf)); | |
7d2eadc9 | 387 | if (ret < 0) { |
704d63f5 JFM |
388 | dev_err(&client->dev, "setpage %04x err %d\n", |
389 | reg, ret); | |
7d2eadc9 JFM |
390 | return ret; |
391 | } | |
e7792ce2 RC |
392 | |
393 | priv->current_page = REG2PAGE(reg); | |
394 | } | |
7d2eadc9 | 395 | return 0; |
e7792ce2 RC |
396 | } |
397 | ||
398 | static int | |
2f7f730a | 399 | reg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt) |
e7792ce2 | 400 | { |
2f7f730a | 401 | struct i2c_client *client = priv->hdmi; |
e7792ce2 RC |
402 | uint8_t addr = REG2ADDR(reg); |
403 | int ret; | |
404 | ||
7d2eadc9 JFM |
405 | ret = set_page(priv, reg); |
406 | if (ret < 0) | |
407 | return ret; | |
e7792ce2 RC |
408 | |
409 | ret = i2c_master_send(client, &addr, sizeof(addr)); | |
410 | if (ret < 0) | |
411 | goto fail; | |
412 | ||
413 | ret = i2c_master_recv(client, buf, cnt); | |
414 | if (ret < 0) | |
415 | goto fail; | |
416 | ||
417 | return ret; | |
418 | ||
419 | fail: | |
420 | dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); | |
421 | return ret; | |
422 | } | |
423 | ||
c4c11dd1 | 424 | static void |
2f7f730a | 425 | reg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt) |
c4c11dd1 | 426 | { |
2f7f730a | 427 | struct i2c_client *client = priv->hdmi; |
c4c11dd1 RK |
428 | uint8_t buf[cnt+1]; |
429 | int ret; | |
430 | ||
431 | buf[0] = REG2ADDR(reg); | |
432 | memcpy(&buf[1], p, cnt); | |
433 | ||
7d2eadc9 JFM |
434 | ret = set_page(priv, reg); |
435 | if (ret < 0) | |
436 | return; | |
c4c11dd1 RK |
437 | |
438 | ret = i2c_master_send(client, buf, cnt + 1); | |
439 | if (ret < 0) | |
440 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); | |
441 | } | |
442 | ||
7d2eadc9 | 443 | static int |
2f7f730a | 444 | reg_read(struct tda998x_priv *priv, uint16_t reg) |
e7792ce2 RC |
445 | { |
446 | uint8_t val = 0; | |
7d2eadc9 JFM |
447 | int ret; |
448 | ||
449 | ret = reg_read_range(priv, reg, &val, sizeof(val)); | |
450 | if (ret < 0) | |
451 | return ret; | |
e7792ce2 RC |
452 | return val; |
453 | } | |
454 | ||
455 | static void | |
2f7f730a | 456 | reg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val) |
e7792ce2 | 457 | { |
2f7f730a | 458 | struct i2c_client *client = priv->hdmi; |
e7792ce2 RC |
459 | uint8_t buf[] = {REG2ADDR(reg), val}; |
460 | int ret; | |
461 | ||
7d2eadc9 JFM |
462 | ret = set_page(priv, reg); |
463 | if (ret < 0) | |
464 | return; | |
e7792ce2 | 465 | |
704d63f5 | 466 | ret = i2c_master_send(client, buf, sizeof(buf)); |
e7792ce2 RC |
467 | if (ret < 0) |
468 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); | |
469 | } | |
470 | ||
471 | static void | |
2f7f730a | 472 | reg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val) |
e7792ce2 | 473 | { |
2f7f730a | 474 | struct i2c_client *client = priv->hdmi; |
e7792ce2 RC |
475 | uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; |
476 | int ret; | |
477 | ||
7d2eadc9 JFM |
478 | ret = set_page(priv, reg); |
479 | if (ret < 0) | |
480 | return; | |
e7792ce2 | 481 | |
704d63f5 | 482 | ret = i2c_master_send(client, buf, sizeof(buf)); |
e7792ce2 RC |
483 | if (ret < 0) |
484 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); | |
485 | } | |
486 | ||
487 | static void | |
2f7f730a | 488 | reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val) |
e7792ce2 | 489 | { |
7d2eadc9 JFM |
490 | int old_val; |
491 | ||
492 | old_val = reg_read(priv, reg); | |
493 | if (old_val >= 0) | |
494 | reg_write(priv, reg, old_val | val); | |
e7792ce2 RC |
495 | } |
496 | ||
497 | static void | |
2f7f730a | 498 | reg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val) |
e7792ce2 | 499 | { |
7d2eadc9 JFM |
500 | int old_val; |
501 | ||
502 | old_val = reg_read(priv, reg); | |
503 | if (old_val >= 0) | |
504 | reg_write(priv, reg, old_val & ~val); | |
e7792ce2 RC |
505 | } |
506 | ||
507 | static void | |
2f7f730a | 508 | tda998x_reset(struct tda998x_priv *priv) |
e7792ce2 RC |
509 | { |
510 | /* reset audio and i2c master: */ | |
81b53a16 | 511 | reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); |
e7792ce2 | 512 | msleep(50); |
81b53a16 | 513 | reg_write(priv, REG_SOFTRESET, 0); |
e7792ce2 RC |
514 | msleep(50); |
515 | ||
516 | /* reset transmitter: */ | |
2f7f730a JFM |
517 | reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); |
518 | reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); | |
e7792ce2 RC |
519 | |
520 | /* PLL registers common configuration */ | |
2f7f730a JFM |
521 | reg_write(priv, REG_PLL_SERIAL_1, 0x00); |
522 | reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); | |
523 | reg_write(priv, REG_PLL_SERIAL_3, 0x00); | |
524 | reg_write(priv, REG_SERIALIZER, 0x00); | |
525 | reg_write(priv, REG_BUFFER_OUT, 0x00); | |
526 | reg_write(priv, REG_PLL_SCG1, 0x00); | |
527 | reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); | |
528 | reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); | |
529 | reg_write(priv, REG_PLL_SCGN1, 0xfa); | |
530 | reg_write(priv, REG_PLL_SCGN2, 0x00); | |
531 | reg_write(priv, REG_PLL_SCGR1, 0x5b); | |
532 | reg_write(priv, REG_PLL_SCGR2, 0x00); | |
533 | reg_write(priv, REG_PLL_SCG2, 0x10); | |
bcb2481d RK |
534 | |
535 | /* Write the default value MUX register */ | |
2f7f730a | 536 | reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); |
e7792ce2 RC |
537 | } |
538 | ||
12473b7d JFM |
539 | /* |
540 | * only 2 interrupts may occur: screen plug/unplug and EDID read | |
541 | */ | |
542 | static irqreturn_t tda998x_irq_thread(int irq, void *data) | |
543 | { | |
544 | struct tda998x_priv *priv = data; | |
545 | u8 sta, cec, lvl, flag0, flag1, flag2; | |
546 | ||
547 | if (!priv) | |
548 | return IRQ_HANDLED; | |
549 | sta = cec_read(priv, REG_CEC_INTSTATUS); | |
550 | cec = cec_read(priv, REG_CEC_RXSHPDINT); | |
551 | lvl = cec_read(priv, REG_CEC_RXSHPDLEV); | |
552 | flag0 = reg_read(priv, REG_INT_FLAGS_0); | |
553 | flag1 = reg_read(priv, REG_INT_FLAGS_1); | |
554 | flag2 = reg_read(priv, REG_INT_FLAGS_2); | |
555 | DRM_DEBUG_DRIVER( | |
556 | "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n", | |
557 | sta, cec, lvl, flag0, flag1, flag2); | |
558 | if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { | |
559 | priv->wq_edid_wait = 0; | |
560 | wake_up(&priv->wq_edid); | |
561 | } else if (cec != 0) { /* HPD change */ | |
562 | if (priv->encoder && priv->encoder->dev) | |
563 | drm_helper_hpd_irq_event(priv->encoder->dev); | |
564 | } | |
565 | return IRQ_HANDLED; | |
566 | } | |
567 | ||
c4c11dd1 RK |
568 | static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes) |
569 | { | |
8268bd48 | 570 | int sum = 0; |
c4c11dd1 RK |
571 | |
572 | while (bytes--) | |
8268bd48 DV |
573 | sum -= *buf++; |
574 | return sum; | |
c4c11dd1 RK |
575 | } |
576 | ||
577 | #define HB(x) (x) | |
578 | #define PB(x) (HB(2) + 1 + (x)) | |
579 | ||
580 | static void | |
2f7f730a | 581 | tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr, |
c4c11dd1 RK |
582 | uint8_t *buf, size_t size) |
583 | { | |
584 | buf[PB(0)] = tda998x_cksum(buf, size); | |
585 | ||
2f7f730a JFM |
586 | reg_clear(priv, REG_DIP_IF_FLAGS, bit); |
587 | reg_write_range(priv, addr, buf, size); | |
588 | reg_set(priv, REG_DIP_IF_FLAGS, bit); | |
c4c11dd1 RK |
589 | } |
590 | ||
591 | static void | |
2f7f730a | 592 | tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p) |
c4c11dd1 | 593 | { |
9e541466 | 594 | u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1]; |
c4c11dd1 | 595 | |
7288ca07 | 596 | memset(buf, 0, sizeof(buf)); |
9e541466 | 597 | buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO; |
c4c11dd1 | 598 | buf[HB(1)] = 0x01; |
9e541466 | 599 | buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE; |
c4c11dd1 RK |
600 | buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */ |
601 | buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */ | |
602 | buf[PB(4)] = p->audio_frame[4]; | |
603 | buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */ | |
604 | ||
2f7f730a | 605 | tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf, |
c4c11dd1 RK |
606 | sizeof(buf)); |
607 | } | |
608 | ||
609 | static void | |
2f7f730a | 610 | tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode) |
c4c11dd1 | 611 | { |
9e541466 | 612 | u8 buf[PB(HDMI_AVI_INFOFRAME_SIZE) + 1]; |
c4c11dd1 RK |
613 | |
614 | memset(buf, 0, sizeof(buf)); | |
9e541466 | 615 | buf[HB(0)] = HDMI_INFOFRAME_TYPE_AVI; |
c4c11dd1 | 616 | buf[HB(1)] = 0x02; |
9e541466 | 617 | buf[HB(2)] = HDMI_AVI_INFOFRAME_SIZE; |
893c3e53 | 618 | buf[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN; |
bdf6345b | 619 | buf[PB(2)] = HDMI_ACTIVE_ASPECT_PICTURE; |
893c3e53 | 620 | buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2; |
c4c11dd1 RK |
621 | buf[PB(4)] = drm_match_cea_mode(mode); |
622 | ||
2f7f730a | 623 | tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, |
c4c11dd1 RK |
624 | sizeof(buf)); |
625 | } | |
626 | ||
2f7f730a | 627 | static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) |
c4c11dd1 RK |
628 | { |
629 | if (on) { | |
2f7f730a JFM |
630 | reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); |
631 | reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO); | |
632 | reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); | |
c4c11dd1 | 633 | } else { |
2f7f730a | 634 | reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); |
c4c11dd1 RK |
635 | } |
636 | } | |
637 | ||
638 | static void | |
2f7f730a | 639 | tda998x_configure_audio(struct tda998x_priv *priv, |
c4c11dd1 RK |
640 | struct drm_display_mode *mode, struct tda998x_encoder_params *p) |
641 | { | |
85c988bb | 642 | uint8_t buf[6], clksel_aip, clksel_fs, cts_n, adiv; |
c4c11dd1 RK |
643 | uint32_t n; |
644 | ||
645 | /* Enable audio ports */ | |
2f7f730a JFM |
646 | reg_write(priv, REG_ENA_AP, p->audio_cfg); |
647 | reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg); | |
c4c11dd1 RK |
648 | |
649 | /* Set audio input source */ | |
650 | switch (p->audio_format) { | |
651 | case AFMT_SPDIF: | |
10df1a95 JFM |
652 | reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF); |
653 | clksel_aip = AIP_CLKSEL_AIP_SPDIF; | |
654 | clksel_fs = AIP_CLKSEL_FS_FS64SPDIF; | |
c4c11dd1 | 655 | cts_n = CTS_N_M(3) | CTS_N_K(3); |
c4c11dd1 RK |
656 | break; |
657 | ||
658 | case AFMT_I2S: | |
10df1a95 JFM |
659 | reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S); |
660 | clksel_aip = AIP_CLKSEL_AIP_I2S; | |
661 | clksel_fs = AIP_CLKSEL_FS_ACLK; | |
c4c11dd1 | 662 | cts_n = CTS_N_M(3) | CTS_N_K(3); |
c4c11dd1 | 663 | break; |
3b28802e DH |
664 | |
665 | default: | |
666 | BUG(); | |
667 | return; | |
c4c11dd1 RK |
668 | } |
669 | ||
2f7f730a | 670 | reg_write(priv, REG_AIP_CLKSEL, clksel_aip); |
a8b517e5 JFM |
671 | reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT | |
672 | AIP_CNTRL_0_ACR_MAN); /* auto CTS */ | |
2f7f730a | 673 | reg_write(priv, REG_CTS_N, cts_n); |
c4c11dd1 RK |
674 | |
675 | /* | |
676 | * Audio input somehow depends on HDMI line rate which is | |
677 | * related to pixclk. Testing showed that modes with pixclk | |
678 | * >100MHz need a larger divider while <40MHz need the default. | |
679 | * There is no detailed info in the datasheet, so we just | |
680 | * assume 100MHz requires larger divider. | |
681 | */ | |
2470fecc | 682 | adiv = AUDIO_DIV_SERCLK_8; |
c4c11dd1 | 683 | if (mode->clock > 100000) |
2470fecc JFM |
684 | adiv++; /* AUDIO_DIV_SERCLK_16 */ |
685 | ||
686 | /* S/PDIF asks for a larger divider */ | |
687 | if (p->audio_format == AFMT_SPDIF) | |
688 | adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */ | |
689 | ||
2f7f730a | 690 | reg_write(priv, REG_AUDIO_DIV, adiv); |
c4c11dd1 RK |
691 | |
692 | /* | |
693 | * This is the approximate value of N, which happens to be | |
694 | * the recommended values for non-coherent clocks. | |
695 | */ | |
696 | n = 128 * p->audio_sample_rate / 1000; | |
697 | ||
698 | /* Write the CTS and N values */ | |
699 | buf[0] = 0x44; | |
700 | buf[1] = 0x42; | |
701 | buf[2] = 0x01; | |
702 | buf[3] = n; | |
703 | buf[4] = n >> 8; | |
704 | buf[5] = n >> 16; | |
2f7f730a | 705 | reg_write_range(priv, REG_ACR_CTS_0, buf, 6); |
c4c11dd1 RK |
706 | |
707 | /* Set CTS clock reference */ | |
2f7f730a | 708 | reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs); |
c4c11dd1 RK |
709 | |
710 | /* Reset CTS generator */ | |
2f7f730a JFM |
711 | reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); |
712 | reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); | |
c4c11dd1 RK |
713 | |
714 | /* Write the channel status */ | |
f0b33b28 | 715 | buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT; |
c4c11dd1 | 716 | buf[1] = 0x00; |
f0b33b28 JFM |
717 | buf[2] = IEC958_AES3_CON_FS_NOTID; |
718 | buf[3] = IEC958_AES4_CON_ORIGFS_NOTID | | |
719 | IEC958_AES4_CON_MAX_WORDLEN_24; | |
2f7f730a | 720 | reg_write_range(priv, REG_CH_STAT_B(0), buf, 4); |
c4c11dd1 | 721 | |
2f7f730a | 722 | tda998x_audio_mute(priv, true); |
73d5e253 | 723 | msleep(20); |
2f7f730a | 724 | tda998x_audio_mute(priv, false); |
c4c11dd1 RK |
725 | |
726 | /* Write the audio information packet */ | |
2f7f730a | 727 | tda998x_write_aif(priv, p); |
c4c11dd1 RK |
728 | } |
729 | ||
e7792ce2 RC |
730 | /* DRM encoder functions */ |
731 | ||
a8f4d4d6 RK |
732 | static void tda998x_encoder_set_config(struct tda998x_priv *priv, |
733 | const struct tda998x_encoder_params *p) | |
e7792ce2 | 734 | { |
c4c11dd1 RK |
735 | priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | |
736 | (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | | |
737 | VIP_CNTRL_0_SWAP_B(p->swap_b) | | |
738 | (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); | |
739 | priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | | |
740 | (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | | |
741 | VIP_CNTRL_1_SWAP_D(p->swap_d) | | |
742 | (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); | |
743 | priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | | |
744 | (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | | |
745 | VIP_CNTRL_2_SWAP_F(p->swap_f) | | |
746 | (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); | |
747 | ||
748 | priv->params = *p; | |
e7792ce2 RC |
749 | } |
750 | ||
a8f4d4d6 | 751 | static void tda998x_encoder_dpms(struct tda998x_priv *priv, int mode) |
e7792ce2 | 752 | { |
e7792ce2 RC |
753 | /* we only care about on or off: */ |
754 | if (mode != DRM_MODE_DPMS_ON) | |
755 | mode = DRM_MODE_DPMS_OFF; | |
756 | ||
757 | if (mode == priv->dpms) | |
758 | return; | |
759 | ||
760 | switch (mode) { | |
761 | case DRM_MODE_DPMS_ON: | |
c4c11dd1 | 762 | /* enable video ports, audio will be enabled later */ |
2f7f730a JFM |
763 | reg_write(priv, REG_ENA_VP_0, 0xff); |
764 | reg_write(priv, REG_ENA_VP_1, 0xff); | |
765 | reg_write(priv, REG_ENA_VP_2, 0xff); | |
e7792ce2 | 766 | /* set muxing after enabling ports: */ |
2f7f730a JFM |
767 | reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); |
768 | reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); | |
769 | reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); | |
e7792ce2 RC |
770 | break; |
771 | case DRM_MODE_DPMS_OFF: | |
db6aaf4d | 772 | /* disable video ports */ |
2f7f730a JFM |
773 | reg_write(priv, REG_ENA_VP_0, 0x00); |
774 | reg_write(priv, REG_ENA_VP_1, 0x00); | |
775 | reg_write(priv, REG_ENA_VP_2, 0x00); | |
e7792ce2 RC |
776 | break; |
777 | } | |
778 | ||
779 | priv->dpms = mode; | |
780 | } | |
781 | ||
782 | static void | |
783 | tda998x_encoder_save(struct drm_encoder *encoder) | |
784 | { | |
785 | DBG(""); | |
786 | } | |
787 | ||
788 | static void | |
789 | tda998x_encoder_restore(struct drm_encoder *encoder) | |
790 | { | |
791 | DBG(""); | |
792 | } | |
793 | ||
794 | static bool | |
795 | tda998x_encoder_mode_fixup(struct drm_encoder *encoder, | |
796 | const struct drm_display_mode *mode, | |
797 | struct drm_display_mode *adjusted_mode) | |
798 | { | |
799 | return true; | |
800 | } | |
801 | ||
a8f4d4d6 RK |
802 | static int tda998x_encoder_mode_valid(struct tda998x_priv *priv, |
803 | struct drm_display_mode *mode) | |
e7792ce2 | 804 | { |
92fbdfcd RK |
805 | if (mode->clock > 150000) |
806 | return MODE_CLOCK_HIGH; | |
807 | if (mode->htotal >= BIT(13)) | |
808 | return MODE_BAD_HVALUE; | |
809 | if (mode->vtotal >= BIT(11)) | |
810 | return MODE_BAD_VVALUE; | |
e7792ce2 RC |
811 | return MODE_OK; |
812 | } | |
813 | ||
814 | static void | |
a8f4d4d6 RK |
815 | tda998x_encoder_mode_set(struct tda998x_priv *priv, |
816 | struct drm_display_mode *mode, | |
817 | struct drm_display_mode *adjusted_mode) | |
e7792ce2 | 818 | { |
088d61d1 SH |
819 | uint16_t ref_pix, ref_line, n_pix, n_line; |
820 | uint16_t hs_pix_s, hs_pix_e; | |
821 | uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; | |
822 | uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; | |
823 | uint16_t vwin1_line_s, vwin1_line_e; | |
824 | uint16_t vwin2_line_s, vwin2_line_e; | |
825 | uint16_t de_pix_s, de_pix_e; | |
e7792ce2 RC |
826 | uint8_t reg, div, rep; |
827 | ||
088d61d1 SH |
828 | /* |
829 | * Internally TDA998x is using ITU-R BT.656 style sync but | |
830 | * we get VESA style sync. TDA998x is using a reference pixel | |
831 | * relative to ITU to sync to the input frame and for output | |
832 | * sync generation. Currently, we are using reference detection | |
833 | * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point | |
834 | * which is position of rising VS with coincident rising HS. | |
835 | * | |
836 | * Now there is some issues to take care of: | |
837 | * - HDMI data islands require sync-before-active | |
838 | * - TDA998x register values must be > 0 to be enabled | |
839 | * - REFLINE needs an additional offset of +1 | |
840 | * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB | |
841 | * | |
842 | * So we add +1 to all horizontal and vertical register values, | |
843 | * plus an additional +3 for REFPIX as we are using RGB input only. | |
e7792ce2 | 844 | */ |
088d61d1 SH |
845 | n_pix = mode->htotal; |
846 | n_line = mode->vtotal; | |
847 | ||
848 | hs_pix_e = mode->hsync_end - mode->hdisplay; | |
849 | hs_pix_s = mode->hsync_start - mode->hdisplay; | |
850 | de_pix_e = mode->htotal; | |
851 | de_pix_s = mode->htotal - mode->hdisplay; | |
852 | ref_pix = 3 + hs_pix_s; | |
853 | ||
179f1aa4 SH |
854 | /* |
855 | * Attached LCD controllers may generate broken sync. Allow | |
856 | * those to adjust the position of the rising VS edge by adding | |
857 | * HSKEW to ref_pix. | |
858 | */ | |
859 | if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) | |
860 | ref_pix += adjusted_mode->hskew; | |
861 | ||
088d61d1 SH |
862 | if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { |
863 | ref_line = 1 + mode->vsync_start - mode->vdisplay; | |
864 | vwin1_line_s = mode->vtotal - mode->vdisplay - 1; | |
865 | vwin1_line_e = vwin1_line_s + mode->vdisplay; | |
866 | vs1_pix_s = vs1_pix_e = hs_pix_s; | |
867 | vs1_line_s = mode->vsync_start - mode->vdisplay; | |
868 | vs1_line_e = vs1_line_s + | |
869 | mode->vsync_end - mode->vsync_start; | |
870 | vwin2_line_s = vwin2_line_e = 0; | |
871 | vs2_pix_s = vs2_pix_e = 0; | |
872 | vs2_line_s = vs2_line_e = 0; | |
873 | } else { | |
874 | ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; | |
875 | vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; | |
876 | vwin1_line_e = vwin1_line_s + mode->vdisplay/2; | |
877 | vs1_pix_s = vs1_pix_e = hs_pix_s; | |
878 | vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; | |
879 | vs1_line_e = vs1_line_s + | |
880 | (mode->vsync_end - mode->vsync_start)/2; | |
881 | vwin2_line_s = vwin1_line_s + mode->vtotal/2; | |
882 | vwin2_line_e = vwin2_line_s + mode->vdisplay/2; | |
883 | vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; | |
884 | vs2_line_s = vs1_line_s + mode->vtotal/2 ; | |
885 | vs2_line_e = vs2_line_s + | |
886 | (mode->vsync_end - mode->vsync_start)/2; | |
887 | } | |
e7792ce2 RC |
888 | |
889 | div = 148500 / mode->clock; | |
3ae471f7 JFM |
890 | if (div != 0) { |
891 | div--; | |
892 | if (div > 3) | |
893 | div = 3; | |
894 | } | |
e7792ce2 | 895 | |
e7792ce2 | 896 | /* mute the audio FIFO: */ |
2f7f730a | 897 | reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); |
e7792ce2 RC |
898 | |
899 | /* set HDMI HDCP mode off: */ | |
81b53a16 | 900 | reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); |
2f7f730a JFM |
901 | reg_clear(priv, REG_TX33, TX33_HDMI); |
902 | reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); | |
e7792ce2 | 903 | |
e7792ce2 | 904 | /* no pre-filter or interpolator: */ |
2f7f730a | 905 | reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | |
e7792ce2 | 906 | HVF_CNTRL_0_INTPOL(0)); |
2f7f730a JFM |
907 | reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); |
908 | reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | | |
e7792ce2 | 909 | VIP_CNTRL_4_BLC(0)); |
e7792ce2 | 910 | |
2f7f730a | 911 | reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); |
a8b517e5 JFM |
912 | reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR | |
913 | PLL_SERIAL_3_SRL_DE); | |
2f7f730a JFM |
914 | reg_write(priv, REG_SERIALIZER, 0); |
915 | reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); | |
e7792ce2 RC |
916 | |
917 | /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ | |
918 | rep = 0; | |
2f7f730a JFM |
919 | reg_write(priv, REG_RPT_CNTRL, 0); |
920 | reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | | |
e7792ce2 RC |
921 | SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); |
922 | ||
2f7f730a | 923 | reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | |
e7792ce2 RC |
924 | PLL_SERIAL_2_SRL_PR(rep)); |
925 | ||
e7792ce2 | 926 | /* set color matrix bypass flag: */ |
81b53a16 JFM |
927 | reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | |
928 | MAT_CONTRL_MAT_SC(1)); | |
e7792ce2 RC |
929 | |
930 | /* set BIAS tmds value: */ | |
2f7f730a | 931 | reg_write(priv, REG_ANA_GENERAL, 0x09); |
e7792ce2 | 932 | |
088d61d1 SH |
933 | /* |
934 | * Sync on rising HSYNC/VSYNC | |
935 | */ | |
81b53a16 | 936 | reg = VIP_CNTRL_3_SYNC_HS; |
088d61d1 SH |
937 | |
938 | /* | |
939 | * TDA19988 requires high-active sync at input stage, | |
940 | * so invert low-active sync provided by master encoder here | |
941 | */ | |
942 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
81b53a16 | 943 | reg |= VIP_CNTRL_3_H_TGL; |
e7792ce2 | 944 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
81b53a16 JFM |
945 | reg |= VIP_CNTRL_3_V_TGL; |
946 | reg_write(priv, REG_VIP_CNTRL_3, reg); | |
2f7f730a JFM |
947 | |
948 | reg_write(priv, REG_VIDFORMAT, 0x00); | |
949 | reg_write16(priv, REG_REFPIX_MSB, ref_pix); | |
950 | reg_write16(priv, REG_REFLINE_MSB, ref_line); | |
951 | reg_write16(priv, REG_NPIX_MSB, n_pix); | |
952 | reg_write16(priv, REG_NLINE_MSB, n_line); | |
953 | reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s); | |
954 | reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); | |
955 | reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e); | |
956 | reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e); | |
957 | reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s); | |
958 | reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); | |
959 | reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e); | |
960 | reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e); | |
961 | reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s); | |
962 | reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e); | |
963 | reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s); | |
964 | reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e); | |
965 | reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s); | |
966 | reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e); | |
967 | reg_write16(priv, REG_DE_START_MSB, de_pix_s); | |
968 | reg_write16(priv, REG_DE_STOP_MSB, de_pix_e); | |
e7792ce2 RC |
969 | |
970 | if (priv->rev == TDA19988) { | |
971 | /* let incoming pixels fill the active space (if any) */ | |
2f7f730a | 972 | reg_write(priv, REG_ENABLE_SPACE, 0x00); |
e7792ce2 RC |
973 | } |
974 | ||
81b53a16 JFM |
975 | /* |
976 | * Always generate sync polarity relative to input sync and | |
977 | * revert input stage toggled sync at output stage | |
978 | */ | |
979 | reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; | |
980 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
981 | reg |= TBG_CNTRL_1_H_TGL; | |
982 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
983 | reg |= TBG_CNTRL_1_V_TGL; | |
984 | reg_write(priv, REG_TBG_CNTRL_1, reg); | |
985 | ||
e7792ce2 | 986 | /* must be last register set: */ |
81b53a16 | 987 | reg_write(priv, REG_TBG_CNTRL_0, 0); |
c4c11dd1 RK |
988 | |
989 | /* Only setup the info frames if the sink is HDMI */ | |
990 | if (priv->is_hdmi_sink) { | |
991 | /* We need to turn HDMI HDCP stuff on to get audio through */ | |
81b53a16 JFM |
992 | reg &= ~TBG_CNTRL_1_DWIN_DIS; |
993 | reg_write(priv, REG_TBG_CNTRL_1, reg); | |
2f7f730a JFM |
994 | reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); |
995 | reg_set(priv, REG_TX33, TX33_HDMI); | |
c4c11dd1 | 996 | |
2f7f730a | 997 | tda998x_write_avi(priv, adjusted_mode); |
c4c11dd1 RK |
998 | |
999 | if (priv->params.audio_cfg) | |
2f7f730a | 1000 | tda998x_configure_audio(priv, adjusted_mode, |
c4c11dd1 RK |
1001 | &priv->params); |
1002 | } | |
e7792ce2 RC |
1003 | } |
1004 | ||
1005 | static enum drm_connector_status | |
a8f4d4d6 | 1006 | tda998x_encoder_detect(struct tda998x_priv *priv) |
e7792ce2 | 1007 | { |
2f7f730a JFM |
1008 | uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV); |
1009 | ||
e7792ce2 RC |
1010 | return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : |
1011 | connector_status_disconnected; | |
1012 | } | |
1013 | ||
a8f4d4d6 | 1014 | static int read_edid_block(struct tda998x_priv *priv, uint8_t *buf, int blk) |
e7792ce2 RC |
1015 | { |
1016 | uint8_t offset, segptr; | |
1017 | int ret, i; | |
1018 | ||
e7792ce2 RC |
1019 | offset = (blk & 1) ? 128 : 0; |
1020 | segptr = blk / 2; | |
1021 | ||
2f7f730a JFM |
1022 | reg_write(priv, REG_DDC_ADDR, 0xa0); |
1023 | reg_write(priv, REG_DDC_OFFS, offset); | |
1024 | reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); | |
1025 | reg_write(priv, REG_DDC_SEGM, segptr); | |
e7792ce2 RC |
1026 | |
1027 | /* enable reading EDID: */ | |
12473b7d | 1028 | priv->wq_edid_wait = 1; |
2f7f730a | 1029 | reg_write(priv, REG_EDID_CTRL, 0x1); |
e7792ce2 RC |
1030 | |
1031 | /* flag must be cleared by sw: */ | |
2f7f730a | 1032 | reg_write(priv, REG_EDID_CTRL, 0x0); |
e7792ce2 RC |
1033 | |
1034 | /* wait for block read to complete: */ | |
12473b7d JFM |
1035 | if (priv->hdmi->irq) { |
1036 | i = wait_event_timeout(priv->wq_edid, | |
1037 | !priv->wq_edid_wait, | |
1038 | msecs_to_jiffies(100)); | |
1039 | if (i < 0) { | |
5e7fe2fe | 1040 | dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); |
12473b7d JFM |
1041 | return i; |
1042 | } | |
1043 | } else { | |
713456db RK |
1044 | for (i = 100; i > 0; i--) { |
1045 | msleep(1); | |
12473b7d JFM |
1046 | ret = reg_read(priv, REG_INT_FLAGS_2); |
1047 | if (ret < 0) | |
1048 | return ret; | |
1049 | if (ret & INT_FLAGS_2_EDID_BLK_RD) | |
1050 | break; | |
1051 | } | |
e7792ce2 RC |
1052 | } |
1053 | ||
12473b7d | 1054 | if (i == 0) { |
5e7fe2fe | 1055 | dev_err(&priv->hdmi->dev, "read edid timeout\n"); |
e7792ce2 | 1056 | return -ETIMEDOUT; |
12473b7d | 1057 | } |
e7792ce2 | 1058 | |
2f7f730a | 1059 | ret = reg_read_range(priv, REG_EDID_DATA_0, buf, EDID_LENGTH); |
e7792ce2 | 1060 | if (ret != EDID_LENGTH) { |
5e7fe2fe RK |
1061 | dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", |
1062 | blk, ret); | |
e7792ce2 RC |
1063 | return ret; |
1064 | } | |
1065 | ||
e7792ce2 RC |
1066 | return 0; |
1067 | } | |
1068 | ||
a8f4d4d6 | 1069 | static uint8_t *do_get_edid(struct tda998x_priv *priv) |
e7792ce2 | 1070 | { |
704d63f5 | 1071 | int j, valid_extensions = 0; |
e7792ce2 RC |
1072 | uint8_t *block, *new; |
1073 | bool print_bad_edid = drm_debug & DRM_UT_KMS; | |
1074 | ||
1075 | if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) | |
1076 | return NULL; | |
1077 | ||
063b472f | 1078 | if (priv->rev == TDA19988) |
2f7f730a | 1079 | reg_clear(priv, REG_TX4, TX4_PD_RAM); |
063b472f | 1080 | |
e7792ce2 | 1081 | /* base block fetch */ |
a8f4d4d6 | 1082 | if (read_edid_block(priv, block, 0)) |
e7792ce2 RC |
1083 | goto fail; |
1084 | ||
1085 | if (!drm_edid_block_valid(block, 0, print_bad_edid)) | |
1086 | goto fail; | |
1087 | ||
1088 | /* if there's no extensions, we're done */ | |
1089 | if (block[0x7e] == 0) | |
063b472f | 1090 | goto done; |
e7792ce2 RC |
1091 | |
1092 | new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); | |
1093 | if (!new) | |
1094 | goto fail; | |
1095 | block = new; | |
1096 | ||
1097 | for (j = 1; j <= block[0x7e]; j++) { | |
1098 | uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; | |
a8f4d4d6 | 1099 | if (read_edid_block(priv, ext_block, j)) |
e7792ce2 RC |
1100 | goto fail; |
1101 | ||
1102 | if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) | |
1103 | goto fail; | |
1104 | ||
1105 | valid_extensions++; | |
1106 | } | |
1107 | ||
1108 | if (valid_extensions != block[0x7e]) { | |
1109 | block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; | |
1110 | block[0x7e] = valid_extensions; | |
1111 | new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); | |
1112 | if (!new) | |
1113 | goto fail; | |
1114 | block = new; | |
1115 | } | |
1116 | ||
063b472f RK |
1117 | done: |
1118 | if (priv->rev == TDA19988) | |
2f7f730a | 1119 | reg_set(priv, REG_TX4, TX4_PD_RAM); |
063b472f | 1120 | |
e7792ce2 RC |
1121 | return block; |
1122 | ||
1123 | fail: | |
063b472f | 1124 | if (priv->rev == TDA19988) |
2f7f730a | 1125 | reg_set(priv, REG_TX4, TX4_PD_RAM); |
5e7fe2fe | 1126 | dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); |
e7792ce2 RC |
1127 | kfree(block); |
1128 | return NULL; | |
1129 | } | |
1130 | ||
1131 | static int | |
a8f4d4d6 RK |
1132 | tda998x_encoder_get_modes(struct tda998x_priv *priv, |
1133 | struct drm_connector *connector) | |
e7792ce2 | 1134 | { |
a8f4d4d6 | 1135 | struct edid *edid = (struct edid *)do_get_edid(priv); |
e7792ce2 RC |
1136 | int n = 0; |
1137 | ||
1138 | if (edid) { | |
1139 | drm_mode_connector_update_edid_property(connector, edid); | |
1140 | n = drm_add_edid_modes(connector, edid); | |
c4c11dd1 | 1141 | priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); |
e7792ce2 RC |
1142 | kfree(edid); |
1143 | } | |
1144 | ||
1145 | return n; | |
1146 | } | |
1147 | ||
a8f4d4d6 RK |
1148 | static void tda998x_encoder_set_polling(struct tda998x_priv *priv, |
1149 | struct drm_connector *connector) | |
e7792ce2 | 1150 | { |
12473b7d JFM |
1151 | if (priv->hdmi->irq) |
1152 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
1153 | else | |
1154 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | | |
1155 | DRM_CONNECTOR_POLL_DISCONNECT; | |
e7792ce2 RC |
1156 | } |
1157 | ||
1158 | static int | |
1159 | tda998x_encoder_set_property(struct drm_encoder *encoder, | |
1160 | struct drm_connector *connector, | |
1161 | struct drm_property *property, | |
1162 | uint64_t val) | |
1163 | { | |
1164 | DBG(""); | |
1165 | return 0; | |
1166 | } | |
1167 | ||
a8f4d4d6 | 1168 | static void tda998x_destroy(struct tda998x_priv *priv) |
e7792ce2 | 1169 | { |
12473b7d JFM |
1170 | /* disable all IRQs and free the IRQ handler */ |
1171 | cec_write(priv, REG_CEC_RXSHPDINTENA, 0); | |
1172 | reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); | |
1173 | if (priv->hdmi->irq) | |
1174 | free_irq(priv->hdmi->irq, priv); | |
1175 | ||
89fc8686 | 1176 | i2c_unregister_device(priv->cec); |
a8f4d4d6 RK |
1177 | } |
1178 | ||
1179 | /* Slave encoder support */ | |
1180 | ||
1181 | static void | |
1182 | tda998x_encoder_slave_set_config(struct drm_encoder *encoder, void *params) | |
1183 | { | |
1184 | tda998x_encoder_set_config(to_tda998x_priv(encoder), params); | |
1185 | } | |
1186 | ||
1187 | static void tda998x_encoder_slave_destroy(struct drm_encoder *encoder) | |
1188 | { | |
1189 | struct tda998x_priv *priv = to_tda998x_priv(encoder); | |
1190 | ||
1191 | tda998x_destroy(priv); | |
2e48cecb | 1192 | drm_i2c_encoder_destroy(encoder); |
e7792ce2 RC |
1193 | kfree(priv); |
1194 | } | |
1195 | ||
a8f4d4d6 RK |
1196 | static void tda998x_encoder_slave_dpms(struct drm_encoder *encoder, int mode) |
1197 | { | |
1198 | tda998x_encoder_dpms(to_tda998x_priv(encoder), mode); | |
1199 | } | |
e7792ce2 | 1200 | |
a8f4d4d6 RK |
1201 | static int tda998x_encoder_slave_mode_valid(struct drm_encoder *encoder, |
1202 | struct drm_display_mode *mode) | |
1203 | { | |
1204 | return tda998x_encoder_mode_valid(to_tda998x_priv(encoder), mode); | |
1205 | } | |
e7792ce2 | 1206 | |
a8f4d4d6 RK |
1207 | static void |
1208 | tda998x_encoder_slave_mode_set(struct drm_encoder *encoder, | |
1209 | struct drm_display_mode *mode, | |
1210 | struct drm_display_mode *adjusted_mode) | |
e7792ce2 | 1211 | { |
a8f4d4d6 RK |
1212 | tda998x_encoder_mode_set(to_tda998x_priv(encoder), mode, adjusted_mode); |
1213 | } | |
1214 | ||
1215 | static enum drm_connector_status | |
1216 | tda998x_encoder_slave_detect(struct drm_encoder *encoder, | |
1217 | struct drm_connector *connector) | |
1218 | { | |
1219 | return tda998x_encoder_detect(to_tda998x_priv(encoder)); | |
1220 | } | |
1221 | ||
1222 | static int tda998x_encoder_slave_get_modes(struct drm_encoder *encoder, | |
1223 | struct drm_connector *connector) | |
1224 | { | |
1225 | return tda998x_encoder_get_modes(to_tda998x_priv(encoder), connector); | |
e7792ce2 RC |
1226 | } |
1227 | ||
1228 | static int | |
a8f4d4d6 RK |
1229 | tda998x_encoder_slave_create_resources(struct drm_encoder *encoder, |
1230 | struct drm_connector *connector) | |
e7792ce2 | 1231 | { |
a8f4d4d6 | 1232 | tda998x_encoder_set_polling(to_tda998x_priv(encoder), connector); |
e7792ce2 RC |
1233 | return 0; |
1234 | } | |
1235 | ||
a8f4d4d6 RK |
1236 | static struct drm_encoder_slave_funcs tda998x_encoder_slave_funcs = { |
1237 | .set_config = tda998x_encoder_slave_set_config, | |
1238 | .destroy = tda998x_encoder_slave_destroy, | |
1239 | .dpms = tda998x_encoder_slave_dpms, | |
e7792ce2 RC |
1240 | .save = tda998x_encoder_save, |
1241 | .restore = tda998x_encoder_restore, | |
1242 | .mode_fixup = tda998x_encoder_mode_fixup, | |
a8f4d4d6 RK |
1243 | .mode_valid = tda998x_encoder_slave_mode_valid, |
1244 | .mode_set = tda998x_encoder_slave_mode_set, | |
1245 | .detect = tda998x_encoder_slave_detect, | |
1246 | .get_modes = tda998x_encoder_slave_get_modes, | |
1247 | .create_resources = tda998x_encoder_slave_create_resources, | |
e7792ce2 RC |
1248 | .set_property = tda998x_encoder_set_property, |
1249 | }; | |
1250 | ||
1251 | /* I2C driver functions */ | |
1252 | ||
a8f4d4d6 | 1253 | static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) |
e7792ce2 | 1254 | { |
0d44ea19 JFM |
1255 | struct device_node *np = client->dev.of_node; |
1256 | u32 video; | |
fb7544d7 | 1257 | int rev_lo, rev_hi, ret; |
e7792ce2 | 1258 | |
5e74c22c RK |
1259 | priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); |
1260 | priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); | |
1261 | priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); | |
1262 | ||
2eb4c7b1 | 1263 | priv->current_page = 0xff; |
2f7f730a | 1264 | priv->hdmi = client; |
e7792ce2 | 1265 | priv->cec = i2c_new_dummy(client->adapter, 0x34); |
a8f4d4d6 | 1266 | if (!priv->cec) |
6ae668cc | 1267 | return -ENODEV; |
12473b7d | 1268 | |
e7792ce2 RC |
1269 | priv->dpms = DRM_MODE_DPMS_OFF; |
1270 | ||
e7792ce2 | 1271 | /* wake up the device: */ |
2f7f730a | 1272 | cec_write(priv, REG_CEC_ENAMODS, |
e7792ce2 RC |
1273 | CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); |
1274 | ||
2f7f730a | 1275 | tda998x_reset(priv); |
e7792ce2 RC |
1276 | |
1277 | /* read version: */ | |
fb7544d7 RK |
1278 | rev_lo = reg_read(priv, REG_VERSION_LSB); |
1279 | rev_hi = reg_read(priv, REG_VERSION_MSB); | |
1280 | if (rev_lo < 0 || rev_hi < 0) { | |
1281 | ret = rev_lo < 0 ? rev_lo : rev_hi; | |
7d2eadc9 | 1282 | goto fail; |
fb7544d7 RK |
1283 | } |
1284 | ||
1285 | priv->rev = rev_lo | rev_hi << 8; | |
e7792ce2 RC |
1286 | |
1287 | /* mask off feature bits: */ | |
1288 | priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ | |
1289 | ||
1290 | switch (priv->rev) { | |
b728fab7 JFM |
1291 | case TDA9989N2: |
1292 | dev_info(&client->dev, "found TDA9989 n2"); | |
1293 | break; | |
1294 | case TDA19989: | |
1295 | dev_info(&client->dev, "found TDA19989"); | |
1296 | break; | |
1297 | case TDA19989N2: | |
1298 | dev_info(&client->dev, "found TDA19989 n2"); | |
1299 | break; | |
1300 | case TDA19988: | |
1301 | dev_info(&client->dev, "found TDA19988"); | |
1302 | break; | |
e7792ce2 | 1303 | default: |
b728fab7 JFM |
1304 | dev_err(&client->dev, "found unsupported device: %04x\n", |
1305 | priv->rev); | |
e7792ce2 RC |
1306 | goto fail; |
1307 | } | |
1308 | ||
1309 | /* after reset, enable DDC: */ | |
2f7f730a | 1310 | reg_write(priv, REG_DDC_DISABLE, 0x00); |
e7792ce2 RC |
1311 | |
1312 | /* set clock on DDC channel: */ | |
2f7f730a | 1313 | reg_write(priv, REG_TX3, 39); |
e7792ce2 RC |
1314 | |
1315 | /* if necessary, disable multi-master: */ | |
1316 | if (priv->rev == TDA19989) | |
2f7f730a | 1317 | reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); |
e7792ce2 | 1318 | |
2f7f730a | 1319 | cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL, |
e7792ce2 RC |
1320 | CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); |
1321 | ||
12473b7d JFM |
1322 | /* initialize the optional IRQ */ |
1323 | if (client->irq) { | |
1324 | int irqf_trigger; | |
1325 | ||
1326 | /* init read EDID waitqueue */ | |
1327 | init_waitqueue_head(&priv->wq_edid); | |
1328 | ||
1329 | /* clear pending interrupts */ | |
1330 | reg_read(priv, REG_INT_FLAGS_0); | |
1331 | reg_read(priv, REG_INT_FLAGS_1); | |
1332 | reg_read(priv, REG_INT_FLAGS_2); | |
1333 | ||
1334 | irqf_trigger = | |
1335 | irqd_get_trigger_type(irq_get_irq_data(client->irq)); | |
1336 | ret = request_threaded_irq(client->irq, NULL, | |
1337 | tda998x_irq_thread, | |
1338 | irqf_trigger | IRQF_ONESHOT, | |
1339 | "tda998x", priv); | |
1340 | if (ret) { | |
1341 | dev_err(&client->dev, | |
1342 | "failed to request IRQ#%u: %d\n", | |
1343 | client->irq, ret); | |
1344 | goto fail; | |
1345 | } | |
1346 | ||
1347 | /* enable HPD irq */ | |
1348 | cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD); | |
1349 | } | |
1350 | ||
e4782627 JFM |
1351 | /* enable EDID read irq: */ |
1352 | reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); | |
1353 | ||
0d44ea19 JFM |
1354 | if (!np) |
1355 | return 0; /* non-DT */ | |
1356 | ||
1357 | /* get the optional video properties */ | |
1358 | ret = of_property_read_u32(np, "video-ports", &video); | |
1359 | if (ret == 0) { | |
1360 | priv->vip_cntrl_0 = video >> 16; | |
1361 | priv->vip_cntrl_1 = video >> 8; | |
1362 | priv->vip_cntrl_2 = video; | |
1363 | } | |
1364 | ||
e7792ce2 RC |
1365 | return 0; |
1366 | ||
1367 | fail: | |
1368 | /* if encoder_init fails, the encoder slave is never registered, | |
1369 | * so cleanup here: | |
1370 | */ | |
1371 | if (priv->cec) | |
1372 | i2c_unregister_device(priv->cec); | |
e7792ce2 RC |
1373 | return -ENXIO; |
1374 | } | |
1375 | ||
a8f4d4d6 RK |
1376 | static int tda998x_encoder_init(struct i2c_client *client, |
1377 | struct drm_device *dev, | |
1378 | struct drm_encoder_slave *encoder_slave) | |
1379 | { | |
1380 | struct tda998x_priv *priv; | |
1381 | int ret; | |
1382 | ||
1383 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
1384 | if (!priv) | |
1385 | return -ENOMEM; | |
1386 | ||
1387 | priv->encoder = &encoder_slave->base; | |
1388 | ||
1389 | ret = tda998x_create(client, priv); | |
1390 | if (ret) { | |
1391 | kfree(priv); | |
1392 | return ret; | |
1393 | } | |
1394 | ||
1395 | encoder_slave->slave_priv = priv; | |
1396 | encoder_slave->slave_funcs = &tda998x_encoder_slave_funcs; | |
1397 | ||
1398 | return 0; | |
1399 | } | |
1400 | ||
c707c361 RK |
1401 | struct tda998x_priv2 { |
1402 | struct tda998x_priv base; | |
1403 | struct drm_encoder encoder; | |
1404 | struct drm_connector connector; | |
1405 | }; | |
1406 | ||
1407 | #define conn_to_tda998x_priv2(x) \ | |
1408 | container_of(x, struct tda998x_priv2, connector); | |
1409 | ||
1410 | #define enc_to_tda998x_priv2(x) \ | |
1411 | container_of(x, struct tda998x_priv2, encoder); | |
1412 | ||
1413 | static void tda998x_encoder2_dpms(struct drm_encoder *encoder, int mode) | |
1414 | { | |
1415 | struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder); | |
1416 | ||
1417 | tda998x_encoder_dpms(&priv->base, mode); | |
1418 | } | |
1419 | ||
1420 | static void tda998x_encoder_prepare(struct drm_encoder *encoder) | |
1421 | { | |
1422 | tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_OFF); | |
1423 | } | |
1424 | ||
1425 | static void tda998x_encoder_commit(struct drm_encoder *encoder) | |
1426 | { | |
1427 | tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_ON); | |
1428 | } | |
1429 | ||
1430 | static void tda998x_encoder2_mode_set(struct drm_encoder *encoder, | |
1431 | struct drm_display_mode *mode, | |
1432 | struct drm_display_mode *adjusted_mode) | |
1433 | { | |
1434 | struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder); | |
1435 | ||
1436 | tda998x_encoder_mode_set(&priv->base, mode, adjusted_mode); | |
1437 | } | |
1438 | ||
1439 | static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = { | |
1440 | .dpms = tda998x_encoder2_dpms, | |
1441 | .save = tda998x_encoder_save, | |
1442 | .restore = tda998x_encoder_restore, | |
1443 | .mode_fixup = tda998x_encoder_mode_fixup, | |
1444 | .prepare = tda998x_encoder_prepare, | |
1445 | .commit = tda998x_encoder_commit, | |
1446 | .mode_set = tda998x_encoder2_mode_set, | |
1447 | }; | |
1448 | ||
1449 | static void tda998x_encoder_destroy(struct drm_encoder *encoder) | |
1450 | { | |
1451 | struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder); | |
1452 | ||
1453 | tda998x_destroy(&priv->base); | |
1454 | drm_encoder_cleanup(encoder); | |
1455 | } | |
1456 | ||
1457 | static const struct drm_encoder_funcs tda998x_encoder_funcs = { | |
1458 | .destroy = tda998x_encoder_destroy, | |
1459 | }; | |
1460 | ||
1461 | static int tda998x_connector_get_modes(struct drm_connector *connector) | |
1462 | { | |
1463 | struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector); | |
1464 | ||
1465 | return tda998x_encoder_get_modes(&priv->base, connector); | |
1466 | } | |
1467 | ||
1468 | static int tda998x_connector_mode_valid(struct drm_connector *connector, | |
1469 | struct drm_display_mode *mode) | |
1470 | { | |
1471 | struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector); | |
1472 | ||
1473 | return tda998x_encoder_mode_valid(&priv->base, mode); | |
1474 | } | |
1475 | ||
1476 | static struct drm_encoder * | |
1477 | tda998x_connector_best_encoder(struct drm_connector *connector) | |
1478 | { | |
1479 | struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector); | |
1480 | ||
1481 | return &priv->encoder; | |
1482 | } | |
1483 | ||
1484 | static | |
1485 | const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = { | |
1486 | .get_modes = tda998x_connector_get_modes, | |
1487 | .mode_valid = tda998x_connector_mode_valid, | |
1488 | .best_encoder = tda998x_connector_best_encoder, | |
1489 | }; | |
1490 | ||
1491 | static enum drm_connector_status | |
1492 | tda998x_connector_detect(struct drm_connector *connector, bool force) | |
1493 | { | |
1494 | struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector); | |
1495 | ||
1496 | return tda998x_encoder_detect(&priv->base); | |
1497 | } | |
1498 | ||
1499 | static void tda998x_connector_destroy(struct drm_connector *connector) | |
1500 | { | |
74cd62ea | 1501 | drm_connector_unregister(connector); |
c707c361 RK |
1502 | drm_connector_cleanup(connector); |
1503 | } | |
1504 | ||
1505 | static const struct drm_connector_funcs tda998x_connector_funcs = { | |
1506 | .dpms = drm_helper_connector_dpms, | |
1507 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1508 | .detect = tda998x_connector_detect, | |
1509 | .destroy = tda998x_connector_destroy, | |
1510 | }; | |
1511 | ||
1512 | static int tda998x_bind(struct device *dev, struct device *master, void *data) | |
1513 | { | |
1514 | struct tda998x_encoder_params *params = dev->platform_data; | |
1515 | struct i2c_client *client = to_i2c_client(dev); | |
1516 | struct drm_device *drm = data; | |
1517 | struct tda998x_priv2 *priv; | |
1518 | int ret; | |
1519 | ||
1520 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
1521 | if (!priv) | |
1522 | return -ENOMEM; | |
1523 | ||
1524 | dev_set_drvdata(dev, priv); | |
1525 | ||
1526 | priv->base.encoder = &priv->encoder; | |
1527 | priv->connector.interlace_allowed = 1; | |
1528 | priv->encoder.possible_crtcs = 1 << 0; | |
1529 | ||
1530 | ret = tda998x_create(client, &priv->base); | |
1531 | if (ret) | |
1532 | return ret; | |
1533 | ||
1534 | if (!dev->of_node && params) | |
1535 | tda998x_encoder_set_config(&priv->base, params); | |
1536 | ||
1537 | tda998x_encoder_set_polling(&priv->base, &priv->connector); | |
1538 | ||
1539 | drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs); | |
1540 | ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs, | |
1541 | DRM_MODE_ENCODER_TMDS); | |
1542 | if (ret) | |
1543 | goto err_encoder; | |
1544 | ||
1545 | drm_connector_helper_add(&priv->connector, | |
1546 | &tda998x_connector_helper_funcs); | |
1547 | ret = drm_connector_init(drm, &priv->connector, | |
1548 | &tda998x_connector_funcs, | |
1549 | DRM_MODE_CONNECTOR_HDMIA); | |
1550 | if (ret) | |
1551 | goto err_connector; | |
1552 | ||
74cd62ea | 1553 | ret = drm_connector_register(&priv->connector); |
c707c361 RK |
1554 | if (ret) |
1555 | goto err_sysfs; | |
1556 | ||
1557 | priv->connector.encoder = &priv->encoder; | |
1558 | drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder); | |
1559 | ||
1560 | return 0; | |
1561 | ||
1562 | err_sysfs: | |
1563 | drm_connector_cleanup(&priv->connector); | |
1564 | err_connector: | |
1565 | drm_encoder_cleanup(&priv->encoder); | |
1566 | err_encoder: | |
1567 | tda998x_destroy(&priv->base); | |
1568 | return ret; | |
1569 | } | |
1570 | ||
1571 | static void tda998x_unbind(struct device *dev, struct device *master, | |
1572 | void *data) | |
1573 | { | |
1574 | struct tda998x_priv2 *priv = dev_get_drvdata(dev); | |
1575 | ||
1576 | drm_connector_cleanup(&priv->connector); | |
1577 | drm_encoder_cleanup(&priv->encoder); | |
1578 | tda998x_destroy(&priv->base); | |
1579 | } | |
1580 | ||
1581 | static const struct component_ops tda998x_ops = { | |
1582 | .bind = tda998x_bind, | |
1583 | .unbind = tda998x_unbind, | |
1584 | }; | |
1585 | ||
1586 | static int | |
1587 | tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) | |
1588 | { | |
1589 | return component_add(&client->dev, &tda998x_ops); | |
1590 | } | |
1591 | ||
1592 | static int tda998x_remove(struct i2c_client *client) | |
1593 | { | |
1594 | component_del(&client->dev, &tda998x_ops); | |
1595 | return 0; | |
1596 | } | |
1597 | ||
0d44ea19 JFM |
1598 | #ifdef CONFIG_OF |
1599 | static const struct of_device_id tda998x_dt_ids[] = { | |
1600 | { .compatible = "nxp,tda998x", }, | |
1601 | { } | |
1602 | }; | |
1603 | MODULE_DEVICE_TABLE(of, tda998x_dt_ids); | |
1604 | #endif | |
1605 | ||
e7792ce2 RC |
1606 | static struct i2c_device_id tda998x_ids[] = { |
1607 | { "tda998x", 0 }, | |
1608 | { } | |
1609 | }; | |
1610 | MODULE_DEVICE_TABLE(i2c, tda998x_ids); | |
1611 | ||
1612 | static struct drm_i2c_encoder_driver tda998x_driver = { | |
1613 | .i2c_driver = { | |
1614 | .probe = tda998x_probe, | |
1615 | .remove = tda998x_remove, | |
1616 | .driver = { | |
1617 | .name = "tda998x", | |
0d44ea19 | 1618 | .of_match_table = of_match_ptr(tda998x_dt_ids), |
e7792ce2 RC |
1619 | }, |
1620 | .id_table = tda998x_ids, | |
1621 | }, | |
1622 | .encoder_init = tda998x_encoder_init, | |
1623 | }; | |
1624 | ||
1625 | /* Module initialization */ | |
1626 | ||
1627 | static int __init | |
1628 | tda998x_init(void) | |
1629 | { | |
1630 | DBG(""); | |
1631 | return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); | |
1632 | } | |
1633 | ||
1634 | static void __exit | |
1635 | tda998x_exit(void) | |
1636 | { | |
1637 | DBG(""); | |
1638 | drm_i2c_encoder_unregister(&tda998x_driver); | |
1639 | } | |
1640 | ||
1641 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
1642 | MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); | |
1643 | MODULE_LICENSE("GPL"); | |
1644 | ||
1645 | module_init(tda998x_init); | |
1646 | module_exit(tda998x_exit); |