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e7792ce2 RC |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | ||
19 | ||
20 | #include <linux/module.h> | |
21 | ||
22 | #include <drm/drmP.h> | |
23 | #include <drm/drm_crtc_helper.h> | |
24 | #include <drm/drm_encoder_slave.h> | |
25 | #include <drm/drm_edid.h> | |
26 | ||
27 | ||
28 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) | |
29 | ||
30 | struct tda998x_priv { | |
31 | struct i2c_client *cec; | |
32 | uint16_t rev; | |
33 | uint8_t current_page; | |
34 | int dpms; | |
35 | }; | |
36 | ||
37 | #define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) | |
38 | ||
39 | /* The TDA9988 series of devices use a paged register scheme.. to simplify | |
40 | * things we encode the page # in upper bits of the register #. To read/ | |
41 | * write a given register, we need to make sure CURPAGE register is set | |
42 | * appropriately. Which implies reads/writes are not atomic. Fun! | |
43 | */ | |
44 | ||
45 | #define REG(page, addr) (((page) << 8) | (addr)) | |
46 | #define REG2ADDR(reg) ((reg) & 0xff) | |
47 | #define REG2PAGE(reg) (((reg) >> 8) & 0xff) | |
48 | ||
49 | #define REG_CURPAGE 0xff /* write */ | |
50 | ||
51 | ||
52 | /* Page 00h: General Control */ | |
53 | #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ | |
54 | #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ | |
55 | # define MAIN_CNTRL0_SR (1 << 0) | |
56 | # define MAIN_CNTRL0_DECS (1 << 1) | |
57 | # define MAIN_CNTRL0_DEHS (1 << 2) | |
58 | # define MAIN_CNTRL0_CECS (1 << 3) | |
59 | # define MAIN_CNTRL0_CEHS (1 << 4) | |
60 | # define MAIN_CNTRL0_SCALER (1 << 7) | |
61 | #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ | |
62 | #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ | |
63 | # define SOFTRESET_AUDIO (1 << 0) | |
64 | # define SOFTRESET_I2C_MASTER (1 << 1) | |
65 | #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ | |
66 | #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ | |
67 | #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ | |
68 | # define I2C_MASTER_DIS_MM (1 << 0) | |
69 | # define I2C_MASTER_DIS_FILT (1 << 1) | |
70 | # define I2C_MASTER_APP_STRT_LAT (1 << 2) | |
71 | #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ | |
72 | #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ | |
73 | #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ | |
74 | # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) | |
75 | #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ | |
76 | #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ | |
77 | #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ | |
78 | #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ | |
79 | #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ | |
80 | # define VIP_CNTRL_0_MIRR_A (1 << 7) | |
81 | # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) | |
82 | # define VIP_CNTRL_0_MIRR_B (1 << 3) | |
83 | # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) | |
84 | #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ | |
85 | # define VIP_CNTRL_1_MIRR_C (1 << 7) | |
86 | # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) | |
87 | # define VIP_CNTRL_1_MIRR_D (1 << 3) | |
88 | # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) | |
89 | #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ | |
90 | # define VIP_CNTRL_2_MIRR_E (1 << 7) | |
91 | # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) | |
92 | # define VIP_CNTRL_2_MIRR_F (1 << 3) | |
93 | # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) | |
94 | #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ | |
95 | # define VIP_CNTRL_3_X_TGL (1 << 0) | |
96 | # define VIP_CNTRL_3_H_TGL (1 << 1) | |
97 | # define VIP_CNTRL_3_V_TGL (1 << 2) | |
98 | # define VIP_CNTRL_3_EMB (1 << 3) | |
99 | # define VIP_CNTRL_3_SYNC_DE (1 << 4) | |
100 | # define VIP_CNTRL_3_SYNC_HS (1 << 5) | |
101 | # define VIP_CNTRL_3_DE_INT (1 << 6) | |
102 | # define VIP_CNTRL_3_EDGE (1 << 7) | |
103 | #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ | |
104 | # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) | |
105 | # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) | |
106 | # define VIP_CNTRL_4_CCIR656 (1 << 4) | |
107 | # define VIP_CNTRL_4_656_ALT (1 << 5) | |
108 | # define VIP_CNTRL_4_TST_656 (1 << 6) | |
109 | # define VIP_CNTRL_4_TST_PAT (1 << 7) | |
110 | #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ | |
111 | # define VIP_CNTRL_5_CKCASE (1 << 0) | |
112 | # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) | |
113 | #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ | |
114 | # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) | |
115 | # define MAT_CONTRL_MAT_BP (1 << 2) | |
116 | #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ | |
117 | #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ | |
118 | #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ | |
119 | #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ | |
120 | #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ | |
121 | #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ | |
122 | #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ | |
123 | #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ | |
124 | #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ | |
125 | #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ | |
126 | #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ | |
127 | #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ | |
128 | #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ | |
129 | #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ | |
130 | #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ | |
131 | #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ | |
132 | #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ | |
133 | #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ | |
134 | #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ | |
135 | #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ | |
136 | #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ | |
137 | #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ | |
138 | #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ | |
139 | #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ | |
140 | #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ | |
141 | #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ | |
142 | #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ | |
143 | #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ | |
144 | #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ | |
145 | #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ | |
146 | #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ | |
147 | #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ | |
148 | #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ | |
149 | #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ | |
150 | # define TBG_CNTRL_0_FRAME_DIS (1 << 5) | |
151 | # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) | |
152 | # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) | |
153 | #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ | |
154 | # define TBG_CNTRL_1_VH_TGL_0 (1 << 0) | |
155 | # define TBG_CNTRL_1_VH_TGL_1 (1 << 1) | |
156 | # define TBG_CNTRL_1_VH_TGL_2 (1 << 2) | |
157 | # define TBG_CNTRL_1_VHX_EXT_DE (1 << 3) | |
158 | # define TBG_CNTRL_1_VHX_EXT_HS (1 << 4) | |
159 | # define TBG_CNTRL_1_VHX_EXT_VS (1 << 5) | |
160 | # define TBG_CNTRL_1_DWIN_DIS (1 << 6) | |
161 | #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ | |
162 | #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ | |
163 | # define HVF_CNTRL_0_SM (1 << 7) | |
164 | # define HVF_CNTRL_0_RWB (1 << 6) | |
165 | # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) | |
166 | # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) | |
167 | #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ | |
168 | # define HVF_CNTRL_1_FOR (1 << 0) | |
169 | # define HVF_CNTRL_1_YUVBLK (1 << 1) | |
170 | # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) | |
171 | # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) | |
172 | # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) | |
173 | #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ | |
174 | ||
175 | ||
176 | /* Page 02h: PLL settings */ | |
177 | #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ | |
178 | # define PLL_SERIAL_1_SRL_FDN (1 << 0) | |
179 | # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) | |
180 | # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) | |
181 | #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ | |
182 | # define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0) | |
183 | # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) | |
184 | #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ | |
185 | # define PLL_SERIAL_3_SRL_CCIR (1 << 0) | |
186 | # define PLL_SERIAL_3_SRL_DE (1 << 2) | |
187 | # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) | |
188 | #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ | |
189 | #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ | |
190 | #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ | |
191 | #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ | |
192 | #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ | |
193 | #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ | |
194 | #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ | |
195 | #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ | |
196 | #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ | |
197 | #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ | |
198 | # define SEL_CLK_SEL_CLK1 (1 << 0) | |
199 | # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) | |
200 | # define SEL_CLK_ENA_SC_CLK (1 << 3) | |
201 | #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ | |
202 | ||
203 | ||
204 | /* Page 09h: EDID Control */ | |
205 | #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ | |
206 | /* next 127 successive registers are the EDID block */ | |
207 | #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ | |
208 | #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ | |
209 | #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ | |
210 | #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ | |
211 | #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ | |
212 | ||
213 | ||
214 | /* Page 10h: information frames and packets */ | |
215 | ||
216 | ||
217 | /* Page 11h: audio settings and content info packets */ | |
218 | #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ | |
219 | # define AIP_CNTRL_0_RST_FIFO (1 << 0) | |
220 | # define AIP_CNTRL_0_SWAP (1 << 1) | |
221 | # define AIP_CNTRL_0_LAYOUT (1 << 2) | |
222 | # define AIP_CNTRL_0_ACR_MAN (1 << 5) | |
223 | # define AIP_CNTRL_0_RST_CTS (1 << 6) | |
224 | #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ | |
225 | # define ENC_CNTRL_RST_ENC (1 << 0) | |
226 | # define ENC_CNTRL_RST_SEL (1 << 1) | |
227 | # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) | |
228 | ||
229 | ||
230 | /* Page 12h: HDCP and OTP */ | |
231 | #define REG_TX3 REG(0x12, 0x9a) /* read/write */ | |
232 | #define REG_TX33 REG(0x12, 0xb8) /* read/write */ | |
233 | # define TX33_HDMI (1 << 1) | |
234 | ||
235 | ||
236 | /* Page 13h: Gamut related metadata packets */ | |
237 | ||
238 | ||
239 | ||
240 | /* CEC registers: (not paged) | |
241 | */ | |
242 | #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ | |
243 | # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) | |
244 | # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) | |
245 | # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) | |
246 | # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) | |
247 | #define REG_CEC_RXSHPDLEV 0xfe /* read */ | |
248 | # define CEC_RXSHPDLEV_RXSENS (1 << 0) | |
249 | # define CEC_RXSHPDLEV_HPD (1 << 1) | |
250 | ||
251 | #define REG_CEC_ENAMODS 0xff /* read/write */ | |
252 | # define CEC_ENAMODS_DIS_FRO (1 << 6) | |
253 | # define CEC_ENAMODS_DIS_CCLK (1 << 5) | |
254 | # define CEC_ENAMODS_EN_RXSENS (1 << 2) | |
255 | # define CEC_ENAMODS_EN_HDMI (1 << 1) | |
256 | # define CEC_ENAMODS_EN_CEC (1 << 0) | |
257 | ||
258 | ||
259 | /* Device versions: */ | |
260 | #define TDA9989N2 0x0101 | |
261 | #define TDA19989 0x0201 | |
262 | #define TDA19989N2 0x0202 | |
263 | #define TDA19988 0x0301 | |
264 | ||
265 | static void | |
266 | cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val) | |
267 | { | |
268 | struct i2c_client *client = to_tda998x_priv(encoder)->cec; | |
269 | uint8_t buf[] = {addr, val}; | |
270 | int ret; | |
271 | ||
272 | ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); | |
273 | if (ret < 0) | |
274 | dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); | |
275 | } | |
276 | ||
277 | static uint8_t | |
278 | cec_read(struct drm_encoder *encoder, uint8_t addr) | |
279 | { | |
280 | struct i2c_client *client = to_tda998x_priv(encoder)->cec; | |
281 | uint8_t val; | |
282 | int ret; | |
283 | ||
284 | ret = i2c_master_send(client, &addr, sizeof(addr)); | |
285 | if (ret < 0) | |
286 | goto fail; | |
287 | ||
288 | ret = i2c_master_recv(client, &val, sizeof(val)); | |
289 | if (ret < 0) | |
290 | goto fail; | |
291 | ||
292 | return val; | |
293 | ||
294 | fail: | |
295 | dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); | |
296 | return 0; | |
297 | } | |
298 | ||
299 | static void | |
300 | set_page(struct drm_encoder *encoder, uint16_t reg) | |
301 | { | |
302 | struct tda998x_priv *priv = to_tda998x_priv(encoder); | |
303 | ||
304 | if (REG2PAGE(reg) != priv->current_page) { | |
305 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); | |
306 | uint8_t buf[] = { | |
307 | REG_CURPAGE, REG2PAGE(reg) | |
308 | }; | |
309 | int ret = i2c_master_send(client, buf, sizeof(buf)); | |
310 | if (ret < 0) | |
311 | dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret); | |
312 | ||
313 | priv->current_page = REG2PAGE(reg); | |
314 | } | |
315 | } | |
316 | ||
317 | static int | |
318 | reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt) | |
319 | { | |
320 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); | |
321 | uint8_t addr = REG2ADDR(reg); | |
322 | int ret; | |
323 | ||
324 | set_page(encoder, reg); | |
325 | ||
326 | ret = i2c_master_send(client, &addr, sizeof(addr)); | |
327 | if (ret < 0) | |
328 | goto fail; | |
329 | ||
330 | ret = i2c_master_recv(client, buf, cnt); | |
331 | if (ret < 0) | |
332 | goto fail; | |
333 | ||
334 | return ret; | |
335 | ||
336 | fail: | |
337 | dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); | |
338 | return ret; | |
339 | } | |
340 | ||
341 | static uint8_t | |
342 | reg_read(struct drm_encoder *encoder, uint16_t reg) | |
343 | { | |
344 | uint8_t val = 0; | |
345 | reg_read_range(encoder, reg, &val, sizeof(val)); | |
346 | return val; | |
347 | } | |
348 | ||
349 | static void | |
350 | reg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val) | |
351 | { | |
352 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); | |
353 | uint8_t buf[] = {REG2ADDR(reg), val}; | |
354 | int ret; | |
355 | ||
356 | set_page(encoder, reg); | |
357 | ||
358 | ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); | |
359 | if (ret < 0) | |
360 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); | |
361 | } | |
362 | ||
363 | static void | |
364 | reg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val) | |
365 | { | |
366 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); | |
367 | uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; | |
368 | int ret; | |
369 | ||
370 | set_page(encoder, reg); | |
371 | ||
372 | ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); | |
373 | if (ret < 0) | |
374 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); | |
375 | } | |
376 | ||
377 | static void | |
378 | reg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val) | |
379 | { | |
380 | reg_write(encoder, reg, reg_read(encoder, reg) | val); | |
381 | } | |
382 | ||
383 | static void | |
384 | reg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val) | |
385 | { | |
386 | reg_write(encoder, reg, reg_read(encoder, reg) & ~val); | |
387 | } | |
388 | ||
389 | static void | |
390 | tda998x_reset(struct drm_encoder *encoder) | |
391 | { | |
392 | /* reset audio and i2c master: */ | |
393 | reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); | |
394 | msleep(50); | |
395 | reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); | |
396 | msleep(50); | |
397 | ||
398 | /* reset transmitter: */ | |
399 | reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); | |
400 | reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); | |
401 | ||
402 | /* PLL registers common configuration */ | |
403 | reg_write(encoder, REG_PLL_SERIAL_1, 0x00); | |
404 | reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); | |
405 | reg_write(encoder, REG_PLL_SERIAL_3, 0x00); | |
406 | reg_write(encoder, REG_SERIALIZER, 0x00); | |
407 | reg_write(encoder, REG_BUFFER_OUT, 0x00); | |
408 | reg_write(encoder, REG_PLL_SCG1, 0x00); | |
409 | reg_write(encoder, REG_AUDIO_DIV, 0x03); | |
410 | reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); | |
411 | reg_write(encoder, REG_PLL_SCGN1, 0xfa); | |
412 | reg_write(encoder, REG_PLL_SCGN2, 0x00); | |
413 | reg_write(encoder, REG_PLL_SCGR1, 0x5b); | |
414 | reg_write(encoder, REG_PLL_SCGR2, 0x00); | |
415 | reg_write(encoder, REG_PLL_SCG2, 0x10); | |
416 | } | |
417 | ||
418 | /* DRM encoder functions */ | |
419 | ||
420 | static void | |
421 | tda998x_encoder_set_config(struct drm_encoder *encoder, void *params) | |
422 | { | |
423 | } | |
424 | ||
425 | static void | |
426 | tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) | |
427 | { | |
428 | struct tda998x_priv *priv = to_tda998x_priv(encoder); | |
429 | ||
430 | /* we only care about on or off: */ | |
431 | if (mode != DRM_MODE_DPMS_ON) | |
432 | mode = DRM_MODE_DPMS_OFF; | |
433 | ||
434 | if (mode == priv->dpms) | |
435 | return; | |
436 | ||
437 | switch (mode) { | |
438 | case DRM_MODE_DPMS_ON: | |
439 | /* enable audio and video ports */ | |
440 | reg_write(encoder, REG_ENA_AP, 0xff); | |
441 | reg_write(encoder, REG_ENA_VP_0, 0xff); | |
442 | reg_write(encoder, REG_ENA_VP_1, 0xff); | |
443 | reg_write(encoder, REG_ENA_VP_2, 0xff); | |
444 | /* set muxing after enabling ports: */ | |
445 | reg_write(encoder, REG_VIP_CNTRL_0, | |
446 | VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3)); | |
447 | reg_write(encoder, REG_VIP_CNTRL_1, | |
448 | VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1)); | |
449 | reg_write(encoder, REG_VIP_CNTRL_2, | |
450 | VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5)); | |
451 | break; | |
452 | case DRM_MODE_DPMS_OFF: | |
453 | /* disable audio and video ports */ | |
454 | reg_write(encoder, REG_ENA_AP, 0x00); | |
455 | reg_write(encoder, REG_ENA_VP_0, 0x00); | |
456 | reg_write(encoder, REG_ENA_VP_1, 0x00); | |
457 | reg_write(encoder, REG_ENA_VP_2, 0x00); | |
458 | break; | |
459 | } | |
460 | ||
461 | priv->dpms = mode; | |
462 | } | |
463 | ||
464 | static void | |
465 | tda998x_encoder_save(struct drm_encoder *encoder) | |
466 | { | |
467 | DBG(""); | |
468 | } | |
469 | ||
470 | static void | |
471 | tda998x_encoder_restore(struct drm_encoder *encoder) | |
472 | { | |
473 | DBG(""); | |
474 | } | |
475 | ||
476 | static bool | |
477 | tda998x_encoder_mode_fixup(struct drm_encoder *encoder, | |
478 | const struct drm_display_mode *mode, | |
479 | struct drm_display_mode *adjusted_mode) | |
480 | { | |
481 | return true; | |
482 | } | |
483 | ||
484 | static int | |
485 | tda998x_encoder_mode_valid(struct drm_encoder *encoder, | |
486 | struct drm_display_mode *mode) | |
487 | { | |
488 | return MODE_OK; | |
489 | } | |
490 | ||
491 | static void | |
492 | tda998x_encoder_mode_set(struct drm_encoder *encoder, | |
493 | struct drm_display_mode *mode, | |
494 | struct drm_display_mode *adjusted_mode) | |
495 | { | |
496 | struct tda998x_priv *priv = to_tda998x_priv(encoder); | |
497 | uint16_t hs_start, hs_end, line_start, line_end; | |
498 | uint16_t vwin_start, vwin_end, de_start, de_end; | |
499 | uint16_t ref_pix, ref_line, pix_start2; | |
500 | uint8_t reg, div, rep; | |
501 | ||
502 | hs_start = mode->hsync_start - mode->hdisplay; | |
503 | hs_end = mode->hsync_end - mode->hdisplay; | |
504 | line_start = 1; | |
505 | line_end = 1 + mode->vsync_end - mode->vsync_start; | |
506 | vwin_start = mode->vtotal - mode->vsync_start; | |
507 | vwin_end = vwin_start + mode->vdisplay; | |
508 | de_start = mode->htotal - mode->hdisplay; | |
509 | de_end = mode->htotal; | |
510 | ||
511 | pix_start2 = 0; | |
512 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
513 | pix_start2 = (mode->htotal / 2) + hs_start; | |
514 | ||
515 | /* TODO how is this value calculated? It is 2 for all common | |
516 | * formats in the tables in out of tree nxp driver (assuming | |
517 | * I've properly deciphered their byzantine table system) | |
518 | */ | |
519 | ref_line = 2; | |
520 | ||
521 | /* this might changes for other color formats from the CRTC: */ | |
522 | ref_pix = 3 + hs_start; | |
523 | ||
524 | div = 148500 / mode->clock; | |
525 | ||
526 | DBG("clock=%d, div=%u", mode->clock, div); | |
527 | DBG("hs_start=%u, hs_end=%u, line_start=%u, line_end=%u", | |
528 | hs_start, hs_end, line_start, line_end); | |
529 | DBG("vwin_start=%u, vwin_end=%u, de_start=%u, de_end=%u", | |
530 | vwin_start, vwin_end, de_start, de_end); | |
531 | DBG("ref_line=%u, ref_pix=%u, pix_start2=%u", | |
532 | ref_line, ref_pix, pix_start2); | |
533 | ||
534 | /* mute the audio FIFO: */ | |
535 | reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); | |
536 | ||
537 | /* set HDMI HDCP mode off: */ | |
538 | reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); | |
539 | reg_clear(encoder, REG_TX33, TX33_HDMI); | |
540 | ||
541 | reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); | |
542 | /* no pre-filter or interpolator: */ | |
543 | reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | | |
544 | HVF_CNTRL_0_INTPOL(0)); | |
545 | reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); | |
546 | reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | | |
547 | VIP_CNTRL_4_BLC(0)); | |
548 | reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); | |
549 | ||
550 | reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); | |
551 | reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); | |
552 | reg_write(encoder, REG_SERIALIZER, 0); | |
553 | reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); | |
554 | ||
555 | /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ | |
556 | rep = 0; | |
557 | reg_write(encoder, REG_RPT_CNTRL, 0); | |
558 | reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | | |
559 | SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); | |
560 | ||
561 | reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | | |
562 | PLL_SERIAL_2_SRL_PR(rep)); | |
563 | ||
564 | reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, pix_start2); | |
565 | reg_write16(encoder, REG_VS_PIX_END_2_MSB, pix_start2); | |
566 | ||
567 | /* set color matrix bypass flag: */ | |
568 | reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP); | |
569 | ||
570 | /* set BIAS tmds value: */ | |
571 | reg_write(encoder, REG_ANA_GENERAL, 0x09); | |
572 | ||
573 | reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); | |
574 | ||
575 | reg_write(encoder, REG_VIP_CNTRL_3, 0); | |
576 | reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS); | |
577 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
578 | reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL); | |
579 | ||
580 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
581 | reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL); | |
582 | ||
583 | reg_write(encoder, REG_VIDFORMAT, 0x00); | |
584 | reg_write16(encoder, REG_NPIX_MSB, mode->hdisplay - 1); | |
585 | reg_write16(encoder, REG_NLINE_MSB, mode->vdisplay - 1); | |
586 | reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, line_start); | |
587 | reg_write16(encoder, REG_VS_LINE_END_1_MSB, line_end); | |
588 | reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, hs_start); | |
589 | reg_write16(encoder, REG_VS_PIX_END_1_MSB, hs_start); | |
590 | reg_write16(encoder, REG_HS_PIX_START_MSB, hs_start); | |
591 | reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_end); | |
592 | reg_write16(encoder, REG_VWIN_START_1_MSB, vwin_start); | |
593 | reg_write16(encoder, REG_VWIN_END_1_MSB, vwin_end); | |
594 | reg_write16(encoder, REG_DE_START_MSB, de_start); | |
595 | reg_write16(encoder, REG_DE_STOP_MSB, de_end); | |
596 | ||
597 | if (priv->rev == TDA19988) { | |
598 | /* let incoming pixels fill the active space (if any) */ | |
599 | reg_write(encoder, REG_ENABLE_SPACE, 0x01); | |
600 | } | |
601 | ||
602 | reg_write16(encoder, REG_REFPIX_MSB, ref_pix); | |
603 | reg_write16(encoder, REG_REFLINE_MSB, ref_line); | |
604 | ||
605 | reg = TBG_CNTRL_1_VHX_EXT_DE | | |
606 | TBG_CNTRL_1_VHX_EXT_HS | | |
607 | TBG_CNTRL_1_VHX_EXT_VS | | |
608 | TBG_CNTRL_1_DWIN_DIS | /* HDCP off */ | |
609 | TBG_CNTRL_1_VH_TGL_2; | |
610 | if (mode->flags & (DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC)) | |
611 | reg |= TBG_CNTRL_1_VH_TGL_0; | |
612 | reg_set(encoder, REG_TBG_CNTRL_1, reg); | |
613 | ||
614 | /* must be last register set: */ | |
615 | reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); | |
616 | } | |
617 | ||
618 | static enum drm_connector_status | |
619 | tda998x_encoder_detect(struct drm_encoder *encoder, | |
620 | struct drm_connector *connector) | |
621 | { | |
622 | uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV); | |
623 | return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : | |
624 | connector_status_disconnected; | |
625 | } | |
626 | ||
627 | static int | |
628 | read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk) | |
629 | { | |
630 | uint8_t offset, segptr; | |
631 | int ret, i; | |
632 | ||
633 | /* enable EDID read irq: */ | |
634 | reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); | |
635 | ||
636 | offset = (blk & 1) ? 128 : 0; | |
637 | segptr = blk / 2; | |
638 | ||
639 | reg_write(encoder, REG_DDC_ADDR, 0xa0); | |
640 | reg_write(encoder, REG_DDC_OFFS, offset); | |
641 | reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60); | |
642 | reg_write(encoder, REG_DDC_SEGM, segptr); | |
643 | ||
644 | /* enable reading EDID: */ | |
645 | reg_write(encoder, REG_EDID_CTRL, 0x1); | |
646 | ||
647 | /* flag must be cleared by sw: */ | |
648 | reg_write(encoder, REG_EDID_CTRL, 0x0); | |
649 | ||
650 | /* wait for block read to complete: */ | |
651 | for (i = 100; i > 0; i--) { | |
652 | uint8_t val = reg_read(encoder, REG_INT_FLAGS_2); | |
653 | if (val & INT_FLAGS_2_EDID_BLK_RD) | |
654 | break; | |
655 | msleep(1); | |
656 | } | |
657 | ||
658 | if (i == 0) | |
659 | return -ETIMEDOUT; | |
660 | ||
661 | ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH); | |
662 | if (ret != EDID_LENGTH) { | |
663 | dev_err(encoder->dev->dev, "failed to read edid block %d: %d", | |
664 | blk, ret); | |
665 | return ret; | |
666 | } | |
667 | ||
668 | reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
673 | static uint8_t * | |
674 | do_get_edid(struct drm_encoder *encoder) | |
675 | { | |
676 | int j = 0, valid_extensions = 0; | |
677 | uint8_t *block, *new; | |
678 | bool print_bad_edid = drm_debug & DRM_UT_KMS; | |
679 | ||
680 | if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) | |
681 | return NULL; | |
682 | ||
683 | /* base block fetch */ | |
684 | if (read_edid_block(encoder, block, 0)) | |
685 | goto fail; | |
686 | ||
687 | if (!drm_edid_block_valid(block, 0, print_bad_edid)) | |
688 | goto fail; | |
689 | ||
690 | /* if there's no extensions, we're done */ | |
691 | if (block[0x7e] == 0) | |
692 | return block; | |
693 | ||
694 | new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); | |
695 | if (!new) | |
696 | goto fail; | |
697 | block = new; | |
698 | ||
699 | for (j = 1; j <= block[0x7e]; j++) { | |
700 | uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; | |
701 | if (read_edid_block(encoder, ext_block, j)) | |
702 | goto fail; | |
703 | ||
704 | if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) | |
705 | goto fail; | |
706 | ||
707 | valid_extensions++; | |
708 | } | |
709 | ||
710 | if (valid_extensions != block[0x7e]) { | |
711 | block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; | |
712 | block[0x7e] = valid_extensions; | |
713 | new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); | |
714 | if (!new) | |
715 | goto fail; | |
716 | block = new; | |
717 | } | |
718 | ||
719 | return block; | |
720 | ||
721 | fail: | |
722 | dev_warn(encoder->dev->dev, "failed to read EDID\n"); | |
723 | kfree(block); | |
724 | return NULL; | |
725 | } | |
726 | ||
727 | static int | |
728 | tda998x_encoder_get_modes(struct drm_encoder *encoder, | |
729 | struct drm_connector *connector) | |
730 | { | |
731 | struct edid *edid = (struct edid *)do_get_edid(encoder); | |
732 | int n = 0; | |
733 | ||
734 | if (edid) { | |
735 | drm_mode_connector_update_edid_property(connector, edid); | |
736 | n = drm_add_edid_modes(connector, edid); | |
737 | kfree(edid); | |
738 | } | |
739 | ||
740 | return n; | |
741 | } | |
742 | ||
743 | static int | |
744 | tda998x_encoder_create_resources(struct drm_encoder *encoder, | |
745 | struct drm_connector *connector) | |
746 | { | |
747 | DBG(""); | |
748 | return 0; | |
749 | } | |
750 | ||
751 | static int | |
752 | tda998x_encoder_set_property(struct drm_encoder *encoder, | |
753 | struct drm_connector *connector, | |
754 | struct drm_property *property, | |
755 | uint64_t val) | |
756 | { | |
757 | DBG(""); | |
758 | return 0; | |
759 | } | |
760 | ||
761 | static void | |
762 | tda998x_encoder_destroy(struct drm_encoder *encoder) | |
763 | { | |
764 | struct tda998x_priv *priv = to_tda998x_priv(encoder); | |
765 | drm_i2c_encoder_destroy(encoder); | |
766 | kfree(priv); | |
767 | } | |
768 | ||
769 | static struct drm_encoder_slave_funcs tda998x_encoder_funcs = { | |
770 | .set_config = tda998x_encoder_set_config, | |
771 | .destroy = tda998x_encoder_destroy, | |
772 | .dpms = tda998x_encoder_dpms, | |
773 | .save = tda998x_encoder_save, | |
774 | .restore = tda998x_encoder_restore, | |
775 | .mode_fixup = tda998x_encoder_mode_fixup, | |
776 | .mode_valid = tda998x_encoder_mode_valid, | |
777 | .mode_set = tda998x_encoder_mode_set, | |
778 | .detect = tda998x_encoder_detect, | |
779 | .get_modes = tda998x_encoder_get_modes, | |
780 | .create_resources = tda998x_encoder_create_resources, | |
781 | .set_property = tda998x_encoder_set_property, | |
782 | }; | |
783 | ||
784 | /* I2C driver functions */ | |
785 | ||
786 | static int | |
787 | tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) | |
788 | { | |
789 | return 0; | |
790 | } | |
791 | ||
792 | static int | |
793 | tda998x_remove(struct i2c_client *client) | |
794 | { | |
795 | return 0; | |
796 | } | |
797 | ||
798 | static int | |
799 | tda998x_encoder_init(struct i2c_client *client, | |
800 | struct drm_device *dev, | |
801 | struct drm_encoder_slave *encoder_slave) | |
802 | { | |
803 | struct drm_encoder *encoder = &encoder_slave->base; | |
804 | struct tda998x_priv *priv; | |
805 | ||
806 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
807 | if (!priv) | |
808 | return -ENOMEM; | |
809 | ||
810 | priv->current_page = 0; | |
811 | priv->cec = i2c_new_dummy(client->adapter, 0x34); | |
812 | priv->dpms = DRM_MODE_DPMS_OFF; | |
813 | ||
814 | encoder_slave->slave_priv = priv; | |
815 | encoder_slave->slave_funcs = &tda998x_encoder_funcs; | |
816 | ||
817 | /* wake up the device: */ | |
818 | cec_write(encoder, REG_CEC_ENAMODS, | |
819 | CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); | |
820 | ||
821 | tda998x_reset(encoder); | |
822 | ||
823 | /* read version: */ | |
824 | priv->rev = reg_read(encoder, REG_VERSION_LSB) | | |
825 | reg_read(encoder, REG_VERSION_MSB) << 8; | |
826 | ||
827 | /* mask off feature bits: */ | |
828 | priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ | |
829 | ||
830 | switch (priv->rev) { | |
831 | case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break; | |
832 | case TDA19989: dev_info(dev->dev, "found TDA19989"); break; | |
833 | case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break; | |
834 | case TDA19988: dev_info(dev->dev, "found TDA19988"); break; | |
835 | default: | |
836 | DBG("found unsupported device: %04x", priv->rev); | |
837 | goto fail; | |
838 | } | |
839 | ||
840 | /* after reset, enable DDC: */ | |
841 | reg_write(encoder, REG_DDC_DISABLE, 0x00); | |
842 | ||
843 | /* set clock on DDC channel: */ | |
844 | reg_write(encoder, REG_TX3, 39); | |
845 | ||
846 | /* if necessary, disable multi-master: */ | |
847 | if (priv->rev == TDA19989) | |
848 | reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM); | |
849 | ||
850 | cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL, | |
851 | CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); | |
852 | ||
853 | return 0; | |
854 | ||
855 | fail: | |
856 | /* if encoder_init fails, the encoder slave is never registered, | |
857 | * so cleanup here: | |
858 | */ | |
859 | if (priv->cec) | |
860 | i2c_unregister_device(priv->cec); | |
861 | kfree(priv); | |
862 | encoder_slave->slave_priv = NULL; | |
863 | encoder_slave->slave_funcs = NULL; | |
864 | return -ENXIO; | |
865 | } | |
866 | ||
867 | static struct i2c_device_id tda998x_ids[] = { | |
868 | { "tda998x", 0 }, | |
869 | { } | |
870 | }; | |
871 | MODULE_DEVICE_TABLE(i2c, tda998x_ids); | |
872 | ||
873 | static struct drm_i2c_encoder_driver tda998x_driver = { | |
874 | .i2c_driver = { | |
875 | .probe = tda998x_probe, | |
876 | .remove = tda998x_remove, | |
877 | .driver = { | |
878 | .name = "tda998x", | |
879 | }, | |
880 | .id_table = tda998x_ids, | |
881 | }, | |
882 | .encoder_init = tda998x_encoder_init, | |
883 | }; | |
884 | ||
885 | /* Module initialization */ | |
886 | ||
887 | static int __init | |
888 | tda998x_init(void) | |
889 | { | |
890 | DBG(""); | |
891 | return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); | |
892 | } | |
893 | ||
894 | static void __exit | |
895 | tda998x_exit(void) | |
896 | { | |
897 | DBG(""); | |
898 | drm_i2c_encoder_unregister(&tda998x_driver); | |
899 | } | |
900 | ||
901 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); | |
902 | MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); | |
903 | MODULE_LICENSE("GPL"); | |
904 | ||
905 | module_init(tda998x_init); | |
906 | module_exit(tda998x_exit); |