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79e53945 JB |
1 | /* |
2 | * Copyright © 2006 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "dvo.h" | |
29 | ||
30 | #define CH7017_TV_DISPLAY_MODE 0x00 | |
31 | #define CH7017_FLICKER_FILTER 0x01 | |
32 | #define CH7017_VIDEO_BANDWIDTH 0x02 | |
33 | #define CH7017_TEXT_ENHANCEMENT 0x03 | |
34 | #define CH7017_START_ACTIVE_VIDEO 0x04 | |
35 | #define CH7017_HORIZONTAL_POSITION 0x05 | |
36 | #define CH7017_VERTICAL_POSITION 0x06 | |
37 | #define CH7017_BLACK_LEVEL 0x07 | |
38 | #define CH7017_CONTRAST_ENHANCEMENT 0x08 | |
39 | #define CH7017_TV_PLL 0x09 | |
40 | #define CH7017_TV_PLL_M 0x0a | |
41 | #define CH7017_TV_PLL_N 0x0b | |
42 | #define CH7017_SUB_CARRIER_0 0x0c | |
43 | #define CH7017_CIV_CONTROL 0x10 | |
44 | #define CH7017_CIV_0 0x11 | |
45 | #define CH7017_CHROMA_BOOST 0x14 | |
46 | #define CH7017_CLOCK_MODE 0x1c | |
47 | #define CH7017_INPUT_CLOCK 0x1d | |
48 | #define CH7017_GPIO_CONTROL 0x1e | |
49 | #define CH7017_INPUT_DATA_FORMAT 0x1f | |
50 | #define CH7017_CONNECTION_DETECT 0x20 | |
51 | #define CH7017_DAC_CONTROL 0x21 | |
52 | #define CH7017_BUFFERED_CLOCK_OUTPUT 0x22 | |
53 | #define CH7017_DEFEAT_VSYNC 0x47 | |
54 | #define CH7017_TEST_PATTERN 0x48 | |
55 | ||
56 | #define CH7017_POWER_MANAGEMENT 0x49 | |
57 | /** Enables the TV output path. */ | |
58 | #define CH7017_TV_EN (1 << 0) | |
59 | #define CH7017_DAC0_POWER_DOWN (1 << 1) | |
60 | #define CH7017_DAC1_POWER_DOWN (1 << 2) | |
61 | #define CH7017_DAC2_POWER_DOWN (1 << 3) | |
62 | #define CH7017_DAC3_POWER_DOWN (1 << 4) | |
63 | /** Powers down the TV out block, and DAC0-3 */ | |
64 | #define CH7017_TV_POWER_DOWN_EN (1 << 5) | |
65 | ||
66 | #define CH7017_VERSION_ID 0x4a | |
67 | ||
68 | #define CH7017_DEVICE_ID 0x4b | |
69 | #define CH7017_DEVICE_ID_VALUE 0x1b | |
70 | #define CH7018_DEVICE_ID_VALUE 0x1a | |
71 | #define CH7019_DEVICE_ID_VALUE 0x19 | |
72 | ||
73 | #define CH7017_XCLK_D2_ADJUST 0x53 | |
74 | #define CH7017_UP_SCALER_COEFF_0 0x55 | |
75 | #define CH7017_UP_SCALER_COEFF_1 0x56 | |
76 | #define CH7017_UP_SCALER_COEFF_2 0x57 | |
77 | #define CH7017_UP_SCALER_COEFF_3 0x58 | |
78 | #define CH7017_UP_SCALER_COEFF_4 0x59 | |
79 | #define CH7017_UP_SCALER_VERTICAL_INC_0 0x5a | |
80 | #define CH7017_UP_SCALER_VERTICAL_INC_1 0x5b | |
81 | #define CH7017_GPIO_INVERT 0x5c | |
82 | #define CH7017_UP_SCALER_HORIZONTAL_INC_0 0x5d | |
83 | #define CH7017_UP_SCALER_HORIZONTAL_INC_1 0x5e | |
84 | ||
85 | #define CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT 0x5f | |
86 | /**< Low bits of horizontal active pixel input */ | |
87 | ||
88 | #define CH7017_ACTIVE_INPUT_LINE_OUTPUT 0x60 | |
89 | /** High bits of horizontal active pixel input */ | |
90 | #define CH7017_LVDS_HAP_INPUT_MASK (0x7 << 0) | |
91 | /** High bits of vertical active line output */ | |
92 | #define CH7017_LVDS_VAL_HIGH_MASK (0x7 << 3) | |
93 | ||
94 | #define CH7017_VERTICAL_ACTIVE_LINE_OUTPUT 0x61 | |
95 | /**< Low bits of vertical active line output */ | |
96 | ||
97 | #define CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT 0x62 | |
98 | /**< Low bits of horizontal active pixel output */ | |
99 | ||
100 | #define CH7017_LVDS_POWER_DOWN 0x63 | |
101 | /** High bits of horizontal active pixel output */ | |
102 | #define CH7017_LVDS_HAP_HIGH_MASK (0x7 << 0) | |
103 | /** Enables the LVDS power down state transition */ | |
104 | #define CH7017_LVDS_POWER_DOWN_EN (1 << 6) | |
105 | /** Enables the LVDS upscaler */ | |
106 | #define CH7017_LVDS_UPSCALER_EN (1 << 7) | |
107 | #define CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED 0x08 | |
108 | ||
109 | #define CH7017_LVDS_ENCODING 0x64 | |
110 | #define CH7017_LVDS_DITHER_2D (1 << 2) | |
111 | #define CH7017_LVDS_DITHER_DIS (1 << 3) | |
112 | #define CH7017_LVDS_DUAL_CHANNEL_EN (1 << 4) | |
113 | #define CH7017_LVDS_24_BIT (1 << 5) | |
114 | ||
115 | #define CH7017_LVDS_ENCODING_2 0x65 | |
116 | ||
117 | #define CH7017_LVDS_PLL_CONTROL 0x66 | |
118 | /** Enables the LVDS panel output path */ | |
119 | #define CH7017_LVDS_PANEN (1 << 0) | |
120 | /** Enables the LVDS panel backlight */ | |
121 | #define CH7017_LVDS_BKLEN (1 << 3) | |
122 | ||
123 | #define CH7017_POWER_SEQUENCING_T1 0x67 | |
124 | #define CH7017_POWER_SEQUENCING_T2 0x68 | |
125 | #define CH7017_POWER_SEQUENCING_T3 0x69 | |
126 | #define CH7017_POWER_SEQUENCING_T4 0x6a | |
127 | #define CH7017_POWER_SEQUENCING_T5 0x6b | |
128 | #define CH7017_GPIO_DRIVER_TYPE 0x6c | |
129 | #define CH7017_GPIO_DATA 0x6d | |
130 | #define CH7017_GPIO_DIRECTION_CONTROL 0x6e | |
131 | ||
132 | #define CH7017_LVDS_PLL_FEEDBACK_DIV 0x71 | |
133 | # define CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT 4 | |
134 | # define CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT 0 | |
135 | # define CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED 0x80 | |
136 | ||
137 | #define CH7017_LVDS_PLL_VCO_CONTROL 0x72 | |
138 | # define CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED 0x80 | |
139 | # define CH7017_LVDS_PLL_VCO_SHIFT 4 | |
140 | # define CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT 0 | |
141 | ||
142 | #define CH7017_OUTPUTS_ENABLE 0x73 | |
143 | # define CH7017_CHARGE_PUMP_LOW 0x0 | |
144 | # define CH7017_CHARGE_PUMP_HIGH 0x3 | |
145 | # define CH7017_LVDS_CHANNEL_A (1 << 3) | |
146 | # define CH7017_LVDS_CHANNEL_B (1 << 4) | |
147 | # define CH7017_TV_DAC_A (1 << 5) | |
148 | # define CH7017_TV_DAC_B (1 << 6) | |
149 | # define CH7017_DDC_SELECT_DC2 (1 << 7) | |
150 | ||
151 | #define CH7017_LVDS_OUTPUT_AMPLITUDE 0x74 | |
152 | #define CH7017_LVDS_PLL_EMI_REDUCTION 0x75 | |
153 | #define CH7017_LVDS_POWER_DOWN_FLICKER 0x76 | |
154 | ||
155 | #define CH7017_LVDS_CONTROL_2 0x78 | |
156 | # define CH7017_LOOP_FILTER_SHIFT 5 | |
157 | # define CH7017_PHASE_DETECTOR_SHIFT 0 | |
158 | ||
159 | #define CH7017_BANG_LIMIT_CONTROL 0x7f | |
160 | ||
161 | struct ch7017_priv { | |
6443170f | 162 | uint8_t dummy; |
79e53945 JB |
163 | }; |
164 | ||
165 | static void ch7017_dump_regs(struct intel_dvo_device *dvo); | |
166 | static void ch7017_dpms(struct intel_dvo_device *dvo, int mode); | |
167 | ||
168 | static bool ch7017_read(struct intel_dvo_device *dvo, int addr, uint8_t *val) | |
169 | { | |
f9c10a9b | 170 | struct i2c_adapter *adapter = dvo->i2c_bus; |
79e53945 JB |
171 | u8 out_buf[2]; |
172 | u8 in_buf[2]; | |
173 | ||
174 | struct i2c_msg msgs[] = { | |
175 | { | |
f9c10a9b | 176 | .addr = dvo->slave_addr, |
79e53945 JB |
177 | .flags = 0, |
178 | .len = 1, | |
179 | .buf = out_buf, | |
180 | }, | |
181 | { | |
f9c10a9b | 182 | .addr = dvo->slave_addr, |
79e53945 JB |
183 | .flags = I2C_M_RD, |
184 | .len = 1, | |
185 | .buf = in_buf, | |
186 | } | |
187 | }; | |
188 | ||
189 | out_buf[0] = addr; | |
190 | out_buf[1] = 0; | |
191 | ||
f899fc64 | 192 | if (i2c_transfer(adapter, msgs, 2) == 2) { |
79e53945 JB |
193 | *val= in_buf[0]; |
194 | return true; | |
195 | }; | |
196 | ||
197 | return false; | |
198 | } | |
199 | ||
200 | static bool ch7017_write(struct intel_dvo_device *dvo, int addr, uint8_t val) | |
201 | { | |
f9c10a9b | 202 | struct i2c_adapter *adapter = dvo->i2c_bus; |
79e53945 JB |
203 | uint8_t out_buf[2]; |
204 | struct i2c_msg msg = { | |
f9c10a9b | 205 | .addr = dvo->slave_addr, |
79e53945 JB |
206 | .flags = 0, |
207 | .len = 2, | |
208 | .buf = out_buf, | |
209 | }; | |
210 | ||
211 | out_buf[0] = addr; | |
212 | out_buf[1] = val; | |
213 | ||
f899fc64 | 214 | if (i2c_transfer(adapter, &msg, 1) == 1) |
79e53945 JB |
215 | return true; |
216 | ||
217 | return false; | |
218 | } | |
219 | ||
220 | /** Probes for a CH7017 on the given bus and slave address. */ | |
221 | static bool ch7017_init(struct intel_dvo_device *dvo, | |
f9c10a9b | 222 | struct i2c_adapter *adapter) |
79e53945 JB |
223 | { |
224 | struct ch7017_priv *priv; | |
225 | uint8_t val; | |
226 | ||
227 | priv = kzalloc(sizeof(struct ch7017_priv), GFP_KERNEL); | |
228 | if (priv == NULL) | |
229 | return false; | |
230 | ||
f9c10a9b | 231 | dvo->i2c_bus = adapter; |
79e53945 JB |
232 | dvo->dev_priv = priv; |
233 | ||
234 | if (!ch7017_read(dvo, CH7017_DEVICE_ID, &val)) | |
235 | goto fail; | |
236 | ||
237 | if (val != CH7017_DEVICE_ID_VALUE && | |
238 | val != CH7018_DEVICE_ID_VALUE && | |
239 | val != CH7019_DEVICE_ID_VALUE) { | |
d0c3b04a ZY |
240 | DRM_DEBUG_KMS("ch701x not detected, got %d: from %s " |
241 | "Slave %d.\n", | |
f899fc64 | 242 | val, adapter->name,dvo->slave_addr); |
79e53945 JB |
243 | goto fail; |
244 | } | |
245 | ||
246 | return true; | |
247 | fail: | |
248 | kfree(priv); | |
249 | return false; | |
250 | } | |
251 | ||
252 | static enum drm_connector_status ch7017_detect(struct intel_dvo_device *dvo) | |
253 | { | |
254 | return connector_status_unknown; | |
255 | } | |
256 | ||
257 | static enum drm_mode_status ch7017_mode_valid(struct intel_dvo_device *dvo, | |
258 | struct drm_display_mode *mode) | |
259 | { | |
260 | if (mode->clock > 160000) | |
261 | return MODE_CLOCK_HIGH; | |
262 | ||
263 | return MODE_OK; | |
264 | } | |
265 | ||
266 | static void ch7017_mode_set(struct intel_dvo_device *dvo, | |
267 | struct drm_display_mode *mode, | |
268 | struct drm_display_mode *adjusted_mode) | |
269 | { | |
270 | uint8_t lvds_pll_feedback_div, lvds_pll_vco_control; | |
271 | uint8_t outputs_enable, lvds_control_2, lvds_power_down; | |
272 | uint8_t horizontal_active_pixel_input; | |
273 | uint8_t horizontal_active_pixel_output, vertical_active_line_output; | |
274 | uint8_t active_input_line_output; | |
275 | ||
d0c3b04a | 276 | DRM_DEBUG_KMS("Registers before mode setting\n"); |
79e53945 JB |
277 | ch7017_dump_regs(dvo); |
278 | ||
279 | /* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/ | |
280 | if (mode->clock < 100000) { | |
281 | outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_LOW; | |
282 | lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED | | |
283 | (2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) | | |
284 | (13 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT); | |
285 | lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED | | |
286 | (2 << CH7017_LVDS_PLL_VCO_SHIFT) | | |
287 | (3 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT); | |
288 | lvds_control_2 = (1 << CH7017_LOOP_FILTER_SHIFT) | | |
289 | (0 << CH7017_PHASE_DETECTOR_SHIFT); | |
290 | } else { | |
291 | outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_HIGH; | |
292 | lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED | | |
293 | (2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) | | |
294 | (3 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT); | |
295 | lvds_pll_feedback_div = 35; | |
296 | lvds_control_2 = (3 << CH7017_LOOP_FILTER_SHIFT) | | |
297 | (0 << CH7017_PHASE_DETECTOR_SHIFT); | |
298 | if (1) { /* XXX: dual channel panel detection. Assume yes for now. */ | |
299 | outputs_enable |= CH7017_LVDS_CHANNEL_B; | |
300 | lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED | | |
301 | (2 << CH7017_LVDS_PLL_VCO_SHIFT) | | |
302 | (13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT); | |
303 | } else { | |
304 | lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED | | |
305 | (1 << CH7017_LVDS_PLL_VCO_SHIFT) | | |
306 | (13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT); | |
307 | } | |
308 | } | |
309 | ||
310 | horizontal_active_pixel_input = mode->hdisplay & 0x00ff; | |
311 | ||
312 | vertical_active_line_output = mode->vdisplay & 0x00ff; | |
313 | horizontal_active_pixel_output = mode->hdisplay & 0x00ff; | |
314 | ||
315 | active_input_line_output = ((mode->hdisplay & 0x0700) >> 8) | | |
316 | (((mode->vdisplay & 0x0700) >> 8) << 3); | |
317 | ||
318 | lvds_power_down = CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED | | |
319 | (mode->hdisplay & 0x0700) >> 8; | |
320 | ||
321 | ch7017_dpms(dvo, DRM_MODE_DPMS_OFF); | |
322 | ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT, | |
323 | horizontal_active_pixel_input); | |
324 | ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT, | |
325 | horizontal_active_pixel_output); | |
326 | ch7017_write(dvo, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT, | |
327 | vertical_active_line_output); | |
328 | ch7017_write(dvo, CH7017_ACTIVE_INPUT_LINE_OUTPUT, | |
329 | active_input_line_output); | |
330 | ch7017_write(dvo, CH7017_LVDS_PLL_VCO_CONTROL, lvds_pll_vco_control); | |
331 | ch7017_write(dvo, CH7017_LVDS_PLL_FEEDBACK_DIV, lvds_pll_feedback_div); | |
332 | ch7017_write(dvo, CH7017_LVDS_CONTROL_2, lvds_control_2); | |
333 | ch7017_write(dvo, CH7017_OUTPUTS_ENABLE, outputs_enable); | |
334 | ||
335 | /* Turn the LVDS back on with new settings. */ | |
336 | ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down); | |
337 | ||
d0c3b04a | 338 | DRM_DEBUG_KMS("Registers after mode setting\n"); |
79e53945 JB |
339 | ch7017_dump_regs(dvo); |
340 | } | |
341 | ||
342 | /* set the CH7017 power state */ | |
343 | static void ch7017_dpms(struct intel_dvo_device *dvo, int mode) | |
344 | { | |
345 | uint8_t val; | |
346 | ||
347 | ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val); | |
348 | ||
349 | /* Turn off TV/VGA, and never turn it on since we don't support it. */ | |
350 | ch7017_write(dvo, CH7017_POWER_MANAGEMENT, | |
351 | CH7017_DAC0_POWER_DOWN | | |
352 | CH7017_DAC1_POWER_DOWN | | |
353 | CH7017_DAC2_POWER_DOWN | | |
354 | CH7017_DAC3_POWER_DOWN | | |
355 | CH7017_TV_POWER_DOWN_EN); | |
356 | ||
357 | if (mode == DRM_MODE_DPMS_ON) { | |
358 | /* Turn on the LVDS */ | |
359 | ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, | |
360 | val & ~CH7017_LVDS_POWER_DOWN_EN); | |
361 | } else { | |
362 | /* Turn off the LVDS */ | |
363 | ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, | |
364 | val | CH7017_LVDS_POWER_DOWN_EN); | |
365 | } | |
366 | ||
367 | /* XXX: Should actually wait for update power status somehow */ | |
368 | udelay(20000); | |
369 | } | |
370 | ||
371 | static void ch7017_dump_regs(struct intel_dvo_device *dvo) | |
372 | { | |
373 | uint8_t val; | |
374 | ||
375 | #define DUMP(reg) \ | |
376 | do { \ | |
377 | ch7017_read(dvo, reg, &val); \ | |
d0c3b04a | 378 | DRM_DEBUG_KMS(#reg ": %02x\n", val); \ |
79e53945 JB |
379 | } while (0) |
380 | ||
381 | DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT); | |
382 | DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT); | |
383 | DUMP(CH7017_VERTICAL_ACTIVE_LINE_OUTPUT); | |
384 | DUMP(CH7017_ACTIVE_INPUT_LINE_OUTPUT); | |
385 | DUMP(CH7017_LVDS_PLL_VCO_CONTROL); | |
386 | DUMP(CH7017_LVDS_PLL_FEEDBACK_DIV); | |
387 | DUMP(CH7017_LVDS_CONTROL_2); | |
388 | DUMP(CH7017_OUTPUTS_ENABLE); | |
389 | DUMP(CH7017_LVDS_POWER_DOWN); | |
390 | } | |
391 | ||
79e53945 JB |
392 | static void ch7017_destroy(struct intel_dvo_device *dvo) |
393 | { | |
394 | struct ch7017_priv *priv = dvo->dev_priv; | |
395 | ||
396 | if (priv) { | |
397 | kfree(priv); | |
398 | dvo->dev_priv = NULL; | |
399 | } | |
400 | } | |
401 | ||
402 | struct intel_dvo_dev_ops ch7017_ops = { | |
403 | .init = ch7017_init, | |
404 | .detect = ch7017_detect, | |
405 | .mode_valid = ch7017_mode_valid, | |
406 | .mode_set = ch7017_mode_set, | |
407 | .dpms = ch7017_dpms, | |
408 | .dump_regs = ch7017_dump_regs, | |
79e53945 JB |
409 | .destroy = ch7017_destroy, |
410 | }; |