drm/i915: Avoid NULL dereference with component_only tv_modes
[deliverable/linux.git] / drivers / gpu / drm / i915 / dvo_ch7017.c
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1/*
2 * Copyright © 2006 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "dvo.h"
29
30#define CH7017_TV_DISPLAY_MODE 0x00
31#define CH7017_FLICKER_FILTER 0x01
32#define CH7017_VIDEO_BANDWIDTH 0x02
33#define CH7017_TEXT_ENHANCEMENT 0x03
34#define CH7017_START_ACTIVE_VIDEO 0x04
35#define CH7017_HORIZONTAL_POSITION 0x05
36#define CH7017_VERTICAL_POSITION 0x06
37#define CH7017_BLACK_LEVEL 0x07
38#define CH7017_CONTRAST_ENHANCEMENT 0x08
39#define CH7017_TV_PLL 0x09
40#define CH7017_TV_PLL_M 0x0a
41#define CH7017_TV_PLL_N 0x0b
42#define CH7017_SUB_CARRIER_0 0x0c
43#define CH7017_CIV_CONTROL 0x10
44#define CH7017_CIV_0 0x11
45#define CH7017_CHROMA_BOOST 0x14
46#define CH7017_CLOCK_MODE 0x1c
47#define CH7017_INPUT_CLOCK 0x1d
48#define CH7017_GPIO_CONTROL 0x1e
49#define CH7017_INPUT_DATA_FORMAT 0x1f
50#define CH7017_CONNECTION_DETECT 0x20
51#define CH7017_DAC_CONTROL 0x21
52#define CH7017_BUFFERED_CLOCK_OUTPUT 0x22
53#define CH7017_DEFEAT_VSYNC 0x47
54#define CH7017_TEST_PATTERN 0x48
55
56#define CH7017_POWER_MANAGEMENT 0x49
57/** Enables the TV output path. */
58#define CH7017_TV_EN (1 << 0)
59#define CH7017_DAC0_POWER_DOWN (1 << 1)
60#define CH7017_DAC1_POWER_DOWN (1 << 2)
61#define CH7017_DAC2_POWER_DOWN (1 << 3)
62#define CH7017_DAC3_POWER_DOWN (1 << 4)
63/** Powers down the TV out block, and DAC0-3 */
64#define CH7017_TV_POWER_DOWN_EN (1 << 5)
65
66#define CH7017_VERSION_ID 0x4a
67
68#define CH7017_DEVICE_ID 0x4b
69#define CH7017_DEVICE_ID_VALUE 0x1b
70#define CH7018_DEVICE_ID_VALUE 0x1a
71#define CH7019_DEVICE_ID_VALUE 0x19
72
73#define CH7017_XCLK_D2_ADJUST 0x53
74#define CH7017_UP_SCALER_COEFF_0 0x55
75#define CH7017_UP_SCALER_COEFF_1 0x56
76#define CH7017_UP_SCALER_COEFF_2 0x57
77#define CH7017_UP_SCALER_COEFF_3 0x58
78#define CH7017_UP_SCALER_COEFF_4 0x59
79#define CH7017_UP_SCALER_VERTICAL_INC_0 0x5a
80#define CH7017_UP_SCALER_VERTICAL_INC_1 0x5b
81#define CH7017_GPIO_INVERT 0x5c
82#define CH7017_UP_SCALER_HORIZONTAL_INC_0 0x5d
83#define CH7017_UP_SCALER_HORIZONTAL_INC_1 0x5e
84
85#define CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT 0x5f
86/**< Low bits of horizontal active pixel input */
87
88#define CH7017_ACTIVE_INPUT_LINE_OUTPUT 0x60
89/** High bits of horizontal active pixel input */
90#define CH7017_LVDS_HAP_INPUT_MASK (0x7 << 0)
91/** High bits of vertical active line output */
92#define CH7017_LVDS_VAL_HIGH_MASK (0x7 << 3)
93
94#define CH7017_VERTICAL_ACTIVE_LINE_OUTPUT 0x61
95/**< Low bits of vertical active line output */
96
97#define CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT 0x62
98/**< Low bits of horizontal active pixel output */
99
100#define CH7017_LVDS_POWER_DOWN 0x63
101/** High bits of horizontal active pixel output */
102#define CH7017_LVDS_HAP_HIGH_MASK (0x7 << 0)
103/** Enables the LVDS power down state transition */
104#define CH7017_LVDS_POWER_DOWN_EN (1 << 6)
105/** Enables the LVDS upscaler */
106#define CH7017_LVDS_UPSCALER_EN (1 << 7)
107#define CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED 0x08
108
109#define CH7017_LVDS_ENCODING 0x64
110#define CH7017_LVDS_DITHER_2D (1 << 2)
111#define CH7017_LVDS_DITHER_DIS (1 << 3)
112#define CH7017_LVDS_DUAL_CHANNEL_EN (1 << 4)
113#define CH7017_LVDS_24_BIT (1 << 5)
114
115#define CH7017_LVDS_ENCODING_2 0x65
116
117#define CH7017_LVDS_PLL_CONTROL 0x66
118/** Enables the LVDS panel output path */
119#define CH7017_LVDS_PANEN (1 << 0)
120/** Enables the LVDS panel backlight */
121#define CH7017_LVDS_BKLEN (1 << 3)
122
123#define CH7017_POWER_SEQUENCING_T1 0x67
124#define CH7017_POWER_SEQUENCING_T2 0x68
125#define CH7017_POWER_SEQUENCING_T3 0x69
126#define CH7017_POWER_SEQUENCING_T4 0x6a
127#define CH7017_POWER_SEQUENCING_T5 0x6b
128#define CH7017_GPIO_DRIVER_TYPE 0x6c
129#define CH7017_GPIO_DATA 0x6d
130#define CH7017_GPIO_DIRECTION_CONTROL 0x6e
131
132#define CH7017_LVDS_PLL_FEEDBACK_DIV 0x71
133# define CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT 4
134# define CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT 0
135# define CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED 0x80
136
137#define CH7017_LVDS_PLL_VCO_CONTROL 0x72
138# define CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED 0x80
139# define CH7017_LVDS_PLL_VCO_SHIFT 4
140# define CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT 0
141
142#define CH7017_OUTPUTS_ENABLE 0x73
143# define CH7017_CHARGE_PUMP_LOW 0x0
144# define CH7017_CHARGE_PUMP_HIGH 0x3
145# define CH7017_LVDS_CHANNEL_A (1 << 3)
146# define CH7017_LVDS_CHANNEL_B (1 << 4)
147# define CH7017_TV_DAC_A (1 << 5)
148# define CH7017_TV_DAC_B (1 << 6)
149# define CH7017_DDC_SELECT_DC2 (1 << 7)
150
151#define CH7017_LVDS_OUTPUT_AMPLITUDE 0x74
152#define CH7017_LVDS_PLL_EMI_REDUCTION 0x75
153#define CH7017_LVDS_POWER_DOWN_FLICKER 0x76
154
155#define CH7017_LVDS_CONTROL_2 0x78
156# define CH7017_LOOP_FILTER_SHIFT 5
157# define CH7017_PHASE_DETECTOR_SHIFT 0
158
159#define CH7017_BANG_LIMIT_CONTROL 0x7f
160
161struct ch7017_priv {
162 uint8_t save_hapi;
163 uint8_t save_vali;
164 uint8_t save_valo;
165 uint8_t save_ailo;
166 uint8_t save_lvds_pll_vco;
167 uint8_t save_feedback_div;
168 uint8_t save_lvds_control_2;
169 uint8_t save_outputs_enable;
170 uint8_t save_lvds_power_down;
171 uint8_t save_power_management;
172};
173
174static void ch7017_dump_regs(struct intel_dvo_device *dvo);
175static void ch7017_dpms(struct intel_dvo_device *dvo, int mode);
176
177static bool ch7017_read(struct intel_dvo_device *dvo, int addr, uint8_t *val)
178{
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179 struct i2c_adapter *adapter = dvo->i2c_bus;
180 struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
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181 u8 out_buf[2];
182 u8 in_buf[2];
183
184 struct i2c_msg msgs[] = {
185 {
f9c10a9b 186 .addr = dvo->slave_addr,
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187 .flags = 0,
188 .len = 1,
189 .buf = out_buf,
190 },
191 {
f9c10a9b 192 .addr = dvo->slave_addr,
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193 .flags = I2C_M_RD,
194 .len = 1,
195 .buf = in_buf,
196 }
197 };
198
199 out_buf[0] = addr;
200 out_buf[1] = 0;
201
202 if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) {
203 *val= in_buf[0];
204 return true;
205 };
206
207 return false;
208}
209
210static bool ch7017_write(struct intel_dvo_device *dvo, int addr, uint8_t val)
211{
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212 struct i2c_adapter *adapter = dvo->i2c_bus;
213 struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
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214 uint8_t out_buf[2];
215 struct i2c_msg msg = {
f9c10a9b 216 .addr = dvo->slave_addr,
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217 .flags = 0,
218 .len = 2,
219 .buf = out_buf,
220 };
221
222 out_buf[0] = addr;
223 out_buf[1] = val;
224
225 if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
226 return true;
227
228 return false;
229}
230
231/** Probes for a CH7017 on the given bus and slave address. */
232static bool ch7017_init(struct intel_dvo_device *dvo,
f9c10a9b 233 struct i2c_adapter *adapter)
79e53945 234{
f9c10a9b 235 struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
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236 struct ch7017_priv *priv;
237 uint8_t val;
238
239 priv = kzalloc(sizeof(struct ch7017_priv), GFP_KERNEL);
240 if (priv == NULL)
241 return false;
242
f9c10a9b 243 dvo->i2c_bus = adapter;
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244 dvo->dev_priv = priv;
245
246 if (!ch7017_read(dvo, CH7017_DEVICE_ID, &val))
247 goto fail;
248
249 if (val != CH7017_DEVICE_ID_VALUE &&
250 val != CH7018_DEVICE_ID_VALUE &&
251 val != CH7019_DEVICE_ID_VALUE) {
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252 DRM_DEBUG_KMS("ch701x not detected, got %d: from %s "
253 "Slave %d.\n",
f9c10a9b 254 val, i2cbus->adapter.name,dvo->slave_addr);
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255 goto fail;
256 }
257
258 return true;
259fail:
260 kfree(priv);
261 return false;
262}
263
264static enum drm_connector_status ch7017_detect(struct intel_dvo_device *dvo)
265{
266 return connector_status_unknown;
267}
268
269static enum drm_mode_status ch7017_mode_valid(struct intel_dvo_device *dvo,
270 struct drm_display_mode *mode)
271{
272 if (mode->clock > 160000)
273 return MODE_CLOCK_HIGH;
274
275 return MODE_OK;
276}
277
278static void ch7017_mode_set(struct intel_dvo_device *dvo,
279 struct drm_display_mode *mode,
280 struct drm_display_mode *adjusted_mode)
281{
282 uint8_t lvds_pll_feedback_div, lvds_pll_vco_control;
283 uint8_t outputs_enable, lvds_control_2, lvds_power_down;
284 uint8_t horizontal_active_pixel_input;
285 uint8_t horizontal_active_pixel_output, vertical_active_line_output;
286 uint8_t active_input_line_output;
287
d0c3b04a 288 DRM_DEBUG_KMS("Registers before mode setting\n");
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289 ch7017_dump_regs(dvo);
290
291 /* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/
292 if (mode->clock < 100000) {
293 outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_LOW;
294 lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED |
295 (2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) |
296 (13 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT);
297 lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED |
298 (2 << CH7017_LVDS_PLL_VCO_SHIFT) |
299 (3 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT);
300 lvds_control_2 = (1 << CH7017_LOOP_FILTER_SHIFT) |
301 (0 << CH7017_PHASE_DETECTOR_SHIFT);
302 } else {
303 outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_HIGH;
304 lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED |
305 (2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) |
306 (3 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT);
307 lvds_pll_feedback_div = 35;
308 lvds_control_2 = (3 << CH7017_LOOP_FILTER_SHIFT) |
309 (0 << CH7017_PHASE_DETECTOR_SHIFT);
310 if (1) { /* XXX: dual channel panel detection. Assume yes for now. */
311 outputs_enable |= CH7017_LVDS_CHANNEL_B;
312 lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED |
313 (2 << CH7017_LVDS_PLL_VCO_SHIFT) |
314 (13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT);
315 } else {
316 lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED |
317 (1 << CH7017_LVDS_PLL_VCO_SHIFT) |
318 (13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT);
319 }
320 }
321
322 horizontal_active_pixel_input = mode->hdisplay & 0x00ff;
323
324 vertical_active_line_output = mode->vdisplay & 0x00ff;
325 horizontal_active_pixel_output = mode->hdisplay & 0x00ff;
326
327 active_input_line_output = ((mode->hdisplay & 0x0700) >> 8) |
328 (((mode->vdisplay & 0x0700) >> 8) << 3);
329
330 lvds_power_down = CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED |
331 (mode->hdisplay & 0x0700) >> 8;
332
333 ch7017_dpms(dvo, DRM_MODE_DPMS_OFF);
334 ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT,
335 horizontal_active_pixel_input);
336 ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT,
337 horizontal_active_pixel_output);
338 ch7017_write(dvo, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT,
339 vertical_active_line_output);
340 ch7017_write(dvo, CH7017_ACTIVE_INPUT_LINE_OUTPUT,
341 active_input_line_output);
342 ch7017_write(dvo, CH7017_LVDS_PLL_VCO_CONTROL, lvds_pll_vco_control);
343 ch7017_write(dvo, CH7017_LVDS_PLL_FEEDBACK_DIV, lvds_pll_feedback_div);
344 ch7017_write(dvo, CH7017_LVDS_CONTROL_2, lvds_control_2);
345 ch7017_write(dvo, CH7017_OUTPUTS_ENABLE, outputs_enable);
346
347 /* Turn the LVDS back on with new settings. */
348 ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down);
349
d0c3b04a 350 DRM_DEBUG_KMS("Registers after mode setting\n");
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351 ch7017_dump_regs(dvo);
352}
353
354/* set the CH7017 power state */
355static void ch7017_dpms(struct intel_dvo_device *dvo, int mode)
356{
357 uint8_t val;
358
359 ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val);
360
361 /* Turn off TV/VGA, and never turn it on since we don't support it. */
362 ch7017_write(dvo, CH7017_POWER_MANAGEMENT,
363 CH7017_DAC0_POWER_DOWN |
364 CH7017_DAC1_POWER_DOWN |
365 CH7017_DAC2_POWER_DOWN |
366 CH7017_DAC3_POWER_DOWN |
367 CH7017_TV_POWER_DOWN_EN);
368
369 if (mode == DRM_MODE_DPMS_ON) {
370 /* Turn on the LVDS */
371 ch7017_write(dvo, CH7017_LVDS_POWER_DOWN,
372 val & ~CH7017_LVDS_POWER_DOWN_EN);
373 } else {
374 /* Turn off the LVDS */
375 ch7017_write(dvo, CH7017_LVDS_POWER_DOWN,
376 val | CH7017_LVDS_POWER_DOWN_EN);
377 }
378
379 /* XXX: Should actually wait for update power status somehow */
380 udelay(20000);
381}
382
383static void ch7017_dump_regs(struct intel_dvo_device *dvo)
384{
385 uint8_t val;
386
387#define DUMP(reg) \
388do { \
389 ch7017_read(dvo, reg, &val); \
d0c3b04a 390 DRM_DEBUG_KMS(#reg ": %02x\n", val); \
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391} while (0)
392
393 DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT);
394 DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT);
395 DUMP(CH7017_VERTICAL_ACTIVE_LINE_OUTPUT);
396 DUMP(CH7017_ACTIVE_INPUT_LINE_OUTPUT);
397 DUMP(CH7017_LVDS_PLL_VCO_CONTROL);
398 DUMP(CH7017_LVDS_PLL_FEEDBACK_DIV);
399 DUMP(CH7017_LVDS_CONTROL_2);
400 DUMP(CH7017_OUTPUTS_ENABLE);
401 DUMP(CH7017_LVDS_POWER_DOWN);
402}
403
404static void ch7017_save(struct intel_dvo_device *dvo)
405{
406 struct ch7017_priv *priv = dvo->dev_priv;
407
408 ch7017_read(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT, &priv->save_hapi);
409 ch7017_read(dvo, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT, &priv->save_valo);
410 ch7017_read(dvo, CH7017_ACTIVE_INPUT_LINE_OUTPUT, &priv->save_ailo);
411 ch7017_read(dvo, CH7017_LVDS_PLL_VCO_CONTROL, &priv->save_lvds_pll_vco);
412 ch7017_read(dvo, CH7017_LVDS_PLL_FEEDBACK_DIV, &priv->save_feedback_div);
413 ch7017_read(dvo, CH7017_LVDS_CONTROL_2, &priv->save_lvds_control_2);
414 ch7017_read(dvo, CH7017_OUTPUTS_ENABLE, &priv->save_outputs_enable);
415 ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &priv->save_lvds_power_down);
416 ch7017_read(dvo, CH7017_POWER_MANAGEMENT, &priv->save_power_management);
417}
418
419static void ch7017_restore(struct intel_dvo_device *dvo)
420{
421 struct ch7017_priv *priv = dvo->dev_priv;
422
423 /* Power down before changing mode */
424 ch7017_dpms(dvo, DRM_MODE_DPMS_OFF);
425
426 ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT, priv->save_hapi);
427 ch7017_write(dvo, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT, priv->save_valo);
428 ch7017_write(dvo, CH7017_ACTIVE_INPUT_LINE_OUTPUT, priv->save_ailo);
429 ch7017_write(dvo, CH7017_LVDS_PLL_VCO_CONTROL, priv->save_lvds_pll_vco);
430 ch7017_write(dvo, CH7017_LVDS_PLL_FEEDBACK_DIV, priv->save_feedback_div);
431 ch7017_write(dvo, CH7017_LVDS_CONTROL_2, priv->save_lvds_control_2);
432 ch7017_write(dvo, CH7017_OUTPUTS_ENABLE, priv->save_outputs_enable);
433 ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, priv->save_lvds_power_down);
434 ch7017_write(dvo, CH7017_POWER_MANAGEMENT, priv->save_power_management);
435}
436
437static void ch7017_destroy(struct intel_dvo_device *dvo)
438{
439 struct ch7017_priv *priv = dvo->dev_priv;
440
441 if (priv) {
442 kfree(priv);
443 dvo->dev_priv = NULL;
444 }
445}
446
447struct intel_dvo_dev_ops ch7017_ops = {
448 .init = ch7017_init,
449 .detect = ch7017_detect,
450 .mode_valid = ch7017_mode_valid,
451 .mode_set = ch7017_mode_set,
452 .dpms = ch7017_dpms,
453 .dump_regs = ch7017_dump_regs,
454 .save = ch7017_save,
455 .restore = ch7017_restore,
456 .destroy = ch7017_destroy,
457};
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