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79e53945 JB |
1 | /* |
2 | * Copyright © 2006 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "dvo.h" | |
29 | ||
30 | /* | |
31 | * register definitions for the i82807aa. | |
32 | * | |
33 | * Documentation on this chipset can be found in datasheet #29069001 at | |
34 | * intel.com. | |
35 | */ | |
36 | ||
37 | /* | |
38 | * VCH Revision & GMBus Base Addr | |
39 | */ | |
40 | #define VR00 0x00 | |
41 | # define VR00_BASE_ADDRESS_MASK 0x007f | |
42 | ||
43 | /* | |
44 | * Functionality Enable | |
45 | */ | |
46 | #define VR01 0x01 | |
47 | ||
48 | /* | |
49 | * Enable the panel fitter | |
50 | */ | |
51 | # define VR01_PANEL_FIT_ENABLE (1 << 3) | |
52 | /* | |
53 | * Enables the LCD display. | |
54 | * | |
55 | * This must not be set while VR01_DVO_BYPASS_ENABLE is set. | |
56 | */ | |
57 | # define VR01_LCD_ENABLE (1 << 2) | |
58 | /** Enables the DVO repeater. */ | |
59 | # define VR01_DVO_BYPASS_ENABLE (1 << 1) | |
60 | /** Enables the DVO clock */ | |
61 | # define VR01_DVO_ENABLE (1 << 0) | |
62 | ||
63 | /* | |
64 | * LCD Interface Format | |
65 | */ | |
66 | #define VR10 0x10 | |
67 | /** Enables LVDS output instead of CMOS */ | |
68 | # define VR10_LVDS_ENABLE (1 << 4) | |
69 | /** Enables 18-bit LVDS output. */ | |
70 | # define VR10_INTERFACE_1X18 (0 << 2) | |
71 | /** Enables 24-bit LVDS or CMOS output */ | |
72 | # define VR10_INTERFACE_1X24 (1 << 2) | |
73 | /** Enables 2x18-bit LVDS or CMOS output. */ | |
74 | # define VR10_INTERFACE_2X18 (2 << 2) | |
75 | /** Enables 2x24-bit LVDS output */ | |
76 | # define VR10_INTERFACE_2X24 (3 << 2) | |
77 | ||
78 | /* | |
79 | * VR20 LCD Horizontal Display Size | |
80 | */ | |
81 | #define VR20 0x20 | |
82 | ||
83 | /* | |
84 | * LCD Vertical Display Size | |
85 | */ | |
86 | #define VR21 0x20 | |
87 | ||
88 | /* | |
89 | * Panel power down status | |
90 | */ | |
91 | #define VR30 0x30 | |
92 | /** Read only bit indicating that the panel is not in a safe poweroff state. */ | |
93 | # define VR30_PANEL_ON (1 << 15) | |
94 | ||
95 | #define VR40 0x40 | |
96 | # define VR40_STALL_ENABLE (1 << 13) | |
97 | # define VR40_VERTICAL_INTERP_ENABLE (1 << 12) | |
98 | # define VR40_ENHANCED_PANEL_FITTING (1 << 11) | |
99 | # define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10) | |
100 | # define VR40_AUTO_RATIO_ENABLE (1 << 9) | |
101 | # define VR40_CLOCK_GATING_ENABLE (1 << 8) | |
102 | ||
103 | /* | |
104 | * Panel Fitting Vertical Ratio | |
105 | * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2 | |
106 | */ | |
107 | #define VR41 0x41 | |
108 | ||
109 | /* | |
110 | * Panel Fitting Horizontal Ratio | |
111 | * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2 | |
112 | */ | |
113 | #define VR42 0x42 | |
114 | ||
115 | /* | |
116 | * Horizontal Image Size | |
117 | */ | |
118 | #define VR43 0x43 | |
119 | ||
120 | /* VR80 GPIO 0 | |
121 | */ | |
122 | #define VR80 0x80 | |
123 | #define VR81 0x81 | |
124 | #define VR82 0x82 | |
125 | #define VR83 0x83 | |
126 | #define VR84 0x84 | |
127 | #define VR85 0x85 | |
128 | #define VR86 0x86 | |
129 | #define VR87 0x87 | |
130 | ||
131 | /* VR88 GPIO 8 | |
132 | */ | |
133 | #define VR88 0x88 | |
134 | ||
135 | /* Graphics BIOS scratch 0 | |
136 | */ | |
137 | #define VR8E 0x8E | |
138 | # define VR8E_PANEL_TYPE_MASK (0xf << 0) | |
139 | # define VR8E_PANEL_INTERFACE_CMOS (0 << 4) | |
140 | # define VR8E_PANEL_INTERFACE_LVDS (1 << 4) | |
141 | # define VR8E_FORCE_DEFAULT_PANEL (1 << 5) | |
142 | ||
143 | /* Graphics BIOS scratch 1 | |
144 | */ | |
145 | #define VR8F 0x8F | |
146 | # define VR8F_VCH_PRESENT (1 << 0) | |
147 | # define VR8F_DISPLAY_CONN (1 << 1) | |
148 | # define VR8F_POWER_MASK (0x3c) | |
149 | # define VR8F_POWER_POS (2) | |
150 | ||
151 | ||
152 | struct ivch_priv { | |
153 | bool quiet; | |
154 | ||
155 | uint16_t width, height; | |
79e53945 JB |
156 | }; |
157 | ||
158 | ||
159 | static void ivch_dump_regs(struct intel_dvo_device *dvo); | |
160 | ||
161 | /** | |
162 | * Reads a register on the ivch. | |
163 | * | |
164 | * Each of the 256 registers are 16 bits long. | |
165 | */ | |
166 | static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data) | |
167 | { | |
168 | struct ivch_priv *priv = dvo->dev_priv; | |
f9c10a9b KP |
169 | struct i2c_adapter *adapter = dvo->i2c_bus; |
170 | struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter); | |
79e53945 JB |
171 | u8 out_buf[1]; |
172 | u8 in_buf[2]; | |
173 | ||
174 | struct i2c_msg msgs[] = { | |
175 | { | |
f9c10a9b | 176 | .addr = dvo->slave_addr, |
79e53945 JB |
177 | .flags = I2C_M_RD, |
178 | .len = 0, | |
179 | }, | |
180 | { | |
181 | .addr = 0, | |
182 | .flags = I2C_M_NOSTART, | |
183 | .len = 1, | |
184 | .buf = out_buf, | |
185 | }, | |
186 | { | |
f9c10a9b | 187 | .addr = dvo->slave_addr, |
79e53945 JB |
188 | .flags = I2C_M_RD | I2C_M_NOSTART, |
189 | .len = 2, | |
190 | .buf = in_buf, | |
191 | } | |
192 | }; | |
193 | ||
194 | out_buf[0] = addr; | |
195 | ||
196 | if (i2c_transfer(&i2cbus->adapter, msgs, 3) == 3) { | |
197 | *data = (in_buf[1] << 8) | in_buf[0]; | |
198 | return true; | |
199 | }; | |
200 | ||
201 | if (!priv->quiet) { | |
d0c3b04a ZY |
202 | DRM_DEBUG_KMS("Unable to read register 0x%02x from " |
203 | "%s:%02x.\n", | |
f9c10a9b | 204 | addr, i2cbus->adapter.name, dvo->slave_addr); |
79e53945 JB |
205 | } |
206 | return false; | |
207 | } | |
208 | ||
209 | /** Writes a 16-bit register on the ivch */ | |
210 | static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data) | |
211 | { | |
212 | struct ivch_priv *priv = dvo->dev_priv; | |
f9c10a9b KP |
213 | struct i2c_adapter *adapter = dvo->i2c_bus; |
214 | struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter); | |
79e53945 JB |
215 | u8 out_buf[3]; |
216 | struct i2c_msg msg = { | |
f9c10a9b | 217 | .addr = dvo->slave_addr, |
79e53945 JB |
218 | .flags = 0, |
219 | .len = 3, | |
220 | .buf = out_buf, | |
221 | }; | |
222 | ||
223 | out_buf[0] = addr; | |
224 | out_buf[1] = data & 0xff; | |
225 | out_buf[2] = data >> 8; | |
226 | ||
227 | if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1) | |
228 | return true; | |
229 | ||
230 | if (!priv->quiet) { | |
d0c3b04a | 231 | DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", |
f9c10a9b | 232 | addr, i2cbus->adapter.name, dvo->slave_addr); |
79e53945 JB |
233 | } |
234 | ||
235 | return false; | |
236 | } | |
237 | ||
238 | /** Probes the given bus and slave address for an ivch */ | |
239 | static bool ivch_init(struct intel_dvo_device *dvo, | |
f9c10a9b | 240 | struct i2c_adapter *adapter) |
79e53945 JB |
241 | { |
242 | struct ivch_priv *priv; | |
243 | uint16_t temp; | |
244 | ||
245 | priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL); | |
246 | if (priv == NULL) | |
247 | return false; | |
248 | ||
f9c10a9b | 249 | dvo->i2c_bus = adapter; |
79e53945 JB |
250 | dvo->dev_priv = priv; |
251 | priv->quiet = true; | |
252 | ||
253 | if (!ivch_read(dvo, VR00, &temp)) | |
254 | goto out; | |
255 | priv->quiet = false; | |
256 | ||
257 | /* Since the identification bits are probably zeroes, which doesn't seem | |
258 | * very unique, check that the value in the base address field matches | |
259 | * the address it's responding on. | |
260 | */ | |
261 | if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) { | |
d0c3b04a | 262 | DRM_DEBUG_KMS("ivch detect failed due to address mismatch " |
79e53945 JB |
263 | "(%d vs %d)\n", |
264 | (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr); | |
265 | goto out; | |
266 | } | |
267 | ||
268 | ivch_read(dvo, VR20, &priv->width); | |
269 | ivch_read(dvo, VR21, &priv->height); | |
270 | ||
271 | return true; | |
272 | ||
273 | out: | |
274 | kfree(priv); | |
275 | return false; | |
276 | } | |
277 | ||
278 | static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo) | |
279 | { | |
280 | return connector_status_connected; | |
281 | } | |
282 | ||
283 | static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo, | |
284 | struct drm_display_mode *mode) | |
285 | { | |
286 | if (mode->clock > 112000) | |
287 | return MODE_CLOCK_HIGH; | |
288 | ||
289 | return MODE_OK; | |
290 | } | |
291 | ||
292 | /** Sets the power state of the panel connected to the ivch */ | |
293 | static void ivch_dpms(struct intel_dvo_device *dvo, int mode) | |
294 | { | |
295 | int i; | |
296 | uint16_t vr01, vr30, backlight; | |
297 | ||
298 | /* Set the new power state of the panel. */ | |
299 | if (!ivch_read(dvo, VR01, &vr01)) | |
300 | return; | |
301 | ||
302 | if (mode == DRM_MODE_DPMS_ON) | |
303 | backlight = 1; | |
304 | else | |
305 | backlight = 0; | |
306 | ivch_write(dvo, VR80, backlight); | |
307 | ||
308 | if (mode == DRM_MODE_DPMS_ON) | |
309 | vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE; | |
310 | else | |
311 | vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE); | |
312 | ||
313 | ivch_write(dvo, VR01, vr01); | |
314 | ||
315 | /* Wait for the panel to make its state transition */ | |
316 | for (i = 0; i < 100; i++) { | |
317 | if (!ivch_read(dvo, VR30, &vr30)) | |
318 | break; | |
319 | ||
320 | if (((vr30 & VR30_PANEL_ON) != 0) == (mode == DRM_MODE_DPMS_ON)) | |
321 | break; | |
322 | udelay(1000); | |
323 | } | |
324 | /* wait some more; vch may fail to resync sometimes without this */ | |
325 | udelay(16 * 1000); | |
326 | } | |
327 | ||
328 | static void ivch_mode_set(struct intel_dvo_device *dvo, | |
329 | struct drm_display_mode *mode, | |
330 | struct drm_display_mode *adjusted_mode) | |
331 | { | |
332 | uint16_t vr40 = 0; | |
333 | uint16_t vr01; | |
334 | ||
335 | vr01 = 0; | |
336 | vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE | | |
337 | VR40_HORIZONTAL_INTERP_ENABLE); | |
338 | ||
339 | if (mode->hdisplay != adjusted_mode->hdisplay || | |
340 | mode->vdisplay != adjusted_mode->vdisplay) { | |
341 | uint16_t x_ratio, y_ratio; | |
342 | ||
343 | vr01 |= VR01_PANEL_FIT_ENABLE; | |
344 | vr40 |= VR40_CLOCK_GATING_ENABLE; | |
345 | x_ratio = (((mode->hdisplay - 1) << 16) / | |
346 | (adjusted_mode->hdisplay - 1)) >> 2; | |
347 | y_ratio = (((mode->vdisplay - 1) << 16) / | |
348 | (adjusted_mode->vdisplay - 1)) >> 2; | |
349 | ivch_write (dvo, VR42, x_ratio); | |
350 | ivch_write (dvo, VR41, y_ratio); | |
351 | } else { | |
352 | vr01 &= ~VR01_PANEL_FIT_ENABLE; | |
353 | vr40 &= ~VR40_CLOCK_GATING_ENABLE; | |
354 | } | |
355 | vr40 &= ~VR40_AUTO_RATIO_ENABLE; | |
356 | ||
357 | ivch_write(dvo, VR01, vr01); | |
358 | ivch_write(dvo, VR40, vr40); | |
359 | ||
360 | ivch_dump_regs(dvo); | |
361 | } | |
362 | ||
363 | static void ivch_dump_regs(struct intel_dvo_device *dvo) | |
364 | { | |
365 | uint16_t val; | |
366 | ||
367 | ivch_read(dvo, VR00, &val); | |
d0c3b04a | 368 | DRM_LOG_KMS("VR00: 0x%04x\n", val); |
79e53945 | 369 | ivch_read(dvo, VR01, &val); |
d0c3b04a | 370 | DRM_LOG_KMS("VR01: 0x%04x\n", val); |
79e53945 | 371 | ivch_read(dvo, VR30, &val); |
d0c3b04a | 372 | DRM_LOG_KMS("VR30: 0x%04x\n", val); |
79e53945 | 373 | ivch_read(dvo, VR40, &val); |
d0c3b04a | 374 | DRM_LOG_KMS("VR40: 0x%04x\n", val); |
79e53945 JB |
375 | |
376 | /* GPIO registers */ | |
377 | ivch_read(dvo, VR80, &val); | |
d0c3b04a | 378 | DRM_LOG_KMS("VR80: 0x%04x\n", val); |
79e53945 | 379 | ivch_read(dvo, VR81, &val); |
d0c3b04a | 380 | DRM_LOG_KMS("VR81: 0x%04x\n", val); |
79e53945 | 381 | ivch_read(dvo, VR82, &val); |
d0c3b04a | 382 | DRM_LOG_KMS("VR82: 0x%04x\n", val); |
79e53945 | 383 | ivch_read(dvo, VR83, &val); |
d0c3b04a | 384 | DRM_LOG_KMS("VR83: 0x%04x\n", val); |
79e53945 | 385 | ivch_read(dvo, VR84, &val); |
d0c3b04a | 386 | DRM_LOG_KMS("VR84: 0x%04x\n", val); |
79e53945 | 387 | ivch_read(dvo, VR85, &val); |
d0c3b04a | 388 | DRM_LOG_KMS("VR85: 0x%04x\n", val); |
79e53945 | 389 | ivch_read(dvo, VR86, &val); |
d0c3b04a | 390 | DRM_LOG_KMS("VR86: 0x%04x\n", val); |
79e53945 | 391 | ivch_read(dvo, VR87, &val); |
d0c3b04a | 392 | DRM_LOG_KMS("VR87: 0x%04x\n", val); |
79e53945 | 393 | ivch_read(dvo, VR88, &val); |
d0c3b04a | 394 | DRM_LOG_KMS("VR88: 0x%04x\n", val); |
79e53945 JB |
395 | |
396 | /* Scratch register 0 - AIM Panel type */ | |
397 | ivch_read(dvo, VR8E, &val); | |
d0c3b04a | 398 | DRM_LOG_KMS("VR8E: 0x%04x\n", val); |
79e53945 JB |
399 | |
400 | /* Scratch register 1 - Status register */ | |
401 | ivch_read(dvo, VR8F, &val); | |
d0c3b04a | 402 | DRM_LOG_KMS("VR8F: 0x%04x\n", val); |
79e53945 JB |
403 | } |
404 | ||
79e53945 JB |
405 | static void ivch_destroy(struct intel_dvo_device *dvo) |
406 | { | |
407 | struct ivch_priv *priv = dvo->dev_priv; | |
408 | ||
409 | if (priv) { | |
410 | kfree(priv); | |
411 | dvo->dev_priv = NULL; | |
412 | } | |
413 | } | |
414 | ||
415 | struct intel_dvo_dev_ops ivch_ops= { | |
416 | .init = ivch_init, | |
417 | .dpms = ivch_dpms, | |
79e53945 JB |
418 | .mode_valid = ivch_mode_valid, |
419 | .mode_set = ivch_mode_set, | |
420 | .detect = ivch_detect, | |
421 | .dump_regs = ivch_dump_regs, | |
422 | .destroy = ivch_destroy, | |
423 | }; |