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351e3db2 BV |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Brad Volkin <bradley.d.volkin@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | ||
30 | /** | |
122b2505 | 31 | * DOC: batch buffer command parser |
351e3db2 BV |
32 | * |
33 | * Motivation: | |
34 | * Certain OpenGL features (e.g. transform feedback, performance monitoring) | |
35 | * require userspace code to submit batches containing commands such as | |
36 | * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some | |
37 | * generations of the hardware will noop these commands in "unsecure" batches | |
38 | * (which includes all userspace batches submitted via i915) even though the | |
39 | * commands may be safe and represent the intended programming model of the | |
40 | * device. | |
41 | * | |
42 | * The software command parser is similar in operation to the command parsing | |
43 | * done in hardware for unsecure batches. However, the software parser allows | |
44 | * some operations that would be noop'd by hardware, if the parser determines | |
45 | * the operation is safe, and submits the batch as "secure" to prevent hardware | |
46 | * parsing. | |
47 | * | |
48 | * Threats: | |
49 | * At a high level, the hardware (and software) checks attempt to prevent | |
50 | * granting userspace undue privileges. There are three categories of privilege. | |
51 | * | |
52 | * First, commands which are explicitly defined as privileged or which should | |
53 | * only be used by the kernel driver. The parser generally rejects such | |
54 | * commands, though it may allow some from the drm master process. | |
55 | * | |
56 | * Second, commands which access registers. To support correct/enhanced | |
57 | * userspace functionality, particularly certain OpenGL extensions, the parser | |
58 | * provides a whitelist of registers which userspace may safely access (for both | |
59 | * normal and drm master processes). | |
60 | * | |
61 | * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). | |
62 | * The parser always rejects such commands. | |
63 | * | |
64 | * The majority of the problematic commands fall in the MI_* range, with only a | |
65 | * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW). | |
66 | * | |
67 | * Implementation: | |
68 | * Each ring maintains tables of commands and registers which the parser uses in | |
69 | * scanning batch buffers submitted to that ring. | |
70 | * | |
71 | * Since the set of commands that the parser must check for is significantly | |
72 | * smaller than the number of commands supported, the parser tables contain only | |
73 | * those commands required by the parser. This generally works because command | |
74 | * opcode ranges have standard command length encodings. So for commands that | |
75 | * the parser does not need to check, it can easily skip them. This is | |
32197aab | 76 | * implemented via a per-ring length decoding vfunc. |
351e3db2 BV |
77 | * |
78 | * Unfortunately, there are a number of commands that do not follow the standard | |
79 | * length encoding for their opcode range, primarily amongst the MI_* commands. | |
80 | * To handle this, the parser provides a way to define explicit "skip" entries | |
81 | * in the per-ring command tables. | |
82 | * | |
83 | * Other command table entries map fairly directly to high level categories | |
84 | * mentioned above: rejected, master-only, register whitelist. The parser | |
85 | * implements a number of checks, including the privileged memory checks, via a | |
86 | * general bitmasking mechanism. | |
87 | */ | |
88 | ||
3a6fa984 BV |
89 | #define STD_MI_OPCODE_MASK 0xFF800000 |
90 | #define STD_3D_OPCODE_MASK 0xFFFF0000 | |
91 | #define STD_2D_OPCODE_MASK 0xFFC00000 | |
92 | #define STD_MFX_OPCODE_MASK 0xFFFF0000 | |
93 | ||
94 | #define CMD(op, opm, f, lm, fl, ...) \ | |
95 | { \ | |
96 | .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ | |
f1afe24f | 97 | .cmd = { (op), (opm) }, \ |
3a6fa984 BV |
98 | .length = { (lm) }, \ |
99 | __VA_ARGS__ \ | |
100 | } | |
101 | ||
102 | /* Convenience macros to compress the tables */ | |
103 | #define SMI STD_MI_OPCODE_MASK | |
104 | #define S3D STD_3D_OPCODE_MASK | |
105 | #define S2D STD_2D_OPCODE_MASK | |
106 | #define SMFX STD_MFX_OPCODE_MASK | |
107 | #define F true | |
108 | #define S CMD_DESC_SKIP | |
109 | #define R CMD_DESC_REJECT | |
110 | #define W CMD_DESC_REGISTER | |
111 | #define B CMD_DESC_BITMASK | |
112 | #define M CMD_DESC_MASTER | |
113 | ||
114 | /* Command Mask Fixed Len Action | |
115 | ---------------------------------------------------------- */ | |
116 | static const struct drm_i915_cmd_descriptor common_cmds[] = { | |
117 | CMD( MI_NOOP, SMI, F, 1, S ), | |
b18b396b | 118 | CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), |
17c1eb15 | 119 | CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ), |
3a6fa984 BV |
120 | CMD( MI_ARB_CHECK, SMI, F, 1, S ), |
121 | CMD( MI_REPORT_HEAD, SMI, F, 1, S ), | |
122 | CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), | |
9c640d1d BV |
123 | CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), |
124 | CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), | |
f0a346bd | 125 | CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, |
6a65c5b9 | 126 | .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), |
614f4ad7 | 127 | CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B, |
d4d48035 BV |
128 | .reg = { .offset = 1, .mask = 0x007FFFFC }, |
129 | .bits = {{ | |
130 | .offset = 0, | |
131 | .mask = MI_GLOBAL_GTT, | |
132 | .expected = 0, | |
133 | }}, ), | |
614f4ad7 | 134 | CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B, |
d4d48035 BV |
135 | .reg = { .offset = 1, .mask = 0x007FFFFC }, |
136 | .bits = {{ | |
137 | .offset = 0, | |
138 | .mask = MI_GLOBAL_GTT, | |
139 | .expected = 0, | |
140 | }}, ), | |
42c7156a BV |
141 | /* |
142 | * MI_BATCH_BUFFER_START requires some special handling. It's not | |
143 | * really a 'skip' action but it doesn't seem like it's worth adding | |
144 | * a new action. See i915_parse_cmds(). | |
145 | */ | |
3a6fa984 BV |
146 | CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), |
147 | }; | |
148 | ||
149 | static const struct drm_i915_cmd_descriptor render_cmds[] = { | |
150 | CMD( MI_FLUSH, SMI, F, 1, S ), | |
9c640d1d | 151 | CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), |
3a6fa984 BV |
152 | CMD( MI_PREDICATE, SMI, F, 1, S ), |
153 | CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), | |
86ef630d | 154 | CMD( MI_SET_APPID, SMI, F, 1, S ), |
9f58582c | 155 | CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), |
9c640d1d | 156 | CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), |
3a6fa984 | 157 | CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), |
d4d48035 BV |
158 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, |
159 | .bits = {{ | |
160 | .offset = 0, | |
161 | .mask = MI_GLOBAL_GTT, | |
162 | .expected = 0, | |
163 | }}, ), | |
9c640d1d | 164 | CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), |
d4d48035 BV |
165 | CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, |
166 | .bits = {{ | |
167 | .offset = 0, | |
168 | .mask = MI_GLOBAL_GTT, | |
169 | .expected = 0, | |
170 | }}, ), | |
171 | CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, | |
172 | .bits = {{ | |
173 | .offset = 1, | |
174 | .mask = MI_REPORT_PERF_COUNT_GGTT, | |
175 | .expected = 0, | |
176 | }}, ), | |
177 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, | |
178 | .bits = {{ | |
179 | .offset = 0, | |
180 | .mask = MI_GLOBAL_GTT, | |
181 | .expected = 0, | |
182 | }}, ), | |
3a6fa984 BV |
183 | CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), |
184 | CMD( PIPELINE_SELECT, S3D, F, 1, S ), | |
f0a346bd BV |
185 | CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, |
186 | .bits = {{ | |
187 | .offset = 2, | |
188 | .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, | |
189 | .expected = 0, | |
190 | }}, ), | |
3a6fa984 BV |
191 | CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), |
192 | CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), | |
193 | CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), | |
f0a346bd BV |
194 | CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, |
195 | .bits = {{ | |
196 | .offset = 1, | |
b18b396b | 197 | .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), |
f0a346bd | 198 | .expected = 0, |
d4d48035 BV |
199 | }, |
200 | { | |
201 | .offset = 1, | |
114d4f70 BV |
202 | .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | |
203 | PIPE_CONTROL_STORE_DATA_INDEX), | |
d4d48035 BV |
204 | .expected = 0, |
205 | .condition_offset = 1, | |
206 | .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, | |
f0a346bd | 207 | }}, ), |
3a6fa984 BV |
208 | }; |
209 | ||
210 | static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { | |
211 | CMD( MI_SET_PREDICATE, SMI, F, 1, S ), | |
212 | CMD( MI_RS_CONTROL, SMI, F, 1, S ), | |
213 | CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), | |
86ef630d | 214 | CMD( MI_SET_APPID, SMI, F, 1, S ), |
3a6fa984 | 215 | CMD( MI_RS_CONTEXT, SMI, F, 1, S ), |
17c1eb15 | 216 | CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), |
9c640d1d BV |
217 | CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), |
218 | CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ), | |
3a6fa984 BV |
219 | CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), |
220 | CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), | |
221 | CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), | |
222 | CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), | |
223 | CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), | |
224 | ||
225 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), | |
226 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), | |
227 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), | |
228 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), | |
229 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), | |
230 | }; | |
231 | ||
232 | static const struct drm_i915_cmd_descriptor video_cmds[] = { | |
9c640d1d | 233 | CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), |
86ef630d | 234 | CMD( MI_SET_APPID, SMI, F, 1, S ), |
d4d48035 BV |
235 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, |
236 | .bits = {{ | |
237 | .offset = 0, | |
238 | .mask = MI_GLOBAL_GTT, | |
239 | .expected = 0, | |
240 | }}, ), | |
9c640d1d | 241 | CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), |
b18b396b BV |
242 | CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, |
243 | .bits = {{ | |
244 | .offset = 0, | |
245 | .mask = MI_FLUSH_DW_NOTIFY, | |
246 | .expected = 0, | |
d4d48035 BV |
247 | }, |
248 | { | |
249 | .offset = 1, | |
250 | .mask = MI_FLUSH_DW_USE_GTT, | |
251 | .expected = 0, | |
252 | .condition_offset = 0, | |
253 | .condition_mask = MI_FLUSH_DW_OP_MASK, | |
114d4f70 BV |
254 | }, |
255 | { | |
256 | .offset = 0, | |
257 | .mask = MI_FLUSH_DW_STORE_INDEX, | |
258 | .expected = 0, | |
259 | .condition_offset = 0, | |
260 | .condition_mask = MI_FLUSH_DW_OP_MASK, | |
d4d48035 BV |
261 | }}, ), |
262 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, | |
263 | .bits = {{ | |
264 | .offset = 0, | |
265 | .mask = MI_GLOBAL_GTT, | |
266 | .expected = 0, | |
b18b396b | 267 | }}, ), |
3a6fa984 BV |
268 | /* |
269 | * MFX_WAIT doesn't fit the way we handle length for most commands. | |
270 | * It has a length field but it uses a non-standard length bias. | |
271 | * It is always 1 dword though, so just treat it as fixed length. | |
272 | */ | |
273 | CMD( MFX_WAIT, SMFX, F, 1, S ), | |
274 | }; | |
275 | ||
276 | static const struct drm_i915_cmd_descriptor vecs_cmds[] = { | |
9c640d1d | 277 | CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), |
86ef630d | 278 | CMD( MI_SET_APPID, SMI, F, 1, S ), |
d4d48035 BV |
279 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, |
280 | .bits = {{ | |
281 | .offset = 0, | |
282 | .mask = MI_GLOBAL_GTT, | |
283 | .expected = 0, | |
284 | }}, ), | |
9c640d1d | 285 | CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), |
b18b396b BV |
286 | CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, |
287 | .bits = {{ | |
288 | .offset = 0, | |
289 | .mask = MI_FLUSH_DW_NOTIFY, | |
290 | .expected = 0, | |
d4d48035 BV |
291 | }, |
292 | { | |
293 | .offset = 1, | |
294 | .mask = MI_FLUSH_DW_USE_GTT, | |
295 | .expected = 0, | |
296 | .condition_offset = 0, | |
297 | .condition_mask = MI_FLUSH_DW_OP_MASK, | |
114d4f70 BV |
298 | }, |
299 | { | |
300 | .offset = 0, | |
301 | .mask = MI_FLUSH_DW_STORE_INDEX, | |
302 | .expected = 0, | |
303 | .condition_offset = 0, | |
304 | .condition_mask = MI_FLUSH_DW_OP_MASK, | |
d4d48035 BV |
305 | }}, ), |
306 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, | |
307 | .bits = {{ | |
308 | .offset = 0, | |
309 | .mask = MI_GLOBAL_GTT, | |
310 | .expected = 0, | |
b18b396b | 311 | }}, ), |
3a6fa984 BV |
312 | }; |
313 | ||
314 | static const struct drm_i915_cmd_descriptor blt_cmds[] = { | |
9c640d1d | 315 | CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), |
d4d48035 BV |
316 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, |
317 | .bits = {{ | |
318 | .offset = 0, | |
319 | .mask = MI_GLOBAL_GTT, | |
320 | .expected = 0, | |
321 | }}, ), | |
9c640d1d | 322 | CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), |
b18b396b BV |
323 | CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, |
324 | .bits = {{ | |
325 | .offset = 0, | |
326 | .mask = MI_FLUSH_DW_NOTIFY, | |
327 | .expected = 0, | |
d4d48035 BV |
328 | }, |
329 | { | |
330 | .offset = 1, | |
331 | .mask = MI_FLUSH_DW_USE_GTT, | |
332 | .expected = 0, | |
333 | .condition_offset = 0, | |
334 | .condition_mask = MI_FLUSH_DW_OP_MASK, | |
114d4f70 BV |
335 | }, |
336 | { | |
337 | .offset = 0, | |
338 | .mask = MI_FLUSH_DW_STORE_INDEX, | |
339 | .expected = 0, | |
340 | .condition_offset = 0, | |
341 | .condition_mask = MI_FLUSH_DW_OP_MASK, | |
b18b396b | 342 | }}, ), |
3a6fa984 BV |
343 | CMD( COLOR_BLT, S2D, !F, 0x3F, S ), |
344 | CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), | |
345 | }; | |
346 | ||
9c640d1d | 347 | static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { |
17c1eb15 | 348 | CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), |
9c640d1d BV |
349 | CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), |
350 | }; | |
351 | ||
3a6fa984 BV |
352 | #undef CMD |
353 | #undef SMI | |
354 | #undef S3D | |
355 | #undef S2D | |
356 | #undef SMFX | |
357 | #undef F | |
358 | #undef S | |
359 | #undef R | |
360 | #undef W | |
361 | #undef B | |
362 | #undef M | |
363 | ||
364 | static const struct drm_i915_cmd_table gen7_render_cmds[] = { | |
365 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
366 | { render_cmds, ARRAY_SIZE(render_cmds) }, | |
367 | }; | |
368 | ||
369 | static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = { | |
370 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
371 | { render_cmds, ARRAY_SIZE(render_cmds) }, | |
372 | { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, | |
373 | }; | |
374 | ||
375 | static const struct drm_i915_cmd_table gen7_video_cmds[] = { | |
376 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
377 | { video_cmds, ARRAY_SIZE(video_cmds) }, | |
378 | }; | |
379 | ||
380 | static const struct drm_i915_cmd_table hsw_vebox_cmds[] = { | |
381 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
382 | { vecs_cmds, ARRAY_SIZE(vecs_cmds) }, | |
383 | }; | |
384 | ||
385 | static const struct drm_i915_cmd_table gen7_blt_cmds[] = { | |
386 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
387 | { blt_cmds, ARRAY_SIZE(blt_cmds) }, | |
388 | }; | |
389 | ||
9c640d1d BV |
390 | static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { |
391 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
392 | { blt_cmds, ARRAY_SIZE(blt_cmds) }, | |
393 | { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, | |
394 | }; | |
395 | ||
5947de9b BV |
396 | /* |
397 | * Register whitelists, sorted by increasing register offset. | |
4e86f725 FJ |
398 | */ |
399 | ||
400 | /* | |
401 | * An individual whitelist entry granting access to register addr. If | |
402 | * mask is non-zero the argument of immediate register writes will be | |
403 | * AND-ed with mask, and the command will be rejected if the result | |
404 | * doesn't match value. | |
405 | * | |
406 | * Registers with non-zero mask are only allowed to be written using | |
407 | * LRI. | |
408 | */ | |
409 | struct drm_i915_reg_descriptor { | |
f0f59a00 | 410 | i915_reg_t addr; |
4e86f725 FJ |
411 | u32 mask; |
412 | u32 value; | |
413 | }; | |
414 | ||
415 | /* Convenience macro for adding 32-bit registers. */ | |
e597ef40 VS |
416 | #define REG32(_reg, ...) \ |
417 | { .addr = (_reg), __VA_ARGS__ } | |
4e86f725 FJ |
418 | |
419 | /* | |
420 | * Convenience macro for adding 64-bit registers. | |
5947de9b BV |
421 | * |
422 | * Some registers that userspace accesses are 64 bits. The register | |
423 | * access commands only allow 32-bit accesses. Hence, we have to include | |
424 | * entries for both halves of the 64-bit registers. | |
425 | */ | |
e597ef40 VS |
426 | #define REG64(_reg) \ |
427 | { .addr = _reg }, \ | |
428 | { .addr = _reg ## _UDW } | |
429 | ||
430 | #define REG64_IDX(_reg, idx) \ | |
431 | { .addr = _reg(idx) }, \ | |
432 | { .addr = _reg ## _UDW(idx) } | |
5947de9b | 433 | |
4e86f725 | 434 | static const struct drm_i915_reg_descriptor gen7_render_regs[] = { |
c61200c2 | 435 | REG64(GPGPU_THREADS_DISPATCHED), |
5947de9b BV |
436 | REG64(HS_INVOCATION_COUNT), |
437 | REG64(DS_INVOCATION_COUNT), | |
438 | REG64(IA_VERTICES_COUNT), | |
439 | REG64(IA_PRIMITIVES_COUNT), | |
440 | REG64(VS_INVOCATION_COUNT), | |
441 | REG64(GS_INVOCATION_COUNT), | |
442 | REG64(GS_PRIMITIVES_COUNT), | |
443 | REG64(CL_INVOCATION_COUNT), | |
444 | REG64(CL_PRIMITIVES_COUNT), | |
445 | REG64(PS_INVOCATION_COUNT), | |
446 | REG64(PS_DEPTH_COUNT), | |
a6573e1f | 447 | REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), |
4e86f725 | 448 | REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */ |
f1f55cc0 NR |
449 | REG64(MI_PREDICATE_SRC0), |
450 | REG64(MI_PREDICATE_SRC1), | |
4e86f725 FJ |
451 | REG32(GEN7_3DPRIM_END_OFFSET), |
452 | REG32(GEN7_3DPRIM_START_VERTEX), | |
453 | REG32(GEN7_3DPRIM_VERTEX_COUNT), | |
454 | REG32(GEN7_3DPRIM_INSTANCE_COUNT), | |
455 | REG32(GEN7_3DPRIM_START_INSTANCE), | |
456 | REG32(GEN7_3DPRIM_BASE_VERTEX), | |
7b9748cb JJ |
457 | REG32(GEN7_GPGPU_DISPATCHDIMX), |
458 | REG32(GEN7_GPGPU_DISPATCHDIMY), | |
459 | REG32(GEN7_GPGPU_DISPATCHDIMZ), | |
e597ef40 VS |
460 | REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0), |
461 | REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1), | |
462 | REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2), | |
463 | REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3), | |
464 | REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0), | |
465 | REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1), | |
466 | REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2), | |
467 | REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3), | |
4e86f725 FJ |
468 | REG32(GEN7_SO_WRITE_OFFSET(0)), |
469 | REG32(GEN7_SO_WRITE_OFFSET(1)), | |
470 | REG32(GEN7_SO_WRITE_OFFSET(2)), | |
471 | REG32(GEN7_SO_WRITE_OFFSET(3)), | |
472 | REG32(GEN7_L3SQCREG1), | |
473 | REG32(GEN7_L3CNTLREG2), | |
474 | REG32(GEN7_L3CNTLREG3), | |
99c5aeca JJ |
475 | }; |
476 | ||
477 | static const struct drm_i915_reg_descriptor hsw_render_regs[] = { | |
1b85066b JJ |
478 | REG64_IDX(HSW_CS_GPR, 0), |
479 | REG64_IDX(HSW_CS_GPR, 1), | |
480 | REG64_IDX(HSW_CS_GPR, 2), | |
481 | REG64_IDX(HSW_CS_GPR, 3), | |
482 | REG64_IDX(HSW_CS_GPR, 4), | |
483 | REG64_IDX(HSW_CS_GPR, 5), | |
484 | REG64_IDX(HSW_CS_GPR, 6), | |
485 | REG64_IDX(HSW_CS_GPR, 7), | |
486 | REG64_IDX(HSW_CS_GPR, 8), | |
487 | REG64_IDX(HSW_CS_GPR, 9), | |
488 | REG64_IDX(HSW_CS_GPR, 10), | |
489 | REG64_IDX(HSW_CS_GPR, 11), | |
490 | REG64_IDX(HSW_CS_GPR, 12), | |
491 | REG64_IDX(HSW_CS_GPR, 13), | |
492 | REG64_IDX(HSW_CS_GPR, 14), | |
493 | REG64_IDX(HSW_CS_GPR, 15), | |
d351f6d9 FJ |
494 | REG32(HSW_SCRATCH1, |
495 | .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, | |
496 | .value = 0), | |
497 | REG32(HSW_ROW_CHICKEN3, | |
498 | .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 | | |
499 | HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), | |
500 | .value = 0), | |
5947de9b BV |
501 | }; |
502 | ||
4e86f725 FJ |
503 | static const struct drm_i915_reg_descriptor gen7_blt_regs[] = { |
504 | REG32(BCS_SWCTRL), | |
5947de9b BV |
505 | }; |
506 | ||
4e86f725 FJ |
507 | static const struct drm_i915_reg_descriptor ivb_master_regs[] = { |
508 | REG32(FORCEWAKE_MT), | |
509 | REG32(DERRMR), | |
510 | REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)), | |
511 | REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)), | |
512 | REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)), | |
220375aa BV |
513 | }; |
514 | ||
4e86f725 FJ |
515 | static const struct drm_i915_reg_descriptor hsw_master_regs[] = { |
516 | REG32(FORCEWAKE_MT), | |
517 | REG32(DERRMR), | |
220375aa BV |
518 | }; |
519 | ||
5947de9b | 520 | #undef REG64 |
4e86f725 | 521 | #undef REG32 |
5947de9b | 522 | |
361b027b JJ |
523 | struct drm_i915_reg_table { |
524 | const struct drm_i915_reg_descriptor *regs; | |
525 | int num_regs; | |
526 | bool master; | |
527 | }; | |
528 | ||
529 | static const struct drm_i915_reg_table ivb_render_reg_tables[] = { | |
530 | { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false }, | |
531 | { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true }, | |
532 | }; | |
533 | ||
534 | static const struct drm_i915_reg_table ivb_blt_reg_tables[] = { | |
535 | { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false }, | |
536 | { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true }, | |
537 | }; | |
538 | ||
539 | static const struct drm_i915_reg_table hsw_render_reg_tables[] = { | |
540 | { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false }, | |
99c5aeca | 541 | { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false }, |
361b027b JJ |
542 | { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true }, |
543 | }; | |
544 | ||
545 | static const struct drm_i915_reg_table hsw_blt_reg_tables[] = { | |
546 | { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false }, | |
547 | { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true }, | |
548 | }; | |
549 | ||
351e3db2 BV |
550 | static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) |
551 | { | |
552 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; | |
553 | u32 subclient = | |
554 | (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; | |
555 | ||
556 | if (client == INSTR_MI_CLIENT) | |
557 | return 0x3F; | |
558 | else if (client == INSTR_RC_CLIENT) { | |
559 | if (subclient == INSTR_MEDIA_SUBCLIENT) | |
560 | return 0xFFFF; | |
561 | else | |
562 | return 0xFF; | |
563 | } | |
564 | ||
565 | DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); | |
566 | return 0; | |
567 | } | |
568 | ||
569 | static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) | |
570 | { | |
571 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; | |
572 | u32 subclient = | |
573 | (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; | |
86ef630d | 574 | u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT; |
351e3db2 BV |
575 | |
576 | if (client == INSTR_MI_CLIENT) | |
577 | return 0x3F; | |
578 | else if (client == INSTR_RC_CLIENT) { | |
86ef630d MN |
579 | if (subclient == INSTR_MEDIA_SUBCLIENT) { |
580 | if (op == 6) | |
581 | return 0xFFFF; | |
582 | else | |
583 | return 0xFFF; | |
584 | } else | |
351e3db2 BV |
585 | return 0xFF; |
586 | } | |
587 | ||
588 | DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); | |
589 | return 0; | |
590 | } | |
591 | ||
592 | static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) | |
593 | { | |
594 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; | |
595 | ||
596 | if (client == INSTR_MI_CLIENT) | |
597 | return 0x3F; | |
598 | else if (client == INSTR_BC_CLIENT) | |
599 | return 0xFF; | |
600 | ||
601 | DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); | |
602 | return 0; | |
603 | } | |
604 | ||
0bc40be8 | 605 | static bool validate_cmds_sorted(struct intel_engine_cs *engine, |
44e895a8 BV |
606 | const struct drm_i915_cmd_table *cmd_tables, |
607 | int cmd_table_count) | |
351e3db2 BV |
608 | { |
609 | int i; | |
300233ee | 610 | bool ret = true; |
351e3db2 | 611 | |
44e895a8 | 612 | if (!cmd_tables || cmd_table_count == 0) |
300233ee | 613 | return true; |
351e3db2 | 614 | |
44e895a8 BV |
615 | for (i = 0; i < cmd_table_count; i++) { |
616 | const struct drm_i915_cmd_table *table = &cmd_tables[i]; | |
351e3db2 BV |
617 | u32 previous = 0; |
618 | int j; | |
619 | ||
620 | for (j = 0; j < table->count; j++) { | |
621 | const struct drm_i915_cmd_descriptor *desc = | |
8453580c | 622 | &table->table[j]; |
351e3db2 BV |
623 | u32 curr = desc->cmd.value & desc->cmd.mask; |
624 | ||
300233ee | 625 | if (curr < previous) { |
351e3db2 | 626 | DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n", |
0bc40be8 | 627 | engine->id, i, j, curr, previous); |
300233ee BV |
628 | ret = false; |
629 | } | |
351e3db2 BV |
630 | |
631 | previous = curr; | |
632 | } | |
633 | } | |
300233ee BV |
634 | |
635 | return ret; | |
351e3db2 BV |
636 | } |
637 | ||
4e86f725 FJ |
638 | static bool check_sorted(int ring_id, |
639 | const struct drm_i915_reg_descriptor *reg_table, | |
640 | int reg_count) | |
351e3db2 BV |
641 | { |
642 | int i; | |
643 | u32 previous = 0; | |
300233ee | 644 | bool ret = true; |
351e3db2 BV |
645 | |
646 | for (i = 0; i < reg_count; i++) { | |
f0f59a00 | 647 | u32 curr = i915_mmio_reg_offset(reg_table[i].addr); |
351e3db2 | 648 | |
300233ee | 649 | if (curr < previous) { |
351e3db2 BV |
650 | DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n", |
651 | ring_id, i, curr, previous); | |
300233ee BV |
652 | ret = false; |
653 | } | |
351e3db2 BV |
654 | |
655 | previous = curr; | |
656 | } | |
300233ee BV |
657 | |
658 | return ret; | |
351e3db2 BV |
659 | } |
660 | ||
0bc40be8 | 661 | static bool validate_regs_sorted(struct intel_engine_cs *engine) |
351e3db2 | 662 | { |
361b027b JJ |
663 | int i; |
664 | const struct drm_i915_reg_table *table; | |
665 | ||
666 | for (i = 0; i < engine->reg_table_count; i++) { | |
667 | table = &engine->reg_tables[i]; | |
668 | if (!check_sorted(engine->id, table->regs, table->num_regs)) | |
669 | return false; | |
670 | } | |
671 | ||
672 | return true; | |
351e3db2 BV |
673 | } |
674 | ||
44e895a8 BV |
675 | struct cmd_node { |
676 | const struct drm_i915_cmd_descriptor *desc; | |
677 | struct hlist_node node; | |
678 | }; | |
679 | ||
680 | /* | |
681 | * Different command ranges have different numbers of bits for the opcode. For | |
682 | * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The | |
683 | * problem is that, for example, MI commands use bits 22:16 for other fields | |
684 | * such as GGTT vs PPGTT bits. If we include those bits in the mask then when | |
685 | * we mask a command from a batch it could hash to the wrong bucket due to | |
686 | * non-opcode bits being set. But if we don't include those bits, some 3D | |
687 | * commands may hash to the same bucket due to not including opcode bits that | |
688 | * make the command unique. For now, we will risk hashing to the same bucket. | |
689 | * | |
690 | * If we attempt to generate a perfect hash, we should be able to look at bits | |
691 | * 31:29 of a command from a batch buffer and use the full mask for that | |
692 | * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this. | |
693 | */ | |
694 | #define CMD_HASH_MASK STD_MI_OPCODE_MASK | |
695 | ||
0bc40be8 | 696 | static int init_hash_table(struct intel_engine_cs *engine, |
44e895a8 BV |
697 | const struct drm_i915_cmd_table *cmd_tables, |
698 | int cmd_table_count) | |
699 | { | |
700 | int i, j; | |
701 | ||
0bc40be8 | 702 | hash_init(engine->cmd_hash); |
44e895a8 BV |
703 | |
704 | for (i = 0; i < cmd_table_count; i++) { | |
705 | const struct drm_i915_cmd_table *table = &cmd_tables[i]; | |
706 | ||
707 | for (j = 0; j < table->count; j++) { | |
708 | const struct drm_i915_cmd_descriptor *desc = | |
709 | &table->table[j]; | |
710 | struct cmd_node *desc_node = | |
711 | kmalloc(sizeof(*desc_node), GFP_KERNEL); | |
712 | ||
713 | if (!desc_node) | |
714 | return -ENOMEM; | |
715 | ||
716 | desc_node->desc = desc; | |
0bc40be8 | 717 | hash_add(engine->cmd_hash, &desc_node->node, |
44e895a8 BV |
718 | desc->cmd.value & CMD_HASH_MASK); |
719 | } | |
720 | } | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
0bc40be8 | 725 | static void fini_hash_table(struct intel_engine_cs *engine) |
44e895a8 BV |
726 | { |
727 | struct hlist_node *tmp; | |
728 | struct cmd_node *desc_node; | |
729 | int i; | |
730 | ||
0bc40be8 | 731 | hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) { |
44e895a8 BV |
732 | hash_del(&desc_node->node); |
733 | kfree(desc_node); | |
734 | } | |
735 | } | |
736 | ||
351e3db2 BV |
737 | /** |
738 | * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer | |
739 | * @ring: the ringbuffer to initialize | |
740 | * | |
741 | * Optionally initializes fields related to batch buffer command parsing in the | |
a4872ba6 | 742 | * struct intel_engine_cs based on whether the platform requires software |
351e3db2 | 743 | * command parsing. |
44e895a8 BV |
744 | * |
745 | * Return: non-zero if initialization fails | |
351e3db2 | 746 | */ |
0bc40be8 | 747 | int i915_cmd_parser_init_ring(struct intel_engine_cs *engine) |
351e3db2 | 748 | { |
44e895a8 BV |
749 | const struct drm_i915_cmd_table *cmd_tables; |
750 | int cmd_table_count; | |
751 | int ret; | |
752 | ||
0bc40be8 | 753 | if (!IS_GEN7(engine->dev)) |
44e895a8 | 754 | return 0; |
351e3db2 | 755 | |
0bc40be8 | 756 | switch (engine->id) { |
351e3db2 | 757 | case RCS: |
0bc40be8 | 758 | if (IS_HASWELL(engine->dev)) { |
44e895a8 BV |
759 | cmd_tables = hsw_render_ring_cmds; |
760 | cmd_table_count = | |
3a6fa984 BV |
761 | ARRAY_SIZE(hsw_render_ring_cmds); |
762 | } else { | |
44e895a8 BV |
763 | cmd_tables = gen7_render_cmds; |
764 | cmd_table_count = ARRAY_SIZE(gen7_render_cmds); | |
3a6fa984 BV |
765 | } |
766 | ||
0bc40be8 | 767 | if (IS_HASWELL(engine->dev)) { |
361b027b JJ |
768 | engine->reg_tables = hsw_render_reg_tables; |
769 | engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables); | |
220375aa | 770 | } else { |
361b027b JJ |
771 | engine->reg_tables = ivb_render_reg_tables; |
772 | engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables); | |
220375aa BV |
773 | } |
774 | ||
0bc40be8 | 775 | engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask; |
351e3db2 BV |
776 | break; |
777 | case VCS: | |
44e895a8 BV |
778 | cmd_tables = gen7_video_cmds; |
779 | cmd_table_count = ARRAY_SIZE(gen7_video_cmds); | |
0bc40be8 | 780 | engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; |
351e3db2 BV |
781 | break; |
782 | case BCS: | |
0bc40be8 | 783 | if (IS_HASWELL(engine->dev)) { |
44e895a8 BV |
784 | cmd_tables = hsw_blt_ring_cmds; |
785 | cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds); | |
9c640d1d | 786 | } else { |
44e895a8 BV |
787 | cmd_tables = gen7_blt_cmds; |
788 | cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); | |
9c640d1d BV |
789 | } |
790 | ||
0bc40be8 | 791 | if (IS_HASWELL(engine->dev)) { |
361b027b JJ |
792 | engine->reg_tables = hsw_blt_reg_tables; |
793 | engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables); | |
220375aa | 794 | } else { |
361b027b JJ |
795 | engine->reg_tables = ivb_blt_reg_tables; |
796 | engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables); | |
220375aa BV |
797 | } |
798 | ||
0bc40be8 | 799 | engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; |
351e3db2 BV |
800 | break; |
801 | case VECS: | |
44e895a8 BV |
802 | cmd_tables = hsw_vebox_cmds; |
803 | cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds); | |
351e3db2 | 804 | /* VECS can use the same length_mask function as VCS */ |
0bc40be8 | 805 | engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; |
351e3db2 BV |
806 | break; |
807 | default: | |
808 | DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n", | |
0bc40be8 | 809 | engine->id); |
351e3db2 BV |
810 | BUG(); |
811 | } | |
812 | ||
0bc40be8 TU |
813 | BUG_ON(!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)); |
814 | BUG_ON(!validate_regs_sorted(engine)); | |
44e895a8 | 815 | |
0bc40be8 | 816 | WARN_ON(!hash_empty(engine->cmd_hash)); |
bfc882b4 | 817 | |
0bc40be8 | 818 | ret = init_hash_table(engine, cmd_tables, cmd_table_count); |
bfc882b4 DV |
819 | if (ret) { |
820 | DRM_ERROR("CMD: cmd_parser_init failed!\n"); | |
0bc40be8 | 821 | fini_hash_table(engine); |
bfc882b4 | 822 | return ret; |
44e895a8 BV |
823 | } |
824 | ||
0bc40be8 | 825 | engine->needs_cmd_parser = true; |
44e895a8 BV |
826 | |
827 | return 0; | |
828 | } | |
829 | ||
830 | /** | |
831 | * i915_cmd_parser_fini_ring() - clean up cmd parser related fields | |
832 | * @ring: the ringbuffer to clean up | |
833 | * | |
834 | * Releases any resources related to command parsing that may have been | |
835 | * initialized for the specified ring. | |
836 | */ | |
0bc40be8 | 837 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine) |
44e895a8 | 838 | { |
0bc40be8 | 839 | if (!engine->needs_cmd_parser) |
44e895a8 BV |
840 | return; |
841 | ||
0bc40be8 | 842 | fini_hash_table(engine); |
351e3db2 BV |
843 | } |
844 | ||
845 | static const struct drm_i915_cmd_descriptor* | |
0bc40be8 | 846 | find_cmd_in_table(struct intel_engine_cs *engine, |
351e3db2 BV |
847 | u32 cmd_header) |
848 | { | |
44e895a8 | 849 | struct cmd_node *desc_node; |
351e3db2 | 850 | |
0bc40be8 | 851 | hash_for_each_possible(engine->cmd_hash, desc_node, node, |
44e895a8 BV |
852 | cmd_header & CMD_HASH_MASK) { |
853 | const struct drm_i915_cmd_descriptor *desc = desc_node->desc; | |
351e3db2 BV |
854 | u32 masked_cmd = desc->cmd.mask & cmd_header; |
855 | u32 masked_value = desc->cmd.value & desc->cmd.mask; | |
856 | ||
857 | if (masked_cmd == masked_value) | |
858 | return desc; | |
859 | } | |
860 | ||
861 | return NULL; | |
862 | } | |
863 | ||
864 | /* | |
865 | * Returns a pointer to a descriptor for the command specified by cmd_header. | |
866 | * | |
867 | * The caller must supply space for a default descriptor via the default_desc | |
868 | * parameter. If no descriptor for the specified command exists in the ring's | |
869 | * command parser tables, this function fills in default_desc based on the | |
870 | * ring's default length encoding and returns default_desc. | |
871 | */ | |
872 | static const struct drm_i915_cmd_descriptor* | |
0bc40be8 | 873 | find_cmd(struct intel_engine_cs *engine, |
351e3db2 BV |
874 | u32 cmd_header, |
875 | struct drm_i915_cmd_descriptor *default_desc) | |
876 | { | |
44e895a8 | 877 | const struct drm_i915_cmd_descriptor *desc; |
351e3db2 | 878 | u32 mask; |
351e3db2 | 879 | |
0bc40be8 | 880 | desc = find_cmd_in_table(engine, cmd_header); |
44e895a8 BV |
881 | if (desc) |
882 | return desc; | |
351e3db2 | 883 | |
0bc40be8 | 884 | mask = engine->get_cmd_length_mask(cmd_header); |
351e3db2 BV |
885 | if (!mask) |
886 | return NULL; | |
887 | ||
888 | BUG_ON(!default_desc); | |
889 | default_desc->flags = CMD_DESC_SKIP; | |
890 | default_desc->length.mask = mask; | |
891 | ||
892 | return default_desc; | |
893 | } | |
894 | ||
4e86f725 FJ |
895 | static const struct drm_i915_reg_descriptor * |
896 | find_reg(const struct drm_i915_reg_descriptor *table, | |
897 | int count, u32 addr) | |
351e3db2 | 898 | { |
361b027b | 899 | int i; |
351e3db2 | 900 | |
361b027b JJ |
901 | for (i = 0; i < count; i++) { |
902 | if (i915_mmio_reg_offset(table[i].addr) == addr) | |
903 | return &table[i]; | |
904 | } | |
905 | ||
906 | return NULL; | |
907 | } | |
908 | ||
909 | static const struct drm_i915_reg_descriptor * | |
910 | find_reg_in_tables(const struct drm_i915_reg_table *tables, | |
911 | int count, bool is_master, u32 addr) | |
912 | { | |
913 | int i; | |
914 | const struct drm_i915_reg_table *table; | |
915 | const struct drm_i915_reg_descriptor *reg; | |
916 | ||
917 | for (i = 0; i < count; i++) { | |
918 | table = &tables[i]; | |
919 | if (!table->master || is_master) { | |
920 | reg = find_reg(table->regs, table->num_regs, | |
921 | addr); | |
922 | if (reg != NULL) | |
923 | return reg; | |
351e3db2 BV |
924 | } |
925 | } | |
926 | ||
4e86f725 | 927 | return NULL; |
351e3db2 BV |
928 | } |
929 | ||
17cabf57 CW |
930 | static u32 *vmap_batch(struct drm_i915_gem_object *obj, |
931 | unsigned start, unsigned len) | |
351e3db2 BV |
932 | { |
933 | int i; | |
934 | void *addr = NULL; | |
935 | struct sg_page_iter sg_iter; | |
17cabf57 CW |
936 | int first_page = start >> PAGE_SHIFT; |
937 | int last_page = (len + start + 4095) >> PAGE_SHIFT; | |
938 | int npages = last_page - first_page; | |
351e3db2 BV |
939 | struct page **pages; |
940 | ||
17cabf57 | 941 | pages = drm_malloc_ab(npages, sizeof(*pages)); |
351e3db2 BV |
942 | if (pages == NULL) { |
943 | DRM_DEBUG_DRIVER("Failed to get space for pages\n"); | |
944 | goto finish; | |
945 | } | |
946 | ||
947 | i = 0; | |
72c5ba95 | 948 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, first_page) { |
17cabf57 | 949 | pages[i++] = sg_page_iter_page(&sg_iter); |
72c5ba95 MK |
950 | if (i == npages) |
951 | break; | |
952 | } | |
351e3db2 BV |
953 | |
954 | addr = vmap(pages, i, 0, PAGE_KERNEL); | |
955 | if (addr == NULL) { | |
956 | DRM_DEBUG_DRIVER("Failed to vmap pages\n"); | |
957 | goto finish; | |
958 | } | |
959 | ||
960 | finish: | |
961 | if (pages) | |
962 | drm_free_large(pages); | |
963 | return (u32*)addr; | |
964 | } | |
965 | ||
78a42377 BV |
966 | /* Returns a vmap'd pointer to dest_obj, which the caller must unmap */ |
967 | static u32 *copy_batch(struct drm_i915_gem_object *dest_obj, | |
b9ffd80e BV |
968 | struct drm_i915_gem_object *src_obj, |
969 | u32 batch_start_offset, | |
970 | u32 batch_len) | |
78a42377 | 971 | { |
78a42377 | 972 | int needs_clflush = 0; |
17cabf57 CW |
973 | void *src_base, *src; |
974 | void *dst = NULL; | |
975 | int ret; | |
b9ffd80e | 976 | |
17cabf57 CW |
977 | if (batch_len > dest_obj->base.size || |
978 | batch_len + batch_start_offset > src_obj->base.size) | |
b9ffd80e | 979 | return ERR_PTR(-E2BIG); |
78a42377 | 980 | |
de4e783a CW |
981 | if (WARN_ON(dest_obj->pages_pin_count == 0)) |
982 | return ERR_PTR(-ENODEV); | |
983 | ||
78a42377 BV |
984 | ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush); |
985 | if (ret) { | |
17cabf57 | 986 | DRM_DEBUG_DRIVER("CMD: failed to prepare shadow batch\n"); |
78a42377 BV |
987 | return ERR_PTR(ret); |
988 | } | |
989 | ||
17cabf57 | 990 | src_base = vmap_batch(src_obj, batch_start_offset, batch_len); |
b9ffd80e | 991 | if (!src_base) { |
78a42377 BV |
992 | DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n"); |
993 | ret = -ENOMEM; | |
994 | goto unpin_src; | |
995 | } | |
996 | ||
78a42377 BV |
997 | ret = i915_gem_object_set_to_cpu_domain(dest_obj, true); |
998 | if (ret) { | |
17cabf57 | 999 | DRM_DEBUG_DRIVER("CMD: Failed to set shadow batch to CPU\n"); |
78a42377 BV |
1000 | goto unmap_src; |
1001 | } | |
1002 | ||
17cabf57 CW |
1003 | dst = vmap_batch(dest_obj, 0, batch_len); |
1004 | if (!dst) { | |
78a42377 BV |
1005 | DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n"); |
1006 | ret = -ENOMEM; | |
1007 | goto unmap_src; | |
1008 | } | |
1009 | ||
17cabf57 CW |
1010 | src = src_base + offset_in_page(batch_start_offset); |
1011 | if (needs_clflush) | |
1012 | drm_clflush_virt_range(src, batch_len); | |
b9ffd80e | 1013 | |
17cabf57 | 1014 | memcpy(dst, src, batch_len); |
78a42377 BV |
1015 | |
1016 | unmap_src: | |
b9ffd80e | 1017 | vunmap(src_base); |
78a42377 BV |
1018 | unpin_src: |
1019 | i915_gem_object_unpin_pages(src_obj); | |
1020 | ||
17cabf57 | 1021 | return ret ? ERR_PTR(ret) : dst; |
78a42377 BV |
1022 | } |
1023 | ||
351e3db2 BV |
1024 | /** |
1025 | * i915_needs_cmd_parser() - should a given ring use software command parsing? | |
1026 | * @ring: the ring in question | |
1027 | * | |
1028 | * Only certain platforms require software batch buffer command parsing, and | |
32197aab | 1029 | * only when enabled via module parameter. |
351e3db2 BV |
1030 | * |
1031 | * Return: true if the ring requires software command parsing | |
1032 | */ | |
0bc40be8 | 1033 | bool i915_needs_cmd_parser(struct intel_engine_cs *engine) |
351e3db2 | 1034 | { |
0bc40be8 | 1035 | if (!engine->needs_cmd_parser) |
351e3db2 BV |
1036 | return false; |
1037 | ||
0bc40be8 | 1038 | if (!USES_PPGTT(engine->dev)) |
d4d48035 BV |
1039 | return false; |
1040 | ||
351e3db2 BV |
1041 | return (i915.enable_cmd_parser == 1); |
1042 | } | |
1043 | ||
0bc40be8 | 1044 | static bool check_cmd(const struct intel_engine_cs *engine, |
b651000b | 1045 | const struct drm_i915_cmd_descriptor *desc, |
6a65c5b9 | 1046 | const u32 *cmd, u32 length, |
6e66ea13 BV |
1047 | const bool is_master, |
1048 | bool *oacontrol_set) | |
b651000b BV |
1049 | { |
1050 | if (desc->flags & CMD_DESC_REJECT) { | |
1051 | DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); | |
1052 | return false; | |
1053 | } | |
1054 | ||
1055 | if ((desc->flags & CMD_DESC_MASTER) && !is_master) { | |
1056 | DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n", | |
1057 | *cmd); | |
1058 | return false; | |
1059 | } | |
1060 | ||
1061 | if (desc->flags & CMD_DESC_REGISTER) { | |
6e66ea13 | 1062 | /* |
6a65c5b9 FJ |
1063 | * Get the distance between individual register offset |
1064 | * fields if the command can perform more than one | |
1065 | * access at a time. | |
6e66ea13 | 1066 | */ |
6a65c5b9 FJ |
1067 | const u32 step = desc->reg.step ? desc->reg.step : length; |
1068 | u32 offset; | |
1069 | ||
1070 | for (offset = desc->reg.offset; offset < length; | |
1071 | offset += step) { | |
1072 | const u32 reg_addr = cmd[offset] & desc->reg.mask; | |
4e86f725 | 1073 | const struct drm_i915_reg_descriptor *reg = |
361b027b JJ |
1074 | find_reg_in_tables(engine->reg_tables, |
1075 | engine->reg_table_count, | |
1076 | is_master, | |
1077 | reg_addr); | |
4e86f725 FJ |
1078 | |
1079 | if (!reg) { | |
1080 | DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n", | |
0bc40be8 | 1081 | reg_addr, *cmd, engine->id); |
4e86f725 FJ |
1082 | return false; |
1083 | } | |
6a65c5b9 FJ |
1084 | |
1085 | /* | |
1086 | * OACONTROL requires some special handling for | |
1087 | * writes. We want to make sure that any batch which | |
1088 | * enables OA also disables it before the end of the | |
1089 | * batch. The goal is to prevent one process from | |
1090 | * snooping on the perf data from another process. To do | |
1091 | * that, we need to check the value that will be written | |
1092 | * to the register. Hence, limit OACONTROL writes to | |
1093 | * only MI_LOAD_REGISTER_IMM commands. | |
1094 | */ | |
f0f59a00 | 1095 | if (reg_addr == i915_mmio_reg_offset(OACONTROL)) { |
f1afe24f | 1096 | if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { |
6a65c5b9 FJ |
1097 | DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n"); |
1098 | return false; | |
1099 | } | |
1100 | ||
1101 | if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) | |
1102 | *oacontrol_set = (cmd[offset + 1] != 0); | |
00caf019 | 1103 | } |
6e66ea13 | 1104 | |
4e86f725 FJ |
1105 | /* |
1106 | * Check the value written to the register against the | |
1107 | * allowed mask/value pair given in the whitelist entry. | |
1108 | */ | |
1109 | if (reg->mask) { | |
f1afe24f | 1110 | if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { |
4e86f725 FJ |
1111 | DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n", |
1112 | reg_addr); | |
1113 | return false; | |
1114 | } | |
1115 | ||
1116 | if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && | |
1117 | (offset + 2 > length || | |
1118 | (cmd[offset + 1] & reg->mask) != reg->value)) { | |
1119 | DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n", | |
1120 | reg_addr); | |
6a65c5b9 FJ |
1121 | return false; |
1122 | } | |
b651000b BV |
1123 | } |
1124 | } | |
1125 | } | |
1126 | ||
1127 | if (desc->flags & CMD_DESC_BITMASK) { | |
1128 | int i; | |
1129 | ||
1130 | for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { | |
1131 | u32 dword; | |
1132 | ||
1133 | if (desc->bits[i].mask == 0) | |
1134 | break; | |
1135 | ||
1136 | if (desc->bits[i].condition_mask != 0) { | |
1137 | u32 offset = | |
1138 | desc->bits[i].condition_offset; | |
1139 | u32 condition = cmd[offset] & | |
1140 | desc->bits[i].condition_mask; | |
1141 | ||
1142 | if (condition == 0) | |
1143 | continue; | |
1144 | } | |
1145 | ||
1146 | dword = cmd[desc->bits[i].offset] & | |
1147 | desc->bits[i].mask; | |
1148 | ||
1149 | if (dword != desc->bits[i].expected) { | |
1150 | DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n", | |
1151 | *cmd, | |
1152 | desc->bits[i].mask, | |
1153 | desc->bits[i].expected, | |
0bc40be8 | 1154 | dword, engine->id); |
b651000b BV |
1155 | return false; |
1156 | } | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | return true; | |
1161 | } | |
1162 | ||
351e3db2 BV |
1163 | #define LENGTH_BIAS 2 |
1164 | ||
1165 | /** | |
1166 | * i915_parse_cmds() - parse a submitted batch buffer for privilege violations | |
1167 | * @ring: the ring on which the batch is to execute | |
1168 | * @batch_obj: the batch buffer in question | |
78a42377 | 1169 | * @shadow_batch_obj: copy of the batch buffer in question |
351e3db2 | 1170 | * @batch_start_offset: byte offset in the batch at which execution starts |
b9ffd80e | 1171 | * @batch_len: length of the commands in batch_obj |
351e3db2 BV |
1172 | * @is_master: is the submitting process the drm master? |
1173 | * | |
1174 | * Parses the specified batch buffer looking for privilege violations as | |
1175 | * described in the overview. | |
1176 | * | |
42c7156a BV |
1177 | * Return: non-zero if the parser finds violations or otherwise fails; -EACCES |
1178 | * if the batch appears legal but should use hardware parsing | |
351e3db2 | 1179 | */ |
0bc40be8 | 1180 | int i915_parse_cmds(struct intel_engine_cs *engine, |
351e3db2 | 1181 | struct drm_i915_gem_object *batch_obj, |
78a42377 | 1182 | struct drm_i915_gem_object *shadow_batch_obj, |
351e3db2 | 1183 | u32 batch_start_offset, |
b9ffd80e | 1184 | u32 batch_len, |
351e3db2 BV |
1185 | bool is_master) |
1186 | { | |
351e3db2 BV |
1187 | u32 *cmd, *batch_base, *batch_end; |
1188 | struct drm_i915_cmd_descriptor default_desc = { 0 }; | |
6e66ea13 | 1189 | bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */ |
17cabf57 | 1190 | int ret = 0; |
71745376 | 1191 | |
b9ffd80e BV |
1192 | batch_base = copy_batch(shadow_batch_obj, batch_obj, |
1193 | batch_start_offset, batch_len); | |
78a42377 BV |
1194 | if (IS_ERR(batch_base)) { |
1195 | DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n"); | |
1196 | return PTR_ERR(batch_base); | |
351e3db2 BV |
1197 | } |
1198 | ||
78a42377 | 1199 | /* |
b9ffd80e | 1200 | * We use the batch length as size because the shadow object is as |
78a42377 BV |
1201 | * large or larger and copy_batch() will write MI_NOPs to the extra |
1202 | * space. Parsing should be faster in some cases this way. | |
1203 | */ | |
17cabf57 | 1204 | batch_end = batch_base + (batch_len / sizeof(*batch_end)); |
351e3db2 | 1205 | |
17cabf57 | 1206 | cmd = batch_base; |
351e3db2 BV |
1207 | while (cmd < batch_end) { |
1208 | const struct drm_i915_cmd_descriptor *desc; | |
1209 | u32 length; | |
1210 | ||
1211 | if (*cmd == MI_BATCH_BUFFER_END) | |
1212 | break; | |
1213 | ||
0bc40be8 | 1214 | desc = find_cmd(engine, *cmd, &default_desc); |
351e3db2 BV |
1215 | if (!desc) { |
1216 | DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n", | |
1217 | *cmd); | |
1218 | ret = -EINVAL; | |
1219 | break; | |
1220 | } | |
1221 | ||
42c7156a BV |
1222 | /* |
1223 | * If the batch buffer contains a chained batch, return an | |
1224 | * error that tells the caller to abort and dispatch the | |
1225 | * workload as a non-secure batch. | |
1226 | */ | |
1227 | if (desc->cmd.value == MI_BATCH_BUFFER_START) { | |
1228 | ret = -EACCES; | |
1229 | break; | |
1230 | } | |
1231 | ||
351e3db2 BV |
1232 | if (desc->flags & CMD_DESC_FIXED) |
1233 | length = desc->length.fixed; | |
1234 | else | |
1235 | length = ((*cmd & desc->length.mask) + LENGTH_BIAS); | |
1236 | ||
1237 | if ((batch_end - cmd) < length) { | |
86a25121 | 1238 | DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", |
351e3db2 BV |
1239 | *cmd, |
1240 | length, | |
4b6eab59 | 1241 | batch_end - cmd); |
351e3db2 BV |
1242 | ret = -EINVAL; |
1243 | break; | |
1244 | } | |
1245 | ||
0bc40be8 | 1246 | if (!check_cmd(engine, desc, cmd, length, is_master, |
6a65c5b9 | 1247 | &oacontrol_set)) { |
351e3db2 BV |
1248 | ret = -EINVAL; |
1249 | break; | |
1250 | } | |
1251 | ||
351e3db2 BV |
1252 | cmd += length; |
1253 | } | |
1254 | ||
6e66ea13 BV |
1255 | if (oacontrol_set) { |
1256 | DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n"); | |
1257 | ret = -EINVAL; | |
1258 | } | |
1259 | ||
351e3db2 BV |
1260 | if (cmd >= batch_end) { |
1261 | DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); | |
1262 | ret = -EINVAL; | |
1263 | } | |
1264 | ||
1265 | vunmap(batch_base); | |
1266 | ||
351e3db2 BV |
1267 | return ret; |
1268 | } | |
d728c8ef BV |
1269 | |
1270 | /** | |
1271 | * i915_cmd_parser_get_version() - get the cmd parser version number | |
1272 | * | |
1273 | * The cmd parser maintains a simple increasing integer version number suitable | |
1274 | * for passing to userspace clients to determine what operations are permitted. | |
1275 | * | |
1276 | * Return: the current version number of the cmd parser | |
1277 | */ | |
1278 | int i915_cmd_parser_get_version(void) | |
1279 | { | |
1280 | /* | |
1281 | * Command parser version history | |
1282 | * | |
1283 | * 1. Initial version. Checks batches and reports violations, but leaves | |
1284 | * hardware parsing enabled (so does not allow new use cases). | |
f1f55cc0 NR |
1285 | * 2. Allow access to the MI_PREDICATE_SRC0 and |
1286 | * MI_PREDICATE_SRC1 registers. | |
c61200c2 | 1287 | * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. |
2bbe6bbb | 1288 | * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. |
7b9748cb | 1289 | * 5. GPGPU dispatch compute indirect registers. |
6cf0716c | 1290 | * 6. TIMESTAMP register and Haswell CS GPR registers |
d728c8ef | 1291 | */ |
6cf0716c | 1292 | return 6; |
d728c8ef | 1293 | } |