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351e3db2 BV |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Brad Volkin <bradley.d.volkin@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | ||
30 | /** | |
31 | * DOC: i915 batch buffer command parser | |
32 | * | |
33 | * Motivation: | |
34 | * Certain OpenGL features (e.g. transform feedback, performance monitoring) | |
35 | * require userspace code to submit batches containing commands such as | |
36 | * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some | |
37 | * generations of the hardware will noop these commands in "unsecure" batches | |
38 | * (which includes all userspace batches submitted via i915) even though the | |
39 | * commands may be safe and represent the intended programming model of the | |
40 | * device. | |
41 | * | |
42 | * The software command parser is similar in operation to the command parsing | |
43 | * done in hardware for unsecure batches. However, the software parser allows | |
44 | * some operations that would be noop'd by hardware, if the parser determines | |
45 | * the operation is safe, and submits the batch as "secure" to prevent hardware | |
46 | * parsing. | |
47 | * | |
48 | * Threats: | |
49 | * At a high level, the hardware (and software) checks attempt to prevent | |
50 | * granting userspace undue privileges. There are three categories of privilege. | |
51 | * | |
52 | * First, commands which are explicitly defined as privileged or which should | |
53 | * only be used by the kernel driver. The parser generally rejects such | |
54 | * commands, though it may allow some from the drm master process. | |
55 | * | |
56 | * Second, commands which access registers. To support correct/enhanced | |
57 | * userspace functionality, particularly certain OpenGL extensions, the parser | |
58 | * provides a whitelist of registers which userspace may safely access (for both | |
59 | * normal and drm master processes). | |
60 | * | |
61 | * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). | |
62 | * The parser always rejects such commands. | |
63 | * | |
64 | * The majority of the problematic commands fall in the MI_* range, with only a | |
65 | * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW). | |
66 | * | |
67 | * Implementation: | |
68 | * Each ring maintains tables of commands and registers which the parser uses in | |
69 | * scanning batch buffers submitted to that ring. | |
70 | * | |
71 | * Since the set of commands that the parser must check for is significantly | |
72 | * smaller than the number of commands supported, the parser tables contain only | |
73 | * those commands required by the parser. This generally works because command | |
74 | * opcode ranges have standard command length encodings. So for commands that | |
75 | * the parser does not need to check, it can easily skip them. This is | |
76 | * implementated via a per-ring length decoding vfunc. | |
77 | * | |
78 | * Unfortunately, there are a number of commands that do not follow the standard | |
79 | * length encoding for their opcode range, primarily amongst the MI_* commands. | |
80 | * To handle this, the parser provides a way to define explicit "skip" entries | |
81 | * in the per-ring command tables. | |
82 | * | |
83 | * Other command table entries map fairly directly to high level categories | |
84 | * mentioned above: rejected, master-only, register whitelist. The parser | |
85 | * implements a number of checks, including the privileged memory checks, via a | |
86 | * general bitmasking mechanism. | |
87 | */ | |
88 | ||
3a6fa984 BV |
89 | #define STD_MI_OPCODE_MASK 0xFF800000 |
90 | #define STD_3D_OPCODE_MASK 0xFFFF0000 | |
91 | #define STD_2D_OPCODE_MASK 0xFFC00000 | |
92 | #define STD_MFX_OPCODE_MASK 0xFFFF0000 | |
93 | ||
94 | #define CMD(op, opm, f, lm, fl, ...) \ | |
95 | { \ | |
96 | .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ | |
97 | .cmd = { (op), (opm) }, \ | |
98 | .length = { (lm) }, \ | |
99 | __VA_ARGS__ \ | |
100 | } | |
101 | ||
102 | /* Convenience macros to compress the tables */ | |
103 | #define SMI STD_MI_OPCODE_MASK | |
104 | #define S3D STD_3D_OPCODE_MASK | |
105 | #define S2D STD_2D_OPCODE_MASK | |
106 | #define SMFX STD_MFX_OPCODE_MASK | |
107 | #define F true | |
108 | #define S CMD_DESC_SKIP | |
109 | #define R CMD_DESC_REJECT | |
110 | #define W CMD_DESC_REGISTER | |
111 | #define B CMD_DESC_BITMASK | |
112 | #define M CMD_DESC_MASTER | |
113 | ||
114 | /* Command Mask Fixed Len Action | |
115 | ---------------------------------------------------------- */ | |
116 | static const struct drm_i915_cmd_descriptor common_cmds[] = { | |
117 | CMD( MI_NOOP, SMI, F, 1, S ), | |
b18b396b | 118 | CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), |
17c1eb15 | 119 | CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ), |
3a6fa984 BV |
120 | CMD( MI_ARB_CHECK, SMI, F, 1, S ), |
121 | CMD( MI_REPORT_HEAD, SMI, F, 1, S ), | |
122 | CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), | |
9c640d1d BV |
123 | CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), |
124 | CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), | |
f0a346bd BV |
125 | CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, |
126 | .reg = { .offset = 1, .mask = 0x007FFFFC } ), | |
d4d48035 BV |
127 | CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W | B, |
128 | .reg = { .offset = 1, .mask = 0x007FFFFC }, | |
129 | .bits = {{ | |
130 | .offset = 0, | |
131 | .mask = MI_GLOBAL_GTT, | |
132 | .expected = 0, | |
133 | }}, ), | |
134 | CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W | B, | |
135 | .reg = { .offset = 1, .mask = 0x007FFFFC }, | |
136 | .bits = {{ | |
137 | .offset = 0, | |
138 | .mask = MI_GLOBAL_GTT, | |
139 | .expected = 0, | |
140 | }}, ), | |
3a6fa984 BV |
141 | CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), |
142 | }; | |
143 | ||
144 | static const struct drm_i915_cmd_descriptor render_cmds[] = { | |
145 | CMD( MI_FLUSH, SMI, F, 1, S ), | |
9c640d1d | 146 | CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), |
3a6fa984 BV |
147 | CMD( MI_PREDICATE, SMI, F, 1, S ), |
148 | CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), | |
9c640d1d BV |
149 | CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), |
150 | CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), | |
3a6fa984 | 151 | CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), |
d4d48035 BV |
152 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, |
153 | .bits = {{ | |
154 | .offset = 0, | |
155 | .mask = MI_GLOBAL_GTT, | |
156 | .expected = 0, | |
157 | }}, ), | |
9c640d1d | 158 | CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), |
d4d48035 BV |
159 | CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, |
160 | .bits = {{ | |
161 | .offset = 0, | |
162 | .mask = MI_GLOBAL_GTT, | |
163 | .expected = 0, | |
164 | }}, ), | |
165 | CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, | |
166 | .bits = {{ | |
167 | .offset = 1, | |
168 | .mask = MI_REPORT_PERF_COUNT_GGTT, | |
169 | .expected = 0, | |
170 | }}, ), | |
171 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, | |
172 | .bits = {{ | |
173 | .offset = 0, | |
174 | .mask = MI_GLOBAL_GTT, | |
175 | .expected = 0, | |
176 | }}, ), | |
3a6fa984 BV |
177 | CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), |
178 | CMD( PIPELINE_SELECT, S3D, F, 1, S ), | |
f0a346bd BV |
179 | CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, |
180 | .bits = {{ | |
181 | .offset = 2, | |
182 | .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, | |
183 | .expected = 0, | |
184 | }}, ), | |
3a6fa984 BV |
185 | CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), |
186 | CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), | |
187 | CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), | |
f0a346bd BV |
188 | CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, |
189 | .bits = {{ | |
190 | .offset = 1, | |
b18b396b | 191 | .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), |
f0a346bd | 192 | .expected = 0, |
d4d48035 BV |
193 | }, |
194 | { | |
195 | .offset = 1, | |
196 | .mask = PIPE_CONTROL_GLOBAL_GTT_IVB, | |
197 | .expected = 0, | |
198 | .condition_offset = 1, | |
199 | .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, | |
f0a346bd | 200 | }}, ), |
3a6fa984 BV |
201 | }; |
202 | ||
203 | static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { | |
204 | CMD( MI_SET_PREDICATE, SMI, F, 1, S ), | |
205 | CMD( MI_RS_CONTROL, SMI, F, 1, S ), | |
206 | CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), | |
207 | CMD( MI_RS_CONTEXT, SMI, F, 1, S ), | |
17c1eb15 | 208 | CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), |
9c640d1d BV |
209 | CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), |
210 | CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ), | |
3a6fa984 BV |
211 | CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), |
212 | CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), | |
213 | CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), | |
214 | CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), | |
215 | CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), | |
216 | ||
217 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), | |
218 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), | |
219 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), | |
220 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), | |
221 | CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), | |
222 | }; | |
223 | ||
224 | static const struct drm_i915_cmd_descriptor video_cmds[] = { | |
9c640d1d | 225 | CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), |
d4d48035 BV |
226 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, |
227 | .bits = {{ | |
228 | .offset = 0, | |
229 | .mask = MI_GLOBAL_GTT, | |
230 | .expected = 0, | |
231 | }}, ), | |
9c640d1d | 232 | CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), |
b18b396b BV |
233 | CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, |
234 | .bits = {{ | |
235 | .offset = 0, | |
236 | .mask = MI_FLUSH_DW_NOTIFY, | |
237 | .expected = 0, | |
d4d48035 BV |
238 | }, |
239 | { | |
240 | .offset = 1, | |
241 | .mask = MI_FLUSH_DW_USE_GTT, | |
242 | .expected = 0, | |
243 | .condition_offset = 0, | |
244 | .condition_mask = MI_FLUSH_DW_OP_MASK, | |
245 | }}, ), | |
246 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, | |
247 | .bits = {{ | |
248 | .offset = 0, | |
249 | .mask = MI_GLOBAL_GTT, | |
250 | .expected = 0, | |
b18b396b | 251 | }}, ), |
3a6fa984 BV |
252 | /* |
253 | * MFX_WAIT doesn't fit the way we handle length for most commands. | |
254 | * It has a length field but it uses a non-standard length bias. | |
255 | * It is always 1 dword though, so just treat it as fixed length. | |
256 | */ | |
257 | CMD( MFX_WAIT, SMFX, F, 1, S ), | |
258 | }; | |
259 | ||
260 | static const struct drm_i915_cmd_descriptor vecs_cmds[] = { | |
9c640d1d | 261 | CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), |
d4d48035 BV |
262 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, |
263 | .bits = {{ | |
264 | .offset = 0, | |
265 | .mask = MI_GLOBAL_GTT, | |
266 | .expected = 0, | |
267 | }}, ), | |
9c640d1d | 268 | CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), |
b18b396b BV |
269 | CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, |
270 | .bits = {{ | |
271 | .offset = 0, | |
272 | .mask = MI_FLUSH_DW_NOTIFY, | |
273 | .expected = 0, | |
d4d48035 BV |
274 | }, |
275 | { | |
276 | .offset = 1, | |
277 | .mask = MI_FLUSH_DW_USE_GTT, | |
278 | .expected = 0, | |
279 | .condition_offset = 0, | |
280 | .condition_mask = MI_FLUSH_DW_OP_MASK, | |
281 | }}, ), | |
282 | CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, | |
283 | .bits = {{ | |
284 | .offset = 0, | |
285 | .mask = MI_GLOBAL_GTT, | |
286 | .expected = 0, | |
b18b396b | 287 | }}, ), |
3a6fa984 BV |
288 | }; |
289 | ||
290 | static const struct drm_i915_cmd_descriptor blt_cmds[] = { | |
9c640d1d | 291 | CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), |
d4d48035 BV |
292 | CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, |
293 | .bits = {{ | |
294 | .offset = 0, | |
295 | .mask = MI_GLOBAL_GTT, | |
296 | .expected = 0, | |
297 | }}, ), | |
9c640d1d | 298 | CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), |
b18b396b BV |
299 | CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, |
300 | .bits = {{ | |
301 | .offset = 0, | |
302 | .mask = MI_FLUSH_DW_NOTIFY, | |
303 | .expected = 0, | |
d4d48035 BV |
304 | }, |
305 | { | |
306 | .offset = 1, | |
307 | .mask = MI_FLUSH_DW_USE_GTT, | |
308 | .expected = 0, | |
309 | .condition_offset = 0, | |
310 | .condition_mask = MI_FLUSH_DW_OP_MASK, | |
b18b396b | 311 | }}, ), |
3a6fa984 BV |
312 | CMD( COLOR_BLT, S2D, !F, 0x3F, S ), |
313 | CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), | |
314 | }; | |
315 | ||
9c640d1d | 316 | static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { |
17c1eb15 | 317 | CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), |
9c640d1d BV |
318 | CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), |
319 | }; | |
320 | ||
3a6fa984 BV |
321 | #undef CMD |
322 | #undef SMI | |
323 | #undef S3D | |
324 | #undef S2D | |
325 | #undef SMFX | |
326 | #undef F | |
327 | #undef S | |
328 | #undef R | |
329 | #undef W | |
330 | #undef B | |
331 | #undef M | |
332 | ||
333 | static const struct drm_i915_cmd_table gen7_render_cmds[] = { | |
334 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
335 | { render_cmds, ARRAY_SIZE(render_cmds) }, | |
336 | }; | |
337 | ||
338 | static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = { | |
339 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
340 | { render_cmds, ARRAY_SIZE(render_cmds) }, | |
341 | { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, | |
342 | }; | |
343 | ||
344 | static const struct drm_i915_cmd_table gen7_video_cmds[] = { | |
345 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
346 | { video_cmds, ARRAY_SIZE(video_cmds) }, | |
347 | }; | |
348 | ||
349 | static const struct drm_i915_cmd_table hsw_vebox_cmds[] = { | |
350 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
351 | { vecs_cmds, ARRAY_SIZE(vecs_cmds) }, | |
352 | }; | |
353 | ||
354 | static const struct drm_i915_cmd_table gen7_blt_cmds[] = { | |
355 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
356 | { blt_cmds, ARRAY_SIZE(blt_cmds) }, | |
357 | }; | |
358 | ||
9c640d1d BV |
359 | static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { |
360 | { common_cmds, ARRAY_SIZE(common_cmds) }, | |
361 | { blt_cmds, ARRAY_SIZE(blt_cmds) }, | |
362 | { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, | |
363 | }; | |
364 | ||
5947de9b BV |
365 | /* |
366 | * Register whitelists, sorted by increasing register offset. | |
367 | * | |
368 | * Some registers that userspace accesses are 64 bits. The register | |
369 | * access commands only allow 32-bit accesses. Hence, we have to include | |
370 | * entries for both halves of the 64-bit registers. | |
371 | */ | |
372 | ||
373 | /* Convenience macro for adding 64-bit registers */ | |
374 | #define REG64(addr) (addr), (addr + sizeof(u32)) | |
375 | ||
376 | static const u32 gen7_render_regs[] = { | |
377 | REG64(HS_INVOCATION_COUNT), | |
378 | REG64(DS_INVOCATION_COUNT), | |
379 | REG64(IA_VERTICES_COUNT), | |
380 | REG64(IA_PRIMITIVES_COUNT), | |
381 | REG64(VS_INVOCATION_COUNT), | |
382 | REG64(GS_INVOCATION_COUNT), | |
383 | REG64(GS_PRIMITIVES_COUNT), | |
384 | REG64(CL_INVOCATION_COUNT), | |
385 | REG64(CL_PRIMITIVES_COUNT), | |
386 | REG64(PS_INVOCATION_COUNT), | |
387 | REG64(PS_DEPTH_COUNT), | |
388 | REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)), | |
389 | REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)), | |
390 | REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)), | |
391 | REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)), | |
392 | GEN7_SO_WRITE_OFFSET(0), | |
393 | GEN7_SO_WRITE_OFFSET(1), | |
394 | GEN7_SO_WRITE_OFFSET(2), | |
395 | GEN7_SO_WRITE_OFFSET(3), | |
396 | }; | |
397 | ||
398 | static const u32 gen7_blt_regs[] = { | |
399 | BCS_SWCTRL, | |
400 | }; | |
401 | ||
220375aa BV |
402 | static const u32 ivb_master_regs[] = { |
403 | FORCEWAKE_MT, | |
404 | DERRMR, | |
405 | GEN7_PIPE_DE_LOAD_SL(PIPE_A), | |
406 | GEN7_PIPE_DE_LOAD_SL(PIPE_B), | |
407 | GEN7_PIPE_DE_LOAD_SL(PIPE_C), | |
408 | }; | |
409 | ||
410 | static const u32 hsw_master_regs[] = { | |
411 | FORCEWAKE_MT, | |
412 | DERRMR, | |
413 | }; | |
414 | ||
5947de9b BV |
415 | #undef REG64 |
416 | ||
351e3db2 BV |
417 | static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) |
418 | { | |
419 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; | |
420 | u32 subclient = | |
421 | (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; | |
422 | ||
423 | if (client == INSTR_MI_CLIENT) | |
424 | return 0x3F; | |
425 | else if (client == INSTR_RC_CLIENT) { | |
426 | if (subclient == INSTR_MEDIA_SUBCLIENT) | |
427 | return 0xFFFF; | |
428 | else | |
429 | return 0xFF; | |
430 | } | |
431 | ||
432 | DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); | |
433 | return 0; | |
434 | } | |
435 | ||
436 | static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) | |
437 | { | |
438 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; | |
439 | u32 subclient = | |
440 | (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; | |
441 | ||
442 | if (client == INSTR_MI_CLIENT) | |
443 | return 0x3F; | |
444 | else if (client == INSTR_RC_CLIENT) { | |
445 | if (subclient == INSTR_MEDIA_SUBCLIENT) | |
446 | return 0xFFF; | |
447 | else | |
448 | return 0xFF; | |
449 | } | |
450 | ||
451 | DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); | |
452 | return 0; | |
453 | } | |
454 | ||
455 | static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) | |
456 | { | |
457 | u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; | |
458 | ||
459 | if (client == INSTR_MI_CLIENT) | |
460 | return 0x3F; | |
461 | else if (client == INSTR_BC_CLIENT) | |
462 | return 0xFF; | |
463 | ||
464 | DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); | |
465 | return 0; | |
466 | } | |
467 | ||
468 | static void validate_cmds_sorted(struct intel_ring_buffer *ring) | |
469 | { | |
470 | int i; | |
471 | ||
472 | if (!ring->cmd_tables || ring->cmd_table_count == 0) | |
473 | return; | |
474 | ||
475 | for (i = 0; i < ring->cmd_table_count; i++) { | |
476 | const struct drm_i915_cmd_table *table = &ring->cmd_tables[i]; | |
477 | u32 previous = 0; | |
478 | int j; | |
479 | ||
480 | for (j = 0; j < table->count; j++) { | |
481 | const struct drm_i915_cmd_descriptor *desc = | |
482 | &table->table[i]; | |
483 | u32 curr = desc->cmd.value & desc->cmd.mask; | |
484 | ||
485 | if (curr < previous) | |
486 | DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n", | |
487 | ring->id, i, j, curr, previous); | |
488 | ||
489 | previous = curr; | |
490 | } | |
491 | } | |
492 | } | |
493 | ||
494 | static void check_sorted(int ring_id, const u32 *reg_table, int reg_count) | |
495 | { | |
496 | int i; | |
497 | u32 previous = 0; | |
498 | ||
499 | for (i = 0; i < reg_count; i++) { | |
500 | u32 curr = reg_table[i]; | |
501 | ||
502 | if (curr < previous) | |
503 | DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n", | |
504 | ring_id, i, curr, previous); | |
505 | ||
506 | previous = curr; | |
507 | } | |
508 | } | |
509 | ||
510 | static void validate_regs_sorted(struct intel_ring_buffer *ring) | |
511 | { | |
512 | check_sorted(ring->id, ring->reg_table, ring->reg_count); | |
513 | check_sorted(ring->id, ring->master_reg_table, ring->master_reg_count); | |
514 | } | |
515 | ||
516 | /** | |
517 | * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer | |
518 | * @ring: the ringbuffer to initialize | |
519 | * | |
520 | * Optionally initializes fields related to batch buffer command parsing in the | |
521 | * struct intel_ring_buffer based on whether the platform requires software | |
522 | * command parsing. | |
523 | */ | |
524 | void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring) | |
525 | { | |
526 | if (!IS_GEN7(ring->dev)) | |
527 | return; | |
528 | ||
529 | switch (ring->id) { | |
530 | case RCS: | |
3a6fa984 BV |
531 | if (IS_HASWELL(ring->dev)) { |
532 | ring->cmd_tables = hsw_render_ring_cmds; | |
533 | ring->cmd_table_count = | |
534 | ARRAY_SIZE(hsw_render_ring_cmds); | |
535 | } else { | |
536 | ring->cmd_tables = gen7_render_cmds; | |
537 | ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds); | |
538 | } | |
539 | ||
5947de9b BV |
540 | ring->reg_table = gen7_render_regs; |
541 | ring->reg_count = ARRAY_SIZE(gen7_render_regs); | |
542 | ||
220375aa BV |
543 | if (IS_HASWELL(ring->dev)) { |
544 | ring->master_reg_table = hsw_master_regs; | |
545 | ring->master_reg_count = ARRAY_SIZE(hsw_master_regs); | |
546 | } else { | |
547 | ring->master_reg_table = ivb_master_regs; | |
548 | ring->master_reg_count = ARRAY_SIZE(ivb_master_regs); | |
549 | } | |
550 | ||
351e3db2 BV |
551 | ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask; |
552 | break; | |
553 | case VCS: | |
3a6fa984 BV |
554 | ring->cmd_tables = gen7_video_cmds; |
555 | ring->cmd_table_count = ARRAY_SIZE(gen7_video_cmds); | |
351e3db2 BV |
556 | ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; |
557 | break; | |
558 | case BCS: | |
9c640d1d BV |
559 | if (IS_HASWELL(ring->dev)) { |
560 | ring->cmd_tables = hsw_blt_ring_cmds; | |
561 | ring->cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds); | |
562 | } else { | |
563 | ring->cmd_tables = gen7_blt_cmds; | |
564 | ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); | |
565 | } | |
566 | ||
5947de9b BV |
567 | ring->reg_table = gen7_blt_regs; |
568 | ring->reg_count = ARRAY_SIZE(gen7_blt_regs); | |
569 | ||
220375aa BV |
570 | if (IS_HASWELL(ring->dev)) { |
571 | ring->master_reg_table = hsw_master_regs; | |
572 | ring->master_reg_count = ARRAY_SIZE(hsw_master_regs); | |
573 | } else { | |
574 | ring->master_reg_table = ivb_master_regs; | |
575 | ring->master_reg_count = ARRAY_SIZE(ivb_master_regs); | |
576 | } | |
577 | ||
351e3db2 BV |
578 | ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; |
579 | break; | |
580 | case VECS: | |
3a6fa984 BV |
581 | ring->cmd_tables = hsw_vebox_cmds; |
582 | ring->cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds); | |
351e3db2 BV |
583 | /* VECS can use the same length_mask function as VCS */ |
584 | ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; | |
585 | break; | |
586 | default: | |
587 | DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n", | |
588 | ring->id); | |
589 | BUG(); | |
590 | } | |
591 | ||
592 | validate_cmds_sorted(ring); | |
593 | validate_regs_sorted(ring); | |
594 | } | |
595 | ||
596 | static const struct drm_i915_cmd_descriptor* | |
597 | find_cmd_in_table(const struct drm_i915_cmd_table *table, | |
598 | u32 cmd_header) | |
599 | { | |
600 | int i; | |
601 | ||
602 | for (i = 0; i < table->count; i++) { | |
603 | const struct drm_i915_cmd_descriptor *desc = &table->table[i]; | |
604 | u32 masked_cmd = desc->cmd.mask & cmd_header; | |
605 | u32 masked_value = desc->cmd.value & desc->cmd.mask; | |
606 | ||
607 | if (masked_cmd == masked_value) | |
608 | return desc; | |
609 | } | |
610 | ||
611 | return NULL; | |
612 | } | |
613 | ||
614 | /* | |
615 | * Returns a pointer to a descriptor for the command specified by cmd_header. | |
616 | * | |
617 | * The caller must supply space for a default descriptor via the default_desc | |
618 | * parameter. If no descriptor for the specified command exists in the ring's | |
619 | * command parser tables, this function fills in default_desc based on the | |
620 | * ring's default length encoding and returns default_desc. | |
621 | */ | |
622 | static const struct drm_i915_cmd_descriptor* | |
623 | find_cmd(struct intel_ring_buffer *ring, | |
624 | u32 cmd_header, | |
625 | struct drm_i915_cmd_descriptor *default_desc) | |
626 | { | |
627 | u32 mask; | |
628 | int i; | |
629 | ||
630 | for (i = 0; i < ring->cmd_table_count; i++) { | |
631 | const struct drm_i915_cmd_descriptor *desc; | |
632 | ||
633 | desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header); | |
634 | if (desc) | |
635 | return desc; | |
636 | } | |
637 | ||
638 | mask = ring->get_cmd_length_mask(cmd_header); | |
639 | if (!mask) | |
640 | return NULL; | |
641 | ||
642 | BUG_ON(!default_desc); | |
643 | default_desc->flags = CMD_DESC_SKIP; | |
644 | default_desc->length.mask = mask; | |
645 | ||
646 | return default_desc; | |
647 | } | |
648 | ||
649 | static bool valid_reg(const u32 *table, int count, u32 addr) | |
650 | { | |
651 | if (table && count != 0) { | |
652 | int i; | |
653 | ||
654 | for (i = 0; i < count; i++) { | |
655 | if (table[i] == addr) | |
656 | return true; | |
657 | } | |
658 | } | |
659 | ||
660 | return false; | |
661 | } | |
662 | ||
663 | static u32 *vmap_batch(struct drm_i915_gem_object *obj) | |
664 | { | |
665 | int i; | |
666 | void *addr = NULL; | |
667 | struct sg_page_iter sg_iter; | |
668 | struct page **pages; | |
669 | ||
670 | pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); | |
671 | if (pages == NULL) { | |
672 | DRM_DEBUG_DRIVER("Failed to get space for pages\n"); | |
673 | goto finish; | |
674 | } | |
675 | ||
676 | i = 0; | |
677 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
678 | pages[i] = sg_page_iter_page(&sg_iter); | |
679 | i++; | |
680 | } | |
681 | ||
682 | addr = vmap(pages, i, 0, PAGE_KERNEL); | |
683 | if (addr == NULL) { | |
684 | DRM_DEBUG_DRIVER("Failed to vmap pages\n"); | |
685 | goto finish; | |
686 | } | |
687 | ||
688 | finish: | |
689 | if (pages) | |
690 | drm_free_large(pages); | |
691 | return (u32*)addr; | |
692 | } | |
693 | ||
694 | /** | |
695 | * i915_needs_cmd_parser() - should a given ring use software command parsing? | |
696 | * @ring: the ring in question | |
697 | * | |
698 | * Only certain platforms require software batch buffer command parsing, and | |
699 | * only when enabled via module paramter. | |
700 | * | |
701 | * Return: true if the ring requires software command parsing | |
702 | */ | |
703 | bool i915_needs_cmd_parser(struct intel_ring_buffer *ring) | |
704 | { | |
d4d48035 BV |
705 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
706 | ||
351e3db2 BV |
707 | /* No command tables indicates a platform without parsing */ |
708 | if (!ring->cmd_tables) | |
709 | return false; | |
710 | ||
d4d48035 BV |
711 | /* |
712 | * XXX: VLV is Gen7 and therefore has cmd_tables, but has PPGTT | |
713 | * disabled. That will cause all of the parser's PPGTT checks to | |
714 | * fail. For now, disable parsing when PPGTT is off. | |
715 | */ | |
716 | if (!dev_priv->mm.aliasing_ppgtt) | |
717 | return false; | |
718 | ||
351e3db2 BV |
719 | return (i915.enable_cmd_parser == 1); |
720 | } | |
721 | ||
722 | #define LENGTH_BIAS 2 | |
723 | ||
724 | /** | |
725 | * i915_parse_cmds() - parse a submitted batch buffer for privilege violations | |
726 | * @ring: the ring on which the batch is to execute | |
727 | * @batch_obj: the batch buffer in question | |
728 | * @batch_start_offset: byte offset in the batch at which execution starts | |
729 | * @is_master: is the submitting process the drm master? | |
730 | * | |
731 | * Parses the specified batch buffer looking for privilege violations as | |
732 | * described in the overview. | |
733 | * | |
734 | * Return: non-zero if the parser finds violations or otherwise fails | |
735 | */ | |
736 | int i915_parse_cmds(struct intel_ring_buffer *ring, | |
737 | struct drm_i915_gem_object *batch_obj, | |
738 | u32 batch_start_offset, | |
739 | bool is_master) | |
740 | { | |
741 | int ret = 0; | |
742 | u32 *cmd, *batch_base, *batch_end; | |
743 | struct drm_i915_cmd_descriptor default_desc = { 0 }; | |
744 | int needs_clflush = 0; | |
745 | ||
746 | ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush); | |
747 | if (ret) { | |
748 | DRM_DEBUG_DRIVER("CMD: failed to prep read\n"); | |
749 | return ret; | |
750 | } | |
751 | ||
752 | batch_base = vmap_batch(batch_obj); | |
753 | if (!batch_base) { | |
754 | DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n"); | |
755 | i915_gem_object_unpin_pages(batch_obj); | |
756 | return -ENOMEM; | |
757 | } | |
758 | ||
759 | if (needs_clflush) | |
760 | drm_clflush_virt_range((char *)batch_base, batch_obj->base.size); | |
761 | ||
762 | cmd = batch_base + (batch_start_offset / sizeof(*cmd)); | |
763 | batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end)); | |
764 | ||
765 | while (cmd < batch_end) { | |
766 | const struct drm_i915_cmd_descriptor *desc; | |
767 | u32 length; | |
768 | ||
769 | if (*cmd == MI_BATCH_BUFFER_END) | |
770 | break; | |
771 | ||
772 | desc = find_cmd(ring, *cmd, &default_desc); | |
773 | if (!desc) { | |
774 | DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n", | |
775 | *cmd); | |
776 | ret = -EINVAL; | |
777 | break; | |
778 | } | |
779 | ||
780 | if (desc->flags & CMD_DESC_FIXED) | |
781 | length = desc->length.fixed; | |
782 | else | |
783 | length = ((*cmd & desc->length.mask) + LENGTH_BIAS); | |
784 | ||
785 | if ((batch_end - cmd) < length) { | |
e5081a53 | 786 | DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%d batchlen=%td\n", |
351e3db2 BV |
787 | *cmd, |
788 | length, | |
789 | batch_end - cmd); | |
790 | ret = -EINVAL; | |
791 | break; | |
792 | } | |
793 | ||
794 | if (desc->flags & CMD_DESC_REJECT) { | |
795 | DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); | |
796 | ret = -EINVAL; | |
797 | break; | |
798 | } | |
799 | ||
800 | if ((desc->flags & CMD_DESC_MASTER) && !is_master) { | |
801 | DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n", | |
802 | *cmd); | |
803 | ret = -EINVAL; | |
804 | break; | |
805 | } | |
806 | ||
807 | if (desc->flags & CMD_DESC_REGISTER) { | |
808 | u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask; | |
809 | ||
810 | if (!valid_reg(ring->reg_table, | |
811 | ring->reg_count, reg_addr)) { | |
812 | if (!is_master || | |
813 | !valid_reg(ring->master_reg_table, | |
814 | ring->master_reg_count, | |
815 | reg_addr)) { | |
816 | DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n", | |
817 | reg_addr, | |
818 | *cmd, | |
819 | ring->id); | |
820 | ret = -EINVAL; | |
821 | break; | |
822 | } | |
823 | } | |
824 | } | |
825 | ||
826 | if (desc->flags & CMD_DESC_BITMASK) { | |
827 | int i; | |
828 | ||
829 | for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { | |
830 | u32 dword; | |
831 | ||
832 | if (desc->bits[i].mask == 0) | |
833 | break; | |
834 | ||
d4d48035 BV |
835 | if (desc->bits[i].condition_mask != 0) { |
836 | u32 offset = | |
837 | desc->bits[i].condition_offset; | |
838 | u32 condition = cmd[offset] & | |
839 | desc->bits[i].condition_mask; | |
840 | ||
841 | if (condition == 0) | |
842 | continue; | |
843 | } | |
844 | ||
351e3db2 BV |
845 | dword = cmd[desc->bits[i].offset] & |
846 | desc->bits[i].mask; | |
847 | ||
848 | if (dword != desc->bits[i].expected) { | |
849 | DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n", | |
850 | *cmd, | |
851 | desc->bits[i].mask, | |
852 | desc->bits[i].expected, | |
853 | dword, ring->id); | |
854 | ret = -EINVAL; | |
855 | break; | |
856 | } | |
857 | } | |
858 | ||
859 | if (ret) | |
860 | break; | |
861 | } | |
862 | ||
863 | cmd += length; | |
864 | } | |
865 | ||
866 | if (cmd >= batch_end) { | |
867 | DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); | |
868 | ret = -EINVAL; | |
869 | } | |
870 | ||
871 | vunmap(batch_base); | |
872 | ||
873 | i915_gem_object_unpin_pages(batch_obj); | |
874 | ||
875 | return ret; | |
876 | } |