Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
6d2b8885 | 33 | #include <linux/list_sort.h> |
ec013e7f | 34 | #include <asm/msr-index.h> |
760285e7 | 35 | #include <drm/drmP.h> |
4e5359cd | 36 | #include "intel_drv.h" |
e5c65260 | 37 | #include "intel_ringbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
2017263e BG |
39 | #include "i915_drv.h" |
40 | ||
41 | #define DRM_I915_RING_DEBUG 1 | |
42 | ||
43 | ||
44 | #if defined(CONFIG_DEBUG_FS) | |
45 | ||
f13d3f73 | 46 | enum { |
69dc4987 | 47 | ACTIVE_LIST, |
f13d3f73 | 48 | INACTIVE_LIST, |
d21d5975 | 49 | PINNED_LIST, |
f13d3f73 | 50 | }; |
2017263e | 51 | |
70d39fe4 CW |
52 | static const char *yesno(int v) |
53 | { | |
54 | return v ? "yes" : "no"; | |
55 | } | |
56 | ||
57 | static int i915_capabilities(struct seq_file *m, void *data) | |
58 | { | |
59 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
60 | struct drm_device *dev = node->minor->dev; | |
61 | const struct intel_device_info *info = INTEL_INFO(dev); | |
62 | ||
63 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 64 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
65 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
66 | #define SEP_SEMICOLON ; | |
67 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
68 | #undef PRINT_FLAG | |
69 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
70 | |
71 | return 0; | |
72 | } | |
2017263e | 73 | |
05394f39 | 74 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 75 | { |
05394f39 | 76 | if (obj->user_pin_count > 0) |
a6172a80 | 77 | return "P"; |
05394f39 | 78 | else if (obj->pin_count > 0) |
a6172a80 CW |
79 | return "p"; |
80 | else | |
81 | return " "; | |
82 | } | |
83 | ||
05394f39 | 84 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 85 | { |
0206e353 AJ |
86 | switch (obj->tiling_mode) { |
87 | default: | |
88 | case I915_TILING_NONE: return " "; | |
89 | case I915_TILING_X: return "X"; | |
90 | case I915_TILING_Y: return "Y"; | |
91 | } | |
a6172a80 CW |
92 | } |
93 | ||
1d693bcc BW |
94 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
95 | { | |
96 | return obj->has_global_gtt_mapping ? "g" : " "; | |
97 | } | |
98 | ||
37811fcc CW |
99 | static void |
100 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
101 | { | |
1d693bcc | 102 | struct i915_vma *vma; |
fb1ae911 | 103 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
104 | &obj->base, |
105 | get_pin_flag(obj), | |
106 | get_tiling_flag(obj), | |
1d693bcc | 107 | get_global_flag(obj), |
a05a5862 | 108 | obj->base.size / 1024, |
37811fcc CW |
109 | obj->base.read_domains, |
110 | obj->base.write_domain, | |
0201f1ec CW |
111 | obj->last_read_seqno, |
112 | obj->last_write_seqno, | |
caea7476 | 113 | obj->last_fenced_seqno, |
84734a04 | 114 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
115 | obj->dirty ? " dirty" : "", |
116 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
117 | if (obj->base.name) | |
118 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
119 | if (obj->pin_count) |
120 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
cc98b413 CW |
121 | if (obj->pin_display) |
122 | seq_printf(m, " (display)"); | |
37811fcc CW |
123 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
124 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
125 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
126 | if (!i915_is_ggtt(vma->vm)) | |
127 | seq_puts(m, " (pp"); | |
128 | else | |
129 | seq_puts(m, " (g"); | |
130 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
131 | vma->node.start, vma->node.size); | |
132 | } | |
c1ad11fc CW |
133 | if (obj->stolen) |
134 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
135 | if (obj->pin_mappable || obj->fault_mappable) { |
136 | char s[3], *t = s; | |
137 | if (obj->pin_mappable) | |
138 | *t++ = 'p'; | |
139 | if (obj->fault_mappable) | |
140 | *t++ = 'f'; | |
141 | *t = '\0'; | |
142 | seq_printf(m, " (%s mappable)", s); | |
143 | } | |
69dc4987 CW |
144 | if (obj->ring != NULL) |
145 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
146 | } |
147 | ||
433e12f7 | 148 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
149 | { |
150 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
151 | uintptr_t list = (uintptr_t) node->info_ent->data; |
152 | struct list_head *head; | |
2017263e | 153 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
154 | struct drm_i915_private *dev_priv = dev->dev_private; |
155 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 156 | struct i915_vma *vma; |
8f2480fb CW |
157 | size_t total_obj_size, total_gtt_size; |
158 | int count, ret; | |
de227ef0 CW |
159 | |
160 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
161 | if (ret) | |
162 | return ret; | |
2017263e | 163 | |
ca191b13 | 164 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
165 | switch (list) { |
166 | case ACTIVE_LIST: | |
267f0c90 | 167 | seq_puts(m, "Active:\n"); |
5cef07e1 | 168 | head = &vm->active_list; |
433e12f7 BG |
169 | break; |
170 | case INACTIVE_LIST: | |
267f0c90 | 171 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 172 | head = &vm->inactive_list; |
433e12f7 | 173 | break; |
433e12f7 | 174 | default: |
de227ef0 CW |
175 | mutex_unlock(&dev->struct_mutex); |
176 | return -EINVAL; | |
2017263e | 177 | } |
2017263e | 178 | |
8f2480fb | 179 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
180 | list_for_each_entry(vma, head, mm_list) { |
181 | seq_printf(m, " "); | |
182 | describe_obj(m, vma->obj); | |
183 | seq_printf(m, "\n"); | |
184 | total_obj_size += vma->obj->base.size; | |
185 | total_gtt_size += vma->node.size; | |
8f2480fb | 186 | count++; |
2017263e | 187 | } |
de227ef0 | 188 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 189 | |
8f2480fb CW |
190 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
191 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
192 | return 0; |
193 | } | |
194 | ||
6d2b8885 CW |
195 | static int obj_rank_by_stolen(void *priv, |
196 | struct list_head *A, struct list_head *B) | |
197 | { | |
198 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 199 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 200 | struct drm_i915_gem_object *b = |
b25cb2f8 | 201 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
202 | |
203 | return a->stolen->start - b->stolen->start; | |
204 | } | |
205 | ||
206 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
207 | { | |
208 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
209 | struct drm_device *dev = node->minor->dev; | |
210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
211 | struct drm_i915_gem_object *obj; | |
212 | size_t total_obj_size, total_gtt_size; | |
213 | LIST_HEAD(stolen); | |
214 | int count, ret; | |
215 | ||
216 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
217 | if (ret) | |
218 | return ret; | |
219 | ||
220 | total_obj_size = total_gtt_size = count = 0; | |
221 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
222 | if (obj->stolen == NULL) | |
223 | continue; | |
224 | ||
b25cb2f8 | 225 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
226 | |
227 | total_obj_size += obj->base.size; | |
228 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
229 | count++; | |
230 | } | |
231 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
232 | if (obj->stolen == NULL) | |
233 | continue; | |
234 | ||
b25cb2f8 | 235 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
236 | |
237 | total_obj_size += obj->base.size; | |
238 | count++; | |
239 | } | |
240 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
241 | seq_puts(m, "Stolen:\n"); | |
242 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 243 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
244 | seq_puts(m, " "); |
245 | describe_obj(m, obj); | |
246 | seq_putc(m, '\n'); | |
b25cb2f8 | 247 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
248 | } |
249 | mutex_unlock(&dev->struct_mutex); | |
250 | ||
251 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
252 | count, total_obj_size, total_gtt_size); | |
253 | return 0; | |
254 | } | |
255 | ||
6299f992 CW |
256 | #define count_objects(list, member) do { \ |
257 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 258 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
259 | ++count; \ |
260 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 261 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
262 | ++mappable_count; \ |
263 | } \ | |
264 | } \ | |
0206e353 | 265 | } while (0) |
6299f992 | 266 | |
2db8e9d6 CW |
267 | struct file_stats { |
268 | int count; | |
269 | size_t total, active, inactive, unbound; | |
270 | }; | |
271 | ||
272 | static int per_file_stats(int id, void *ptr, void *data) | |
273 | { | |
274 | struct drm_i915_gem_object *obj = ptr; | |
275 | struct file_stats *stats = data; | |
276 | ||
277 | stats->count++; | |
278 | stats->total += obj->base.size; | |
279 | ||
f343c5f6 | 280 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
281 | if (!list_empty(&obj->ring_list)) |
282 | stats->active += obj->base.size; | |
283 | else | |
284 | stats->inactive += obj->base.size; | |
285 | } else { | |
286 | if (!list_empty(&obj->global_list)) | |
287 | stats->unbound += obj->base.size; | |
288 | } | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
ca191b13 BW |
293 | #define count_vmas(list, member) do { \ |
294 | list_for_each_entry(vma, list, member) { \ | |
295 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
296 | ++count; \ | |
297 | if (vma->obj->map_and_fenceable) { \ | |
298 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
299 | ++mappable_count; \ | |
300 | } \ | |
301 | } \ | |
302 | } while (0) | |
303 | ||
304 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
305 | { |
306 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
307 | struct drm_device *dev = node->minor->dev; | |
308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
309 | u32 count, mappable_count, purgeable_count; |
310 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 311 | struct drm_i915_gem_object *obj; |
5cef07e1 | 312 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 313 | struct drm_file *file; |
ca191b13 | 314 | struct i915_vma *vma; |
73aa808f CW |
315 | int ret; |
316 | ||
317 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
318 | if (ret) | |
319 | return ret; | |
320 | ||
6299f992 CW |
321 | seq_printf(m, "%u objects, %zu bytes\n", |
322 | dev_priv->mm.object_count, | |
323 | dev_priv->mm.object_memory); | |
324 | ||
325 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 326 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
327 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
328 | count, mappable_count, size, mappable_size); | |
329 | ||
330 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 331 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
332 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
333 | count, mappable_count, size, mappable_size); | |
334 | ||
6299f992 | 335 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 336 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
337 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
338 | count, mappable_count, size, mappable_size); | |
339 | ||
b7abb714 | 340 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 341 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 342 | size += obj->base.size, ++count; |
b7abb714 CW |
343 | if (obj->madv == I915_MADV_DONTNEED) |
344 | purgeable_size += obj->base.size, ++purgeable_count; | |
345 | } | |
6c085a72 CW |
346 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
347 | ||
6299f992 | 348 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 349 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 350 | if (obj->fault_mappable) { |
f343c5f6 | 351 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
352 | ++count; |
353 | } | |
354 | if (obj->pin_mappable) { | |
f343c5f6 | 355 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
356 | ++mappable_count; |
357 | } | |
b7abb714 CW |
358 | if (obj->madv == I915_MADV_DONTNEED) { |
359 | purgeable_size += obj->base.size; | |
360 | ++purgeable_count; | |
361 | } | |
6299f992 | 362 | } |
b7abb714 CW |
363 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
364 | purgeable_count, purgeable_size); | |
6299f992 CW |
365 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
366 | mappable_count, mappable_size); | |
367 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
368 | count, size); | |
369 | ||
93d18799 | 370 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
371 | dev_priv->gtt.base.total, |
372 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 373 | |
267f0c90 | 374 | seq_putc(m, '\n'); |
2db8e9d6 CW |
375 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
376 | struct file_stats stats; | |
377 | ||
378 | memset(&stats, 0, sizeof(stats)); | |
379 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
380 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
381 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
382 | stats.count, | |
383 | stats.total, | |
384 | stats.active, | |
385 | stats.inactive, | |
386 | stats.unbound); | |
387 | } | |
388 | ||
73aa808f CW |
389 | mutex_unlock(&dev->struct_mutex); |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
aee56cff | 394 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
395 | { |
396 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
397 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 398 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
399 | struct drm_i915_private *dev_priv = dev->dev_private; |
400 | struct drm_i915_gem_object *obj; | |
401 | size_t total_obj_size, total_gtt_size; | |
402 | int count, ret; | |
403 | ||
404 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
405 | if (ret) | |
406 | return ret; | |
407 | ||
408 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 409 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
410 | if (list == PINNED_LIST && obj->pin_count == 0) |
411 | continue; | |
412 | ||
267f0c90 | 413 | seq_puts(m, " "); |
08c18323 | 414 | describe_obj(m, obj); |
267f0c90 | 415 | seq_putc(m, '\n'); |
08c18323 | 416 | total_obj_size += obj->base.size; |
f343c5f6 | 417 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
418 | count++; |
419 | } | |
420 | ||
421 | mutex_unlock(&dev->struct_mutex); | |
422 | ||
423 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
424 | count, total_obj_size, total_gtt_size); | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
4e5359cd SF |
429 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
430 | { | |
431 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
432 | struct drm_device *dev = node->minor->dev; | |
433 | unsigned long flags; | |
434 | struct intel_crtc *crtc; | |
435 | ||
436 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
437 | const char pipe = pipe_name(crtc->pipe); |
438 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
439 | struct intel_unpin_work *work; |
440 | ||
441 | spin_lock_irqsave(&dev->event_lock, flags); | |
442 | work = crtc->unpin_work; | |
443 | if (work == NULL) { | |
9db4a9c7 | 444 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
445 | pipe, plane); |
446 | } else { | |
e7d841ca | 447 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 448 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
449 | pipe, plane); |
450 | } else { | |
9db4a9c7 | 451 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
452 | pipe, plane); |
453 | } | |
454 | if (work->enable_stall_check) | |
267f0c90 | 455 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 456 | else |
267f0c90 | 457 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 458 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
459 | |
460 | if (work->old_fb_obj) { | |
05394f39 CW |
461 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
462 | if (obj) | |
f343c5f6 BW |
463 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
464 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
465 | } |
466 | if (work->pending_flip_obj) { | |
05394f39 CW |
467 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
468 | if (obj) | |
f343c5f6 BW |
469 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
470 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
471 | } |
472 | } | |
473 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
474 | } | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
2017263e BG |
479 | static int i915_gem_request_info(struct seq_file *m, void *data) |
480 | { | |
481 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
482 | struct drm_device *dev = node->minor->dev; | |
483 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 484 | struct intel_ring_buffer *ring; |
2017263e | 485 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 486 | int ret, count, i; |
de227ef0 CW |
487 | |
488 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
489 | if (ret) | |
490 | return ret; | |
2017263e | 491 | |
c2c347a9 | 492 | count = 0; |
a2c7f6fd CW |
493 | for_each_ring(ring, dev_priv, i) { |
494 | if (list_empty(&ring->request_list)) | |
495 | continue; | |
496 | ||
497 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 498 | list_for_each_entry(gem_request, |
a2c7f6fd | 499 | &ring->request_list, |
c2c347a9 CW |
500 | list) { |
501 | seq_printf(m, " %d @ %d\n", | |
502 | gem_request->seqno, | |
503 | (int) (jiffies - gem_request->emitted_jiffies)); | |
504 | } | |
505 | count++; | |
2017263e | 506 | } |
de227ef0 CW |
507 | mutex_unlock(&dev->struct_mutex); |
508 | ||
c2c347a9 | 509 | if (count == 0) |
267f0c90 | 510 | seq_puts(m, "No requests\n"); |
c2c347a9 | 511 | |
2017263e BG |
512 | return 0; |
513 | } | |
514 | ||
b2223497 CW |
515 | static void i915_ring_seqno_info(struct seq_file *m, |
516 | struct intel_ring_buffer *ring) | |
517 | { | |
518 | if (ring->get_seqno) { | |
43a7b924 | 519 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 520 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
521 | } |
522 | } | |
523 | ||
2017263e BG |
524 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
525 | { | |
526 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
527 | struct drm_device *dev = node->minor->dev; | |
528 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 529 | struct intel_ring_buffer *ring; |
1ec14ad3 | 530 | int ret, i; |
de227ef0 CW |
531 | |
532 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
533 | if (ret) | |
534 | return ret; | |
2017263e | 535 | |
a2c7f6fd CW |
536 | for_each_ring(ring, dev_priv, i) |
537 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
538 | |
539 | mutex_unlock(&dev->struct_mutex); | |
540 | ||
2017263e BG |
541 | return 0; |
542 | } | |
543 | ||
544 | ||
545 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
546 | { | |
547 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
548 | struct drm_device *dev = node->minor->dev; | |
549 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 550 | struct intel_ring_buffer *ring; |
9db4a9c7 | 551 | int ret, i, pipe; |
de227ef0 CW |
552 | |
553 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
554 | if (ret) | |
555 | return ret; | |
2017263e | 556 | |
7e231dbe JB |
557 | if (IS_VALLEYVIEW(dev)) { |
558 | seq_printf(m, "Display IER:\t%08x\n", | |
559 | I915_READ(VLV_IER)); | |
560 | seq_printf(m, "Display IIR:\t%08x\n", | |
561 | I915_READ(VLV_IIR)); | |
562 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
563 | I915_READ(VLV_IIR_RW)); | |
564 | seq_printf(m, "Display IMR:\t%08x\n", | |
565 | I915_READ(VLV_IMR)); | |
566 | for_each_pipe(pipe) | |
567 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
568 | pipe_name(pipe), | |
569 | I915_READ(PIPESTAT(pipe))); | |
570 | ||
571 | seq_printf(m, "Master IER:\t%08x\n", | |
572 | I915_READ(VLV_MASTER_IER)); | |
573 | ||
574 | seq_printf(m, "Render IER:\t%08x\n", | |
575 | I915_READ(GTIER)); | |
576 | seq_printf(m, "Render IIR:\t%08x\n", | |
577 | I915_READ(GTIIR)); | |
578 | seq_printf(m, "Render IMR:\t%08x\n", | |
579 | I915_READ(GTIMR)); | |
580 | ||
581 | seq_printf(m, "PM IER:\t\t%08x\n", | |
582 | I915_READ(GEN6_PMIER)); | |
583 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
584 | I915_READ(GEN6_PMIIR)); | |
585 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
586 | I915_READ(GEN6_PMIMR)); | |
587 | ||
588 | seq_printf(m, "Port hotplug:\t%08x\n", | |
589 | I915_READ(PORT_HOTPLUG_EN)); | |
590 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
591 | I915_READ(VLV_DPFLIPSTAT)); | |
592 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
593 | I915_READ(DPINVGTT)); | |
594 | ||
595 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
596 | seq_printf(m, "Interrupt enable: %08x\n", |
597 | I915_READ(IER)); | |
598 | seq_printf(m, "Interrupt identity: %08x\n", | |
599 | I915_READ(IIR)); | |
600 | seq_printf(m, "Interrupt mask: %08x\n", | |
601 | I915_READ(IMR)); | |
9db4a9c7 JB |
602 | for_each_pipe(pipe) |
603 | seq_printf(m, "Pipe %c stat: %08x\n", | |
604 | pipe_name(pipe), | |
605 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
606 | } else { |
607 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
608 | I915_READ(DEIER)); | |
609 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
610 | I915_READ(DEIIR)); | |
611 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
612 | I915_READ(DEIMR)); | |
613 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
614 | I915_READ(SDEIER)); | |
615 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
616 | I915_READ(SDEIIR)); | |
617 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
618 | I915_READ(SDEIMR)); | |
619 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
620 | I915_READ(GTIER)); | |
621 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
622 | I915_READ(GTIIR)); | |
623 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
624 | I915_READ(GTIMR)); | |
625 | } | |
2017263e BG |
626 | seq_printf(m, "Interrupts received: %d\n", |
627 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 628 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 629 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
630 | seq_printf(m, |
631 | "Graphics Interrupt mask (%s): %08x\n", | |
632 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 633 | } |
a2c7f6fd | 634 | i915_ring_seqno_info(m, ring); |
9862e600 | 635 | } |
de227ef0 CW |
636 | mutex_unlock(&dev->struct_mutex); |
637 | ||
2017263e BG |
638 | return 0; |
639 | } | |
640 | ||
a6172a80 CW |
641 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
642 | { | |
643 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
644 | struct drm_device *dev = node->minor->dev; | |
645 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
646 | int i, ret; |
647 | ||
648 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
649 | if (ret) | |
650 | return ret; | |
a6172a80 CW |
651 | |
652 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
653 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
654 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 655 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 656 | |
6c085a72 CW |
657 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
658 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 659 | if (obj == NULL) |
267f0c90 | 660 | seq_puts(m, "unused"); |
c2c347a9 | 661 | else |
05394f39 | 662 | describe_obj(m, obj); |
267f0c90 | 663 | seq_putc(m, '\n'); |
a6172a80 CW |
664 | } |
665 | ||
05394f39 | 666 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
667 | return 0; |
668 | } | |
669 | ||
2017263e BG |
670 | static int i915_hws_info(struct seq_file *m, void *data) |
671 | { | |
672 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
673 | struct drm_device *dev = node->minor->dev; | |
674 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 675 | struct intel_ring_buffer *ring; |
1a240d4d | 676 | const u32 *hws; |
4066c0ae CW |
677 | int i; |
678 | ||
1ec14ad3 | 679 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 680 | hws = ring->status_page.page_addr; |
2017263e BG |
681 | if (hws == NULL) |
682 | return 0; | |
683 | ||
684 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
685 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
686 | i * 4, | |
687 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
688 | } | |
689 | return 0; | |
690 | } | |
691 | ||
d5442303 DV |
692 | static ssize_t |
693 | i915_error_state_write(struct file *filp, | |
694 | const char __user *ubuf, | |
695 | size_t cnt, | |
696 | loff_t *ppos) | |
697 | { | |
edc3d884 | 698 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 699 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 700 | int ret; |
d5442303 DV |
701 | |
702 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
703 | ||
22bcfc6a DV |
704 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
705 | if (ret) | |
706 | return ret; | |
707 | ||
d5442303 DV |
708 | i915_destroy_error_state(dev); |
709 | mutex_unlock(&dev->struct_mutex); | |
710 | ||
711 | return cnt; | |
712 | } | |
713 | ||
714 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
715 | { | |
716 | struct drm_device *dev = inode->i_private; | |
d5442303 | 717 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
718 | |
719 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
720 | if (!error_priv) | |
721 | return -ENOMEM; | |
722 | ||
723 | error_priv->dev = dev; | |
724 | ||
95d5bfb3 | 725 | i915_error_state_get(dev, error_priv); |
d5442303 | 726 | |
edc3d884 MK |
727 | file->private_data = error_priv; |
728 | ||
729 | return 0; | |
d5442303 DV |
730 | } |
731 | ||
732 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
733 | { | |
edc3d884 | 734 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 735 | |
95d5bfb3 | 736 | i915_error_state_put(error_priv); |
d5442303 DV |
737 | kfree(error_priv); |
738 | ||
edc3d884 MK |
739 | return 0; |
740 | } | |
741 | ||
4dc955f7 MK |
742 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
743 | size_t count, loff_t *pos) | |
744 | { | |
745 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
746 | struct drm_i915_error_state_buf error_str; | |
747 | loff_t tmp_pos = 0; | |
748 | ssize_t ret_count = 0; | |
749 | int ret; | |
750 | ||
751 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
752 | if (ret) | |
753 | return ret; | |
edc3d884 | 754 | |
fc16b48b | 755 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
756 | if (ret) |
757 | goto out; | |
758 | ||
edc3d884 MK |
759 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
760 | error_str.buf, | |
761 | error_str.bytes); | |
762 | ||
763 | if (ret_count < 0) | |
764 | ret = ret_count; | |
765 | else | |
766 | *pos = error_str.start + ret_count; | |
767 | out: | |
4dc955f7 | 768 | i915_error_state_buf_release(&error_str); |
edc3d884 | 769 | return ret ?: ret_count; |
d5442303 DV |
770 | } |
771 | ||
772 | static const struct file_operations i915_error_state_fops = { | |
773 | .owner = THIS_MODULE, | |
774 | .open = i915_error_state_open, | |
edc3d884 | 775 | .read = i915_error_state_read, |
d5442303 DV |
776 | .write = i915_error_state_write, |
777 | .llseek = default_llseek, | |
778 | .release = i915_error_state_release, | |
779 | }; | |
780 | ||
647416f9 KC |
781 | static int |
782 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 783 | { |
647416f9 | 784 | struct drm_device *dev = data; |
40633219 | 785 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
786 | int ret; |
787 | ||
788 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
789 | if (ret) | |
790 | return ret; | |
791 | ||
647416f9 | 792 | *val = dev_priv->next_seqno; |
40633219 MK |
793 | mutex_unlock(&dev->struct_mutex); |
794 | ||
647416f9 | 795 | return 0; |
40633219 MK |
796 | } |
797 | ||
647416f9 KC |
798 | static int |
799 | i915_next_seqno_set(void *data, u64 val) | |
800 | { | |
801 | struct drm_device *dev = data; | |
40633219 MK |
802 | int ret; |
803 | ||
40633219 MK |
804 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
805 | if (ret) | |
806 | return ret; | |
807 | ||
e94fbaa8 | 808 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
809 | mutex_unlock(&dev->struct_mutex); |
810 | ||
647416f9 | 811 | return ret; |
40633219 MK |
812 | } |
813 | ||
647416f9 KC |
814 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
815 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 816 | "0x%llx\n"); |
40633219 | 817 | |
f97108d1 JB |
818 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
819 | { | |
820 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
821 | struct drm_device *dev = node->minor->dev; | |
822 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
823 | u16 crstanddelay; |
824 | int ret; | |
825 | ||
826 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
827 | if (ret) | |
828 | return ret; | |
829 | ||
830 | crstanddelay = I915_READ16(CRSTANDVID); | |
831 | ||
832 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
833 | |
834 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
839 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
840 | { | |
841 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
842 | struct drm_device *dev = node->minor->dev; | |
843 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 844 | int ret; |
3b8d8d91 JB |
845 | |
846 | if (IS_GEN5(dev)) { | |
847 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
848 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
849 | ||
850 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
851 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
852 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
853 | MEMSTAT_VID_SHIFT); | |
854 | seq_printf(m, "Current P-state: %d\n", | |
855 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 856 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
857 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
858 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
859 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
8e8c06cd | 860 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
861 | u32 rpupei, rpcurup, rpprevup; |
862 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
863 | int max_freq; |
864 | ||
865 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
866 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
867 | if (ret) | |
868 | return ret; | |
869 | ||
fcca7926 | 870 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 871 | |
8e8c06cd CW |
872 | reqf = I915_READ(GEN6_RPNSWREQ); |
873 | reqf &= ~GEN6_TURBO_DISABLE; | |
874 | if (IS_HASWELL(dev)) | |
875 | reqf >>= 24; | |
876 | else | |
877 | reqf >>= 25; | |
878 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
879 | ||
ccab5c82 JB |
880 | rpstat = I915_READ(GEN6_RPSTAT1); |
881 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
882 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
883 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
884 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
885 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
886 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
887 | if (IS_HASWELL(dev)) |
888 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
889 | else | |
890 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
891 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 892 | |
d1ebd816 BW |
893 | gen6_gt_force_wake_put(dev_priv); |
894 | mutex_unlock(&dev->struct_mutex); | |
895 | ||
3b8d8d91 | 896 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 897 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
898 | seq_printf(m, "Render p-state ratio: %d\n", |
899 | (gt_perf_status & 0xff00) >> 8); | |
900 | seq_printf(m, "Render p-state VID: %d\n", | |
901 | gt_perf_status & 0xff); | |
902 | seq_printf(m, "Render p-state limit: %d\n", | |
903 | rp_state_limits & 0xff); | |
8e8c06cd | 904 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 905 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
906 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
907 | GEN6_CURICONT_MASK); | |
908 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
909 | GEN6_CURBSYTAVG_MASK); | |
910 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
911 | GEN6_CURBSYTAVG_MASK); | |
912 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
913 | GEN6_CURIAVG_MASK); | |
914 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
915 | GEN6_CURBSYTAVG_MASK); | |
916 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
917 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
918 | |
919 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
920 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 921 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
922 | |
923 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
924 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 925 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
926 | |
927 | max_freq = rp_state_cap & 0xff; | |
928 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 929 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
930 | |
931 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
932 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
933 | } else if (IS_VALLEYVIEW(dev)) { |
934 | u32 freq_sts, val; | |
935 | ||
259bd5d4 | 936 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 937 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
938 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
939 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
940 | ||
64936258 | 941 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
942 | seq_printf(m, "max GPU freq: %d MHz\n", |
943 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
944 | ||
64936258 | 945 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
946 | seq_printf(m, "min GPU freq: %d MHz\n", |
947 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
948 | ||
949 | seq_printf(m, "current GPU freq: %d MHz\n", | |
950 | vlv_gpu_freq(dev_priv->mem_freq, | |
951 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 952 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 953 | } else { |
267f0c90 | 954 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 955 | } |
f97108d1 JB |
956 | |
957 | return 0; | |
958 | } | |
959 | ||
960 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
961 | { | |
962 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
963 | struct drm_device *dev = node->minor->dev; | |
964 | drm_i915_private_t *dev_priv = dev->dev_private; | |
965 | u32 delayfreq; | |
616fdb5a BW |
966 | int ret, i; |
967 | ||
968 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
969 | if (ret) | |
970 | return ret; | |
f97108d1 JB |
971 | |
972 | for (i = 0; i < 16; i++) { | |
973 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
974 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
975 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
976 | } |
977 | ||
616fdb5a BW |
978 | mutex_unlock(&dev->struct_mutex); |
979 | ||
f97108d1 JB |
980 | return 0; |
981 | } | |
982 | ||
983 | static inline int MAP_TO_MV(int map) | |
984 | { | |
985 | return 1250 - (map * 25); | |
986 | } | |
987 | ||
988 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
989 | { | |
990 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
991 | struct drm_device *dev = node->minor->dev; | |
992 | drm_i915_private_t *dev_priv = dev->dev_private; | |
993 | u32 inttoext; | |
616fdb5a BW |
994 | int ret, i; |
995 | ||
996 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
997 | if (ret) | |
998 | return ret; | |
f97108d1 JB |
999 | |
1000 | for (i = 1; i <= 32; i++) { | |
1001 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1002 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1003 | } | |
1004 | ||
616fdb5a BW |
1005 | mutex_unlock(&dev->struct_mutex); |
1006 | ||
f97108d1 JB |
1007 | return 0; |
1008 | } | |
1009 | ||
4d85529d | 1010 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1011 | { |
1012 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1013 | struct drm_device *dev = node->minor->dev; | |
1014 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1015 | u32 rgvmodectl, rstdbyctl; |
1016 | u16 crstandvid; | |
1017 | int ret; | |
1018 | ||
1019 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1020 | if (ret) | |
1021 | return ret; | |
1022 | ||
1023 | rgvmodectl = I915_READ(MEMMODECTL); | |
1024 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1025 | crstandvid = I915_READ16(CRSTANDVID); | |
1026 | ||
1027 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1028 | |
1029 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1030 | "yes" : "no"); | |
1031 | seq_printf(m, "Boost freq: %d\n", | |
1032 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1033 | MEMMODE_BOOST_FREQ_SHIFT); | |
1034 | seq_printf(m, "HW control enabled: %s\n", | |
1035 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1036 | seq_printf(m, "SW control enabled: %s\n", | |
1037 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1038 | seq_printf(m, "Gated voltage change: %s\n", | |
1039 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1040 | seq_printf(m, "Starting frequency: P%d\n", | |
1041 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1042 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1043 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1044 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1045 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1046 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1047 | seq_printf(m, "Render standby enabled: %s\n", | |
1048 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1049 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1050 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1051 | case RSX_STATUS_ON: | |
267f0c90 | 1052 | seq_puts(m, "on\n"); |
88271da3 JB |
1053 | break; |
1054 | case RSX_STATUS_RC1: | |
267f0c90 | 1055 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1056 | break; |
1057 | case RSX_STATUS_RC1E: | |
267f0c90 | 1058 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1059 | break; |
1060 | case RSX_STATUS_RS1: | |
267f0c90 | 1061 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1062 | break; |
1063 | case RSX_STATUS_RS2: | |
267f0c90 | 1064 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1065 | break; |
1066 | case RSX_STATUS_RS3: | |
267f0c90 | 1067 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1068 | break; |
1069 | default: | |
267f0c90 | 1070 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1071 | break; |
1072 | } | |
f97108d1 JB |
1073 | |
1074 | return 0; | |
1075 | } | |
1076 | ||
4d85529d BW |
1077 | static int gen6_drpc_info(struct seq_file *m) |
1078 | { | |
1079 | ||
1080 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1081 | struct drm_device *dev = node->minor->dev; | |
1082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1083 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1084 | unsigned forcewake_count; |
aee56cff | 1085 | int count = 0, ret; |
4d85529d BW |
1086 | |
1087 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1088 | if (ret) | |
1089 | return ret; | |
1090 | ||
907b28c5 CW |
1091 | spin_lock_irq(&dev_priv->uncore.lock); |
1092 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1093 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1094 | |
1095 | if (forcewake_count) { | |
267f0c90 DL |
1096 | seq_puts(m, "RC information inaccurate because somebody " |
1097 | "holds a forcewake reference \n"); | |
4d85529d BW |
1098 | } else { |
1099 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1100 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1101 | udelay(10); | |
1102 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1103 | } | |
1104 | ||
1105 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1106 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1107 | |
1108 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1109 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1110 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1111 | mutex_lock(&dev_priv->rps.hw_lock); |
1112 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1113 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1114 | |
1115 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1116 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1117 | seq_printf(m, "HW control enabled: %s\n", | |
1118 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1119 | seq_printf(m, "SW control enabled: %s\n", | |
1120 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1121 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1122 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1123 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1124 | seq_printf(m, "RC6 Enabled: %s\n", | |
1125 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1126 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1127 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1128 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1129 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1130 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1131 | switch (gt_core_status & GEN6_RCn_MASK) { |
1132 | case GEN6_RC0: | |
1133 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1134 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1135 | else |
267f0c90 | 1136 | seq_puts(m, "on\n"); |
4d85529d BW |
1137 | break; |
1138 | case GEN6_RC3: | |
267f0c90 | 1139 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1140 | break; |
1141 | case GEN6_RC6: | |
267f0c90 | 1142 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1143 | break; |
1144 | case GEN6_RC7: | |
267f0c90 | 1145 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1146 | break; |
1147 | default: | |
267f0c90 | 1148 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1149 | break; |
1150 | } | |
1151 | ||
1152 | seq_printf(m, "Core Power Down: %s\n", | |
1153 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1154 | |
1155 | /* Not exactly sure what this is */ | |
1156 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1157 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1158 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1159 | I915_READ(GEN6_GT_GFX_RC6)); | |
1160 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1161 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1162 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1163 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1164 | ||
ecd8faea BW |
1165 | seq_printf(m, "RC6 voltage: %dmV\n", |
1166 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1167 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1168 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1169 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1170 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1171 | return 0; |
1172 | } | |
1173 | ||
1174 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1175 | { | |
1176 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1177 | struct drm_device *dev = node->minor->dev; | |
1178 | ||
1179 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1180 | return gen6_drpc_info(m); | |
1181 | else | |
1182 | return ironlake_drpc_info(m); | |
1183 | } | |
1184 | ||
b5e50c3f JB |
1185 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1186 | { | |
1187 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1188 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1189 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1190 | |
ee5382ae | 1191 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1192 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1193 | return 0; |
1194 | } | |
1195 | ||
ee5382ae | 1196 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1197 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1198 | } else { |
267f0c90 | 1199 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1200 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1201 | case FBC_OK: |
1202 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1203 | break; | |
1204 | case FBC_UNSUPPORTED: | |
1205 | seq_puts(m, "unsupported by this chipset"); | |
1206 | break; | |
bed4a673 | 1207 | case FBC_NO_OUTPUT: |
267f0c90 | 1208 | seq_puts(m, "no outputs"); |
bed4a673 | 1209 | break; |
b5e50c3f | 1210 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1211 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1212 | break; |
1213 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1214 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1215 | break; |
1216 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1217 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1218 | break; |
1219 | case FBC_BAD_PLANE: | |
267f0c90 | 1220 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1221 | break; |
1222 | case FBC_NOT_TILED: | |
267f0c90 | 1223 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1224 | break; |
9c928d16 | 1225 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1226 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1227 | break; |
c1a9f047 | 1228 | case FBC_MODULE_PARAM: |
267f0c90 | 1229 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1230 | break; |
8a5729a3 | 1231 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1232 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1233 | break; |
b5e50c3f | 1234 | default: |
267f0c90 | 1235 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1236 | } |
267f0c90 | 1237 | seq_putc(m, '\n'); |
b5e50c3f JB |
1238 | } |
1239 | return 0; | |
1240 | } | |
1241 | ||
92d44621 PZ |
1242 | static int i915_ips_status(struct seq_file *m, void *unused) |
1243 | { | |
1244 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1245 | struct drm_device *dev = node->minor->dev; | |
1246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1247 | ||
f5adf94e | 1248 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1249 | seq_puts(m, "not supported\n"); |
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1254 | seq_puts(m, "enabled\n"); | |
1255 | else | |
1256 | seq_puts(m, "disabled\n"); | |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
4a9bef37 JB |
1261 | static int i915_sr_status(struct seq_file *m, void *unused) |
1262 | { | |
1263 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1264 | struct drm_device *dev = node->minor->dev; | |
1265 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1266 | bool sr_enabled = false; | |
1267 | ||
1398261a | 1268 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1269 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1270 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1271 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1272 | else if (IS_I915GM(dev)) | |
1273 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1274 | else if (IS_PINEVIEW(dev)) | |
1275 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1276 | ||
5ba2aaaa CW |
1277 | seq_printf(m, "self-refresh: %s\n", |
1278 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1279 | |
1280 | return 0; | |
1281 | } | |
1282 | ||
7648fa99 JB |
1283 | static int i915_emon_status(struct seq_file *m, void *unused) |
1284 | { | |
1285 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1286 | struct drm_device *dev = node->minor->dev; | |
1287 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1288 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1289 | int ret; |
1290 | ||
582be6b4 CW |
1291 | if (!IS_GEN5(dev)) |
1292 | return -ENODEV; | |
1293 | ||
de227ef0 CW |
1294 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1295 | if (ret) | |
1296 | return ret; | |
7648fa99 JB |
1297 | |
1298 | temp = i915_mch_val(dev_priv); | |
1299 | chipset = i915_chipset_val(dev_priv); | |
1300 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1301 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1302 | |
1303 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1304 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1305 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1306 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
23b2f8bb JB |
1311 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1312 | { | |
1313 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1314 | struct drm_device *dev = node->minor->dev; | |
1315 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1316 | int ret; | |
1317 | int gpu_freq, ia_freq; | |
1318 | ||
1c70c0ce | 1319 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1320 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1321 | return 0; |
1322 | } | |
1323 | ||
4fc688ce | 1324 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1325 | if (ret) |
1326 | return ret; | |
1327 | ||
267f0c90 | 1328 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1329 | |
c6a828d3 DV |
1330 | for (gpu_freq = dev_priv->rps.min_delay; |
1331 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1332 | gpu_freq++) { |
42c0526c BW |
1333 | ia_freq = gpu_freq; |
1334 | sandybridge_pcode_read(dev_priv, | |
1335 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1336 | &ia_freq); | |
3ebecd07 CW |
1337 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1338 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1339 | ((ia_freq >> 0) & 0xff) * 100, | |
1340 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1341 | } |
1342 | ||
4fc688ce | 1343 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1344 | |
1345 | return 0; | |
1346 | } | |
1347 | ||
7648fa99 JB |
1348 | static int i915_gfxec(struct seq_file *m, void *unused) |
1349 | { | |
1350 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1351 | struct drm_device *dev = node->minor->dev; | |
1352 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1353 | int ret; |
1354 | ||
1355 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1356 | if (ret) | |
1357 | return ret; | |
7648fa99 JB |
1358 | |
1359 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1360 | ||
616fdb5a BW |
1361 | mutex_unlock(&dev->struct_mutex); |
1362 | ||
7648fa99 JB |
1363 | return 0; |
1364 | } | |
1365 | ||
44834a67 CW |
1366 | static int i915_opregion(struct seq_file *m, void *unused) |
1367 | { | |
1368 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1369 | struct drm_device *dev = node->minor->dev; | |
1370 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1371 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1372 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1373 | int ret; |
1374 | ||
0d38f009 DV |
1375 | if (data == NULL) |
1376 | return -ENOMEM; | |
1377 | ||
44834a67 CW |
1378 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1379 | if (ret) | |
0d38f009 | 1380 | goto out; |
44834a67 | 1381 | |
0d38f009 DV |
1382 | if (opregion->header) { |
1383 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1384 | seq_write(m, data, OPREGION_SIZE); | |
1385 | } | |
44834a67 CW |
1386 | |
1387 | mutex_unlock(&dev->struct_mutex); | |
1388 | ||
0d38f009 DV |
1389 | out: |
1390 | kfree(data); | |
44834a67 CW |
1391 | return 0; |
1392 | } | |
1393 | ||
37811fcc CW |
1394 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1395 | { | |
1396 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1397 | struct drm_device *dev = node->minor->dev; | |
1398 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1399 | struct intel_fbdev *ifbdev; | |
1400 | struct intel_framebuffer *fb; | |
1401 | int ret; | |
1402 | ||
1403 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1404 | if (ret) | |
1405 | return ret; | |
1406 | ||
1407 | ifbdev = dev_priv->fbdev; | |
1408 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1409 | ||
623f9783 | 1410 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1411 | fb->base.width, |
1412 | fb->base.height, | |
1413 | fb->base.depth, | |
623f9783 DV |
1414 | fb->base.bits_per_pixel, |
1415 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1416 | describe_obj(m, fb->obj); |
267f0c90 | 1417 | seq_putc(m, '\n'); |
4b096ac1 | 1418 | mutex_unlock(&dev->mode_config.mutex); |
37811fcc | 1419 | |
4b096ac1 | 1420 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1421 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1422 | if (&fb->base == ifbdev->helper.fb) | |
1423 | continue; | |
1424 | ||
623f9783 | 1425 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1426 | fb->base.width, |
1427 | fb->base.height, | |
1428 | fb->base.depth, | |
623f9783 DV |
1429 | fb->base.bits_per_pixel, |
1430 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1431 | describe_obj(m, fb->obj); |
267f0c90 | 1432 | seq_putc(m, '\n'); |
37811fcc | 1433 | } |
4b096ac1 | 1434 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1435 | |
1436 | return 0; | |
1437 | } | |
1438 | ||
e76d3630 BW |
1439 | static int i915_context_status(struct seq_file *m, void *unused) |
1440 | { | |
1441 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1442 | struct drm_device *dev = node->minor->dev; | |
1443 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 BW |
1444 | struct intel_ring_buffer *ring; |
1445 | int ret, i; | |
e76d3630 BW |
1446 | |
1447 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1448 | if (ret) | |
1449 | return ret; | |
1450 | ||
3e373948 | 1451 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1452 | seq_puts(m, "power context "); |
3e373948 | 1453 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1454 | seq_putc(m, '\n'); |
dc501fbc | 1455 | } |
e76d3630 | 1456 | |
3e373948 | 1457 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1458 | seq_puts(m, "render context "); |
3e373948 | 1459 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1460 | seq_putc(m, '\n'); |
dc501fbc | 1461 | } |
e76d3630 | 1462 | |
a168c293 BW |
1463 | for_each_ring(ring, dev_priv, i) { |
1464 | if (ring->default_context) { | |
472f8acc | 1465 | seq_printf(m, "HW default context %s ", ring->name); |
a168c293 | 1466 | describe_obj(m, ring->default_context->obj); |
267f0c90 | 1467 | seq_putc(m, '\n'); |
a168c293 BW |
1468 | } |
1469 | } | |
1470 | ||
e76d3630 BW |
1471 | mutex_unlock(&dev->mode_config.mutex); |
1472 | ||
1473 | return 0; | |
1474 | } | |
1475 | ||
6d794d42 BW |
1476 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1477 | { | |
1478 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1479 | struct drm_device *dev = node->minor->dev; | |
1480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1481 | unsigned forcewake_count; |
6d794d42 | 1482 | |
907b28c5 CW |
1483 | spin_lock_irq(&dev_priv->uncore.lock); |
1484 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1485 | spin_unlock_irq(&dev_priv->uncore.lock); | |
6d794d42 | 1486 | |
9f1f46a4 | 1487 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1488 | |
1489 | return 0; | |
1490 | } | |
1491 | ||
ea16a3cd DV |
1492 | static const char *swizzle_string(unsigned swizzle) |
1493 | { | |
aee56cff | 1494 | switch (swizzle) { |
ea16a3cd DV |
1495 | case I915_BIT_6_SWIZZLE_NONE: |
1496 | return "none"; | |
1497 | case I915_BIT_6_SWIZZLE_9: | |
1498 | return "bit9"; | |
1499 | case I915_BIT_6_SWIZZLE_9_10: | |
1500 | return "bit9/bit10"; | |
1501 | case I915_BIT_6_SWIZZLE_9_11: | |
1502 | return "bit9/bit11"; | |
1503 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1504 | return "bit9/bit10/bit11"; | |
1505 | case I915_BIT_6_SWIZZLE_9_17: | |
1506 | return "bit9/bit17"; | |
1507 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1508 | return "bit9/bit10/bit17"; | |
1509 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1510 | return "unknown"; |
ea16a3cd DV |
1511 | } |
1512 | ||
1513 | return "bug"; | |
1514 | } | |
1515 | ||
1516 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1517 | { | |
1518 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1519 | struct drm_device *dev = node->minor->dev; | |
1520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1521 | int ret; |
1522 | ||
1523 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1524 | if (ret) | |
1525 | return ret; | |
ea16a3cd | 1526 | |
ea16a3cd DV |
1527 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1528 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1529 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1530 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1531 | ||
1532 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1533 | seq_printf(m, "DDC = 0x%08x\n", | |
1534 | I915_READ(DCC)); | |
1535 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1536 | I915_READ16(C0DRB3)); | |
1537 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1538 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1539 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1540 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1541 | I915_READ(MAD_DIMM_C0)); | |
1542 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1543 | I915_READ(MAD_DIMM_C1)); | |
1544 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1545 | I915_READ(MAD_DIMM_C2)); | |
1546 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1547 | I915_READ(TILECTL)); | |
1548 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1549 | I915_READ(ARB_MODE)); | |
1550 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1551 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1552 | } |
1553 | mutex_unlock(&dev->struct_mutex); | |
1554 | ||
1555 | return 0; | |
1556 | } | |
1557 | ||
3cf17fc5 DV |
1558 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1559 | { | |
1560 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1561 | struct drm_device *dev = node->minor->dev; | |
1562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1563 | struct intel_ring_buffer *ring; | |
1564 | int i, ret; | |
1565 | ||
1566 | ||
1567 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1568 | if (ret) | |
1569 | return ret; | |
1570 | if (INTEL_INFO(dev)->gen == 6) | |
1571 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1572 | ||
a2c7f6fd | 1573 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1574 | seq_printf(m, "%s\n", ring->name); |
1575 | if (INTEL_INFO(dev)->gen == 7) | |
1576 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1577 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1578 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1579 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1580 | } | |
1581 | if (dev_priv->mm.aliasing_ppgtt) { | |
1582 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1583 | ||
267f0c90 | 1584 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1585 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1586 | } | |
1587 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1588 | mutex_unlock(&dev->struct_mutex); | |
1589 | ||
1590 | return 0; | |
1591 | } | |
1592 | ||
57f350b6 JB |
1593 | static int i915_dpio_info(struct seq_file *m, void *data) |
1594 | { | |
1595 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1596 | struct drm_device *dev = node->minor->dev; | |
1597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1598 | int ret; | |
1599 | ||
1600 | ||
1601 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1602 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1603 | return 0; |
1604 | } | |
1605 | ||
09153000 | 1606 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1607 | if (ret) |
1608 | return ret; | |
1609 | ||
1610 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1611 | ||
1612 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
5e69f97f | 1613 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); |
57f350b6 | 1614 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
5e69f97f | 1615 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); |
57f350b6 JB |
1616 | |
1617 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
5e69f97f | 1618 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); |
57f350b6 | 1619 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
5e69f97f | 1620 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); |
57f350b6 JB |
1621 | |
1622 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
5e69f97f | 1623 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); |
57f350b6 | 1624 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
5e69f97f | 1625 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); |
57f350b6 | 1626 | |
4abb2c39 | 1627 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
5e69f97f | 1628 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); |
4abb2c39 | 1629 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", |
5e69f97f | 1630 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); |
57f350b6 JB |
1631 | |
1632 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
5e69f97f | 1633 | vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1634 | |
09153000 | 1635 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1636 | |
1637 | return 0; | |
1638 | } | |
1639 | ||
63573eb7 BW |
1640 | static int i915_llc(struct seq_file *m, void *data) |
1641 | { | |
1642 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1643 | struct drm_device *dev = node->minor->dev; | |
1644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1645 | ||
1646 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1647 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1648 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1649 | ||
1650 | return 0; | |
1651 | } | |
1652 | ||
e91fd8c6 RV |
1653 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1654 | { | |
1655 | struct drm_info_node *node = m->private; | |
1656 | struct drm_device *dev = node->minor->dev; | |
1657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3f51e471 | 1658 | u32 psrstat, psrperf; |
e91fd8c6 RV |
1659 | |
1660 | if (!IS_HASWELL(dev)) { | |
1661 | seq_puts(m, "PSR not supported on this platform\n"); | |
3f51e471 RV |
1662 | } else if (IS_HASWELL(dev) && I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) { |
1663 | seq_puts(m, "PSR enabled\n"); | |
1664 | } else { | |
1665 | seq_puts(m, "PSR disabled: "); | |
1666 | switch (dev_priv->no_psr_reason) { | |
1667 | case PSR_NO_SOURCE: | |
1668 | seq_puts(m, "not supported on this platform"); | |
1669 | break; | |
1670 | case PSR_NO_SINK: | |
1671 | seq_puts(m, "not supported by panel"); | |
1672 | break; | |
105b7c11 RV |
1673 | case PSR_MODULE_PARAM: |
1674 | seq_puts(m, "disabled by flag"); | |
1675 | break; | |
3f51e471 RV |
1676 | case PSR_CRTC_NOT_ACTIVE: |
1677 | seq_puts(m, "crtc not active"); | |
1678 | break; | |
1679 | case PSR_PWR_WELL_ENABLED: | |
1680 | seq_puts(m, "power well enabled"); | |
1681 | break; | |
1682 | case PSR_NOT_TILED: | |
1683 | seq_puts(m, "not tiled"); | |
1684 | break; | |
1685 | case PSR_SPRITE_ENABLED: | |
1686 | seq_puts(m, "sprite enabled"); | |
1687 | break; | |
1688 | case PSR_S3D_ENABLED: | |
1689 | seq_puts(m, "stereo 3d enabled"); | |
1690 | break; | |
1691 | case PSR_INTERLACED_ENABLED: | |
1692 | seq_puts(m, "interlaced enabled"); | |
1693 | break; | |
1694 | case PSR_HSW_NOT_DDIA: | |
1695 | seq_puts(m, "HSW ties PSR to DDI A (eDP)"); | |
1696 | break; | |
1697 | default: | |
1698 | seq_puts(m, "unknown reason"); | |
1699 | } | |
1700 | seq_puts(m, "\n"); | |
e91fd8c6 RV |
1701 | return 0; |
1702 | } | |
1703 | ||
e91fd8c6 RV |
1704 | psrstat = I915_READ(EDP_PSR_STATUS_CTL); |
1705 | ||
1706 | seq_puts(m, "PSR Current State: "); | |
1707 | switch (psrstat & EDP_PSR_STATUS_STATE_MASK) { | |
1708 | case EDP_PSR_STATUS_STATE_IDLE: | |
1709 | seq_puts(m, "Reset state\n"); | |
1710 | break; | |
1711 | case EDP_PSR_STATUS_STATE_SRDONACK: | |
1712 | seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n"); | |
1713 | break; | |
1714 | case EDP_PSR_STATUS_STATE_SRDENT: | |
1715 | seq_puts(m, "SRD entry\n"); | |
1716 | break; | |
1717 | case EDP_PSR_STATUS_STATE_BUFOFF: | |
1718 | seq_puts(m, "Wait for buffer turn off\n"); | |
1719 | break; | |
1720 | case EDP_PSR_STATUS_STATE_BUFON: | |
1721 | seq_puts(m, "Wait for buffer turn on\n"); | |
1722 | break; | |
1723 | case EDP_PSR_STATUS_STATE_AUXACK: | |
1724 | seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n"); | |
1725 | break; | |
1726 | case EDP_PSR_STATUS_STATE_SRDOFFACK: | |
1727 | seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n"); | |
1728 | break; | |
1729 | default: | |
1730 | seq_puts(m, "Unknown\n"); | |
1731 | break; | |
1732 | } | |
1733 | ||
1734 | seq_puts(m, "Link Status: "); | |
1735 | switch (psrstat & EDP_PSR_STATUS_LINK_MASK) { | |
1736 | case EDP_PSR_STATUS_LINK_FULL_OFF: | |
1737 | seq_puts(m, "Link is fully off\n"); | |
1738 | break; | |
1739 | case EDP_PSR_STATUS_LINK_FULL_ON: | |
1740 | seq_puts(m, "Link is fully on\n"); | |
1741 | break; | |
1742 | case EDP_PSR_STATUS_LINK_STANDBY: | |
1743 | seq_puts(m, "Link is in standby\n"); | |
1744 | break; | |
1745 | default: | |
1746 | seq_puts(m, "Unknown\n"); | |
1747 | break; | |
1748 | } | |
1749 | ||
1750 | seq_printf(m, "PSR Entry Count: %u\n", | |
1751 | psrstat >> EDP_PSR_STATUS_COUNT_SHIFT & | |
1752 | EDP_PSR_STATUS_COUNT_MASK); | |
1753 | ||
1754 | seq_printf(m, "Max Sleep Timer Counter: %u\n", | |
1755 | psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT & | |
1756 | EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK); | |
1757 | ||
1758 | seq_printf(m, "Had AUX error: %s\n", | |
1759 | yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR)); | |
1760 | ||
1761 | seq_printf(m, "Sending AUX: %s\n", | |
1762 | yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING)); | |
1763 | ||
1764 | seq_printf(m, "Sending Idle: %s\n", | |
1765 | yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE)); | |
1766 | ||
1767 | seq_printf(m, "Sending TP2 TP3: %s\n", | |
1768 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3)); | |
1769 | ||
1770 | seq_printf(m, "Sending TP1: %s\n", | |
1771 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1)); | |
1772 | ||
1773 | seq_printf(m, "Idle Count: %u\n", | |
1774 | psrstat & EDP_PSR_STATUS_IDLE_MASK); | |
1775 | ||
1776 | psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK; | |
1777 | seq_printf(m, "Performance Counter: %u\n", psrperf); | |
1778 | ||
1779 | return 0; | |
1780 | } | |
1781 | ||
ec013e7f JB |
1782 | static int i915_energy_uJ(struct seq_file *m, void *data) |
1783 | { | |
1784 | struct drm_info_node *node = m->private; | |
1785 | struct drm_device *dev = node->minor->dev; | |
1786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1787 | u64 power; | |
1788 | u32 units; | |
1789 | ||
1790 | if (INTEL_INFO(dev)->gen < 6) | |
1791 | return -ENODEV; | |
1792 | ||
1793 | rdmsrl(MSR_RAPL_POWER_UNIT, power); | |
1794 | power = (power & 0x1f00) >> 8; | |
1795 | units = 1000000 / (1 << power); /* convert to uJ */ | |
1796 | power = I915_READ(MCH_SECP_NRG_STTS); | |
1797 | power *= units; | |
1798 | ||
1799 | seq_printf(m, "%llu", (long long unsigned)power); | |
371db66a PZ |
1800 | |
1801 | return 0; | |
1802 | } | |
1803 | ||
1804 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
1805 | { | |
1806 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1807 | struct drm_device *dev = node->minor->dev; | |
1808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1809 | ||
1810 | if (!IS_HASWELL(dev)) { | |
1811 | seq_puts(m, "not supported\n"); | |
1812 | return 0; | |
1813 | } | |
1814 | ||
1815 | mutex_lock(&dev_priv->pc8.lock); | |
1816 | seq_printf(m, "Requirements met: %s\n", | |
1817 | yesno(dev_priv->pc8.requirements_met)); | |
1818 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); | |
1819 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); | |
1820 | seq_printf(m, "IRQs disabled: %s\n", | |
1821 | yesno(dev_priv->pc8.irqs_disabled)); | |
1822 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); | |
1823 | mutex_unlock(&dev_priv->pc8.lock); | |
1824 | ||
ec013e7f JB |
1825 | return 0; |
1826 | } | |
1827 | ||
647416f9 KC |
1828 | static int |
1829 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 1830 | { |
647416f9 | 1831 | struct drm_device *dev = data; |
f3cd474b | 1832 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 1833 | |
647416f9 | 1834 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 1835 | |
647416f9 | 1836 | return 0; |
f3cd474b CW |
1837 | } |
1838 | ||
647416f9 KC |
1839 | static int |
1840 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 1841 | { |
647416f9 | 1842 | struct drm_device *dev = data; |
f3cd474b | 1843 | |
647416f9 | 1844 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 1845 | i915_handle_error(dev, val); |
f3cd474b | 1846 | |
647416f9 | 1847 | return 0; |
f3cd474b CW |
1848 | } |
1849 | ||
647416f9 KC |
1850 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
1851 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 1852 | "%llu\n"); |
f3cd474b | 1853 | |
647416f9 KC |
1854 | static int |
1855 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 1856 | { |
647416f9 | 1857 | struct drm_device *dev = data; |
e5eb3d63 | 1858 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 1859 | |
647416f9 | 1860 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 1861 | |
647416f9 | 1862 | return 0; |
e5eb3d63 DV |
1863 | } |
1864 | ||
647416f9 KC |
1865 | static int |
1866 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 1867 | { |
647416f9 | 1868 | struct drm_device *dev = data; |
e5eb3d63 | 1869 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1870 | int ret; |
e5eb3d63 | 1871 | |
647416f9 | 1872 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 1873 | |
22bcfc6a DV |
1874 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1875 | if (ret) | |
1876 | return ret; | |
1877 | ||
99584db3 | 1878 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
1879 | mutex_unlock(&dev->struct_mutex); |
1880 | ||
647416f9 | 1881 | return 0; |
e5eb3d63 DV |
1882 | } |
1883 | ||
647416f9 KC |
1884 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
1885 | i915_ring_stop_get, i915_ring_stop_set, | |
1886 | "0x%08llx\n"); | |
d5442303 | 1887 | |
dd624afd CW |
1888 | #define DROP_UNBOUND 0x1 |
1889 | #define DROP_BOUND 0x2 | |
1890 | #define DROP_RETIRE 0x4 | |
1891 | #define DROP_ACTIVE 0x8 | |
1892 | #define DROP_ALL (DROP_UNBOUND | \ | |
1893 | DROP_BOUND | \ | |
1894 | DROP_RETIRE | \ | |
1895 | DROP_ACTIVE) | |
647416f9 KC |
1896 | static int |
1897 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 1898 | { |
647416f9 | 1899 | *val = DROP_ALL; |
dd624afd | 1900 | |
647416f9 | 1901 | return 0; |
dd624afd CW |
1902 | } |
1903 | ||
647416f9 KC |
1904 | static int |
1905 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 1906 | { |
647416f9 | 1907 | struct drm_device *dev = data; |
dd624afd CW |
1908 | struct drm_i915_private *dev_priv = dev->dev_private; |
1909 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
1910 | struct i915_address_space *vm; |
1911 | struct i915_vma *vma, *x; | |
647416f9 | 1912 | int ret; |
dd624afd | 1913 | |
647416f9 | 1914 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
1915 | |
1916 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
1917 | * on ioctls on -EAGAIN. */ | |
1918 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1919 | if (ret) | |
1920 | return ret; | |
1921 | ||
1922 | if (val & DROP_ACTIVE) { | |
1923 | ret = i915_gpu_idle(dev); | |
1924 | if (ret) | |
1925 | goto unlock; | |
1926 | } | |
1927 | ||
1928 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
1929 | i915_gem_retire_requests(dev); | |
1930 | ||
1931 | if (val & DROP_BOUND) { | |
ca191b13 BW |
1932 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
1933 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
1934 | mm_list) { | |
1935 | if (vma->obj->pin_count) | |
1936 | continue; | |
1937 | ||
1938 | ret = i915_vma_unbind(vma); | |
1939 | if (ret) | |
1940 | goto unlock; | |
1941 | } | |
31a46c9c | 1942 | } |
dd624afd CW |
1943 | } |
1944 | ||
1945 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
1946 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
1947 | global_list) | |
dd624afd CW |
1948 | if (obj->pages_pin_count == 0) { |
1949 | ret = i915_gem_object_put_pages(obj); | |
1950 | if (ret) | |
1951 | goto unlock; | |
1952 | } | |
1953 | } | |
1954 | ||
1955 | unlock: | |
1956 | mutex_unlock(&dev->struct_mutex); | |
1957 | ||
647416f9 | 1958 | return ret; |
dd624afd CW |
1959 | } |
1960 | ||
647416f9 KC |
1961 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
1962 | i915_drop_caches_get, i915_drop_caches_set, | |
1963 | "0x%08llx\n"); | |
dd624afd | 1964 | |
647416f9 KC |
1965 | static int |
1966 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 1967 | { |
647416f9 | 1968 | struct drm_device *dev = data; |
358733e9 | 1969 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 1970 | int ret; |
004777cb DV |
1971 | |
1972 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1973 | return -ENODEV; | |
1974 | ||
4fc688ce | 1975 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1976 | if (ret) |
1977 | return ret; | |
358733e9 | 1978 | |
0a073b84 JB |
1979 | if (IS_VALLEYVIEW(dev)) |
1980 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
1981 | dev_priv->rps.max_delay); | |
1982 | else | |
1983 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 1984 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1985 | |
647416f9 | 1986 | return 0; |
358733e9 JB |
1987 | } |
1988 | ||
647416f9 KC |
1989 | static int |
1990 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 1991 | { |
647416f9 | 1992 | struct drm_device *dev = data; |
358733e9 | 1993 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1994 | int ret; |
004777cb DV |
1995 | |
1996 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1997 | return -ENODEV; | |
358733e9 | 1998 | |
647416f9 | 1999 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 2000 | |
4fc688ce | 2001 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2002 | if (ret) |
2003 | return ret; | |
2004 | ||
358733e9 JB |
2005 | /* |
2006 | * Turbo will still be enabled, but won't go above the set value. | |
2007 | */ | |
0a073b84 JB |
2008 | if (IS_VALLEYVIEW(dev)) { |
2009 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2010 | dev_priv->rps.max_delay = val; | |
2011 | gen6_set_rps(dev, val); | |
2012 | } else { | |
2013 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2014 | dev_priv->rps.max_delay = val; | |
2015 | gen6_set_rps(dev, val); | |
2016 | } | |
2017 | ||
4fc688ce | 2018 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2019 | |
647416f9 | 2020 | return 0; |
358733e9 JB |
2021 | } |
2022 | ||
647416f9 KC |
2023 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
2024 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 2025 | "%llu\n"); |
358733e9 | 2026 | |
647416f9 KC |
2027 | static int |
2028 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 2029 | { |
647416f9 | 2030 | struct drm_device *dev = data; |
1523c310 | 2031 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2032 | int ret; |
004777cb DV |
2033 | |
2034 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2035 | return -ENODEV; | |
2036 | ||
4fc688ce | 2037 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2038 | if (ret) |
2039 | return ret; | |
1523c310 | 2040 | |
0a073b84 JB |
2041 | if (IS_VALLEYVIEW(dev)) |
2042 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2043 | dev_priv->rps.min_delay); | |
2044 | else | |
2045 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2046 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2047 | |
647416f9 | 2048 | return 0; |
1523c310 JB |
2049 | } |
2050 | ||
647416f9 KC |
2051 | static int |
2052 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 2053 | { |
647416f9 | 2054 | struct drm_device *dev = data; |
1523c310 | 2055 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2056 | int ret; |
004777cb DV |
2057 | |
2058 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2059 | return -ENODEV; | |
1523c310 | 2060 | |
647416f9 | 2061 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 2062 | |
4fc688ce | 2063 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2064 | if (ret) |
2065 | return ret; | |
2066 | ||
1523c310 JB |
2067 | /* |
2068 | * Turbo will still be enabled, but won't go below the set value. | |
2069 | */ | |
0a073b84 JB |
2070 | if (IS_VALLEYVIEW(dev)) { |
2071 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2072 | dev_priv->rps.min_delay = val; | |
2073 | valleyview_set_rps(dev, val); | |
2074 | } else { | |
2075 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2076 | dev_priv->rps.min_delay = val; | |
2077 | gen6_set_rps(dev, val); | |
2078 | } | |
4fc688ce | 2079 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2080 | |
647416f9 | 2081 | return 0; |
1523c310 JB |
2082 | } |
2083 | ||
647416f9 KC |
2084 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
2085 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 2086 | "%llu\n"); |
1523c310 | 2087 | |
647416f9 KC |
2088 | static int |
2089 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 2090 | { |
647416f9 | 2091 | struct drm_device *dev = data; |
07b7ddd9 | 2092 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 2093 | u32 snpcr; |
647416f9 | 2094 | int ret; |
07b7ddd9 | 2095 | |
004777cb DV |
2096 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2097 | return -ENODEV; | |
2098 | ||
22bcfc6a DV |
2099 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2100 | if (ret) | |
2101 | return ret; | |
2102 | ||
07b7ddd9 JB |
2103 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
2104 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
2105 | ||
647416f9 | 2106 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 2107 | |
647416f9 | 2108 | return 0; |
07b7ddd9 JB |
2109 | } |
2110 | ||
647416f9 KC |
2111 | static int |
2112 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 2113 | { |
647416f9 | 2114 | struct drm_device *dev = data; |
07b7ddd9 | 2115 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 2116 | u32 snpcr; |
07b7ddd9 | 2117 | |
004777cb DV |
2118 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2119 | return -ENODEV; | |
2120 | ||
647416f9 | 2121 | if (val > 3) |
07b7ddd9 JB |
2122 | return -EINVAL; |
2123 | ||
647416f9 | 2124 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
2125 | |
2126 | /* Update the cache sharing policy here as well */ | |
2127 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
2128 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
2129 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
2130 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
2131 | ||
647416f9 | 2132 | return 0; |
07b7ddd9 JB |
2133 | } |
2134 | ||
647416f9 KC |
2135 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
2136 | i915_cache_sharing_get, i915_cache_sharing_set, | |
2137 | "%llu\n"); | |
07b7ddd9 | 2138 | |
f3cd474b CW |
2139 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
2140 | * allocated we need to hook into the minor for release. */ | |
2141 | static int | |
2142 | drm_add_fake_info_node(struct drm_minor *minor, | |
2143 | struct dentry *ent, | |
2144 | const void *key) | |
2145 | { | |
2146 | struct drm_info_node *node; | |
2147 | ||
2148 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
2149 | if (node == NULL) { | |
2150 | debugfs_remove(ent); | |
2151 | return -ENOMEM; | |
2152 | } | |
2153 | ||
2154 | node->minor = minor; | |
2155 | node->dent = ent; | |
2156 | node->info_ent = (void *) key; | |
b3e067c0 MS |
2157 | |
2158 | mutex_lock(&minor->debugfs_lock); | |
2159 | list_add(&node->list, &minor->debugfs_list); | |
2160 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
2161 | |
2162 | return 0; | |
2163 | } | |
2164 | ||
6d794d42 BW |
2165 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2166 | { | |
2167 | struct drm_device *dev = inode->i_private; | |
2168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2169 | |
075edca4 | 2170 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2171 | return 0; |
2172 | ||
6d794d42 | 2173 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2174 | |
2175 | return 0; | |
2176 | } | |
2177 | ||
c43b5634 | 2178 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2179 | { |
2180 | struct drm_device *dev = inode->i_private; | |
2181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2182 | ||
075edca4 | 2183 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2184 | return 0; |
2185 | ||
6d794d42 | 2186 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2187 | |
2188 | return 0; | |
2189 | } | |
2190 | ||
2191 | static const struct file_operations i915_forcewake_fops = { | |
2192 | .owner = THIS_MODULE, | |
2193 | .open = i915_forcewake_open, | |
2194 | .release = i915_forcewake_release, | |
2195 | }; | |
2196 | ||
2197 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2198 | { | |
2199 | struct drm_device *dev = minor->dev; | |
2200 | struct dentry *ent; | |
2201 | ||
2202 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2203 | S_IRUSR, |
6d794d42 BW |
2204 | root, dev, |
2205 | &i915_forcewake_fops); | |
2206 | if (IS_ERR(ent)) | |
2207 | return PTR_ERR(ent); | |
2208 | ||
8eb57294 | 2209 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2210 | } |
2211 | ||
6a9c308d DV |
2212 | static int i915_debugfs_create(struct dentry *root, |
2213 | struct drm_minor *minor, | |
2214 | const char *name, | |
2215 | const struct file_operations *fops) | |
07b7ddd9 JB |
2216 | { |
2217 | struct drm_device *dev = minor->dev; | |
2218 | struct dentry *ent; | |
2219 | ||
6a9c308d | 2220 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2221 | S_IRUGO | S_IWUSR, |
2222 | root, dev, | |
6a9c308d | 2223 | fops); |
07b7ddd9 JB |
2224 | if (IS_ERR(ent)) |
2225 | return PTR_ERR(ent); | |
2226 | ||
6a9c308d | 2227 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2228 | } |
2229 | ||
27c202ad | 2230 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2231 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2232 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2233 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2234 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2235 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2236 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 2237 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 2238 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2239 | {"i915_gem_request", i915_gem_request_info, 0}, |
2240 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2241 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2242 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2243 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2244 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2245 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 2246 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
2247 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2248 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2249 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2250 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2251 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2252 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2253 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2254 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2255 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 2256 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 2257 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2258 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2259 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2260 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2261 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2262 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2263 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2264 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 2265 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 2266 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
ec013e7f | 2267 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 2268 | {"i915_pc8_status", i915_pc8_status, 0}, |
2017263e | 2269 | }; |
27c202ad | 2270 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2271 | |
2b4bd0e0 | 2272 | static struct i915_debugfs_files { |
34b9674c DV |
2273 | const char *name; |
2274 | const struct file_operations *fops; | |
2275 | } i915_debugfs_files[] = { | |
2276 | {"i915_wedged", &i915_wedged_fops}, | |
2277 | {"i915_max_freq", &i915_max_freq_fops}, | |
2278 | {"i915_min_freq", &i915_min_freq_fops}, | |
2279 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
2280 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
2281 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, | |
2282 | {"i915_error_state", &i915_error_state_fops}, | |
2283 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
2284 | }; | |
2285 | ||
27c202ad | 2286 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2287 | { |
34b9674c | 2288 | int ret, i; |
f3cd474b | 2289 | |
6d794d42 | 2290 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2291 | if (ret) |
2292 | return ret; | |
6a9c308d | 2293 | |
34b9674c DV |
2294 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2295 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2296 | i915_debugfs_files[i].name, | |
2297 | i915_debugfs_files[i].fops); | |
2298 | if (ret) | |
2299 | return ret; | |
2300 | } | |
40633219 | 2301 | |
27c202ad BG |
2302 | return drm_debugfs_create_files(i915_debugfs_list, |
2303 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2304 | minor->debugfs_root, minor); |
2305 | } | |
2306 | ||
27c202ad | 2307 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2308 | { |
34b9674c DV |
2309 | int i; |
2310 | ||
27c202ad BG |
2311 | drm_debugfs_remove_files(i915_debugfs_list, |
2312 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2313 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2314 | 1, minor); | |
34b9674c DV |
2315 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2316 | struct drm_info_list *info_list = | |
2317 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
2318 | ||
2319 | drm_debugfs_remove_files(info_list, 1, minor); | |
2320 | } | |
2017263e BG |
2321 | } |
2322 | ||
2323 | #endif /* CONFIG_DEBUG_FS */ |