Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
2017263e BG |
43 | #if defined(CONFIG_DEBUG_FS) |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 | 47 | INACTIVE_LIST, |
d21d5975 | 48 | PINNED_LIST, |
f13d3f73 | 49 | }; |
2017263e | 50 | |
70d39fe4 CW |
51 | static const char *yesno(int v) |
52 | { | |
53 | return v ? "yes" : "no"; | |
54 | } | |
55 | ||
497666d8 DL |
56 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
57 | * allocated we need to hook into the minor for release. */ | |
58 | static int | |
59 | drm_add_fake_info_node(struct drm_minor *minor, | |
60 | struct dentry *ent, | |
61 | const void *key) | |
62 | { | |
63 | struct drm_info_node *node; | |
64 | ||
65 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
66 | if (node == NULL) { | |
67 | debugfs_remove(ent); | |
68 | return -ENOMEM; | |
69 | } | |
70 | ||
71 | node->minor = minor; | |
72 | node->dent = ent; | |
73 | node->info_ent = (void *) key; | |
74 | ||
75 | mutex_lock(&minor->debugfs_lock); | |
76 | list_add(&node->list, &minor->debugfs_list); | |
77 | mutex_unlock(&minor->debugfs_lock); | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
70d39fe4 CW |
82 | static int i915_capabilities(struct seq_file *m, void *data) |
83 | { | |
84 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
85 | struct drm_device *dev = node->minor->dev; | |
86 | const struct intel_device_info *info = INTEL_INFO(dev); | |
87 | ||
88 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 89 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
90 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
91 | #define SEP_SEMICOLON ; | |
92 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
93 | #undef PRINT_FLAG | |
94 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
95 | |
96 | return 0; | |
97 | } | |
2017263e | 98 | |
05394f39 | 99 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 100 | { |
05394f39 | 101 | if (obj->user_pin_count > 0) |
a6172a80 | 102 | return "P"; |
05394f39 | 103 | else if (obj->pin_count > 0) |
a6172a80 CW |
104 | return "p"; |
105 | else | |
106 | return " "; | |
107 | } | |
108 | ||
05394f39 | 109 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 110 | { |
0206e353 AJ |
111 | switch (obj->tiling_mode) { |
112 | default: | |
113 | case I915_TILING_NONE: return " "; | |
114 | case I915_TILING_X: return "X"; | |
115 | case I915_TILING_Y: return "Y"; | |
116 | } | |
a6172a80 CW |
117 | } |
118 | ||
1d693bcc BW |
119 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
120 | { | |
121 | return obj->has_global_gtt_mapping ? "g" : " "; | |
122 | } | |
123 | ||
37811fcc CW |
124 | static void |
125 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
126 | { | |
1d693bcc | 127 | struct i915_vma *vma; |
fb1ae911 | 128 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
129 | &obj->base, |
130 | get_pin_flag(obj), | |
131 | get_tiling_flag(obj), | |
1d693bcc | 132 | get_global_flag(obj), |
a05a5862 | 133 | obj->base.size / 1024, |
37811fcc CW |
134 | obj->base.read_domains, |
135 | obj->base.write_domain, | |
0201f1ec CW |
136 | obj->last_read_seqno, |
137 | obj->last_write_seqno, | |
caea7476 | 138 | obj->last_fenced_seqno, |
84734a04 | 139 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
140 | obj->dirty ? " dirty" : "", |
141 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
142 | if (obj->base.name) | |
143 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
144 | if (obj->pin_count) |
145 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
cc98b413 CW |
146 | if (obj->pin_display) |
147 | seq_printf(m, " (display)"); | |
37811fcc CW |
148 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
149 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
150 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
151 | if (!i915_is_ggtt(vma->vm)) | |
152 | seq_puts(m, " (pp"); | |
153 | else | |
154 | seq_puts(m, " (g"); | |
155 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
156 | vma->node.start, vma->node.size); | |
157 | } | |
c1ad11fc CW |
158 | if (obj->stolen) |
159 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
160 | if (obj->pin_mappable || obj->fault_mappable) { |
161 | char s[3], *t = s; | |
162 | if (obj->pin_mappable) | |
163 | *t++ = 'p'; | |
164 | if (obj->fault_mappable) | |
165 | *t++ = 'f'; | |
166 | *t = '\0'; | |
167 | seq_printf(m, " (%s mappable)", s); | |
168 | } | |
69dc4987 CW |
169 | if (obj->ring != NULL) |
170 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
171 | } |
172 | ||
3ccfd19d BW |
173 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
174 | { | |
175 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); | |
176 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); | |
177 | seq_putc(m, ' '); | |
178 | } | |
179 | ||
433e12f7 | 180 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
181 | { |
182 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
183 | uintptr_t list = (uintptr_t) node->info_ent->data; |
184 | struct list_head *head; | |
2017263e | 185 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
186 | struct drm_i915_private *dev_priv = dev->dev_private; |
187 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 188 | struct i915_vma *vma; |
8f2480fb CW |
189 | size_t total_obj_size, total_gtt_size; |
190 | int count, ret; | |
de227ef0 CW |
191 | |
192 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
193 | if (ret) | |
194 | return ret; | |
2017263e | 195 | |
ca191b13 | 196 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
197 | switch (list) { |
198 | case ACTIVE_LIST: | |
267f0c90 | 199 | seq_puts(m, "Active:\n"); |
5cef07e1 | 200 | head = &vm->active_list; |
433e12f7 BG |
201 | break; |
202 | case INACTIVE_LIST: | |
267f0c90 | 203 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 204 | head = &vm->inactive_list; |
433e12f7 | 205 | break; |
433e12f7 | 206 | default: |
de227ef0 CW |
207 | mutex_unlock(&dev->struct_mutex); |
208 | return -EINVAL; | |
2017263e | 209 | } |
2017263e | 210 | |
8f2480fb | 211 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
212 | list_for_each_entry(vma, head, mm_list) { |
213 | seq_printf(m, " "); | |
214 | describe_obj(m, vma->obj); | |
215 | seq_printf(m, "\n"); | |
216 | total_obj_size += vma->obj->base.size; | |
217 | total_gtt_size += vma->node.size; | |
8f2480fb | 218 | count++; |
2017263e | 219 | } |
de227ef0 | 220 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 221 | |
8f2480fb CW |
222 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
223 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
224 | return 0; |
225 | } | |
226 | ||
6d2b8885 CW |
227 | static int obj_rank_by_stolen(void *priv, |
228 | struct list_head *A, struct list_head *B) | |
229 | { | |
230 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 231 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 232 | struct drm_i915_gem_object *b = |
b25cb2f8 | 233 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
234 | |
235 | return a->stolen->start - b->stolen->start; | |
236 | } | |
237 | ||
238 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
239 | { | |
240 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
241 | struct drm_device *dev = node->minor->dev; | |
242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
243 | struct drm_i915_gem_object *obj; | |
244 | size_t total_obj_size, total_gtt_size; | |
245 | LIST_HEAD(stolen); | |
246 | int count, ret; | |
247 | ||
248 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
249 | if (ret) | |
250 | return ret; | |
251 | ||
252 | total_obj_size = total_gtt_size = count = 0; | |
253 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
254 | if (obj->stolen == NULL) | |
255 | continue; | |
256 | ||
b25cb2f8 | 257 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
258 | |
259 | total_obj_size += obj->base.size; | |
260 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
261 | count++; | |
262 | } | |
263 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
264 | if (obj->stolen == NULL) | |
265 | continue; | |
266 | ||
b25cb2f8 | 267 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
268 | |
269 | total_obj_size += obj->base.size; | |
270 | count++; | |
271 | } | |
272 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
273 | seq_puts(m, "Stolen:\n"); | |
274 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 275 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
276 | seq_puts(m, " "); |
277 | describe_obj(m, obj); | |
278 | seq_putc(m, '\n'); | |
b25cb2f8 | 279 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
280 | } |
281 | mutex_unlock(&dev->struct_mutex); | |
282 | ||
283 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
284 | count, total_obj_size, total_gtt_size); | |
285 | return 0; | |
286 | } | |
287 | ||
6299f992 CW |
288 | #define count_objects(list, member) do { \ |
289 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 290 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
291 | ++count; \ |
292 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 293 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
294 | ++mappable_count; \ |
295 | } \ | |
296 | } \ | |
0206e353 | 297 | } while (0) |
6299f992 | 298 | |
2db8e9d6 CW |
299 | struct file_stats { |
300 | int count; | |
301 | size_t total, active, inactive, unbound; | |
302 | }; | |
303 | ||
304 | static int per_file_stats(int id, void *ptr, void *data) | |
305 | { | |
306 | struct drm_i915_gem_object *obj = ptr; | |
307 | struct file_stats *stats = data; | |
308 | ||
309 | stats->count++; | |
310 | stats->total += obj->base.size; | |
311 | ||
f343c5f6 | 312 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
313 | if (!list_empty(&obj->ring_list)) |
314 | stats->active += obj->base.size; | |
315 | else | |
316 | stats->inactive += obj->base.size; | |
317 | } else { | |
318 | if (!list_empty(&obj->global_list)) | |
319 | stats->unbound += obj->base.size; | |
320 | } | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
ca191b13 BW |
325 | #define count_vmas(list, member) do { \ |
326 | list_for_each_entry(vma, list, member) { \ | |
327 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
328 | ++count; \ | |
329 | if (vma->obj->map_and_fenceable) { \ | |
330 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
331 | ++mappable_count; \ | |
332 | } \ | |
333 | } \ | |
334 | } while (0) | |
335 | ||
336 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
337 | { |
338 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
339 | struct drm_device *dev = node->minor->dev; | |
340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
341 | u32 count, mappable_count, purgeable_count; |
342 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 343 | struct drm_i915_gem_object *obj; |
5cef07e1 | 344 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 345 | struct drm_file *file; |
ca191b13 | 346 | struct i915_vma *vma; |
73aa808f CW |
347 | int ret; |
348 | ||
349 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
350 | if (ret) | |
351 | return ret; | |
352 | ||
6299f992 CW |
353 | seq_printf(m, "%u objects, %zu bytes\n", |
354 | dev_priv->mm.object_count, | |
355 | dev_priv->mm.object_memory); | |
356 | ||
357 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 358 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
359 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
360 | count, mappable_count, size, mappable_size); | |
361 | ||
362 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 363 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
364 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
365 | count, mappable_count, size, mappable_size); | |
366 | ||
6299f992 | 367 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 368 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
369 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
370 | count, mappable_count, size, mappable_size); | |
371 | ||
b7abb714 | 372 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 373 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 374 | size += obj->base.size, ++count; |
b7abb714 CW |
375 | if (obj->madv == I915_MADV_DONTNEED) |
376 | purgeable_size += obj->base.size, ++purgeable_count; | |
377 | } | |
6c085a72 CW |
378 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
379 | ||
6299f992 | 380 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 381 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 382 | if (obj->fault_mappable) { |
f343c5f6 | 383 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
384 | ++count; |
385 | } | |
386 | if (obj->pin_mappable) { | |
f343c5f6 | 387 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
388 | ++mappable_count; |
389 | } | |
b7abb714 CW |
390 | if (obj->madv == I915_MADV_DONTNEED) { |
391 | purgeable_size += obj->base.size; | |
392 | ++purgeable_count; | |
393 | } | |
6299f992 | 394 | } |
b7abb714 CW |
395 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
396 | purgeable_count, purgeable_size); | |
6299f992 CW |
397 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
398 | mappable_count, mappable_size); | |
399 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
400 | count, size); | |
401 | ||
93d18799 | 402 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
403 | dev_priv->gtt.base.total, |
404 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 405 | |
267f0c90 | 406 | seq_putc(m, '\n'); |
2db8e9d6 CW |
407 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
408 | struct file_stats stats; | |
409 | ||
410 | memset(&stats, 0, sizeof(stats)); | |
411 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
412 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
413 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
414 | stats.count, | |
415 | stats.total, | |
416 | stats.active, | |
417 | stats.inactive, | |
418 | stats.unbound); | |
419 | } | |
420 | ||
73aa808f CW |
421 | mutex_unlock(&dev->struct_mutex); |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
aee56cff | 426 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
427 | { |
428 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
429 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 430 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
431 | struct drm_i915_private *dev_priv = dev->dev_private; |
432 | struct drm_i915_gem_object *obj; | |
433 | size_t total_obj_size, total_gtt_size; | |
434 | int count, ret; | |
435 | ||
436 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
437 | if (ret) | |
438 | return ret; | |
439 | ||
440 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 441 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
442 | if (list == PINNED_LIST && obj->pin_count == 0) |
443 | continue; | |
444 | ||
267f0c90 | 445 | seq_puts(m, " "); |
08c18323 | 446 | describe_obj(m, obj); |
267f0c90 | 447 | seq_putc(m, '\n'); |
08c18323 | 448 | total_obj_size += obj->base.size; |
f343c5f6 | 449 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
450 | count++; |
451 | } | |
452 | ||
453 | mutex_unlock(&dev->struct_mutex); | |
454 | ||
455 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
456 | count, total_obj_size, total_gtt_size); | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
4e5359cd SF |
461 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
462 | { | |
463 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
464 | struct drm_device *dev = node->minor->dev; | |
465 | unsigned long flags; | |
466 | struct intel_crtc *crtc; | |
467 | ||
468 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
469 | const char pipe = pipe_name(crtc->pipe); |
470 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
471 | struct intel_unpin_work *work; |
472 | ||
473 | spin_lock_irqsave(&dev->event_lock, flags); | |
474 | work = crtc->unpin_work; | |
475 | if (work == NULL) { | |
9db4a9c7 | 476 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
477 | pipe, plane); |
478 | } else { | |
e7d841ca | 479 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 480 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
481 | pipe, plane); |
482 | } else { | |
9db4a9c7 | 483 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
484 | pipe, plane); |
485 | } | |
486 | if (work->enable_stall_check) | |
267f0c90 | 487 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 488 | else |
267f0c90 | 489 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 490 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
491 | |
492 | if (work->old_fb_obj) { | |
05394f39 CW |
493 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
494 | if (obj) | |
f343c5f6 BW |
495 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
496 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
497 | } |
498 | if (work->pending_flip_obj) { | |
05394f39 CW |
499 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
500 | if (obj) | |
f343c5f6 BW |
501 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
502 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
503 | } |
504 | } | |
505 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
506 | } | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
2017263e BG |
511 | static int i915_gem_request_info(struct seq_file *m, void *data) |
512 | { | |
513 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
514 | struct drm_device *dev = node->minor->dev; | |
515 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 516 | struct intel_ring_buffer *ring; |
2017263e | 517 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 518 | int ret, count, i; |
de227ef0 CW |
519 | |
520 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
521 | if (ret) | |
522 | return ret; | |
2017263e | 523 | |
c2c347a9 | 524 | count = 0; |
a2c7f6fd CW |
525 | for_each_ring(ring, dev_priv, i) { |
526 | if (list_empty(&ring->request_list)) | |
527 | continue; | |
528 | ||
529 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 530 | list_for_each_entry(gem_request, |
a2c7f6fd | 531 | &ring->request_list, |
c2c347a9 CW |
532 | list) { |
533 | seq_printf(m, " %d @ %d\n", | |
534 | gem_request->seqno, | |
535 | (int) (jiffies - gem_request->emitted_jiffies)); | |
536 | } | |
537 | count++; | |
2017263e | 538 | } |
de227ef0 CW |
539 | mutex_unlock(&dev->struct_mutex); |
540 | ||
c2c347a9 | 541 | if (count == 0) |
267f0c90 | 542 | seq_puts(m, "No requests\n"); |
c2c347a9 | 543 | |
2017263e BG |
544 | return 0; |
545 | } | |
546 | ||
b2223497 CW |
547 | static void i915_ring_seqno_info(struct seq_file *m, |
548 | struct intel_ring_buffer *ring) | |
549 | { | |
550 | if (ring->get_seqno) { | |
43a7b924 | 551 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 552 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
553 | } |
554 | } | |
555 | ||
2017263e BG |
556 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
557 | { | |
558 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
559 | struct drm_device *dev = node->minor->dev; | |
560 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 561 | struct intel_ring_buffer *ring; |
1ec14ad3 | 562 | int ret, i; |
de227ef0 CW |
563 | |
564 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
565 | if (ret) | |
566 | return ret; | |
2017263e | 567 | |
a2c7f6fd CW |
568 | for_each_ring(ring, dev_priv, i) |
569 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
570 | |
571 | mutex_unlock(&dev->struct_mutex); | |
572 | ||
2017263e BG |
573 | return 0; |
574 | } | |
575 | ||
576 | ||
577 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
578 | { | |
579 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
580 | struct drm_device *dev = node->minor->dev; | |
581 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 582 | struct intel_ring_buffer *ring; |
9db4a9c7 | 583 | int ret, i, pipe; |
de227ef0 CW |
584 | |
585 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
586 | if (ret) | |
587 | return ret; | |
2017263e | 588 | |
a123f157 BW |
589 | if (INTEL_INFO(dev)->gen >= 8) { |
590 | int i; | |
591 | seq_printf(m, "Master Interrupt Control:\t%08x\n", | |
592 | I915_READ(GEN8_MASTER_IRQ)); | |
593 | ||
594 | for (i = 0; i < 4; i++) { | |
595 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
596 | i, I915_READ(GEN8_GT_IMR(i))); | |
597 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
598 | i, I915_READ(GEN8_GT_IIR(i))); | |
599 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
600 | i, I915_READ(GEN8_GT_IER(i))); | |
601 | } | |
602 | ||
603 | for_each_pipe(i) { | |
604 | seq_printf(m, "Pipe %c IMR:\t%08x\n", | |
605 | pipe_name(i), | |
606 | I915_READ(GEN8_DE_PIPE_IMR(i))); | |
607 | seq_printf(m, "Pipe %c IIR:\t%08x\n", | |
608 | pipe_name(i), | |
609 | I915_READ(GEN8_DE_PIPE_IIR(i))); | |
610 | seq_printf(m, "Pipe %c IER:\t%08x\n", | |
611 | pipe_name(i), | |
612 | I915_READ(GEN8_DE_PIPE_IER(i))); | |
613 | } | |
614 | ||
615 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
616 | I915_READ(GEN8_DE_PORT_IMR)); | |
617 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
618 | I915_READ(GEN8_DE_PORT_IIR)); | |
619 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
620 | I915_READ(GEN8_DE_PORT_IER)); | |
621 | ||
622 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
623 | I915_READ(GEN8_DE_MISC_IMR)); | |
624 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
625 | I915_READ(GEN8_DE_MISC_IIR)); | |
626 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
627 | I915_READ(GEN8_DE_MISC_IER)); | |
628 | ||
629 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
630 | I915_READ(GEN8_PCU_IMR)); | |
631 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
632 | I915_READ(GEN8_PCU_IIR)); | |
633 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
634 | I915_READ(GEN8_PCU_IER)); | |
635 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
636 | seq_printf(m, "Display IER:\t%08x\n", |
637 | I915_READ(VLV_IER)); | |
638 | seq_printf(m, "Display IIR:\t%08x\n", | |
639 | I915_READ(VLV_IIR)); | |
640 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
641 | I915_READ(VLV_IIR_RW)); | |
642 | seq_printf(m, "Display IMR:\t%08x\n", | |
643 | I915_READ(VLV_IMR)); | |
644 | for_each_pipe(pipe) | |
645 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
646 | pipe_name(pipe), | |
647 | I915_READ(PIPESTAT(pipe))); | |
648 | ||
649 | seq_printf(m, "Master IER:\t%08x\n", | |
650 | I915_READ(VLV_MASTER_IER)); | |
651 | ||
652 | seq_printf(m, "Render IER:\t%08x\n", | |
653 | I915_READ(GTIER)); | |
654 | seq_printf(m, "Render IIR:\t%08x\n", | |
655 | I915_READ(GTIIR)); | |
656 | seq_printf(m, "Render IMR:\t%08x\n", | |
657 | I915_READ(GTIMR)); | |
658 | ||
659 | seq_printf(m, "PM IER:\t\t%08x\n", | |
660 | I915_READ(GEN6_PMIER)); | |
661 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
662 | I915_READ(GEN6_PMIIR)); | |
663 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
664 | I915_READ(GEN6_PMIMR)); | |
665 | ||
666 | seq_printf(m, "Port hotplug:\t%08x\n", | |
667 | I915_READ(PORT_HOTPLUG_EN)); | |
668 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
669 | I915_READ(VLV_DPFLIPSTAT)); | |
670 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
671 | I915_READ(DPINVGTT)); | |
672 | ||
673 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
674 | seq_printf(m, "Interrupt enable: %08x\n", |
675 | I915_READ(IER)); | |
676 | seq_printf(m, "Interrupt identity: %08x\n", | |
677 | I915_READ(IIR)); | |
678 | seq_printf(m, "Interrupt mask: %08x\n", | |
679 | I915_READ(IMR)); | |
9db4a9c7 JB |
680 | for_each_pipe(pipe) |
681 | seq_printf(m, "Pipe %c stat: %08x\n", | |
682 | pipe_name(pipe), | |
683 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
684 | } else { |
685 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
686 | I915_READ(DEIER)); | |
687 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
688 | I915_READ(DEIIR)); | |
689 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
690 | I915_READ(DEIMR)); | |
691 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
692 | I915_READ(SDEIER)); | |
693 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
694 | I915_READ(SDEIIR)); | |
695 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
696 | I915_READ(SDEIMR)); | |
697 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
698 | I915_READ(GTIER)); | |
699 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
700 | I915_READ(GTIIR)); | |
701 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
702 | I915_READ(GTIMR)); | |
703 | } | |
2017263e BG |
704 | seq_printf(m, "Interrupts received: %d\n", |
705 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 706 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 707 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
708 | seq_printf(m, |
709 | "Graphics Interrupt mask (%s): %08x\n", | |
710 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 711 | } |
a2c7f6fd | 712 | i915_ring_seqno_info(m, ring); |
9862e600 | 713 | } |
de227ef0 CW |
714 | mutex_unlock(&dev->struct_mutex); |
715 | ||
2017263e BG |
716 | return 0; |
717 | } | |
718 | ||
a6172a80 CW |
719 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
720 | { | |
721 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
722 | struct drm_device *dev = node->minor->dev; | |
723 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
724 | int i, ret; |
725 | ||
726 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
727 | if (ret) | |
728 | return ret; | |
a6172a80 CW |
729 | |
730 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
731 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
732 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 733 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 734 | |
6c085a72 CW |
735 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
736 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 737 | if (obj == NULL) |
267f0c90 | 738 | seq_puts(m, "unused"); |
c2c347a9 | 739 | else |
05394f39 | 740 | describe_obj(m, obj); |
267f0c90 | 741 | seq_putc(m, '\n'); |
a6172a80 CW |
742 | } |
743 | ||
05394f39 | 744 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
745 | return 0; |
746 | } | |
747 | ||
2017263e BG |
748 | static int i915_hws_info(struct seq_file *m, void *data) |
749 | { | |
750 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
751 | struct drm_device *dev = node->minor->dev; | |
752 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 753 | struct intel_ring_buffer *ring; |
1a240d4d | 754 | const u32 *hws; |
4066c0ae CW |
755 | int i; |
756 | ||
1ec14ad3 | 757 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 758 | hws = ring->status_page.page_addr; |
2017263e BG |
759 | if (hws == NULL) |
760 | return 0; | |
761 | ||
762 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
763 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
764 | i * 4, | |
765 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
766 | } | |
767 | return 0; | |
768 | } | |
769 | ||
d5442303 DV |
770 | static ssize_t |
771 | i915_error_state_write(struct file *filp, | |
772 | const char __user *ubuf, | |
773 | size_t cnt, | |
774 | loff_t *ppos) | |
775 | { | |
edc3d884 | 776 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 777 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 778 | int ret; |
d5442303 DV |
779 | |
780 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
781 | ||
22bcfc6a DV |
782 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
783 | if (ret) | |
784 | return ret; | |
785 | ||
d5442303 DV |
786 | i915_destroy_error_state(dev); |
787 | mutex_unlock(&dev->struct_mutex); | |
788 | ||
789 | return cnt; | |
790 | } | |
791 | ||
792 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
793 | { | |
794 | struct drm_device *dev = inode->i_private; | |
d5442303 | 795 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
796 | |
797 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
798 | if (!error_priv) | |
799 | return -ENOMEM; | |
800 | ||
801 | error_priv->dev = dev; | |
802 | ||
95d5bfb3 | 803 | i915_error_state_get(dev, error_priv); |
d5442303 | 804 | |
edc3d884 MK |
805 | file->private_data = error_priv; |
806 | ||
807 | return 0; | |
d5442303 DV |
808 | } |
809 | ||
810 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
811 | { | |
edc3d884 | 812 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 813 | |
95d5bfb3 | 814 | i915_error_state_put(error_priv); |
d5442303 DV |
815 | kfree(error_priv); |
816 | ||
edc3d884 MK |
817 | return 0; |
818 | } | |
819 | ||
4dc955f7 MK |
820 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
821 | size_t count, loff_t *pos) | |
822 | { | |
823 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
824 | struct drm_i915_error_state_buf error_str; | |
825 | loff_t tmp_pos = 0; | |
826 | ssize_t ret_count = 0; | |
827 | int ret; | |
828 | ||
829 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
830 | if (ret) | |
831 | return ret; | |
edc3d884 | 832 | |
fc16b48b | 833 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
834 | if (ret) |
835 | goto out; | |
836 | ||
edc3d884 MK |
837 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
838 | error_str.buf, | |
839 | error_str.bytes); | |
840 | ||
841 | if (ret_count < 0) | |
842 | ret = ret_count; | |
843 | else | |
844 | *pos = error_str.start + ret_count; | |
845 | out: | |
4dc955f7 | 846 | i915_error_state_buf_release(&error_str); |
edc3d884 | 847 | return ret ?: ret_count; |
d5442303 DV |
848 | } |
849 | ||
850 | static const struct file_operations i915_error_state_fops = { | |
851 | .owner = THIS_MODULE, | |
852 | .open = i915_error_state_open, | |
edc3d884 | 853 | .read = i915_error_state_read, |
d5442303 DV |
854 | .write = i915_error_state_write, |
855 | .llseek = default_llseek, | |
856 | .release = i915_error_state_release, | |
857 | }; | |
858 | ||
647416f9 KC |
859 | static int |
860 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 861 | { |
647416f9 | 862 | struct drm_device *dev = data; |
40633219 | 863 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
864 | int ret; |
865 | ||
866 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
867 | if (ret) | |
868 | return ret; | |
869 | ||
647416f9 | 870 | *val = dev_priv->next_seqno; |
40633219 MK |
871 | mutex_unlock(&dev->struct_mutex); |
872 | ||
647416f9 | 873 | return 0; |
40633219 MK |
874 | } |
875 | ||
647416f9 KC |
876 | static int |
877 | i915_next_seqno_set(void *data, u64 val) | |
878 | { | |
879 | struct drm_device *dev = data; | |
40633219 MK |
880 | int ret; |
881 | ||
40633219 MK |
882 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
883 | if (ret) | |
884 | return ret; | |
885 | ||
e94fbaa8 | 886 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
887 | mutex_unlock(&dev->struct_mutex); |
888 | ||
647416f9 | 889 | return ret; |
40633219 MK |
890 | } |
891 | ||
647416f9 KC |
892 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
893 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 894 | "0x%llx\n"); |
40633219 | 895 | |
f97108d1 JB |
896 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
897 | { | |
898 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
899 | struct drm_device *dev = node->minor->dev; | |
900 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
901 | u16 crstanddelay; |
902 | int ret; | |
903 | ||
904 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
905 | if (ret) | |
906 | return ret; | |
907 | ||
908 | crstanddelay = I915_READ16(CRSTANDVID); | |
909 | ||
910 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
911 | |
912 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
917 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
918 | { | |
919 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
920 | struct drm_device *dev = node->minor->dev; | |
921 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 922 | int ret; |
3b8d8d91 | 923 | |
5c9669ce TR |
924 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
925 | ||
3b8d8d91 JB |
926 | if (IS_GEN5(dev)) { |
927 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
928 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
929 | ||
930 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
931 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
932 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
933 | MEMSTAT_VID_SHIFT); | |
934 | seq_printf(m, "Current P-state: %d\n", | |
935 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 936 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
937 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
938 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
939 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
8e8c06cd | 940 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
941 | u32 rpupei, rpcurup, rpprevup; |
942 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
943 | int max_freq; |
944 | ||
945 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
946 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
947 | if (ret) | |
948 | return ret; | |
949 | ||
fcca7926 | 950 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 951 | |
8e8c06cd CW |
952 | reqf = I915_READ(GEN6_RPNSWREQ); |
953 | reqf &= ~GEN6_TURBO_DISABLE; | |
954 | if (IS_HASWELL(dev)) | |
955 | reqf >>= 24; | |
956 | else | |
957 | reqf >>= 25; | |
958 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
959 | ||
ccab5c82 JB |
960 | rpstat = I915_READ(GEN6_RPSTAT1); |
961 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
962 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
963 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
964 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
965 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
966 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
967 | if (IS_HASWELL(dev)) |
968 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
969 | else | |
970 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
971 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 972 | |
d1ebd816 BW |
973 | gen6_gt_force_wake_put(dev_priv); |
974 | mutex_unlock(&dev->struct_mutex); | |
975 | ||
3b8d8d91 | 976 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 977 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
978 | seq_printf(m, "Render p-state ratio: %d\n", |
979 | (gt_perf_status & 0xff00) >> 8); | |
980 | seq_printf(m, "Render p-state VID: %d\n", | |
981 | gt_perf_status & 0xff); | |
982 | seq_printf(m, "Render p-state limit: %d\n", | |
983 | rp_state_limits & 0xff); | |
8e8c06cd | 984 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 985 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
986 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
987 | GEN6_CURICONT_MASK); | |
988 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
989 | GEN6_CURBSYTAVG_MASK); | |
990 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
991 | GEN6_CURBSYTAVG_MASK); | |
992 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
993 | GEN6_CURIAVG_MASK); | |
994 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
995 | GEN6_CURBSYTAVG_MASK); | |
996 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
997 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
998 | |
999 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
1000 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 1001 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1002 | |
1003 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
1004 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 1005 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1006 | |
1007 | max_freq = rp_state_cap & 0xff; | |
1008 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 1009 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
1010 | |
1011 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
1012 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
1013 | } else if (IS_VALLEYVIEW(dev)) { |
1014 | u32 freq_sts, val; | |
1015 | ||
259bd5d4 | 1016 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1017 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1018 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1019 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1020 | ||
64936258 | 1021 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
1022 | seq_printf(m, "max GPU freq: %d MHz\n", |
1023 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
1024 | ||
64936258 | 1025 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
1026 | seq_printf(m, "min GPU freq: %d MHz\n", |
1027 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
1028 | ||
1029 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1030 | vlv_gpu_freq(dev_priv->mem_freq, | |
1031 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 1032 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1033 | } else { |
267f0c90 | 1034 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1035 | } |
f97108d1 JB |
1036 | |
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
1041 | { | |
1042 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1043 | struct drm_device *dev = node->minor->dev; | |
1044 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1045 | u32 delayfreq; | |
616fdb5a BW |
1046 | int ret, i; |
1047 | ||
1048 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1049 | if (ret) | |
1050 | return ret; | |
f97108d1 JB |
1051 | |
1052 | for (i = 0; i < 16; i++) { | |
1053 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
1054 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
1055 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
1056 | } |
1057 | ||
616fdb5a BW |
1058 | mutex_unlock(&dev->struct_mutex); |
1059 | ||
f97108d1 JB |
1060 | return 0; |
1061 | } | |
1062 | ||
1063 | static inline int MAP_TO_MV(int map) | |
1064 | { | |
1065 | return 1250 - (map * 25); | |
1066 | } | |
1067 | ||
1068 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
1069 | { | |
1070 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1071 | struct drm_device *dev = node->minor->dev; | |
1072 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1073 | u32 inttoext; | |
616fdb5a BW |
1074 | int ret, i; |
1075 | ||
1076 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1077 | if (ret) | |
1078 | return ret; | |
f97108d1 JB |
1079 | |
1080 | for (i = 1; i <= 32; i++) { | |
1081 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1082 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1083 | } | |
1084 | ||
616fdb5a BW |
1085 | mutex_unlock(&dev->struct_mutex); |
1086 | ||
f97108d1 JB |
1087 | return 0; |
1088 | } | |
1089 | ||
4d85529d | 1090 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1091 | { |
1092 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1093 | struct drm_device *dev = node->minor->dev; | |
1094 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1095 | u32 rgvmodectl, rstdbyctl; |
1096 | u16 crstandvid; | |
1097 | int ret; | |
1098 | ||
1099 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1100 | if (ret) | |
1101 | return ret; | |
1102 | ||
1103 | rgvmodectl = I915_READ(MEMMODECTL); | |
1104 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1105 | crstandvid = I915_READ16(CRSTANDVID); | |
1106 | ||
1107 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1108 | |
1109 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1110 | "yes" : "no"); | |
1111 | seq_printf(m, "Boost freq: %d\n", | |
1112 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1113 | MEMMODE_BOOST_FREQ_SHIFT); | |
1114 | seq_printf(m, "HW control enabled: %s\n", | |
1115 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1116 | seq_printf(m, "SW control enabled: %s\n", | |
1117 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1118 | seq_printf(m, "Gated voltage change: %s\n", | |
1119 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1120 | seq_printf(m, "Starting frequency: P%d\n", | |
1121 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1122 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1123 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1124 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1125 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1126 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1127 | seq_printf(m, "Render standby enabled: %s\n", | |
1128 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1129 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1130 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1131 | case RSX_STATUS_ON: | |
267f0c90 | 1132 | seq_puts(m, "on\n"); |
88271da3 JB |
1133 | break; |
1134 | case RSX_STATUS_RC1: | |
267f0c90 | 1135 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1136 | break; |
1137 | case RSX_STATUS_RC1E: | |
267f0c90 | 1138 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1139 | break; |
1140 | case RSX_STATUS_RS1: | |
267f0c90 | 1141 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1142 | break; |
1143 | case RSX_STATUS_RS2: | |
267f0c90 | 1144 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1145 | break; |
1146 | case RSX_STATUS_RS3: | |
267f0c90 | 1147 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1148 | break; |
1149 | default: | |
267f0c90 | 1150 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1151 | break; |
1152 | } | |
f97108d1 JB |
1153 | |
1154 | return 0; | |
1155 | } | |
1156 | ||
4d85529d BW |
1157 | static int gen6_drpc_info(struct seq_file *m) |
1158 | { | |
1159 | ||
1160 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1161 | struct drm_device *dev = node->minor->dev; | |
1162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1163 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1164 | unsigned forcewake_count; |
aee56cff | 1165 | int count = 0, ret; |
4d85529d BW |
1166 | |
1167 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1168 | if (ret) | |
1169 | return ret; | |
1170 | ||
907b28c5 CW |
1171 | spin_lock_irq(&dev_priv->uncore.lock); |
1172 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1173 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1174 | |
1175 | if (forcewake_count) { | |
267f0c90 DL |
1176 | seq_puts(m, "RC information inaccurate because somebody " |
1177 | "holds a forcewake reference \n"); | |
4d85529d BW |
1178 | } else { |
1179 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1180 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1181 | udelay(10); | |
1182 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1183 | } | |
1184 | ||
1185 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1186 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1187 | |
1188 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1189 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1190 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1191 | mutex_lock(&dev_priv->rps.hw_lock); |
1192 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1193 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1194 | |
1195 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1196 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1197 | seq_printf(m, "HW control enabled: %s\n", | |
1198 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1199 | seq_printf(m, "SW control enabled: %s\n", | |
1200 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1201 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1202 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1203 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1204 | seq_printf(m, "RC6 Enabled: %s\n", | |
1205 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1206 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1207 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1208 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1209 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1210 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1211 | switch (gt_core_status & GEN6_RCn_MASK) { |
1212 | case GEN6_RC0: | |
1213 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1214 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1215 | else |
267f0c90 | 1216 | seq_puts(m, "on\n"); |
4d85529d BW |
1217 | break; |
1218 | case GEN6_RC3: | |
267f0c90 | 1219 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1220 | break; |
1221 | case GEN6_RC6: | |
267f0c90 | 1222 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1223 | break; |
1224 | case GEN6_RC7: | |
267f0c90 | 1225 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1226 | break; |
1227 | default: | |
267f0c90 | 1228 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1229 | break; |
1230 | } | |
1231 | ||
1232 | seq_printf(m, "Core Power Down: %s\n", | |
1233 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1234 | |
1235 | /* Not exactly sure what this is */ | |
1236 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1237 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1238 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1239 | I915_READ(GEN6_GT_GFX_RC6)); | |
1240 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1241 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1242 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1243 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1244 | ||
ecd8faea BW |
1245 | seq_printf(m, "RC6 voltage: %dmV\n", |
1246 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1247 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1248 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1249 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1250 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1251 | return 0; |
1252 | } | |
1253 | ||
1254 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1255 | { | |
1256 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1257 | struct drm_device *dev = node->minor->dev; | |
1258 | ||
1259 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1260 | return gen6_drpc_info(m); | |
1261 | else | |
1262 | return ironlake_drpc_info(m); | |
1263 | } | |
1264 | ||
b5e50c3f JB |
1265 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1266 | { | |
1267 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1268 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1269 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1270 | |
ee5382ae | 1271 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1272 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1273 | return 0; |
1274 | } | |
1275 | ||
ee5382ae | 1276 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1277 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1278 | } else { |
267f0c90 | 1279 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1280 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1281 | case FBC_OK: |
1282 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1283 | break; | |
1284 | case FBC_UNSUPPORTED: | |
1285 | seq_puts(m, "unsupported by this chipset"); | |
1286 | break; | |
bed4a673 | 1287 | case FBC_NO_OUTPUT: |
267f0c90 | 1288 | seq_puts(m, "no outputs"); |
bed4a673 | 1289 | break; |
b5e50c3f | 1290 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1291 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1292 | break; |
1293 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1294 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1295 | break; |
1296 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1297 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1298 | break; |
1299 | case FBC_BAD_PLANE: | |
267f0c90 | 1300 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1301 | break; |
1302 | case FBC_NOT_TILED: | |
267f0c90 | 1303 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1304 | break; |
9c928d16 | 1305 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1306 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1307 | break; |
c1a9f047 | 1308 | case FBC_MODULE_PARAM: |
267f0c90 | 1309 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1310 | break; |
8a5729a3 | 1311 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1312 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1313 | break; |
b5e50c3f | 1314 | default: |
267f0c90 | 1315 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1316 | } |
267f0c90 | 1317 | seq_putc(m, '\n'); |
b5e50c3f JB |
1318 | } |
1319 | return 0; | |
1320 | } | |
1321 | ||
92d44621 PZ |
1322 | static int i915_ips_status(struct seq_file *m, void *unused) |
1323 | { | |
1324 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1325 | struct drm_device *dev = node->minor->dev; | |
1326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1327 | ||
f5adf94e | 1328 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1329 | seq_puts(m, "not supported\n"); |
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1334 | seq_puts(m, "enabled\n"); | |
1335 | else | |
1336 | seq_puts(m, "disabled\n"); | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
4a9bef37 JB |
1341 | static int i915_sr_status(struct seq_file *m, void *unused) |
1342 | { | |
1343 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1344 | struct drm_device *dev = node->minor->dev; | |
1345 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1346 | bool sr_enabled = false; | |
1347 | ||
1398261a | 1348 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1349 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1350 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1351 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1352 | else if (IS_I915GM(dev)) | |
1353 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1354 | else if (IS_PINEVIEW(dev)) | |
1355 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1356 | ||
5ba2aaaa CW |
1357 | seq_printf(m, "self-refresh: %s\n", |
1358 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1359 | |
1360 | return 0; | |
1361 | } | |
1362 | ||
7648fa99 JB |
1363 | static int i915_emon_status(struct seq_file *m, void *unused) |
1364 | { | |
1365 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1366 | struct drm_device *dev = node->minor->dev; | |
1367 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1368 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1369 | int ret; |
1370 | ||
582be6b4 CW |
1371 | if (!IS_GEN5(dev)) |
1372 | return -ENODEV; | |
1373 | ||
de227ef0 CW |
1374 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1375 | if (ret) | |
1376 | return ret; | |
7648fa99 JB |
1377 | |
1378 | temp = i915_mch_val(dev_priv); | |
1379 | chipset = i915_chipset_val(dev_priv); | |
1380 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1381 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1382 | |
1383 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1384 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1385 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1386 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1387 | ||
1388 | return 0; | |
1389 | } | |
1390 | ||
23b2f8bb JB |
1391 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1392 | { | |
1393 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1394 | struct drm_device *dev = node->minor->dev; | |
1395 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1396 | int ret; | |
1397 | int gpu_freq, ia_freq; | |
1398 | ||
1c70c0ce | 1399 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1400 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1401 | return 0; |
1402 | } | |
1403 | ||
5c9669ce TR |
1404 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1405 | ||
4fc688ce | 1406 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1407 | if (ret) |
1408 | return ret; | |
1409 | ||
267f0c90 | 1410 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1411 | |
c6a828d3 DV |
1412 | for (gpu_freq = dev_priv->rps.min_delay; |
1413 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1414 | gpu_freq++) { |
42c0526c BW |
1415 | ia_freq = gpu_freq; |
1416 | sandybridge_pcode_read(dev_priv, | |
1417 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1418 | &ia_freq); | |
3ebecd07 CW |
1419 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1420 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1421 | ((ia_freq >> 0) & 0xff) * 100, | |
1422 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1423 | } |
1424 | ||
4fc688ce | 1425 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1426 | |
1427 | return 0; | |
1428 | } | |
1429 | ||
7648fa99 JB |
1430 | static int i915_gfxec(struct seq_file *m, void *unused) |
1431 | { | |
1432 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1433 | struct drm_device *dev = node->minor->dev; | |
1434 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1435 | int ret; |
1436 | ||
1437 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1438 | if (ret) | |
1439 | return ret; | |
7648fa99 JB |
1440 | |
1441 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1442 | ||
616fdb5a BW |
1443 | mutex_unlock(&dev->struct_mutex); |
1444 | ||
7648fa99 JB |
1445 | return 0; |
1446 | } | |
1447 | ||
44834a67 CW |
1448 | static int i915_opregion(struct seq_file *m, void *unused) |
1449 | { | |
1450 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1451 | struct drm_device *dev = node->minor->dev; | |
1452 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1453 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1454 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1455 | int ret; |
1456 | ||
0d38f009 DV |
1457 | if (data == NULL) |
1458 | return -ENOMEM; | |
1459 | ||
44834a67 CW |
1460 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1461 | if (ret) | |
0d38f009 | 1462 | goto out; |
44834a67 | 1463 | |
0d38f009 DV |
1464 | if (opregion->header) { |
1465 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1466 | seq_write(m, data, OPREGION_SIZE); | |
1467 | } | |
44834a67 CW |
1468 | |
1469 | mutex_unlock(&dev->struct_mutex); | |
1470 | ||
0d38f009 DV |
1471 | out: |
1472 | kfree(data); | |
44834a67 CW |
1473 | return 0; |
1474 | } | |
1475 | ||
37811fcc CW |
1476 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1477 | { | |
1478 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1479 | struct drm_device *dev = node->minor->dev; | |
4520f53a | 1480 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1481 | struct intel_framebuffer *fb; |
37811fcc | 1482 | |
4520f53a DV |
1483 | #ifdef CONFIG_DRM_I915_FBDEV |
1484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1485 | int ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
37811fcc CW |
1486 | if (ret) |
1487 | return ret; | |
1488 | ||
1489 | ifbdev = dev_priv->fbdev; | |
1490 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1491 | ||
623f9783 | 1492 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1493 | fb->base.width, |
1494 | fb->base.height, | |
1495 | fb->base.depth, | |
623f9783 DV |
1496 | fb->base.bits_per_pixel, |
1497 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1498 | describe_obj(m, fb->obj); |
267f0c90 | 1499 | seq_putc(m, '\n'); |
4b096ac1 | 1500 | mutex_unlock(&dev->mode_config.mutex); |
4520f53a | 1501 | #endif |
37811fcc | 1502 | |
4b096ac1 | 1503 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc | 1504 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
131a56dc | 1505 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
37811fcc CW |
1506 | continue; |
1507 | ||
623f9783 | 1508 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1509 | fb->base.width, |
1510 | fb->base.height, | |
1511 | fb->base.depth, | |
623f9783 DV |
1512 | fb->base.bits_per_pixel, |
1513 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1514 | describe_obj(m, fb->obj); |
267f0c90 | 1515 | seq_putc(m, '\n'); |
37811fcc | 1516 | } |
4b096ac1 | 1517 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1518 | |
1519 | return 0; | |
1520 | } | |
1521 | ||
e76d3630 BW |
1522 | static int i915_context_status(struct seq_file *m, void *unused) |
1523 | { | |
1524 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1525 | struct drm_device *dev = node->minor->dev; | |
1526 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 | 1527 | struct intel_ring_buffer *ring; |
a33afea5 | 1528 | struct i915_hw_context *ctx; |
a168c293 | 1529 | int ret, i; |
e76d3630 BW |
1530 | |
1531 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1532 | if (ret) | |
1533 | return ret; | |
1534 | ||
3e373948 | 1535 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1536 | seq_puts(m, "power context "); |
3e373948 | 1537 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1538 | seq_putc(m, '\n'); |
dc501fbc | 1539 | } |
e76d3630 | 1540 | |
3e373948 | 1541 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1542 | seq_puts(m, "render context "); |
3e373948 | 1543 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1544 | seq_putc(m, '\n'); |
dc501fbc | 1545 | } |
e76d3630 | 1546 | |
a33afea5 BW |
1547 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
1548 | seq_puts(m, "HW context "); | |
3ccfd19d | 1549 | describe_ctx(m, ctx); |
a33afea5 BW |
1550 | for_each_ring(ring, dev_priv, i) |
1551 | if (ring->default_context == ctx) | |
1552 | seq_printf(m, "(default context %s) ", ring->name); | |
1553 | ||
1554 | describe_obj(m, ctx->obj); | |
1555 | seq_putc(m, '\n'); | |
a168c293 BW |
1556 | } |
1557 | ||
e76d3630 BW |
1558 | mutex_unlock(&dev->mode_config.mutex); |
1559 | ||
1560 | return 0; | |
1561 | } | |
1562 | ||
6d794d42 BW |
1563 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1564 | { | |
1565 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1566 | struct drm_device *dev = node->minor->dev; | |
1567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1568 | unsigned forcewake_count; |
6d794d42 | 1569 | |
907b28c5 CW |
1570 | spin_lock_irq(&dev_priv->uncore.lock); |
1571 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1572 | spin_unlock_irq(&dev_priv->uncore.lock); | |
6d794d42 | 1573 | |
9f1f46a4 | 1574 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1575 | |
1576 | return 0; | |
1577 | } | |
1578 | ||
ea16a3cd DV |
1579 | static const char *swizzle_string(unsigned swizzle) |
1580 | { | |
aee56cff | 1581 | switch (swizzle) { |
ea16a3cd DV |
1582 | case I915_BIT_6_SWIZZLE_NONE: |
1583 | return "none"; | |
1584 | case I915_BIT_6_SWIZZLE_9: | |
1585 | return "bit9"; | |
1586 | case I915_BIT_6_SWIZZLE_9_10: | |
1587 | return "bit9/bit10"; | |
1588 | case I915_BIT_6_SWIZZLE_9_11: | |
1589 | return "bit9/bit11"; | |
1590 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1591 | return "bit9/bit10/bit11"; | |
1592 | case I915_BIT_6_SWIZZLE_9_17: | |
1593 | return "bit9/bit17"; | |
1594 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1595 | return "bit9/bit10/bit17"; | |
1596 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1597 | return "unknown"; |
ea16a3cd DV |
1598 | } |
1599 | ||
1600 | return "bug"; | |
1601 | } | |
1602 | ||
1603 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1604 | { | |
1605 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1606 | struct drm_device *dev = node->minor->dev; | |
1607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1608 | int ret; |
1609 | ||
1610 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1611 | if (ret) | |
1612 | return ret; | |
ea16a3cd | 1613 | |
ea16a3cd DV |
1614 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1615 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1616 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1617 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1618 | ||
1619 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1620 | seq_printf(m, "DDC = 0x%08x\n", | |
1621 | I915_READ(DCC)); | |
1622 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1623 | I915_READ16(C0DRB3)); | |
1624 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1625 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1626 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1627 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1628 | I915_READ(MAD_DIMM_C0)); | |
1629 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1630 | I915_READ(MAD_DIMM_C1)); | |
1631 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1632 | I915_READ(MAD_DIMM_C2)); | |
1633 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1634 | I915_READ(TILECTL)); | |
1635 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1636 | I915_READ(ARB_MODE)); | |
1637 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1638 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1639 | } |
1640 | mutex_unlock(&dev->struct_mutex); | |
1641 | ||
1642 | return 0; | |
1643 | } | |
1644 | ||
3cf17fc5 DV |
1645 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1646 | { | |
1647 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1648 | struct drm_device *dev = node->minor->dev; | |
1649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1650 | struct intel_ring_buffer *ring; | |
1651 | int i, ret; | |
1652 | ||
1653 | ||
1654 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1655 | if (ret) | |
1656 | return ret; | |
1657 | if (INTEL_INFO(dev)->gen == 6) | |
1658 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1659 | ||
a2c7f6fd | 1660 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1661 | seq_printf(m, "%s\n", ring->name); |
1662 | if (INTEL_INFO(dev)->gen == 7) | |
1663 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1664 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1665 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1666 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1667 | } | |
1668 | if (dev_priv->mm.aliasing_ppgtt) { | |
1669 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1670 | ||
267f0c90 | 1671 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1672 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1673 | } | |
1674 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1675 | mutex_unlock(&dev->struct_mutex); | |
1676 | ||
1677 | return 0; | |
1678 | } | |
1679 | ||
57f350b6 JB |
1680 | static int i915_dpio_info(struct seq_file *m, void *data) |
1681 | { | |
1682 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1683 | struct drm_device *dev = node->minor->dev; | |
1684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1685 | int ret; | |
1686 | ||
1687 | ||
1688 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1689 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1690 | return 0; |
1691 | } | |
1692 | ||
09153000 | 1693 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1694 | if (ret) |
1695 | return ret; | |
1696 | ||
1697 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1698 | ||
1699 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
5e69f97f | 1700 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); |
57f350b6 | 1701 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
5e69f97f | 1702 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); |
57f350b6 JB |
1703 | |
1704 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
5e69f97f | 1705 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); |
57f350b6 | 1706 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
5e69f97f | 1707 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); |
57f350b6 JB |
1708 | |
1709 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
5e69f97f | 1710 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); |
57f350b6 | 1711 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
5e69f97f | 1712 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); |
57f350b6 | 1713 | |
4abb2c39 | 1714 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
5e69f97f | 1715 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); |
4abb2c39 | 1716 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", |
5e69f97f | 1717 | vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); |
57f350b6 JB |
1718 | |
1719 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
5e69f97f | 1720 | vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1721 | |
09153000 | 1722 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1723 | |
1724 | return 0; | |
1725 | } | |
1726 | ||
63573eb7 BW |
1727 | static int i915_llc(struct seq_file *m, void *data) |
1728 | { | |
1729 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1730 | struct drm_device *dev = node->minor->dev; | |
1731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1732 | ||
1733 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1734 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1735 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1736 | ||
1737 | return 0; | |
1738 | } | |
1739 | ||
e91fd8c6 RV |
1740 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1741 | { | |
1742 | struct drm_info_node *node = m->private; | |
1743 | struct drm_device *dev = node->minor->dev; | |
1744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1745 | u32 psrperf = 0; |
1746 | bool enabled = false; | |
e91fd8c6 | 1747 | |
a031d709 RV |
1748 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1749 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
e91fd8c6 | 1750 | |
a031d709 RV |
1751 | enabled = HAS_PSR(dev) && |
1752 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
1753 | seq_printf(m, "Enabled: %s\n", yesno(enabled)); | |
e91fd8c6 | 1754 | |
a031d709 RV |
1755 | if (HAS_PSR(dev)) |
1756 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1757 | EDP_PSR_PERF_CNT_MASK; | |
1758 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
e91fd8c6 RV |
1759 | |
1760 | return 0; | |
1761 | } | |
1762 | ||
ec013e7f JB |
1763 | static int i915_energy_uJ(struct seq_file *m, void *data) |
1764 | { | |
1765 | struct drm_info_node *node = m->private; | |
1766 | struct drm_device *dev = node->minor->dev; | |
1767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1768 | u64 power; | |
1769 | u32 units; | |
1770 | ||
1771 | if (INTEL_INFO(dev)->gen < 6) | |
1772 | return -ENODEV; | |
1773 | ||
1774 | rdmsrl(MSR_RAPL_POWER_UNIT, power); | |
1775 | power = (power & 0x1f00) >> 8; | |
1776 | units = 1000000 / (1 << power); /* convert to uJ */ | |
1777 | power = I915_READ(MCH_SECP_NRG_STTS); | |
1778 | power *= units; | |
1779 | ||
1780 | seq_printf(m, "%llu", (long long unsigned)power); | |
371db66a PZ |
1781 | |
1782 | return 0; | |
1783 | } | |
1784 | ||
1785 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
1786 | { | |
1787 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1788 | struct drm_device *dev = node->minor->dev; | |
1789 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1790 | ||
1791 | if (!IS_HASWELL(dev)) { | |
1792 | seq_puts(m, "not supported\n"); | |
1793 | return 0; | |
1794 | } | |
1795 | ||
1796 | mutex_lock(&dev_priv->pc8.lock); | |
1797 | seq_printf(m, "Requirements met: %s\n", | |
1798 | yesno(dev_priv->pc8.requirements_met)); | |
1799 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); | |
1800 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); | |
1801 | seq_printf(m, "IRQs disabled: %s\n", | |
1802 | yesno(dev_priv->pc8.irqs_disabled)); | |
1803 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); | |
1804 | mutex_unlock(&dev_priv->pc8.lock); | |
1805 | ||
ec013e7f JB |
1806 | return 0; |
1807 | } | |
1808 | ||
07144428 DL |
1809 | struct pipe_crc_info { |
1810 | const char *name; | |
1811 | struct drm_device *dev; | |
1812 | enum pipe pipe; | |
1813 | }; | |
1814 | ||
1815 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) | |
1816 | { | |
be5c7a90 DL |
1817 | struct pipe_crc_info *info = inode->i_private; |
1818 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
1819 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
1820 | ||
d538bbdf DL |
1821 | spin_lock_irq(&pipe_crc->lock); |
1822 | ||
1823 | if (pipe_crc->opened) { | |
1824 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
1825 | return -EBUSY; /* already open */ |
1826 | } | |
1827 | ||
d538bbdf | 1828 | pipe_crc->opened = true; |
07144428 DL |
1829 | filep->private_data = inode->i_private; |
1830 | ||
d538bbdf DL |
1831 | spin_unlock_irq(&pipe_crc->lock); |
1832 | ||
07144428 DL |
1833 | return 0; |
1834 | } | |
1835 | ||
1836 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
1837 | { | |
be5c7a90 DL |
1838 | struct pipe_crc_info *info = inode->i_private; |
1839 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
1840 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
1841 | ||
d538bbdf DL |
1842 | spin_lock_irq(&pipe_crc->lock); |
1843 | pipe_crc->opened = false; | |
1844 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 1845 | |
07144428 DL |
1846 | return 0; |
1847 | } | |
1848 | ||
1849 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
1850 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
1851 | /* account for \'0' */ | |
1852 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
1853 | ||
1854 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 1855 | { |
d538bbdf DL |
1856 | assert_spin_locked(&pipe_crc->lock); |
1857 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
1858 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
1859 | } |
1860 | ||
1861 | static ssize_t | |
1862 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
1863 | loff_t *pos) | |
1864 | { | |
1865 | struct pipe_crc_info *info = filep->private_data; | |
1866 | struct drm_device *dev = info->dev; | |
1867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1868 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
1869 | char buf[PIPE_CRC_BUFFER_LEN]; | |
1870 | int head, tail, n_entries, n; | |
1871 | ssize_t bytes_read; | |
1872 | ||
1873 | /* | |
1874 | * Don't allow user space to provide buffers not big enough to hold | |
1875 | * a line of data. | |
1876 | */ | |
1877 | if (count < PIPE_CRC_LINE_LEN) | |
1878 | return -EINVAL; | |
1879 | ||
1880 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 1881 | return 0; |
07144428 DL |
1882 | |
1883 | /* nothing to read */ | |
d538bbdf | 1884 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 1885 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
1886 | int ret; |
1887 | ||
1888 | if (filep->f_flags & O_NONBLOCK) { | |
1889 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 1890 | return -EAGAIN; |
d538bbdf | 1891 | } |
07144428 | 1892 | |
d538bbdf DL |
1893 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
1894 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
1895 | if (ret) { | |
1896 | spin_unlock_irq(&pipe_crc->lock); | |
1897 | return ret; | |
1898 | } | |
8bf1e9f1 SH |
1899 | } |
1900 | ||
07144428 | 1901 | /* We now have one or more entries to read */ |
d538bbdf DL |
1902 | head = pipe_crc->head; |
1903 | tail = pipe_crc->tail; | |
07144428 DL |
1904 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
1905 | count / PIPE_CRC_LINE_LEN); | |
d538bbdf DL |
1906 | spin_unlock_irq(&pipe_crc->lock); |
1907 | ||
07144428 DL |
1908 | bytes_read = 0; |
1909 | n = 0; | |
1910 | do { | |
b2c88f5b | 1911 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
07144428 | 1912 | int ret; |
8bf1e9f1 | 1913 | |
07144428 DL |
1914 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
1915 | "%8u %8x %8x %8x %8x %8x\n", | |
1916 | entry->frame, entry->crc[0], | |
1917 | entry->crc[1], entry->crc[2], | |
1918 | entry->crc[3], entry->crc[4]); | |
1919 | ||
1920 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, | |
1921 | buf, PIPE_CRC_LINE_LEN); | |
1922 | if (ret == PIPE_CRC_LINE_LEN) | |
1923 | return -EFAULT; | |
b2c88f5b DL |
1924 | |
1925 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
1926 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
07144428 DL |
1927 | n++; |
1928 | } while (--n_entries); | |
8bf1e9f1 | 1929 | |
d538bbdf DL |
1930 | spin_lock_irq(&pipe_crc->lock); |
1931 | pipe_crc->tail = tail; | |
1932 | spin_unlock_irq(&pipe_crc->lock); | |
1933 | ||
07144428 DL |
1934 | return bytes_read; |
1935 | } | |
1936 | ||
1937 | static const struct file_operations i915_pipe_crc_fops = { | |
1938 | .owner = THIS_MODULE, | |
1939 | .open = i915_pipe_crc_open, | |
1940 | .read = i915_pipe_crc_read, | |
1941 | .release = i915_pipe_crc_release, | |
1942 | }; | |
1943 | ||
1944 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
1945 | { | |
1946 | .name = "i915_pipe_A_crc", | |
1947 | .pipe = PIPE_A, | |
1948 | }, | |
1949 | { | |
1950 | .name = "i915_pipe_B_crc", | |
1951 | .pipe = PIPE_B, | |
1952 | }, | |
1953 | { | |
1954 | .name = "i915_pipe_C_crc", | |
1955 | .pipe = PIPE_C, | |
1956 | }, | |
1957 | }; | |
1958 | ||
1959 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
1960 | enum pipe pipe) | |
1961 | { | |
1962 | struct drm_device *dev = minor->dev; | |
1963 | struct dentry *ent; | |
1964 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
1965 | ||
1966 | info->dev = dev; | |
1967 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
1968 | &i915_pipe_crc_fops); | |
1969 | if (IS_ERR(ent)) | |
1970 | return PTR_ERR(ent); | |
1971 | ||
1972 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
1973 | } |
1974 | ||
e8dfcf78 | 1975 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
1976 | "none", |
1977 | "plane1", | |
1978 | "plane2", | |
1979 | "pf", | |
5b3a856b | 1980 | "pipe", |
3d099a05 DV |
1981 | "TV", |
1982 | "DP-B", | |
1983 | "DP-C", | |
1984 | "DP-D", | |
46a19188 | 1985 | "auto", |
926321d5 DV |
1986 | }; |
1987 | ||
1988 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
1989 | { | |
1990 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
1991 | return pipe_crc_sources[source]; | |
1992 | } | |
1993 | ||
bd9db02f | 1994 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
1995 | { |
1996 | struct drm_device *dev = m->private; | |
1997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1998 | int i; | |
1999 | ||
2000 | for (i = 0; i < I915_MAX_PIPES; i++) | |
2001 | seq_printf(m, "%c %s\n", pipe_name(i), | |
2002 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
2003 | ||
2004 | return 0; | |
2005 | } | |
2006 | ||
bd9db02f | 2007 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
2008 | { |
2009 | struct drm_device *dev = inode->i_private; | |
2010 | ||
bd9db02f | 2011 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
2012 | } |
2013 | ||
46a19188 | 2014 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
2015 | uint32_t *val) |
2016 | { | |
46a19188 DV |
2017 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2018 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2019 | ||
2020 | switch (*source) { | |
52f843f6 DV |
2021 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2022 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
2023 | break; | |
2024 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2025 | *val = 0; | |
2026 | break; | |
2027 | default: | |
2028 | return -EINVAL; | |
2029 | } | |
2030 | ||
2031 | return 0; | |
2032 | } | |
2033 | ||
46a19188 DV |
2034 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
2035 | enum intel_pipe_crc_source *source) | |
2036 | { | |
2037 | struct intel_encoder *encoder; | |
2038 | struct intel_crtc *crtc; | |
26756809 | 2039 | struct intel_digital_port *dig_port; |
46a19188 DV |
2040 | int ret = 0; |
2041 | ||
2042 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2043 | ||
2044 | mutex_lock(&dev->mode_config.mutex); | |
2045 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
2046 | base.head) { | |
2047 | if (!encoder->base.crtc) | |
2048 | continue; | |
2049 | ||
2050 | crtc = to_intel_crtc(encoder->base.crtc); | |
2051 | ||
2052 | if (crtc->pipe != pipe) | |
2053 | continue; | |
2054 | ||
2055 | switch (encoder->type) { | |
2056 | case INTEL_OUTPUT_TVOUT: | |
2057 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
2058 | break; | |
2059 | case INTEL_OUTPUT_DISPLAYPORT: | |
2060 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
2061 | dig_port = enc_to_dig_port(&encoder->base); |
2062 | switch (dig_port->port) { | |
2063 | case PORT_B: | |
2064 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
2065 | break; | |
2066 | case PORT_C: | |
2067 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
2068 | break; | |
2069 | case PORT_D: | |
2070 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
2071 | break; | |
2072 | default: | |
2073 | WARN(1, "nonexisting DP port %c\n", | |
2074 | port_name(dig_port->port)); | |
2075 | break; | |
2076 | } | |
46a19188 DV |
2077 | break; |
2078 | } | |
2079 | } | |
2080 | mutex_unlock(&dev->mode_config.mutex); | |
2081 | ||
2082 | return ret; | |
2083 | } | |
2084 | ||
2085 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
2086 | enum pipe pipe, | |
2087 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
2088 | uint32_t *val) |
2089 | { | |
8d2f24ca DV |
2090 | struct drm_i915_private *dev_priv = dev->dev_private; |
2091 | bool need_stable_symbols = false; | |
2092 | ||
46a19188 DV |
2093 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2094 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2095 | if (ret) | |
2096 | return ret; | |
2097 | } | |
2098 | ||
2099 | switch (*source) { | |
7ac0129b DV |
2100 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2101 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
2102 | break; | |
2103 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2104 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 2105 | need_stable_symbols = true; |
7ac0129b DV |
2106 | break; |
2107 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2108 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 2109 | need_stable_symbols = true; |
7ac0129b DV |
2110 | break; |
2111 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2112 | *val = 0; | |
2113 | break; | |
2114 | default: | |
2115 | return -EINVAL; | |
2116 | } | |
2117 | ||
8d2f24ca DV |
2118 | /* |
2119 | * When the pipe CRC tap point is after the transcoders we need | |
2120 | * to tweak symbol-level features to produce a deterministic series of | |
2121 | * symbols for a given frame. We need to reset those features only once | |
2122 | * a frame (instead of every nth symbol): | |
2123 | * - DC-balance: used to ensure a better clock recovery from the data | |
2124 | * link (SDVO) | |
2125 | * - DisplayPort scrambling: used for EMI reduction | |
2126 | */ | |
2127 | if (need_stable_symbols) { | |
2128 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2129 | ||
2130 | WARN_ON(!IS_G4X(dev)); | |
2131 | ||
2132 | tmp |= DC_BALANCE_RESET_VLV; | |
2133 | if (pipe == PIPE_A) | |
2134 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2135 | else | |
2136 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2137 | ||
2138 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2139 | } | |
2140 | ||
7ac0129b DV |
2141 | return 0; |
2142 | } | |
2143 | ||
4b79ebf7 | 2144 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
2145 | enum pipe pipe, |
2146 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
2147 | uint32_t *val) |
2148 | { | |
84093603 DV |
2149 | struct drm_i915_private *dev_priv = dev->dev_private; |
2150 | bool need_stable_symbols = false; | |
2151 | ||
46a19188 DV |
2152 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2153 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2154 | if (ret) | |
2155 | return ret; | |
2156 | } | |
2157 | ||
2158 | switch (*source) { | |
4b79ebf7 DV |
2159 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2160 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
2161 | break; | |
2162 | case INTEL_PIPE_CRC_SOURCE_TV: | |
2163 | if (!SUPPORTS_TV(dev)) | |
2164 | return -EINVAL; | |
2165 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
2166 | break; | |
2167 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2168 | if (!IS_G4X(dev)) | |
2169 | return -EINVAL; | |
2170 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 2171 | need_stable_symbols = true; |
4b79ebf7 DV |
2172 | break; |
2173 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2174 | if (!IS_G4X(dev)) | |
2175 | return -EINVAL; | |
2176 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 2177 | need_stable_symbols = true; |
4b79ebf7 DV |
2178 | break; |
2179 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
2180 | if (!IS_G4X(dev)) | |
2181 | return -EINVAL; | |
2182 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 2183 | need_stable_symbols = true; |
4b79ebf7 DV |
2184 | break; |
2185 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2186 | *val = 0; | |
2187 | break; | |
2188 | default: | |
2189 | return -EINVAL; | |
2190 | } | |
2191 | ||
84093603 DV |
2192 | /* |
2193 | * When the pipe CRC tap point is after the transcoders we need | |
2194 | * to tweak symbol-level features to produce a deterministic series of | |
2195 | * symbols for a given frame. We need to reset those features only once | |
2196 | * a frame (instead of every nth symbol): | |
2197 | * - DC-balance: used to ensure a better clock recovery from the data | |
2198 | * link (SDVO) | |
2199 | * - DisplayPort scrambling: used for EMI reduction | |
2200 | */ | |
2201 | if (need_stable_symbols) { | |
2202 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2203 | ||
2204 | WARN_ON(!IS_G4X(dev)); | |
2205 | ||
2206 | I915_WRITE(PORT_DFT_I9XX, | |
2207 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
2208 | ||
2209 | if (pipe == PIPE_A) | |
2210 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2211 | else | |
2212 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2213 | ||
2214 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2215 | } | |
2216 | ||
4b79ebf7 DV |
2217 | return 0; |
2218 | } | |
2219 | ||
8d2f24ca DV |
2220 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
2221 | enum pipe pipe) | |
2222 | { | |
2223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2224 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2225 | ||
2226 | if (pipe == PIPE_A) | |
2227 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2228 | else | |
2229 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2230 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) | |
2231 | tmp &= ~DC_BALANCE_RESET_VLV; | |
2232 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2233 | ||
2234 | } | |
2235 | ||
84093603 DV |
2236 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
2237 | enum pipe pipe) | |
2238 | { | |
2239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2240 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2241 | ||
2242 | if (pipe == PIPE_A) | |
2243 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2244 | else | |
2245 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2246 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2247 | ||
2248 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
2249 | I915_WRITE(PORT_DFT_I9XX, | |
2250 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
2251 | } | |
2252 | } | |
2253 | ||
46a19188 | 2254 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2255 | uint32_t *val) |
2256 | { | |
46a19188 DV |
2257 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2258 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2259 | ||
2260 | switch (*source) { | |
5b3a856b DV |
2261 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2262 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
2263 | break; | |
2264 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2265 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
2266 | break; | |
5b3a856b DV |
2267 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2268 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
2269 | break; | |
3d099a05 | 2270 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2271 | *val = 0; |
2272 | break; | |
3d099a05 DV |
2273 | default: |
2274 | return -EINVAL; | |
5b3a856b DV |
2275 | } |
2276 | ||
2277 | return 0; | |
2278 | } | |
2279 | ||
46a19188 | 2280 | static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2281 | uint32_t *val) |
2282 | { | |
46a19188 DV |
2283 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2284 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
2285 | ||
2286 | switch (*source) { | |
5b3a856b DV |
2287 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2288 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
2289 | break; | |
2290 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2291 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
2292 | break; | |
2293 | case INTEL_PIPE_CRC_SOURCE_PF: | |
2294 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; | |
2295 | break; | |
3d099a05 | 2296 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2297 | *val = 0; |
2298 | break; | |
3d099a05 DV |
2299 | default: |
2300 | return -EINVAL; | |
5b3a856b DV |
2301 | } |
2302 | ||
2303 | return 0; | |
2304 | } | |
2305 | ||
926321d5 DV |
2306 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
2307 | enum intel_pipe_crc_source source) | |
2308 | { | |
2309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 2310 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
926321d5 | 2311 | u32 val; |
5b3a856b | 2312 | int ret; |
926321d5 | 2313 | |
cc3da175 DL |
2314 | if (pipe_crc->source == source) |
2315 | return 0; | |
2316 | ||
ae676fcd DL |
2317 | /* forbid changing the source without going back to 'none' */ |
2318 | if (pipe_crc->source && source) | |
2319 | return -EINVAL; | |
2320 | ||
52f843f6 | 2321 | if (IS_GEN2(dev)) |
46a19188 | 2322 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 2323 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 2324 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
7ac0129b | 2325 | else if (IS_VALLEYVIEW(dev)) |
46a19188 | 2326 | ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val); |
4b79ebf7 | 2327 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 2328 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 2329 | else |
46a19188 | 2330 | ret = ivb_pipe_crc_ctl_reg(&source, &val); |
5b3a856b DV |
2331 | |
2332 | if (ret != 0) | |
2333 | return ret; | |
2334 | ||
4b584369 DL |
2335 | /* none -> real source transition */ |
2336 | if (source) { | |
7cd6ccff DL |
2337 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
2338 | pipe_name(pipe), pipe_crc_source_name(source)); | |
2339 | ||
e5f75aca DL |
2340 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
2341 | INTEL_PIPE_CRC_ENTRIES_NR, | |
2342 | GFP_KERNEL); | |
2343 | if (!pipe_crc->entries) | |
2344 | return -ENOMEM; | |
2345 | ||
d538bbdf DL |
2346 | spin_lock_irq(&pipe_crc->lock); |
2347 | pipe_crc->head = 0; | |
2348 | pipe_crc->tail = 0; | |
2349 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
2350 | } |
2351 | ||
cc3da175 | 2352 | pipe_crc->source = source; |
926321d5 | 2353 | |
926321d5 DV |
2354 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
2355 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
2356 | ||
e5f75aca DL |
2357 | /* real source -> none transition */ |
2358 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf DL |
2359 | struct intel_pipe_crc_entry *entries; |
2360 | ||
7cd6ccff DL |
2361 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
2362 | pipe_name(pipe)); | |
2363 | ||
bcf17ab2 DV |
2364 | intel_wait_for_vblank(dev, pipe); |
2365 | ||
d538bbdf DL |
2366 | spin_lock_irq(&pipe_crc->lock); |
2367 | entries = pipe_crc->entries; | |
e5f75aca | 2368 | pipe_crc->entries = NULL; |
d538bbdf DL |
2369 | spin_unlock_irq(&pipe_crc->lock); |
2370 | ||
2371 | kfree(entries); | |
84093603 DV |
2372 | |
2373 | if (IS_G4X(dev)) | |
2374 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
8d2f24ca DV |
2375 | else if (IS_VALLEYVIEW(dev)) |
2376 | vlv_undo_pipe_scramble_reset(dev, pipe); | |
e5f75aca DL |
2377 | } |
2378 | ||
926321d5 DV |
2379 | return 0; |
2380 | } | |
2381 | ||
2382 | /* | |
2383 | * Parse pipe CRC command strings: | |
b94dec87 DL |
2384 | * command: wsp* object wsp+ name wsp+ source wsp* |
2385 | * object: 'pipe' | |
2386 | * name: (A | B | C) | |
926321d5 DV |
2387 | * source: (none | plane1 | plane2 | pf) |
2388 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
2389 | * | |
2390 | * eg.: | |
b94dec87 DL |
2391 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
2392 | * "pipe A none" -> Stop CRC | |
926321d5 | 2393 | */ |
bd9db02f | 2394 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
2395 | { |
2396 | int n_words = 0; | |
2397 | ||
2398 | while (*buf) { | |
2399 | char *end; | |
2400 | ||
2401 | /* skip leading white space */ | |
2402 | buf = skip_spaces(buf); | |
2403 | if (!*buf) | |
2404 | break; /* end of buffer */ | |
2405 | ||
2406 | /* find end of word */ | |
2407 | for (end = buf; *end && !isspace(*end); end++) | |
2408 | ; | |
2409 | ||
2410 | if (n_words == max_words) { | |
2411 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
2412 | max_words); | |
2413 | return -EINVAL; /* ran out of words[] before bytes */ | |
2414 | } | |
2415 | ||
2416 | if (*end) | |
2417 | *end++ = '\0'; | |
2418 | words[n_words++] = buf; | |
2419 | buf = end; | |
2420 | } | |
2421 | ||
2422 | return n_words; | |
2423 | } | |
2424 | ||
b94dec87 DL |
2425 | enum intel_pipe_crc_object { |
2426 | PIPE_CRC_OBJECT_PIPE, | |
2427 | }; | |
2428 | ||
e8dfcf78 | 2429 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
2430 | "pipe", |
2431 | }; | |
2432 | ||
2433 | static int | |
bd9db02f | 2434 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
2435 | { |
2436 | int i; | |
2437 | ||
2438 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
2439 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 2440 | *o = i; |
b94dec87 DL |
2441 | return 0; |
2442 | } | |
2443 | ||
2444 | return -EINVAL; | |
2445 | } | |
2446 | ||
bd9db02f | 2447 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
2448 | { |
2449 | const char name = buf[0]; | |
2450 | ||
2451 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
2452 | return -EINVAL; | |
2453 | ||
2454 | *pipe = name - 'A'; | |
2455 | ||
2456 | return 0; | |
2457 | } | |
2458 | ||
2459 | static int | |
bd9db02f | 2460 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
2461 | { |
2462 | int i; | |
2463 | ||
2464 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
2465 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 2466 | *s = i; |
926321d5 DV |
2467 | return 0; |
2468 | } | |
2469 | ||
2470 | return -EINVAL; | |
2471 | } | |
2472 | ||
bd9db02f | 2473 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 2474 | { |
b94dec87 | 2475 | #define N_WORDS 3 |
926321d5 | 2476 | int n_words; |
b94dec87 | 2477 | char *words[N_WORDS]; |
926321d5 | 2478 | enum pipe pipe; |
b94dec87 | 2479 | enum intel_pipe_crc_object object; |
926321d5 DV |
2480 | enum intel_pipe_crc_source source; |
2481 | ||
bd9db02f | 2482 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
2483 | if (n_words != N_WORDS) { |
2484 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
2485 | N_WORDS); | |
2486 | return -EINVAL; | |
2487 | } | |
2488 | ||
bd9db02f | 2489 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 2490 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
2491 | return -EINVAL; |
2492 | } | |
2493 | ||
bd9db02f | 2494 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 2495 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
2496 | return -EINVAL; |
2497 | } | |
2498 | ||
bd9db02f | 2499 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 2500 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
2501 | return -EINVAL; |
2502 | } | |
2503 | ||
2504 | return pipe_crc_set_source(dev, pipe, source); | |
2505 | } | |
2506 | ||
bd9db02f DL |
2507 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
2508 | size_t len, loff_t *offp) | |
926321d5 DV |
2509 | { |
2510 | struct seq_file *m = file->private_data; | |
2511 | struct drm_device *dev = m->private; | |
2512 | char *tmpbuf; | |
2513 | int ret; | |
2514 | ||
2515 | if (len == 0) | |
2516 | return 0; | |
2517 | ||
2518 | if (len > PAGE_SIZE - 1) { | |
2519 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
2520 | PAGE_SIZE); | |
2521 | return -E2BIG; | |
2522 | } | |
2523 | ||
2524 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
2525 | if (!tmpbuf) | |
2526 | return -ENOMEM; | |
2527 | ||
2528 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
2529 | ret = -EFAULT; | |
2530 | goto out; | |
2531 | } | |
2532 | tmpbuf[len] = '\0'; | |
2533 | ||
bd9db02f | 2534 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
2535 | |
2536 | out: | |
2537 | kfree(tmpbuf); | |
2538 | if (ret < 0) | |
2539 | return ret; | |
2540 | ||
2541 | *offp += len; | |
2542 | return len; | |
2543 | } | |
2544 | ||
bd9db02f | 2545 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 2546 | .owner = THIS_MODULE, |
bd9db02f | 2547 | .open = display_crc_ctl_open, |
926321d5 DV |
2548 | .read = seq_read, |
2549 | .llseek = seq_lseek, | |
2550 | .release = single_release, | |
bd9db02f | 2551 | .write = display_crc_ctl_write |
926321d5 DV |
2552 | }; |
2553 | ||
647416f9 KC |
2554 | static int |
2555 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 2556 | { |
647416f9 | 2557 | struct drm_device *dev = data; |
f3cd474b | 2558 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 2559 | |
647416f9 | 2560 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 2561 | |
647416f9 | 2562 | return 0; |
f3cd474b CW |
2563 | } |
2564 | ||
647416f9 KC |
2565 | static int |
2566 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 2567 | { |
647416f9 | 2568 | struct drm_device *dev = data; |
f3cd474b | 2569 | |
647416f9 | 2570 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 2571 | i915_handle_error(dev, val); |
f3cd474b | 2572 | |
647416f9 | 2573 | return 0; |
f3cd474b CW |
2574 | } |
2575 | ||
647416f9 KC |
2576 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
2577 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 2578 | "%llu\n"); |
f3cd474b | 2579 | |
647416f9 KC |
2580 | static int |
2581 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 2582 | { |
647416f9 | 2583 | struct drm_device *dev = data; |
e5eb3d63 | 2584 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 2585 | |
647416f9 | 2586 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 2587 | |
647416f9 | 2588 | return 0; |
e5eb3d63 DV |
2589 | } |
2590 | ||
647416f9 KC |
2591 | static int |
2592 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 2593 | { |
647416f9 | 2594 | struct drm_device *dev = data; |
e5eb3d63 | 2595 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2596 | int ret; |
e5eb3d63 | 2597 | |
647416f9 | 2598 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 2599 | |
22bcfc6a DV |
2600 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2601 | if (ret) | |
2602 | return ret; | |
2603 | ||
99584db3 | 2604 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
2605 | mutex_unlock(&dev->struct_mutex); |
2606 | ||
647416f9 | 2607 | return 0; |
e5eb3d63 DV |
2608 | } |
2609 | ||
647416f9 KC |
2610 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
2611 | i915_ring_stop_get, i915_ring_stop_set, | |
2612 | "0x%08llx\n"); | |
d5442303 | 2613 | |
094f9a54 CW |
2614 | static int |
2615 | i915_ring_missed_irq_get(void *data, u64 *val) | |
2616 | { | |
2617 | struct drm_device *dev = data; | |
2618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2619 | ||
2620 | *val = dev_priv->gpu_error.missed_irq_rings; | |
2621 | return 0; | |
2622 | } | |
2623 | ||
2624 | static int | |
2625 | i915_ring_missed_irq_set(void *data, u64 val) | |
2626 | { | |
2627 | struct drm_device *dev = data; | |
2628 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2629 | int ret; | |
2630 | ||
2631 | /* Lock against concurrent debugfs callers */ | |
2632 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2633 | if (ret) | |
2634 | return ret; | |
2635 | dev_priv->gpu_error.missed_irq_rings = val; | |
2636 | mutex_unlock(&dev->struct_mutex); | |
2637 | ||
2638 | return 0; | |
2639 | } | |
2640 | ||
2641 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
2642 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
2643 | "0x%08llx\n"); | |
2644 | ||
2645 | static int | |
2646 | i915_ring_test_irq_get(void *data, u64 *val) | |
2647 | { | |
2648 | struct drm_device *dev = data; | |
2649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2650 | ||
2651 | *val = dev_priv->gpu_error.test_irq_rings; | |
2652 | ||
2653 | return 0; | |
2654 | } | |
2655 | ||
2656 | static int | |
2657 | i915_ring_test_irq_set(void *data, u64 val) | |
2658 | { | |
2659 | struct drm_device *dev = data; | |
2660 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2661 | int ret; | |
2662 | ||
2663 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
2664 | ||
2665 | /* Lock against concurrent debugfs callers */ | |
2666 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2667 | if (ret) | |
2668 | return ret; | |
2669 | ||
2670 | dev_priv->gpu_error.test_irq_rings = val; | |
2671 | mutex_unlock(&dev->struct_mutex); | |
2672 | ||
2673 | return 0; | |
2674 | } | |
2675 | ||
2676 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
2677 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
2678 | "0x%08llx\n"); | |
2679 | ||
dd624afd CW |
2680 | #define DROP_UNBOUND 0x1 |
2681 | #define DROP_BOUND 0x2 | |
2682 | #define DROP_RETIRE 0x4 | |
2683 | #define DROP_ACTIVE 0x8 | |
2684 | #define DROP_ALL (DROP_UNBOUND | \ | |
2685 | DROP_BOUND | \ | |
2686 | DROP_RETIRE | \ | |
2687 | DROP_ACTIVE) | |
647416f9 KC |
2688 | static int |
2689 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 2690 | { |
647416f9 | 2691 | *val = DROP_ALL; |
dd624afd | 2692 | |
647416f9 | 2693 | return 0; |
dd624afd CW |
2694 | } |
2695 | ||
647416f9 KC |
2696 | static int |
2697 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 2698 | { |
647416f9 | 2699 | struct drm_device *dev = data; |
dd624afd CW |
2700 | struct drm_i915_private *dev_priv = dev->dev_private; |
2701 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
2702 | struct i915_address_space *vm; |
2703 | struct i915_vma *vma, *x; | |
647416f9 | 2704 | int ret; |
dd624afd | 2705 | |
647416f9 | 2706 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
2707 | |
2708 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
2709 | * on ioctls on -EAGAIN. */ | |
2710 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2711 | if (ret) | |
2712 | return ret; | |
2713 | ||
2714 | if (val & DROP_ACTIVE) { | |
2715 | ret = i915_gpu_idle(dev); | |
2716 | if (ret) | |
2717 | goto unlock; | |
2718 | } | |
2719 | ||
2720 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
2721 | i915_gem_retire_requests(dev); | |
2722 | ||
2723 | if (val & DROP_BOUND) { | |
ca191b13 BW |
2724 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2725 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
2726 | mm_list) { | |
2727 | if (vma->obj->pin_count) | |
2728 | continue; | |
2729 | ||
2730 | ret = i915_vma_unbind(vma); | |
2731 | if (ret) | |
2732 | goto unlock; | |
2733 | } | |
31a46c9c | 2734 | } |
dd624afd CW |
2735 | } |
2736 | ||
2737 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
2738 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
2739 | global_list) | |
dd624afd CW |
2740 | if (obj->pages_pin_count == 0) { |
2741 | ret = i915_gem_object_put_pages(obj); | |
2742 | if (ret) | |
2743 | goto unlock; | |
2744 | } | |
2745 | } | |
2746 | ||
2747 | unlock: | |
2748 | mutex_unlock(&dev->struct_mutex); | |
2749 | ||
647416f9 | 2750 | return ret; |
dd624afd CW |
2751 | } |
2752 | ||
647416f9 KC |
2753 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
2754 | i915_drop_caches_get, i915_drop_caches_set, | |
2755 | "0x%08llx\n"); | |
dd624afd | 2756 | |
647416f9 KC |
2757 | static int |
2758 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 2759 | { |
647416f9 | 2760 | struct drm_device *dev = data; |
358733e9 | 2761 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2762 | int ret; |
004777cb DV |
2763 | |
2764 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2765 | return -ENODEV; | |
2766 | ||
5c9669ce TR |
2767 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2768 | ||
4fc688ce | 2769 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2770 | if (ret) |
2771 | return ret; | |
358733e9 | 2772 | |
0a073b84 JB |
2773 | if (IS_VALLEYVIEW(dev)) |
2774 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2775 | dev_priv->rps.max_delay); | |
2776 | else | |
2777 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2778 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2779 | |
647416f9 | 2780 | return 0; |
358733e9 JB |
2781 | } |
2782 | ||
647416f9 KC |
2783 | static int |
2784 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 2785 | { |
647416f9 | 2786 | struct drm_device *dev = data; |
358733e9 | 2787 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2788 | int ret; |
004777cb DV |
2789 | |
2790 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2791 | return -ENODEV; | |
358733e9 | 2792 | |
5c9669ce TR |
2793 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2794 | ||
647416f9 | 2795 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 2796 | |
4fc688ce | 2797 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2798 | if (ret) |
2799 | return ret; | |
2800 | ||
358733e9 JB |
2801 | /* |
2802 | * Turbo will still be enabled, but won't go above the set value. | |
2803 | */ | |
0a073b84 JB |
2804 | if (IS_VALLEYVIEW(dev)) { |
2805 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2806 | dev_priv->rps.max_delay = val; | |
2807 | gen6_set_rps(dev, val); | |
2808 | } else { | |
2809 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2810 | dev_priv->rps.max_delay = val; | |
2811 | gen6_set_rps(dev, val); | |
2812 | } | |
2813 | ||
4fc688ce | 2814 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2815 | |
647416f9 | 2816 | return 0; |
358733e9 JB |
2817 | } |
2818 | ||
647416f9 KC |
2819 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
2820 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 2821 | "%llu\n"); |
358733e9 | 2822 | |
647416f9 KC |
2823 | static int |
2824 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 2825 | { |
647416f9 | 2826 | struct drm_device *dev = data; |
1523c310 | 2827 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2828 | int ret; |
004777cb DV |
2829 | |
2830 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2831 | return -ENODEV; | |
2832 | ||
5c9669ce TR |
2833 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2834 | ||
4fc688ce | 2835 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2836 | if (ret) |
2837 | return ret; | |
1523c310 | 2838 | |
0a073b84 JB |
2839 | if (IS_VALLEYVIEW(dev)) |
2840 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
2841 | dev_priv->rps.min_delay); | |
2842 | else | |
2843 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2844 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2845 | |
647416f9 | 2846 | return 0; |
1523c310 JB |
2847 | } |
2848 | ||
647416f9 KC |
2849 | static int |
2850 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 2851 | { |
647416f9 | 2852 | struct drm_device *dev = data; |
1523c310 | 2853 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2854 | int ret; |
004777cb DV |
2855 | |
2856 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2857 | return -ENODEV; | |
1523c310 | 2858 | |
5c9669ce TR |
2859 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2860 | ||
647416f9 | 2861 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 2862 | |
4fc688ce | 2863 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2864 | if (ret) |
2865 | return ret; | |
2866 | ||
1523c310 JB |
2867 | /* |
2868 | * Turbo will still be enabled, but won't go below the set value. | |
2869 | */ | |
0a073b84 JB |
2870 | if (IS_VALLEYVIEW(dev)) { |
2871 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
2872 | dev_priv->rps.min_delay = val; | |
2873 | valleyview_set_rps(dev, val); | |
2874 | } else { | |
2875 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2876 | dev_priv->rps.min_delay = val; | |
2877 | gen6_set_rps(dev, val); | |
2878 | } | |
4fc688ce | 2879 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2880 | |
647416f9 | 2881 | return 0; |
1523c310 JB |
2882 | } |
2883 | ||
647416f9 KC |
2884 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
2885 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 2886 | "%llu\n"); |
1523c310 | 2887 | |
647416f9 KC |
2888 | static int |
2889 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 2890 | { |
647416f9 | 2891 | struct drm_device *dev = data; |
07b7ddd9 | 2892 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 2893 | u32 snpcr; |
647416f9 | 2894 | int ret; |
07b7ddd9 | 2895 | |
004777cb DV |
2896 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2897 | return -ENODEV; | |
2898 | ||
22bcfc6a DV |
2899 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2900 | if (ret) | |
2901 | return ret; | |
2902 | ||
07b7ddd9 JB |
2903 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
2904 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
2905 | ||
647416f9 | 2906 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 2907 | |
647416f9 | 2908 | return 0; |
07b7ddd9 JB |
2909 | } |
2910 | ||
647416f9 KC |
2911 | static int |
2912 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 2913 | { |
647416f9 | 2914 | struct drm_device *dev = data; |
07b7ddd9 | 2915 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 2916 | u32 snpcr; |
07b7ddd9 | 2917 | |
004777cb DV |
2918 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
2919 | return -ENODEV; | |
2920 | ||
647416f9 | 2921 | if (val > 3) |
07b7ddd9 JB |
2922 | return -EINVAL; |
2923 | ||
647416f9 | 2924 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
2925 | |
2926 | /* Update the cache sharing policy here as well */ | |
2927 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
2928 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
2929 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
2930 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
2931 | ||
647416f9 | 2932 | return 0; |
07b7ddd9 JB |
2933 | } |
2934 | ||
647416f9 KC |
2935 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
2936 | i915_cache_sharing_get, i915_cache_sharing_set, | |
2937 | "%llu\n"); | |
07b7ddd9 | 2938 | |
6d794d42 BW |
2939 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2940 | { | |
2941 | struct drm_device *dev = inode->i_private; | |
2942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2943 | |
075edca4 | 2944 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2945 | return 0; |
2946 | ||
6d794d42 | 2947 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2948 | |
2949 | return 0; | |
2950 | } | |
2951 | ||
c43b5634 | 2952 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2953 | { |
2954 | struct drm_device *dev = inode->i_private; | |
2955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2956 | ||
075edca4 | 2957 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2958 | return 0; |
2959 | ||
6d794d42 | 2960 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2961 | |
2962 | return 0; | |
2963 | } | |
2964 | ||
2965 | static const struct file_operations i915_forcewake_fops = { | |
2966 | .owner = THIS_MODULE, | |
2967 | .open = i915_forcewake_open, | |
2968 | .release = i915_forcewake_release, | |
2969 | }; | |
2970 | ||
2971 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2972 | { | |
2973 | struct drm_device *dev = minor->dev; | |
2974 | struct dentry *ent; | |
2975 | ||
2976 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2977 | S_IRUSR, |
6d794d42 BW |
2978 | root, dev, |
2979 | &i915_forcewake_fops); | |
2980 | if (IS_ERR(ent)) | |
2981 | return PTR_ERR(ent); | |
2982 | ||
8eb57294 | 2983 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2984 | } |
2985 | ||
6a9c308d DV |
2986 | static int i915_debugfs_create(struct dentry *root, |
2987 | struct drm_minor *minor, | |
2988 | const char *name, | |
2989 | const struct file_operations *fops) | |
07b7ddd9 JB |
2990 | { |
2991 | struct drm_device *dev = minor->dev; | |
2992 | struct dentry *ent; | |
2993 | ||
6a9c308d | 2994 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2995 | S_IRUGO | S_IWUSR, |
2996 | root, dev, | |
6a9c308d | 2997 | fops); |
07b7ddd9 JB |
2998 | if (IS_ERR(ent)) |
2999 | return PTR_ERR(ent); | |
3000 | ||
6a9c308d | 3001 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
3002 | } |
3003 | ||
27c202ad | 3004 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 3005 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 3006 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 3007 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 3008 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 3009 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 3010 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 3011 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 3012 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
3013 | {"i915_gem_request", i915_gem_request_info, 0}, |
3014 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 3015 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 3016 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
3017 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
3018 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
3019 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 3020 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
3021 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
3022 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
3023 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
3024 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
3025 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 3026 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 3027 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 3028 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 3029 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 3030 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 3031 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 3032 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 3033 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 3034 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 3035 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 3036 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 3037 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 3038 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 3039 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 3040 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
ec013e7f | 3041 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 3042 | {"i915_pc8_status", i915_pc8_status, 0}, |
2017263e | 3043 | }; |
27c202ad | 3044 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 3045 | |
2b4bd0e0 | 3046 | static struct i915_debugfs_files { |
34b9674c DV |
3047 | const char *name; |
3048 | const struct file_operations *fops; | |
3049 | } i915_debugfs_files[] = { | |
3050 | {"i915_wedged", &i915_wedged_fops}, | |
3051 | {"i915_max_freq", &i915_max_freq_fops}, | |
3052 | {"i915_min_freq", &i915_min_freq_fops}, | |
3053 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
3054 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
3055 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
3056 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
3057 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
3058 | {"i915_error_state", &i915_error_state_fops}, | |
3059 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 3060 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
34b9674c DV |
3061 | }; |
3062 | ||
07144428 DL |
3063 | void intel_display_crc_init(struct drm_device *dev) |
3064 | { | |
3065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3066 | int i; | |
3067 | ||
3068 | for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) { | |
3069 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[i]; | |
3070 | ||
d538bbdf DL |
3071 | pipe_crc->opened = false; |
3072 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
3073 | init_waitqueue_head(&pipe_crc->wq); |
3074 | } | |
3075 | } | |
3076 | ||
27c202ad | 3077 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 3078 | { |
34b9674c | 3079 | int ret, i; |
f3cd474b | 3080 | |
6d794d42 | 3081 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
3082 | if (ret) |
3083 | return ret; | |
6a9c308d | 3084 | |
07144428 DL |
3085 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
3086 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
3087 | if (ret) | |
3088 | return ret; | |
3089 | } | |
3090 | ||
34b9674c DV |
3091 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3092 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
3093 | i915_debugfs_files[i].name, | |
3094 | i915_debugfs_files[i].fops); | |
3095 | if (ret) | |
3096 | return ret; | |
3097 | } | |
40633219 | 3098 | |
27c202ad BG |
3099 | return drm_debugfs_create_files(i915_debugfs_list, |
3100 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
3101 | minor->debugfs_root, minor); |
3102 | } | |
3103 | ||
27c202ad | 3104 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 3105 | { |
34b9674c DV |
3106 | int i; |
3107 | ||
27c202ad BG |
3108 | drm_debugfs_remove_files(i915_debugfs_list, |
3109 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 3110 | |
6d794d42 BW |
3111 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
3112 | 1, minor); | |
07144428 | 3113 | |
e309a997 | 3114 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
3115 | struct drm_info_list *info_list = |
3116 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
3117 | ||
3118 | drm_debugfs_remove_files(info_list, 1, minor); | |
3119 | } | |
3120 | ||
34b9674c DV |
3121 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3122 | struct drm_info_list *info_list = | |
3123 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
3124 | ||
3125 | drm_debugfs_remove_files(info_list, 1, minor); | |
3126 | } | |
2017263e BG |
3127 | } |
3128 | ||
3129 | #endif /* CONFIG_DEBUG_FS */ |