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drm/i915: use ERR_CAST instead of ERR_PTR/PTR_ERR
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
baaa5cfb 99 if (obj->pin_display)
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
481a3d43 126 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
37811fcc 127 &obj->base,
481a3d43 128 obj->active ? "*" : " ",
37811fcc
CW		 129 get_pin_flag(obj),
130 get_tiling_flag(obj),
1d693bcc 131 get_global_flag(obj),
a05a5862 132 obj->base.size / 1024,
37811fcc
CW		 133 obj->base.read_domains,
134 obj->base.write_domain,
97b2a6a1
JH		 135 i915_gem_request_get_seqno(obj->last_read_req),
136 i915_gem_request_get_seqno(obj->last_write_req),
137 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 138 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 139 obj->dirty ? " dirty" : "",
140 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
141 if (obj->base.name)
142 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 143 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 144 if (vma->pin_count > 0)
145 pin_count++;
ba0635ff
DC		 146 }
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
440fd528 157 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
fe14d5f4
TU		 158 vma->node.start, vma->node.size,
159 vma->ggtt_view.type);
1d693bcc 160 }
c1ad11fc 161 if (obj->stolen)
440fd528 162 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 163 if (obj->pin_display || obj->fault_mappable) {
6299f992 164 char s[3], *t = s;
30154650 165 if (obj->pin_display)
6299f992
CW		 166 *t++ = 'p';
167 if (obj->fault_mappable)
168 *t++ = 'f';
169 *t = '\0';
170 seq_printf(m, " (%s mappable)", s);
171 }
41c52415
JH		 172 if (obj->last_read_req != NULL)
173 seq_printf(m, " (%s)",
174 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 175 if (obj->frontbuffer_bits)
176 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 177}
178
273497e5 179static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 180{
ea0c76f8 181 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 182 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
183 seq_putc(m, ' ');
184}
185
433e12f7 186static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 187{
9f25d007 188 struct drm_info_node *node = m->private;
433e12f7
BG		 189 uintptr_t list = (uintptr_t) node->info_ent->data;
190 struct list_head *head;
2017263e 191 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 192 struct drm_i915_private *dev_priv = dev->dev_private;
193 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 194 struct i915_vma *vma;
8f2480fb
CW		 195 size_t total_obj_size, total_gtt_size;
196 int count, ret;
de227ef0
CW		 197
198 ret = mutex_lock_interruptible(&dev->struct_mutex);
199 if (ret)
200 return ret;
2017263e 201
ca191b13 202 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 203 switch (list) {
204 case ACTIVE_LIST:
267f0c90 205 seq_puts(m, "Active:\n");
5cef07e1 206 head = &vm->active_list;
433e12f7
BG		 207 break;
208 case INACTIVE_LIST:
267f0c90 209 seq_puts(m, "Inactive:\n");
5cef07e1 210 head = &vm->inactive_list;
433e12f7 211 break;
433e12f7 212 default:
de227ef0
CW		 213 mutex_unlock(&dev->struct_mutex);
214 return -EINVAL;
2017263e 215 }
2017263e 216
8f2480fb 217 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 218 list_for_each_entry(vma, head, mm_list) {
219 seq_printf(m, " ");
220 describe_obj(m, vma->obj);
221 seq_printf(m, "\n");
222 total_obj_size += vma->obj->base.size;
223 total_gtt_size += vma->node.size;
8f2480fb 224 count++;
2017263e 225 }
de227ef0 226 mutex_unlock(&dev->struct_mutex);
5e118f41 227
8f2480fb
CW		 228 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
229 count, total_obj_size, total_gtt_size);
2017263e
BG		 230 return 0;
231}
232
6d2b8885
CW		 233static int obj_rank_by_stolen(void *priv,
234 struct list_head *A, struct list_head *B)
235{
236 struct drm_i915_gem_object *a =
b25cb2f8 237 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 238 struct drm_i915_gem_object *b =
b25cb2f8 239 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 240
241 return a->stolen->start - b->stolen->start;
242}
243
244static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
245{
9f25d007 246 struct drm_info_node *node = m->private;
6d2b8885
CW		 247 struct drm_device *dev = node->minor->dev;
248 struct drm_i915_private *dev_priv = dev->dev_private;
249 struct drm_i915_gem_object *obj;
250 size_t total_obj_size, total_gtt_size;
251 LIST_HEAD(stolen);
252 int count, ret;
253
254 ret = mutex_lock_interruptible(&dev->struct_mutex);
255 if (ret)
256 return ret;
257
258 total_obj_size = total_gtt_size = count = 0;
259 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
260 if (obj->stolen == NULL)
261 continue;
262
b25cb2f8 263 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 264
265 total_obj_size += obj->base.size;
266 total_gtt_size += i915_gem_obj_ggtt_size(obj);
267 count++;
268 }
269 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
270 if (obj->stolen == NULL)
271 continue;
272
b25cb2f8 273 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 274
275 total_obj_size += obj->base.size;
276 count++;
277 }
278 list_sort(NULL, &stolen, obj_rank_by_stolen);
279 seq_puts(m, "Stolen:\n");
280 while (!list_empty(&stolen)) {
b25cb2f8 281 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 282 seq_puts(m, " ");
283 describe_obj(m, obj);
284 seq_putc(m, '\n');
b25cb2f8 285 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 286 }
287 mutex_unlock(&dev->struct_mutex);
288
289 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
290 count, total_obj_size, total_gtt_size);
291 return 0;
292}
293
6299f992
CW		 294#define count_objects(list, member) do { \
295 list_for_each_entry(obj, list, member) { \
f343c5f6 296 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 297 ++count; \
298 if (obj->map_and_fenceable) { \
f343c5f6 299 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 300 ++mappable_count; \
301 } \
302 } \
0206e353 303} while (0)
6299f992 304
2db8e9d6 305struct file_stats {
6313c204 306 struct drm_i915_file_private *file_priv;
2db8e9d6 307 int count;
c67a17e9
CW		 308 size_t total, unbound;
309 size_t global, shared;
310 size_t active, inactive;
2db8e9d6
CW		 311};
312
313static int per_file_stats(int id, void *ptr, void *data)
314{
315 struct drm_i915_gem_object *obj = ptr;
316 struct file_stats *stats = data;
6313c204 317 struct i915_vma *vma;
2db8e9d6
CW		 318
319 stats->count++;
320 stats->total += obj->base.size;
321
c67a17e9
CW		 322 if (obj->base.name || obj->base.dma_buf)
323 stats->shared += obj->base.size;
324
6313c204
CW		 325 if (USES_FULL_PPGTT(obj->base.dev)) {
326 list_for_each_entry(vma, &obj->vma_list, vma_link) {
327 struct i915_hw_ppgtt *ppgtt;
328
329 if (!drm_mm_node_allocated(&vma->node))
330 continue;
331
332 if (i915_is_ggtt(vma->vm)) {
333 stats->global += obj->base.size;
334 continue;
335 }
336
337 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 338 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 339 continue;
340
41c52415 341 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 342 stats->active += obj->base.size;
343 else
344 stats->inactive += obj->base.size;
345
346 return 0;
347 }
2db8e9d6 348 } else {
6313c204
CW		 349 if (i915_gem_obj_ggtt_bound(obj)) {
350 stats->global += obj->base.size;
41c52415 351 if (obj->active)
6313c204
CW		 352 stats->active += obj->base.size;
353 else
354 stats->inactive += obj->base.size;
355 return 0;
356 }
2db8e9d6
CW		 357 }
358
6313c204
CW		 359 if (!list_empty(&obj->global_list))
360 stats->unbound += obj->base.size;
361
2db8e9d6
CW		 362 return 0;
363}
364
b0da1b79
CW		 365#define print_file_stats(m, name, stats) do { \
366 if (stats.count) \
367 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
368 name, \
369 stats.count, \
370 stats.total, \
371 stats.active, \
372 stats.inactive, \
373 stats.global, \
374 stats.shared, \
375 stats.unbound); \
376} while (0)
493018dc
BV		 377
378static void print_batch_pool_stats(struct seq_file *m,
379 struct drm_i915_private *dev_priv)
380{
381 struct drm_i915_gem_object *obj;
382 struct file_stats stats;
06fbca71 383 struct intel_engine_cs *ring;
8d9d5744 384 int i, j;
493018dc
BV		 385
386 memset(&stats, 0, sizeof(stats));
387
06fbca71 388 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 389 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
390 list_for_each_entry(obj,
391 &ring->batch_pool.cache_list[j],
392 batch_pool_link)
393 per_file_stats(0, obj, &stats);
394 }
06fbca71 395 }
493018dc 396
b0da1b79 397 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 398}
399
ca191b13
BW		 400#define count_vmas(list, member) do { \
401 list_for_each_entry(vma, list, member) { \
402 size += i915_gem_obj_ggtt_size(vma->obj); \
403 ++count; \
404 if (vma->obj->map_and_fenceable) { \
405 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
406 ++mappable_count; \
407 } \
408 } \
409} while (0)
410
411static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 412{
9f25d007 413 struct drm_info_node *node = m->private;
73aa808f
CW		 414 struct drm_device *dev = node->minor->dev;
415 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 416 u32 count, mappable_count, purgeable_count;
417 size_t size, mappable_size, purgeable_size;
6299f992 418 struct drm_i915_gem_object *obj;
5cef07e1 419 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 420 struct drm_file *file;
ca191b13 421 struct i915_vma *vma;
73aa808f
CW		 422 int ret;
423
424 ret = mutex_lock_interruptible(&dev->struct_mutex);
425 if (ret)
426 return ret;
427
6299f992
CW		 428 seq_printf(m, "%u objects, %zu bytes\n",
429 dev_priv->mm.object_count,
430 dev_priv->mm.object_memory);
431
432 size = count = mappable_size = mappable_count = 0;
35c20a60 433 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 434 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
435 count, mappable_count, size, mappable_size);
436
437 size = count = mappable_size = mappable_count = 0;
ca191b13 438 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 439 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
440 count, mappable_count, size, mappable_size);
441
6299f992 442 size = count = mappable_size = mappable_count = 0;
ca191b13 443 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 444 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
445 count, mappable_count, size, mappable_size);
446
b7abb714 447 size = count = purgeable_size = purgeable_count = 0;
35c20a60 448 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 449 size += obj->base.size, ++count;
b7abb714
CW		 450 if (obj->madv == I915_MADV_DONTNEED)
451 purgeable_size += obj->base.size, ++purgeable_count;
452 }
6c085a72
CW		 453 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
454
6299f992 455 size = count = mappable_size = mappable_count = 0;
35c20a60 456 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 457 if (obj->fault_mappable) {
f343c5f6 458 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 459 ++count;
460 }
30154650 461 if (obj->pin_display) {
f343c5f6 462 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 463 ++mappable_count;
464 }
b7abb714
CW		 465 if (obj->madv == I915_MADV_DONTNEED) {
466 purgeable_size += obj->base.size;
467 ++purgeable_count;
468 }
6299f992 469 }
b7abb714
CW		 470 seq_printf(m, "%u purgeable objects, %zu bytes\n",
471 purgeable_count, purgeable_size);
6299f992
CW		 472 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
473 mappable_count, mappable_size);
474 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
475 count, size);
476
93d18799 477 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 478 dev_priv->gtt.base.total,
479 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 480
493018dc
BV		 481 seq_putc(m, '\n');
482 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 483 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
484 struct file_stats stats;
3ec2f427 485 struct task_struct *task;
2db8e9d6
CW		 486
487 memset(&stats, 0, sizeof(stats));
6313c204 488 stats.file_priv = file->driver_priv;
5b5ffff0 489 spin_lock(&file->table_lock);
2db8e9d6 490 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 491 spin_unlock(&file->table_lock);
3ec2f427
TH		 492 /*
493 * Although we have a valid reference on file->pid, that does
494 * not guarantee that the task_struct who called get_pid() is
495 * still alive (e.g. get_pid(current) => fork() => exit()).
496 * Therefore, we need to protect this ->comm access using RCU.
497 */
498 rcu_read_lock();
499 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 500 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 501 rcu_read_unlock();
2db8e9d6
CW		 502 }
503
73aa808f
CW		 504 mutex_unlock(&dev->struct_mutex);
505
506 return 0;
507}
508
aee56cff 509static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 510{
9f25d007 511 struct drm_info_node *node = m->private;
08c18323 512 struct drm_device *dev = node->minor->dev;
1b50247a 513 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 514 struct drm_i915_private *dev_priv = dev->dev_private;
515 struct drm_i915_gem_object *obj;
516 size_t total_obj_size, total_gtt_size;
517 int count, ret;
518
519 ret = mutex_lock_interruptible(&dev->struct_mutex);
520 if (ret)
521 return ret;
522
523 total_obj_size = total_gtt_size = count = 0;
35c20a60 524 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 525 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 526 continue;
527
267f0c90 528 seq_puts(m, " ");
08c18323 529 describe_obj(m, obj);
267f0c90 530 seq_putc(m, '\n');
08c18323 531 total_obj_size += obj->base.size;
f343c5f6 532 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 533 count++;
534 }
535
536 mutex_unlock(&dev->struct_mutex);
537
538 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
539 count, total_obj_size, total_gtt_size);
540
541 return 0;
542}
543
4e5359cd
SF		 544static int i915_gem_pageflip_info(struct seq_file *m, void *data)
545{
9f25d007 546 struct drm_info_node *node = m->private;
4e5359cd 547 struct drm_device *dev = node->minor->dev;
d6bbafa1 548 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 549 struct intel_crtc *crtc;
8a270ebf
DV		 550 int ret;
551
552 ret = mutex_lock_interruptible(&dev->struct_mutex);
553 if (ret)
554 return ret;
4e5359cd 555
d3fcc808 556 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 557 const char pipe = pipe_name(crtc->pipe);
558 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 559 struct intel_unpin_work *work;
560
5e2d7afc 561 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 562 work = crtc->unpin_work;
563 if (work == NULL) {
9db4a9c7 564 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 565 pipe, plane);
566 } else {
d6bbafa1
CW		 567 u32 addr;
568
e7d841ca 569 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 570 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 571 pipe, plane);
572 } else {
9db4a9c7 573 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 574 pipe, plane);
575 }
3a8a946e
DV		 576 if (work->flip_queued_req) {
577 struct intel_engine_cs *ring =
578 i915_gem_request_get_ring(work->flip_queued_req);
579
20e28fba 580 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 581 ring->name,
f06cc1b9 582 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 583 dev_priv->next_seqno,
3a8a946e 584 ring->get_seqno(ring, true),
1b5a433a 585 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 586 } else
587 seq_printf(m, "Flip not associated with any ring\n");
588 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
589 work->flip_queued_vblank,
590 work->flip_ready_vblank,
1e3feefd 591 drm_crtc_vblank_count(&crtc->base));
4e5359cd 592 if (work->enable_stall_check)
267f0c90 593 seq_puts(m, "Stall check enabled, ");
4e5359cd 594 else
267f0c90 595 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 596 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 597
d6bbafa1
CW		 598 if (INTEL_INFO(dev)->gen >= 4)
599 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
600 else
601 addr = I915_READ(DSPADDR(crtc->plane));
602 seq_printf(m, "Current scanout address 0x%08x\n", addr);
603
4e5359cd 604 if (work->pending_flip_obj) {
d6bbafa1
CW		 605 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
606 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 607 }
608 }
5e2d7afc 609 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 610 }
611
8a270ebf
DV		 612 mutex_unlock(&dev->struct_mutex);
613
4e5359cd
SF		 614 return 0;
615}
616
493018dc
BV		 617static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
618{
619 struct drm_info_node *node = m->private;
620 struct drm_device *dev = node->minor->dev;
621 struct drm_i915_private *dev_priv = dev->dev_private;
622 struct drm_i915_gem_object *obj;
06fbca71 623 struct intel_engine_cs *ring;
8d9d5744
CW		 624 int total = 0;
625 int ret, i, j;
493018dc
BV		 626
627 ret = mutex_lock_interruptible(&dev->struct_mutex);
628 if (ret)
629 return ret;
630
06fbca71 631 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 632 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
633 int count;
634
635 count = 0;
636 list_for_each_entry(obj,
637 &ring->batch_pool.cache_list[j],
638 batch_pool_link)
639 count++;
640 seq_printf(m, "%s cache[%d]: %d objects\n",
641 ring->name, j, count);
642
643 list_for_each_entry(obj,
644 &ring->batch_pool.cache_list[j],
645 batch_pool_link) {
646 seq_puts(m, " ");
647 describe_obj(m, obj);
648 seq_putc(m, '\n');
649 }
650
651 total += count;
06fbca71 652 }
493018dc
BV		 653 }
654
8d9d5744 655 seq_printf(m, "total: %d\n", total);
493018dc
BV		 656
657 mutex_unlock(&dev->struct_mutex);
658
659 return 0;
660}
661
2017263e
BG		 662static int i915_gem_request_info(struct seq_file *m, void *data)
663{
9f25d007 664 struct drm_info_node *node = m->private;
2017263e 665 struct drm_device *dev = node->minor->dev;
e277a1f8 666 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 667 struct intel_engine_cs *ring;
2d1070b2
CW		 668 struct drm_i915_gem_request *rq;
669 int ret, any, i;
de227ef0
CW		 670
671 ret = mutex_lock_interruptible(&dev->struct_mutex);
672 if (ret)
673 return ret;
2017263e 674
2d1070b2 675 any = 0;
a2c7f6fd 676 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 677 int count;
678
679 count = 0;
680 list_for_each_entry(rq, &ring->request_list, list)
681 count++;
682 if (count == 0)
a2c7f6fd
CW		 683 continue;
684
2d1070b2
CW		 685 seq_printf(m, "%s requests: %d\n", ring->name, count);
686 list_for_each_entry(rq, &ring->request_list, list) {
687 struct task_struct *task;
688
689 rcu_read_lock();
690 task = NULL;
691 if (rq->pid)
692 task = pid_task(rq->pid, PIDTYPE_PID);
693 seq_printf(m, " %x @ %d: %s [%d]\n",
694 rq->seqno,
695 (int) (jiffies - rq->emitted_jiffies),
696 task ? task->comm : "<unknown>",
697 task ? task->pid : -1);
698 rcu_read_unlock();
c2c347a9 699 }
2d1070b2
CW		 700
701 any++;
2017263e 702 }
de227ef0
CW		 703 mutex_unlock(&dev->struct_mutex);
704
2d1070b2 705 if (any == 0)
267f0c90 706 seq_puts(m, "No requests\n");
c2c347a9 707
2017263e
BG		 708 return 0;
709}
710
b2223497 711static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 712 struct intel_engine_cs *ring)
b2223497
CW		 713{
714 if (ring->get_seqno) {
20e28fba 715 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 716 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 717 }
718}
719
2017263e
BG		 720static int i915_gem_seqno_info(struct seq_file *m, void *data)
721{
9f25d007 722 struct drm_info_node *node = m->private;
2017263e 723 struct drm_device *dev = node->minor->dev;
e277a1f8 724 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 725 struct intel_engine_cs *ring;
1ec14ad3 726 int ret, i;
de227ef0
CW		 727
728 ret = mutex_lock_interruptible(&dev->struct_mutex);
729 if (ret)
730 return ret;
c8c8fb33 731 intel_runtime_pm_get(dev_priv);
2017263e 732
a2c7f6fd
CW		 733 for_each_ring(ring, dev_priv, i)
734 i915_ring_seqno_info(m, ring);
de227ef0 735
c8c8fb33 736 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 737 mutex_unlock(&dev->struct_mutex);
738
2017263e
BG		 739 return 0;
740}
741
742
743static int i915_interrupt_info(struct seq_file *m, void *data)
744{
9f25d007 745 struct drm_info_node *node = m->private;
2017263e 746 struct drm_device *dev = node->minor->dev;
e277a1f8 747 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 748 struct intel_engine_cs *ring;
9db4a9c7 749 int ret, i, pipe;
de227ef0
CW		 750
751 ret = mutex_lock_interruptible(&dev->struct_mutex);
752 if (ret)
753 return ret;
c8c8fb33 754 intel_runtime_pm_get(dev_priv);
2017263e 755
74e1ca8c 756 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 757 seq_printf(m, "Master Interrupt Control:\t%08x\n",
758 I915_READ(GEN8_MASTER_IRQ));
759
760 seq_printf(m, "Display IER:\t%08x\n",
761 I915_READ(VLV_IER));
762 seq_printf(m, "Display IIR:\t%08x\n",
763 I915_READ(VLV_IIR));
764 seq_printf(m, "Display IIR_RW:\t%08x\n",
765 I915_READ(VLV_IIR_RW));
766 seq_printf(m, "Display IMR:\t%08x\n",
767 I915_READ(VLV_IMR));
055e393f 768 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 769 seq_printf(m, "Pipe %c stat:\t%08x\n",
770 pipe_name(pipe),
771 I915_READ(PIPESTAT(pipe)));
772
773 seq_printf(m, "Port hotplug:\t%08x\n",
774 I915_READ(PORT_HOTPLUG_EN));
775 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
776 I915_READ(VLV_DPFLIPSTAT));
777 seq_printf(m, "DPINVGTT:\t%08x\n",
778 I915_READ(DPINVGTT));
779
780 for (i = 0; i < 4; i++) {
781 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
782 i, I915_READ(GEN8_GT_IMR(i)));
783 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
784 i, I915_READ(GEN8_GT_IIR(i)));
785 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
786 i, I915_READ(GEN8_GT_IER(i)));
787 }
788
789 seq_printf(m, "PCU interrupt mask:\t%08x\n",
790 I915_READ(GEN8_PCU_IMR));
791 seq_printf(m, "PCU interrupt identity:\t%08x\n",
792 I915_READ(GEN8_PCU_IIR));
793 seq_printf(m, "PCU interrupt enable:\t%08x\n",
794 I915_READ(GEN8_PCU_IER));
795 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 796 seq_printf(m, "Master Interrupt Control:\t%08x\n",
797 I915_READ(GEN8_MASTER_IRQ));
798
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
806 }
807
055e393f 808 for_each_pipe(dev_priv, pipe) {
f458ebbc 809 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 810 POWER_DOMAIN_PIPE(pipe))) {
811 seq_printf(m, "Pipe %c power disabled\n",
812 pipe_name(pipe));
813 continue;
814 }
a123f157 815 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 816 pipe_name(pipe),
817 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 818 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 819 pipe_name(pipe),
820 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 821 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 822 pipe_name(pipe),
823 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 824 }
825
826 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
827 I915_READ(GEN8_DE_PORT_IMR));
828 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
829 I915_READ(GEN8_DE_PORT_IIR));
830 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
831 I915_READ(GEN8_DE_PORT_IER));
832
833 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
834 I915_READ(GEN8_DE_MISC_IMR));
835 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
836 I915_READ(GEN8_DE_MISC_IIR));
837 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
838 I915_READ(GEN8_DE_MISC_IER));
839
840 seq_printf(m, "PCU interrupt mask:\t%08x\n",
841 I915_READ(GEN8_PCU_IMR));
842 seq_printf(m, "PCU interrupt identity:\t%08x\n",
843 I915_READ(GEN8_PCU_IIR));
844 seq_printf(m, "PCU interrupt enable:\t%08x\n",
845 I915_READ(GEN8_PCU_IER));
846 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 847 seq_printf(m, "Display IER:\t%08x\n",
848 I915_READ(VLV_IER));
849 seq_printf(m, "Display IIR:\t%08x\n",
850 I915_READ(VLV_IIR));
851 seq_printf(m, "Display IIR_RW:\t%08x\n",
852 I915_READ(VLV_IIR_RW));
853 seq_printf(m, "Display IMR:\t%08x\n",
854 I915_READ(VLV_IMR));
055e393f 855 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 856 seq_printf(m, "Pipe %c stat:\t%08x\n",
857 pipe_name(pipe),
858 I915_READ(PIPESTAT(pipe)));
859
860 seq_printf(m, "Master IER:\t%08x\n",
861 I915_READ(VLV_MASTER_IER));
862
863 seq_printf(m, "Render IER:\t%08x\n",
864 I915_READ(GTIER));
865 seq_printf(m, "Render IIR:\t%08x\n",
866 I915_READ(GTIIR));
867 seq_printf(m, "Render IMR:\t%08x\n",
868 I915_READ(GTIMR));
869
870 seq_printf(m, "PM IER:\t\t%08x\n",
871 I915_READ(GEN6_PMIER));
872 seq_printf(m, "PM IIR:\t\t%08x\n",
873 I915_READ(GEN6_PMIIR));
874 seq_printf(m, "PM IMR:\t\t%08x\n",
875 I915_READ(GEN6_PMIMR));
876
877 seq_printf(m, "Port hotplug:\t%08x\n",
878 I915_READ(PORT_HOTPLUG_EN));
879 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
880 I915_READ(VLV_DPFLIPSTAT));
881 seq_printf(m, "DPINVGTT:\t%08x\n",
882 I915_READ(DPINVGTT));
883
884 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 885 seq_printf(m, "Interrupt enable: %08x\n",
886 I915_READ(IER));
887 seq_printf(m, "Interrupt identity: %08x\n",
888 I915_READ(IIR));
889 seq_printf(m, "Interrupt mask: %08x\n",
890 I915_READ(IMR));
055e393f 891 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 892 seq_printf(m, "Pipe %c stat: %08x\n",
893 pipe_name(pipe),
894 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 895 } else {
896 seq_printf(m, "North Display Interrupt enable: %08x\n",
897 I915_READ(DEIER));
898 seq_printf(m, "North Display Interrupt identity: %08x\n",
899 I915_READ(DEIIR));
900 seq_printf(m, "North Display Interrupt mask: %08x\n",
901 I915_READ(DEIMR));
902 seq_printf(m, "South Display Interrupt enable: %08x\n",
903 I915_READ(SDEIER));
904 seq_printf(m, "South Display Interrupt identity: %08x\n",
905 I915_READ(SDEIIR));
906 seq_printf(m, "South Display Interrupt mask: %08x\n",
907 I915_READ(SDEIMR));
908 seq_printf(m, "Graphics Interrupt enable: %08x\n",
909 I915_READ(GTIER));
910 seq_printf(m, "Graphics Interrupt identity: %08x\n",
911 I915_READ(GTIIR));
912 seq_printf(m, "Graphics Interrupt mask: %08x\n",
913 I915_READ(GTIMR));
914 }
a2c7f6fd 915 for_each_ring(ring, dev_priv, i) {
a123f157 916 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 917 seq_printf(m,
918 "Graphics Interrupt mask (%s): %08x\n",
919 ring->name, I915_READ_IMR(ring));
9862e600 920 }
a2c7f6fd 921 i915_ring_seqno_info(m, ring);
9862e600 922 }
c8c8fb33 923 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 924 mutex_unlock(&dev->struct_mutex);
925
2017263e
BG		 926 return 0;
927}
928
a6172a80
CW		 929static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
930{
9f25d007 931 struct drm_info_node *node = m->private;
a6172a80 932 struct drm_device *dev = node->minor->dev;
e277a1f8 933 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 934 int i, ret;
935
936 ret = mutex_lock_interruptible(&dev->struct_mutex);
937 if (ret)
938 return ret;
a6172a80
CW		 939
940 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
941 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
942 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 943 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 944
6c085a72
CW		 945 seq_printf(m, "Fence %d, pin count = %d, object = ",
946 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 947 if (obj == NULL)
267f0c90 948 seq_puts(m, "unused");
c2c347a9 949 else
05394f39 950 describe_obj(m, obj);
267f0c90 951 seq_putc(m, '\n');
a6172a80
CW		 952 }
953
05394f39 954 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 955 return 0;
956}
957
2017263e
BG		 958static int i915_hws_info(struct seq_file *m, void *data)
959{
9f25d007 960 struct drm_info_node *node = m->private;
2017263e 961 struct drm_device *dev = node->minor->dev;
e277a1f8 962 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 963 struct intel_engine_cs *ring;
1a240d4d 964 const u32 *hws;
4066c0ae
CW		 965 int i;
966
1ec14ad3 967 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 968 hws = ring->status_page.page_addr;
2017263e
BG		 969 if (hws == NULL)
970 return 0;
971
972 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
973 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
974 i * 4,
975 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
976 }
977 return 0;
978}
979
d5442303
DV		 980static ssize_t
981i915_error_state_write(struct file *filp,
982 const char __user *ubuf,
983 size_t cnt,
984 loff_t *ppos)
985{
edc3d884 986 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 987 struct drm_device *dev = error_priv->dev;
22bcfc6a 988 int ret;
d5442303
DV		 989
990 DRM_DEBUG_DRIVER("Resetting error state\n");
991
22bcfc6a
DV		 992 ret = mutex_lock_interruptible(&dev->struct_mutex);
993 if (ret)
994 return ret;
995
d5442303
DV		 996 i915_destroy_error_state(dev);
997 mutex_unlock(&dev->struct_mutex);
998
999 return cnt;
1000}
1001
1002static int i915_error_state_open(struct inode *inode, struct file *file)
1003{
1004 struct drm_device *dev = inode->i_private;
d5442303 1005 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1006
1007 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1008 if (!error_priv)
1009 return -ENOMEM;
1010
1011 error_priv->dev = dev;
1012
95d5bfb3 1013 i915_error_state_get(dev, error_priv);
d5442303 1014
edc3d884
MK		 1015 file->private_data = error_priv;
1016
1017 return 0;
d5442303
DV		 1018}
1019
1020static int i915_error_state_release(struct inode *inode, struct file *file)
1021{
edc3d884 1022 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1023
95d5bfb3 1024 i915_error_state_put(error_priv);
d5442303
DV		 1025 kfree(error_priv);
1026
edc3d884
MK		 1027 return 0;
1028}
1029
4dc955f7
MK		 1030static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1031 size_t count, loff_t *pos)
1032{
1033 struct i915_error_state_file_priv *error_priv = file->private_data;
1034 struct drm_i915_error_state_buf error_str;
1035 loff_t tmp_pos = 0;
1036 ssize_t ret_count = 0;
1037 int ret;
1038
0a4cd7c8 1039 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1040 if (ret)
1041 return ret;
edc3d884 1042
fc16b48b 1043 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1044 if (ret)
1045 goto out;
1046
edc3d884
MK		 1047 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1048 error_str.buf,
1049 error_str.bytes);
1050
1051 if (ret_count < 0)
1052 ret = ret_count;
1053 else
1054 *pos = error_str.start + ret_count;
1055out:
4dc955f7 1056 i915_error_state_buf_release(&error_str);
edc3d884 1057 return ret ?: ret_count;
d5442303
DV		 1058}
1059
1060static const struct file_operations i915_error_state_fops = {
1061 .owner = THIS_MODULE,
1062 .open = i915_error_state_open,
edc3d884 1063 .read = i915_error_state_read,
d5442303
DV		 1064 .write = i915_error_state_write,
1065 .llseek = default_llseek,
1066 .release = i915_error_state_release,
1067};
1068
647416f9
KC		 1069static int
1070i915_next_seqno_get(void *data, u64 *val)
40633219 1071{
647416f9 1072 struct drm_device *dev = data;
e277a1f8 1073 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1074 int ret;
1075
1076 ret = mutex_lock_interruptible(&dev->struct_mutex);
1077 if (ret)
1078 return ret;
1079
647416f9 1080 *val = dev_priv->next_seqno;
40633219
MK		 1081 mutex_unlock(&dev->struct_mutex);
1082
647416f9 1083 return 0;
40633219
MK		 1084}
1085
647416f9
KC		 1086static int
1087i915_next_seqno_set(void *data, u64 val)
1088{
1089 struct drm_device *dev = data;
40633219
MK		 1090 int ret;
1091
40633219
MK		 1092 ret = mutex_lock_interruptible(&dev->struct_mutex);
1093 if (ret)
1094 return ret;
1095
e94fbaa8 1096 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1097 mutex_unlock(&dev->struct_mutex);
1098
647416f9 1099 return ret;
40633219
MK		 1100}
1101
647416f9
KC		 1102DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1103 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1104 "0x%llx\n");
40633219 1105
adb4bd12 1106static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1107{
9f25d007 1108 struct drm_info_node *node = m->private;
f97108d1 1109 struct drm_device *dev = node->minor->dev;
e277a1f8 1110 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1111 int ret = 0;
1112
1113 intel_runtime_pm_get(dev_priv);
3b8d8d91 1114
5c9669ce
TR		 1115 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1116
3b8d8d91
JB		 1117 if (IS_GEN5(dev)) {
1118 u16 rgvswctl = I915_READ16(MEMSWCTL);
1119 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1120
1121 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1122 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1123 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1124 MEMSTAT_VID_SHIFT);
1125 seq_printf(m, "Current P-state: %d\n",
1126 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2 1127 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
60260a5b 1128 IS_BROADWELL(dev) || IS_GEN9(dev)) {
3b8d8d91
JB		 1129 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1130 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1131 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1132 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1133 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1134 u32 rpupei, rpcurup, rpprevup;
1135 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1136 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1137 int max_freq;
1138
1139 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1140 ret = mutex_lock_interruptible(&dev->struct_mutex);
1141 if (ret)
c8c8fb33 1142 goto out;
d1ebd816 1143
59bad947 1144 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1145
8e8c06cd 1146 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1147 if (IS_GEN9(dev))
1148 reqf >>= 23;
1149 else {
1150 reqf &= ~GEN6_TURBO_DISABLE;
1151 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1152 reqf >>= 24;
1153 else
1154 reqf >>= 25;
1155 }
7c59a9c1 1156 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1157
0d8f9491
CW		 1158 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1159 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1160 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1161
ccab5c82
JB		 1162 rpstat = I915_READ(GEN6_RPSTAT1);
1163 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1164 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1165 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1166 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1167 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1168 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1169 if (IS_GEN9(dev))
1170 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1171 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1172 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1173 else
1174 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1175 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1176
59bad947 1177 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1178 mutex_unlock(&dev->struct_mutex);
1179
9dd3c605
PZ		 1180 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1181 pm_ier = I915_READ(GEN6_PMIER);
1182 pm_imr = I915_READ(GEN6_PMIMR);
1183 pm_isr = I915_READ(GEN6_PMISR);
1184 pm_iir = I915_READ(GEN6_PMIIR);
1185 pm_mask = I915_READ(GEN6_PMINTRMSK);
1186 } else {
1187 pm_ier = I915_READ(GEN8_GT_IER(2));
1188 pm_imr = I915_READ(GEN8_GT_IMR(2));
1189 pm_isr = I915_READ(GEN8_GT_ISR(2));
1190 pm_iir = I915_READ(GEN8_GT_IIR(2));
1191 pm_mask = I915_READ(GEN6_PMINTRMSK);
1192 }
0d8f9491 1193 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1194 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1195 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1196 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1197 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1198 seq_printf(m, "Render p-state VID: %d\n",
1199 gt_perf_status & 0xff);
1200 seq_printf(m, "Render p-state limit: %d\n",
1201 rp_state_limits & 0xff);
0d8f9491
CW		 1202 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1203 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1204 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1205 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1206 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1207 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1208 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1209 GEN6_CURICONT_MASK);
1210 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1211 GEN6_CURBSYTAVG_MASK);
1212 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1213 GEN6_CURBSYTAVG_MASK);
1214 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1215 GEN6_CURIAVG_MASK);
1216 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1217 GEN6_CURBSYTAVG_MASK);
1218 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1219 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1220
1221 max_freq = (rp_state_cap & 0xff0000) >> 16;
60260a5b 1222 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1223 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1224 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1225
1226 max_freq = (rp_state_cap & 0xff00) >> 8;
60260a5b 1227 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1228 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1229 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1230
1231 max_freq = rp_state_cap & 0xff;
60260a5b 1232 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1233 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1234 intel_gpu_freq(dev_priv, max_freq));
31c77388
BW		 1235
1236 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1237 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff
CW		 1238
1239 seq_printf(m, "Idle freq: %d MHz\n",
1240 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
0a073b84 1241 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1242 u32 freq_sts;
0a073b84 1243
259bd5d4 1244 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1245 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1246 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1247 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1248
0a073b84 1249 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1250 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1251
0a073b84 1252 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1253 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1254
aed242ff
CW		 1255 seq_printf(m, "idle GPU freq: %d MHz\n",
1256 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1257
7c59a9c1
VS		 1258 seq_printf(m,
1259 "efficient (RPe) frequency: %d MHz\n",
1260 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1261
1262 seq_printf(m, "current GPU freq: %d MHz\n",
7c59a9c1 1263 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1264 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1265 } else {
267f0c90 1266 seq_puts(m, "no P-state info available\n");
3b8d8d91 1267 }
f97108d1 1268
c8c8fb33
PZ		 1269out:
1270 intel_runtime_pm_put(dev_priv);
1271 return ret;
f97108d1
JB		 1272}
1273
f654449a
CW		 1274static int i915_hangcheck_info(struct seq_file *m, void *unused)
1275{
1276 struct drm_info_node *node = m->private;
ebbc7546
MK		 1277 struct drm_device *dev = node->minor->dev;
1278 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1279 struct intel_engine_cs *ring;
ebbc7546
MK		 1280 u64 acthd[I915_NUM_RINGS];
1281 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1282 int i;
1283
1284 if (!i915.enable_hangcheck) {
1285 seq_printf(m, "Hangcheck disabled\n");
1286 return 0;
1287 }
1288
ebbc7546
MK		 1289 intel_runtime_pm_get(dev_priv);
1290
1291 for_each_ring(ring, dev_priv, i) {
1292 seqno[i] = ring->get_seqno(ring, false);
1293 acthd[i] = intel_ring_get_active_head(ring);
1294 }
1295
1296 intel_runtime_pm_put(dev_priv);
1297
f654449a
CW		 1298 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1299 seq_printf(m, "Hangcheck active, fires in %dms\n",
1300 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1301 jiffies));
1302 } else
1303 seq_printf(m, "Hangcheck inactive\n");
1304
1305 for_each_ring(ring, dev_priv, i) {
1306 seq_printf(m, "%s:\n", ring->name);
1307 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1308 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1309 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1310 (long long)ring->hangcheck.acthd,
ebbc7546 1311 (long long)acthd[i]);
f654449a
CW		 1312 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1313 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1314 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1315 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1316 }
1317
1318 return 0;
1319}
1320
4d85529d 1321static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1322{
9f25d007 1323 struct drm_info_node *node = m->private;
f97108d1 1324 struct drm_device *dev = node->minor->dev;
e277a1f8 1325 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1326 u32 rgvmodectl, rstdbyctl;
1327 u16 crstandvid;
1328 int ret;
1329
1330 ret = mutex_lock_interruptible(&dev->struct_mutex);
1331 if (ret)
1332 return ret;
c8c8fb33 1333 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1334
1335 rgvmodectl = I915_READ(MEMMODECTL);
1336 rstdbyctl = I915_READ(RSTDBYCTL);
1337 crstandvid = I915_READ16(CRSTANDVID);
1338
c8c8fb33 1339 intel_runtime_pm_put(dev_priv);
616fdb5a 1340 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1341
1342 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1343 "yes" : "no");
1344 seq_printf(m, "Boost freq: %d\n",
1345 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1346 MEMMODE_BOOST_FREQ_SHIFT);
1347 seq_printf(m, "HW control enabled: %s\n",
1348 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1349 seq_printf(m, "SW control enabled: %s\n",
1350 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1351 seq_printf(m, "Gated voltage change: %s\n",
1352 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1353 seq_printf(m, "Starting frequency: P%d\n",
1354 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1355 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1356 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1357 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1358 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1359 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1360 seq_printf(m, "Render standby enabled: %s\n",
1361 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1362 seq_puts(m, "Current RS state: ");
88271da3
JB		 1363 switch (rstdbyctl & RSX_STATUS_MASK) {
1364 case RSX_STATUS_ON:
267f0c90 1365 seq_puts(m, "on\n");
88271da3
JB		 1366 break;
1367 case RSX_STATUS_RC1:
267f0c90 1368 seq_puts(m, "RC1\n");
88271da3
JB		 1369 break;
1370 case RSX_STATUS_RC1E:
267f0c90 1371 seq_puts(m, "RC1E\n");
88271da3
JB		 1372 break;
1373 case RSX_STATUS_RS1:
267f0c90 1374 seq_puts(m, "RS1\n");
88271da3
JB		 1375 break;
1376 case RSX_STATUS_RS2:
267f0c90 1377 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1378 break;
1379 case RSX_STATUS_RS3:
267f0c90 1380 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1381 break;
1382 default:
267f0c90 1383 seq_puts(m, "unknown\n");
88271da3
JB		 1384 break;
1385 }
f97108d1
JB		 1386
1387 return 0;
1388}
1389
f65367b5 1390static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1391{
b2cff0db
CW		 1392 struct drm_info_node *node = m->private;
1393 struct drm_device *dev = node->minor->dev;
1394 struct drm_i915_private *dev_priv = dev->dev_private;
1395 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1396 int i;
1397
1398 spin_lock_irq(&dev_priv->uncore.lock);
1399 for_each_fw_domain(fw_domain, dev_priv, i) {
1400 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1401 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1402 fw_domain->wake_count);
1403 }
1404 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1405
b2cff0db
CW		 1406 return 0;
1407}
1408
1409static int vlv_drpc_info(struct seq_file *m)
1410{
9f25d007 1411 struct drm_info_node *node = m->private;
669ab5aa
D		 1412 struct drm_device *dev = node->minor->dev;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1414 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1415
d46c0517
ID		 1416 intel_runtime_pm_get(dev_priv);
1417
6b312cd3 1418 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1419 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1420 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1421
d46c0517
ID		 1422 intel_runtime_pm_put(dev_priv);
1423
669ab5aa
D		 1424 seq_printf(m, "Video Turbo Mode: %s\n",
1425 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1426 seq_printf(m, "Turbo enabled: %s\n",
1427 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1428 seq_printf(m, "HW control enabled: %s\n",
1429 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1430 seq_printf(m, "SW control enabled: %s\n",
1431 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1432 GEN6_RP_MEDIA_SW_MODE));
1433 seq_printf(m, "RC6 Enabled: %s\n",
1434 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1435 GEN6_RC_CTL_EI_MODE(1))));
1436 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1437 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1438 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1439 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1440
9cc19be5
ID		 1441 seq_printf(m, "Render RC6 residency since boot: %u\n",
1442 I915_READ(VLV_GT_RENDER_RC6));
1443 seq_printf(m, "Media RC6 residency since boot: %u\n",
1444 I915_READ(VLV_GT_MEDIA_RC6));
1445
f65367b5 1446 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1447}
1448
4d85529d
BW		 1449static int gen6_drpc_info(struct seq_file *m)
1450{
9f25d007 1451 struct drm_info_node *node = m->private;
4d85529d
BW		 1452 struct drm_device *dev = node->minor->dev;
1453 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1454 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1455 unsigned forcewake_count;
aee56cff 1456 int count = 0, ret;
4d85529d
BW		 1457
1458 ret = mutex_lock_interruptible(&dev->struct_mutex);
1459 if (ret)
1460 return ret;
c8c8fb33 1461 intel_runtime_pm_get(dev_priv);
4d85529d 1462
907b28c5 1463 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1464 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1465 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1466
1467 if (forcewake_count) {
267f0c90
DL		 1468 seq_puts(m, "RC information inaccurate because somebody "
1469 "holds a forcewake reference \n");
4d85529d
BW		 1470 } else {
1471 /* NB: we cannot use forcewake, else we read the wrong values */
1472 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1473 udelay(10);
1474 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1475 }
1476
1477 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1478 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1479
1480 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1481 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1482 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1483 mutex_lock(&dev_priv->rps.hw_lock);
1484 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1485 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1486
c8c8fb33
PZ		 1487 intel_runtime_pm_put(dev_priv);
1488
4d85529d
BW		 1489 seq_printf(m, "Video Turbo Mode: %s\n",
1490 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1491 seq_printf(m, "HW control enabled: %s\n",
1492 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1493 seq_printf(m, "SW control enabled: %s\n",
1494 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1495 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1496 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1497 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1498 seq_printf(m, "RC6 Enabled: %s\n",
1499 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1500 seq_printf(m, "Deep RC6 Enabled: %s\n",
1501 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1502 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1503 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1504 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1505 switch (gt_core_status & GEN6_RCn_MASK) {
1506 case GEN6_RC0:
1507 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1508 seq_puts(m, "Core Power Down\n");
4d85529d 1509 else
267f0c90 1510 seq_puts(m, "on\n");
4d85529d
BW		 1511 break;
1512 case GEN6_RC3:
267f0c90 1513 seq_puts(m, "RC3\n");
4d85529d
BW		 1514 break;
1515 case GEN6_RC6:
267f0c90 1516 seq_puts(m, "RC6\n");
4d85529d
BW		 1517 break;
1518 case GEN6_RC7:
267f0c90 1519 seq_puts(m, "RC7\n");
4d85529d
BW		 1520 break;
1521 default:
267f0c90 1522 seq_puts(m, "Unknown\n");
4d85529d
BW		 1523 break;
1524 }
1525
1526 seq_printf(m, "Core Power Down: %s\n",
1527 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1528
1529 /* Not exactly sure what this is */
1530 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1531 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1532 seq_printf(m, "RC6 residency since boot: %u\n",
1533 I915_READ(GEN6_GT_GFX_RC6));
1534 seq_printf(m, "RC6+ residency since boot: %u\n",
1535 I915_READ(GEN6_GT_GFX_RC6p));
1536 seq_printf(m, "RC6++ residency since boot: %u\n",
1537 I915_READ(GEN6_GT_GFX_RC6pp));
1538
ecd8faea
BW		 1539 seq_printf(m, "RC6 voltage: %dmV\n",
1540 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1541 seq_printf(m, "RC6+ voltage: %dmV\n",
1542 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1543 seq_printf(m, "RC6++ voltage: %dmV\n",
1544 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1545 return 0;
1546}
1547
1548static int i915_drpc_info(struct seq_file *m, void *unused)
1549{
9f25d007 1550 struct drm_info_node *node = m->private;
4d85529d
BW		 1551 struct drm_device *dev = node->minor->dev;
1552
669ab5aa
D		 1553 if (IS_VALLEYVIEW(dev))
1554 return vlv_drpc_info(m);
ac66cf4b 1555 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1556 return gen6_drpc_info(m);
1557 else
1558 return ironlake_drpc_info(m);
1559}
1560
b5e50c3f
JB		 1561static int i915_fbc_status(struct seq_file *m, void *unused)
1562{
9f25d007 1563 struct drm_info_node *node = m->private;
b5e50c3f 1564 struct drm_device *dev = node->minor->dev;
e277a1f8 1565 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1566
3a77c4c4 1567 if (!HAS_FBC(dev)) {
267f0c90 1568 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1569 return 0;
1570 }
1571
36623ef8
PZ		 1572 intel_runtime_pm_get(dev_priv);
1573
ee5382ae 1574 if (intel_fbc_enabled(dev)) {
267f0c90 1575 seq_puts(m, "FBC enabled\n");
b5e50c3f 1576 } else {
267f0c90 1577 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1578 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1579 case FBC_OK:
1580 seq_puts(m, "FBC actived, but currently disabled in hardware");
1581 break;
1582 case FBC_UNSUPPORTED:
1583 seq_puts(m, "unsupported by this chipset");
1584 break;
bed4a673 1585 case FBC_NO_OUTPUT:
267f0c90 1586 seq_puts(m, "no outputs");
bed4a673 1587 break;
b5e50c3f 1588 case FBC_STOLEN_TOO_SMALL:
267f0c90 1589 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1590 break;
1591 case FBC_UNSUPPORTED_MODE:
267f0c90 1592 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1593 break;
1594 case FBC_MODE_TOO_LARGE:
267f0c90 1595 seq_puts(m, "mode too large");
b5e50c3f
JB		 1596 break;
1597 case FBC_BAD_PLANE:
267f0c90 1598 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1599 break;
1600 case FBC_NOT_TILED:
267f0c90 1601 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1602 break;
9c928d16 1603 case FBC_MULTIPLE_PIPES:
267f0c90 1604 seq_puts(m, "multiple pipes are enabled");
9c928d16 1605 break;
c1a9f047 1606 case FBC_MODULE_PARAM:
267f0c90 1607 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1608 break;
8a5729a3 1609 case FBC_CHIP_DEFAULT:
267f0c90 1610 seq_puts(m, "disabled per chip default");
8a5729a3 1611 break;
b5e50c3f 1612 default:
267f0c90 1613 seq_puts(m, "unknown reason");
b5e50c3f 1614 }
267f0c90 1615 seq_putc(m, '\n');
b5e50c3f 1616 }
36623ef8
PZ		 1617
1618 intel_runtime_pm_put(dev_priv);
1619
b5e50c3f
JB		 1620 return 0;
1621}
1622
da46f936
RV		 1623static int i915_fbc_fc_get(void *data, u64 *val)
1624{
1625 struct drm_device *dev = data;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627
1628 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1629 return -ENODEV;
1630
1631 drm_modeset_lock_all(dev);
1632 *val = dev_priv->fbc.false_color;
1633 drm_modeset_unlock_all(dev);
1634
1635 return 0;
1636}
1637
1638static int i915_fbc_fc_set(void *data, u64 val)
1639{
1640 struct drm_device *dev = data;
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 u32 reg;
1643
1644 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1645 return -ENODEV;
1646
1647 drm_modeset_lock_all(dev);
1648
1649 reg = I915_READ(ILK_DPFC_CONTROL);
1650 dev_priv->fbc.false_color = val;
1651
1652 I915_WRITE(ILK_DPFC_CONTROL, val ?
1653 (reg | FBC_CTL_FALSE_COLOR) :
1654 (reg & ~FBC_CTL_FALSE_COLOR));
1655
1656 drm_modeset_unlock_all(dev);
1657 return 0;
1658}
1659
1660DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1661 i915_fbc_fc_get, i915_fbc_fc_set,
1662 "%llu\n");
1663
92d44621
PZ		 1664static int i915_ips_status(struct seq_file *m, void *unused)
1665{
9f25d007 1666 struct drm_info_node *node = m->private;
92d44621
PZ		 1667 struct drm_device *dev = node->minor->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669
f5adf94e 1670 if (!HAS_IPS(dev)) {
92d44621
PZ		 1671 seq_puts(m, "not supported\n");
1672 return 0;
1673 }
1674
36623ef8
PZ		 1675 intel_runtime_pm_get(dev_priv);
1676
0eaa53f0
RV		 1677 seq_printf(m, "Enabled by kernel parameter: %s\n",
1678 yesno(i915.enable_ips));
1679
1680 if (INTEL_INFO(dev)->gen >= 8) {
1681 seq_puts(m, "Currently: unknown\n");
1682 } else {
1683 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1684 seq_puts(m, "Currently: enabled\n");
1685 else
1686 seq_puts(m, "Currently: disabled\n");
1687 }
92d44621 1688
36623ef8
PZ		 1689 intel_runtime_pm_put(dev_priv);
1690
92d44621
PZ		 1691 return 0;
1692}
1693
4a9bef37
JB		 1694static int i915_sr_status(struct seq_file *m, void *unused)
1695{
9f25d007 1696 struct drm_info_node *node = m->private;
4a9bef37 1697 struct drm_device *dev = node->minor->dev;
e277a1f8 1698 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1699 bool sr_enabled = false;
1700
36623ef8
PZ		 1701 intel_runtime_pm_get(dev_priv);
1702
1398261a 1703 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1704 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1705 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1706 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1707 else if (IS_I915GM(dev))
1708 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1709 else if (IS_PINEVIEW(dev))
1710 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1711
36623ef8
PZ		 1712 intel_runtime_pm_put(dev_priv);
1713
5ba2aaaa
CW		 1714 seq_printf(m, "self-refresh: %s\n",
1715 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1716
1717 return 0;
1718}
1719
7648fa99
JB		 1720static int i915_emon_status(struct seq_file *m, void *unused)
1721{
9f25d007 1722 struct drm_info_node *node = m->private;
7648fa99 1723 struct drm_device *dev = node->minor->dev;
e277a1f8 1724 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1725 unsigned long temp, chipset, gfx;
de227ef0
CW		 1726 int ret;
1727
582be6b4
CW		 1728 if (!IS_GEN5(dev))
1729 return -ENODEV;
1730
de227ef0
CW		 1731 ret = mutex_lock_interruptible(&dev->struct_mutex);
1732 if (ret)
1733 return ret;
7648fa99
JB		 1734
1735 temp = i915_mch_val(dev_priv);
1736 chipset = i915_chipset_val(dev_priv);
1737 gfx = i915_gfx_val(dev_priv);
de227ef0 1738 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1739
1740 seq_printf(m, "GMCH temp: %ld\n", temp);
1741 seq_printf(m, "Chipset power: %ld\n", chipset);
1742 seq_printf(m, "GFX power: %ld\n", gfx);
1743 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1744
1745 return 0;
1746}
1747
23b2f8bb
JB		 1748static int i915_ring_freq_table(struct seq_file *m, void *unused)
1749{
9f25d007 1750 struct drm_info_node *node = m->private;
23b2f8bb 1751 struct drm_device *dev = node->minor->dev;
e277a1f8 1752 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1753 int ret = 0;
23b2f8bb
JB		 1754 int gpu_freq, ia_freq;
1755
1c70c0ce 1756 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1757 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1758 return 0;
1759 }
1760
5bfa0199
PZ		 1761 intel_runtime_pm_get(dev_priv);
1762
5c9669ce
TR		 1763 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1764
4fc688ce 1765 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1766 if (ret)
5bfa0199 1767 goto out;
23b2f8bb 1768
267f0c90 1769 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1770
b39fb297
BW		 1771 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1772 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1773 gpu_freq++) {
42c0526c
BW		 1774 ia_freq = gpu_freq;
1775 sandybridge_pcode_read(dev_priv,
1776 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1777 &ia_freq);
3ebecd07 1778 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
7c59a9c1 1779 intel_gpu_freq(dev_priv, gpu_freq),
3ebecd07
CW		 1780 ((ia_freq >> 0) & 0xff) * 100,
1781 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1782 }
1783
4fc688ce 1784 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1785
5bfa0199
PZ		 1786out:
1787 intel_runtime_pm_put(dev_priv);
1788 return ret;
23b2f8bb
JB		 1789}
1790
44834a67
CW		 1791static int i915_opregion(struct seq_file *m, void *unused)
1792{
9f25d007 1793 struct drm_info_node *node = m->private;
44834a67 1794 struct drm_device *dev = node->minor->dev;
e277a1f8 1795 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1796 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1797 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1798 int ret;
1799
0d38f009
DV		 1800 if (data == NULL)
1801 return -ENOMEM;
1802
44834a67
CW		 1803 ret = mutex_lock_interruptible(&dev->struct_mutex);
1804 if (ret)
0d38f009 1805 goto out;
44834a67 1806
0d38f009
DV		 1807 if (opregion->header) {
1808 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1809 seq_write(m, data, OPREGION_SIZE);
1810 }
44834a67
CW		 1811
1812 mutex_unlock(&dev->struct_mutex);
1813
0d38f009
DV		 1814out:
1815 kfree(data);
44834a67
CW		 1816 return 0;
1817}
1818
37811fcc
CW		 1819static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1820{
9f25d007 1821 struct drm_info_node *node = m->private;
37811fcc 1822 struct drm_device *dev = node->minor->dev;
4520f53a 1823 struct intel_fbdev *ifbdev = NULL;
37811fcc 1824 struct intel_framebuffer *fb;
37811fcc 1825
4520f53a
DV		 1826#ifdef CONFIG_DRM_I915_FBDEV
1827 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1828
1829 ifbdev = dev_priv->fbdev;
1830 fb = to_intel_framebuffer(ifbdev->helper.fb);
1831
c1ca506d 1832 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1833 fb->base.width,
1834 fb->base.height,
1835 fb->base.depth,
623f9783 1836 fb->base.bits_per_pixel,
c1ca506d 1837 fb->base.modifier[0],
623f9783 1838 atomic_read(&fb->base.refcount.refcount));
05394f39 1839 describe_obj(m, fb->obj);
267f0c90 1840 seq_putc(m, '\n');
4520f53a 1841#endif
37811fcc 1842
4b096ac1 1843 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1844 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1845 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1846 continue;
1847
c1ca506d 1848 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1849 fb->base.width,
1850 fb->base.height,
1851 fb->base.depth,
623f9783 1852 fb->base.bits_per_pixel,
c1ca506d 1853 fb->base.modifier[0],
623f9783 1854 atomic_read(&fb->base.refcount.refcount));
05394f39 1855 describe_obj(m, fb->obj);
267f0c90 1856 seq_putc(m, '\n');
37811fcc 1857 }
4b096ac1 1858 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1859
1860 return 0;
1861}
1862
c9fe99bd
OM		 1863static void describe_ctx_ringbuf(struct seq_file *m,
1864 struct intel_ringbuffer *ringbuf)
1865{
1866 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1867 ringbuf->space, ringbuf->head, ringbuf->tail,
1868 ringbuf->last_retired_head);
1869}
1870
e76d3630
BW		 1871static int i915_context_status(struct seq_file *m, void *unused)
1872{
9f25d007 1873 struct drm_info_node *node = m->private;
e76d3630 1874 struct drm_device *dev = node->minor->dev;
e277a1f8 1875 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1876 struct intel_engine_cs *ring;
273497e5 1877 struct intel_context *ctx;
a168c293 1878 int ret, i;
e76d3630 1879
f3d28878 1880 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1881 if (ret)
1882 return ret;
1883
a33afea5 1884 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1885 if (!i915.enable_execlists &&
1886 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1887 continue;
1888
a33afea5 1889 seq_puts(m, "HW context ");
3ccfd19d 1890 describe_ctx(m, ctx);
c9fe99bd 1891 for_each_ring(ring, dev_priv, i) {
a33afea5 1892 if (ring->default_context == ctx)
c9fe99bd
OM		 1893 seq_printf(m, "(default context %s) ",
1894 ring->name);
1895 }
1896
1897 if (i915.enable_execlists) {
1898 seq_putc(m, '\n');
1899 for_each_ring(ring, dev_priv, i) {
1900 struct drm_i915_gem_object *ctx_obj =
1901 ctx->engine[i].state;
1902 struct intel_ringbuffer *ringbuf =
1903 ctx->engine[i].ringbuf;
1904
1905 seq_printf(m, "%s: ", ring->name);
1906 if (ctx_obj)
1907 describe_obj(m, ctx_obj);
1908 if (ringbuf)
1909 describe_ctx_ringbuf(m, ringbuf);
1910 seq_putc(m, '\n');
1911 }
1912 } else {
1913 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1914 }
a33afea5 1915
a33afea5 1916 seq_putc(m, '\n');
a168c293
BW		 1917 }
1918
f3d28878 1919 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1920
1921 return 0;
1922}
1923
064ca1d2
TD		 1924static void i915_dump_lrc_obj(struct seq_file *m,
1925 struct intel_engine_cs *ring,
1926 struct drm_i915_gem_object *ctx_obj)
1927{
1928 struct page *page;
1929 uint32_t *reg_state;
1930 int j;
1931 unsigned long ggtt_offset = 0;
1932
1933 if (ctx_obj == NULL) {
1934 seq_printf(m, "Context on %s with no gem object\n",
1935 ring->name);
1936 return;
1937 }
1938
1939 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1940 intel_execlists_ctx_id(ctx_obj));
1941
1942 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1943 seq_puts(m, "\tNot bound in GGTT\n");
1944 else
1945 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1946
1947 if (i915_gem_object_get_pages(ctx_obj)) {
1948 seq_puts(m, "\tFailed to get pages for context object\n");
1949 return;
1950 }
1951
1952 page = i915_gem_object_get_page(ctx_obj, 1);
1953 if (!WARN_ON(page == NULL)) {
1954 reg_state = kmap_atomic(page);
1955
1956 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1957 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1958 ggtt_offset + 4096 + (j * 4),
1959 reg_state[j], reg_state[j + 1],
1960 reg_state[j + 2], reg_state[j + 3]);
1961 }
1962 kunmap_atomic(reg_state);
1963 }
1964
1965 seq_putc(m, '\n');
1966}
1967
c0ab1ae9
BW		 1968static int i915_dump_lrc(struct seq_file *m, void *unused)
1969{
1970 struct drm_info_node *node = (struct drm_info_node *) m->private;
1971 struct drm_device *dev = node->minor->dev;
1972 struct drm_i915_private *dev_priv = dev->dev_private;
1973 struct intel_engine_cs *ring;
1974 struct intel_context *ctx;
1975 int ret, i;
1976
1977 if (!i915.enable_execlists) {
1978 seq_printf(m, "Logical Ring Contexts are disabled\n");
1979 return 0;
1980 }
1981
1982 ret = mutex_lock_interruptible(&dev->struct_mutex);
1983 if (ret)
1984 return ret;
1985
1986 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1987 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 1988 if (ring->default_context != ctx)
1989 i915_dump_lrc_obj(m, ring,
1990 ctx->engine[i].state);
c0ab1ae9
BW		 1991 }
1992 }
1993
1994 mutex_unlock(&dev->struct_mutex);
1995
1996 return 0;
1997}
1998
4ba70e44
OM		 1999static int i915_execlists(struct seq_file *m, void *data)
2000{
2001 struct drm_info_node *node = (struct drm_info_node *)m->private;
2002 struct drm_device *dev = node->minor->dev;
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004 struct intel_engine_cs *ring;
2005 u32 status_pointer;
2006 u8 read_pointer;
2007 u8 write_pointer;
2008 u32 status;
2009 u32 ctx_id;
2010 struct list_head *cursor;
2011 int ring_id, i;
2012 int ret;
2013
2014 if (!i915.enable_execlists) {
2015 seq_puts(m, "Logical Ring Contexts are disabled\n");
2016 return 0;
2017 }
2018
2019 ret = mutex_lock_interruptible(&dev->struct_mutex);
2020 if (ret)
2021 return ret;
2022
fc0412ec
MT		 2023 intel_runtime_pm_get(dev_priv);
2024
4ba70e44 2025 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2026 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2027 int count = 0;
2028 unsigned long flags;
2029
2030 seq_printf(m, "%s\n", ring->name);
2031
2032 status = I915_READ(RING_EXECLIST_STATUS(ring));
2033 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2034 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2035 status, ctx_id);
2036
2037 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2038 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2039
2040 read_pointer = ring->next_context_status_buffer;
2041 write_pointer = status_pointer & 0x07;
2042 if (read_pointer > write_pointer)
2043 write_pointer += 6;
2044 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2045 read_pointer, write_pointer);
2046
2047 for (i = 0; i < 6; i++) {
2048 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2049 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2050
2051 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2052 i, status, ctx_id);
2053 }
2054
2055 spin_lock_irqsave(&ring->execlist_lock, flags);
2056 list_for_each(cursor, &ring->execlist_queue)
2057 count++;
2058 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2059 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2060 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2061
2062 seq_printf(m, "\t%d requests in queue\n", count);
2063 if (head_req) {
2064 struct drm_i915_gem_object *ctx_obj;
2065
6d3d8274 2066 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2067 seq_printf(m, "\tHead request id: %u\n",
2068 intel_execlists_ctx_id(ctx_obj));
2069 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2070 head_req->tail);
4ba70e44
OM		 2071 }
2072
2073 seq_putc(m, '\n');
2074 }
2075
fc0412ec 2076 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2077 mutex_unlock(&dev->struct_mutex);
2078
2079 return 0;
2080}
2081
ea16a3cd
DV		 2082static const char *swizzle_string(unsigned swizzle)
2083{
aee56cff 2084 switch (swizzle) {
ea16a3cd
DV		 2085 case I915_BIT_6_SWIZZLE_NONE:
2086 return "none";
2087 case I915_BIT_6_SWIZZLE_9:
2088 return "bit9";
2089 case I915_BIT_6_SWIZZLE_9_10:
2090 return "bit9/bit10";
2091 case I915_BIT_6_SWIZZLE_9_11:
2092 return "bit9/bit11";
2093 case I915_BIT_6_SWIZZLE_9_10_11:
2094 return "bit9/bit10/bit11";
2095 case I915_BIT_6_SWIZZLE_9_17:
2096 return "bit9/bit17";
2097 case I915_BIT_6_SWIZZLE_9_10_17:
2098 return "bit9/bit10/bit17";
2099 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2100 return "unknown";
ea16a3cd
DV		 2101 }
2102
2103 return "bug";
2104}
2105
2106static int i915_swizzle_info(struct seq_file *m, void *data)
2107{
9f25d007 2108 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2109 struct drm_device *dev = node->minor->dev;
2110 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2111 int ret;
2112
2113 ret = mutex_lock_interruptible(&dev->struct_mutex);
2114 if (ret)
2115 return ret;
c8c8fb33 2116 intel_runtime_pm_get(dev_priv);
ea16a3cd 2117
ea16a3cd
DV		 2118 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2119 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2120 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2121 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2122
2123 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2124 seq_printf(m, "DDC = 0x%08x\n",
2125 I915_READ(DCC));
656bfa3a
DV		 2126 seq_printf(m, "DDC2 = 0x%08x\n",
2127 I915_READ(DCC2));
ea16a3cd
DV		 2128 seq_printf(m, "C0DRB3 = 0x%04x\n",
2129 I915_READ16(C0DRB3));
2130 seq_printf(m, "C1DRB3 = 0x%04x\n",
2131 I915_READ16(C1DRB3));
9d3203e1 2132 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2133 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2134 I915_READ(MAD_DIMM_C0));
2135 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2136 I915_READ(MAD_DIMM_C1));
2137 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2138 I915_READ(MAD_DIMM_C2));
2139 seq_printf(m, "TILECTL = 0x%08x\n",
2140 I915_READ(TILECTL));
5907f5fb 2141 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2142 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2143 I915_READ(GAMTARBMODE));
2144 else
2145 seq_printf(m, "ARB_MODE = 0x%08x\n",
2146 I915_READ(ARB_MODE));
3fa7d235
DV		 2147 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2148 I915_READ(DISP_ARB_CTL));
ea16a3cd 2149 }
656bfa3a
DV		 2150
2151 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2152 seq_puts(m, "L-shaped memory detected\n");
2153
c8c8fb33 2154 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2155 mutex_unlock(&dev->struct_mutex);
2156
2157 return 0;
2158}
2159
1c60fef5
BW		 2160static int per_file_ctx(int id, void *ptr, void *data)
2161{
273497e5 2162 struct intel_context *ctx = ptr;
1c60fef5 2163 struct seq_file *m = data;
ae6c4806
DV		 2164 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2165
2166 if (!ppgtt) {
2167 seq_printf(m, " no ppgtt for context %d\n",
2168 ctx->user_handle);
2169 return 0;
2170 }
1c60fef5 2171
f83d6518
OM		 2172 if (i915_gem_context_is_default(ctx))
2173 seq_puts(m, " default context:\n");
2174 else
821d66dd 2175 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2176 ppgtt->debug_dump(ppgtt, m);
2177
2178 return 0;
2179}
2180
77df6772 2181static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2182{
3cf17fc5 2183 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2184 struct intel_engine_cs *ring;
77df6772
BW		 2185 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2186 int unused, i;
3cf17fc5 2187
77df6772
BW		 2188 if (!ppgtt)
2189 return;
2190
77df6772
BW		 2191 for_each_ring(ring, dev_priv, unused) {
2192 seq_printf(m, "%s\n", ring->name);
2193 for (i = 0; i < 4; i++) {
2194 u32 offset = 0x270 + i * 8;
2195 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2196 pdp <<= 32;
2197 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2198 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2199 }
2200 }
2201}
2202
2203static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2204{
2205 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2206 struct intel_engine_cs *ring;
1c60fef5 2207 struct drm_file *file;
77df6772 2208 int i;
3cf17fc5 2209
3cf17fc5
DV		 2210 if (INTEL_INFO(dev)->gen == 6)
2211 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2212
a2c7f6fd 2213 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2214 seq_printf(m, "%s\n", ring->name);
2215 if (INTEL_INFO(dev)->gen == 7)
2216 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2217 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2218 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2219 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2220 }
2221 if (dev_priv->mm.aliasing_ppgtt) {
2222 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2223
267f0c90 2224 seq_puts(m, "aliasing PPGTT:\n");
7324cc04 2225 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
1c60fef5 2226
87d60b63 2227 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2228 }
1c60fef5
BW		 2229
2230 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2231 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2232
1c60fef5
BW		 2233 seq_printf(m, "proc: %s\n",
2234 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2235 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2236 }
2237 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2238}
2239
2240static int i915_ppgtt_info(struct seq_file *m, void *data)
2241{
9f25d007 2242 struct drm_info_node *node = m->private;
77df6772 2243 struct drm_device *dev = node->minor->dev;
c8c8fb33 2244 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2245
2246 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2247 if (ret)
2248 return ret;
c8c8fb33 2249 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2250
2251 if (INTEL_INFO(dev)->gen >= 8)
2252 gen8_ppgtt_info(m, dev);
2253 else if (INTEL_INFO(dev)->gen >= 6)
2254 gen6_ppgtt_info(m, dev);
2255
c8c8fb33 2256 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2257 mutex_unlock(&dev->struct_mutex);
2258
2259 return 0;
2260}
2261
1854d5ca
CW		 2262static int i915_rps_boost_info(struct seq_file *m, void *data)
2263{
2264 struct drm_info_node *node = m->private;
2265 struct drm_device *dev = node->minor->dev;
2266 struct drm_i915_private *dev_priv = dev->dev_private;
2267 struct drm_file *file;
2268 int ret;
2269
2270 ret = mutex_lock_interruptible(&dev->struct_mutex);
2271 if (ret)
2272 return ret;
2273
2274 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2275 if (ret)
2276 goto unlock;
2277
2278 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2279 struct drm_i915_file_private *file_priv = file->driver_priv;
2280 struct task_struct *task;
2281
2282 rcu_read_lock();
2283 task = pid_task(file->pid, PIDTYPE_PID);
2284 seq_printf(m, "%s [%d]: %d boosts%s\n",
2285 task ? task->comm : "<unknown>",
2286 task ? task->pid : -1,
2287 file_priv->rps_boosts,
2288 list_empty(&file_priv->rps_boost) ? "" : ", active");
2289 rcu_read_unlock();
2290 }
2291 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2292
2293 mutex_unlock(&dev_priv->rps.hw_lock);
2294unlock:
2295 mutex_unlock(&dev->struct_mutex);
2296
2297 return ret;
2298}
2299
63573eb7
BW		 2300static int i915_llc(struct seq_file *m, void *data)
2301{
9f25d007 2302 struct drm_info_node *node = m->private;
63573eb7
BW		 2303 struct drm_device *dev = node->minor->dev;
2304 struct drm_i915_private *dev_priv = dev->dev_private;
2305
2306 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2307 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2308 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2309
2310 return 0;
2311}
2312
e91fd8c6
RV		 2313static int i915_edp_psr_status(struct seq_file *m, void *data)
2314{
2315 struct drm_info_node *node = m->private;
2316 struct drm_device *dev = node->minor->dev;
2317 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2318 u32 psrperf = 0;
a6cbdb8e
RV		 2319 u32 stat[3];
2320 enum pipe pipe;
a031d709 2321 bool enabled = false;
e91fd8c6 2322
3553a8ea
DL		 2323 if (!HAS_PSR(dev)) {
2324 seq_puts(m, "PSR not supported\n");
2325 return 0;
2326 }
2327
c8c8fb33
PZ		 2328 intel_runtime_pm_get(dev_priv);
2329
fa128fa6 2330 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2331 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2332 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2333 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2334 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2335 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2336 dev_priv->psr.busy_frontbuffer_bits);
2337 seq_printf(m, "Re-enable work scheduled: %s\n",
2338 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2339
3553a8ea
DL		 2340 if (HAS_DDI(dev))
2341 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2342 else {
2343 for_each_pipe(dev_priv, pipe) {
2344 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2345 VLV_EDP_PSR_CURR_STATE_MASK;
2346 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2347 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2348 enabled = true;
a6cbdb8e
RV		 2349 }
2350 }
2351 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2352
2353 if (!HAS_DDI(dev))
2354 for_each_pipe(dev_priv, pipe) {
2355 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2356 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2357 seq_printf(m, " pipe %c", pipe_name(pipe));
2358 }
2359 seq_puts(m, "\n");
e91fd8c6 2360
a6cbdb8e 2361 /* CHV PSR has no kind of performance counter */
3553a8ea 2362 if (HAS_DDI(dev)) {
a031d709
RV		 2363 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2364 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2365
2366 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2367 }
fa128fa6 2368 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2369
c8c8fb33 2370 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2371 return 0;
2372}
2373
d2e216d0
RV		 2374static int i915_sink_crc(struct seq_file *m, void *data)
2375{
2376 struct drm_info_node *node = m->private;
2377 struct drm_device *dev = node->minor->dev;
2378 struct intel_encoder *encoder;
2379 struct intel_connector *connector;
2380 struct intel_dp *intel_dp = NULL;
2381 int ret;
2382 u8 crc[6];
2383
2384 drm_modeset_lock_all(dev);
aca5e361 2385 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2386
2387 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2388 continue;
2389
b6ae3c7c
PZ		 2390 if (!connector->base.encoder)
2391 continue;
2392
d2e216d0
RV		 2393 encoder = to_intel_encoder(connector->base.encoder);
2394 if (encoder->type != INTEL_OUTPUT_EDP)
2395 continue;
2396
2397 intel_dp = enc_to_intel_dp(&encoder->base);
2398
2399 ret = intel_dp_sink_crc(intel_dp, crc);
2400 if (ret)
2401 goto out;
2402
2403 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2404 crc[0], crc[1], crc[2],
2405 crc[3], crc[4], crc[5]);
2406 goto out;
2407 }
2408 ret = -ENODEV;
2409out:
2410 drm_modeset_unlock_all(dev);
2411 return ret;
2412}
2413
ec013e7f
JB		 2414static int i915_energy_uJ(struct seq_file *m, void *data)
2415{
2416 struct drm_info_node *node = m->private;
2417 struct drm_device *dev = node->minor->dev;
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2419 u64 power;
2420 u32 units;
2421
2422 if (INTEL_INFO(dev)->gen < 6)
2423 return -ENODEV;
2424
36623ef8
PZ		 2425 intel_runtime_pm_get(dev_priv);
2426
ec013e7f
JB		 2427 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2428 power = (power & 0x1f00) >> 8;
2429 units = 1000000 / (1 << power); /* convert to uJ */
2430 power = I915_READ(MCH_SECP_NRG_STTS);
2431 power *= units;
2432
36623ef8
PZ		 2433 intel_runtime_pm_put(dev_priv);
2434
ec013e7f 2435 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2436
2437 return 0;
2438}
2439
2440static int i915_pc8_status(struct seq_file *m, void *unused)
2441{
9f25d007 2442 struct drm_info_node *node = m->private;
371db66a
PZ		 2443 struct drm_device *dev = node->minor->dev;
2444 struct drm_i915_private *dev_priv = dev->dev_private;
2445
85b8d5c2 2446 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2447 seq_puts(m, "not supported\n");
2448 return 0;
2449 }
2450
86c4ec0d 2451 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2452 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2453 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2454
ec013e7f
JB		 2455 return 0;
2456}
2457
1da51581
ID		 2458static const char *power_domain_str(enum intel_display_power_domain domain)
2459{
2460 switch (domain) {
2461 case POWER_DOMAIN_PIPE_A:
2462 return "PIPE_A";
2463 case POWER_DOMAIN_PIPE_B:
2464 return "PIPE_B";
2465 case POWER_DOMAIN_PIPE_C:
2466 return "PIPE_C";
2467 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2468 return "PIPE_A_PANEL_FITTER";
2469 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2470 return "PIPE_B_PANEL_FITTER";
2471 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2472 return "PIPE_C_PANEL_FITTER";
2473 case POWER_DOMAIN_TRANSCODER_A:
2474 return "TRANSCODER_A";
2475 case POWER_DOMAIN_TRANSCODER_B:
2476 return "TRANSCODER_B";
2477 case POWER_DOMAIN_TRANSCODER_C:
2478 return "TRANSCODER_C";
2479 case POWER_DOMAIN_TRANSCODER_EDP:
2480 return "TRANSCODER_EDP";
319be8ae
ID		 2481 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2482 return "PORT_DDI_A_2_LANES";
2483 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2484 return "PORT_DDI_A_4_LANES";
2485 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2486 return "PORT_DDI_B_2_LANES";
2487 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2488 return "PORT_DDI_B_4_LANES";
2489 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2490 return "PORT_DDI_C_2_LANES";
2491 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2492 return "PORT_DDI_C_4_LANES";
2493 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2494 return "PORT_DDI_D_2_LANES";
2495 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2496 return "PORT_DDI_D_4_LANES";
2497 case POWER_DOMAIN_PORT_DSI:
2498 return "PORT_DSI";
2499 case POWER_DOMAIN_PORT_CRT:
2500 return "PORT_CRT";
2501 case POWER_DOMAIN_PORT_OTHER:
2502 return "PORT_OTHER";
1da51581
ID		 2503 case POWER_DOMAIN_VGA:
2504 return "VGA";
2505 case POWER_DOMAIN_AUDIO:
2506 return "AUDIO";
bd2bb1b9
PZ		 2507 case POWER_DOMAIN_PLLS:
2508 return "PLLS";
1407121a
S		 2509 case POWER_DOMAIN_AUX_A:
2510 return "AUX_A";
2511 case POWER_DOMAIN_AUX_B:
2512 return "AUX_B";
2513 case POWER_DOMAIN_AUX_C:
2514 return "AUX_C";
2515 case POWER_DOMAIN_AUX_D:
2516 return "AUX_D";
1da51581
ID		 2517 case POWER_DOMAIN_INIT:
2518 return "INIT";
2519 default:
5f77eeb0 2520 MISSING_CASE(domain);
1da51581
ID		 2521 return "?";
2522 }
2523}
2524
2525static int i915_power_domain_info(struct seq_file *m, void *unused)
2526{
9f25d007 2527 struct drm_info_node *node = m->private;
1da51581
ID		 2528 struct drm_device *dev = node->minor->dev;
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2531 int i;
2532
2533 mutex_lock(&power_domains->lock);
2534
2535 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2536 for (i = 0; i < power_domains->power_well_count; i++) {
2537 struct i915_power_well *power_well;
2538 enum intel_display_power_domain power_domain;
2539
2540 power_well = &power_domains->power_wells[i];
2541 seq_printf(m, "%-25s %d\n", power_well->name,
2542 power_well->count);
2543
2544 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2545 power_domain++) {
2546 if (!(BIT(power_domain) & power_well->domains))
2547 continue;
2548
2549 seq_printf(m, " %-23s %d\n",
2550 power_domain_str(power_domain),
2551 power_domains->domain_use_count[power_domain]);
2552 }
2553 }
2554
2555 mutex_unlock(&power_domains->lock);
2556
2557 return 0;
2558}
2559
53f5e3ca
JB		 2560static void intel_seq_print_mode(struct seq_file *m, int tabs,
2561 struct drm_display_mode *mode)
2562{
2563 int i;
2564
2565 for (i = 0; i < tabs; i++)
2566 seq_putc(m, '\t');
2567
2568 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2569 mode->base.id, mode->name,
2570 mode->vrefresh, mode->clock,
2571 mode->hdisplay, mode->hsync_start,
2572 mode->hsync_end, mode->htotal,
2573 mode->vdisplay, mode->vsync_start,
2574 mode->vsync_end, mode->vtotal,
2575 mode->type, mode->flags);
2576}
2577
2578static void intel_encoder_info(struct seq_file *m,
2579 struct intel_crtc *intel_crtc,
2580 struct intel_encoder *intel_encoder)
2581{
9f25d007 2582 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2583 struct drm_device *dev = node->minor->dev;
2584 struct drm_crtc *crtc = &intel_crtc->base;
2585 struct intel_connector *intel_connector;
2586 struct drm_encoder *encoder;
2587
2588 encoder = &intel_encoder->base;
2589 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2590 encoder->base.id, encoder->name);
53f5e3ca
JB		 2591 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2592 struct drm_connector *connector = &intel_connector->base;
2593 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2594 connector->base.id,
c23cc417 2595 connector->name,
53f5e3ca
JB		 2596 drm_get_connector_status_name(connector->status));
2597 if (connector->status == connector_status_connected) {
2598 struct drm_display_mode *mode = &crtc->mode;
2599 seq_printf(m, ", mode:\n");
2600 intel_seq_print_mode(m, 2, mode);
2601 } else {
2602 seq_putc(m, '\n');
2603 }
2604 }
2605}
2606
2607static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2608{
9f25d007 2609 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2610 struct drm_device *dev = node->minor->dev;
2611 struct drm_crtc *crtc = &intel_crtc->base;
2612 struct intel_encoder *intel_encoder;
2613
5aa8a937
MR		 2614 if (crtc->primary->fb)
2615 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2616 crtc->primary->fb->base.id, crtc->x, crtc->y,
2617 crtc->primary->fb->width, crtc->primary->fb->height);
2618 else
2619 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2620 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2621 intel_encoder_info(m, intel_crtc, intel_encoder);
2622}
2623
2624static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2625{
2626 struct drm_display_mode *mode = panel->fixed_mode;
2627
2628 seq_printf(m, "\tfixed mode:\n");
2629 intel_seq_print_mode(m, 2, mode);
2630}
2631
2632static void intel_dp_info(struct seq_file *m,
2633 struct intel_connector *intel_connector)
2634{
2635 struct intel_encoder *intel_encoder = intel_connector->encoder;
2636 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2637
2638 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2639 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2640 "no");
2641 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2642 intel_panel_info(m, &intel_connector->panel);
2643}
2644
2645static void intel_hdmi_info(struct seq_file *m,
2646 struct intel_connector *intel_connector)
2647{
2648 struct intel_encoder *intel_encoder = intel_connector->encoder;
2649 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2650
2651 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2652 "no");
2653}
2654
2655static void intel_lvds_info(struct seq_file *m,
2656 struct intel_connector *intel_connector)
2657{
2658 intel_panel_info(m, &intel_connector->panel);
2659}
2660
2661static void intel_connector_info(struct seq_file *m,
2662 struct drm_connector *connector)
2663{
2664 struct intel_connector *intel_connector = to_intel_connector(connector);
2665 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2666 struct drm_display_mode *mode;
53f5e3ca
JB		 2667
2668 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2669 connector->base.id, connector->name,
53f5e3ca
JB		 2670 drm_get_connector_status_name(connector->status));
2671 if (connector->status == connector_status_connected) {
2672 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2673 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2674 connector->display_info.width_mm,
2675 connector->display_info.height_mm);
2676 seq_printf(m, "\tsubpixel order: %s\n",
2677 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2678 seq_printf(m, "\tCEA rev: %d\n",
2679 connector->display_info.cea_rev);
2680 }
36cd7444
DA		 2681 if (intel_encoder) {
2682 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2683 intel_encoder->type == INTEL_OUTPUT_EDP)
2684 intel_dp_info(m, intel_connector);
2685 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2686 intel_hdmi_info(m, intel_connector);
2687 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2688 intel_lvds_info(m, intel_connector);
2689 }
53f5e3ca 2690
f103fc7d
JB		 2691 seq_printf(m, "\tmodes:\n");
2692 list_for_each_entry(mode, &connector->modes, head)
2693 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2694}
2695
065f2ec2
CW		 2696static bool cursor_active(struct drm_device *dev, int pipe)
2697{
2698 struct drm_i915_private *dev_priv = dev->dev_private;
2699 u32 state;
2700
2701 if (IS_845G(dev) || IS_I865G(dev))
2702 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2703 else
5efb3e28 2704 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2705
2706 return state;
2707}
2708
2709static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2710{
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712 u32 pos;
2713
5efb3e28 2714 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2715
2716 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2717 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2718 *x = -*x;
2719
2720 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2721 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2722 *y = -*y;
2723
2724 return cursor_active(dev, pipe);
2725}
2726
53f5e3ca
JB		 2727static int i915_display_info(struct seq_file *m, void *unused)
2728{
9f25d007 2729 struct drm_info_node *node = m->private;
53f5e3ca 2730 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2731 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2732 struct intel_crtc *crtc;
53f5e3ca
JB		 2733 struct drm_connector *connector;
2734
b0e5ddf3 2735 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2736 drm_modeset_lock_all(dev);
2737 seq_printf(m, "CRTC info\n");
2738 seq_printf(m, "---------\n");
d3fcc808 2739 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2740 bool active;
2741 int x, y;
53f5e3ca 2742
57127efa 2743 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2744 crtc->base.base.id, pipe_name(crtc->pipe),
6e3c9717
ACO		 2745 yesno(crtc->active), crtc->config->pipe_src_w,
2746 crtc->config->pipe_src_h);
a23dc658 2747 if (crtc->active) {
065f2ec2
CW		 2748 intel_crtc_info(m, crtc);
2749
a23dc658 2750 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2751 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2752 yesno(crtc->cursor_base),
3dd512fb
MR		 2753 x, y, crtc->base.cursor->state->crtc_w,
2754 crtc->base.cursor->state->crtc_h,
57127efa 2755 crtc->cursor_addr, yesno(active));
a23dc658 2756 }
cace841c
DV		 2757
2758 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2759 yesno(!crtc->cpu_fifo_underrun_disabled),
2760 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2761 }
2762
2763 seq_printf(m, "\n");
2764 seq_printf(m, "Connector info\n");
2765 seq_printf(m, "--------------\n");
2766 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2767 intel_connector_info(m, connector);
2768 }
2769 drm_modeset_unlock_all(dev);
b0e5ddf3 2770 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2771
2772 return 0;
2773}
2774
e04934cf
BW		 2775static int i915_semaphore_status(struct seq_file *m, void *unused)
2776{
2777 struct drm_info_node *node = (struct drm_info_node *) m->private;
2778 struct drm_device *dev = node->minor->dev;
2779 struct drm_i915_private *dev_priv = dev->dev_private;
2780 struct intel_engine_cs *ring;
2781 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2782 int i, j, ret;
2783
2784 if (!i915_semaphore_is_enabled(dev)) {
2785 seq_puts(m, "Semaphores are disabled\n");
2786 return 0;
2787 }
2788
2789 ret = mutex_lock_interruptible(&dev->struct_mutex);
2790 if (ret)
2791 return ret;
03872064 2792 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2793
2794 if (IS_BROADWELL(dev)) {
2795 struct page *page;
2796 uint64_t *seqno;
2797
2798 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2799
2800 seqno = (uint64_t *)kmap_atomic(page);
2801 for_each_ring(ring, dev_priv, i) {
2802 uint64_t offset;
2803
2804 seq_printf(m, "%s\n", ring->name);
2805
2806 seq_puts(m, " Last signal:");
2807 for (j = 0; j < num_rings; j++) {
2808 offset = i * I915_NUM_RINGS + j;
2809 seq_printf(m, "0x%08llx (0x%02llx) ",
2810 seqno[offset], offset * 8);
2811 }
2812 seq_putc(m, '\n');
2813
2814 seq_puts(m, " Last wait: ");
2815 for (j = 0; j < num_rings; j++) {
2816 offset = i + (j * I915_NUM_RINGS);
2817 seq_printf(m, "0x%08llx (0x%02llx) ",
2818 seqno[offset], offset * 8);
2819 }
2820 seq_putc(m, '\n');
2821
2822 }
2823 kunmap_atomic(seqno);
2824 } else {
2825 seq_puts(m, " Last signal:");
2826 for_each_ring(ring, dev_priv, i)
2827 for (j = 0; j < num_rings; j++)
2828 seq_printf(m, "0x%08x\n",
2829 I915_READ(ring->semaphore.mbox.signal[j]));
2830 seq_putc(m, '\n');
2831 }
2832
2833 seq_puts(m, "\nSync seqno:\n");
2834 for_each_ring(ring, dev_priv, i) {
2835 for (j = 0; j < num_rings; j++) {
2836 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2837 }
2838 seq_putc(m, '\n');
2839 }
2840 seq_putc(m, '\n');
2841
03872064 2842 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2843 mutex_unlock(&dev->struct_mutex);
2844 return 0;
2845}
2846
728e29d7
DV		 2847static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2848{
2849 struct drm_info_node *node = (struct drm_info_node *) m->private;
2850 struct drm_device *dev = node->minor->dev;
2851 struct drm_i915_private *dev_priv = dev->dev_private;
2852 int i;
2853
2854 drm_modeset_lock_all(dev);
2855 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2856 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2857
2858 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2859 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2860 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2861 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2862 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2863 seq_printf(m, " dpll_md: 0x%08x\n",
2864 pll->config.hw_state.dpll_md);
2865 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2866 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2867 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2868 }
2869 drm_modeset_unlock_all(dev);
2870
2871 return 0;
2872}
2873
1ed1ef9d 2874static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2875{
2876 int i;
2877 int ret;
2878 struct drm_info_node *node = (struct drm_info_node *) m->private;
2879 struct drm_device *dev = node->minor->dev;
2880 struct drm_i915_private *dev_priv = dev->dev_private;
2881
888b5995
AS		 2882 ret = mutex_lock_interruptible(&dev->struct_mutex);
2883 if (ret)
2884 return ret;
2885
2886 intel_runtime_pm_get(dev_priv);
2887
7225342a
MK		 2888 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2889 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2890 u32 addr, mask, value, read;
2891 bool ok;
888b5995 2892
7225342a
MK		 2893 addr = dev_priv->workarounds.reg[i].addr;
2894 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2895 value = dev_priv->workarounds.reg[i].value;
2896 read = I915_READ(addr);
2897 ok = (value & mask) == (read & mask);
2898 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2899 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2900 }
2901
2902 intel_runtime_pm_put(dev_priv);
2903 mutex_unlock(&dev->struct_mutex);
2904
2905 return 0;
2906}
2907
c5511e44
DL		 2908static int i915_ddb_info(struct seq_file *m, void *unused)
2909{
2910 struct drm_info_node *node = m->private;
2911 struct drm_device *dev = node->minor->dev;
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2913 struct skl_ddb_allocation *ddb;
2914 struct skl_ddb_entry *entry;
2915 enum pipe pipe;
2916 int plane;
2917
2fcffe19
DL		 2918 if (INTEL_INFO(dev)->gen < 9)
2919 return 0;
2920
c5511e44
DL		 2921 drm_modeset_lock_all(dev);
2922
2923 ddb = &dev_priv->wm.skl_hw.ddb;
2924
2925 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2926
2927 for_each_pipe(dev_priv, pipe) {
2928 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2929
dd740780 2930 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 2931 entry = &ddb->plane[pipe][plane];
2932 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2933 entry->start, entry->end,
2934 skl_ddb_entry_size(entry));
2935 }
2936
2937 entry = &ddb->cursor[pipe];
2938 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2939 entry->end, skl_ddb_entry_size(entry));
2940 }
2941
2942 drm_modeset_unlock_all(dev);
2943
2944 return 0;
2945}
2946
a54746e3
VK		 2947static void drrs_status_per_crtc(struct seq_file *m,
2948 struct drm_device *dev, struct intel_crtc *intel_crtc)
2949{
2950 struct intel_encoder *intel_encoder;
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952 struct i915_drrs *drrs = &dev_priv->drrs;
2953 int vrefresh = 0;
2954
2955 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
2956 /* Encoder connected on this CRTC */
2957 switch (intel_encoder->type) {
2958 case INTEL_OUTPUT_EDP:
2959 seq_puts(m, "eDP:\n");
2960 break;
2961 case INTEL_OUTPUT_DSI:
2962 seq_puts(m, "DSI:\n");
2963 break;
2964 case INTEL_OUTPUT_HDMI:
2965 seq_puts(m, "HDMI:\n");
2966 break;
2967 case INTEL_OUTPUT_DISPLAYPORT:
2968 seq_puts(m, "DP:\n");
2969 break;
2970 default:
2971 seq_printf(m, "Other encoder (id=%d).\n",
2972 intel_encoder->type);
2973 return;
2974 }
2975 }
2976
2977 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
2978 seq_puts(m, "\tVBT: DRRS_type: Static");
2979 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
2980 seq_puts(m, "\tVBT: DRRS_type: Seamless");
2981 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
2982 seq_puts(m, "\tVBT: DRRS_type: None");
2983 else
2984 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
2985
2986 seq_puts(m, "\n\n");
2987
2988 if (intel_crtc->config->has_drrs) {
2989 struct intel_panel *panel;
2990
2991 mutex_lock(&drrs->mutex);
2992 /* DRRS Supported */
2993 seq_puts(m, "\tDRRS Supported: Yes\n");
2994
2995 /* disable_drrs() will make drrs->dp NULL */
2996 if (!drrs->dp) {
2997 seq_puts(m, "Idleness DRRS: Disabled");
2998 mutex_unlock(&drrs->mutex);
2999 return;
3000 }
3001
3002 panel = &drrs->dp->attached_connector->panel;
3003 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3004 drrs->busy_frontbuffer_bits);
3005
3006 seq_puts(m, "\n\t\t");
3007 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3008 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3009 vrefresh = panel->fixed_mode->vrefresh;
3010 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3011 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3012 vrefresh = panel->downclock_mode->vrefresh;
3013 } else {
3014 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3015 drrs->refresh_rate_type);
3016 mutex_unlock(&drrs->mutex);
3017 return;
3018 }
3019 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3020
3021 seq_puts(m, "\n\t\t");
3022 mutex_unlock(&drrs->mutex);
3023 } else {
3024 /* DRRS not supported. Print the VBT parameter*/
3025 seq_puts(m, "\tDRRS Supported : No");
3026 }
3027 seq_puts(m, "\n");
3028}
3029
3030static int i915_drrs_status(struct seq_file *m, void *unused)
3031{
3032 struct drm_info_node *node = m->private;
3033 struct drm_device *dev = node->minor->dev;
3034 struct intel_crtc *intel_crtc;
3035 int active_crtc_cnt = 0;
3036
3037 for_each_intel_crtc(dev, intel_crtc) {
3038 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3039
3040 if (intel_crtc->active) {
3041 active_crtc_cnt++;
3042 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3043
3044 drrs_status_per_crtc(m, dev, intel_crtc);
3045 }
3046
3047 drm_modeset_unlock(&intel_crtc->base.mutex);
3048 }
3049
3050 if (!active_crtc_cnt)
3051 seq_puts(m, "No active crtc found\n");
3052
3053 return 0;
3054}
3055
07144428
DL		 3056struct pipe_crc_info {
3057 const char *name;
3058 struct drm_device *dev;
3059 enum pipe pipe;
3060};
3061
11bed958
DA		 3062static int i915_dp_mst_info(struct seq_file *m, void *unused)
3063{
3064 struct drm_info_node *node = (struct drm_info_node *) m->private;
3065 struct drm_device *dev = node->minor->dev;
3066 struct drm_encoder *encoder;
3067 struct intel_encoder *intel_encoder;
3068 struct intel_digital_port *intel_dig_port;
3069 drm_modeset_lock_all(dev);
3070 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3071 intel_encoder = to_intel_encoder(encoder);
3072 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3073 continue;
3074 intel_dig_port = enc_to_dig_port(encoder);
3075 if (!intel_dig_port->dp.can_mst)
3076 continue;
3077
3078 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3079 }
3080 drm_modeset_unlock_all(dev);
3081 return 0;
3082}
3083
07144428
DL		 3084static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3085{
be5c7a90
DL		 3086 struct pipe_crc_info *info = inode->i_private;
3087 struct drm_i915_private *dev_priv = info->dev->dev_private;
3088 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3089
7eb1c496
DV		 3090 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3091 return -ENODEV;
3092
d538bbdf
DL		 3093 spin_lock_irq(&pipe_crc->lock);
3094
3095 if (pipe_crc->opened) {
3096 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3097 return -EBUSY; /* already open */
3098 }
3099
d538bbdf 3100 pipe_crc->opened = true;
07144428
DL		 3101 filep->private_data = inode->i_private;
3102
d538bbdf
DL		 3103 spin_unlock_irq(&pipe_crc->lock);
3104
07144428
DL		 3105 return 0;
3106}
3107
3108static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3109{
be5c7a90
DL		 3110 struct pipe_crc_info *info = inode->i_private;
3111 struct drm_i915_private *dev_priv = info->dev->dev_private;
3112 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3113
d538bbdf
DL		 3114 spin_lock_irq(&pipe_crc->lock);
3115 pipe_crc->opened = false;
3116 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3117
07144428
DL		 3118 return 0;
3119}
3120
3121/* (6 fields, 8 chars each, space separated (5) + '\n') */
3122#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3123/* account for \'0' */
3124#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3125
3126static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3127{
d538bbdf
DL		 3128 assert_spin_locked(&pipe_crc->lock);
3129 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3130 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3131}
3132
3133static ssize_t
3134i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3135 loff_t *pos)
3136{
3137 struct pipe_crc_info *info = filep->private_data;
3138 struct drm_device *dev = info->dev;
3139 struct drm_i915_private *dev_priv = dev->dev_private;
3140 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3141 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3142 int n_entries;
07144428
DL		 3143 ssize_t bytes_read;
3144
3145 /*
3146 * Don't allow user space to provide buffers not big enough to hold
3147 * a line of data.
3148 */
3149 if (count < PIPE_CRC_LINE_LEN)
3150 return -EINVAL;
3151
3152 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3153 return 0;
07144428
DL		 3154
3155 /* nothing to read */
d538bbdf 3156 spin_lock_irq(&pipe_crc->lock);
07144428 3157 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3158 int ret;
3159
3160 if (filep->f_flags & O_NONBLOCK) {
3161 spin_unlock_irq(&pipe_crc->lock);
07144428 3162 return -EAGAIN;
d538bbdf 3163 }
07144428 3164
d538bbdf
DL		 3165 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3166 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3167 if (ret) {
3168 spin_unlock_irq(&pipe_crc->lock);
3169 return ret;
3170 }
8bf1e9f1
SH		 3171 }
3172
07144428 3173 /* We now have one or more entries to read */
9ad6d99f 3174 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3175
07144428 3176 bytes_read = 0;
9ad6d99f
VS		 3177 while (n_entries > 0) {
3178 struct intel_pipe_crc_entry *entry =
3179 &pipe_crc->entries[pipe_crc->tail];
07144428 3180 int ret;
8bf1e9f1 3181
9ad6d99f
VS		 3182 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3183 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3184 break;
3185
3186 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3187 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3188
07144428
DL		 3189 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3190 "%8u %8x %8x %8x %8x %8x\n",
3191 entry->frame, entry->crc[0],
3192 entry->crc[1], entry->crc[2],
3193 entry->crc[3], entry->crc[4]);
3194
9ad6d99f
VS		 3195 spin_unlock_irq(&pipe_crc->lock);
3196
3197 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3198 if (ret == PIPE_CRC_LINE_LEN)
3199 return -EFAULT;
b2c88f5b 3200
9ad6d99f
VS		 3201 user_buf += PIPE_CRC_LINE_LEN;
3202 n_entries--;
3203
3204 spin_lock_irq(&pipe_crc->lock);
3205 }
8bf1e9f1 3206
d538bbdf
DL		 3207 spin_unlock_irq(&pipe_crc->lock);
3208
07144428
DL		 3209 return bytes_read;
3210}
3211
3212static const struct file_operations i915_pipe_crc_fops = {
3213 .owner = THIS_MODULE,
3214 .open = i915_pipe_crc_open,
3215 .read = i915_pipe_crc_read,
3216 .release = i915_pipe_crc_release,
3217};
3218
3219static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3220 {
3221 .name = "i915_pipe_A_crc",
3222 .pipe = PIPE_A,
3223 },
3224 {
3225 .name = "i915_pipe_B_crc",
3226 .pipe = PIPE_B,
3227 },
3228 {
3229 .name = "i915_pipe_C_crc",
3230 .pipe = PIPE_C,
3231 },
3232};
3233
3234static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3235 enum pipe pipe)
3236{
3237 struct drm_device *dev = minor->dev;
3238 struct dentry *ent;
3239 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3240
3241 info->dev = dev;
3242 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3243 &i915_pipe_crc_fops);
f3c5fe97
WY		 3244 if (!ent)
3245 return -ENOMEM;
07144428
DL		 3246
3247 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3248}
3249
e8dfcf78 3250static const char * const pipe_crc_sources[] = {
926321d5
DV		 3251 "none",
3252 "plane1",
3253 "plane2",
3254 "pf",
5b3a856b 3255 "pipe",
3d099a05
DV		 3256 "TV",
3257 "DP-B",
3258 "DP-C",
3259 "DP-D",
46a19188 3260 "auto",
926321d5
DV		 3261};
3262
3263static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3264{
3265 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3266 return pipe_crc_sources[source];
3267}
3268
bd9db02f 3269static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3270{
3271 struct drm_device *dev = m->private;
3272 struct drm_i915_private *dev_priv = dev->dev_private;
3273 int i;
3274
3275 for (i = 0; i < I915_MAX_PIPES; i++)
3276 seq_printf(m, "%c %s\n", pipe_name(i),
3277 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3278
3279 return 0;
3280}
3281
bd9db02f 3282static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3283{
3284 struct drm_device *dev = inode->i_private;
3285
bd9db02f 3286 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3287}
3288
46a19188 3289static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3290 uint32_t *val)
3291{
46a19188
DV		 3292 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3293 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3294
3295 switch (*source) {
52f843f6
DV		 3296 case INTEL_PIPE_CRC_SOURCE_PIPE:
3297 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3298 break;
3299 case INTEL_PIPE_CRC_SOURCE_NONE:
3300 *val = 0;
3301 break;
3302 default:
3303 return -EINVAL;
3304 }
3305
3306 return 0;
3307}
3308
46a19188
DV		 3309static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3310 enum intel_pipe_crc_source *source)
3311{
3312 struct intel_encoder *encoder;
3313 struct intel_crtc *crtc;
26756809 3314 struct intel_digital_port *dig_port;
46a19188
DV		 3315 int ret = 0;
3316
3317 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3318
6e9f798d 3319 drm_modeset_lock_all(dev);
b2784e15 3320 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3321 if (!encoder->base.crtc)
3322 continue;
3323
3324 crtc = to_intel_crtc(encoder->base.crtc);
3325
3326 if (crtc->pipe != pipe)
3327 continue;
3328
3329 switch (encoder->type) {
3330 case INTEL_OUTPUT_TVOUT:
3331 *source = INTEL_PIPE_CRC_SOURCE_TV;
3332 break;
3333 case INTEL_OUTPUT_DISPLAYPORT:
3334 case INTEL_OUTPUT_EDP:
26756809
DV		 3335 dig_port = enc_to_dig_port(&encoder->base);
3336 switch (dig_port->port) {
3337 case PORT_B:
3338 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3339 break;
3340 case PORT_C:
3341 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3342 break;
3343 case PORT_D:
3344 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3345 break;
3346 default:
3347 WARN(1, "nonexisting DP port %c\n",
3348 port_name(dig_port->port));
3349 break;
3350 }
46a19188 3351 break;
6847d71b
PZ		 3352 default:
3353 break;
46a19188
DV		 3354 }
3355 }
6e9f798d 3356 drm_modeset_unlock_all(dev);
46a19188
DV		 3357
3358 return ret;
3359}
3360
3361static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3362 enum pipe pipe,
3363 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3364 uint32_t *val)
3365{
8d2f24ca
DV		 3366 struct drm_i915_private *dev_priv = dev->dev_private;
3367 bool need_stable_symbols = false;
3368
46a19188
DV		 3369 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3370 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3371 if (ret)
3372 return ret;
3373 }
3374
3375 switch (*source) {
7ac0129b
DV		 3376 case INTEL_PIPE_CRC_SOURCE_PIPE:
3377 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3378 break;
3379 case INTEL_PIPE_CRC_SOURCE_DP_B:
3380 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3381 need_stable_symbols = true;
7ac0129b
DV		 3382 break;
3383 case INTEL_PIPE_CRC_SOURCE_DP_C:
3384 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3385 need_stable_symbols = true;
7ac0129b 3386 break;
2be57922
VS		 3387 case INTEL_PIPE_CRC_SOURCE_DP_D:
3388 if (!IS_CHERRYVIEW(dev))
3389 return -EINVAL;
3390 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3391 need_stable_symbols = true;
3392 break;
7ac0129b
DV		 3393 case INTEL_PIPE_CRC_SOURCE_NONE:
3394 *val = 0;
3395 break;
3396 default:
3397 return -EINVAL;
3398 }
3399
8d2f24ca
DV		 3400 /*
3401 * When the pipe CRC tap point is after the transcoders we need
3402 * to tweak symbol-level features to produce a deterministic series of
3403 * symbols for a given frame. We need to reset those features only once
3404 * a frame (instead of every nth symbol):
3405 * - DC-balance: used to ensure a better clock recovery from the data
3406 * link (SDVO)
3407 * - DisplayPort scrambling: used for EMI reduction
3408 */
3409 if (need_stable_symbols) {
3410 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3411
8d2f24ca 3412 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3413 switch (pipe) {
3414 case PIPE_A:
8d2f24ca 3415 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3416 break;
3417 case PIPE_B:
8d2f24ca 3418 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3419 break;
3420 case PIPE_C:
3421 tmp |= PIPE_C_SCRAMBLE_RESET;
3422 break;
3423 default:
3424 return -EINVAL;
3425 }
8d2f24ca
DV		 3426 I915_WRITE(PORT_DFT2_G4X, tmp);
3427 }
3428
7ac0129b
DV		 3429 return 0;
3430}
3431
4b79ebf7 3432static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3433 enum pipe pipe,
3434 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3435 uint32_t *val)
3436{
84093603
DV		 3437 struct drm_i915_private *dev_priv = dev->dev_private;
3438 bool need_stable_symbols = false;
3439
46a19188
DV		 3440 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3441 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3442 if (ret)
3443 return ret;
3444 }
3445
3446 switch (*source) {
4b79ebf7
DV		 3447 case INTEL_PIPE_CRC_SOURCE_PIPE:
3448 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3449 break;
3450 case INTEL_PIPE_CRC_SOURCE_TV:
3451 if (!SUPPORTS_TV(dev))
3452 return -EINVAL;
3453 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3454 break;
3455 case INTEL_PIPE_CRC_SOURCE_DP_B:
3456 if (!IS_G4X(dev))
3457 return -EINVAL;
3458 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3459 need_stable_symbols = true;
4b79ebf7
DV		 3460 break;
3461 case INTEL_PIPE_CRC_SOURCE_DP_C:
3462 if (!IS_G4X(dev))
3463 return -EINVAL;
3464 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3465 need_stable_symbols = true;
4b79ebf7
DV		 3466 break;
3467 case INTEL_PIPE_CRC_SOURCE_DP_D:
3468 if (!IS_G4X(dev))
3469 return -EINVAL;
3470 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3471 need_stable_symbols = true;
4b79ebf7
DV		 3472 break;
3473 case INTEL_PIPE_CRC_SOURCE_NONE:
3474 *val = 0;
3475 break;
3476 default:
3477 return -EINVAL;
3478 }
3479
84093603
DV		 3480 /*
3481 * When the pipe CRC tap point is after the transcoders we need
3482 * to tweak symbol-level features to produce a deterministic series of
3483 * symbols for a given frame. We need to reset those features only once
3484 * a frame (instead of every nth symbol):
3485 * - DC-balance: used to ensure a better clock recovery from the data
3486 * link (SDVO)
3487 * - DisplayPort scrambling: used for EMI reduction
3488 */
3489 if (need_stable_symbols) {
3490 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3491
3492 WARN_ON(!IS_G4X(dev));
3493
3494 I915_WRITE(PORT_DFT_I9XX,
3495 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3496
3497 if (pipe == PIPE_A)
3498 tmp |= PIPE_A_SCRAMBLE_RESET;
3499 else
3500 tmp |= PIPE_B_SCRAMBLE_RESET;
3501
3502 I915_WRITE(PORT_DFT2_G4X, tmp);
3503 }
3504
4b79ebf7
DV		 3505 return 0;
3506}
3507
8d2f24ca
DV		 3508static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3509 enum pipe pipe)
3510{
3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3513
eb736679
VS		 3514 switch (pipe) {
3515 case PIPE_A:
8d2f24ca 3516 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3517 break;
3518 case PIPE_B:
8d2f24ca 3519 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3520 break;
3521 case PIPE_C:
3522 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3523 break;
3524 default:
3525 return;
3526 }
8d2f24ca
DV		 3527 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3528 tmp &= ~DC_BALANCE_RESET_VLV;
3529 I915_WRITE(PORT_DFT2_G4X, tmp);
3530
3531}
3532
84093603
DV		 3533static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3534 enum pipe pipe)
3535{
3536 struct drm_i915_private *dev_priv = dev->dev_private;
3537 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3538
3539 if (pipe == PIPE_A)
3540 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3541 else
3542 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3543 I915_WRITE(PORT_DFT2_G4X, tmp);
3544
3545 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3546 I915_WRITE(PORT_DFT_I9XX,
3547 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3548 }
3549}
3550
46a19188 3551static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3552 uint32_t *val)
3553{
46a19188
DV		 3554 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3555 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3556
3557 switch (*source) {
5b3a856b
DV		 3558 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3559 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3560 break;
3561 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3562 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3563 break;
5b3a856b
DV		 3564 case INTEL_PIPE_CRC_SOURCE_PIPE:
3565 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3566 break;
3d099a05 3567 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3568 *val = 0;
3569 break;
3d099a05
DV		 3570 default:
3571 return -EINVAL;
5b3a856b
DV		 3572 }
3573
3574 return 0;
3575}
3576
fabf6e51
DV		 3577static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3578{
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 struct intel_crtc *crtc =
3581 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3582
3583 drm_modeset_lock_all(dev);
3584 /*
3585 * If we use the eDP transcoder we need to make sure that we don't
3586 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3587 * relevant on hsw with pipe A when using the always-on power well
3588 * routing.
3589 */
6e3c9717
ACO		 3590 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3591 !crtc->config->pch_pfit.enabled) {
3592 crtc->config->pch_pfit.force_thru = true;
fabf6e51
DV		 3593
3594 intel_display_power_get(dev_priv,
3595 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3596
3597 dev_priv->display.crtc_disable(&crtc->base);
3598 dev_priv->display.crtc_enable(&crtc->base);
3599 }
3600 drm_modeset_unlock_all(dev);
3601}
3602
3603static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3604{
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 struct intel_crtc *crtc =
3607 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3608
3609 drm_modeset_lock_all(dev);
3610 /*
3611 * If we use the eDP transcoder we need to make sure that we don't
3612 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3613 * relevant on hsw with pipe A when using the always-on power well
3614 * routing.
3615 */
6e3c9717
ACO		 3616 if (crtc->config->pch_pfit.force_thru) {
3617 crtc->config->pch_pfit.force_thru = false;
fabf6e51
DV		 3618
3619 dev_priv->display.crtc_disable(&crtc->base);
3620 dev_priv->display.crtc_enable(&crtc->base);
3621
3622 intel_display_power_put(dev_priv,
3623 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3624 }
3625 drm_modeset_unlock_all(dev);
3626}
3627
3628static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3629 enum pipe pipe,
3630 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3631 uint32_t *val)
3632{
46a19188
DV		 3633 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3634 *source = INTEL_PIPE_CRC_SOURCE_PF;
3635
3636 switch (*source) {
5b3a856b
DV		 3637 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3638 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3639 break;
3640 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3641 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3642 break;
3643 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3644 if (IS_HASWELL(dev) && pipe == PIPE_A)
3645 hsw_trans_edp_pipe_A_crc_wa(dev);
3646
5b3a856b
DV		 3647 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3648 break;
3d099a05 3649 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3650 *val = 0;
3651 break;
3d099a05
DV		 3652 default:
3653 return -EINVAL;
5b3a856b
DV		 3654 }
3655
3656 return 0;
3657}
3658
926321d5
DV		 3659static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3660 enum intel_pipe_crc_source source)
3661{
3662 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3663 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3664 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3665 pipe));
432f3342 3666 u32 val = 0; /* shut up gcc */
5b3a856b 3667 int ret;
926321d5 3668
cc3da175
DL		 3669 if (pipe_crc->source == source)
3670 return 0;
3671
ae676fcd
DL		 3672 /* forbid changing the source without going back to 'none' */
3673 if (pipe_crc->source && source)
3674 return -EINVAL;
3675
9d8b0588
DV		 3676 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3677 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3678 return -EIO;
3679 }
3680
52f843f6 3681 if (IS_GEN2(dev))
46a19188 3682 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3683 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3684 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3685 else if (IS_VALLEYVIEW(dev))
fabf6e51 3686 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3687 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3688 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3689 else
fabf6e51 3690 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3691
3692 if (ret != 0)
3693 return ret;
3694
4b584369
DL		 3695 /* none -> real source transition */
3696 if (source) {
4252fbc3
VS		 3697 struct intel_pipe_crc_entry *entries;
3698
7cd6ccff
DL		 3699 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3700 pipe_name(pipe), pipe_crc_source_name(source));
3701
3cf54b34
VS		 3702 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3703 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3704 GFP_KERNEL);
3705 if (!entries)
e5f75aca
DL		 3706 return -ENOMEM;
3707
8c740dce
PZ		 3708 /*
3709 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3710 * enabled and disabled dynamically based on package C states,
3711 * user space can't make reliable use of the CRCs, so let's just
3712 * completely disable it.
3713 */
3714 hsw_disable_ips(crtc);
3715
d538bbdf 3716 spin_lock_irq(&pipe_crc->lock);
64387b61 3717 kfree(pipe_crc->entries);
4252fbc3 3718 pipe_crc->entries = entries;
d538bbdf
DL		 3719 pipe_crc->head = 0;
3720 pipe_crc->tail = 0;
3721 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3722 }
3723
cc3da175 3724 pipe_crc->source = source;
926321d5 3725
926321d5
DV		 3726 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3727 POSTING_READ(PIPE_CRC_CTL(pipe));
3728
e5f75aca
DL		 3729 /* real source -> none transition */
3730 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3731 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3732 struct intel_crtc *crtc =
3733 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3734
7cd6ccff
DL		 3735 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3736 pipe_name(pipe));
3737
a33d7105
DV		 3738 drm_modeset_lock(&crtc->base.mutex, NULL);
3739 if (crtc->active)
3740 intel_wait_for_vblank(dev, pipe);
3741 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3742
d538bbdf
DL		 3743 spin_lock_irq(&pipe_crc->lock);
3744 entries = pipe_crc->entries;
e5f75aca 3745 pipe_crc->entries = NULL;
9ad6d99f
VS		 3746 pipe_crc->head = 0;
3747 pipe_crc->tail = 0;
d538bbdf
DL		 3748 spin_unlock_irq(&pipe_crc->lock);
3749
3750 kfree(entries);
84093603
DV		 3751
3752 if (IS_G4X(dev))
3753 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3754 else if (IS_VALLEYVIEW(dev))
3755 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3756 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3757 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3758
3759 hsw_enable_ips(crtc);
e5f75aca
DL		 3760 }
3761
926321d5
DV		 3762 return 0;
3763}
3764
3765/*
3766 * Parse pipe CRC command strings:
b94dec87
DL		 3767 * command: wsp* object wsp+ name wsp+ source wsp*
3768 * object: 'pipe'
3769 * name: (A | B | C)
926321d5
DV		 3770 * source: (none | plane1 | plane2 | pf)
3771 * wsp: (#0x20 | #0x9 | #0xA)+
3772 *
3773 * eg.:
b94dec87
DL		 3774 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3775 * "pipe A none" -> Stop CRC
926321d5 3776 */
bd9db02f 3777static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3778{
3779 int n_words = 0;
3780
3781 while (*buf) {
3782 char *end;
3783
3784 /* skip leading white space */
3785 buf = skip_spaces(buf);
3786 if (!*buf)
3787 break; /* end of buffer */
3788
3789 /* find end of word */
3790 for (end = buf; *end && !isspace(*end); end++)
3791 ;
3792
3793 if (n_words == max_words) {
3794 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3795 max_words);
3796 return -EINVAL; /* ran out of words[] before bytes */
3797 }
3798
3799 if (*end)
3800 *end++ = '\0';
3801 words[n_words++] = buf;
3802 buf = end;
3803 }
3804
3805 return n_words;
3806}
3807
b94dec87
DL		 3808enum intel_pipe_crc_object {
3809 PIPE_CRC_OBJECT_PIPE,
3810};
3811
e8dfcf78 3812static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3813 "pipe",
3814};
3815
3816static int
bd9db02f 3817display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3818{
3819 int i;
3820
3821 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3822 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3823 *o = i;
b94dec87
DL		 3824 return 0;
3825 }
3826
3827 return -EINVAL;
3828}
3829
bd9db02f 3830static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3831{
3832 const char name = buf[0];
3833
3834 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3835 return -EINVAL;
3836
3837 *pipe = name - 'A';
3838
3839 return 0;
3840}
3841
3842static int
bd9db02f 3843display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3844{
3845 int i;
3846
3847 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3848 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3849 *s = i;
926321d5
DV		 3850 return 0;
3851 }
3852
3853 return -EINVAL;
3854}
3855
bd9db02f 3856static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3857{
b94dec87 3858#define N_WORDS 3
926321d5 3859 int n_words;
b94dec87 3860 char *words[N_WORDS];
926321d5 3861 enum pipe pipe;
b94dec87 3862 enum intel_pipe_crc_object object;
926321d5
DV		 3863 enum intel_pipe_crc_source source;
3864
bd9db02f 3865 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3866 if (n_words != N_WORDS) {
3867 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3868 N_WORDS);
3869 return -EINVAL;
3870 }
3871
bd9db02f 3872 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3873 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3874 return -EINVAL;
3875 }
3876
bd9db02f 3877 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3878 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3879 return -EINVAL;
3880 }
3881
bd9db02f 3882 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3883 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3884 return -EINVAL;
3885 }
3886
3887 return pipe_crc_set_source(dev, pipe, source);
3888}
3889
bd9db02f
DL		 3890static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3891 size_t len, loff_t *offp)
926321d5
DV		 3892{
3893 struct seq_file *m = file->private_data;
3894 struct drm_device *dev = m->private;
3895 char *tmpbuf;
3896 int ret;
3897
3898 if (len == 0)
3899 return 0;
3900
3901 if (len > PAGE_SIZE - 1) {
3902 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3903 PAGE_SIZE);
3904 return -E2BIG;
3905 }
3906
3907 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3908 if (!tmpbuf)
3909 return -ENOMEM;
3910
3911 if (copy_from_user(tmpbuf, ubuf, len)) {
3912 ret = -EFAULT;
3913 goto out;
3914 }
3915 tmpbuf[len] = '\0';
3916
bd9db02f 3917 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3918
3919out:
3920 kfree(tmpbuf);
3921 if (ret < 0)
3922 return ret;
3923
3924 *offp += len;
3925 return len;
3926}
3927
bd9db02f 3928static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3929 .owner = THIS_MODULE,
bd9db02f 3930 .open = display_crc_ctl_open,
926321d5
DV		 3931 .read = seq_read,
3932 .llseek = seq_lseek,
3933 .release = single_release,
bd9db02f 3934 .write = display_crc_ctl_write
926321d5
DV		 3935};
3936
97e94b22 3937static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3938{
3939 struct drm_device *dev = m->private;
546c81fd 3940 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3941 int level;
3942
3943 drm_modeset_lock_all(dev);
3944
3945 for (level = 0; level < num_levels; level++) {
3946 unsigned int latency = wm[level];
3947
97e94b22
DL		 3948 /*
3949 * - WM1+ latency values in 0.5us units
3950 * - latencies are in us on gen9
3951 */
3952 if (INTEL_INFO(dev)->gen >= 9)
3953 latency *= 10;
3954 else if (level > 0)
369a1342
VS		 3955 latency *= 5;
3956
3957 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3958 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3959 }
3960
3961 drm_modeset_unlock_all(dev);
3962}
3963
3964static int pri_wm_latency_show(struct seq_file *m, void *data)
3965{
3966 struct drm_device *dev = m->private;
97e94b22
DL		 3967 struct drm_i915_private *dev_priv = dev->dev_private;
3968 const uint16_t *latencies;
3969
3970 if (INTEL_INFO(dev)->gen >= 9)
3971 latencies = dev_priv->wm.skl_latency;
3972 else
3973 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3974
97e94b22 3975 wm_latency_show(m, latencies);
369a1342
VS		 3976
3977 return 0;
3978}
3979
3980static int spr_wm_latency_show(struct seq_file *m, void *data)
3981{
3982 struct drm_device *dev = m->private;
97e94b22
DL		 3983 struct drm_i915_private *dev_priv = dev->dev_private;
3984 const uint16_t *latencies;
3985
3986 if (INTEL_INFO(dev)->gen >= 9)
3987 latencies = dev_priv->wm.skl_latency;
3988 else
3989 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3990
97e94b22 3991 wm_latency_show(m, latencies);
369a1342
VS		 3992
3993 return 0;
3994}
3995
3996static int cur_wm_latency_show(struct seq_file *m, void *data)
3997{
3998 struct drm_device *dev = m->private;
97e94b22
DL		 3999 struct drm_i915_private *dev_priv = dev->dev_private;
4000 const uint16_t *latencies;
4001
4002 if (INTEL_INFO(dev)->gen >= 9)
4003 latencies = dev_priv->wm.skl_latency;
4004 else
4005 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4006
97e94b22 4007 wm_latency_show(m, latencies);
369a1342
VS		 4008
4009 return 0;
4010}
4011
4012static int pri_wm_latency_open(struct inode *inode, struct file *file)
4013{
4014 struct drm_device *dev = inode->i_private;
4015
9ad0257c 4016 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4017 return -ENODEV;
4018
4019 return single_open(file, pri_wm_latency_show, dev);
4020}
4021
4022static int spr_wm_latency_open(struct inode *inode, struct file *file)
4023{
4024 struct drm_device *dev = inode->i_private;
4025
9ad0257c 4026 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4027 return -ENODEV;
4028
4029 return single_open(file, spr_wm_latency_show, dev);
4030}
4031
4032static int cur_wm_latency_open(struct inode *inode, struct file *file)
4033{
4034 struct drm_device *dev = inode->i_private;
4035
9ad0257c 4036 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4037 return -ENODEV;
4038
4039 return single_open(file, cur_wm_latency_show, dev);
4040}
4041
4042static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4043 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4044{
4045 struct seq_file *m = file->private_data;
4046 struct drm_device *dev = m->private;
97e94b22 4047 uint16_t new[8] = { 0 };
546c81fd 4048 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4049 int level;
4050 int ret;
4051 char tmp[32];
4052
4053 if (len >= sizeof(tmp))
4054 return -EINVAL;
4055
4056 if (copy_from_user(tmp, ubuf, len))
4057 return -EFAULT;
4058
4059 tmp[len] = '\0';
4060
97e94b22
DL		 4061 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4062 &new[0], &new[1], &new[2], &new[3],
4063 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4064 if (ret != num_levels)
4065 return -EINVAL;
4066
4067 drm_modeset_lock_all(dev);
4068
4069 for (level = 0; level < num_levels; level++)
4070 wm[level] = new[level];
4071
4072 drm_modeset_unlock_all(dev);
4073
4074 return len;
4075}
4076
4077
4078static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4079 size_t len, loff_t *offp)
4080{
4081 struct seq_file *m = file->private_data;
4082 struct drm_device *dev = m->private;
97e94b22
DL		 4083 struct drm_i915_private *dev_priv = dev->dev_private;
4084 uint16_t *latencies;
369a1342 4085
97e94b22
DL		 4086 if (INTEL_INFO(dev)->gen >= 9)
4087 latencies = dev_priv->wm.skl_latency;
4088 else
4089 latencies = to_i915(dev)->wm.pri_latency;
4090
4091 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4092}
4093
4094static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4095 size_t len, loff_t *offp)
4096{
4097 struct seq_file *m = file->private_data;
4098 struct drm_device *dev = m->private;
97e94b22
DL		 4099 struct drm_i915_private *dev_priv = dev->dev_private;
4100 uint16_t *latencies;
369a1342 4101
97e94b22
DL		 4102 if (INTEL_INFO(dev)->gen >= 9)
4103 latencies = dev_priv->wm.skl_latency;
4104 else
4105 latencies = to_i915(dev)->wm.spr_latency;
4106
4107 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4108}
4109
4110static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4111 size_t len, loff_t *offp)
4112{
4113 struct seq_file *m = file->private_data;
4114 struct drm_device *dev = m->private;
97e94b22
DL		 4115 struct drm_i915_private *dev_priv = dev->dev_private;
4116 uint16_t *latencies;
4117
4118 if (INTEL_INFO(dev)->gen >= 9)
4119 latencies = dev_priv->wm.skl_latency;
4120 else
4121 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4122
97e94b22 4123 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4124}
4125
4126static const struct file_operations i915_pri_wm_latency_fops = {
4127 .owner = THIS_MODULE,
4128 .open = pri_wm_latency_open,
4129 .read = seq_read,
4130 .llseek = seq_lseek,
4131 .release = single_release,
4132 .write = pri_wm_latency_write
4133};
4134
4135static const struct file_operations i915_spr_wm_latency_fops = {
4136 .owner = THIS_MODULE,
4137 .open = spr_wm_latency_open,
4138 .read = seq_read,
4139 .llseek = seq_lseek,
4140 .release = single_release,
4141 .write = spr_wm_latency_write
4142};
4143
4144static const struct file_operations i915_cur_wm_latency_fops = {
4145 .owner = THIS_MODULE,
4146 .open = cur_wm_latency_open,
4147 .read = seq_read,
4148 .llseek = seq_lseek,
4149 .release = single_release,
4150 .write = cur_wm_latency_write
4151};
4152
647416f9
KC		 4153static int
4154i915_wedged_get(void *data, u64 *val)
f3cd474b 4155{
647416f9 4156 struct drm_device *dev = data;
e277a1f8 4157 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4158
647416f9 4159 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4160
647416f9 4161 return 0;
f3cd474b
CW		 4162}
4163
647416f9
KC		 4164static int
4165i915_wedged_set(void *data, u64 val)
f3cd474b 4166{
647416f9 4167 struct drm_device *dev = data;
d46c0517
ID		 4168 struct drm_i915_private *dev_priv = dev->dev_private;
4169
b8d24a06
MK		 4170 /*
4171 * There is no safeguard against this debugfs entry colliding
4172 * with the hangcheck calling same i915_handle_error() in
4173 * parallel, causing an explosion. For now we assume that the
4174 * test harness is responsible enough not to inject gpu hangs
4175 * while it is writing to 'i915_wedged'
4176 */
4177
4178 if (i915_reset_in_progress(&dev_priv->gpu_error))
4179 return -EAGAIN;
4180
d46c0517 4181 intel_runtime_pm_get(dev_priv);
f3cd474b 4182
58174462
MK		 4183 i915_handle_error(dev, val,
4184 "Manually setting wedged to %llu", val);
d46c0517
ID		 4185
4186 intel_runtime_pm_put(dev_priv);
4187
647416f9 4188 return 0;
f3cd474b
CW		 4189}
4190
647416f9
KC		 4191DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4192 i915_wedged_get, i915_wedged_set,
3a3b4f98 4193 "%llu\n");
f3cd474b 4194
647416f9
KC		 4195static int
4196i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4197{
647416f9 4198 struct drm_device *dev = data;
e277a1f8 4199 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4200
647416f9 4201 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4202
647416f9 4203 return 0;
e5eb3d63
DV		 4204}
4205
647416f9
KC		 4206static int
4207i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4208{
647416f9 4209 struct drm_device *dev = data;
e5eb3d63 4210 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4211 int ret;
e5eb3d63 4212
647416f9 4213 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4214
22bcfc6a
DV		 4215 ret = mutex_lock_interruptible(&dev->struct_mutex);
4216 if (ret)
4217 return ret;
4218
99584db3 4219 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4220 mutex_unlock(&dev->struct_mutex);
4221
647416f9 4222 return 0;
e5eb3d63
DV		 4223}
4224
647416f9
KC		 4225DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4226 i915_ring_stop_get, i915_ring_stop_set,
4227 "0x%08llx\n");
d5442303 4228
094f9a54
CW		 4229static int
4230i915_ring_missed_irq_get(void *data, u64 *val)
4231{
4232 struct drm_device *dev = data;
4233 struct drm_i915_private *dev_priv = dev->dev_private;
4234
4235 *val = dev_priv->gpu_error.missed_irq_rings;
4236 return 0;
4237}
4238
4239static int
4240i915_ring_missed_irq_set(void *data, u64 val)
4241{
4242 struct drm_device *dev = data;
4243 struct drm_i915_private *dev_priv = dev->dev_private;
4244 int ret;
4245
4246 /* Lock against concurrent debugfs callers */
4247 ret = mutex_lock_interruptible(&dev->struct_mutex);
4248 if (ret)
4249 return ret;
4250 dev_priv->gpu_error.missed_irq_rings = val;
4251 mutex_unlock(&dev->struct_mutex);
4252
4253 return 0;
4254}
4255
4256DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4257 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4258 "0x%08llx\n");
4259
4260static int
4261i915_ring_test_irq_get(void *data, u64 *val)
4262{
4263 struct drm_device *dev = data;
4264 struct drm_i915_private *dev_priv = dev->dev_private;
4265
4266 *val = dev_priv->gpu_error.test_irq_rings;
4267
4268 return 0;
4269}
4270
4271static int
4272i915_ring_test_irq_set(void *data, u64 val)
4273{
4274 struct drm_device *dev = data;
4275 struct drm_i915_private *dev_priv = dev->dev_private;
4276 int ret;
4277
4278 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4279
4280 /* Lock against concurrent debugfs callers */
4281 ret = mutex_lock_interruptible(&dev->struct_mutex);
4282 if (ret)
4283 return ret;
4284
4285 dev_priv->gpu_error.test_irq_rings = val;
4286 mutex_unlock(&dev->struct_mutex);
4287
4288 return 0;
4289}
4290
4291DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4292 i915_ring_test_irq_get, i915_ring_test_irq_set,
4293 "0x%08llx\n");
4294
dd624afd
CW		 4295#define DROP_UNBOUND 0x1
4296#define DROP_BOUND 0x2
4297#define DROP_RETIRE 0x4
4298#define DROP_ACTIVE 0x8
4299#define DROP_ALL (DROP_UNBOUND | \
4300 DROP_BOUND | \
4301 DROP_RETIRE | \
4302 DROP_ACTIVE)
647416f9
KC		 4303static int
4304i915_drop_caches_get(void *data, u64 *val)
dd624afd 4305{
647416f9 4306 *val = DROP_ALL;
dd624afd 4307
647416f9 4308 return 0;
dd624afd
CW		 4309}
4310
647416f9
KC		 4311static int
4312i915_drop_caches_set(void *data, u64 val)
dd624afd 4313{
647416f9 4314 struct drm_device *dev = data;
dd624afd 4315 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4316 int ret;
dd624afd 4317
2f9fe5ff 4318 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4319
4320 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4321 * on ioctls on -EAGAIN. */
4322 ret = mutex_lock_interruptible(&dev->struct_mutex);
4323 if (ret)
4324 return ret;
4325
4326 if (val & DROP_ACTIVE) {
4327 ret = i915_gpu_idle(dev);
4328 if (ret)
4329 goto unlock;
4330 }
4331
4332 if (val & (DROP_RETIRE | DROP_ACTIVE))
4333 i915_gem_retire_requests(dev);
4334
21ab4e74
CW		 4335 if (val & DROP_BOUND)
4336 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4337
21ab4e74
CW		 4338 if (val & DROP_UNBOUND)
4339 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4340
4341unlock:
4342 mutex_unlock(&dev->struct_mutex);
4343
647416f9 4344 return ret;
dd624afd
CW		 4345}
4346
647416f9
KC		 4347DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4348 i915_drop_caches_get, i915_drop_caches_set,
4349 "0x%08llx\n");
dd624afd 4350
647416f9
KC		 4351static int
4352i915_max_freq_get(void *data, u64 *val)
358733e9 4353{
647416f9 4354 struct drm_device *dev = data;
e277a1f8 4355 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4356 int ret;
004777cb 4357
daa3afb2 4358 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4359 return -ENODEV;
4360
5c9669ce
TR		 4361 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4362
4fc688ce 4363 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4364 if (ret)
4365 return ret;
358733e9 4366
7c59a9c1 4367 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4368 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4369
647416f9 4370 return 0;
358733e9
JB		 4371}
4372
647416f9
KC		 4373static int
4374i915_max_freq_set(void *data, u64 val)
358733e9 4375{
647416f9 4376 struct drm_device *dev = data;
358733e9 4377 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4378 u32 hw_max, hw_min;
647416f9 4379 int ret;
004777cb 4380
daa3afb2 4381 if (INTEL_INFO(dev)->gen < 6)
004777cb 4382 return -ENODEV;
358733e9 4383
5c9669ce
TR		 4384 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4385
647416f9 4386 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4387
4fc688ce 4388 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4389 if (ret)
4390 return ret;
4391
358733e9
JB		 4392 /*
4393 * Turbo will still be enabled, but won't go above the set value.
4394 */
bc4d91f6 4395 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4396
bc4d91f6
AG		 4397 hw_max = dev_priv->rps.max_freq;
4398 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4399
b39fb297 4400 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4401 mutex_unlock(&dev_priv->rps.hw_lock);
4402 return -EINVAL;
0a073b84
JB		 4403 }
4404
b39fb297 4405 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4406
ffe02b40 4407 intel_set_rps(dev, val);
dd0a1aa1 4408
4fc688ce 4409 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4410
647416f9 4411 return 0;
358733e9
JB		 4412}
4413
647416f9
KC		 4414DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4415 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4416 "%llu\n");
358733e9 4417
647416f9
KC		 4418static int
4419i915_min_freq_get(void *data, u64 *val)
1523c310 4420{
647416f9 4421 struct drm_device *dev = data;
e277a1f8 4422 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4423 int ret;
004777cb 4424
daa3afb2 4425 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4426 return -ENODEV;
4427
5c9669ce
TR		 4428 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4429
4fc688ce 4430 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4431 if (ret)
4432 return ret;
1523c310 4433
7c59a9c1 4434 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4435 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4436
647416f9 4437 return 0;
1523c310
JB		 4438}
4439
647416f9
KC		 4440static int
4441i915_min_freq_set(void *data, u64 val)
1523c310 4442{
647416f9 4443 struct drm_device *dev = data;
1523c310 4444 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4445 u32 hw_max, hw_min;
647416f9 4446 int ret;
004777cb 4447
daa3afb2 4448 if (INTEL_INFO(dev)->gen < 6)
004777cb 4449 return -ENODEV;
1523c310 4450
5c9669ce
TR		 4451 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4452
647416f9 4453 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4454
4fc688ce 4455 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4456 if (ret)
4457 return ret;
4458
1523c310
JB		 4459 /*
4460 * Turbo will still be enabled, but won't go below the set value.
4461 */
bc4d91f6 4462 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4463
bc4d91f6
AG		 4464 hw_max = dev_priv->rps.max_freq;
4465 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4466
b39fb297 4467 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4468 mutex_unlock(&dev_priv->rps.hw_lock);
4469 return -EINVAL;
0a073b84 4470 }
dd0a1aa1 4471
b39fb297 4472 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4473
ffe02b40 4474 intel_set_rps(dev, val);
dd0a1aa1 4475
4fc688ce 4476 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4477
647416f9 4478 return 0;
1523c310
JB		 4479}
4480
647416f9
KC		 4481DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4482 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4483 "%llu\n");
1523c310 4484
647416f9
KC		 4485static int
4486i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4487{
647416f9 4488 struct drm_device *dev = data;
e277a1f8 4489 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4490 u32 snpcr;
647416f9 4491 int ret;
07b7ddd9 4492
004777cb
DV		 4493 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4494 return -ENODEV;
4495
22bcfc6a
DV		 4496 ret = mutex_lock_interruptible(&dev->struct_mutex);
4497 if (ret)
4498 return ret;
c8c8fb33 4499 intel_runtime_pm_get(dev_priv);
22bcfc6a 4500
07b7ddd9 4501 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4502
4503 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4504 mutex_unlock(&dev_priv->dev->struct_mutex);
4505
647416f9 4506 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4507
647416f9 4508 return 0;
07b7ddd9
JB		 4509}
4510
647416f9
KC		 4511static int
4512i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4513{
647416f9 4514 struct drm_device *dev = data;
07b7ddd9 4515 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4516 u32 snpcr;
07b7ddd9 4517
004777cb
DV		 4518 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4519 return -ENODEV;
4520
647416f9 4521 if (val > 3)
07b7ddd9
JB		 4522 return -EINVAL;
4523
c8c8fb33 4524 intel_runtime_pm_get(dev_priv);
647416f9 4525 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4526
4527 /* Update the cache sharing policy here as well */
4528 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4529 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4530 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4531 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4532
c8c8fb33 4533 intel_runtime_pm_put(dev_priv);
647416f9 4534 return 0;
07b7ddd9
JB		 4535}
4536
647416f9
KC		 4537DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4538 i915_cache_sharing_get, i915_cache_sharing_set,
4539 "%llu\n");
07b7ddd9 4540
5d39525a
JM		 4541struct sseu_dev_status {
4542 unsigned int slice_total;
4543 unsigned int subslice_total;
4544 unsigned int subslice_per_slice;
4545 unsigned int eu_total;
4546 unsigned int eu_per_subslice;
4547};
4548
4549static void cherryview_sseu_device_status(struct drm_device *dev,
4550 struct sseu_dev_status *stat)
4551{
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4553 const int ss_max = 2;
4554 int ss;
4555 u32 sig1[ss_max], sig2[ss_max];
4556
4557 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4558 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4559 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4560 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4561
4562 for (ss = 0; ss < ss_max; ss++) {
4563 unsigned int eu_cnt;
4564
4565 if (sig1[ss] & CHV_SS_PG_ENABLE)
4566 /* skip disabled subslice */
4567 continue;
4568
4569 stat->slice_total = 1;
4570 stat->subslice_per_slice++;
4571 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4572 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4573 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4574 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4575 stat->eu_total += eu_cnt;
4576 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4577 }
4578 stat->subslice_total = stat->subslice_per_slice;
4579}
4580
4581static void gen9_sseu_device_status(struct drm_device *dev,
4582 struct sseu_dev_status *stat)
4583{
4584 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 4585 int s_max = 3, ss_max = 4;
5d39525a
JM		 4586 int s, ss;
4587 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4588
1c046bc1
JM		 4589 /* BXT has a single slice and at most 3 subslices. */
4590 if (IS_BROXTON(dev)) {
4591 s_max = 1;
4592 ss_max = 3;
4593 }
4594
4595 for (s = 0; s < s_max; s++) {
4596 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4597 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4598 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4599 }
4600
5d39525a
JM		 4601 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4602 GEN9_PGCTL_SSA_EU19_ACK |
4603 GEN9_PGCTL_SSA_EU210_ACK |
4604 GEN9_PGCTL_SSA_EU311_ACK;
4605 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4606 GEN9_PGCTL_SSB_EU19_ACK |
4607 GEN9_PGCTL_SSB_EU210_ACK |
4608 GEN9_PGCTL_SSB_EU311_ACK;
4609
4610 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 4611 unsigned int ss_cnt = 0;
4612
5d39525a
JM		 4613 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4614 /* skip disabled slice */
4615 continue;
4616
4617 stat->slice_total++;
1c046bc1
JM		 4618
4619 if (IS_SKYLAKE(dev))
4620 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4621
5d39525a
JM		 4622 for (ss = 0; ss < ss_max; ss++) {
4623 unsigned int eu_cnt;
4624
1c046bc1
JM		 4625 if (IS_BROXTON(dev) &&
4626 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4627 /* skip disabled subslice */
4628 continue;
4629
4630 if (IS_BROXTON(dev))
4631 ss_cnt++;
4632
5d39525a
JM		 4633 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4634 eu_mask[ss%2]);
4635 stat->eu_total += eu_cnt;
4636 stat->eu_per_subslice = max(stat->eu_per_subslice,
4637 eu_cnt);
4638 }
1c046bc1
JM		 4639
4640 stat->subslice_total += ss_cnt;
4641 stat->subslice_per_slice = max(stat->subslice_per_slice,
4642 ss_cnt);
5d39525a
JM		 4643 }
4644}
4645
3873218f
JM		 4646static int i915_sseu_status(struct seq_file *m, void *unused)
4647{
4648 struct drm_info_node *node = (struct drm_info_node *) m->private;
4649 struct drm_device *dev = node->minor->dev;
5d39525a 4650 struct sseu_dev_status stat;
3873218f 4651
5575f03a 4652 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
3873218f
JM		 4653 return -ENODEV;
4654
4655 seq_puts(m, "SSEU Device Info\n");
4656 seq_printf(m, " Available Slice Total: %u\n",
4657 INTEL_INFO(dev)->slice_total);
4658 seq_printf(m, " Available Subslice Total: %u\n",
4659 INTEL_INFO(dev)->subslice_total);
4660 seq_printf(m, " Available Subslice Per Slice: %u\n",
4661 INTEL_INFO(dev)->subslice_per_slice);
4662 seq_printf(m, " Available EU Total: %u\n",
4663 INTEL_INFO(dev)->eu_total);
4664 seq_printf(m, " Available EU Per Subslice: %u\n",
4665 INTEL_INFO(dev)->eu_per_subslice);
4666 seq_printf(m, " Has Slice Power Gating: %s\n",
4667 yesno(INTEL_INFO(dev)->has_slice_pg));
4668 seq_printf(m, " Has Subslice Power Gating: %s\n",
4669 yesno(INTEL_INFO(dev)->has_subslice_pg));
4670 seq_printf(m, " Has EU Power Gating: %s\n",
4671 yesno(INTEL_INFO(dev)->has_eu_pg));
4672
7f992aba 4673 seq_puts(m, "SSEU Device Status\n");
5d39525a 4674 memset(&stat, 0, sizeof(stat));
5575f03a 4675 if (IS_CHERRYVIEW(dev)) {
5d39525a 4676 cherryview_sseu_device_status(dev, &stat);
1c046bc1 4677 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 4678 gen9_sseu_device_status(dev, &stat);
7f992aba 4679 }
5d39525a
JM		 4680 seq_printf(m, " Enabled Slice Total: %u\n",
4681 stat.slice_total);
4682 seq_printf(m, " Enabled Subslice Total: %u\n",
4683 stat.subslice_total);
4684 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
4685 stat.subslice_per_slice);
4686 seq_printf(m, " Enabled EU Total: %u\n",
4687 stat.eu_total);
4688 seq_printf(m, " Enabled EU Per Subslice: %u\n",
4689 stat.eu_per_subslice);
7f992aba 4690
3873218f
JM		 4691 return 0;
4692}
4693
6d794d42
BW		 4694static int i915_forcewake_open(struct inode *inode, struct file *file)
4695{
4696 struct drm_device *dev = inode->i_private;
4697 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4698
075edca4 4699 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4700 return 0;
4701
6daccb0b 4702 intel_runtime_pm_get(dev_priv);
59bad947 4703 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4704
4705 return 0;
4706}
4707
c43b5634 4708static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4709{
4710 struct drm_device *dev = inode->i_private;
4711 struct drm_i915_private *dev_priv = dev->dev_private;
4712
075edca4 4713 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4714 return 0;
4715
59bad947 4716 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4717 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4718
4719 return 0;
4720}
4721
4722static const struct file_operations i915_forcewake_fops = {
4723 .owner = THIS_MODULE,
4724 .open = i915_forcewake_open,
4725 .release = i915_forcewake_release,
4726};
4727
4728static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4729{
4730 struct drm_device *dev = minor->dev;
4731 struct dentry *ent;
4732
4733 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4734 S_IRUSR,
6d794d42
BW		 4735 root, dev,
4736 &i915_forcewake_fops);
f3c5fe97
WY		 4737 if (!ent)
4738 return -ENOMEM;
6d794d42 4739
8eb57294 4740 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4741}
4742
6a9c308d
DV		 4743static int i915_debugfs_create(struct dentry *root,
4744 struct drm_minor *minor,
4745 const char *name,
4746 const struct file_operations *fops)
07b7ddd9
JB		 4747{
4748 struct drm_device *dev = minor->dev;
4749 struct dentry *ent;
4750
6a9c308d 4751 ent = debugfs_create_file(name,
07b7ddd9
JB		 4752 S_IRUGO | S_IWUSR,
4753 root, dev,
6a9c308d 4754 fops);
f3c5fe97
WY		 4755 if (!ent)
4756 return -ENOMEM;
07b7ddd9 4757
6a9c308d 4758 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4759}
4760
06c5bf8c 4761static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4762 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4763 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4764 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4765 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4766 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4767 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4768 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4769 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4770 {"i915_gem_request", i915_gem_request_info, 0},
4771 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4772 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4773 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4774 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4775 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4776 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4777 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 4778 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 4779 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 4780 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 4781 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4782 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4783 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4784 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4785 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4786 {"i915_sr_status", i915_sr_status, 0},
44834a67 4787 {"i915_opregion", i915_opregion, 0},
37811fcc 4788 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4789 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4790 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4791 {"i915_execlists", i915_execlists, 0},
f65367b5 4792 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 4793 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4794 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4795 {"i915_llc", i915_llc, 0},
e91fd8c6 4796 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4797 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4798 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4799 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4800 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4801 {"i915_display_info", i915_display_info, 0},
e04934cf 4802 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4803 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4804 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4805 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4806 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 4807 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 4808 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 4809 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 4810};
27c202ad 4811#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4812
06c5bf8c 4813static const struct i915_debugfs_files {
34b9674c
DV		 4814 const char *name;
4815 const struct file_operations *fops;
4816} i915_debugfs_files[] = {
4817 {"i915_wedged", &i915_wedged_fops},
4818 {"i915_max_freq", &i915_max_freq_fops},
4819 {"i915_min_freq", &i915_min_freq_fops},
4820 {"i915_cache_sharing", &i915_cache_sharing_fops},
4821 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4822 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4823 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4824 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4825 {"i915_error_state", &i915_error_state_fops},
4826 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4827 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4828 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4829 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4830 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4831 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4832};
4833
07144428
DL		 4834void intel_display_crc_init(struct drm_device *dev)
4835{
4836 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4837 enum pipe pipe;
07144428 4838
055e393f 4839 for_each_pipe(dev_priv, pipe) {
b378360e 4840 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4841
d538bbdf
DL		 4842 pipe_crc->opened = false;
4843 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4844 init_waitqueue_head(&pipe_crc->wq);
4845 }
4846}
4847
27c202ad 4848int i915_debugfs_init(struct drm_minor *minor)
2017263e 4849{
34b9674c 4850 int ret, i;
f3cd474b 4851
6d794d42 4852 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4853 if (ret)
4854 return ret;
6a9c308d 4855
07144428
DL		 4856 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4857 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4858 if (ret)
4859 return ret;
4860 }
4861
34b9674c
DV		 4862 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4863 ret = i915_debugfs_create(minor->debugfs_root, minor,
4864 i915_debugfs_files[i].name,
4865 i915_debugfs_files[i].fops);
4866 if (ret)
4867 return ret;
4868 }
40633219 4869
27c202ad
BG		 4870 return drm_debugfs_create_files(i915_debugfs_list,
4871 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4872 minor->debugfs_root, minor);
4873}
4874
27c202ad 4875void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4876{
34b9674c
DV		 4877 int i;
4878
27c202ad
BG		 4879 drm_debugfs_remove_files(i915_debugfs_list,
4880 I915_DEBUGFS_ENTRIES, minor);
07144428 4881
6d794d42
BW		 4882 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4883 1, minor);
07144428 4884
e309a997 4885 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4886 struct drm_info_list *info_list =
4887 (struct drm_info_list *)&i915_pipe_crc_data[i];
4888
4889 drm_debugfs_remove_files(info_list, 1, minor);
4890 }
4891
34b9674c
DV		 4892 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4893 struct drm_info_list *info_list =
4894 (struct drm_info_list *) i915_debugfs_files[i].fops;
4895
4896 drm_debugfs_remove_files(info_list, 1, minor);
4897 }
2017263e 4898}
aa7471d2
JN		 4899
4900struct dpcd_block {
4901 /* DPCD dump start address. */
4902 unsigned int offset;
4903 /* DPCD dump end address, inclusive. If unset, .size will be used. */
4904 unsigned int end;
4905 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4906 size_t size;
4907 /* Only valid for eDP. */
4908 bool edp;
4909};
4910
4911static const struct dpcd_block i915_dpcd_debug[] = {
4912 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4913 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4914 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4915 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4916 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4917 { .offset = DP_SET_POWER },
4918 { .offset = DP_EDP_DPCD_REV },
4919 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4920 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4921 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4922};
4923
4924static int i915_dpcd_show(struct seq_file *m, void *data)
4925{
4926 struct drm_connector *connector = m->private;
4927 struct intel_dp *intel_dp =
4928 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4929 uint8_t buf[16];
4930 ssize_t err;
4931 int i;
4932
4933 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4934 const struct dpcd_block *b = &i915_dpcd_debug[i];
4935 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4936
4937 if (b->edp &&
4938 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4939 continue;
4940
4941 /* low tech for now */
4942 if (WARN_ON(size > sizeof(buf)))
4943 continue;
4944
4945 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4946 if (err <= 0) {
4947 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4948 size, b->offset, err);
4949 continue;
4950 }
4951
4952 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 4953 }
aa7471d2
JN		 4954
4955 return 0;
4956}
4957
4958static int i915_dpcd_open(struct inode *inode, struct file *file)
4959{
4960 return single_open(file, i915_dpcd_show, inode->i_private);
4961}
4962
4963static const struct file_operations i915_dpcd_fops = {
4964 .owner = THIS_MODULE,
4965 .open = i915_dpcd_open,
4966 .read = seq_read,
4967 .llseek = seq_lseek,
4968 .release = single_release,
4969};
4970
4971/**
4972 * i915_debugfs_connector_add - add i915 specific connector debugfs files
4973 * @connector: pointer to a registered drm_connector
4974 *
4975 * Cleanup will be done by drm_connector_unregister() through a call to
4976 * drm_debugfs_connector_remove().
4977 *
4978 * Returns 0 on success, negative error codes on error.
4979 */
4980int i915_debugfs_connector_add(struct drm_connector *connector)
4981{
4982 struct dentry *root = connector->debugfs_entry;
4983
4984 /* The connector must have been registered beforehands. */
4985 if (!root)
4986 return -ENODEV;
4987
4988 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4989 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4990 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
4991 &i915_dpcd_fops);
4992
4993 return 0;
4994}
Linux kernel - Deliverables
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