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drm/i915: Rename intel_engine_cs function parameters
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
497666d8
DL		 49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
70d39fe4
CW		 75static int i915_capabilities(struct seq_file *m, void *data)
76{
9f25d007 77 struct drm_info_node *node = m->private;
70d39fe4
CW		 78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
70d39fe4
CW		 88
89 return 0;
90}
2017263e 91
05394f39 92static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 93{
baaa5cfb 94 if (obj->pin_display)
a6172a80
CW		 95 return "p";
96 else
97 return " ";
98}
99
05394f39 100static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 101{
0206e353
AJ		 102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
a6172a80
CW		 108}
109
1d693bcc
BW		 110static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111{
aff43766 112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 113}
114
ca1543be
TU		 115static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116{
117 u64 size = 0;
118 struct i915_vma *vma;
119
1c7f4bca 120 list_for_each_entry(vma, &obj->vma_list, obj_link) {
596c5923 121 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
ca1543be
TU		 122 size += vma->node.size;
123 }
124
125 return size;
126}
127
37811fcc
CW		 128static void
129describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
130{
b4716185 131 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
e2f80391 132 struct intel_engine_cs *engine;
1d693bcc 133 struct i915_vma *vma;
d7f46fc4 134 int pin_count = 0;
b4716185 135 int i;
d7f46fc4 136
b4716185 137 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 138 &obj->base,
481a3d43 139 obj->active ? "*" : " ",
37811fcc
CW		 140 get_pin_flag(obj),
141 get_tiling_flag(obj),
1d693bcc 142 get_global_flag(obj),
a05a5862 143 obj->base.size / 1024,
37811fcc 144 obj->base.read_domains,
b4716185 145 obj->base.write_domain);
e2f80391 146 for_each_ring(engine, dev_priv, i)
b4716185
CW		 147 seq_printf(m, "%x ",
148 i915_gem_request_get_seqno(obj->last_read_req[i]));
149 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 150 i915_gem_request_get_seqno(obj->last_write_req),
151 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 152 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 153 obj->dirty ? " dirty" : "",
154 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
155 if (obj->base.name)
156 seq_printf(m, " (name: %d)", obj->base.name);
1c7f4bca 157 list_for_each_entry(vma, &obj->vma_list, obj_link) {
d7f46fc4
BW		 158 if (vma->pin_count > 0)
159 pin_count++;
ba0635ff
DC		 160 }
161 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 162 if (obj->pin_display)
163 seq_printf(m, " (display)");
37811fcc
CW		 164 if (obj->fence_reg != I915_FENCE_REG_NONE)
165 seq_printf(m, " (fence: %d)", obj->fence_reg);
1c7f4bca 166 list_for_each_entry(vma, &obj->vma_list, obj_link) {
8d2fdc3f 167 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
596c5923 168 vma->is_ggtt ? "g" : "pp",
8d2fdc3f 169 vma->node.start, vma->node.size);
596c5923
CW		 170 if (vma->is_ggtt)
171 seq_printf(m, ", type: %u", vma->ggtt_view.type);
172 seq_puts(m, ")");
1d693bcc 173 }
c1ad11fc 174 if (obj->stolen)
440fd528 175 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 176 if (obj->pin_display || obj->fault_mappable) {
6299f992 177 char s[3], *t = s;
30154650 178 if (obj->pin_display)
6299f992
CW		 179 *t++ = 'p';
180 if (obj->fault_mappable)
181 *t++ = 'f';
182 *t = '\0';
183 seq_printf(m, " (%s mappable)", s);
184 }
b4716185 185 if (obj->last_write_req != NULL)
41c52415 186 seq_printf(m, " (%s)",
b4716185 187 i915_gem_request_get_ring(obj->last_write_req)->name);
d5a81ef1
DV		 188 if (obj->frontbuffer_bits)
189 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 190}
191
273497e5 192static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 193{
ea0c76f8 194 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 195 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
196 seq_putc(m, ' ');
197}
198
433e12f7 199static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 200{
9f25d007 201 struct drm_info_node *node = m->private;
433e12f7
BG		 202 uintptr_t list = (uintptr_t) node->info_ent->data;
203 struct list_head *head;
2017263e 204 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 205 struct drm_i915_private *dev_priv = dev->dev_private;
206 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 207 struct i915_vma *vma;
c44ef60e 208 u64 total_obj_size, total_gtt_size;
8f2480fb 209 int count, ret;
de227ef0
CW		 210
211 ret = mutex_lock_interruptible(&dev->struct_mutex);
212 if (ret)
213 return ret;
2017263e 214
ca191b13 215 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 216 switch (list) {
217 case ACTIVE_LIST:
267f0c90 218 seq_puts(m, "Active:\n");
5cef07e1 219 head = &vm->active_list;
433e12f7
BG		 220 break;
221 case INACTIVE_LIST:
267f0c90 222 seq_puts(m, "Inactive:\n");
5cef07e1 223 head = &vm->inactive_list;
433e12f7 224 break;
433e12f7 225 default:
de227ef0
CW		 226 mutex_unlock(&dev->struct_mutex);
227 return -EINVAL;
2017263e 228 }
2017263e 229
8f2480fb 230 total_obj_size = total_gtt_size = count = 0;
1c7f4bca 231 list_for_each_entry(vma, head, vm_link) {
ca191b13
BW		 232 seq_printf(m, " ");
233 describe_obj(m, vma->obj);
234 seq_printf(m, "\n");
235 total_obj_size += vma->obj->base.size;
236 total_gtt_size += vma->node.size;
8f2480fb 237 count++;
2017263e 238 }
de227ef0 239 mutex_unlock(&dev->struct_mutex);
5e118f41 240
c44ef60e 241 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 242 count, total_obj_size, total_gtt_size);
2017263e
BG		 243 return 0;
244}
245
6d2b8885
CW		 246static int obj_rank_by_stolen(void *priv,
247 struct list_head *A, struct list_head *B)
248{
249 struct drm_i915_gem_object *a =
b25cb2f8 250 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 251 struct drm_i915_gem_object *b =
b25cb2f8 252 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 253
2d05fa16
RV		 254 if (a->stolen->start < b->stolen->start)
255 return -1;
256 if (a->stolen->start > b->stolen->start)
257 return 1;
258 return 0;
6d2b8885
CW		 259}
260
261static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
262{
9f25d007 263 struct drm_info_node *node = m->private;
6d2b8885
CW		 264 struct drm_device *dev = node->minor->dev;
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 struct drm_i915_gem_object *obj;
c44ef60e 267 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 268 LIST_HEAD(stolen);
269 int count, ret;
270
271 ret = mutex_lock_interruptible(&dev->struct_mutex);
272 if (ret)
273 return ret;
274
275 total_obj_size = total_gtt_size = count = 0;
276 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
277 if (obj->stolen == NULL)
278 continue;
279
b25cb2f8 280 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 281
282 total_obj_size += obj->base.size;
ca1543be 283 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 284 count++;
285 }
286 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
287 if (obj->stolen == NULL)
288 continue;
289
b25cb2f8 290 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 291
292 total_obj_size += obj->base.size;
293 count++;
294 }
295 list_sort(NULL, &stolen, obj_rank_by_stolen);
296 seq_puts(m, "Stolen:\n");
297 while (!list_empty(&stolen)) {
b25cb2f8 298 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 299 seq_puts(m, " ");
300 describe_obj(m, obj);
301 seq_putc(m, '\n');
b25cb2f8 302 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 303 }
304 mutex_unlock(&dev->struct_mutex);
305
c44ef60e 306 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 307 count, total_obj_size, total_gtt_size);
308 return 0;
309}
310
6299f992
CW		 311#define count_objects(list, member) do { \
312 list_for_each_entry(obj, list, member) { \
ca1543be 313 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 314 ++count; \
315 if (obj->map_and_fenceable) { \
f343c5f6 316 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 317 ++mappable_count; \
318 } \
319 } \
0206e353 320} while (0)
6299f992 321
2db8e9d6 322struct file_stats {
6313c204 323 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 324 unsigned long count;
325 u64 total, unbound;
326 u64 global, shared;
327 u64 active, inactive;
2db8e9d6
CW		 328};
329
330static int per_file_stats(int id, void *ptr, void *data)
331{
332 struct drm_i915_gem_object *obj = ptr;
333 struct file_stats *stats = data;
6313c204 334 struct i915_vma *vma;
2db8e9d6
CW		 335
336 stats->count++;
337 stats->total += obj->base.size;
338
c67a17e9
CW		 339 if (obj->base.name || obj->base.dma_buf)
340 stats->shared += obj->base.size;
341
6313c204 342 if (USES_FULL_PPGTT(obj->base.dev)) {
1c7f4bca 343 list_for_each_entry(vma, &obj->vma_list, obj_link) {
6313c204
CW		 344 struct i915_hw_ppgtt *ppgtt;
345
346 if (!drm_mm_node_allocated(&vma->node))
347 continue;
348
596c5923 349 if (vma->is_ggtt) {
6313c204
CW		 350 stats->global += obj->base.size;
351 continue;
352 }
353
354 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 355 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 356 continue;
357
41c52415 358 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 359 stats->active += obj->base.size;
360 else
361 stats->inactive += obj->base.size;
362
363 return 0;
364 }
2db8e9d6 365 } else {
6313c204
CW		 366 if (i915_gem_obj_ggtt_bound(obj)) {
367 stats->global += obj->base.size;
41c52415 368 if (obj->active)
6313c204
CW		 369 stats->active += obj->base.size;
370 else
371 stats->inactive += obj->base.size;
372 return 0;
373 }
2db8e9d6
CW		 374 }
375
6313c204
CW		 376 if (!list_empty(&obj->global_list))
377 stats->unbound += obj->base.size;
378
2db8e9d6
CW		 379 return 0;
380}
381
b0da1b79
CW		 382#define print_file_stats(m, name, stats) do { \
383 if (stats.count) \
c44ef60e 384 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 385 name, \
386 stats.count, \
387 stats.total, \
388 stats.active, \
389 stats.inactive, \
390 stats.global, \
391 stats.shared, \
392 stats.unbound); \
393} while (0)
493018dc
BV		 394
395static void print_batch_pool_stats(struct seq_file *m,
396 struct drm_i915_private *dev_priv)
397{
398 struct drm_i915_gem_object *obj;
399 struct file_stats stats;
e2f80391 400 struct intel_engine_cs *engine;
8d9d5744 401 int i, j;
493018dc
BV		 402
403 memset(&stats, 0, sizeof(stats));
404
e2f80391
TU		 405 for_each_ring(engine, dev_priv, i) {
406 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744 407 list_for_each_entry(obj,
e2f80391 408 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 409 batch_pool_link)
410 per_file_stats(0, obj, &stats);
411 }
06fbca71 412 }
493018dc 413
b0da1b79 414 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 415}
416
ca191b13
BW		 417#define count_vmas(list, member) do { \
418 list_for_each_entry(vma, list, member) { \
ca1543be 419 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 420 ++count; \
421 if (vma->obj->map_and_fenceable) { \
422 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
423 ++mappable_count; \
424 } \
425 } \
426} while (0)
427
428static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 429{
9f25d007 430 struct drm_info_node *node = m->private;
73aa808f
CW		 431 struct drm_device *dev = node->minor->dev;
432 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714 433 u32 count, mappable_count, purgeable_count;
c44ef60e 434 u64 size, mappable_size, purgeable_size;
6299f992 435 struct drm_i915_gem_object *obj;
5cef07e1 436 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 437 struct drm_file *file;
ca191b13 438 struct i915_vma *vma;
73aa808f
CW		 439 int ret;
440
441 ret = mutex_lock_interruptible(&dev->struct_mutex);
442 if (ret)
443 return ret;
444
6299f992
CW		 445 seq_printf(m, "%u objects, %zu bytes\n",
446 dev_priv->mm.object_count,
447 dev_priv->mm.object_memory);
448
449 size = count = mappable_size = mappable_count = 0;
35c20a60 450 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 451 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 452 count, mappable_count, size, mappable_size);
453
454 size = count = mappable_size = mappable_count = 0;
1c7f4bca 455 count_vmas(&vm->active_list, vm_link);
c44ef60e 456 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 457 count, mappable_count, size, mappable_size);
458
6299f992 459 size = count = mappable_size = mappable_count = 0;
1c7f4bca 460 count_vmas(&vm->inactive_list, vm_link);
c44ef60e 461 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 462 count, mappable_count, size, mappable_size);
463
b7abb714 464 size = count = purgeable_size = purgeable_count = 0;
35c20a60 465 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 466 size += obj->base.size, ++count;
b7abb714
CW		 467 if (obj->madv == I915_MADV_DONTNEED)
468 purgeable_size += obj->base.size, ++purgeable_count;
469 }
c44ef60e 470 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 471
6299f992 472 size = count = mappable_size = mappable_count = 0;
35c20a60 473 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 474 if (obj->fault_mappable) {
f343c5f6 475 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 476 ++count;
477 }
30154650 478 if (obj->pin_display) {
f343c5f6 479 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 480 ++mappable_count;
481 }
b7abb714
CW		 482 if (obj->madv == I915_MADV_DONTNEED) {
483 purgeable_size += obj->base.size;
484 ++purgeable_count;
485 }
6299f992 486 }
c44ef60e 487 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 488 purgeable_count, purgeable_size);
c44ef60e 489 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 490 mappable_count, mappable_size);
c44ef60e 491 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992
CW		 492 count, size);
493
c44ef60e 494 seq_printf(m, "%llu [%llu] gtt total\n",
853ba5d2 495 dev_priv->gtt.base.total,
c44ef60e 496 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 497
493018dc
BV		 498 seq_putc(m, '\n');
499 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 500 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
501 struct file_stats stats;
3ec2f427 502 struct task_struct *task;
2db8e9d6
CW		 503
504 memset(&stats, 0, sizeof(stats));
6313c204 505 stats.file_priv = file->driver_priv;
5b5ffff0 506 spin_lock(&file->table_lock);
2db8e9d6 507 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 508 spin_unlock(&file->table_lock);
3ec2f427
TH		 509 /*
510 * Although we have a valid reference on file->pid, that does
511 * not guarantee that the task_struct who called get_pid() is
512 * still alive (e.g. get_pid(current) => fork() => exit()).
513 * Therefore, we need to protect this ->comm access using RCU.
514 */
515 rcu_read_lock();
516 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 517 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 518 rcu_read_unlock();
2db8e9d6
CW		 519 }
520
73aa808f
CW		 521 mutex_unlock(&dev->struct_mutex);
522
523 return 0;
524}
525
aee56cff 526static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 527{
9f25d007 528 struct drm_info_node *node = m->private;
08c18323 529 struct drm_device *dev = node->minor->dev;
1b50247a 530 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 531 struct drm_i915_private *dev_priv = dev->dev_private;
532 struct drm_i915_gem_object *obj;
c44ef60e 533 u64 total_obj_size, total_gtt_size;
08c18323
CW		 534 int count, ret;
535
536 ret = mutex_lock_interruptible(&dev->struct_mutex);
537 if (ret)
538 return ret;
539
540 total_obj_size = total_gtt_size = count = 0;
35c20a60 541 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 542 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 543 continue;
544
267f0c90 545 seq_puts(m, " ");
08c18323 546 describe_obj(m, obj);
267f0c90 547 seq_putc(m, '\n');
08c18323 548 total_obj_size += obj->base.size;
ca1543be 549 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 550 count++;
551 }
552
553 mutex_unlock(&dev->struct_mutex);
554
c44ef60e 555 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 556 count, total_obj_size, total_gtt_size);
557
558 return 0;
559}
560
4e5359cd
SF		 561static int i915_gem_pageflip_info(struct seq_file *m, void *data)
562{
9f25d007 563 struct drm_info_node *node = m->private;
4e5359cd 564 struct drm_device *dev = node->minor->dev;
d6bbafa1 565 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 566 struct intel_crtc *crtc;
8a270ebf
DV		 567 int ret;
568
569 ret = mutex_lock_interruptible(&dev->struct_mutex);
570 if (ret)
571 return ret;
4e5359cd 572
d3fcc808 573 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 574 const char pipe = pipe_name(crtc->pipe);
575 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 576 struct intel_unpin_work *work;
577
5e2d7afc 578 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 579 work = crtc->unpin_work;
580 if (work == NULL) {
9db4a9c7 581 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 582 pipe, plane);
583 } else {
d6bbafa1
CW		 584 u32 addr;
585
e7d841ca 586 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 587 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 588 pipe, plane);
589 } else {
9db4a9c7 590 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 591 pipe, plane);
592 }
3a8a946e 593 if (work->flip_queued_req) {
e2f80391 594 struct intel_engine_cs *engine = i915_gem_request_get_ring(work->flip_queued_req);
3a8a946e 595
20e28fba 596 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
e2f80391 597 engine->name,
f06cc1b9 598 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 599 dev_priv->next_seqno,
e2f80391 600 engine->get_seqno(engine, true),
1b5a433a 601 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 602 } else
603 seq_printf(m, "Flip not associated with any ring\n");
604 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
605 work->flip_queued_vblank,
606 work->flip_ready_vblank,
1e3feefd 607 drm_crtc_vblank_count(&crtc->base));
4e5359cd 608 if (work->enable_stall_check)
267f0c90 609 seq_puts(m, "Stall check enabled, ");
4e5359cd 610 else
267f0c90 611 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 612 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 613
d6bbafa1
CW		 614 if (INTEL_INFO(dev)->gen >= 4)
615 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
616 else
617 addr = I915_READ(DSPADDR(crtc->plane));
618 seq_printf(m, "Current scanout address 0x%08x\n", addr);
619
4e5359cd 620 if (work->pending_flip_obj) {
d6bbafa1
CW		 621 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
622 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 623 }
624 }
5e2d7afc 625 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 626 }
627
8a270ebf
DV		 628 mutex_unlock(&dev->struct_mutex);
629
4e5359cd
SF		 630 return 0;
631}
632
493018dc
BV		 633static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
634{
635 struct drm_info_node *node = m->private;
636 struct drm_device *dev = node->minor->dev;
637 struct drm_i915_private *dev_priv = dev->dev_private;
638 struct drm_i915_gem_object *obj;
e2f80391 639 struct intel_engine_cs *engine;
8d9d5744
CW		 640 int total = 0;
641 int ret, i, j;
493018dc
BV		 642
643 ret = mutex_lock_interruptible(&dev->struct_mutex);
644 if (ret)
645 return ret;
646
e2f80391
TU		 647 for_each_ring(engine, dev_priv, i) {
648 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744
CW		 649 int count;
650
651 count = 0;
652 list_for_each_entry(obj,
e2f80391 653 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 654 batch_pool_link)
655 count++;
656 seq_printf(m, "%s cache[%d]: %d objects\n",
e2f80391 657 engine->name, j, count);
8d9d5744
CW		 658
659 list_for_each_entry(obj,
e2f80391 660 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 661 batch_pool_link) {
662 seq_puts(m, " ");
663 describe_obj(m, obj);
664 seq_putc(m, '\n');
665 }
666
667 total += count;
06fbca71 668 }
493018dc
BV		 669 }
670
8d9d5744 671 seq_printf(m, "total: %d\n", total);
493018dc
BV		 672
673 mutex_unlock(&dev->struct_mutex);
674
675 return 0;
676}
677
2017263e
BG		 678static int i915_gem_request_info(struct seq_file *m, void *data)
679{
9f25d007 680 struct drm_info_node *node = m->private;
2017263e 681 struct drm_device *dev = node->minor->dev;
e277a1f8 682 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 683 struct intel_engine_cs *engine;
eed29a5b 684 struct drm_i915_gem_request *req;
2d1070b2 685 int ret, any, i;
de227ef0
CW		 686
687 ret = mutex_lock_interruptible(&dev->struct_mutex);
688 if (ret)
689 return ret;
2017263e 690
2d1070b2 691 any = 0;
e2f80391 692 for_each_ring(engine, dev_priv, i) {
2d1070b2
CW		 693 int count;
694
695 count = 0;
e2f80391 696 list_for_each_entry(req, &engine->request_list, list)
2d1070b2
CW		 697 count++;
698 if (count == 0)
a2c7f6fd
CW		 699 continue;
700
e2f80391
TU		 701 seq_printf(m, "%s requests: %d\n", engine->name, count);
702 list_for_each_entry(req, &engine->request_list, list) {
2d1070b2
CW		 703 struct task_struct *task;
704
705 rcu_read_lock();
706 task = NULL;
eed29a5b
DV		 707 if (req->pid)
708 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 709 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 710 req->seqno,
711 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 712 task ? task->comm : "<unknown>",
713 task ? task->pid : -1);
714 rcu_read_unlock();
c2c347a9 715 }
2d1070b2
CW		 716
717 any++;
2017263e 718 }
de227ef0
CW		 719 mutex_unlock(&dev->struct_mutex);
720
2d1070b2 721 if (any == 0)
267f0c90 722 seq_puts(m, "No requests\n");
c2c347a9 723
2017263e
BG		 724 return 0;
725}
726
b2223497 727static void i915_ring_seqno_info(struct seq_file *m,
0bc40be8 728 struct intel_engine_cs *engine)
b2223497 729{
0bc40be8 730 if (engine->get_seqno) {
20e28fba 731 seq_printf(m, "Current sequence (%s): %x\n",
0bc40be8 732 engine->name, engine->get_seqno(engine, false));
b2223497
CW		 733 }
734}
735
2017263e
BG		 736static int i915_gem_seqno_info(struct seq_file *m, void *data)
737{
9f25d007 738 struct drm_info_node *node = m->private;
2017263e 739 struct drm_device *dev = node->minor->dev;
e277a1f8 740 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 741 struct intel_engine_cs *engine;
1ec14ad3 742 int ret, i;
de227ef0
CW		 743
744 ret = mutex_lock_interruptible(&dev->struct_mutex);
745 if (ret)
746 return ret;
c8c8fb33 747 intel_runtime_pm_get(dev_priv);
2017263e 748
e2f80391
TU		 749 for_each_ring(engine, dev_priv, i)
750 i915_ring_seqno_info(m, engine);
de227ef0 751
c8c8fb33 752 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 753 mutex_unlock(&dev->struct_mutex);
754
2017263e
BG		 755 return 0;
756}
757
758
759static int i915_interrupt_info(struct seq_file *m, void *data)
760{
9f25d007 761 struct drm_info_node *node = m->private;
2017263e 762 struct drm_device *dev = node->minor->dev;
e277a1f8 763 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 764 struct intel_engine_cs *engine;
9db4a9c7 765 int ret, i, pipe;
de227ef0
CW		 766
767 ret = mutex_lock_interruptible(&dev->struct_mutex);
768 if (ret)
769 return ret;
c8c8fb33 770 intel_runtime_pm_get(dev_priv);
2017263e 771
74e1ca8c 772 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 773 seq_printf(m, "Master Interrupt Control:\t%08x\n",
774 I915_READ(GEN8_MASTER_IRQ));
775
776 seq_printf(m, "Display IER:\t%08x\n",
777 I915_READ(VLV_IER));
778 seq_printf(m, "Display IIR:\t%08x\n",
779 I915_READ(VLV_IIR));
780 seq_printf(m, "Display IIR_RW:\t%08x\n",
781 I915_READ(VLV_IIR_RW));
782 seq_printf(m, "Display IMR:\t%08x\n",
783 I915_READ(VLV_IMR));
055e393f 784 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 785 seq_printf(m, "Pipe %c stat:\t%08x\n",
786 pipe_name(pipe),
787 I915_READ(PIPESTAT(pipe)));
788
789 seq_printf(m, "Port hotplug:\t%08x\n",
790 I915_READ(PORT_HOTPLUG_EN));
791 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
792 I915_READ(VLV_DPFLIPSTAT));
793 seq_printf(m, "DPINVGTT:\t%08x\n",
794 I915_READ(DPINVGTT));
795
796 for (i = 0; i < 4; i++) {
797 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
798 i, I915_READ(GEN8_GT_IMR(i)));
799 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
800 i, I915_READ(GEN8_GT_IIR(i)));
801 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
802 i, I915_READ(GEN8_GT_IER(i)));
803 }
804
805 seq_printf(m, "PCU interrupt mask:\t%08x\n",
806 I915_READ(GEN8_PCU_IMR));
807 seq_printf(m, "PCU interrupt identity:\t%08x\n",
808 I915_READ(GEN8_PCU_IIR));
809 seq_printf(m, "PCU interrupt enable:\t%08x\n",
810 I915_READ(GEN8_PCU_IER));
811 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 812 seq_printf(m, "Master Interrupt Control:\t%08x\n",
813 I915_READ(GEN8_MASTER_IRQ));
814
815 for (i = 0; i < 4; i++) {
816 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
817 i, I915_READ(GEN8_GT_IMR(i)));
818 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
819 i, I915_READ(GEN8_GT_IIR(i)));
820 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
821 i, I915_READ(GEN8_GT_IER(i)));
822 }
823
055e393f 824 for_each_pipe(dev_priv, pipe) {
e129649b
ID		 825 enum intel_display_power_domain power_domain;
826
827 power_domain = POWER_DOMAIN_PIPE(pipe);
828 if (!intel_display_power_get_if_enabled(dev_priv,
829 power_domain)) {
22c59960
PZ		 830 seq_printf(m, "Pipe %c power disabled\n",
831 pipe_name(pipe));
832 continue;
833 }
a123f157 834 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 835 pipe_name(pipe),
836 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 837 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 838 pipe_name(pipe),
839 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 840 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 841 pipe_name(pipe),
842 I915_READ(GEN8_DE_PIPE_IER(pipe)));
e129649b
ID		 843
844 intel_display_power_put(dev_priv, power_domain);
a123f157
BW		 845 }
846
847 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IMR));
849 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IIR));
851 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
852 I915_READ(GEN8_DE_PORT_IER));
853
854 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IMR));
856 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IIR));
858 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
859 I915_READ(GEN8_DE_MISC_IER));
860
861 seq_printf(m, "PCU interrupt mask:\t%08x\n",
862 I915_READ(GEN8_PCU_IMR));
863 seq_printf(m, "PCU interrupt identity:\t%08x\n",
864 I915_READ(GEN8_PCU_IIR));
865 seq_printf(m, "PCU interrupt enable:\t%08x\n",
866 I915_READ(GEN8_PCU_IER));
867 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 868 seq_printf(m, "Display IER:\t%08x\n",
869 I915_READ(VLV_IER));
870 seq_printf(m, "Display IIR:\t%08x\n",
871 I915_READ(VLV_IIR));
872 seq_printf(m, "Display IIR_RW:\t%08x\n",
873 I915_READ(VLV_IIR_RW));
874 seq_printf(m, "Display IMR:\t%08x\n",
875 I915_READ(VLV_IMR));
055e393f 876 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 877 seq_printf(m, "Pipe %c stat:\t%08x\n",
878 pipe_name(pipe),
879 I915_READ(PIPESTAT(pipe)));
880
881 seq_printf(m, "Master IER:\t%08x\n",
882 I915_READ(VLV_MASTER_IER));
883
884 seq_printf(m, "Render IER:\t%08x\n",
885 I915_READ(GTIER));
886 seq_printf(m, "Render IIR:\t%08x\n",
887 I915_READ(GTIIR));
888 seq_printf(m, "Render IMR:\t%08x\n",
889 I915_READ(GTIMR));
890
891 seq_printf(m, "PM IER:\t\t%08x\n",
892 I915_READ(GEN6_PMIER));
893 seq_printf(m, "PM IIR:\t\t%08x\n",
894 I915_READ(GEN6_PMIIR));
895 seq_printf(m, "PM IMR:\t\t%08x\n",
896 I915_READ(GEN6_PMIMR));
897
898 seq_printf(m, "Port hotplug:\t%08x\n",
899 I915_READ(PORT_HOTPLUG_EN));
900 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
901 I915_READ(VLV_DPFLIPSTAT));
902 seq_printf(m, "DPINVGTT:\t%08x\n",
903 I915_READ(DPINVGTT));
904
905 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 906 seq_printf(m, "Interrupt enable: %08x\n",
907 I915_READ(IER));
908 seq_printf(m, "Interrupt identity: %08x\n",
909 I915_READ(IIR));
910 seq_printf(m, "Interrupt mask: %08x\n",
911 I915_READ(IMR));
055e393f 912 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 913 seq_printf(m, "Pipe %c stat: %08x\n",
914 pipe_name(pipe),
915 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 916 } else {
917 seq_printf(m, "North Display Interrupt enable: %08x\n",
918 I915_READ(DEIER));
919 seq_printf(m, "North Display Interrupt identity: %08x\n",
920 I915_READ(DEIIR));
921 seq_printf(m, "North Display Interrupt mask: %08x\n",
922 I915_READ(DEIMR));
923 seq_printf(m, "South Display Interrupt enable: %08x\n",
924 I915_READ(SDEIER));
925 seq_printf(m, "South Display Interrupt identity: %08x\n",
926 I915_READ(SDEIIR));
927 seq_printf(m, "South Display Interrupt mask: %08x\n",
928 I915_READ(SDEIMR));
929 seq_printf(m, "Graphics Interrupt enable: %08x\n",
930 I915_READ(GTIER));
931 seq_printf(m, "Graphics Interrupt identity: %08x\n",
932 I915_READ(GTIIR));
933 seq_printf(m, "Graphics Interrupt mask: %08x\n",
934 I915_READ(GTIMR));
935 }
e2f80391 936 for_each_ring(engine, dev_priv, i) {
a123f157 937 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 938 seq_printf(m,
939 "Graphics Interrupt mask (%s): %08x\n",
e2f80391 940 engine->name, I915_READ_IMR(engine));
9862e600 941 }
e2f80391 942 i915_ring_seqno_info(m, engine);
9862e600 943 }
c8c8fb33 944 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 945 mutex_unlock(&dev->struct_mutex);
946
2017263e
BG		 947 return 0;
948}
949
a6172a80
CW		 950static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
951{
9f25d007 952 struct drm_info_node *node = m->private;
a6172a80 953 struct drm_device *dev = node->minor->dev;
e277a1f8 954 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 955 int i, ret;
956
957 ret = mutex_lock_interruptible(&dev->struct_mutex);
958 if (ret)
959 return ret;
a6172a80 960
a6172a80
CW		 961 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
962 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 963 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 964
6c085a72
CW		 965 seq_printf(m, "Fence %d, pin count = %d, object = ",
966 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 967 if (obj == NULL)
267f0c90 968 seq_puts(m, "unused");
c2c347a9 969 else
05394f39 970 describe_obj(m, obj);
267f0c90 971 seq_putc(m, '\n');
a6172a80
CW		 972 }
973
05394f39 974 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 975 return 0;
976}
977
2017263e
BG		 978static int i915_hws_info(struct seq_file *m, void *data)
979{
9f25d007 980 struct drm_info_node *node = m->private;
2017263e 981 struct drm_device *dev = node->minor->dev;
e277a1f8 982 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 983 struct intel_engine_cs *engine;
1a240d4d 984 const u32 *hws;
4066c0ae
CW		 985 int i;
986
e2f80391
TU		 987 engine = &dev_priv->ring[(uintptr_t)node->info_ent->data];
988 hws = engine->status_page.page_addr;
2017263e
BG		 989 if (hws == NULL)
990 return 0;
991
992 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
993 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
994 i * 4,
995 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
996 }
997 return 0;
998}
999
d5442303
DV		 1000static ssize_t
1001i915_error_state_write(struct file *filp,
1002 const char __user *ubuf,
1003 size_t cnt,
1004 loff_t *ppos)
1005{
edc3d884 1006 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1007 struct drm_device *dev = error_priv->dev;
22bcfc6a 1008 int ret;
d5442303
DV		 1009
1010 DRM_DEBUG_DRIVER("Resetting error state\n");
1011
22bcfc6a
DV		 1012 ret = mutex_lock_interruptible(&dev->struct_mutex);
1013 if (ret)
1014 return ret;
1015
d5442303
DV		 1016 i915_destroy_error_state(dev);
1017 mutex_unlock(&dev->struct_mutex);
1018
1019 return cnt;
1020}
1021
1022static int i915_error_state_open(struct inode *inode, struct file *file)
1023{
1024 struct drm_device *dev = inode->i_private;
d5442303 1025 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1026
1027 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1028 if (!error_priv)
1029 return -ENOMEM;
1030
1031 error_priv->dev = dev;
1032
95d5bfb3 1033 i915_error_state_get(dev, error_priv);
d5442303 1034
edc3d884
MK		 1035 file->private_data = error_priv;
1036
1037 return 0;
d5442303
DV		 1038}
1039
1040static int i915_error_state_release(struct inode *inode, struct file *file)
1041{
edc3d884 1042 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1043
95d5bfb3 1044 i915_error_state_put(error_priv);
d5442303
DV		 1045 kfree(error_priv);
1046
edc3d884
MK		 1047 return 0;
1048}
1049
4dc955f7
MK		 1050static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1051 size_t count, loff_t *pos)
1052{
1053 struct i915_error_state_file_priv *error_priv = file->private_data;
1054 struct drm_i915_error_state_buf error_str;
1055 loff_t tmp_pos = 0;
1056 ssize_t ret_count = 0;
1057 int ret;
1058
0a4cd7c8 1059 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1060 if (ret)
1061 return ret;
edc3d884 1062
fc16b48b 1063 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1064 if (ret)
1065 goto out;
1066
edc3d884
MK		 1067 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1068 error_str.buf,
1069 error_str.bytes);
1070
1071 if (ret_count < 0)
1072 ret = ret_count;
1073 else
1074 *pos = error_str.start + ret_count;
1075out:
4dc955f7 1076 i915_error_state_buf_release(&error_str);
edc3d884 1077 return ret ?: ret_count;
d5442303
DV		 1078}
1079
1080static const struct file_operations i915_error_state_fops = {
1081 .owner = THIS_MODULE,
1082 .open = i915_error_state_open,
edc3d884 1083 .read = i915_error_state_read,
d5442303
DV		 1084 .write = i915_error_state_write,
1085 .llseek = default_llseek,
1086 .release = i915_error_state_release,
1087};
1088
647416f9
KC		 1089static int
1090i915_next_seqno_get(void *data, u64 *val)
40633219 1091{
647416f9 1092 struct drm_device *dev = data;
e277a1f8 1093 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1094 int ret;
1095
1096 ret = mutex_lock_interruptible(&dev->struct_mutex);
1097 if (ret)
1098 return ret;
1099
647416f9 1100 *val = dev_priv->next_seqno;
40633219
MK		 1101 mutex_unlock(&dev->struct_mutex);
1102
647416f9 1103 return 0;
40633219
MK		 1104}
1105
647416f9
KC		 1106static int
1107i915_next_seqno_set(void *data, u64 val)
1108{
1109 struct drm_device *dev = data;
40633219
MK		 1110 int ret;
1111
40633219
MK		 1112 ret = mutex_lock_interruptible(&dev->struct_mutex);
1113 if (ret)
1114 return ret;
1115
e94fbaa8 1116 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1117 mutex_unlock(&dev->struct_mutex);
1118
647416f9 1119 return ret;
40633219
MK		 1120}
1121
647416f9
KC		 1122DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1123 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1124 "0x%llx\n");
40633219 1125
adb4bd12 1126static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1127{
9f25d007 1128 struct drm_info_node *node = m->private;
f97108d1 1129 struct drm_device *dev = node->minor->dev;
e277a1f8 1130 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1131 int ret = 0;
1132
1133 intel_runtime_pm_get(dev_priv);
3b8d8d91 1134
5c9669ce
TR		 1135 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1136
3b8d8d91
JB		 1137 if (IS_GEN5(dev)) {
1138 u16 rgvswctl = I915_READ16(MEMSWCTL);
1139 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1140
1141 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1142 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1143 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1144 MEMSTAT_VID_SHIFT);
1145 seq_printf(m, "Current P-state: %d\n",
1146 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
666a4537
WB		 1147 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1148 u32 freq_sts;
1149
1150 mutex_lock(&dev_priv->rps.hw_lock);
1151 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1152 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1153 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1154
1155 seq_printf(m, "actual GPU freq: %d MHz\n",
1156 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1157
1158 seq_printf(m, "current GPU freq: %d MHz\n",
1159 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1160
1161 seq_printf(m, "max GPU freq: %d MHz\n",
1162 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1163
1164 seq_printf(m, "min GPU freq: %d MHz\n",
1165 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1166
1167 seq_printf(m, "idle GPU freq: %d MHz\n",
1168 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1169
1170 seq_printf(m,
1171 "efficient (RPe) frequency: %d MHz\n",
1172 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1173 mutex_unlock(&dev_priv->rps.hw_lock);
1174 } else if (INTEL_INFO(dev)->gen >= 6) {
35040562
BP		 1175 u32 rp_state_limits;
1176 u32 gt_perf_status;
1177 u32 rp_state_cap;
0d8f9491 1178 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1179 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1180 u32 rpupei, rpcurup, rpprevup;
1181 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1182 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1183 int max_freq;
1184
35040562
BP		 1185 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1186 if (IS_BROXTON(dev)) {
1187 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1188 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1189 } else {
1190 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1191 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1192 }
1193
3b8d8d91 1194 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1195 ret = mutex_lock_interruptible(&dev->struct_mutex);
1196 if (ret)
c8c8fb33 1197 goto out;
d1ebd816 1198
59bad947 1199 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1200
8e8c06cd 1201 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1202 if (IS_GEN9(dev))
1203 reqf >>= 23;
1204 else {
1205 reqf &= ~GEN6_TURBO_DISABLE;
1206 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1207 reqf >>= 24;
1208 else
1209 reqf >>= 25;
1210 }
7c59a9c1 1211 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1212
0d8f9491
CW		 1213 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1214 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1215 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1216
ccab5c82
JB		 1217 rpstat = I915_READ(GEN6_RPSTAT1);
1218 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1219 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1220 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1221 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1222 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1223 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1224 if (IS_GEN9(dev))
1225 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1226 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1227 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1228 else
1229 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1230 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1231
59bad947 1232 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1233 mutex_unlock(&dev->struct_mutex);
1234
9dd3c605
PZ		 1235 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1236 pm_ier = I915_READ(GEN6_PMIER);
1237 pm_imr = I915_READ(GEN6_PMIMR);
1238 pm_isr = I915_READ(GEN6_PMISR);
1239 pm_iir = I915_READ(GEN6_PMIIR);
1240 pm_mask = I915_READ(GEN6_PMINTRMSK);
1241 } else {
1242 pm_ier = I915_READ(GEN8_GT_IER(2));
1243 pm_imr = I915_READ(GEN8_GT_IMR(2));
1244 pm_isr = I915_READ(GEN8_GT_ISR(2));
1245 pm_iir = I915_READ(GEN8_GT_IIR(2));
1246 pm_mask = I915_READ(GEN6_PMINTRMSK);
1247 }
0d8f9491 1248 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1249 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1250 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1251 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1252 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1253 seq_printf(m, "Render p-state VID: %d\n",
1254 gt_perf_status & 0xff);
1255 seq_printf(m, "Render p-state limit: %d\n",
1256 rp_state_limits & 0xff);
0d8f9491
CW		 1257 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1258 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1259 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1260 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1261 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1262 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1263 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1264 GEN6_CURICONT_MASK);
1265 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1266 GEN6_CURBSYTAVG_MASK);
1267 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1268 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1269 seq_printf(m, "Up threshold: %d%%\n",
1270 dev_priv->rps.up_threshold);
1271
ccab5c82
JB		 1272 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1273 GEN6_CURIAVG_MASK);
1274 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1275 GEN6_CURBSYTAVG_MASK);
1276 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1277 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1278 seq_printf(m, "Down threshold: %d%%\n",
1279 dev_priv->rps.down_threshold);
3b8d8d91 1280
35040562
BP		 1281 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1282 rp_state_cap >> 16) & 0xff;
ef11bdb3
RV		 1283 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1284 GEN9_FREQ_SCALER : 1);
3b8d8d91 1285 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1286 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1287
1288 max_freq = (rp_state_cap & 0xff00) >> 8;
ef11bdb3
RV		 1289 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1290 GEN9_FREQ_SCALER : 1);
3b8d8d91 1291 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1292 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1293
35040562
BP		 1294 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1295 rp_state_cap >> 0) & 0xff;
ef11bdb3
RV		 1296 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1297 GEN9_FREQ_SCALER : 1);
3b8d8d91 1298 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1299 intel_gpu_freq(dev_priv, max_freq));
31c77388 1300 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1301 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1302
d86ed34a
CW		 1303 seq_printf(m, "Current freq: %d MHz\n",
1304 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1305 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1306 seq_printf(m, "Idle freq: %d MHz\n",
1307 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1308 seq_printf(m, "Min freq: %d MHz\n",
1309 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1310 seq_printf(m, "Max freq: %d MHz\n",
1311 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1312 seq_printf(m,
1313 "efficient (RPe) frequency: %d MHz\n",
1314 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
3b8d8d91 1315 } else {
267f0c90 1316 seq_puts(m, "no P-state info available\n");
3b8d8d91 1317 }
f97108d1 1318
1170f28c
MK		 1319 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1320 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1321 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1322
c8c8fb33
PZ		 1323out:
1324 intel_runtime_pm_put(dev_priv);
1325 return ret;
f97108d1
JB		 1326}
1327
f654449a
CW		 1328static int i915_hangcheck_info(struct seq_file *m, void *unused)
1329{
1330 struct drm_info_node *node = m->private;
ebbc7546
MK		 1331 struct drm_device *dev = node->minor->dev;
1332 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1333 struct intel_engine_cs *engine;
ebbc7546
MK		 1334 u64 acthd[I915_NUM_RINGS];
1335 u32 seqno[I915_NUM_RINGS];
61642ff0
MK		 1336 u32 instdone[I915_NUM_INSTDONE_REG];
1337 int i, j;
f654449a
CW		 1338
1339 if (!i915.enable_hangcheck) {
1340 seq_printf(m, "Hangcheck disabled\n");
1341 return 0;
1342 }
1343
ebbc7546
MK		 1344 intel_runtime_pm_get(dev_priv);
1345
e2f80391
TU		 1346 for_each_ring(engine, dev_priv, i) {
1347 seqno[i] = engine->get_seqno(engine, false);
1348 acthd[i] = intel_ring_get_active_head(engine);
ebbc7546
MK		 1349 }
1350
61642ff0
MK		 1351 i915_get_extra_instdone(dev, instdone);
1352
ebbc7546
MK		 1353 intel_runtime_pm_put(dev_priv);
1354
f654449a
CW		 1355 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1356 seq_printf(m, "Hangcheck active, fires in %dms\n",
1357 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1358 jiffies));
1359 } else
1360 seq_printf(m, "Hangcheck inactive\n");
1361
e2f80391
TU		 1362 for_each_ring(engine, dev_priv, i) {
1363 seq_printf(m, "%s:\n", engine->name);
f654449a 1364 seq_printf(m, "\tseqno = %x [current %x]\n",
e2f80391 1365 engine->hangcheck.seqno, seqno[i]);
f654449a 1366 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
e2f80391 1367 (long long)engine->hangcheck.acthd,
ebbc7546 1368 (long long)acthd[i]);
e2f80391
TU		 1369 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1370 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
61642ff0 1371
e2f80391 1372 if (engine->id == RCS) {
61642ff0
MK		 1373 seq_puts(m, "\tinstdone read =");
1374
1375 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1376 seq_printf(m, " 0x%08x", instdone[j]);
1377
1378 seq_puts(m, "\n\tinstdone accu =");
1379
1380 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1381 seq_printf(m, " 0x%08x",
e2f80391 1382 engine->hangcheck.instdone[j]);
61642ff0
MK		 1383
1384 seq_puts(m, "\n");
1385 }
f654449a
CW		 1386 }
1387
1388 return 0;
1389}
1390
4d85529d 1391static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1392{
9f25d007 1393 struct drm_info_node *node = m->private;
f97108d1 1394 struct drm_device *dev = node->minor->dev;
e277a1f8 1395 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1396 u32 rgvmodectl, rstdbyctl;
1397 u16 crstandvid;
1398 int ret;
1399
1400 ret = mutex_lock_interruptible(&dev->struct_mutex);
1401 if (ret)
1402 return ret;
c8c8fb33 1403 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1404
1405 rgvmodectl = I915_READ(MEMMODECTL);
1406 rstdbyctl = I915_READ(RSTDBYCTL);
1407 crstandvid = I915_READ16(CRSTANDVID);
1408
c8c8fb33 1409 intel_runtime_pm_put(dev_priv);
616fdb5a 1410 mutex_unlock(&dev->struct_mutex);
f97108d1 1411
742f491d 1412 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1413 seq_printf(m, "Boost freq: %d\n",
1414 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1415 MEMMODE_BOOST_FREQ_SHIFT);
1416 seq_printf(m, "HW control enabled: %s\n",
742f491d 1417 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1418 seq_printf(m, "SW control enabled: %s\n",
742f491d 1419 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1420 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1421 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1422 seq_printf(m, "Starting frequency: P%d\n",
1423 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1424 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1425 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1426 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1427 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1428 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1429 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1430 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1431 seq_puts(m, "Current RS state: ");
88271da3
JB		 1432 switch (rstdbyctl & RSX_STATUS_MASK) {
1433 case RSX_STATUS_ON:
267f0c90 1434 seq_puts(m, "on\n");
88271da3
JB		 1435 break;
1436 case RSX_STATUS_RC1:
267f0c90 1437 seq_puts(m, "RC1\n");
88271da3
JB		 1438 break;
1439 case RSX_STATUS_RC1E:
267f0c90 1440 seq_puts(m, "RC1E\n");
88271da3
JB		 1441 break;
1442 case RSX_STATUS_RS1:
267f0c90 1443 seq_puts(m, "RS1\n");
88271da3
JB		 1444 break;
1445 case RSX_STATUS_RS2:
267f0c90 1446 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1447 break;
1448 case RSX_STATUS_RS3:
267f0c90 1449 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1450 break;
1451 default:
267f0c90 1452 seq_puts(m, "unknown\n");
88271da3
JB		 1453 break;
1454 }
f97108d1
JB		 1455
1456 return 0;
1457}
1458
f65367b5 1459static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1460{
b2cff0db
CW		 1461 struct drm_info_node *node = m->private;
1462 struct drm_device *dev = node->minor->dev;
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1465 int i;
1466
1467 spin_lock_irq(&dev_priv->uncore.lock);
1468 for_each_fw_domain(fw_domain, dev_priv, i) {
1469 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1470 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1471 fw_domain->wake_count);
1472 }
1473 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1474
b2cff0db
CW		 1475 return 0;
1476}
1477
1478static int vlv_drpc_info(struct seq_file *m)
1479{
9f25d007 1480 struct drm_info_node *node = m->private;
669ab5aa
D		 1481 struct drm_device *dev = node->minor->dev;
1482 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1483 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1484
d46c0517
ID		 1485 intel_runtime_pm_get(dev_priv);
1486
6b312cd3 1487 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1488 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1489 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1490
d46c0517
ID		 1491 intel_runtime_pm_put(dev_priv);
1492
669ab5aa
D		 1493 seq_printf(m, "Video Turbo Mode: %s\n",
1494 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1495 seq_printf(m, "Turbo enabled: %s\n",
1496 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1497 seq_printf(m, "HW control enabled: %s\n",
1498 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1499 seq_printf(m, "SW control enabled: %s\n",
1500 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1501 GEN6_RP_MEDIA_SW_MODE));
1502 seq_printf(m, "RC6 Enabled: %s\n",
1503 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1504 GEN6_RC_CTL_EI_MODE(1))));
1505 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1506 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1507 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1508 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1509
9cc19be5
ID		 1510 seq_printf(m, "Render RC6 residency since boot: %u\n",
1511 I915_READ(VLV_GT_RENDER_RC6));
1512 seq_printf(m, "Media RC6 residency since boot: %u\n",
1513 I915_READ(VLV_GT_MEDIA_RC6));
1514
f65367b5 1515 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1516}
1517
4d85529d
BW		 1518static int gen6_drpc_info(struct seq_file *m)
1519{
9f25d007 1520 struct drm_info_node *node = m->private;
4d85529d
BW		 1521 struct drm_device *dev = node->minor->dev;
1522 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1523 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1524 unsigned forcewake_count;
aee56cff 1525 int count = 0, ret;
4d85529d
BW		 1526
1527 ret = mutex_lock_interruptible(&dev->struct_mutex);
1528 if (ret)
1529 return ret;
c8c8fb33 1530 intel_runtime_pm_get(dev_priv);
4d85529d 1531
907b28c5 1532 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1533 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1534 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1535
1536 if (forcewake_count) {
267f0c90
DL		 1537 seq_puts(m, "RC information inaccurate because somebody "
1538 "holds a forcewake reference \n");
4d85529d
BW		 1539 } else {
1540 /* NB: we cannot use forcewake, else we read the wrong values */
1541 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1542 udelay(10);
1543 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1544 }
1545
75aa3f63 1546 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
ed71f1b4 1547 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1548
1549 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1550 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1551 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1552 mutex_lock(&dev_priv->rps.hw_lock);
1553 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1554 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1555
c8c8fb33
PZ		 1556 intel_runtime_pm_put(dev_priv);
1557
4d85529d
BW		 1558 seq_printf(m, "Video Turbo Mode: %s\n",
1559 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1560 seq_printf(m, "HW control enabled: %s\n",
1561 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1562 seq_printf(m, "SW control enabled: %s\n",
1563 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1564 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1565 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1566 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1567 seq_printf(m, "RC6 Enabled: %s\n",
1568 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1569 seq_printf(m, "Deep RC6 Enabled: %s\n",
1570 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1571 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1572 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1573 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1574 switch (gt_core_status & GEN6_RCn_MASK) {
1575 case GEN6_RC0:
1576 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1577 seq_puts(m, "Core Power Down\n");
4d85529d 1578 else
267f0c90 1579 seq_puts(m, "on\n");
4d85529d
BW		 1580 break;
1581 case GEN6_RC3:
267f0c90 1582 seq_puts(m, "RC3\n");
4d85529d
BW		 1583 break;
1584 case GEN6_RC6:
267f0c90 1585 seq_puts(m, "RC6\n");
4d85529d
BW		 1586 break;
1587 case GEN6_RC7:
267f0c90 1588 seq_puts(m, "RC7\n");
4d85529d
BW		 1589 break;
1590 default:
267f0c90 1591 seq_puts(m, "Unknown\n");
4d85529d
BW		 1592 break;
1593 }
1594
1595 seq_printf(m, "Core Power Down: %s\n",
1596 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1597
1598 /* Not exactly sure what this is */
1599 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1600 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1601 seq_printf(m, "RC6 residency since boot: %u\n",
1602 I915_READ(GEN6_GT_GFX_RC6));
1603 seq_printf(m, "RC6+ residency since boot: %u\n",
1604 I915_READ(GEN6_GT_GFX_RC6p));
1605 seq_printf(m, "RC6++ residency since boot: %u\n",
1606 I915_READ(GEN6_GT_GFX_RC6pp));
1607
ecd8faea
BW		 1608 seq_printf(m, "RC6 voltage: %dmV\n",
1609 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1610 seq_printf(m, "RC6+ voltage: %dmV\n",
1611 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1612 seq_printf(m, "RC6++ voltage: %dmV\n",
1613 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1614 return 0;
1615}
1616
1617static int i915_drpc_info(struct seq_file *m, void *unused)
1618{
9f25d007 1619 struct drm_info_node *node = m->private;
4d85529d
BW		 1620 struct drm_device *dev = node->minor->dev;
1621
666a4537 1622 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
669ab5aa 1623 return vlv_drpc_info(m);
ac66cf4b 1624 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1625 return gen6_drpc_info(m);
1626 else
1627 return ironlake_drpc_info(m);
1628}
1629
9a851789
DV		 1630static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1631{
1632 struct drm_info_node *node = m->private;
1633 struct drm_device *dev = node->minor->dev;
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635
1636 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1637 dev_priv->fb_tracking.busy_bits);
1638
1639 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1640 dev_priv->fb_tracking.flip_bits);
1641
1642 return 0;
1643}
1644
b5e50c3f
JB		 1645static int i915_fbc_status(struct seq_file *m, void *unused)
1646{
9f25d007 1647 struct drm_info_node *node = m->private;
b5e50c3f 1648 struct drm_device *dev = node->minor->dev;
e277a1f8 1649 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1650
3a77c4c4 1651 if (!HAS_FBC(dev)) {
267f0c90 1652 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1653 return 0;
1654 }
1655
36623ef8 1656 intel_runtime_pm_get(dev_priv);
25ad93fd 1657 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1658
0e631adc 1659 if (intel_fbc_is_active(dev_priv))
267f0c90 1660 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1661 else
1662 seq_printf(m, "FBC disabled: %s\n",
bf6189c6 1663 dev_priv->fbc.no_fbc_reason);
36623ef8 1664
31b9df10
PZ		 1665 if (INTEL_INFO(dev_priv)->gen >= 7)
1666 seq_printf(m, "Compressing: %s\n",
1667 yesno(I915_READ(FBC_STATUS2) &
1668 FBC_COMPRESSION_MASK));
1669
25ad93fd 1670 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1671 intel_runtime_pm_put(dev_priv);
1672
b5e50c3f
JB		 1673 return 0;
1674}
1675
da46f936
RV		 1676static int i915_fbc_fc_get(void *data, u64 *val)
1677{
1678 struct drm_device *dev = data;
1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680
1681 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1682 return -ENODEV;
1683
da46f936 1684 *val = dev_priv->fbc.false_color;
da46f936
RV		 1685
1686 return 0;
1687}
1688
1689static int i915_fbc_fc_set(void *data, u64 val)
1690{
1691 struct drm_device *dev = data;
1692 struct drm_i915_private *dev_priv = dev->dev_private;
1693 u32 reg;
1694
1695 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1696 return -ENODEV;
1697
25ad93fd 1698 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1699
1700 reg = I915_READ(ILK_DPFC_CONTROL);
1701 dev_priv->fbc.false_color = val;
1702
1703 I915_WRITE(ILK_DPFC_CONTROL, val ?
1704 (reg | FBC_CTL_FALSE_COLOR) :
1705 (reg & ~FBC_CTL_FALSE_COLOR));
1706
25ad93fd 1707 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1708 return 0;
1709}
1710
1711DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1712 i915_fbc_fc_get, i915_fbc_fc_set,
1713 "%llu\n");
1714
92d44621
PZ		 1715static int i915_ips_status(struct seq_file *m, void *unused)
1716{
9f25d007 1717 struct drm_info_node *node = m->private;
92d44621
PZ		 1718 struct drm_device *dev = node->minor->dev;
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720
f5adf94e 1721 if (!HAS_IPS(dev)) {
92d44621
PZ		 1722 seq_puts(m, "not supported\n");
1723 return 0;
1724 }
1725
36623ef8
PZ		 1726 intel_runtime_pm_get(dev_priv);
1727
0eaa53f0
RV		 1728 seq_printf(m, "Enabled by kernel parameter: %s\n",
1729 yesno(i915.enable_ips));
1730
1731 if (INTEL_INFO(dev)->gen >= 8) {
1732 seq_puts(m, "Currently: unknown\n");
1733 } else {
1734 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1735 seq_puts(m, "Currently: enabled\n");
1736 else
1737 seq_puts(m, "Currently: disabled\n");
1738 }
92d44621 1739
36623ef8
PZ		 1740 intel_runtime_pm_put(dev_priv);
1741
92d44621
PZ		 1742 return 0;
1743}
1744
4a9bef37
JB		 1745static int i915_sr_status(struct seq_file *m, void *unused)
1746{
9f25d007 1747 struct drm_info_node *node = m->private;
4a9bef37 1748 struct drm_device *dev = node->minor->dev;
e277a1f8 1749 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1750 bool sr_enabled = false;
1751
36623ef8
PZ		 1752 intel_runtime_pm_get(dev_priv);
1753
1398261a 1754 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1755 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1756 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1757 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1758 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1759 else if (IS_I915GM(dev))
1760 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1761 else if (IS_PINEVIEW(dev))
1762 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
666a4537 1763 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
77b64555 1764 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1765
36623ef8
PZ		 1766 intel_runtime_pm_put(dev_priv);
1767
5ba2aaaa
CW		 1768 seq_printf(m, "self-refresh: %s\n",
1769 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1770
1771 return 0;
1772}
1773
7648fa99
JB		 1774static int i915_emon_status(struct seq_file *m, void *unused)
1775{
9f25d007 1776 struct drm_info_node *node = m->private;
7648fa99 1777 struct drm_device *dev = node->minor->dev;
e277a1f8 1778 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1779 unsigned long temp, chipset, gfx;
de227ef0
CW		 1780 int ret;
1781
582be6b4
CW		 1782 if (!IS_GEN5(dev))
1783 return -ENODEV;
1784
de227ef0
CW		 1785 ret = mutex_lock_interruptible(&dev->struct_mutex);
1786 if (ret)
1787 return ret;
7648fa99
JB		 1788
1789 temp = i915_mch_val(dev_priv);
1790 chipset = i915_chipset_val(dev_priv);
1791 gfx = i915_gfx_val(dev_priv);
de227ef0 1792 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1793
1794 seq_printf(m, "GMCH temp: %ld\n", temp);
1795 seq_printf(m, "Chipset power: %ld\n", chipset);
1796 seq_printf(m, "GFX power: %ld\n", gfx);
1797 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1798
1799 return 0;
1800}
1801
23b2f8bb
JB		 1802static int i915_ring_freq_table(struct seq_file *m, void *unused)
1803{
9f25d007 1804 struct drm_info_node *node = m->private;
23b2f8bb 1805 struct drm_device *dev = node->minor->dev;
e277a1f8 1806 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1807 int ret = 0;
23b2f8bb 1808 int gpu_freq, ia_freq;
f936ec34 1809 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1810
97d3308a 1811 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1812 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1813 return 0;
1814 }
1815
5bfa0199
PZ		 1816 intel_runtime_pm_get(dev_priv);
1817
5c9669ce
TR		 1818 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1819
4fc688ce 1820 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1821 if (ret)
5bfa0199 1822 goto out;
23b2f8bb 1823
ef11bdb3 1824 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
f936ec34
AG		 1825 /* Convert GT frequency to 50 HZ units */
1826 min_gpu_freq =
1827 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1828 max_gpu_freq =
1829 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1830 } else {
1831 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1832 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1833 }
1834
267f0c90 1835 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1836
f936ec34 1837 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1838 ia_freq = gpu_freq;
1839 sandybridge_pcode_read(dev_priv,
1840 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1841 &ia_freq);
3ebecd07 1842 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34 1843 intel_gpu_freq(dev_priv, (gpu_freq *
ef11bdb3
RV		 1844 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1845 GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1846 ((ia_freq >> 0) & 0xff) * 100,
1847 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1848 }
1849
4fc688ce 1850 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1851
5bfa0199
PZ		 1852out:
1853 intel_runtime_pm_put(dev_priv);
1854 return ret;
23b2f8bb
JB		 1855}
1856
44834a67
CW		 1857static int i915_opregion(struct seq_file *m, void *unused)
1858{
9f25d007 1859 struct drm_info_node *node = m->private;
44834a67 1860 struct drm_device *dev = node->minor->dev;
e277a1f8 1861 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67
CW		 1862 struct intel_opregion *opregion = &dev_priv->opregion;
1863 int ret;
1864
1865 ret = mutex_lock_interruptible(&dev->struct_mutex);
1866 if (ret)
0d38f009 1867 goto out;
44834a67 1868
2455a8e4
JN		 1869 if (opregion->header)
1870 seq_write(m, opregion->header, OPREGION_SIZE);
44834a67
CW		 1871
1872 mutex_unlock(&dev->struct_mutex);
1873
0d38f009 1874out:
44834a67
CW		 1875 return 0;
1876}
1877
ada8f955
JN		 1878static int i915_vbt(struct seq_file *m, void *unused)
1879{
1880 struct drm_info_node *node = m->private;
1881 struct drm_device *dev = node->minor->dev;
1882 struct drm_i915_private *dev_priv = dev->dev_private;
1883 struct intel_opregion *opregion = &dev_priv->opregion;
1884
1885 if (opregion->vbt)
1886 seq_write(m, opregion->vbt, opregion->vbt_size);
1887
1888 return 0;
1889}
1890
37811fcc
CW		 1891static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1892{
9f25d007 1893 struct drm_info_node *node = m->private;
37811fcc 1894 struct drm_device *dev = node->minor->dev;
b13b8402 1895 struct intel_framebuffer *fbdev_fb = NULL;
3a58ee10 1896 struct drm_framebuffer *drm_fb;
37811fcc 1897
0695726e 1898#ifdef CONFIG_DRM_FBDEV_EMULATION
b13b8402
NS		 1899 if (to_i915(dev)->fbdev) {
1900 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1901
1902 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1903 fbdev_fb->base.width,
1904 fbdev_fb->base.height,
1905 fbdev_fb->base.depth,
1906 fbdev_fb->base.bits_per_pixel,
1907 fbdev_fb->base.modifier[0],
1908 atomic_read(&fbdev_fb->base.refcount.refcount));
1909 describe_obj(m, fbdev_fb->obj);
1910 seq_putc(m, '\n');
1911 }
4520f53a 1912#endif
37811fcc 1913
4b096ac1 1914 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10 1915 drm_for_each_fb(drm_fb, dev) {
b13b8402
NS		 1916 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1917 if (fb == fbdev_fb)
37811fcc
CW		 1918 continue;
1919
c1ca506d 1920 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1921 fb->base.width,
1922 fb->base.height,
1923 fb->base.depth,
623f9783 1924 fb->base.bits_per_pixel,
c1ca506d 1925 fb->base.modifier[0],
623f9783 1926 atomic_read(&fb->base.refcount.refcount));
05394f39 1927 describe_obj(m, fb->obj);
267f0c90 1928 seq_putc(m, '\n');
37811fcc 1929 }
4b096ac1 1930 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1931
1932 return 0;
1933}
1934
c9fe99bd
OM		 1935static void describe_ctx_ringbuf(struct seq_file *m,
1936 struct intel_ringbuffer *ringbuf)
1937{
1938 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1939 ringbuf->space, ringbuf->head, ringbuf->tail,
1940 ringbuf->last_retired_head);
1941}
1942
e76d3630
BW		 1943static int i915_context_status(struct seq_file *m, void *unused)
1944{
9f25d007 1945 struct drm_info_node *node = m->private;
e76d3630 1946 struct drm_device *dev = node->minor->dev;
e277a1f8 1947 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1948 struct intel_engine_cs *engine;
273497e5 1949 struct intel_context *ctx;
a168c293 1950 int ret, i;
e76d3630 1951
f3d28878 1952 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1953 if (ret)
1954 return ret;
1955
a33afea5 1956 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1957 if (!i915.enable_execlists &&
1958 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1959 continue;
1960
a33afea5 1961 seq_puts(m, "HW context ");
3ccfd19d 1962 describe_ctx(m, ctx);
e28e404c
DG		 1963 if (ctx == dev_priv->kernel_context)
1964 seq_printf(m, "(kernel context) ");
c9fe99bd
OM		 1965
1966 if (i915.enable_execlists) {
1967 seq_putc(m, '\n');
e2f80391 1968 for_each_ring(engine, dev_priv, i) {
c9fe99bd
OM		 1969 struct drm_i915_gem_object *ctx_obj =
1970 ctx->engine[i].state;
1971 struct intel_ringbuffer *ringbuf =
1972 ctx->engine[i].ringbuf;
1973
e2f80391 1974 seq_printf(m, "%s: ", engine->name);
c9fe99bd
OM		 1975 if (ctx_obj)
1976 describe_obj(m, ctx_obj);
1977 if (ringbuf)
1978 describe_ctx_ringbuf(m, ringbuf);
1979 seq_putc(m, '\n');
1980 }
1981 } else {
1982 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1983 }
a33afea5 1984
a33afea5 1985 seq_putc(m, '\n');
a168c293
BW		 1986 }
1987
f3d28878 1988 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1989
1990 return 0;
1991}
1992
064ca1d2 1993static void i915_dump_lrc_obj(struct seq_file *m,
ca82580c 1994 struct intel_context *ctx,
0bc40be8 1995 struct intel_engine_cs *engine)
064ca1d2
TD		 1996{
1997 struct page *page;
1998 uint32_t *reg_state;
1999 int j;
0bc40be8 2000 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
064ca1d2
TD		 2001 unsigned long ggtt_offset = 0;
2002
2003 if (ctx_obj == NULL) {
2004 seq_printf(m, "Context on %s with no gem object\n",
0bc40be8 2005 engine->name);
064ca1d2
TD		 2006 return;
2007 }
2008
0bc40be8
TU		 2009 seq_printf(m, "CONTEXT: %s %u\n", engine->name,
2010 intel_execlists_ctx_id(ctx, engine));
064ca1d2
TD		 2011
2012 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2013 seq_puts(m, "\tNot bound in GGTT\n");
2014 else
2015 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2016
2017 if (i915_gem_object_get_pages(ctx_obj)) {
2018 seq_puts(m, "\tFailed to get pages for context object\n");
2019 return;
2020 }
2021
d1675198 2022 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
064ca1d2
TD		 2023 if (!WARN_ON(page == NULL)) {
2024 reg_state = kmap_atomic(page);
2025
2026 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2027 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2028 ggtt_offset + 4096 + (j * 4),
2029 reg_state[j], reg_state[j + 1],
2030 reg_state[j + 2], reg_state[j + 3]);
2031 }
2032 kunmap_atomic(reg_state);
2033 }
2034
2035 seq_putc(m, '\n');
2036}
2037
c0ab1ae9
BW		 2038static int i915_dump_lrc(struct seq_file *m, void *unused)
2039{
2040 struct drm_info_node *node = (struct drm_info_node *) m->private;
2041 struct drm_device *dev = node->minor->dev;
2042 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2043 struct intel_engine_cs *engine;
c0ab1ae9
BW		 2044 struct intel_context *ctx;
2045 int ret, i;
2046
2047 if (!i915.enable_execlists) {
2048 seq_printf(m, "Logical Ring Contexts are disabled\n");
2049 return 0;
2050 }
2051
2052 ret = mutex_lock_interruptible(&dev->struct_mutex);
2053 if (ret)
2054 return ret;
2055
e28e404c
DG		 2056 list_for_each_entry(ctx, &dev_priv->context_list, link)
2057 if (ctx != dev_priv->kernel_context)
e2f80391
TU		 2058 for_each_ring(engine, dev_priv, i)
2059 i915_dump_lrc_obj(m, ctx, engine);
c0ab1ae9
BW		 2060
2061 mutex_unlock(&dev->struct_mutex);
2062
2063 return 0;
2064}
2065
4ba70e44
OM		 2066static int i915_execlists(struct seq_file *m, void *data)
2067{
2068 struct drm_info_node *node = (struct drm_info_node *)m->private;
2069 struct drm_device *dev = node->minor->dev;
2070 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2071 struct intel_engine_cs *engine;
4ba70e44
OM		 2072 u32 status_pointer;
2073 u8 read_pointer;
2074 u8 write_pointer;
2075 u32 status;
2076 u32 ctx_id;
2077 struct list_head *cursor;
2078 int ring_id, i;
2079 int ret;
2080
2081 if (!i915.enable_execlists) {
2082 seq_puts(m, "Logical Ring Contexts are disabled\n");
2083 return 0;
2084 }
2085
2086 ret = mutex_lock_interruptible(&dev->struct_mutex);
2087 if (ret)
2088 return ret;
2089
fc0412ec
MT		 2090 intel_runtime_pm_get(dev_priv);
2091
e2f80391 2092 for_each_ring(engine, dev_priv, ring_id) {
6d3d8274 2093 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2094 int count = 0;
2095 unsigned long flags;
2096
e2f80391 2097 seq_printf(m, "%s\n", engine->name);
4ba70e44 2098
e2f80391
TU		 2099 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2100 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
4ba70e44
OM		 2101 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2102 status, ctx_id);
2103
e2f80391 2104 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
4ba70e44
OM		 2105 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2106
e2f80391 2107 read_pointer = engine->next_context_status_buffer;
5590a5f0 2108 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
4ba70e44 2109 if (read_pointer > write_pointer)
5590a5f0 2110 write_pointer += GEN8_CSB_ENTRIES;
4ba70e44
OM		 2111 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2112 read_pointer, write_pointer);
2113
5590a5f0 2114 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
e2f80391
TU		 2115 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2116 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
4ba70e44
OM		 2117
2118 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2119 i, status, ctx_id);
2120 }
2121
e2f80391
TU		 2122 spin_lock_irqsave(&engine->execlist_lock, flags);
2123 list_for_each(cursor, &engine->execlist_queue)
4ba70e44 2124 count++;
e2f80391
TU		 2125 head_req = list_first_entry_or_null(&engine->execlist_queue,
2126 struct drm_i915_gem_request,
2127 execlist_link);
2128 spin_unlock_irqrestore(&engine->execlist_lock, flags);
4ba70e44
OM		 2129
2130 seq_printf(m, "\t%d requests in queue\n", count);
2131 if (head_req) {
4ba70e44 2132 seq_printf(m, "\tHead request id: %u\n",
e2f80391 2133 intel_execlists_ctx_id(head_req->ctx, engine));
4ba70e44 2134 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2135 head_req->tail);
4ba70e44
OM		 2136 }
2137
2138 seq_putc(m, '\n');
2139 }
2140
fc0412ec 2141 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2142 mutex_unlock(&dev->struct_mutex);
2143
2144 return 0;
2145}
2146
ea16a3cd
DV		 2147static const char *swizzle_string(unsigned swizzle)
2148{
aee56cff 2149 switch (swizzle) {
ea16a3cd
DV		 2150 case I915_BIT_6_SWIZZLE_NONE:
2151 return "none";
2152 case I915_BIT_6_SWIZZLE_9:
2153 return "bit9";
2154 case I915_BIT_6_SWIZZLE_9_10:
2155 return "bit9/bit10";
2156 case I915_BIT_6_SWIZZLE_9_11:
2157 return "bit9/bit11";
2158 case I915_BIT_6_SWIZZLE_9_10_11:
2159 return "bit9/bit10/bit11";
2160 case I915_BIT_6_SWIZZLE_9_17:
2161 return "bit9/bit17";
2162 case I915_BIT_6_SWIZZLE_9_10_17:
2163 return "bit9/bit10/bit17";
2164 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2165 return "unknown";
ea16a3cd
DV		 2166 }
2167
2168 return "bug";
2169}
2170
2171static int i915_swizzle_info(struct seq_file *m, void *data)
2172{
9f25d007 2173 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2174 struct drm_device *dev = node->minor->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2176 int ret;
2177
2178 ret = mutex_lock_interruptible(&dev->struct_mutex);
2179 if (ret)
2180 return ret;
c8c8fb33 2181 intel_runtime_pm_get(dev_priv);
ea16a3cd 2182
ea16a3cd
DV		 2183 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2184 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2185 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2186 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2187
2188 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2189 seq_printf(m, "DDC = 0x%08x\n",
2190 I915_READ(DCC));
656bfa3a
DV		 2191 seq_printf(m, "DDC2 = 0x%08x\n",
2192 I915_READ(DCC2));
ea16a3cd
DV		 2193 seq_printf(m, "C0DRB3 = 0x%04x\n",
2194 I915_READ16(C0DRB3));
2195 seq_printf(m, "C1DRB3 = 0x%04x\n",
2196 I915_READ16(C1DRB3));
9d3203e1 2197 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2198 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2199 I915_READ(MAD_DIMM_C0));
2200 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2201 I915_READ(MAD_DIMM_C1));
2202 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2203 I915_READ(MAD_DIMM_C2));
2204 seq_printf(m, "TILECTL = 0x%08x\n",
2205 I915_READ(TILECTL));
5907f5fb 2206 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2207 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2208 I915_READ(GAMTARBMODE));
2209 else
2210 seq_printf(m, "ARB_MODE = 0x%08x\n",
2211 I915_READ(ARB_MODE));
3fa7d235
DV		 2212 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2213 I915_READ(DISP_ARB_CTL));
ea16a3cd 2214 }
656bfa3a
DV		 2215
2216 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2217 seq_puts(m, "L-shaped memory detected\n");
2218
c8c8fb33 2219 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2220 mutex_unlock(&dev->struct_mutex);
2221
2222 return 0;
2223}
2224
1c60fef5
BW		 2225static int per_file_ctx(int id, void *ptr, void *data)
2226{
273497e5 2227 struct intel_context *ctx = ptr;
1c60fef5 2228 struct seq_file *m = data;
ae6c4806
DV		 2229 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2230
2231 if (!ppgtt) {
2232 seq_printf(m, " no ppgtt for context %d\n",
2233 ctx->user_handle);
2234 return 0;
2235 }
1c60fef5 2236
f83d6518
OM		 2237 if (i915_gem_context_is_default(ctx))
2238 seq_puts(m, " default context:\n");
2239 else
821d66dd 2240 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2241 ppgtt->debug_dump(ppgtt, m);
2242
2243 return 0;
2244}
2245
77df6772 2246static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2247{
3cf17fc5 2248 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2249 struct intel_engine_cs *engine;
77df6772
BW		 2250 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2251 int unused, i;
3cf17fc5 2252
77df6772
BW		 2253 if (!ppgtt)
2254 return;
2255
e2f80391
TU		 2256 for_each_ring(engine, dev_priv, unused) {
2257 seq_printf(m, "%s\n", engine->name);
77df6772 2258 for (i = 0; i < 4; i++) {
e2f80391 2259 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
77df6772 2260 pdp <<= 32;
e2f80391 2261 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
a2a5b15c 2262 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2263 }
2264 }
2265}
2266
2267static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2268{
2269 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2270 struct intel_engine_cs *engine;
77df6772 2271 int i;
3cf17fc5 2272
3cf17fc5
DV		 2273 if (INTEL_INFO(dev)->gen == 6)
2274 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2275
e2f80391
TU		 2276 for_each_ring(engine, dev_priv, i) {
2277 seq_printf(m, "%s\n", engine->name);
3cf17fc5 2278 if (INTEL_INFO(dev)->gen == 7)
e2f80391
TU		 2279 seq_printf(m, "GFX_MODE: 0x%08x\n",
2280 I915_READ(RING_MODE_GEN7(engine)));
2281 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2282 I915_READ(RING_PP_DIR_BASE(engine)));
2283 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2284 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2285 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2286 I915_READ(RING_PP_DIR_DCLV(engine)));
3cf17fc5
DV		 2287 }
2288 if (dev_priv->mm.aliasing_ppgtt) {
2289 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2290
267f0c90 2291 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2292 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2293
87d60b63 2294 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2295 }
1c60fef5 2296
3cf17fc5 2297 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2298}
2299
2300static int i915_ppgtt_info(struct seq_file *m, void *data)
2301{
9f25d007 2302 struct drm_info_node *node = m->private;
77df6772 2303 struct drm_device *dev = node->minor->dev;
c8c8fb33 2304 struct drm_i915_private *dev_priv = dev->dev_private;
ea91e401 2305 struct drm_file *file;
77df6772
BW		 2306
2307 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2308 if (ret)
2309 return ret;
c8c8fb33 2310 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2311
2312 if (INTEL_INFO(dev)->gen >= 8)
2313 gen8_ppgtt_info(m, dev);
2314 else if (INTEL_INFO(dev)->gen >= 6)
2315 gen6_ppgtt_info(m, dev);
2316
ea91e401
MT		 2317 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2318 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2319 struct task_struct *task;
ea91e401 2320
7cb5dff8 2321 task = get_pid_task(file->pid, PIDTYPE_PID);
06812760
DC		 2322 if (!task) {
2323 ret = -ESRCH;
2324 goto out_put;
2325 }
7cb5dff8
GT		 2326 seq_printf(m, "\nproc: %s\n", task->comm);
2327 put_task_struct(task);
ea91e401
MT		 2328 idr_for_each(&file_priv->context_idr, per_file_ctx,
2329 (void *)(unsigned long)m);
2330 }
2331
06812760 2332out_put:
c8c8fb33 2333 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2334 mutex_unlock(&dev->struct_mutex);
2335
06812760 2336 return ret;
3cf17fc5
DV		 2337}
2338
f5a4c67d
CW		 2339static int count_irq_waiters(struct drm_i915_private *i915)
2340{
e2f80391 2341 struct intel_engine_cs *engine;
f5a4c67d
CW		 2342 int count = 0;
2343 int i;
2344
e2f80391
TU		 2345 for_each_ring(engine, i915, i)
2346 count += engine->irq_refcount;
f5a4c67d
CW		 2347
2348 return count;
2349}
2350
1854d5ca
CW		 2351static int i915_rps_boost_info(struct seq_file *m, void *data)
2352{
2353 struct drm_info_node *node = m->private;
2354 struct drm_device *dev = node->minor->dev;
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 struct drm_file *file;
1854d5ca 2357
f5a4c67d
CW		 2358 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2359 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2360 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2361 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2362 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2363 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2364 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2365 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2366 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2367 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2368 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2369 struct drm_i915_file_private *file_priv = file->driver_priv;
2370 struct task_struct *task;
2371
2372 rcu_read_lock();
2373 task = pid_task(file->pid, PIDTYPE_PID);
2374 seq_printf(m, "%s [%d]: %d boosts%s\n",
2375 task ? task->comm : "<unknown>",
2376 task ? task->pid : -1,
2e1b8730
CW		 2377 file_priv->rps.boosts,
2378 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2379 rcu_read_unlock();
2380 }
2e1b8730
CW		 2381 seq_printf(m, "Semaphore boosts: %d%s\n",
2382 dev_priv->rps.semaphores.boosts,
2383 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2384 seq_printf(m, "MMIO flip boosts: %d%s\n",
2385 dev_priv->rps.mmioflips.boosts,
2386 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2387 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2388 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2389
8d3afd7d 2390 return 0;
1854d5ca
CW		 2391}
2392
63573eb7
BW		 2393static int i915_llc(struct seq_file *m, void *data)
2394{
9f25d007 2395 struct drm_info_node *node = m->private;
63573eb7
BW		 2396 struct drm_device *dev = node->minor->dev;
2397 struct drm_i915_private *dev_priv = dev->dev_private;
2398
2399 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2400 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2401 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2402
2403 return 0;
2404}
2405
fdf5d357
AD		 2406static int i915_guc_load_status_info(struct seq_file *m, void *data)
2407{
2408 struct drm_info_node *node = m->private;
2409 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2410 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2411 u32 tmp, i;
2412
2413 if (!HAS_GUC_UCODE(dev_priv->dev))
2414 return 0;
2415
2416 seq_printf(m, "GuC firmware status:\n");
2417 seq_printf(m, "\tpath: %s\n",
2418 guc_fw->guc_fw_path);
2419 seq_printf(m, "\tfetch: %s\n",
2420 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2421 seq_printf(m, "\tload: %s\n",
2422 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2423 seq_printf(m, "\tversion wanted: %d.%d\n",
2424 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2425 seq_printf(m, "\tversion found: %d.%d\n",
2426 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
feda33ef
AD		 2427 seq_printf(m, "\theader: offset is %d; size = %d\n",
2428 guc_fw->header_offset, guc_fw->header_size);
2429 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2430 guc_fw->ucode_offset, guc_fw->ucode_size);
2431 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2432 guc_fw->rsa_offset, guc_fw->rsa_size);
fdf5d357
AD		 2433
2434 tmp = I915_READ(GUC_STATUS);
2435
2436 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2437 seq_printf(m, "\tBootrom status = 0x%x\n",
2438 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2439 seq_printf(m, "\tuKernel status = 0x%x\n",
2440 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2441 seq_printf(m, "\tMIA Core status = 0x%x\n",
2442 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2443 seq_puts(m, "\nScratch registers:\n");
2444 for (i = 0; i < 16; i++)
2445 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2446
2447 return 0;
2448}
2449
8b417c26
DG		 2450static void i915_guc_client_info(struct seq_file *m,
2451 struct drm_i915_private *dev_priv,
2452 struct i915_guc_client *client)
2453{
e2f80391 2454 struct intel_engine_cs *engine;
8b417c26
DG		 2455 uint64_t tot = 0;
2456 uint32_t i;
2457
2458 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2459 client->priority, client->ctx_index, client->proc_desc_offset);
2460 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2461 client->doorbell_id, client->doorbell_offset, client->cookie);
2462 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2463 client->wq_size, client->wq_offset, client->wq_tail);
2464
2465 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2466 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2467 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2468
e2f80391 2469 for_each_ring(engine, dev_priv, i) {
8b417c26 2470 seq_printf(m, "\tSubmissions: %llu %s\n",
e2f80391
TU		 2471 client->submissions[engine->guc_id],
2472 engine->name);
2473 tot += client->submissions[engine->guc_id];
8b417c26
DG		 2474 }
2475 seq_printf(m, "\tTotal: %llu\n", tot);
2476}
2477
2478static int i915_guc_info(struct seq_file *m, void *data)
2479{
2480 struct drm_info_node *node = m->private;
2481 struct drm_device *dev = node->minor->dev;
2482 struct drm_i915_private *dev_priv = dev->dev_private;
2483 struct intel_guc guc;
0a0b457f 2484 struct i915_guc_client client = {};
e2f80391 2485 struct intel_engine_cs *engine;
8b417c26
DG		 2486 enum intel_ring_id i;
2487 u64 total = 0;
2488
2489 if (!HAS_GUC_SCHED(dev_priv->dev))
2490 return 0;
2491
5a843307
AD		 2492 if (mutex_lock_interruptible(&dev->struct_mutex))
2493 return 0;
2494
8b417c26 2495 /* Take a local copy of the GuC data, so we can dump it at leisure */
8b417c26 2496 guc = dev_priv->guc;
5a843307 2497 if (guc.execbuf_client)
8b417c26 2498 client = *guc.execbuf_client;
5a843307
AD		 2499
2500 mutex_unlock(&dev->struct_mutex);
8b417c26
DG		 2501
2502 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2503 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2504 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2505 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2506 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2507
2508 seq_printf(m, "\nGuC submissions:\n");
e2f80391 2509 for_each_ring(engine, dev_priv, i) {
397097b0 2510 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
e2f80391
TU		 2511 engine->name, guc.submissions[engine->guc_id],
2512 guc.last_seqno[engine->guc_id]);
2513 total += guc.submissions[engine->guc_id];
8b417c26
DG		 2514 }
2515 seq_printf(m, "\t%s: %llu\n", "Total", total);
2516
2517 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2518 i915_guc_client_info(m, dev_priv, &client);
2519
2520 /* Add more as required ... */
2521
2522 return 0;
2523}
2524
4c7e77fc
AD		 2525static int i915_guc_log_dump(struct seq_file *m, void *data)
2526{
2527 struct drm_info_node *node = m->private;
2528 struct drm_device *dev = node->minor->dev;
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2531 u32 *log;
2532 int i = 0, pg;
2533
2534 if (!log_obj)
2535 return 0;
2536
2537 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2538 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2539
2540 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2541 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2542 *(log + i), *(log + i + 1),
2543 *(log + i + 2), *(log + i + 3));
2544
2545 kunmap_atomic(log);
2546 }
2547
2548 seq_putc(m, '\n');
2549
2550 return 0;
2551}
2552
e91fd8c6
RV		 2553static int i915_edp_psr_status(struct seq_file *m, void *data)
2554{
2555 struct drm_info_node *node = m->private;
2556 struct drm_device *dev = node->minor->dev;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2558 u32 psrperf = 0;
a6cbdb8e
RV		 2559 u32 stat[3];
2560 enum pipe pipe;
a031d709 2561 bool enabled = false;
e91fd8c6 2562
3553a8ea
DL		 2563 if (!HAS_PSR(dev)) {
2564 seq_puts(m, "PSR not supported\n");
2565 return 0;
2566 }
2567
c8c8fb33
PZ		 2568 intel_runtime_pm_get(dev_priv);
2569
fa128fa6 2570 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2571 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2572 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2573 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2574 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2575 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2576 dev_priv->psr.busy_frontbuffer_bits);
2577 seq_printf(m, "Re-enable work scheduled: %s\n",
2578 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2579
3553a8ea 2580 if (HAS_DDI(dev))
443a389f 2581 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
3553a8ea
DL		 2582 else {
2583 for_each_pipe(dev_priv, pipe) {
2584 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2585 VLV_EDP_PSR_CURR_STATE_MASK;
2586 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2587 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2588 enabled = true;
a6cbdb8e
RV		 2589 }
2590 }
60e5ffe3
RV		 2591
2592 seq_printf(m, "Main link in standby mode: %s\n",
2593 yesno(dev_priv->psr.link_standby));
2594
a6cbdb8e
RV		 2595 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2596
2597 if (!HAS_DDI(dev))
2598 for_each_pipe(dev_priv, pipe) {
2599 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2600 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2601 seq_printf(m, " pipe %c", pipe_name(pipe));
2602 }
2603 seq_puts(m, "\n");
e91fd8c6 2604
05eec3c2
RV		 2605 /*
2606 * VLV/CHV PSR has no kind of performance counter
2607 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2608 */
2609 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
443a389f 2610 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
a031d709 2611 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2612
2613 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2614 }
fa128fa6 2615 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2616
c8c8fb33 2617 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2618 return 0;
2619}
2620
d2e216d0
RV		 2621static int i915_sink_crc(struct seq_file *m, void *data)
2622{
2623 struct drm_info_node *node = m->private;
2624 struct drm_device *dev = node->minor->dev;
2625 struct intel_encoder *encoder;
2626 struct intel_connector *connector;
2627 struct intel_dp *intel_dp = NULL;
2628 int ret;
2629 u8 crc[6];
2630
2631 drm_modeset_lock_all(dev);
aca5e361 2632 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2633
2634 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2635 continue;
2636
b6ae3c7c
PZ		 2637 if (!connector->base.encoder)
2638 continue;
2639
d2e216d0
RV		 2640 encoder = to_intel_encoder(connector->base.encoder);
2641 if (encoder->type != INTEL_OUTPUT_EDP)
2642 continue;
2643
2644 intel_dp = enc_to_intel_dp(&encoder->base);
2645
2646 ret = intel_dp_sink_crc(intel_dp, crc);
2647 if (ret)
2648 goto out;
2649
2650 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2651 crc[0], crc[1], crc[2],
2652 crc[3], crc[4], crc[5]);
2653 goto out;
2654 }
2655 ret = -ENODEV;
2656out:
2657 drm_modeset_unlock_all(dev);
2658 return ret;
2659}
2660
ec013e7f
JB		 2661static int i915_energy_uJ(struct seq_file *m, void *data)
2662{
2663 struct drm_info_node *node = m->private;
2664 struct drm_device *dev = node->minor->dev;
2665 struct drm_i915_private *dev_priv = dev->dev_private;
2666 u64 power;
2667 u32 units;
2668
2669 if (INTEL_INFO(dev)->gen < 6)
2670 return -ENODEV;
2671
36623ef8
PZ		 2672 intel_runtime_pm_get(dev_priv);
2673
ec013e7f
JB		 2674 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2675 power = (power & 0x1f00) >> 8;
2676 units = 1000000 / (1 << power); /* convert to uJ */
2677 power = I915_READ(MCH_SECP_NRG_STTS);
2678 power *= units;
2679
36623ef8
PZ		 2680 intel_runtime_pm_put(dev_priv);
2681
ec013e7f 2682 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2683
2684 return 0;
2685}
2686
6455c870 2687static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2688{
9f25d007 2689 struct drm_info_node *node = m->private;
371db66a
PZ		 2690 struct drm_device *dev = node->minor->dev;
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692
6455c870 2693 if (!HAS_RUNTIME_PM(dev)) {
371db66a
PZ		 2694 seq_puts(m, "not supported\n");
2695 return 0;
2696 }
2697
86c4ec0d 2698 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2699 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2700 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2701#ifdef CONFIG_PM
a6aaec8b
DL		 2702 seq_printf(m, "Usage count: %d\n",
2703 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2704#else
2705 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2706#endif
371db66a 2707
ec013e7f
JB		 2708 return 0;
2709}
2710
1da51581
ID		 2711static int i915_power_domain_info(struct seq_file *m, void *unused)
2712{
9f25d007 2713 struct drm_info_node *node = m->private;
1da51581
ID		 2714 struct drm_device *dev = node->minor->dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2717 int i;
2718
2719 mutex_lock(&power_domains->lock);
2720
2721 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2722 for (i = 0; i < power_domains->power_well_count; i++) {
2723 struct i915_power_well *power_well;
2724 enum intel_display_power_domain power_domain;
2725
2726 power_well = &power_domains->power_wells[i];
2727 seq_printf(m, "%-25s %d\n", power_well->name,
2728 power_well->count);
2729
2730 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2731 power_domain++) {
2732 if (!(BIT(power_domain) & power_well->domains))
2733 continue;
2734
2735 seq_printf(m, " %-23s %d\n",
9895ad03 2736 intel_display_power_domain_str(power_domain),
1da51581
ID		 2737 power_domains->domain_use_count[power_domain]);
2738 }
2739 }
2740
2741 mutex_unlock(&power_domains->lock);
2742
2743 return 0;
2744}
2745
b7cec66d
DL		 2746static int i915_dmc_info(struct seq_file *m, void *unused)
2747{
2748 struct drm_info_node *node = m->private;
2749 struct drm_device *dev = node->minor->dev;
2750 struct drm_i915_private *dev_priv = dev->dev_private;
2751 struct intel_csr *csr;
2752
2753 if (!HAS_CSR(dev)) {
2754 seq_puts(m, "not supported\n");
2755 return 0;
2756 }
2757
2758 csr = &dev_priv->csr;
2759
6fb403de
MK		 2760 intel_runtime_pm_get(dev_priv);
2761
b7cec66d
DL		 2762 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2763 seq_printf(m, "path: %s\n", csr->fw_path);
2764
2765 if (!csr->dmc_payload)
6fb403de 2766 goto out;
b7cec66d
DL		 2767
2768 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2769 CSR_VERSION_MINOR(csr->version));
2770
8337206d
DL		 2771 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2772 seq_printf(m, "DC3 -> DC5 count: %d\n",
2773 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2774 seq_printf(m, "DC5 -> DC6 count: %d\n",
2775 I915_READ(SKL_CSR_DC5_DC6_COUNT));
16e11b99
MK		 2776 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2777 seq_printf(m, "DC3 -> DC5 count: %d\n",
2778 I915_READ(BXT_CSR_DC3_DC5_COUNT));
8337206d
DL		 2779 }
2780
6fb403de
MK		 2781out:
2782 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2783 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2784 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2785
8337206d
DL		 2786 intel_runtime_pm_put(dev_priv);
2787
b7cec66d
DL		 2788 return 0;
2789}
2790
53f5e3ca
JB		 2791static void intel_seq_print_mode(struct seq_file *m, int tabs,
2792 struct drm_display_mode *mode)
2793{
2794 int i;
2795
2796 for (i = 0; i < tabs; i++)
2797 seq_putc(m, '\t');
2798
2799 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2800 mode->base.id, mode->name,
2801 mode->vrefresh, mode->clock,
2802 mode->hdisplay, mode->hsync_start,
2803 mode->hsync_end, mode->htotal,
2804 mode->vdisplay, mode->vsync_start,
2805 mode->vsync_end, mode->vtotal,
2806 mode->type, mode->flags);
2807}
2808
2809static void intel_encoder_info(struct seq_file *m,
2810 struct intel_crtc *intel_crtc,
2811 struct intel_encoder *intel_encoder)
2812{
9f25d007 2813 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2814 struct drm_device *dev = node->minor->dev;
2815 struct drm_crtc *crtc = &intel_crtc->base;
2816 struct intel_connector *intel_connector;
2817 struct drm_encoder *encoder;
2818
2819 encoder = &intel_encoder->base;
2820 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2821 encoder->base.id, encoder->name);
53f5e3ca
JB		 2822 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2823 struct drm_connector *connector = &intel_connector->base;
2824 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2825 connector->base.id,
c23cc417 2826 connector->name,
53f5e3ca
JB		 2827 drm_get_connector_status_name(connector->status));
2828 if (connector->status == connector_status_connected) {
2829 struct drm_display_mode *mode = &crtc->mode;
2830 seq_printf(m, ", mode:\n");
2831 intel_seq_print_mode(m, 2, mode);
2832 } else {
2833 seq_putc(m, '\n');
2834 }
2835 }
2836}
2837
2838static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2839{
9f25d007 2840 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2841 struct drm_device *dev = node->minor->dev;
2842 struct drm_crtc *crtc = &intel_crtc->base;
2843 struct intel_encoder *intel_encoder;
23a48d53
ML		 2844 struct drm_plane_state *plane_state = crtc->primary->state;
2845 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2846
23a48d53 2847 if (fb)
5aa8a937 2848 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2849 fb->base.id, plane_state->src_x >> 16,
2850 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2851 else
2852 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2853 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2854 intel_encoder_info(m, intel_crtc, intel_encoder);
2855}
2856
2857static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2858{
2859 struct drm_display_mode *mode = panel->fixed_mode;
2860
2861 seq_printf(m, "\tfixed mode:\n");
2862 intel_seq_print_mode(m, 2, mode);
2863}
2864
2865static void intel_dp_info(struct seq_file *m,
2866 struct intel_connector *intel_connector)
2867{
2868 struct intel_encoder *intel_encoder = intel_connector->encoder;
2869 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2870
2871 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2872 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
53f5e3ca
JB		 2873 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2874 intel_panel_info(m, &intel_connector->panel);
2875}
2876
3d52ccf5
LY		 2877static void intel_dp_mst_info(struct seq_file *m,
2878 struct intel_connector *intel_connector)
2879{
2880 struct intel_encoder *intel_encoder = intel_connector->encoder;
2881 struct intel_dp_mst_encoder *intel_mst =
2882 enc_to_mst(&intel_encoder->base);
2883 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2884 struct intel_dp *intel_dp = &intel_dig_port->dp;
2885 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2886 intel_connector->port);
2887
2888 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2889}
2890
53f5e3ca
JB		 2891static void intel_hdmi_info(struct seq_file *m,
2892 struct intel_connector *intel_connector)
2893{
2894 struct intel_encoder *intel_encoder = intel_connector->encoder;
2895 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2896
742f491d 2897 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2898}
2899
2900static void intel_lvds_info(struct seq_file *m,
2901 struct intel_connector *intel_connector)
2902{
2903 intel_panel_info(m, &intel_connector->panel);
2904}
2905
2906static void intel_connector_info(struct seq_file *m,
2907 struct drm_connector *connector)
2908{
2909 struct intel_connector *intel_connector = to_intel_connector(connector);
2910 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2911 struct drm_display_mode *mode;
53f5e3ca
JB		 2912
2913 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2914 connector->base.id, connector->name,
53f5e3ca
JB		 2915 drm_get_connector_status_name(connector->status));
2916 if (connector->status == connector_status_connected) {
2917 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2918 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2919 connector->display_info.width_mm,
2920 connector->display_info.height_mm);
2921 seq_printf(m, "\tsubpixel order: %s\n",
2922 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2923 seq_printf(m, "\tCEA rev: %d\n",
2924 connector->display_info.cea_rev);
2925 }
36cd7444
DA		 2926 if (intel_encoder) {
2927 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2928 intel_encoder->type == INTEL_OUTPUT_EDP)
2929 intel_dp_info(m, intel_connector);
2930 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2931 intel_hdmi_info(m, intel_connector);
2932 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2933 intel_lvds_info(m, intel_connector);
3d52ccf5
LY		 2934 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2935 intel_dp_mst_info(m, intel_connector);
36cd7444 2936 }
53f5e3ca 2937
f103fc7d
JB		 2938 seq_printf(m, "\tmodes:\n");
2939 list_for_each_entry(mode, &connector->modes, head)
2940 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2941}
2942
065f2ec2
CW		 2943static bool cursor_active(struct drm_device *dev, int pipe)
2944{
2945 struct drm_i915_private *dev_priv = dev->dev_private;
2946 u32 state;
2947
2948 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 2949 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
065f2ec2 2950 else
5efb3e28 2951 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2952
2953 return state;
2954}
2955
2956static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2957{
2958 struct drm_i915_private *dev_priv = dev->dev_private;
2959 u32 pos;
2960
5efb3e28 2961 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2962
2963 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2964 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2965 *x = -*x;
2966
2967 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2968 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2969 *y = -*y;
2970
2971 return cursor_active(dev, pipe);
2972}
2973
3abc4e09
RF		 2974static const char *plane_type(enum drm_plane_type type)
2975{
2976 switch (type) {
2977 case DRM_PLANE_TYPE_OVERLAY:
2978 return "OVL";
2979 case DRM_PLANE_TYPE_PRIMARY:
2980 return "PRI";
2981 case DRM_PLANE_TYPE_CURSOR:
2982 return "CUR";
2983 /*
2984 * Deliberately omitting default: to generate compiler warnings
2985 * when a new drm_plane_type gets added.
2986 */
2987 }
2988
2989 return "unknown";
2990}
2991
2992static const char *plane_rotation(unsigned int rotation)
2993{
2994 static char buf[48];
2995 /*
2996 * According to doc only one DRM_ROTATE_ is allowed but this
2997 * will print them all to visualize if the values are misused
2998 */
2999 snprintf(buf, sizeof(buf),
3000 "%s%s%s%s%s%s(0x%08x)",
3001 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3002 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3003 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3004 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3005 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3006 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3007 rotation);
3008
3009 return buf;
3010}
3011
3012static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3013{
3014 struct drm_info_node *node = m->private;
3015 struct drm_device *dev = node->minor->dev;
3016 struct intel_plane *intel_plane;
3017
3018 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3019 struct drm_plane_state *state;
3020 struct drm_plane *plane = &intel_plane->base;
3021
3022 if (!plane->state) {
3023 seq_puts(m, "plane->state is NULL!\n");
3024 continue;
3025 }
3026
3027 state = plane->state;
3028
3029 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3030 plane->base.id,
3031 plane_type(intel_plane->base.type),
3032 state->crtc_x, state->crtc_y,
3033 state->crtc_w, state->crtc_h,
3034 (state->src_x >> 16),
3035 ((state->src_x & 0xffff) * 15625) >> 10,
3036 (state->src_y >> 16),
3037 ((state->src_y & 0xffff) * 15625) >> 10,
3038 (state->src_w >> 16),
3039 ((state->src_w & 0xffff) * 15625) >> 10,
3040 (state->src_h >> 16),
3041 ((state->src_h & 0xffff) * 15625) >> 10,
3042 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3043 plane_rotation(state->rotation));
3044 }
3045}
3046
3047static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3048{
3049 struct intel_crtc_state *pipe_config;
3050 int num_scalers = intel_crtc->num_scalers;
3051 int i;
3052
3053 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3054
3055 /* Not all platformas have a scaler */
3056 if (num_scalers) {
3057 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3058 num_scalers,
3059 pipe_config->scaler_state.scaler_users,
3060 pipe_config->scaler_state.scaler_id);
3061
3062 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3063 struct intel_scaler *sc =
3064 &pipe_config->scaler_state.scalers[i];
3065
3066 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3067 i, yesno(sc->in_use), sc->mode);
3068 }
3069 seq_puts(m, "\n");
3070 } else {
3071 seq_puts(m, "\tNo scalers available on this platform\n");
3072 }
3073}
3074
53f5e3ca
JB		 3075static int i915_display_info(struct seq_file *m, void *unused)
3076{
9f25d007 3077 struct drm_info_node *node = m->private;
53f5e3ca 3078 struct drm_device *dev = node->minor->dev;
b0e5ddf3 3079 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 3080 struct intel_crtc *crtc;
53f5e3ca
JB		 3081 struct drm_connector *connector;
3082
b0e5ddf3 3083 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 3084 drm_modeset_lock_all(dev);
3085 seq_printf(m, "CRTC info\n");
3086 seq_printf(m, "---------\n");
d3fcc808 3087 for_each_intel_crtc(dev, crtc) {
065f2ec2 3088 bool active;
f77076c9 3089 struct intel_crtc_state *pipe_config;
065f2ec2 3090 int x, y;
53f5e3ca 3091
f77076c9
ML		 3092 pipe_config = to_intel_crtc_state(crtc->base.state);
3093
3abc4e09 3094 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
065f2ec2 3095 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9 3096 yesno(pipe_config->base.active),
3abc4e09
RF		 3097 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3098 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3099
f77076c9 3100 if (pipe_config->base.active) {
065f2ec2
CW		 3101 intel_crtc_info(m, crtc);
3102
a23dc658 3103 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 3104 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 3105 yesno(crtc->cursor_base),
3dd512fb
MR		 3106 x, y, crtc->base.cursor->state->crtc_w,
3107 crtc->base.cursor->state->crtc_h,
57127efa 3108 crtc->cursor_addr, yesno(active));
3abc4e09
RF		 3109 intel_scaler_info(m, crtc);
3110 intel_plane_info(m, crtc);
a23dc658 3111 }
cace841c
DV		 3112
3113 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3114 yesno(!crtc->cpu_fifo_underrun_disabled),
3115 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 3116 }
3117
3118 seq_printf(m, "\n");
3119 seq_printf(m, "Connector info\n");
3120 seq_printf(m, "--------------\n");
3121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3122 intel_connector_info(m, connector);
3123 }
3124 drm_modeset_unlock_all(dev);
b0e5ddf3 3125 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 3126
3127 return 0;
3128}
3129
e04934cf
BW		 3130static int i915_semaphore_status(struct seq_file *m, void *unused)
3131{
3132 struct drm_info_node *node = (struct drm_info_node *) m->private;
3133 struct drm_device *dev = node->minor->dev;
3134 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 3135 struct intel_engine_cs *engine;
e04934cf
BW		 3136 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3137 int i, j, ret;
3138
3139 if (!i915_semaphore_is_enabled(dev)) {
3140 seq_puts(m, "Semaphores are disabled\n");
3141 return 0;
3142 }
3143
3144 ret = mutex_lock_interruptible(&dev->struct_mutex);
3145 if (ret)
3146 return ret;
03872064 3147 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 3148
3149 if (IS_BROADWELL(dev)) {
3150 struct page *page;
3151 uint64_t *seqno;
3152
3153 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3154
3155 seqno = (uint64_t *)kmap_atomic(page);
e2f80391 3156 for_each_ring(engine, dev_priv, i) {
e04934cf
BW		 3157 uint64_t offset;
3158
e2f80391 3159 seq_printf(m, "%s\n", engine->name);
e04934cf
BW		 3160
3161 seq_puts(m, " Last signal:");
3162 for (j = 0; j < num_rings; j++) {
3163 offset = i * I915_NUM_RINGS + j;
3164 seq_printf(m, "0x%08llx (0x%02llx) ",
3165 seqno[offset], offset * 8);
3166 }
3167 seq_putc(m, '\n');
3168
3169 seq_puts(m, " Last wait: ");
3170 for (j = 0; j < num_rings; j++) {
3171 offset = i + (j * I915_NUM_RINGS);
3172 seq_printf(m, "0x%08llx (0x%02llx) ",
3173 seqno[offset], offset * 8);
3174 }
3175 seq_putc(m, '\n');
3176
3177 }
3178 kunmap_atomic(seqno);
3179 } else {
3180 seq_puts(m, " Last signal:");
e2f80391 3181 for_each_ring(engine, dev_priv, i)
e04934cf
BW		 3182 for (j = 0; j < num_rings; j++)
3183 seq_printf(m, "0x%08x\n",
e2f80391 3184 I915_READ(engine->semaphore.mbox.signal[j]));
e04934cf
BW		 3185 seq_putc(m, '\n');
3186 }
3187
3188 seq_puts(m, "\nSync seqno:\n");
e2f80391 3189 for_each_ring(engine, dev_priv, i) {
e04934cf 3190 for (j = 0; j < num_rings; j++) {
e2f80391
TU		 3191 seq_printf(m, " 0x%08x ",
3192 engine->semaphore.sync_seqno[j]);
e04934cf
BW		 3193 }
3194 seq_putc(m, '\n');
3195 }
3196 seq_putc(m, '\n');
3197
03872064 3198 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3199 mutex_unlock(&dev->struct_mutex);
3200 return 0;
3201}
3202
728e29d7
DV		 3203static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3204{
3205 struct drm_info_node *node = (struct drm_info_node *) m->private;
3206 struct drm_device *dev = node->minor->dev;
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 int i;
3209
3210 drm_modeset_lock_all(dev);
3211 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3212 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3213
3214 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 3215 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 3216 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 3217 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3218 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3219 seq_printf(m, " dpll_md: 0x%08x\n",
3220 pll->config.hw_state.dpll_md);
3221 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3222 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3223 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3224 }
3225 drm_modeset_unlock_all(dev);
3226
3227 return 0;
3228}
3229
1ed1ef9d 3230static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3231{
3232 int i;
3233 int ret;
e2f80391 3234 struct intel_engine_cs *engine;
888b5995
AS		 3235 struct drm_info_node *node = (struct drm_info_node *) m->private;
3236 struct drm_device *dev = node->minor->dev;
3237 struct drm_i915_private *dev_priv = dev->dev_private;
33136b06 3238 struct i915_workarounds *workarounds = &dev_priv->workarounds;
888b5995 3239
888b5995
AS		 3240 ret = mutex_lock_interruptible(&dev->struct_mutex);
3241 if (ret)
3242 return ret;
3243
3244 intel_runtime_pm_get(dev_priv);
3245
33136b06 3246 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
e2f80391 3247 for_each_ring(engine, dev_priv, i)
33136b06 3248 seq_printf(m, "HW whitelist count for %s: %d\n",
e2f80391 3249 engine->name, workarounds->hw_whitelist_count[i]);
33136b06 3250 for (i = 0; i < workarounds->count; ++i) {
f0f59a00
VS		 3251 i915_reg_t addr;
3252 u32 mask, value, read;
2fa60f6d 3253 bool ok;
888b5995 3254
33136b06
AS		 3255 addr = workarounds->reg[i].addr;
3256 mask = workarounds->reg[i].mask;
3257 value = workarounds->reg[i].value;
2fa60f6d
MK		 3258 read = I915_READ(addr);
3259 ok = (value & mask) == (read & mask);
3260 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
f0f59a00 3261 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3262 }
3263
3264 intel_runtime_pm_put(dev_priv);
3265 mutex_unlock(&dev->struct_mutex);
3266
3267 return 0;
3268}
3269
c5511e44
DL		 3270static int i915_ddb_info(struct seq_file *m, void *unused)
3271{
3272 struct drm_info_node *node = m->private;
3273 struct drm_device *dev = node->minor->dev;
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275 struct skl_ddb_allocation *ddb;
3276 struct skl_ddb_entry *entry;
3277 enum pipe pipe;
3278 int plane;
3279
2fcffe19
DL		 3280 if (INTEL_INFO(dev)->gen < 9)
3281 return 0;
3282
c5511e44
DL		 3283 drm_modeset_lock_all(dev);
3284
3285 ddb = &dev_priv->wm.skl_hw.ddb;
3286
3287 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3288
3289 for_each_pipe(dev_priv, pipe) {
3290 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3291
dd740780 3292 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3293 entry = &ddb->plane[pipe][plane];
3294 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3295 entry->start, entry->end,
3296 skl_ddb_entry_size(entry));
3297 }
3298
4969d33e 3299 entry = &ddb->plane[pipe][PLANE_CURSOR];
c5511e44
DL		 3300 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3301 entry->end, skl_ddb_entry_size(entry));
3302 }
3303
3304 drm_modeset_unlock_all(dev);
3305
3306 return 0;
3307}
3308
a54746e3
VK		 3309static void drrs_status_per_crtc(struct seq_file *m,
3310 struct drm_device *dev, struct intel_crtc *intel_crtc)
3311{
3312 struct intel_encoder *intel_encoder;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314 struct i915_drrs *drrs = &dev_priv->drrs;
3315 int vrefresh = 0;
3316
3317 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3318 /* Encoder connected on this CRTC */
3319 switch (intel_encoder->type) {
3320 case INTEL_OUTPUT_EDP:
3321 seq_puts(m, "eDP:\n");
3322 break;
3323 case INTEL_OUTPUT_DSI:
3324 seq_puts(m, "DSI:\n");
3325 break;
3326 case INTEL_OUTPUT_HDMI:
3327 seq_puts(m, "HDMI:\n");
3328 break;
3329 case INTEL_OUTPUT_DISPLAYPORT:
3330 seq_puts(m, "DP:\n");
3331 break;
3332 default:
3333 seq_printf(m, "Other encoder (id=%d).\n",
3334 intel_encoder->type);
3335 return;
3336 }
3337 }
3338
3339 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3340 seq_puts(m, "\tVBT: DRRS_type: Static");
3341 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3342 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3343 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3344 seq_puts(m, "\tVBT: DRRS_type: None");
3345 else
3346 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3347
3348 seq_puts(m, "\n\n");
3349
f77076c9 3350 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3351 struct intel_panel *panel;
3352
3353 mutex_lock(&drrs->mutex);
3354 /* DRRS Supported */
3355 seq_puts(m, "\tDRRS Supported: Yes\n");
3356
3357 /* disable_drrs() will make drrs->dp NULL */
3358 if (!drrs->dp) {
3359 seq_puts(m, "Idleness DRRS: Disabled");
3360 mutex_unlock(&drrs->mutex);
3361 return;
3362 }
3363
3364 panel = &drrs->dp->attached_connector->panel;
3365 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3366 drrs->busy_frontbuffer_bits);
3367
3368 seq_puts(m, "\n\t\t");
3369 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3370 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3371 vrefresh = panel->fixed_mode->vrefresh;
3372 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3373 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3374 vrefresh = panel->downclock_mode->vrefresh;
3375 } else {
3376 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3377 drrs->refresh_rate_type);
3378 mutex_unlock(&drrs->mutex);
3379 return;
3380 }
3381 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3382
3383 seq_puts(m, "\n\t\t");
3384 mutex_unlock(&drrs->mutex);
3385 } else {
3386 /* DRRS not supported. Print the VBT parameter*/
3387 seq_puts(m, "\tDRRS Supported : No");
3388 }
3389 seq_puts(m, "\n");
3390}
3391
3392static int i915_drrs_status(struct seq_file *m, void *unused)
3393{
3394 struct drm_info_node *node = m->private;
3395 struct drm_device *dev = node->minor->dev;
3396 struct intel_crtc *intel_crtc;
3397 int active_crtc_cnt = 0;
3398
3399 for_each_intel_crtc(dev, intel_crtc) {
3400 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3401
f77076c9 3402 if (intel_crtc->base.state->active) {
a54746e3
VK		 3403 active_crtc_cnt++;
3404 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3405
3406 drrs_status_per_crtc(m, dev, intel_crtc);
3407 }
3408
3409 drm_modeset_unlock(&intel_crtc->base.mutex);
3410 }
3411
3412 if (!active_crtc_cnt)
3413 seq_puts(m, "No active crtc found\n");
3414
3415 return 0;
3416}
3417
07144428
DL		 3418struct pipe_crc_info {
3419 const char *name;
3420 struct drm_device *dev;
3421 enum pipe pipe;
3422};
3423
11bed958
DA		 3424static int i915_dp_mst_info(struct seq_file *m, void *unused)
3425{
3426 struct drm_info_node *node = (struct drm_info_node *) m->private;
3427 struct drm_device *dev = node->minor->dev;
3428 struct drm_encoder *encoder;
3429 struct intel_encoder *intel_encoder;
3430 struct intel_digital_port *intel_dig_port;
3431 drm_modeset_lock_all(dev);
3432 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3433 intel_encoder = to_intel_encoder(encoder);
3434 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3435 continue;
3436 intel_dig_port = enc_to_dig_port(encoder);
3437 if (!intel_dig_port->dp.can_mst)
3438 continue;
3439
3440 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3441 }
3442 drm_modeset_unlock_all(dev);
3443 return 0;
3444}
3445
07144428
DL		 3446static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3447{
be5c7a90
DL		 3448 struct pipe_crc_info *info = inode->i_private;
3449 struct drm_i915_private *dev_priv = info->dev->dev_private;
3450 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3451
7eb1c496
DV		 3452 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3453 return -ENODEV;
3454
d538bbdf
DL		 3455 spin_lock_irq(&pipe_crc->lock);
3456
3457 if (pipe_crc->opened) {
3458 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3459 return -EBUSY; /* already open */
3460 }
3461
d538bbdf 3462 pipe_crc->opened = true;
07144428
DL		 3463 filep->private_data = inode->i_private;
3464
d538bbdf
DL		 3465 spin_unlock_irq(&pipe_crc->lock);
3466
07144428
DL		 3467 return 0;
3468}
3469
3470static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3471{
be5c7a90
DL		 3472 struct pipe_crc_info *info = inode->i_private;
3473 struct drm_i915_private *dev_priv = info->dev->dev_private;
3474 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3475
d538bbdf
DL		 3476 spin_lock_irq(&pipe_crc->lock);
3477 pipe_crc->opened = false;
3478 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3479
07144428
DL		 3480 return 0;
3481}
3482
3483/* (6 fields, 8 chars each, space separated (5) + '\n') */
3484#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3485/* account for \'0' */
3486#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3487
3488static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3489{
d538bbdf
DL		 3490 assert_spin_locked(&pipe_crc->lock);
3491 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3492 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3493}
3494
3495static ssize_t
3496i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3497 loff_t *pos)
3498{
3499 struct pipe_crc_info *info = filep->private_data;
3500 struct drm_device *dev = info->dev;
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3502 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3503 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3504 int n_entries;
07144428
DL		 3505 ssize_t bytes_read;
3506
3507 /*
3508 * Don't allow user space to provide buffers not big enough to hold
3509 * a line of data.
3510 */
3511 if (count < PIPE_CRC_LINE_LEN)
3512 return -EINVAL;
3513
3514 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3515 return 0;
07144428
DL		 3516
3517 /* nothing to read */
d538bbdf 3518 spin_lock_irq(&pipe_crc->lock);
07144428 3519 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3520 int ret;
3521
3522 if (filep->f_flags & O_NONBLOCK) {
3523 spin_unlock_irq(&pipe_crc->lock);
07144428 3524 return -EAGAIN;
d538bbdf 3525 }
07144428 3526
d538bbdf
DL		 3527 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3528 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3529 if (ret) {
3530 spin_unlock_irq(&pipe_crc->lock);
3531 return ret;
3532 }
8bf1e9f1
SH		 3533 }
3534
07144428 3535 /* We now have one or more entries to read */
9ad6d99f 3536 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3537
07144428 3538 bytes_read = 0;
9ad6d99f
VS		 3539 while (n_entries > 0) {
3540 struct intel_pipe_crc_entry *entry =
3541 &pipe_crc->entries[pipe_crc->tail];
07144428 3542 int ret;
8bf1e9f1 3543
9ad6d99f
VS		 3544 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3545 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3546 break;
3547
3548 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3549 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3550
07144428
DL		 3551 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3552 "%8u %8x %8x %8x %8x %8x\n",
3553 entry->frame, entry->crc[0],
3554 entry->crc[1], entry->crc[2],
3555 entry->crc[3], entry->crc[4]);
3556
9ad6d99f
VS		 3557 spin_unlock_irq(&pipe_crc->lock);
3558
3559 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3560 if (ret == PIPE_CRC_LINE_LEN)
3561 return -EFAULT;
b2c88f5b 3562
9ad6d99f
VS		 3563 user_buf += PIPE_CRC_LINE_LEN;
3564 n_entries--;
3565
3566 spin_lock_irq(&pipe_crc->lock);
3567 }
8bf1e9f1 3568
d538bbdf
DL		 3569 spin_unlock_irq(&pipe_crc->lock);
3570
07144428
DL		 3571 return bytes_read;
3572}
3573
3574static const struct file_operations i915_pipe_crc_fops = {
3575 .owner = THIS_MODULE,
3576 .open = i915_pipe_crc_open,
3577 .read = i915_pipe_crc_read,
3578 .release = i915_pipe_crc_release,
3579};
3580
3581static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3582 {
3583 .name = "i915_pipe_A_crc",
3584 .pipe = PIPE_A,
3585 },
3586 {
3587 .name = "i915_pipe_B_crc",
3588 .pipe = PIPE_B,
3589 },
3590 {
3591 .name = "i915_pipe_C_crc",
3592 .pipe = PIPE_C,
3593 },
3594};
3595
3596static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3597 enum pipe pipe)
3598{
3599 struct drm_device *dev = minor->dev;
3600 struct dentry *ent;
3601 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3602
3603 info->dev = dev;
3604 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3605 &i915_pipe_crc_fops);
f3c5fe97
WY		 3606 if (!ent)
3607 return -ENOMEM;
07144428
DL		 3608
3609 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3610}
3611
e8dfcf78 3612static const char * const pipe_crc_sources[] = {
926321d5
DV		 3613 "none",
3614 "plane1",
3615 "plane2",
3616 "pf",
5b3a856b 3617 "pipe",
3d099a05
DV		 3618 "TV",
3619 "DP-B",
3620 "DP-C",
3621 "DP-D",
46a19188 3622 "auto",
926321d5
DV		 3623};
3624
3625static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3626{
3627 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3628 return pipe_crc_sources[source];
3629}
3630
bd9db02f 3631static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3632{
3633 struct drm_device *dev = m->private;
3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 int i;
3636
3637 for (i = 0; i < I915_MAX_PIPES; i++)
3638 seq_printf(m, "%c %s\n", pipe_name(i),
3639 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3640
3641 return 0;
3642}
3643
bd9db02f 3644static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3645{
3646 struct drm_device *dev = inode->i_private;
3647
bd9db02f 3648 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3649}
3650
46a19188 3651static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3652 uint32_t *val)
3653{
46a19188
DV		 3654 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3655 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3656
3657 switch (*source) {
52f843f6
DV		 3658 case INTEL_PIPE_CRC_SOURCE_PIPE:
3659 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3660 break;
3661 case INTEL_PIPE_CRC_SOURCE_NONE:
3662 *val = 0;
3663 break;
3664 default:
3665 return -EINVAL;
3666 }
3667
3668 return 0;
3669}
3670
46a19188
DV		 3671static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3672 enum intel_pipe_crc_source *source)
3673{
3674 struct intel_encoder *encoder;
3675 struct intel_crtc *crtc;
26756809 3676 struct intel_digital_port *dig_port;
46a19188
DV		 3677 int ret = 0;
3678
3679 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3680
6e9f798d 3681 drm_modeset_lock_all(dev);
b2784e15 3682 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3683 if (!encoder->base.crtc)
3684 continue;
3685
3686 crtc = to_intel_crtc(encoder->base.crtc);
3687
3688 if (crtc->pipe != pipe)
3689 continue;
3690
3691 switch (encoder->type) {
3692 case INTEL_OUTPUT_TVOUT:
3693 *source = INTEL_PIPE_CRC_SOURCE_TV;
3694 break;
3695 case INTEL_OUTPUT_DISPLAYPORT:
3696 case INTEL_OUTPUT_EDP:
26756809
DV		 3697 dig_port = enc_to_dig_port(&encoder->base);
3698 switch (dig_port->port) {
3699 case PORT_B:
3700 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3701 break;
3702 case PORT_C:
3703 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3704 break;
3705 case PORT_D:
3706 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3707 break;
3708 default:
3709 WARN(1, "nonexisting DP port %c\n",
3710 port_name(dig_port->port));
3711 break;
3712 }
46a19188 3713 break;
6847d71b
PZ		 3714 default:
3715 break;
46a19188
DV		 3716 }
3717 }
6e9f798d 3718 drm_modeset_unlock_all(dev);
46a19188
DV		 3719
3720 return ret;
3721}
3722
3723static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3724 enum pipe pipe,
3725 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3726 uint32_t *val)
3727{
8d2f24ca
DV		 3728 struct drm_i915_private *dev_priv = dev->dev_private;
3729 bool need_stable_symbols = false;
3730
46a19188
DV		 3731 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3732 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3733 if (ret)
3734 return ret;
3735 }
3736
3737 switch (*source) {
7ac0129b
DV		 3738 case INTEL_PIPE_CRC_SOURCE_PIPE:
3739 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3740 break;
3741 case INTEL_PIPE_CRC_SOURCE_DP_B:
3742 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3743 need_stable_symbols = true;
7ac0129b
DV		 3744 break;
3745 case INTEL_PIPE_CRC_SOURCE_DP_C:
3746 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3747 need_stable_symbols = true;
7ac0129b 3748 break;
2be57922
VS		 3749 case INTEL_PIPE_CRC_SOURCE_DP_D:
3750 if (!IS_CHERRYVIEW(dev))
3751 return -EINVAL;
3752 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3753 need_stable_symbols = true;
3754 break;
7ac0129b
DV		 3755 case INTEL_PIPE_CRC_SOURCE_NONE:
3756 *val = 0;
3757 break;
3758 default:
3759 return -EINVAL;
3760 }
3761
8d2f24ca
DV		 3762 /*
3763 * When the pipe CRC tap point is after the transcoders we need
3764 * to tweak symbol-level features to produce a deterministic series of
3765 * symbols for a given frame. We need to reset those features only once
3766 * a frame (instead of every nth symbol):
3767 * - DC-balance: used to ensure a better clock recovery from the data
3768 * link (SDVO)
3769 * - DisplayPort scrambling: used for EMI reduction
3770 */
3771 if (need_stable_symbols) {
3772 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3773
8d2f24ca 3774 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3775 switch (pipe) {
3776 case PIPE_A:
8d2f24ca 3777 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3778 break;
3779 case PIPE_B:
8d2f24ca 3780 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3781 break;
3782 case PIPE_C:
3783 tmp |= PIPE_C_SCRAMBLE_RESET;
3784 break;
3785 default:
3786 return -EINVAL;
3787 }
8d2f24ca
DV		 3788 I915_WRITE(PORT_DFT2_G4X, tmp);
3789 }
3790
7ac0129b
DV		 3791 return 0;
3792}
3793
4b79ebf7 3794static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3795 enum pipe pipe,
3796 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3797 uint32_t *val)
3798{
84093603
DV		 3799 struct drm_i915_private *dev_priv = dev->dev_private;
3800 bool need_stable_symbols = false;
3801
46a19188
DV		 3802 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3803 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3804 if (ret)
3805 return ret;
3806 }
3807
3808 switch (*source) {
4b79ebf7
DV		 3809 case INTEL_PIPE_CRC_SOURCE_PIPE:
3810 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3811 break;
3812 case INTEL_PIPE_CRC_SOURCE_TV:
3813 if (!SUPPORTS_TV(dev))
3814 return -EINVAL;
3815 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3816 break;
3817 case INTEL_PIPE_CRC_SOURCE_DP_B:
3818 if (!IS_G4X(dev))
3819 return -EINVAL;
3820 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3821 need_stable_symbols = true;
4b79ebf7
DV		 3822 break;
3823 case INTEL_PIPE_CRC_SOURCE_DP_C:
3824 if (!IS_G4X(dev))
3825 return -EINVAL;
3826 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3827 need_stable_symbols = true;
4b79ebf7
DV		 3828 break;
3829 case INTEL_PIPE_CRC_SOURCE_DP_D:
3830 if (!IS_G4X(dev))
3831 return -EINVAL;
3832 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3833 need_stable_symbols = true;
4b79ebf7
DV		 3834 break;
3835 case INTEL_PIPE_CRC_SOURCE_NONE:
3836 *val = 0;
3837 break;
3838 default:
3839 return -EINVAL;
3840 }
3841
84093603
DV		 3842 /*
3843 * When the pipe CRC tap point is after the transcoders we need
3844 * to tweak symbol-level features to produce a deterministic series of
3845 * symbols for a given frame. We need to reset those features only once
3846 * a frame (instead of every nth symbol):
3847 * - DC-balance: used to ensure a better clock recovery from the data
3848 * link (SDVO)
3849 * - DisplayPort scrambling: used for EMI reduction
3850 */
3851 if (need_stable_symbols) {
3852 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3853
3854 WARN_ON(!IS_G4X(dev));
3855
3856 I915_WRITE(PORT_DFT_I9XX,
3857 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3858
3859 if (pipe == PIPE_A)
3860 tmp |= PIPE_A_SCRAMBLE_RESET;
3861 else
3862 tmp |= PIPE_B_SCRAMBLE_RESET;
3863
3864 I915_WRITE(PORT_DFT2_G4X, tmp);
3865 }
3866
4b79ebf7
DV		 3867 return 0;
3868}
3869
8d2f24ca
DV		 3870static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3871 enum pipe pipe)
3872{
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3875
eb736679
VS		 3876 switch (pipe) {
3877 case PIPE_A:
8d2f24ca 3878 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3879 break;
3880 case PIPE_B:
8d2f24ca 3881 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3882 break;
3883 case PIPE_C:
3884 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3885 break;
3886 default:
3887 return;
3888 }
8d2f24ca
DV		 3889 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3890 tmp &= ~DC_BALANCE_RESET_VLV;
3891 I915_WRITE(PORT_DFT2_G4X, tmp);
3892
3893}
3894
84093603
DV		 3895static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3896 enum pipe pipe)
3897{
3898 struct drm_i915_private *dev_priv = dev->dev_private;
3899 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3900
3901 if (pipe == PIPE_A)
3902 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3903 else
3904 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3905 I915_WRITE(PORT_DFT2_G4X, tmp);
3906
3907 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3908 I915_WRITE(PORT_DFT_I9XX,
3909 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3910 }
3911}
3912
46a19188 3913static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3914 uint32_t *val)
3915{
46a19188
DV		 3916 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3917 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3918
3919 switch (*source) {
5b3a856b
DV		 3920 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3921 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3922 break;
3923 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3924 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3925 break;
5b3a856b
DV		 3926 case INTEL_PIPE_CRC_SOURCE_PIPE:
3927 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3928 break;
3d099a05 3929 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3930 *val = 0;
3931 break;
3d099a05
DV		 3932 default:
3933 return -EINVAL;
5b3a856b
DV		 3934 }
3935
3936 return 0;
3937}
3938
c4e2d043 3939static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51
DV		 3940{
3941 struct drm_i915_private *dev_priv = dev->dev_private;
3942 struct intel_crtc *crtc =
3943 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3944 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3945 struct drm_atomic_state *state;
3946 int ret = 0;
fabf6e51
DV		 3947
3948 drm_modeset_lock_all(dev);
c4e2d043
ML		 3949 state = drm_atomic_state_alloc(dev);
3950 if (!state) {
3951 ret = -ENOMEM;
3952 goto out;
fabf6e51 3953 }
fabf6e51 3954
c4e2d043
ML		 3955 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3956 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3957 if (IS_ERR(pipe_config)) {
3958 ret = PTR_ERR(pipe_config);
3959 goto out;
3960 }
fabf6e51 3961
c4e2d043
ML		 3962 pipe_config->pch_pfit.force_thru = enable;
3963 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3964 pipe_config->pch_pfit.enabled != enable)
3965 pipe_config->base.connectors_changed = true;
1b509259 3966
c4e2d043
ML		 3967 ret = drm_atomic_commit(state);
3968out:
fabf6e51 3969 drm_modeset_unlock_all(dev);
c4e2d043
ML		 3970 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3971 if (ret)
3972 drm_atomic_state_free(state);
fabf6e51
DV		 3973}
3974
3975static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3976 enum pipe pipe,
3977 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3978 uint32_t *val)
3979{
46a19188
DV		 3980 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3981 *source = INTEL_PIPE_CRC_SOURCE_PF;
3982
3983 switch (*source) {
5b3a856b
DV		 3984 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3985 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3986 break;
3987 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3988 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3989 break;
3990 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 3991 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 3992 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 3993
5b3a856b
DV		 3994 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3995 break;
3d099a05 3996 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3997 *val = 0;
3998 break;
3d099a05
DV		 3999 default:
4000 return -EINVAL;
5b3a856b
DV		 4001 }
4002
4003 return 0;
4004}
4005
926321d5
DV		 4006static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4007 enum intel_pipe_crc_source source)
4008{
4009 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 4010 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 4011 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4012 pipe));
e129649b 4013 enum intel_display_power_domain power_domain;
432f3342 4014 u32 val = 0; /* shut up gcc */
5b3a856b 4015 int ret;
926321d5 4016
cc3da175
DL		 4017 if (pipe_crc->source == source)
4018 return 0;
4019
ae676fcd
DL		 4020 /* forbid changing the source without going back to 'none' */
4021 if (pipe_crc->source && source)
4022 return -EINVAL;
4023
e129649b
ID		 4024 power_domain = POWER_DOMAIN_PIPE(pipe);
4025 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9d8b0588
DV		 4026 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4027 return -EIO;
4028 }
4029
52f843f6 4030 if (IS_GEN2(dev))
46a19188 4031 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 4032 else if (INTEL_INFO(dev)->gen < 5)
46a19188 4033 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
666a4537 4034 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
fabf6e51 4035 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 4036 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 4037 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 4038 else
fabf6e51 4039 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 4040
4041 if (ret != 0)
e129649b 4042 goto out;
5b3a856b 4043
4b584369
DL		 4044 /* none -> real source transition */
4045 if (source) {
4252fbc3
VS		 4046 struct intel_pipe_crc_entry *entries;
4047
7cd6ccff
DL		 4048 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4049 pipe_name(pipe), pipe_crc_source_name(source));
4050
3cf54b34
VS		 4051 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4052 sizeof(pipe_crc->entries[0]),
4252fbc3 4053 GFP_KERNEL);
e129649b
ID		 4054 if (!entries) {
4055 ret = -ENOMEM;
4056 goto out;
4057 }
e5f75aca 4058
8c740dce
PZ		 4059 /*
4060 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4061 * enabled and disabled dynamically based on package C states,
4062 * user space can't make reliable use of the CRCs, so let's just
4063 * completely disable it.
4064 */
4065 hsw_disable_ips(crtc);
4066
d538bbdf 4067 spin_lock_irq(&pipe_crc->lock);
64387b61 4068 kfree(pipe_crc->entries);
4252fbc3 4069 pipe_crc->entries = entries;
d538bbdf
DL		 4070 pipe_crc->head = 0;
4071 pipe_crc->tail = 0;
4072 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 4073 }
4074
cc3da175 4075 pipe_crc->source = source;
926321d5 4076
926321d5
DV		 4077 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4078 POSTING_READ(PIPE_CRC_CTL(pipe));
4079
e5f75aca
DL		 4080 /* real source -> none transition */
4081 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 4082 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 4083 struct intel_crtc *crtc =
4084 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 4085
7cd6ccff
DL		 4086 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4087 pipe_name(pipe));
4088
a33d7105 4089 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 4090 if (crtc->base.state->active)
a33d7105
DV		 4091 intel_wait_for_vblank(dev, pipe);
4092 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 4093
d538bbdf
DL		 4094 spin_lock_irq(&pipe_crc->lock);
4095 entries = pipe_crc->entries;
e5f75aca 4096 pipe_crc->entries = NULL;
9ad6d99f
VS		 4097 pipe_crc->head = 0;
4098 pipe_crc->tail = 0;
d538bbdf
DL		 4099 spin_unlock_irq(&pipe_crc->lock);
4100
4101 kfree(entries);
84093603
DV		 4102
4103 if (IS_G4X(dev))
4104 g4x_undo_pipe_scramble_reset(dev, pipe);
666a4537 4105 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
8d2f24ca 4106 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 4107 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4108 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 4109
4110 hsw_enable_ips(crtc);
e5f75aca
DL		 4111 }
4112
e129649b
ID		 4113 ret = 0;
4114
4115out:
4116 intel_display_power_put(dev_priv, power_domain);
4117
4118 return ret;
926321d5
DV		 4119}
4120
4121/*
4122 * Parse pipe CRC command strings:
b94dec87
DL		 4123 * command: wsp* object wsp+ name wsp+ source wsp*
4124 * object: 'pipe'
4125 * name: (A | B | C)
926321d5
DV		 4126 * source: (none | plane1 | plane2 | pf)
4127 * wsp: (#0x20 | #0x9 | #0xA)+
4128 *
4129 * eg.:
b94dec87
DL		 4130 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4131 * "pipe A none" -> Stop CRC
926321d5 4132 */
bd9db02f 4133static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 4134{
4135 int n_words = 0;
4136
4137 while (*buf) {
4138 char *end;
4139
4140 /* skip leading white space */
4141 buf = skip_spaces(buf);
4142 if (!*buf)
4143 break; /* end of buffer */
4144
4145 /* find end of word */
4146 for (end = buf; *end && !isspace(*end); end++)
4147 ;
4148
4149 if (n_words == max_words) {
4150 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4151 max_words);
4152 return -EINVAL; /* ran out of words[] before bytes */
4153 }
4154
4155 if (*end)
4156 *end++ = '\0';
4157 words[n_words++] = buf;
4158 buf = end;
4159 }
4160
4161 return n_words;
4162}
4163
b94dec87
DL		 4164enum intel_pipe_crc_object {
4165 PIPE_CRC_OBJECT_PIPE,
4166};
4167
e8dfcf78 4168static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4169 "pipe",
4170};
4171
4172static int
bd9db02f 4173display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4174{
4175 int i;
4176
4177 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4178 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4179 *o = i;
b94dec87
DL		 4180 return 0;
4181 }
4182
4183 return -EINVAL;
4184}
4185
bd9db02f 4186static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4187{
4188 const char name = buf[0];
4189
4190 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4191 return -EINVAL;
4192
4193 *pipe = name - 'A';
4194
4195 return 0;
4196}
4197
4198static int
bd9db02f 4199display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4200{
4201 int i;
4202
4203 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4204 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4205 *s = i;
926321d5
DV		 4206 return 0;
4207 }
4208
4209 return -EINVAL;
4210}
4211
bd9db02f 4212static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 4213{
b94dec87 4214#define N_WORDS 3
926321d5 4215 int n_words;
b94dec87 4216 char *words[N_WORDS];
926321d5 4217 enum pipe pipe;
b94dec87 4218 enum intel_pipe_crc_object object;
926321d5
DV		 4219 enum intel_pipe_crc_source source;
4220
bd9db02f 4221 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4222 if (n_words != N_WORDS) {
4223 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4224 N_WORDS);
4225 return -EINVAL;
4226 }
4227
bd9db02f 4228 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4229 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4230 return -EINVAL;
4231 }
4232
bd9db02f 4233 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4234 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4235 return -EINVAL;
4236 }
4237
bd9db02f 4238 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4239 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4240 return -EINVAL;
4241 }
4242
4243 return pipe_crc_set_source(dev, pipe, source);
4244}
4245
bd9db02f
DL		 4246static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4247 size_t len, loff_t *offp)
926321d5
DV		 4248{
4249 struct seq_file *m = file->private_data;
4250 struct drm_device *dev = m->private;
4251 char *tmpbuf;
4252 int ret;
4253
4254 if (len == 0)
4255 return 0;
4256
4257 if (len > PAGE_SIZE - 1) {
4258 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4259 PAGE_SIZE);
4260 return -E2BIG;
4261 }
4262
4263 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4264 if (!tmpbuf)
4265 return -ENOMEM;
4266
4267 if (copy_from_user(tmpbuf, ubuf, len)) {
4268 ret = -EFAULT;
4269 goto out;
4270 }
4271 tmpbuf[len] = '\0';
4272
bd9db02f 4273 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4274
4275out:
4276 kfree(tmpbuf);
4277 if (ret < 0)
4278 return ret;
4279
4280 *offp += len;
4281 return len;
4282}
4283
bd9db02f 4284static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4285 .owner = THIS_MODULE,
bd9db02f 4286 .open = display_crc_ctl_open,
926321d5
DV		 4287 .read = seq_read,
4288 .llseek = seq_lseek,
4289 .release = single_release,
bd9db02f 4290 .write = display_crc_ctl_write
926321d5
DV		 4291};
4292
eb3394fa
TP		 4293static ssize_t i915_displayport_test_active_write(struct file *file,
4294 const char __user *ubuf,
4295 size_t len, loff_t *offp)
4296{
4297 char *input_buffer;
4298 int status = 0;
eb3394fa
TP		 4299 struct drm_device *dev;
4300 struct drm_connector *connector;
4301 struct list_head *connector_list;
4302 struct intel_dp *intel_dp;
4303 int val = 0;
4304
9aaffa34 4305 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4306
eb3394fa
TP		 4307 connector_list = &dev->mode_config.connector_list;
4308
4309 if (len == 0)
4310 return 0;
4311
4312 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4313 if (!input_buffer)
4314 return -ENOMEM;
4315
4316 if (copy_from_user(input_buffer, ubuf, len)) {
4317 status = -EFAULT;
4318 goto out;
4319 }
4320
4321 input_buffer[len] = '\0';
4322 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4323
4324 list_for_each_entry(connector, connector_list, head) {
4325
4326 if (connector->connector_type !=
4327 DRM_MODE_CONNECTOR_DisplayPort)
4328 continue;
4329
b8bb08ec 4330 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4331 connector->encoder != NULL) {
4332 intel_dp = enc_to_intel_dp(connector->encoder);
4333 status = kstrtoint(input_buffer, 10, &val);
4334 if (status < 0)
4335 goto out;
4336 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4337 /* To prevent erroneous activation of the compliance
4338 * testing code, only accept an actual value of 1 here
4339 */
4340 if (val == 1)
4341 intel_dp->compliance_test_active = 1;
4342 else
4343 intel_dp->compliance_test_active = 0;
4344 }
4345 }
4346out:
4347 kfree(input_buffer);
4348 if (status < 0)
4349 return status;
4350
4351 *offp += len;
4352 return len;
4353}
4354
4355static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4356{
4357 struct drm_device *dev = m->private;
4358 struct drm_connector *connector;
4359 struct list_head *connector_list = &dev->mode_config.connector_list;
4360 struct intel_dp *intel_dp;
4361
eb3394fa
TP		 4362 list_for_each_entry(connector, connector_list, head) {
4363
4364 if (connector->connector_type !=
4365 DRM_MODE_CONNECTOR_DisplayPort)
4366 continue;
4367
4368 if (connector->status == connector_status_connected &&
4369 connector->encoder != NULL) {
4370 intel_dp = enc_to_intel_dp(connector->encoder);
4371 if (intel_dp->compliance_test_active)
4372 seq_puts(m, "1");
4373 else
4374 seq_puts(m, "0");
4375 } else
4376 seq_puts(m, "0");
4377 }
4378
4379 return 0;
4380}
4381
4382static int i915_displayport_test_active_open(struct inode *inode,
4383 struct file *file)
4384{
4385 struct drm_device *dev = inode->i_private;
4386
4387 return single_open(file, i915_displayport_test_active_show, dev);
4388}
4389
4390static const struct file_operations i915_displayport_test_active_fops = {
4391 .owner = THIS_MODULE,
4392 .open = i915_displayport_test_active_open,
4393 .read = seq_read,
4394 .llseek = seq_lseek,
4395 .release = single_release,
4396 .write = i915_displayport_test_active_write
4397};
4398
4399static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4400{
4401 struct drm_device *dev = m->private;
4402 struct drm_connector *connector;
4403 struct list_head *connector_list = &dev->mode_config.connector_list;
4404 struct intel_dp *intel_dp;
4405
eb3394fa
TP		 4406 list_for_each_entry(connector, connector_list, head) {
4407
4408 if (connector->connector_type !=
4409 DRM_MODE_CONNECTOR_DisplayPort)
4410 continue;
4411
4412 if (connector->status == connector_status_connected &&
4413 connector->encoder != NULL) {
4414 intel_dp = enc_to_intel_dp(connector->encoder);
4415 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4416 } else
4417 seq_puts(m, "0");
4418 }
4419
4420 return 0;
4421}
4422static int i915_displayport_test_data_open(struct inode *inode,
4423 struct file *file)
4424{
4425 struct drm_device *dev = inode->i_private;
4426
4427 return single_open(file, i915_displayport_test_data_show, dev);
4428}
4429
4430static const struct file_operations i915_displayport_test_data_fops = {
4431 .owner = THIS_MODULE,
4432 .open = i915_displayport_test_data_open,
4433 .read = seq_read,
4434 .llseek = seq_lseek,
4435 .release = single_release
4436};
4437
4438static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4439{
4440 struct drm_device *dev = m->private;
4441 struct drm_connector *connector;
4442 struct list_head *connector_list = &dev->mode_config.connector_list;
4443 struct intel_dp *intel_dp;
4444
eb3394fa
TP		 4445 list_for_each_entry(connector, connector_list, head) {
4446
4447 if (connector->connector_type !=
4448 DRM_MODE_CONNECTOR_DisplayPort)
4449 continue;
4450
4451 if (connector->status == connector_status_connected &&
4452 connector->encoder != NULL) {
4453 intel_dp = enc_to_intel_dp(connector->encoder);
4454 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4455 } else
4456 seq_puts(m, "0");
4457 }
4458
4459 return 0;
4460}
4461
4462static int i915_displayport_test_type_open(struct inode *inode,
4463 struct file *file)
4464{
4465 struct drm_device *dev = inode->i_private;
4466
4467 return single_open(file, i915_displayport_test_type_show, dev);
4468}
4469
4470static const struct file_operations i915_displayport_test_type_fops = {
4471 .owner = THIS_MODULE,
4472 .open = i915_displayport_test_type_open,
4473 .read = seq_read,
4474 .llseek = seq_lseek,
4475 .release = single_release
4476};
4477
97e94b22 4478static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4479{
4480 struct drm_device *dev = m->private;
369a1342 4481 int level;
de38b95c
VS		 4482 int num_levels;
4483
4484 if (IS_CHERRYVIEW(dev))
4485 num_levels = 3;
4486 else if (IS_VALLEYVIEW(dev))
4487 num_levels = 1;
4488 else
4489 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4490
4491 drm_modeset_lock_all(dev);
4492
4493 for (level = 0; level < num_levels; level++) {
4494 unsigned int latency = wm[level];
4495
97e94b22
DL		 4496 /*
4497 * - WM1+ latency values in 0.5us units
de38b95c 4498 * - latencies are in us on gen9/vlv/chv
97e94b22 4499 */
666a4537
WB		 4500 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4501 IS_CHERRYVIEW(dev))
97e94b22
DL		 4502 latency *= 10;
4503 else if (level > 0)
369a1342
VS		 4504 latency *= 5;
4505
4506 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4507 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4508 }
4509
4510 drm_modeset_unlock_all(dev);
4511}
4512
4513static int pri_wm_latency_show(struct seq_file *m, void *data)
4514{
4515 struct drm_device *dev = m->private;
97e94b22
DL		 4516 struct drm_i915_private *dev_priv = dev->dev_private;
4517 const uint16_t *latencies;
4518
4519 if (INTEL_INFO(dev)->gen >= 9)
4520 latencies = dev_priv->wm.skl_latency;
4521 else
4522 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4523
97e94b22 4524 wm_latency_show(m, latencies);
369a1342
VS		 4525
4526 return 0;
4527}
4528
4529static int spr_wm_latency_show(struct seq_file *m, void *data)
4530{
4531 struct drm_device *dev = m->private;
97e94b22
DL		 4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 const uint16_t *latencies;
4534
4535 if (INTEL_INFO(dev)->gen >= 9)
4536 latencies = dev_priv->wm.skl_latency;
4537 else
4538 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4539
97e94b22 4540 wm_latency_show(m, latencies);
369a1342
VS		 4541
4542 return 0;
4543}
4544
4545static int cur_wm_latency_show(struct seq_file *m, void *data)
4546{
4547 struct drm_device *dev = m->private;
97e94b22
DL		 4548 struct drm_i915_private *dev_priv = dev->dev_private;
4549 const uint16_t *latencies;
4550
4551 if (INTEL_INFO(dev)->gen >= 9)
4552 latencies = dev_priv->wm.skl_latency;
4553 else
4554 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4555
97e94b22 4556 wm_latency_show(m, latencies);
369a1342
VS		 4557
4558 return 0;
4559}
4560
4561static int pri_wm_latency_open(struct inode *inode, struct file *file)
4562{
4563 struct drm_device *dev = inode->i_private;
4564
de38b95c 4565 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4566 return -ENODEV;
4567
4568 return single_open(file, pri_wm_latency_show, dev);
4569}
4570
4571static int spr_wm_latency_open(struct inode *inode, struct file *file)
4572{
4573 struct drm_device *dev = inode->i_private;
4574
9ad0257c 4575 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4576 return -ENODEV;
4577
4578 return single_open(file, spr_wm_latency_show, dev);
4579}
4580
4581static int cur_wm_latency_open(struct inode *inode, struct file *file)
4582{
4583 struct drm_device *dev = inode->i_private;
4584
9ad0257c 4585 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4586 return -ENODEV;
4587
4588 return single_open(file, cur_wm_latency_show, dev);
4589}
4590
4591static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4592 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4593{
4594 struct seq_file *m = file->private_data;
4595 struct drm_device *dev = m->private;
97e94b22 4596 uint16_t new[8] = { 0 };
de38b95c 4597 int num_levels;
369a1342
VS		 4598 int level;
4599 int ret;
4600 char tmp[32];
4601
de38b95c
VS		 4602 if (IS_CHERRYVIEW(dev))
4603 num_levels = 3;
4604 else if (IS_VALLEYVIEW(dev))
4605 num_levels = 1;
4606 else
4607 num_levels = ilk_wm_max_level(dev) + 1;
4608
369a1342
VS		 4609 if (len >= sizeof(tmp))
4610 return -EINVAL;
4611
4612 if (copy_from_user(tmp, ubuf, len))
4613 return -EFAULT;
4614
4615 tmp[len] = '\0';
4616
97e94b22
DL		 4617 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4618 &new[0], &new[1], &new[2], &new[3],
4619 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4620 if (ret != num_levels)
4621 return -EINVAL;
4622
4623 drm_modeset_lock_all(dev);
4624
4625 for (level = 0; level < num_levels; level++)
4626 wm[level] = new[level];
4627
4628 drm_modeset_unlock_all(dev);
4629
4630 return len;
4631}
4632
4633
4634static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4635 size_t len, loff_t *offp)
4636{
4637 struct seq_file *m = file->private_data;
4638 struct drm_device *dev = m->private;
97e94b22
DL		 4639 struct drm_i915_private *dev_priv = dev->dev_private;
4640 uint16_t *latencies;
369a1342 4641
97e94b22
DL		 4642 if (INTEL_INFO(dev)->gen >= 9)
4643 latencies = dev_priv->wm.skl_latency;
4644 else
4645 latencies = to_i915(dev)->wm.pri_latency;
4646
4647 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4648}
4649
4650static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4651 size_t len, loff_t *offp)
4652{
4653 struct seq_file *m = file->private_data;
4654 struct drm_device *dev = m->private;
97e94b22
DL		 4655 struct drm_i915_private *dev_priv = dev->dev_private;
4656 uint16_t *latencies;
369a1342 4657
97e94b22
DL		 4658 if (INTEL_INFO(dev)->gen >= 9)
4659 latencies = dev_priv->wm.skl_latency;
4660 else
4661 latencies = to_i915(dev)->wm.spr_latency;
4662
4663 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4664}
4665
4666static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4667 size_t len, loff_t *offp)
4668{
4669 struct seq_file *m = file->private_data;
4670 struct drm_device *dev = m->private;
97e94b22
DL		 4671 struct drm_i915_private *dev_priv = dev->dev_private;
4672 uint16_t *latencies;
4673
4674 if (INTEL_INFO(dev)->gen >= 9)
4675 latencies = dev_priv->wm.skl_latency;
4676 else
4677 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4678
97e94b22 4679 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4680}
4681
4682static const struct file_operations i915_pri_wm_latency_fops = {
4683 .owner = THIS_MODULE,
4684 .open = pri_wm_latency_open,
4685 .read = seq_read,
4686 .llseek = seq_lseek,
4687 .release = single_release,
4688 .write = pri_wm_latency_write
4689};
4690
4691static const struct file_operations i915_spr_wm_latency_fops = {
4692 .owner = THIS_MODULE,
4693 .open = spr_wm_latency_open,
4694 .read = seq_read,
4695 .llseek = seq_lseek,
4696 .release = single_release,
4697 .write = spr_wm_latency_write
4698};
4699
4700static const struct file_operations i915_cur_wm_latency_fops = {
4701 .owner = THIS_MODULE,
4702 .open = cur_wm_latency_open,
4703 .read = seq_read,
4704 .llseek = seq_lseek,
4705 .release = single_release,
4706 .write = cur_wm_latency_write
4707};
4708
647416f9
KC		 4709static int
4710i915_wedged_get(void *data, u64 *val)
f3cd474b 4711{
647416f9 4712 struct drm_device *dev = data;
e277a1f8 4713 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4714
647416f9 4715 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4716
647416f9 4717 return 0;
f3cd474b
CW		 4718}
4719
647416f9
KC		 4720static int
4721i915_wedged_set(void *data, u64 val)
f3cd474b 4722{
647416f9 4723 struct drm_device *dev = data;
d46c0517
ID		 4724 struct drm_i915_private *dev_priv = dev->dev_private;
4725
b8d24a06
MK		 4726 /*
4727 * There is no safeguard against this debugfs entry colliding
4728 * with the hangcheck calling same i915_handle_error() in
4729 * parallel, causing an explosion. For now we assume that the
4730 * test harness is responsible enough not to inject gpu hangs
4731 * while it is writing to 'i915_wedged'
4732 */
4733
4734 if (i915_reset_in_progress(&dev_priv->gpu_error))
4735 return -EAGAIN;
4736
d46c0517 4737 intel_runtime_pm_get(dev_priv);
f3cd474b 4738
58174462
MK		 4739 i915_handle_error(dev, val,
4740 "Manually setting wedged to %llu", val);
d46c0517
ID		 4741
4742 intel_runtime_pm_put(dev_priv);
4743
647416f9 4744 return 0;
f3cd474b
CW		 4745}
4746
647416f9
KC		 4747DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4748 i915_wedged_get, i915_wedged_set,
3a3b4f98 4749 "%llu\n");
f3cd474b 4750
647416f9
KC		 4751static int
4752i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4753{
647416f9 4754 struct drm_device *dev = data;
e277a1f8 4755 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4756
647416f9 4757 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4758
647416f9 4759 return 0;
e5eb3d63
DV		 4760}
4761
647416f9
KC		 4762static int
4763i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4764{
647416f9 4765 struct drm_device *dev = data;
e5eb3d63 4766 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4767 int ret;
e5eb3d63 4768
647416f9 4769 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4770
22bcfc6a
DV		 4771 ret = mutex_lock_interruptible(&dev->struct_mutex);
4772 if (ret)
4773 return ret;
4774
99584db3 4775 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4776 mutex_unlock(&dev->struct_mutex);
4777
647416f9 4778 return 0;
e5eb3d63
DV		 4779}
4780
647416f9
KC		 4781DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4782 i915_ring_stop_get, i915_ring_stop_set,
4783 "0x%08llx\n");
d5442303 4784
094f9a54
CW		 4785static int
4786i915_ring_missed_irq_get(void *data, u64 *val)
4787{
4788 struct drm_device *dev = data;
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790
4791 *val = dev_priv->gpu_error.missed_irq_rings;
4792 return 0;
4793}
4794
4795static int
4796i915_ring_missed_irq_set(void *data, u64 val)
4797{
4798 struct drm_device *dev = data;
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800 int ret;
4801
4802 /* Lock against concurrent debugfs callers */
4803 ret = mutex_lock_interruptible(&dev->struct_mutex);
4804 if (ret)
4805 return ret;
4806 dev_priv->gpu_error.missed_irq_rings = val;
4807 mutex_unlock(&dev->struct_mutex);
4808
4809 return 0;
4810}
4811
4812DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4813 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4814 "0x%08llx\n");
4815
4816static int
4817i915_ring_test_irq_get(void *data, u64 *val)
4818{
4819 struct drm_device *dev = data;
4820 struct drm_i915_private *dev_priv = dev->dev_private;
4821
4822 *val = dev_priv->gpu_error.test_irq_rings;
4823
4824 return 0;
4825}
4826
4827static int
4828i915_ring_test_irq_set(void *data, u64 val)
4829{
4830 struct drm_device *dev = data;
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 int ret;
4833
4834 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4835
4836 /* Lock against concurrent debugfs callers */
4837 ret = mutex_lock_interruptible(&dev->struct_mutex);
4838 if (ret)
4839 return ret;
4840
4841 dev_priv->gpu_error.test_irq_rings = val;
4842 mutex_unlock(&dev->struct_mutex);
4843
4844 return 0;
4845}
4846
4847DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4848 i915_ring_test_irq_get, i915_ring_test_irq_set,
4849 "0x%08llx\n");
4850
dd624afd
CW		 4851#define DROP_UNBOUND 0x1
4852#define DROP_BOUND 0x2
4853#define DROP_RETIRE 0x4
4854#define DROP_ACTIVE 0x8
4855#define DROP_ALL (DROP_UNBOUND | \
4856 DROP_BOUND | \
4857 DROP_RETIRE | \
4858 DROP_ACTIVE)
647416f9
KC		 4859static int
4860i915_drop_caches_get(void *data, u64 *val)
dd624afd 4861{
647416f9 4862 *val = DROP_ALL;
dd624afd 4863
647416f9 4864 return 0;
dd624afd
CW		 4865}
4866
647416f9
KC		 4867static int
4868i915_drop_caches_set(void *data, u64 val)
dd624afd 4869{
647416f9 4870 struct drm_device *dev = data;
dd624afd 4871 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4872 int ret;
dd624afd 4873
2f9fe5ff 4874 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4875
4876 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4877 * on ioctls on -EAGAIN. */
4878 ret = mutex_lock_interruptible(&dev->struct_mutex);
4879 if (ret)
4880 return ret;
4881
4882 if (val & DROP_ACTIVE) {
4883 ret = i915_gpu_idle(dev);
4884 if (ret)
4885 goto unlock;
4886 }
4887
4888 if (val & (DROP_RETIRE | DROP_ACTIVE))
4889 i915_gem_retire_requests(dev);
4890
21ab4e74
CW		 4891 if (val & DROP_BOUND)
4892 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4893
21ab4e74
CW		 4894 if (val & DROP_UNBOUND)
4895 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4896
4897unlock:
4898 mutex_unlock(&dev->struct_mutex);
4899
647416f9 4900 return ret;
dd624afd
CW		 4901}
4902
647416f9
KC		 4903DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4904 i915_drop_caches_get, i915_drop_caches_set,
4905 "0x%08llx\n");
dd624afd 4906
647416f9
KC		 4907static int
4908i915_max_freq_get(void *data, u64 *val)
358733e9 4909{
647416f9 4910 struct drm_device *dev = data;
e277a1f8 4911 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4912 int ret;
004777cb 4913
daa3afb2 4914 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4915 return -ENODEV;
4916
5c9669ce
TR		 4917 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4918
4fc688ce 4919 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4920 if (ret)
4921 return ret;
358733e9 4922
7c59a9c1 4923 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4924 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4925
647416f9 4926 return 0;
358733e9
JB		 4927}
4928
647416f9
KC		 4929static int
4930i915_max_freq_set(void *data, u64 val)
358733e9 4931{
647416f9 4932 struct drm_device *dev = data;
358733e9 4933 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4934 u32 hw_max, hw_min;
647416f9 4935 int ret;
004777cb 4936
daa3afb2 4937 if (INTEL_INFO(dev)->gen < 6)
004777cb 4938 return -ENODEV;
358733e9 4939
5c9669ce
TR		 4940 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4941
647416f9 4942 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4943
4fc688ce 4944 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4945 if (ret)
4946 return ret;
4947
358733e9
JB		 4948 /*
4949 * Turbo will still be enabled, but won't go above the set value.
4950 */
bc4d91f6 4951 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4952
bc4d91f6
AG		 4953 hw_max = dev_priv->rps.max_freq;
4954 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4955
b39fb297 4956 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4957 mutex_unlock(&dev_priv->rps.hw_lock);
4958 return -EINVAL;
0a073b84
JB		 4959 }
4960
b39fb297 4961 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4962
ffe02b40 4963 intel_set_rps(dev, val);
dd0a1aa1 4964
4fc688ce 4965 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4966
647416f9 4967 return 0;
358733e9
JB		 4968}
4969
647416f9
KC		 4970DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4971 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4972 "%llu\n");
358733e9 4973
647416f9
KC		 4974static int
4975i915_min_freq_get(void *data, u64 *val)
1523c310 4976{
647416f9 4977 struct drm_device *dev = data;
e277a1f8 4978 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4979 int ret;
004777cb 4980
daa3afb2 4981 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4982 return -ENODEV;
4983
5c9669ce
TR		 4984 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4985
4fc688ce 4986 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4987 if (ret)
4988 return ret;
1523c310 4989
7c59a9c1 4990 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4991 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4992
647416f9 4993 return 0;
1523c310
JB		 4994}
4995
647416f9
KC		 4996static int
4997i915_min_freq_set(void *data, u64 val)
1523c310 4998{
647416f9 4999 struct drm_device *dev = data;
1523c310 5000 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 5001 u32 hw_max, hw_min;
647416f9 5002 int ret;
004777cb 5003
daa3afb2 5004 if (INTEL_INFO(dev)->gen < 6)
004777cb 5005 return -ENODEV;
1523c310 5006
5c9669ce
TR		 5007 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5008
647416f9 5009 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 5010
4fc688ce 5011 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 5012 if (ret)
5013 return ret;
5014
1523c310
JB		 5015 /*
5016 * Turbo will still be enabled, but won't go below the set value.
5017 */
bc4d91f6 5018 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 5019
bc4d91f6
AG		 5020 hw_max = dev_priv->rps.max_freq;
5021 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 5022
b39fb297 5023 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 5024 mutex_unlock(&dev_priv->rps.hw_lock);
5025 return -EINVAL;
0a073b84 5026 }
dd0a1aa1 5027
b39fb297 5028 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 5029
ffe02b40 5030 intel_set_rps(dev, val);
dd0a1aa1 5031
4fc688ce 5032 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 5033
647416f9 5034 return 0;
1523c310
JB		 5035}
5036
647416f9
KC		 5037DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5038 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 5039 "%llu\n");
1523c310 5040
647416f9
KC		 5041static int
5042i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 5043{
647416f9 5044 struct drm_device *dev = data;
e277a1f8 5045 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5046 u32 snpcr;
647416f9 5047 int ret;
07b7ddd9 5048
004777cb
DV		 5049 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5050 return -ENODEV;
5051
22bcfc6a
DV		 5052 ret = mutex_lock_interruptible(&dev->struct_mutex);
5053 if (ret)
5054 return ret;
c8c8fb33 5055 intel_runtime_pm_get(dev_priv);
22bcfc6a 5056
07b7ddd9 5057 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 5058
5059 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 5060 mutex_unlock(&dev_priv->dev->struct_mutex);
5061
647416f9 5062 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 5063
647416f9 5064 return 0;
07b7ddd9
JB		 5065}
5066
647416f9
KC		 5067static int
5068i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 5069{
647416f9 5070 struct drm_device *dev = data;
07b7ddd9 5071 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5072 u32 snpcr;
07b7ddd9 5073
004777cb
DV		 5074 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5075 return -ENODEV;
5076
647416f9 5077 if (val > 3)
07b7ddd9
JB		 5078 return -EINVAL;
5079
c8c8fb33 5080 intel_runtime_pm_get(dev_priv);
647416f9 5081 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 5082
5083 /* Update the cache sharing policy here as well */
5084 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5085 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5086 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5087 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5088
c8c8fb33 5089 intel_runtime_pm_put(dev_priv);
647416f9 5090 return 0;
07b7ddd9
JB		 5091}
5092
647416f9
KC		 5093DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5094 i915_cache_sharing_get, i915_cache_sharing_set,
5095 "%llu\n");
07b7ddd9 5096
5d39525a
JM		 5097struct sseu_dev_status {
5098 unsigned int slice_total;
5099 unsigned int subslice_total;
5100 unsigned int subslice_per_slice;
5101 unsigned int eu_total;
5102 unsigned int eu_per_subslice;
5103};
5104
5105static void cherryview_sseu_device_status(struct drm_device *dev,
5106 struct sseu_dev_status *stat)
5107{
5108 struct drm_i915_private *dev_priv = dev->dev_private;
0a0b457f 5109 int ss_max = 2;
5d39525a
JM		 5110 int ss;
5111 u32 sig1[ss_max], sig2[ss_max];
5112
5113 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5114 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5115 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5116 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5117
5118 for (ss = 0; ss < ss_max; ss++) {
5119 unsigned int eu_cnt;
5120
5121 if (sig1[ss] & CHV_SS_PG_ENABLE)
5122 /* skip disabled subslice */
5123 continue;
5124
5125 stat->slice_total = 1;
5126 stat->subslice_per_slice++;
5127 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5128 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5129 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5130 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5131 stat->eu_total += eu_cnt;
5132 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5133 }
5134 stat->subslice_total = stat->subslice_per_slice;
5135}
5136
5137static void gen9_sseu_device_status(struct drm_device *dev,
5138 struct sseu_dev_status *stat)
5139{
5140 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 5141 int s_max = 3, ss_max = 4;
5d39525a
JM		 5142 int s, ss;
5143 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5144
1c046bc1
JM		 5145 /* BXT has a single slice and at most 3 subslices. */
5146 if (IS_BROXTON(dev)) {
5147 s_max = 1;
5148 ss_max = 3;
5149 }
5150
5151 for (s = 0; s < s_max; s++) {
5152 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5153 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5154 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5155 }
5156
5d39525a
JM		 5157 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5158 GEN9_PGCTL_SSA_EU19_ACK |
5159 GEN9_PGCTL_SSA_EU210_ACK |
5160 GEN9_PGCTL_SSA_EU311_ACK;
5161 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5162 GEN9_PGCTL_SSB_EU19_ACK |
5163 GEN9_PGCTL_SSB_EU210_ACK |
5164 GEN9_PGCTL_SSB_EU311_ACK;
5165
5166 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 5167 unsigned int ss_cnt = 0;
5168
5d39525a
JM		 5169 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5170 /* skip disabled slice */
5171 continue;
5172
5173 stat->slice_total++;
1c046bc1 5174
ef11bdb3 5175 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1c046bc1
JM		 5176 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5177
5d39525a
JM		 5178 for (ss = 0; ss < ss_max; ss++) {
5179 unsigned int eu_cnt;
5180
1c046bc1
JM		 5181 if (IS_BROXTON(dev) &&
5182 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5183 /* skip disabled subslice */
5184 continue;
5185
5186 if (IS_BROXTON(dev))
5187 ss_cnt++;
5188
5d39525a
JM		 5189 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5190 eu_mask[ss%2]);
5191 stat->eu_total += eu_cnt;
5192 stat->eu_per_subslice = max(stat->eu_per_subslice,
5193 eu_cnt);
5194 }
1c046bc1
JM		 5195
5196 stat->subslice_total += ss_cnt;
5197 stat->subslice_per_slice = max(stat->subslice_per_slice,
5198 ss_cnt);
5d39525a
JM		 5199 }
5200}
5201
91bedd34
ŁD		 5202static void broadwell_sseu_device_status(struct drm_device *dev,
5203 struct sseu_dev_status *stat)
5204{
5205 struct drm_i915_private *dev_priv = dev->dev_private;
5206 int s;
5207 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5208
5209 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5210
5211 if (stat->slice_total) {
5212 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5213 stat->subslice_total = stat->slice_total *
5214 stat->subslice_per_slice;
5215 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5216 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5217
5218 /* subtract fused off EU(s) from enabled slice(s) */
5219 for (s = 0; s < stat->slice_total; s++) {
5220 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5221
5222 stat->eu_total -= hweight8(subslice_7eu);
5223 }
5224 }
5225}
5226
3873218f
JM		 5227static int i915_sseu_status(struct seq_file *m, void *unused)
5228{
5229 struct drm_info_node *node = (struct drm_info_node *) m->private;
5230 struct drm_device *dev = node->minor->dev;
5d39525a 5231 struct sseu_dev_status stat;
3873218f 5232
91bedd34 5233 if (INTEL_INFO(dev)->gen < 8)
3873218f
JM		 5234 return -ENODEV;
5235
5236 seq_puts(m, "SSEU Device Info\n");
5237 seq_printf(m, " Available Slice Total: %u\n",
5238 INTEL_INFO(dev)->slice_total);
5239 seq_printf(m, " Available Subslice Total: %u\n",
5240 INTEL_INFO(dev)->subslice_total);
5241 seq_printf(m, " Available Subslice Per Slice: %u\n",
5242 INTEL_INFO(dev)->subslice_per_slice);
5243 seq_printf(m, " Available EU Total: %u\n",
5244 INTEL_INFO(dev)->eu_total);
5245 seq_printf(m, " Available EU Per Subslice: %u\n",
5246 INTEL_INFO(dev)->eu_per_subslice);
5247 seq_printf(m, " Has Slice Power Gating: %s\n",
5248 yesno(INTEL_INFO(dev)->has_slice_pg));
5249 seq_printf(m, " Has Subslice Power Gating: %s\n",
5250 yesno(INTEL_INFO(dev)->has_subslice_pg));
5251 seq_printf(m, " Has EU Power Gating: %s\n",
5252 yesno(INTEL_INFO(dev)->has_eu_pg));
5253
7f992aba 5254 seq_puts(m, "SSEU Device Status\n");
5d39525a 5255 memset(&stat, 0, sizeof(stat));
5575f03a 5256 if (IS_CHERRYVIEW(dev)) {
5d39525a 5257 cherryview_sseu_device_status(dev, &stat);
91bedd34
ŁD		 5258 } else if (IS_BROADWELL(dev)) {
5259 broadwell_sseu_device_status(dev, &stat);
1c046bc1 5260 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 5261 gen9_sseu_device_status(dev, &stat);
7f992aba 5262 }
5d39525a
JM		 5263 seq_printf(m, " Enabled Slice Total: %u\n",
5264 stat.slice_total);
5265 seq_printf(m, " Enabled Subslice Total: %u\n",
5266 stat.subslice_total);
5267 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5268 stat.subslice_per_slice);
5269 seq_printf(m, " Enabled EU Total: %u\n",
5270 stat.eu_total);
5271 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5272 stat.eu_per_subslice);
7f992aba 5273
3873218f
JM		 5274 return 0;
5275}
5276
6d794d42
BW		 5277static int i915_forcewake_open(struct inode *inode, struct file *file)
5278{
5279 struct drm_device *dev = inode->i_private;
5280 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 5281
075edca4 5282 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5283 return 0;
5284
6daccb0b 5285 intel_runtime_pm_get(dev_priv);
59bad947 5286 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5287
5288 return 0;
5289}
5290
c43b5634 5291static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5292{
5293 struct drm_device *dev = inode->i_private;
5294 struct drm_i915_private *dev_priv = dev->dev_private;
5295
075edca4 5296 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5297 return 0;
5298
59bad947 5299 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5300 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5301
5302 return 0;
5303}
5304
5305static const struct file_operations i915_forcewake_fops = {
5306 .owner = THIS_MODULE,
5307 .open = i915_forcewake_open,
5308 .release = i915_forcewake_release,
5309};
5310
5311static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5312{
5313 struct drm_device *dev = minor->dev;
5314 struct dentry *ent;
5315
5316 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5317 S_IRUSR,
6d794d42
BW		 5318 root, dev,
5319 &i915_forcewake_fops);
f3c5fe97
WY		 5320 if (!ent)
5321 return -ENOMEM;
6d794d42 5322
8eb57294 5323 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5324}
5325
6a9c308d
DV		 5326static int i915_debugfs_create(struct dentry *root,
5327 struct drm_minor *minor,
5328 const char *name,
5329 const struct file_operations *fops)
07b7ddd9
JB		 5330{
5331 struct drm_device *dev = minor->dev;
5332 struct dentry *ent;
5333
6a9c308d 5334 ent = debugfs_create_file(name,
07b7ddd9
JB		 5335 S_IRUGO | S_IWUSR,
5336 root, dev,
6a9c308d 5337 fops);
f3c5fe97
WY		 5338 if (!ent)
5339 return -ENOMEM;
07b7ddd9 5340
6a9c308d 5341 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5342}
5343
06c5bf8c 5344static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5345 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5346 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5347 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5348 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5349 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5350 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5351 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5352 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5353 {"i915_gem_request", i915_gem_request_info, 0},
5354 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5355 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5356 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5357 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5358 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5359 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5360 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5361 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5362 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5363 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5364 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5365 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5366 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5367 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5368 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5369 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5370 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5371 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5372 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5373 {"i915_sr_status", i915_sr_status, 0},
44834a67 5374 {"i915_opregion", i915_opregion, 0},
ada8f955 5375 {"i915_vbt", i915_vbt, 0},
37811fcc 5376 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5377 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5378 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5379 {"i915_execlists", i915_execlists, 0},
f65367b5 5380 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5381 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5382 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5383 {"i915_llc", i915_llc, 0},
e91fd8c6 5384 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5385 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5386 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5387 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5388 {"i915_power_domain_info", i915_power_domain_info, 0},
b7cec66d 5389 {"i915_dmc_info", i915_dmc_info, 0},
53f5e3ca 5390 {"i915_display_info", i915_display_info, 0},
e04934cf 5391 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5392 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5393 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5394 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5395 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5396 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5397 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5398 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5399};
27c202ad 5400#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5401
06c5bf8c 5402static const struct i915_debugfs_files {
34b9674c
DV		 5403 const char *name;
5404 const struct file_operations *fops;
5405} i915_debugfs_files[] = {
5406 {"i915_wedged", &i915_wedged_fops},
5407 {"i915_max_freq", &i915_max_freq_fops},
5408 {"i915_min_freq", &i915_min_freq_fops},
5409 {"i915_cache_sharing", &i915_cache_sharing_fops},
5410 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5411 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5412 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5413 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5414 {"i915_error_state", &i915_error_state_fops},
5415 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5416 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5417 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5418 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5419 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5420 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5421 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5422 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5423 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5424};
5425
07144428
DL		 5426void intel_display_crc_init(struct drm_device *dev)
5427{
5428 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5429 enum pipe pipe;
07144428 5430
055e393f 5431 for_each_pipe(dev_priv, pipe) {
b378360e 5432 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5433
d538bbdf
DL		 5434 pipe_crc->opened = false;
5435 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5436 init_waitqueue_head(&pipe_crc->wq);
5437 }
5438}
5439
27c202ad 5440int i915_debugfs_init(struct drm_minor *minor)
2017263e 5441{
34b9674c 5442 int ret, i;
f3cd474b 5443
6d794d42 5444 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5445 if (ret)
5446 return ret;
6a9c308d 5447
07144428
DL		 5448 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5449 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5450 if (ret)
5451 return ret;
5452 }
5453
34b9674c
DV		 5454 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5455 ret = i915_debugfs_create(minor->debugfs_root, minor,
5456 i915_debugfs_files[i].name,
5457 i915_debugfs_files[i].fops);
5458 if (ret)
5459 return ret;
5460 }
40633219 5461
27c202ad
BG		 5462 return drm_debugfs_create_files(i915_debugfs_list,
5463 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5464 minor->debugfs_root, minor);
5465}
5466
27c202ad 5467void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5468{
34b9674c
DV		 5469 int i;
5470
27c202ad
BG		 5471 drm_debugfs_remove_files(i915_debugfs_list,
5472 I915_DEBUGFS_ENTRIES, minor);
07144428 5473
6d794d42
BW		 5474 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5475 1, minor);
07144428 5476
e309a997 5477 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5478 struct drm_info_list *info_list =
5479 (struct drm_info_list *)&i915_pipe_crc_data[i];
5480
5481 drm_debugfs_remove_files(info_list, 1, minor);
5482 }
5483
34b9674c
DV		 5484 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5485 struct drm_info_list *info_list =
5486 (struct drm_info_list *) i915_debugfs_files[i].fops;
5487
5488 drm_debugfs_remove_files(info_list, 1, minor);
5489 }
2017263e 5490}
aa7471d2
JN		 5491
5492struct dpcd_block {
5493 /* DPCD dump start address. */
5494 unsigned int offset;
5495 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5496 unsigned int end;
5497 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5498 size_t size;
5499 /* Only valid for eDP. */
5500 bool edp;
5501};
5502
5503static const struct dpcd_block i915_dpcd_debug[] = {
5504 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5505 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5506 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5507 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5508 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5509 { .offset = DP_SET_POWER },
5510 { .offset = DP_EDP_DPCD_REV },
5511 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5512 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5513 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5514};
5515
5516static int i915_dpcd_show(struct seq_file *m, void *data)
5517{
5518 struct drm_connector *connector = m->private;
5519 struct intel_dp *intel_dp =
5520 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5521 uint8_t buf[16];
5522 ssize_t err;
5523 int i;
5524
5c1a8875
MK		 5525 if (connector->status != connector_status_connected)
5526 return -ENODEV;
5527
aa7471d2
JN		 5528 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5529 const struct dpcd_block *b = &i915_dpcd_debug[i];
5530 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5531
5532 if (b->edp &&
5533 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5534 continue;
5535
5536 /* low tech for now */
5537 if (WARN_ON(size > sizeof(buf)))
5538 continue;
5539
5540 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5541 if (err <= 0) {
5542 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5543 size, b->offset, err);
5544 continue;
5545 }
5546
5547 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5548 }
aa7471d2
JN		 5549
5550 return 0;
5551}
5552
5553static int i915_dpcd_open(struct inode *inode, struct file *file)
5554{
5555 return single_open(file, i915_dpcd_show, inode->i_private);
5556}
5557
5558static const struct file_operations i915_dpcd_fops = {
5559 .owner = THIS_MODULE,
5560 .open = i915_dpcd_open,
5561 .read = seq_read,
5562 .llseek = seq_lseek,
5563 .release = single_release,
5564};
5565
5566/**
5567 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5568 * @connector: pointer to a registered drm_connector
5569 *
5570 * Cleanup will be done by drm_connector_unregister() through a call to
5571 * drm_debugfs_connector_remove().
5572 *
5573 * Returns 0 on success, negative error codes on error.
5574 */
5575int i915_debugfs_connector_add(struct drm_connector *connector)
5576{
5577 struct dentry *root = connector->debugfs_entry;
5578
5579 /* The connector must have been registered beforehands. */
5580 if (!root)
5581 return -ENODEV;
5582
5583 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5584 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5585 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5586 &i915_dpcd_fops);
5587
5588 return 0;
5589}
Linux kernel - Deliverables
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