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drm/i915: Add a FIXME about drrs/psr interactions
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
d7f46fc4 101 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
d7f46fc4
BW		 126 int pin_count = 0;
127
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
84734a04 139 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
c1ad11fc
CW		 160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
69dc4987
CW		 171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
d5a81ef1
DV		 173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 175}
176
273497e5 177static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 178{
ea0c76f8 179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 185{
9f25d007 186 struct drm_info_node *node = m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
9f25d007 244 struct drm_info_node *node = m->private;
6d2b8885
CW		 245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6 303struct file_stats {
6313c204 304 struct drm_i915_file_private *file_priv;
2db8e9d6 305 int count;
c67a17e9
CW		 306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
2db8e9d6
CW		 309};
310
311static int per_file_stats(int id, void *ptr, void *data)
312{
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
6313c204 315 struct i915_vma *vma;
2db8e9d6
CW		 316
317 stats->count++;
318 stats->total += obj->base.size;
319
c67a17e9
CW		 320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
6313c204
CW		 323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
336 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
337 continue;
338
339 if (obj->ring) /* XXX per-vma statistic */
340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
2db8e9d6 346 } else {
6313c204
CW		 347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
349 if (obj->ring)
350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
2db8e9d6
CW		 355 }
356
6313c204
CW		 357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
2db8e9d6
CW		 360 return 0;
361}
362
ca191b13
BW		 363#define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
366 ++count; \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
369 ++mappable_count; \
370 } \
371 } \
372} while (0)
373
374static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 375{
9f25d007 376 struct drm_info_node *node = m->private;
73aa808f
CW		 377 struct drm_device *dev = node->minor->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 379 u32 count, mappable_count, purgeable_count;
380 size_t size, mappable_size, purgeable_size;
6299f992 381 struct drm_i915_gem_object *obj;
5cef07e1 382 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 383 struct drm_file *file;
ca191b13 384 struct i915_vma *vma;
73aa808f
CW		 385 int ret;
386
387 ret = mutex_lock_interruptible(&dev->struct_mutex);
388 if (ret)
389 return ret;
390
6299f992
CW		 391 seq_printf(m, "%u objects, %zu bytes\n",
392 dev_priv->mm.object_count,
393 dev_priv->mm.object_memory);
394
395 size = count = mappable_size = mappable_count = 0;
35c20a60 396 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 397 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count, mappable_count, size, mappable_size);
399
400 size = count = mappable_size = mappable_count = 0;
ca191b13 401 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 402 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count, mappable_count, size, mappable_size);
404
6299f992 405 size = count = mappable_size = mappable_count = 0;
ca191b13 406 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 407 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count, mappable_count, size, mappable_size);
409
b7abb714 410 size = count = purgeable_size = purgeable_count = 0;
35c20a60 411 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 412 size += obj->base.size, ++count;
b7abb714
CW		 413 if (obj->madv == I915_MADV_DONTNEED)
414 purgeable_size += obj->base.size, ++purgeable_count;
415 }
6c085a72
CW		 416 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
417
6299f992 418 size = count = mappable_size = mappable_count = 0;
35c20a60 419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 420 if (obj->fault_mappable) {
f343c5f6 421 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 422 ++count;
423 }
424 if (obj->pin_mappable) {
f343c5f6 425 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 426 ++mappable_count;
427 }
b7abb714
CW		 428 if (obj->madv == I915_MADV_DONTNEED) {
429 purgeable_size += obj->base.size;
430 ++purgeable_count;
431 }
6299f992 432 }
b7abb714
CW		 433 seq_printf(m, "%u purgeable objects, %zu bytes\n",
434 purgeable_count, purgeable_size);
6299f992
CW		 435 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count, mappable_size);
437 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
438 count, size);
439
93d18799 440 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 441 dev_priv->gtt.base.total,
442 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 443
267f0c90 444 seq_putc(m, '\n');
2db8e9d6
CW		 445 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
446 struct file_stats stats;
3ec2f427 447 struct task_struct *task;
2db8e9d6
CW		 448
449 memset(&stats, 0, sizeof(stats));
6313c204 450 stats.file_priv = file->driver_priv;
5b5ffff0 451 spin_lock(&file->table_lock);
2db8e9d6 452 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 453 spin_unlock(&file->table_lock);
3ec2f427
TH		 454 /*
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
459 */
460 rcu_read_lock();
461 task = pid_task(file->pid, PIDTYPE_PID);
c67a17e9 462 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
3ec2f427 463 task ? task->comm : "<unknown>",
2db8e9d6
CW		 464 stats.count,
465 stats.total,
466 stats.active,
467 stats.inactive,
6313c204 468 stats.global,
c67a17e9 469 stats.shared,
2db8e9d6 470 stats.unbound);
3ec2f427 471 rcu_read_unlock();
2db8e9d6
CW		 472 }
473
73aa808f
CW		 474 mutex_unlock(&dev->struct_mutex);
475
476 return 0;
477}
478
aee56cff 479static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 480{
9f25d007 481 struct drm_info_node *node = m->private;
08c18323 482 struct drm_device *dev = node->minor->dev;
1b50247a 483 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_i915_gem_object *obj;
486 size_t total_obj_size, total_gtt_size;
487 int count, ret;
488
489 ret = mutex_lock_interruptible(&dev->struct_mutex);
490 if (ret)
491 return ret;
492
493 total_obj_size = total_gtt_size = count = 0;
35c20a60 494 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 495 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 496 continue;
497
267f0c90 498 seq_puts(m, " ");
08c18323 499 describe_obj(m, obj);
267f0c90 500 seq_putc(m, '\n');
08c18323 501 total_obj_size += obj->base.size;
f343c5f6 502 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 503 count++;
504 }
505
506 mutex_unlock(&dev->struct_mutex);
507
508 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count, total_obj_size, total_gtt_size);
510
511 return 0;
512}
513
4e5359cd
SF		 514static int i915_gem_pageflip_info(struct seq_file *m, void *data)
515{
9f25d007 516 struct drm_info_node *node = m->private;
4e5359cd
SF		 517 struct drm_device *dev = node->minor->dev;
518 unsigned long flags;
519 struct intel_crtc *crtc;
8a270ebf
DV		 520 int ret;
521
522 ret = mutex_lock_interruptible(&dev->struct_mutex);
523 if (ret)
524 return ret;
4e5359cd 525
d3fcc808 526 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 527 const char pipe = pipe_name(crtc->pipe);
528 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 529 struct intel_unpin_work *work;
530
531 spin_lock_irqsave(&dev->event_lock, flags);
532 work = crtc->unpin_work;
533 if (work == NULL) {
9db4a9c7 534 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 535 pipe, plane);
536 } else {
e7d841ca 537 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 538 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 539 pipe, plane);
540 } else {
9db4a9c7 541 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 542 pipe, plane);
543 }
544 if (work->enable_stall_check)
267f0c90 545 seq_puts(m, "Stall check enabled, ");
4e5359cd 546 else
267f0c90 547 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 548 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 549
550 if (work->old_fb_obj) {
05394f39
CW		 551 struct drm_i915_gem_object *obj = work->old_fb_obj;
552 if (obj)
f343c5f6
BW		 553 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
554 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 555 }
556 if (work->pending_flip_obj) {
05394f39
CW		 557 struct drm_i915_gem_object *obj = work->pending_flip_obj;
558 if (obj)
f343c5f6
BW		 559 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
560 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 561 }
562 }
563 spin_unlock_irqrestore(&dev->event_lock, flags);
564 }
565
8a270ebf
DV		 566 mutex_unlock(&dev->struct_mutex);
567
4e5359cd
SF		 568 return 0;
569}
570
2017263e
BG		 571static int i915_gem_request_info(struct seq_file *m, void *data)
572{
9f25d007 573 struct drm_info_node *node = m->private;
2017263e 574 struct drm_device *dev = node->minor->dev;
e277a1f8 575 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 576 struct intel_engine_cs *ring;
2017263e 577 struct drm_i915_gem_request *gem_request;
a2c7f6fd 578 int ret, count, i;
de227ef0
CW		 579
580 ret = mutex_lock_interruptible(&dev->struct_mutex);
581 if (ret)
582 return ret;
2017263e 583
c2c347a9 584 count = 0;
a2c7f6fd
CW		 585 for_each_ring(ring, dev_priv, i) {
586 if (list_empty(&ring->request_list))
587 continue;
588
589 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 590 list_for_each_entry(gem_request,
a2c7f6fd 591 &ring->request_list,
c2c347a9
CW		 592 list) {
593 seq_printf(m, " %d @ %d\n",
594 gem_request->seqno,
595 (int) (jiffies - gem_request->emitted_jiffies));
596 }
597 count++;
2017263e 598 }
de227ef0
CW		 599 mutex_unlock(&dev->struct_mutex);
600
c2c347a9 601 if (count == 0)
267f0c90 602 seq_puts(m, "No requests\n");
c2c347a9 603
2017263e
BG		 604 return 0;
605}
606
b2223497 607static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 608 struct intel_engine_cs *ring)
b2223497
CW		 609{
610 if (ring->get_seqno) {
43a7b924 611 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 612 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 613 }
614}
615
2017263e
BG		 616static int i915_gem_seqno_info(struct seq_file *m, void *data)
617{
9f25d007 618 struct drm_info_node *node = m->private;
2017263e 619 struct drm_device *dev = node->minor->dev;
e277a1f8 620 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 621 struct intel_engine_cs *ring;
1ec14ad3 622 int ret, i;
de227ef0
CW		 623
624 ret = mutex_lock_interruptible(&dev->struct_mutex);
625 if (ret)
626 return ret;
c8c8fb33 627 intel_runtime_pm_get(dev_priv);
2017263e 628
a2c7f6fd
CW		 629 for_each_ring(ring, dev_priv, i)
630 i915_ring_seqno_info(m, ring);
de227ef0 631
c8c8fb33 632 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 633 mutex_unlock(&dev->struct_mutex);
634
2017263e
BG		 635 return 0;
636}
637
638
639static int i915_interrupt_info(struct seq_file *m, void *data)
640{
9f25d007 641 struct drm_info_node *node = m->private;
2017263e 642 struct drm_device *dev = node->minor->dev;
e277a1f8 643 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 644 struct intel_engine_cs *ring;
9db4a9c7 645 int ret, i, pipe;
de227ef0
CW		 646
647 ret = mutex_lock_interruptible(&dev->struct_mutex);
648 if (ret)
649 return ret;
c8c8fb33 650 intel_runtime_pm_get(dev_priv);
2017263e 651
74e1ca8c
VS		 652 if (IS_CHERRYVIEW(dev)) {
653 int i;
654 seq_printf(m, "Master Interrupt Control:\t%08x\n",
655 I915_READ(GEN8_MASTER_IRQ));
656
657 seq_printf(m, "Display IER:\t%08x\n",
658 I915_READ(VLV_IER));
659 seq_printf(m, "Display IIR:\t%08x\n",
660 I915_READ(VLV_IIR));
661 seq_printf(m, "Display IIR_RW:\t%08x\n",
662 I915_READ(VLV_IIR_RW));
663 seq_printf(m, "Display IMR:\t%08x\n",
664 I915_READ(VLV_IMR));
665 for_each_pipe(pipe)
666 seq_printf(m, "Pipe %c stat:\t%08x\n",
667 pipe_name(pipe),
668 I915_READ(PIPESTAT(pipe)));
669
670 seq_printf(m, "Port hotplug:\t%08x\n",
671 I915_READ(PORT_HOTPLUG_EN));
672 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
673 I915_READ(VLV_DPFLIPSTAT));
674 seq_printf(m, "DPINVGTT:\t%08x\n",
675 I915_READ(DPINVGTT));
676
677 for (i = 0; i < 4; i++) {
678 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
679 i, I915_READ(GEN8_GT_IMR(i)));
680 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
681 i, I915_READ(GEN8_GT_IIR(i)));
682 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
683 i, I915_READ(GEN8_GT_IER(i)));
684 }
685
686 seq_printf(m, "PCU interrupt mask:\t%08x\n",
687 I915_READ(GEN8_PCU_IMR));
688 seq_printf(m, "PCU interrupt identity:\t%08x\n",
689 I915_READ(GEN8_PCU_IIR));
690 seq_printf(m, "PCU interrupt enable:\t%08x\n",
691 I915_READ(GEN8_PCU_IER));
692 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 693 seq_printf(m, "Master Interrupt Control:\t%08x\n",
694 I915_READ(GEN8_MASTER_IRQ));
695
696 for (i = 0; i < 4; i++) {
697 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
698 i, I915_READ(GEN8_GT_IMR(i)));
699 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
700 i, I915_READ(GEN8_GT_IIR(i)));
701 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
702 i, I915_READ(GEN8_GT_IER(i)));
703 }
704
07d27e20 705 for_each_pipe(pipe) {
a123f157 706 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 707 pipe_name(pipe),
708 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 709 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 710 pipe_name(pipe),
711 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 712 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 713 pipe_name(pipe),
714 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 715 }
716
717 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
718 I915_READ(GEN8_DE_PORT_IMR));
719 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
720 I915_READ(GEN8_DE_PORT_IIR));
721 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
722 I915_READ(GEN8_DE_PORT_IER));
723
724 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
725 I915_READ(GEN8_DE_MISC_IMR));
726 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
727 I915_READ(GEN8_DE_MISC_IIR));
728 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
729 I915_READ(GEN8_DE_MISC_IER));
730
731 seq_printf(m, "PCU interrupt mask:\t%08x\n",
732 I915_READ(GEN8_PCU_IMR));
733 seq_printf(m, "PCU interrupt identity:\t%08x\n",
734 I915_READ(GEN8_PCU_IIR));
735 seq_printf(m, "PCU interrupt enable:\t%08x\n",
736 I915_READ(GEN8_PCU_IER));
737 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 738 seq_printf(m, "Display IER:\t%08x\n",
739 I915_READ(VLV_IER));
740 seq_printf(m, "Display IIR:\t%08x\n",
741 I915_READ(VLV_IIR));
742 seq_printf(m, "Display IIR_RW:\t%08x\n",
743 I915_READ(VLV_IIR_RW));
744 seq_printf(m, "Display IMR:\t%08x\n",
745 I915_READ(VLV_IMR));
746 for_each_pipe(pipe)
747 seq_printf(m, "Pipe %c stat:\t%08x\n",
748 pipe_name(pipe),
749 I915_READ(PIPESTAT(pipe)));
750
751 seq_printf(m, "Master IER:\t%08x\n",
752 I915_READ(VLV_MASTER_IER));
753
754 seq_printf(m, "Render IER:\t%08x\n",
755 I915_READ(GTIER));
756 seq_printf(m, "Render IIR:\t%08x\n",
757 I915_READ(GTIIR));
758 seq_printf(m, "Render IMR:\t%08x\n",
759 I915_READ(GTIMR));
760
761 seq_printf(m, "PM IER:\t\t%08x\n",
762 I915_READ(GEN6_PMIER));
763 seq_printf(m, "PM IIR:\t\t%08x\n",
764 I915_READ(GEN6_PMIIR));
765 seq_printf(m, "PM IMR:\t\t%08x\n",
766 I915_READ(GEN6_PMIMR));
767
768 seq_printf(m, "Port hotplug:\t%08x\n",
769 I915_READ(PORT_HOTPLUG_EN));
770 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
771 I915_READ(VLV_DPFLIPSTAT));
772 seq_printf(m, "DPINVGTT:\t%08x\n",
773 I915_READ(DPINVGTT));
774
775 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 776 seq_printf(m, "Interrupt enable: %08x\n",
777 I915_READ(IER));
778 seq_printf(m, "Interrupt identity: %08x\n",
779 I915_READ(IIR));
780 seq_printf(m, "Interrupt mask: %08x\n",
781 I915_READ(IMR));
9db4a9c7
JB		 782 for_each_pipe(pipe)
783 seq_printf(m, "Pipe %c stat: %08x\n",
784 pipe_name(pipe),
785 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 786 } else {
787 seq_printf(m, "North Display Interrupt enable: %08x\n",
788 I915_READ(DEIER));
789 seq_printf(m, "North Display Interrupt identity: %08x\n",
790 I915_READ(DEIIR));
791 seq_printf(m, "North Display Interrupt mask: %08x\n",
792 I915_READ(DEIMR));
793 seq_printf(m, "South Display Interrupt enable: %08x\n",
794 I915_READ(SDEIER));
795 seq_printf(m, "South Display Interrupt identity: %08x\n",
796 I915_READ(SDEIIR));
797 seq_printf(m, "South Display Interrupt mask: %08x\n",
798 I915_READ(SDEIMR));
799 seq_printf(m, "Graphics Interrupt enable: %08x\n",
800 I915_READ(GTIER));
801 seq_printf(m, "Graphics Interrupt identity: %08x\n",
802 I915_READ(GTIIR));
803 seq_printf(m, "Graphics Interrupt mask: %08x\n",
804 I915_READ(GTIMR));
805 }
a2c7f6fd 806 for_each_ring(ring, dev_priv, i) {
a123f157 807 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 808 seq_printf(m,
809 "Graphics Interrupt mask (%s): %08x\n",
810 ring->name, I915_READ_IMR(ring));
9862e600 811 }
a2c7f6fd 812 i915_ring_seqno_info(m, ring);
9862e600 813 }
c8c8fb33 814 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 815 mutex_unlock(&dev->struct_mutex);
816
2017263e
BG		 817 return 0;
818}
819
a6172a80
CW		 820static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
821{
9f25d007 822 struct drm_info_node *node = m->private;
a6172a80 823 struct drm_device *dev = node->minor->dev;
e277a1f8 824 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 825 int i, ret;
826
827 ret = mutex_lock_interruptible(&dev->struct_mutex);
828 if (ret)
829 return ret;
a6172a80
CW		 830
831 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
832 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
833 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 834 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 835
6c085a72
CW		 836 seq_printf(m, "Fence %d, pin count = %d, object = ",
837 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 838 if (obj == NULL)
267f0c90 839 seq_puts(m, "unused");
c2c347a9 840 else
05394f39 841 describe_obj(m, obj);
267f0c90 842 seq_putc(m, '\n');
a6172a80
CW		 843 }
844
05394f39 845 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 846 return 0;
847}
848
2017263e
BG		 849static int i915_hws_info(struct seq_file *m, void *data)
850{
9f25d007 851 struct drm_info_node *node = m->private;
2017263e 852 struct drm_device *dev = node->minor->dev;
e277a1f8 853 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 854 struct intel_engine_cs *ring;
1a240d4d 855 const u32 *hws;
4066c0ae
CW		 856 int i;
857
1ec14ad3 858 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 859 hws = ring->status_page.page_addr;
2017263e
BG		 860 if (hws == NULL)
861 return 0;
862
863 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
864 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
865 i * 4,
866 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
867 }
868 return 0;
869}
870
d5442303
DV		 871static ssize_t
872i915_error_state_write(struct file *filp,
873 const char __user *ubuf,
874 size_t cnt,
875 loff_t *ppos)
876{
edc3d884 877 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 878 struct drm_device *dev = error_priv->dev;
22bcfc6a 879 int ret;
d5442303
DV		 880
881 DRM_DEBUG_DRIVER("Resetting error state\n");
882
22bcfc6a
DV		 883 ret = mutex_lock_interruptible(&dev->struct_mutex);
884 if (ret)
885 return ret;
886
d5442303
DV		 887 i915_destroy_error_state(dev);
888 mutex_unlock(&dev->struct_mutex);
889
890 return cnt;
891}
892
893static int i915_error_state_open(struct inode *inode, struct file *file)
894{
895 struct drm_device *dev = inode->i_private;
d5442303 896 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 897
898 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
899 if (!error_priv)
900 return -ENOMEM;
901
902 error_priv->dev = dev;
903
95d5bfb3 904 i915_error_state_get(dev, error_priv);
d5442303 905
edc3d884
MK		 906 file->private_data = error_priv;
907
908 return 0;
d5442303
DV		 909}
910
911static int i915_error_state_release(struct inode *inode, struct file *file)
912{
edc3d884 913 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 914
95d5bfb3 915 i915_error_state_put(error_priv);
d5442303
DV		 916 kfree(error_priv);
917
edc3d884
MK		 918 return 0;
919}
920
4dc955f7
MK		 921static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
922 size_t count, loff_t *pos)
923{
924 struct i915_error_state_file_priv *error_priv = file->private_data;
925 struct drm_i915_error_state_buf error_str;
926 loff_t tmp_pos = 0;
927 ssize_t ret_count = 0;
928 int ret;
929
930 ret = i915_error_state_buf_init(&error_str, count, *pos);
931 if (ret)
932 return ret;
edc3d884 933
fc16b48b 934 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 935 if (ret)
936 goto out;
937
edc3d884
MK		 938 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
939 error_str.buf,
940 error_str.bytes);
941
942 if (ret_count < 0)
943 ret = ret_count;
944 else
945 *pos = error_str.start + ret_count;
946out:
4dc955f7 947 i915_error_state_buf_release(&error_str);
edc3d884 948 return ret ?: ret_count;
d5442303
DV		 949}
950
951static const struct file_operations i915_error_state_fops = {
952 .owner = THIS_MODULE,
953 .open = i915_error_state_open,
edc3d884 954 .read = i915_error_state_read,
d5442303
DV		 955 .write = i915_error_state_write,
956 .llseek = default_llseek,
957 .release = i915_error_state_release,
958};
959
647416f9
KC		 960static int
961i915_next_seqno_get(void *data, u64 *val)
40633219 962{
647416f9 963 struct drm_device *dev = data;
e277a1f8 964 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 965 int ret;
966
967 ret = mutex_lock_interruptible(&dev->struct_mutex);
968 if (ret)
969 return ret;
970
647416f9 971 *val = dev_priv->next_seqno;
40633219
MK		 972 mutex_unlock(&dev->struct_mutex);
973
647416f9 974 return 0;
40633219
MK		 975}
976
647416f9
KC		 977static int
978i915_next_seqno_set(void *data, u64 val)
979{
980 struct drm_device *dev = data;
40633219
MK		 981 int ret;
982
40633219
MK		 983 ret = mutex_lock_interruptible(&dev->struct_mutex);
984 if (ret)
985 return ret;
986
e94fbaa8 987 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 988 mutex_unlock(&dev->struct_mutex);
989
647416f9 990 return ret;
40633219
MK		 991}
992
647416f9
KC		 993DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
994 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 995 "0x%llx\n");
40633219 996
adb4bd12 997static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 998{
9f25d007 999 struct drm_info_node *node = m->private;
f97108d1 1000 struct drm_device *dev = node->minor->dev;
e277a1f8 1001 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1002 int ret = 0;
1003
1004 intel_runtime_pm_get(dev_priv);
3b8d8d91 1005
5c9669ce
TR		 1006 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1007
3b8d8d91
JB		 1008 if (IS_GEN5(dev)) {
1009 u16 rgvswctl = I915_READ16(MEMSWCTL);
1010 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1011
1012 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1013 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1014 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1015 MEMSTAT_VID_SHIFT);
1016 seq_printf(m, "Current P-state: %d\n",
1017 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1018 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1019 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1020 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1021 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1022 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1023 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1024 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1025 u32 rpupei, rpcurup, rpprevup;
1026 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 1027 int max_freq;
1028
1029 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1030 ret = mutex_lock_interruptible(&dev->struct_mutex);
1031 if (ret)
c8c8fb33 1032 goto out;
d1ebd816 1033
c8d9a590 1034 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1035
8e8c06cd
CW		 1036 reqf = I915_READ(GEN6_RPNSWREQ);
1037 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1038 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1039 reqf >>= 24;
1040 else
1041 reqf >>= 25;
1042 reqf *= GT_FREQUENCY_MULTIPLIER;
1043
0d8f9491
CW		 1044 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1045 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1046 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1047
ccab5c82
JB		 1048 rpstat = I915_READ(GEN6_RPSTAT1);
1049 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1050 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1051 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1052 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1053 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1054 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1055 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1056 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1057 else
1058 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1059 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1060
c8d9a590 1061 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1062 mutex_unlock(&dev->struct_mutex);
1063
0d8f9491
CW		 1064 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1065 I915_READ(GEN6_PMIER),
1066 I915_READ(GEN6_PMIMR),
1067 I915_READ(GEN6_PMISR),
1068 I915_READ(GEN6_PMIIR),
1069 I915_READ(GEN6_PMINTRMSK));
3b8d8d91 1070 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1071 seq_printf(m, "Render p-state ratio: %d\n",
1072 (gt_perf_status & 0xff00) >> 8);
1073 seq_printf(m, "Render p-state VID: %d\n",
1074 gt_perf_status & 0xff);
1075 seq_printf(m, "Render p-state limit: %d\n",
1076 rp_state_limits & 0xff);
0d8f9491
CW		 1077 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1078 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1079 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1080 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1081 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1082 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1083 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1084 GEN6_CURICONT_MASK);
1085 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1086 GEN6_CURBSYTAVG_MASK);
1087 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1088 GEN6_CURBSYTAVG_MASK);
1089 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1090 GEN6_CURIAVG_MASK);
1091 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1092 GEN6_CURBSYTAVG_MASK);
1093 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1094 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1095
1096 max_freq = (rp_state_cap & 0xff0000) >> 16;
1097 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1098 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1099
1100 max_freq = (rp_state_cap & 0xff00) >> 8;
1101 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1102 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1103
1104 max_freq = rp_state_cap & 0xff;
1105 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1106 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1107
1108 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1109 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84 1110 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1111 u32 freq_sts;
0a073b84 1112
259bd5d4 1113 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1114 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1115 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1116 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1117
0a073b84 1118 seq_printf(m, "max GPU freq: %d MHz\n",
03af2045 1119 dev_priv->rps.max_freq);
0a073b84 1120
0a073b84 1121 seq_printf(m, "min GPU freq: %d MHz\n",
03af2045
VS		 1122 dev_priv->rps.min_freq);
1123
1124 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
1125 dev_priv->rps.efficient_freq);
0a073b84
JB		 1126
1127 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1128 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1129 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1130 } else {
267f0c90 1131 seq_puts(m, "no P-state info available\n");
3b8d8d91 1132 }
f97108d1 1133
c8c8fb33
PZ		 1134out:
1135 intel_runtime_pm_put(dev_priv);
1136 return ret;
f97108d1
JB		 1137}
1138
4d85529d 1139static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1140{
9f25d007 1141 struct drm_info_node *node = m->private;
f97108d1 1142 struct drm_device *dev = node->minor->dev;
e277a1f8 1143 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1144 u32 rgvmodectl, rstdbyctl;
1145 u16 crstandvid;
1146 int ret;
1147
1148 ret = mutex_lock_interruptible(&dev->struct_mutex);
1149 if (ret)
1150 return ret;
c8c8fb33 1151 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1152
1153 rgvmodectl = I915_READ(MEMMODECTL);
1154 rstdbyctl = I915_READ(RSTDBYCTL);
1155 crstandvid = I915_READ16(CRSTANDVID);
1156
c8c8fb33 1157 intel_runtime_pm_put(dev_priv);
616fdb5a 1158 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1159
1160 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1161 "yes" : "no");
1162 seq_printf(m, "Boost freq: %d\n",
1163 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1164 MEMMODE_BOOST_FREQ_SHIFT);
1165 seq_printf(m, "HW control enabled: %s\n",
1166 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1167 seq_printf(m, "SW control enabled: %s\n",
1168 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1169 seq_printf(m, "Gated voltage change: %s\n",
1170 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1171 seq_printf(m, "Starting frequency: P%d\n",
1172 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1173 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1174 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1175 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1176 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1177 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1178 seq_printf(m, "Render standby enabled: %s\n",
1179 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1180 seq_puts(m, "Current RS state: ");
88271da3
JB		 1181 switch (rstdbyctl & RSX_STATUS_MASK) {
1182 case RSX_STATUS_ON:
267f0c90 1183 seq_puts(m, "on\n");
88271da3
JB		 1184 break;
1185 case RSX_STATUS_RC1:
267f0c90 1186 seq_puts(m, "RC1\n");
88271da3
JB		 1187 break;
1188 case RSX_STATUS_RC1E:
267f0c90 1189 seq_puts(m, "RC1E\n");
88271da3
JB		 1190 break;
1191 case RSX_STATUS_RS1:
267f0c90 1192 seq_puts(m, "RS1\n");
88271da3
JB		 1193 break;
1194 case RSX_STATUS_RS2:
267f0c90 1195 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1196 break;
1197 case RSX_STATUS_RS3:
267f0c90 1198 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1199 break;
1200 default:
267f0c90 1201 seq_puts(m, "unknown\n");
88271da3
JB		 1202 break;
1203 }
f97108d1
JB		 1204
1205 return 0;
1206}
1207
669ab5aa
D		 1208static int vlv_drpc_info(struct seq_file *m)
1209{
1210
9f25d007 1211 struct drm_info_node *node = m->private;
669ab5aa
D		 1212 struct drm_device *dev = node->minor->dev;
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214 u32 rpmodectl1, rcctl1;
1215 unsigned fw_rendercount = 0, fw_mediacount = 0;
1216
d46c0517
ID		 1217 intel_runtime_pm_get(dev_priv);
1218
669ab5aa
D		 1219 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1220 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1221
d46c0517
ID		 1222 intel_runtime_pm_put(dev_priv);
1223
669ab5aa
D		 1224 seq_printf(m, "Video Turbo Mode: %s\n",
1225 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1226 seq_printf(m, "Turbo enabled: %s\n",
1227 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1228 seq_printf(m, "HW control enabled: %s\n",
1229 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1230 seq_printf(m, "SW control enabled: %s\n",
1231 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1232 GEN6_RP_MEDIA_SW_MODE));
1233 seq_printf(m, "RC6 Enabled: %s\n",
1234 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1235 GEN6_RC_CTL_EI_MODE(1))));
1236 seq_printf(m, "Render Power Well: %s\n",
1237 (I915_READ(VLV_GTLC_PW_STATUS) &
1238 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1239 seq_printf(m, "Media Power Well: %s\n",
1240 (I915_READ(VLV_GTLC_PW_STATUS) &
1241 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1242
9cc19be5
ID		 1243 seq_printf(m, "Render RC6 residency since boot: %u\n",
1244 I915_READ(VLV_GT_RENDER_RC6));
1245 seq_printf(m, "Media RC6 residency since boot: %u\n",
1246 I915_READ(VLV_GT_MEDIA_RC6));
1247
669ab5aa
D		 1248 spin_lock_irq(&dev_priv->uncore.lock);
1249 fw_rendercount = dev_priv->uncore.fw_rendercount;
1250 fw_mediacount = dev_priv->uncore.fw_mediacount;
1251 spin_unlock_irq(&dev_priv->uncore.lock);
1252
1253 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1254 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1255
1256
1257 return 0;
1258}
1259
1260
4d85529d
BW		 1261static int gen6_drpc_info(struct seq_file *m)
1262{
1263
9f25d007 1264 struct drm_info_node *node = m->private;
4d85529d
BW		 1265 struct drm_device *dev = node->minor->dev;
1266 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1267 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1268 unsigned forcewake_count;
aee56cff 1269 int count = 0, ret;
4d85529d
BW		 1270
1271 ret = mutex_lock_interruptible(&dev->struct_mutex);
1272 if (ret)
1273 return ret;
c8c8fb33 1274 intel_runtime_pm_get(dev_priv);
4d85529d 1275
907b28c5
CW		 1276 spin_lock_irq(&dev_priv->uncore.lock);
1277 forcewake_count = dev_priv->uncore.forcewake_count;
1278 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1279
1280 if (forcewake_count) {
267f0c90
DL		 1281 seq_puts(m, "RC information inaccurate because somebody "
1282 "holds a forcewake reference \n");
4d85529d
BW		 1283 } else {
1284 /* NB: we cannot use forcewake, else we read the wrong values */
1285 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1286 udelay(10);
1287 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1288 }
1289
1290 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1291 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1292
1293 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1294 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1295 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1296 mutex_lock(&dev_priv->rps.hw_lock);
1297 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1298 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1299
c8c8fb33
PZ		 1300 intel_runtime_pm_put(dev_priv);
1301
4d85529d
BW		 1302 seq_printf(m, "Video Turbo Mode: %s\n",
1303 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1304 seq_printf(m, "HW control enabled: %s\n",
1305 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1306 seq_printf(m, "SW control enabled: %s\n",
1307 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1308 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1309 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1310 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1311 seq_printf(m, "RC6 Enabled: %s\n",
1312 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1313 seq_printf(m, "Deep RC6 Enabled: %s\n",
1314 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1315 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1316 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1317 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1318 switch (gt_core_status & GEN6_RCn_MASK) {
1319 case GEN6_RC0:
1320 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1321 seq_puts(m, "Core Power Down\n");
4d85529d 1322 else
267f0c90 1323 seq_puts(m, "on\n");
4d85529d
BW		 1324 break;
1325 case GEN6_RC3:
267f0c90 1326 seq_puts(m, "RC3\n");
4d85529d
BW		 1327 break;
1328 case GEN6_RC6:
267f0c90 1329 seq_puts(m, "RC6\n");
4d85529d
BW		 1330 break;
1331 case GEN6_RC7:
267f0c90 1332 seq_puts(m, "RC7\n");
4d85529d
BW		 1333 break;
1334 default:
267f0c90 1335 seq_puts(m, "Unknown\n");
4d85529d
BW		 1336 break;
1337 }
1338
1339 seq_printf(m, "Core Power Down: %s\n",
1340 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1341
1342 /* Not exactly sure what this is */
1343 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1344 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1345 seq_printf(m, "RC6 residency since boot: %u\n",
1346 I915_READ(GEN6_GT_GFX_RC6));
1347 seq_printf(m, "RC6+ residency since boot: %u\n",
1348 I915_READ(GEN6_GT_GFX_RC6p));
1349 seq_printf(m, "RC6++ residency since boot: %u\n",
1350 I915_READ(GEN6_GT_GFX_RC6pp));
1351
ecd8faea
BW		 1352 seq_printf(m, "RC6 voltage: %dmV\n",
1353 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1354 seq_printf(m, "RC6+ voltage: %dmV\n",
1355 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1356 seq_printf(m, "RC6++ voltage: %dmV\n",
1357 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1358 return 0;
1359}
1360
1361static int i915_drpc_info(struct seq_file *m, void *unused)
1362{
9f25d007 1363 struct drm_info_node *node = m->private;
4d85529d
BW		 1364 struct drm_device *dev = node->minor->dev;
1365
669ab5aa
D		 1366 if (IS_VALLEYVIEW(dev))
1367 return vlv_drpc_info(m);
1368 else if (IS_GEN6(dev) || IS_GEN7(dev))
4d85529d
BW		 1369 return gen6_drpc_info(m);
1370 else
1371 return ironlake_drpc_info(m);
1372}
1373
b5e50c3f
JB		 1374static int i915_fbc_status(struct seq_file *m, void *unused)
1375{
9f25d007 1376 struct drm_info_node *node = m->private;
b5e50c3f 1377 struct drm_device *dev = node->minor->dev;
e277a1f8 1378 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1379
3a77c4c4 1380 if (!HAS_FBC(dev)) {
267f0c90 1381 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1382 return 0;
1383 }
1384
36623ef8
PZ		 1385 intel_runtime_pm_get(dev_priv);
1386
ee5382ae 1387 if (intel_fbc_enabled(dev)) {
267f0c90 1388 seq_puts(m, "FBC enabled\n");
b5e50c3f 1389 } else {
267f0c90 1390 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1391 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1392 case FBC_OK:
1393 seq_puts(m, "FBC actived, but currently disabled in hardware");
1394 break;
1395 case FBC_UNSUPPORTED:
1396 seq_puts(m, "unsupported by this chipset");
1397 break;
bed4a673 1398 case FBC_NO_OUTPUT:
267f0c90 1399 seq_puts(m, "no outputs");
bed4a673 1400 break;
b5e50c3f 1401 case FBC_STOLEN_TOO_SMALL:
267f0c90 1402 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1403 break;
1404 case FBC_UNSUPPORTED_MODE:
267f0c90 1405 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1406 break;
1407 case FBC_MODE_TOO_LARGE:
267f0c90 1408 seq_puts(m, "mode too large");
b5e50c3f
JB		 1409 break;
1410 case FBC_BAD_PLANE:
267f0c90 1411 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1412 break;
1413 case FBC_NOT_TILED:
267f0c90 1414 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1415 break;
9c928d16 1416 case FBC_MULTIPLE_PIPES:
267f0c90 1417 seq_puts(m, "multiple pipes are enabled");
9c928d16 1418 break;
c1a9f047 1419 case FBC_MODULE_PARAM:
267f0c90 1420 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1421 break;
8a5729a3 1422 case FBC_CHIP_DEFAULT:
267f0c90 1423 seq_puts(m, "disabled per chip default");
8a5729a3 1424 break;
b5e50c3f 1425 default:
267f0c90 1426 seq_puts(m, "unknown reason");
b5e50c3f 1427 }
267f0c90 1428 seq_putc(m, '\n');
b5e50c3f 1429 }
36623ef8
PZ		 1430
1431 intel_runtime_pm_put(dev_priv);
1432
b5e50c3f
JB		 1433 return 0;
1434}
1435
92d44621
PZ		 1436static int i915_ips_status(struct seq_file *m, void *unused)
1437{
9f25d007 1438 struct drm_info_node *node = m->private;
92d44621
PZ		 1439 struct drm_device *dev = node->minor->dev;
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441
f5adf94e 1442 if (!HAS_IPS(dev)) {
92d44621
PZ		 1443 seq_puts(m, "not supported\n");
1444 return 0;
1445 }
1446
36623ef8
PZ		 1447 intel_runtime_pm_get(dev_priv);
1448
0eaa53f0
RV		 1449 seq_printf(m, "Enabled by kernel parameter: %s\n",
1450 yesno(i915.enable_ips));
1451
1452 if (INTEL_INFO(dev)->gen >= 8) {
1453 seq_puts(m, "Currently: unknown\n");
1454 } else {
1455 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1456 seq_puts(m, "Currently: enabled\n");
1457 else
1458 seq_puts(m, "Currently: disabled\n");
1459 }
92d44621 1460
36623ef8
PZ		 1461 intel_runtime_pm_put(dev_priv);
1462
92d44621
PZ		 1463 return 0;
1464}
1465
4a9bef37
JB		 1466static int i915_sr_status(struct seq_file *m, void *unused)
1467{
9f25d007 1468 struct drm_info_node *node = m->private;
4a9bef37 1469 struct drm_device *dev = node->minor->dev;
e277a1f8 1470 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1471 bool sr_enabled = false;
1472
36623ef8
PZ		 1473 intel_runtime_pm_get(dev_priv);
1474
1398261a 1475 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1476 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1477 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1478 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1479 else if (IS_I915GM(dev))
1480 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1481 else if (IS_PINEVIEW(dev))
1482 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1483
36623ef8
PZ		 1484 intel_runtime_pm_put(dev_priv);
1485
5ba2aaaa
CW		 1486 seq_printf(m, "self-refresh: %s\n",
1487 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1488
1489 return 0;
1490}
1491
7648fa99
JB		 1492static int i915_emon_status(struct seq_file *m, void *unused)
1493{
9f25d007 1494 struct drm_info_node *node = m->private;
7648fa99 1495 struct drm_device *dev = node->minor->dev;
e277a1f8 1496 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1497 unsigned long temp, chipset, gfx;
de227ef0
CW		 1498 int ret;
1499
582be6b4
CW		 1500 if (!IS_GEN5(dev))
1501 return -ENODEV;
1502
de227ef0
CW		 1503 ret = mutex_lock_interruptible(&dev->struct_mutex);
1504 if (ret)
1505 return ret;
7648fa99
JB		 1506
1507 temp = i915_mch_val(dev_priv);
1508 chipset = i915_chipset_val(dev_priv);
1509 gfx = i915_gfx_val(dev_priv);
de227ef0 1510 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1511
1512 seq_printf(m, "GMCH temp: %ld\n", temp);
1513 seq_printf(m, "Chipset power: %ld\n", chipset);
1514 seq_printf(m, "GFX power: %ld\n", gfx);
1515 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1516
1517 return 0;
1518}
1519
23b2f8bb
JB		 1520static int i915_ring_freq_table(struct seq_file *m, void *unused)
1521{
9f25d007 1522 struct drm_info_node *node = m->private;
23b2f8bb 1523 struct drm_device *dev = node->minor->dev;
e277a1f8 1524 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1525 int ret = 0;
23b2f8bb
JB		 1526 int gpu_freq, ia_freq;
1527
1c70c0ce 1528 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1529 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1530 return 0;
1531 }
1532
5bfa0199
PZ		 1533 intel_runtime_pm_get(dev_priv);
1534
5c9669ce
TR		 1535 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1536
4fc688ce 1537 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1538 if (ret)
5bfa0199 1539 goto out;
23b2f8bb 1540
267f0c90 1541 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1542
b39fb297
BW		 1543 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1544 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1545 gpu_freq++) {
42c0526c
BW		 1546 ia_freq = gpu_freq;
1547 sandybridge_pcode_read(dev_priv,
1548 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1549 &ia_freq);
3ebecd07
CW		 1550 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1551 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1552 ((ia_freq >> 0) & 0xff) * 100,
1553 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1554 }
1555
4fc688ce 1556 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1557
5bfa0199
PZ		 1558out:
1559 intel_runtime_pm_put(dev_priv);
1560 return ret;
23b2f8bb
JB		 1561}
1562
44834a67
CW		 1563static int i915_opregion(struct seq_file *m, void *unused)
1564{
9f25d007 1565 struct drm_info_node *node = m->private;
44834a67 1566 struct drm_device *dev = node->minor->dev;
e277a1f8 1567 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1568 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1569 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1570 int ret;
1571
0d38f009
DV		 1572 if (data == NULL)
1573 return -ENOMEM;
1574
44834a67
CW		 1575 ret = mutex_lock_interruptible(&dev->struct_mutex);
1576 if (ret)
0d38f009 1577 goto out;
44834a67 1578
0d38f009
DV		 1579 if (opregion->header) {
1580 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1581 seq_write(m, data, OPREGION_SIZE);
1582 }
44834a67
CW		 1583
1584 mutex_unlock(&dev->struct_mutex);
1585
0d38f009
DV		 1586out:
1587 kfree(data);
44834a67
CW		 1588 return 0;
1589}
1590
37811fcc
CW		 1591static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1592{
9f25d007 1593 struct drm_info_node *node = m->private;
37811fcc 1594 struct drm_device *dev = node->minor->dev;
4520f53a 1595 struct intel_fbdev *ifbdev = NULL;
37811fcc 1596 struct intel_framebuffer *fb;
37811fcc 1597
4520f53a
DV		 1598#ifdef CONFIG_DRM_I915_FBDEV
1599 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1600
1601 ifbdev = dev_priv->fbdev;
1602 fb = to_intel_framebuffer(ifbdev->helper.fb);
1603
623f9783 1604 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1605 fb->base.width,
1606 fb->base.height,
1607 fb->base.depth,
623f9783
DV		 1608 fb->base.bits_per_pixel,
1609 atomic_read(&fb->base.refcount.refcount));
05394f39 1610 describe_obj(m, fb->obj);
267f0c90 1611 seq_putc(m, '\n');
4520f53a 1612#endif
37811fcc 1613
4b096ac1 1614 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1615 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1616 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1617 continue;
1618
623f9783 1619 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1620 fb->base.width,
1621 fb->base.height,
1622 fb->base.depth,
623f9783
DV		 1623 fb->base.bits_per_pixel,
1624 atomic_read(&fb->base.refcount.refcount));
05394f39 1625 describe_obj(m, fb->obj);
267f0c90 1626 seq_putc(m, '\n');
37811fcc 1627 }
4b096ac1 1628 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1629
1630 return 0;
1631}
1632
e76d3630
BW		 1633static int i915_context_status(struct seq_file *m, void *unused)
1634{
9f25d007 1635 struct drm_info_node *node = m->private;
e76d3630 1636 struct drm_device *dev = node->minor->dev;
e277a1f8 1637 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1638 struct intel_engine_cs *ring;
273497e5 1639 struct intel_context *ctx;
a168c293 1640 int ret, i;
e76d3630 1641
f3d28878 1642 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1643 if (ret)
1644 return ret;
1645
3e373948 1646 if (dev_priv->ips.pwrctx) {
267f0c90 1647 seq_puts(m, "power context ");
3e373948 1648 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1649 seq_putc(m, '\n');
dc501fbc 1650 }
e76d3630 1651
3e373948 1652 if (dev_priv->ips.renderctx) {
267f0c90 1653 seq_puts(m, "render context ");
3e373948 1654 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1655 seq_putc(m, '\n');
dc501fbc 1656 }
e76d3630 1657
a33afea5 1658 list_for_each_entry(ctx, &dev_priv->context_list, link) {
ea0c76f8 1659 if (ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1660 continue;
1661
a33afea5 1662 seq_puts(m, "HW context ");
3ccfd19d 1663 describe_ctx(m, ctx);
a33afea5
BW		 1664 for_each_ring(ring, dev_priv, i)
1665 if (ring->default_context == ctx)
1666 seq_printf(m, "(default context %s) ", ring->name);
1667
ea0c76f8 1668 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
a33afea5 1669 seq_putc(m, '\n');
a168c293
BW		 1670 }
1671
f3d28878 1672 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1673
1674 return 0;
1675}
1676
6d794d42
BW		 1677static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1678{
9f25d007 1679 struct drm_info_node *node = m->private;
6d794d42
BW		 1680 struct drm_device *dev = node->minor->dev;
1681 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1682 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1683
907b28c5 1684 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1685 if (IS_VALLEYVIEW(dev)) {
1686 fw_rendercount = dev_priv->uncore.fw_rendercount;
1687 fw_mediacount = dev_priv->uncore.fw_mediacount;
1688 } else
1689 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1690 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1691
43709ba0
D		 1692 if (IS_VALLEYVIEW(dev)) {
1693 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1694 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1695 } else
1696 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1697
1698 return 0;
1699}
1700
ea16a3cd
DV		 1701static const char *swizzle_string(unsigned swizzle)
1702{
aee56cff 1703 switch (swizzle) {
ea16a3cd
DV		 1704 case I915_BIT_6_SWIZZLE_NONE:
1705 return "none";
1706 case I915_BIT_6_SWIZZLE_9:
1707 return "bit9";
1708 case I915_BIT_6_SWIZZLE_9_10:
1709 return "bit9/bit10";
1710 case I915_BIT_6_SWIZZLE_9_11:
1711 return "bit9/bit11";
1712 case I915_BIT_6_SWIZZLE_9_10_11:
1713 return "bit9/bit10/bit11";
1714 case I915_BIT_6_SWIZZLE_9_17:
1715 return "bit9/bit17";
1716 case I915_BIT_6_SWIZZLE_9_10_17:
1717 return "bit9/bit10/bit17";
1718 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1719 return "unknown";
ea16a3cd
DV		 1720 }
1721
1722 return "bug";
1723}
1724
1725static int i915_swizzle_info(struct seq_file *m, void *data)
1726{
9f25d007 1727 struct drm_info_node *node = m->private;
ea16a3cd
DV		 1728 struct drm_device *dev = node->minor->dev;
1729 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1730 int ret;
1731
1732 ret = mutex_lock_interruptible(&dev->struct_mutex);
1733 if (ret)
1734 return ret;
c8c8fb33 1735 intel_runtime_pm_get(dev_priv);
ea16a3cd 1736
ea16a3cd
DV		 1737 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1738 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1739 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1740 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1741
1742 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1743 seq_printf(m, "DDC = 0x%08x\n",
1744 I915_READ(DCC));
1745 seq_printf(m, "C0DRB3 = 0x%04x\n",
1746 I915_READ16(C0DRB3));
1747 seq_printf(m, "C1DRB3 = 0x%04x\n",
1748 I915_READ16(C1DRB3));
9d3203e1 1749 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1750 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1751 I915_READ(MAD_DIMM_C0));
1752 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1753 I915_READ(MAD_DIMM_C1));
1754 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1755 I915_READ(MAD_DIMM_C2));
1756 seq_printf(m, "TILECTL = 0x%08x\n",
1757 I915_READ(TILECTL));
9d3203e1
BW		 1758 if (IS_GEN8(dev))
1759 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1760 I915_READ(GAMTARBMODE));
1761 else
1762 seq_printf(m, "ARB_MODE = 0x%08x\n",
1763 I915_READ(ARB_MODE));
3fa7d235
DV		 1764 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1765 I915_READ(DISP_ARB_CTL));
ea16a3cd 1766 }
c8c8fb33 1767 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 1768 mutex_unlock(&dev->struct_mutex);
1769
1770 return 0;
1771}
1772
1c60fef5
BW		 1773static int per_file_ctx(int id, void *ptr, void *data)
1774{
273497e5 1775 struct intel_context *ctx = ptr;
1c60fef5
BW		 1776 struct seq_file *m = data;
1777 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1778
f83d6518
OM		 1779 if (i915_gem_context_is_default(ctx))
1780 seq_puts(m, " default context:\n");
1781 else
821d66dd 1782 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 1783 ppgtt->debug_dump(ppgtt, m);
1784
1785 return 0;
1786}
1787
77df6772 1788static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 1789{
3cf17fc5 1790 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1791 struct intel_engine_cs *ring;
77df6772
BW		 1792 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1793 int unused, i;
3cf17fc5 1794
77df6772
BW		 1795 if (!ppgtt)
1796 return;
1797
1798 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 1799 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 1800 for_each_ring(ring, dev_priv, unused) {
1801 seq_printf(m, "%s\n", ring->name);
1802 for (i = 0; i < 4; i++) {
1803 u32 offset = 0x270 + i * 8;
1804 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1805 pdp <<= 32;
1806 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 1807 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 1808 }
1809 }
1810}
1811
1812static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1813{
1814 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1815 struct intel_engine_cs *ring;
1c60fef5 1816 struct drm_file *file;
77df6772 1817 int i;
3cf17fc5 1818
3cf17fc5
DV		 1819 if (INTEL_INFO(dev)->gen == 6)
1820 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1821
a2c7f6fd 1822 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1823 seq_printf(m, "%s\n", ring->name);
1824 if (INTEL_INFO(dev)->gen == 7)
1825 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1826 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1827 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1828 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1829 }
1830 if (dev_priv->mm.aliasing_ppgtt) {
1831 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1832
267f0c90 1833 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 1834 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 1835
87d60b63 1836 ppgtt->debug_dump(ppgtt, m);
1c60fef5
BW		 1837 } else
1838 return;
1839
1840 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1841 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 1842
1c60fef5
BW		 1843 seq_printf(m, "proc: %s\n",
1844 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 1845 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 1846 }
1847 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 1848}
1849
1850static int i915_ppgtt_info(struct seq_file *m, void *data)
1851{
9f25d007 1852 struct drm_info_node *node = m->private;
77df6772 1853 struct drm_device *dev = node->minor->dev;
c8c8fb33 1854 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 1855
1856 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1857 if (ret)
1858 return ret;
c8c8fb33 1859 intel_runtime_pm_get(dev_priv);
77df6772
BW		 1860
1861 if (INTEL_INFO(dev)->gen >= 8)
1862 gen8_ppgtt_info(m, dev);
1863 else if (INTEL_INFO(dev)->gen >= 6)
1864 gen6_ppgtt_info(m, dev);
1865
c8c8fb33 1866 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 1867 mutex_unlock(&dev->struct_mutex);
1868
1869 return 0;
1870}
1871
63573eb7
BW		 1872static int i915_llc(struct seq_file *m, void *data)
1873{
9f25d007 1874 struct drm_info_node *node = m->private;
63573eb7
BW		 1875 struct drm_device *dev = node->minor->dev;
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1877
1878 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1879 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1880 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1881
1882 return 0;
1883}
1884
e91fd8c6
RV		 1885static int i915_edp_psr_status(struct seq_file *m, void *data)
1886{
1887 struct drm_info_node *node = m->private;
1888 struct drm_device *dev = node->minor->dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1890 u32 psrperf = 0;
1891 bool enabled = false;
e91fd8c6 1892
c8c8fb33
PZ		 1893 intel_runtime_pm_get(dev_priv);
1894
a031d709
RV		 1895 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1896 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
5755c78f
RV		 1897 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
1898 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
e91fd8c6 1899
a031d709
RV		 1900 enabled = HAS_PSR(dev) &&
1901 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
5755c78f 1902 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
e91fd8c6 1903
a031d709
RV		 1904 if (HAS_PSR(dev))
1905 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1906 EDP_PSR_PERF_CNT_MASK;
1907 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6 1908
c8c8fb33 1909 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 1910 return 0;
1911}
1912
d2e216d0
RV		 1913static int i915_sink_crc(struct seq_file *m, void *data)
1914{
1915 struct drm_info_node *node = m->private;
1916 struct drm_device *dev = node->minor->dev;
1917 struct intel_encoder *encoder;
1918 struct intel_connector *connector;
1919 struct intel_dp *intel_dp = NULL;
1920 int ret;
1921 u8 crc[6];
1922
1923 drm_modeset_lock_all(dev);
1924 list_for_each_entry(connector, &dev->mode_config.connector_list,
1925 base.head) {
1926
1927 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1928 continue;
1929
b6ae3c7c
PZ		 1930 if (!connector->base.encoder)
1931 continue;
1932
d2e216d0
RV		 1933 encoder = to_intel_encoder(connector->base.encoder);
1934 if (encoder->type != INTEL_OUTPUT_EDP)
1935 continue;
1936
1937 intel_dp = enc_to_intel_dp(&encoder->base);
1938
1939 ret = intel_dp_sink_crc(intel_dp, crc);
1940 if (ret)
1941 goto out;
1942
1943 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1944 crc[0], crc[1], crc[2],
1945 crc[3], crc[4], crc[5]);
1946 goto out;
1947 }
1948 ret = -ENODEV;
1949out:
1950 drm_modeset_unlock_all(dev);
1951 return ret;
1952}
1953
ec013e7f
JB		 1954static int i915_energy_uJ(struct seq_file *m, void *data)
1955{
1956 struct drm_info_node *node = m->private;
1957 struct drm_device *dev = node->minor->dev;
1958 struct drm_i915_private *dev_priv = dev->dev_private;
1959 u64 power;
1960 u32 units;
1961
1962 if (INTEL_INFO(dev)->gen < 6)
1963 return -ENODEV;
1964
36623ef8
PZ		 1965 intel_runtime_pm_get(dev_priv);
1966
ec013e7f
JB		 1967 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1968 power = (power & 0x1f00) >> 8;
1969 units = 1000000 / (1 << power); /* convert to uJ */
1970 power = I915_READ(MCH_SECP_NRG_STTS);
1971 power *= units;
1972
36623ef8
PZ		 1973 intel_runtime_pm_put(dev_priv);
1974
ec013e7f 1975 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 1976
1977 return 0;
1978}
1979
1980static int i915_pc8_status(struct seq_file *m, void *unused)
1981{
9f25d007 1982 struct drm_info_node *node = m->private;
371db66a
PZ		 1983 struct drm_device *dev = node->minor->dev;
1984 struct drm_i915_private *dev_priv = dev->dev_private;
1985
85b8d5c2 1986 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 1987 seq_puts(m, "not supported\n");
1988 return 0;
1989 }
1990
86c4ec0d 1991 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 1992 seq_printf(m, "IRQs disabled: %s\n",
5d584b2e 1993 yesno(dev_priv->pm.irqs_disabled));
371db66a 1994
ec013e7f
JB		 1995 return 0;
1996}
1997
1da51581
ID		 1998static const char *power_domain_str(enum intel_display_power_domain domain)
1999{
2000 switch (domain) {
2001 case POWER_DOMAIN_PIPE_A:
2002 return "PIPE_A";
2003 case POWER_DOMAIN_PIPE_B:
2004 return "PIPE_B";
2005 case POWER_DOMAIN_PIPE_C:
2006 return "PIPE_C";
2007 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2008 return "PIPE_A_PANEL_FITTER";
2009 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2010 return "PIPE_B_PANEL_FITTER";
2011 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2012 return "PIPE_C_PANEL_FITTER";
2013 case POWER_DOMAIN_TRANSCODER_A:
2014 return "TRANSCODER_A";
2015 case POWER_DOMAIN_TRANSCODER_B:
2016 return "TRANSCODER_B";
2017 case POWER_DOMAIN_TRANSCODER_C:
2018 return "TRANSCODER_C";
2019 case POWER_DOMAIN_TRANSCODER_EDP:
2020 return "TRANSCODER_EDP";
319be8ae
ID		 2021 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2022 return "PORT_DDI_A_2_LANES";
2023 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2024 return "PORT_DDI_A_4_LANES";
2025 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2026 return "PORT_DDI_B_2_LANES";
2027 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2028 return "PORT_DDI_B_4_LANES";
2029 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2030 return "PORT_DDI_C_2_LANES";
2031 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2032 return "PORT_DDI_C_4_LANES";
2033 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2034 return "PORT_DDI_D_2_LANES";
2035 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2036 return "PORT_DDI_D_4_LANES";
2037 case POWER_DOMAIN_PORT_DSI:
2038 return "PORT_DSI";
2039 case POWER_DOMAIN_PORT_CRT:
2040 return "PORT_CRT";
2041 case POWER_DOMAIN_PORT_OTHER:
2042 return "PORT_OTHER";
1da51581
ID		 2043 case POWER_DOMAIN_VGA:
2044 return "VGA";
2045 case POWER_DOMAIN_AUDIO:
2046 return "AUDIO";
bd2bb1b9
PZ		 2047 case POWER_DOMAIN_PLLS:
2048 return "PLLS";
1da51581
ID		 2049 case POWER_DOMAIN_INIT:
2050 return "INIT";
2051 default:
2052 WARN_ON(1);
2053 return "?";
2054 }
2055}
2056
2057static int i915_power_domain_info(struct seq_file *m, void *unused)
2058{
9f25d007 2059 struct drm_info_node *node = m->private;
1da51581
ID		 2060 struct drm_device *dev = node->minor->dev;
2061 struct drm_i915_private *dev_priv = dev->dev_private;
2062 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2063 int i;
2064
2065 mutex_lock(&power_domains->lock);
2066
2067 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2068 for (i = 0; i < power_domains->power_well_count; i++) {
2069 struct i915_power_well *power_well;
2070 enum intel_display_power_domain power_domain;
2071
2072 power_well = &power_domains->power_wells[i];
2073 seq_printf(m, "%-25s %d\n", power_well->name,
2074 power_well->count);
2075
2076 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2077 power_domain++) {
2078 if (!(BIT(power_domain) & power_well->domains))
2079 continue;
2080
2081 seq_printf(m, " %-23s %d\n",
2082 power_domain_str(power_domain),
2083 power_domains->domain_use_count[power_domain]);
2084 }
2085 }
2086
2087 mutex_unlock(&power_domains->lock);
2088
2089 return 0;
2090}
2091
53f5e3ca
JB		 2092static void intel_seq_print_mode(struct seq_file *m, int tabs,
2093 struct drm_display_mode *mode)
2094{
2095 int i;
2096
2097 for (i = 0; i < tabs; i++)
2098 seq_putc(m, '\t');
2099
2100 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2101 mode->base.id, mode->name,
2102 mode->vrefresh, mode->clock,
2103 mode->hdisplay, mode->hsync_start,
2104 mode->hsync_end, mode->htotal,
2105 mode->vdisplay, mode->vsync_start,
2106 mode->vsync_end, mode->vtotal,
2107 mode->type, mode->flags);
2108}
2109
2110static void intel_encoder_info(struct seq_file *m,
2111 struct intel_crtc *intel_crtc,
2112 struct intel_encoder *intel_encoder)
2113{
9f25d007 2114 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2115 struct drm_device *dev = node->minor->dev;
2116 struct drm_crtc *crtc = &intel_crtc->base;
2117 struct intel_connector *intel_connector;
2118 struct drm_encoder *encoder;
2119
2120 encoder = &intel_encoder->base;
2121 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2122 encoder->base.id, encoder->name);
53f5e3ca
JB		 2123 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2124 struct drm_connector *connector = &intel_connector->base;
2125 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2126 connector->base.id,
c23cc417 2127 connector->name,
53f5e3ca
JB		 2128 drm_get_connector_status_name(connector->status));
2129 if (connector->status == connector_status_connected) {
2130 struct drm_display_mode *mode = &crtc->mode;
2131 seq_printf(m, ", mode:\n");
2132 intel_seq_print_mode(m, 2, mode);
2133 } else {
2134 seq_putc(m, '\n');
2135 }
2136 }
2137}
2138
2139static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2140{
9f25d007 2141 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2142 struct drm_device *dev = node->minor->dev;
2143 struct drm_crtc *crtc = &intel_crtc->base;
2144 struct intel_encoder *intel_encoder;
2145
5aa8a937
MR		 2146 if (crtc->primary->fb)
2147 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2148 crtc->primary->fb->base.id, crtc->x, crtc->y,
2149 crtc->primary->fb->width, crtc->primary->fb->height);
2150 else
2151 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2152 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2153 intel_encoder_info(m, intel_crtc, intel_encoder);
2154}
2155
2156static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2157{
2158 struct drm_display_mode *mode = panel->fixed_mode;
2159
2160 seq_printf(m, "\tfixed mode:\n");
2161 intel_seq_print_mode(m, 2, mode);
2162}
2163
2164static void intel_dp_info(struct seq_file *m,
2165 struct intel_connector *intel_connector)
2166{
2167 struct intel_encoder *intel_encoder = intel_connector->encoder;
2168 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2169
2170 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2171 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2172 "no");
2173 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2174 intel_panel_info(m, &intel_connector->panel);
2175}
2176
2177static void intel_hdmi_info(struct seq_file *m,
2178 struct intel_connector *intel_connector)
2179{
2180 struct intel_encoder *intel_encoder = intel_connector->encoder;
2181 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2182
2183 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2184 "no");
2185}
2186
2187static void intel_lvds_info(struct seq_file *m,
2188 struct intel_connector *intel_connector)
2189{
2190 intel_panel_info(m, &intel_connector->panel);
2191}
2192
2193static void intel_connector_info(struct seq_file *m,
2194 struct drm_connector *connector)
2195{
2196 struct intel_connector *intel_connector = to_intel_connector(connector);
2197 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2198 struct drm_display_mode *mode;
53f5e3ca
JB		 2199
2200 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2201 connector->base.id, connector->name,
53f5e3ca
JB		 2202 drm_get_connector_status_name(connector->status));
2203 if (connector->status == connector_status_connected) {
2204 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2205 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2206 connector->display_info.width_mm,
2207 connector->display_info.height_mm);
2208 seq_printf(m, "\tsubpixel order: %s\n",
2209 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2210 seq_printf(m, "\tCEA rev: %d\n",
2211 connector->display_info.cea_rev);
2212 }
2213 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2214 intel_encoder->type == INTEL_OUTPUT_EDP)
2215 intel_dp_info(m, intel_connector);
2216 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2217 intel_hdmi_info(m, intel_connector);
2218 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2219 intel_lvds_info(m, intel_connector);
2220
f103fc7d
JB		 2221 seq_printf(m, "\tmodes:\n");
2222 list_for_each_entry(mode, &connector->modes, head)
2223 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2224}
2225
065f2ec2
CW		 2226static bool cursor_active(struct drm_device *dev, int pipe)
2227{
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229 u32 state;
2230
2231 if (IS_845G(dev) || IS_I865G(dev))
2232 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2233 else
5efb3e28 2234 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2235
2236 return state;
2237}
2238
2239static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2240{
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 u32 pos;
2243
5efb3e28 2244 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2245
2246 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2247 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2248 *x = -*x;
2249
2250 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2251 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2252 *y = -*y;
2253
2254 return cursor_active(dev, pipe);
2255}
2256
53f5e3ca
JB		 2257static int i915_display_info(struct seq_file *m, void *unused)
2258{
9f25d007 2259 struct drm_info_node *node = m->private;
53f5e3ca 2260 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2261 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2262 struct intel_crtc *crtc;
53f5e3ca
JB		 2263 struct drm_connector *connector;
2264
b0e5ddf3 2265 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2266 drm_modeset_lock_all(dev);
2267 seq_printf(m, "CRTC info\n");
2268 seq_printf(m, "---------\n");
d3fcc808 2269 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2270 bool active;
2271 int x, y;
53f5e3ca 2272
57127efa 2273 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2274 crtc->base.base.id, pipe_name(crtc->pipe),
57127efa 2275 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
a23dc658 2276 if (crtc->active) {
065f2ec2
CW		 2277 intel_crtc_info(m, crtc);
2278
a23dc658 2279 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2280 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2281 yesno(crtc->cursor_base),
57127efa
CW		 2282 x, y, crtc->cursor_width, crtc->cursor_height,
2283 crtc->cursor_addr, yesno(active));
a23dc658 2284 }
cace841c
DV		 2285
2286 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2287 yesno(!crtc->cpu_fifo_underrun_disabled),
2288 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2289 }
2290
2291 seq_printf(m, "\n");
2292 seq_printf(m, "Connector info\n");
2293 seq_printf(m, "--------------\n");
2294 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2295 intel_connector_info(m, connector);
2296 }
2297 drm_modeset_unlock_all(dev);
b0e5ddf3 2298 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2299
2300 return 0;
2301}
2302
e04934cf
BW		 2303static int i915_semaphore_status(struct seq_file *m, void *unused)
2304{
2305 struct drm_info_node *node = (struct drm_info_node *) m->private;
2306 struct drm_device *dev = node->minor->dev;
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 struct intel_engine_cs *ring;
2309 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2310 int i, j, ret;
2311
2312 if (!i915_semaphore_is_enabled(dev)) {
2313 seq_puts(m, "Semaphores are disabled\n");
2314 return 0;
2315 }
2316
2317 ret = mutex_lock_interruptible(&dev->struct_mutex);
2318 if (ret)
2319 return ret;
03872064 2320 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2321
2322 if (IS_BROADWELL(dev)) {
2323 struct page *page;
2324 uint64_t *seqno;
2325
2326 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2327
2328 seqno = (uint64_t *)kmap_atomic(page);
2329 for_each_ring(ring, dev_priv, i) {
2330 uint64_t offset;
2331
2332 seq_printf(m, "%s\n", ring->name);
2333
2334 seq_puts(m, " Last signal:");
2335 for (j = 0; j < num_rings; j++) {
2336 offset = i * I915_NUM_RINGS + j;
2337 seq_printf(m, "0x%08llx (0x%02llx) ",
2338 seqno[offset], offset * 8);
2339 }
2340 seq_putc(m, '\n');
2341
2342 seq_puts(m, " Last wait: ");
2343 for (j = 0; j < num_rings; j++) {
2344 offset = i + (j * I915_NUM_RINGS);
2345 seq_printf(m, "0x%08llx (0x%02llx) ",
2346 seqno[offset], offset * 8);
2347 }
2348 seq_putc(m, '\n');
2349
2350 }
2351 kunmap_atomic(seqno);
2352 } else {
2353 seq_puts(m, " Last signal:");
2354 for_each_ring(ring, dev_priv, i)
2355 for (j = 0; j < num_rings; j++)
2356 seq_printf(m, "0x%08x\n",
2357 I915_READ(ring->semaphore.mbox.signal[j]));
2358 seq_putc(m, '\n');
2359 }
2360
2361 seq_puts(m, "\nSync seqno:\n");
2362 for_each_ring(ring, dev_priv, i) {
2363 for (j = 0; j < num_rings; j++) {
2364 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2365 }
2366 seq_putc(m, '\n');
2367 }
2368 seq_putc(m, '\n');
2369
03872064 2370 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2371 mutex_unlock(&dev->struct_mutex);
2372 return 0;
2373}
2374
728e29d7
DV		 2375static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2376{
2377 struct drm_info_node *node = (struct drm_info_node *) m->private;
2378 struct drm_device *dev = node->minor->dev;
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 int i;
2381
2382 drm_modeset_lock_all(dev);
2383 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2384 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2385
2386 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2387 seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount,
2388 pll->active, yesno(pll->on));
2389 seq_printf(m, " tracked hardware state:\n");
2390 seq_printf(m, " dpll: 0x%08x\n", pll->hw_state.dpll);
2391 seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);
2392 seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0);
2393 seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1);
d452c5b6 2394 seq_printf(m, " wrpll: 0x%08x\n", pll->hw_state.wrpll);
728e29d7
DV		 2395 }
2396 drm_modeset_unlock_all(dev);
2397
2398 return 0;
2399}
2400
07144428
DL		 2401struct pipe_crc_info {
2402 const char *name;
2403 struct drm_device *dev;
2404 enum pipe pipe;
2405};
2406
2407static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2408{
be5c7a90
DL		 2409 struct pipe_crc_info *info = inode->i_private;
2410 struct drm_i915_private *dev_priv = info->dev->dev_private;
2411 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2412
7eb1c496
DV		 2413 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2414 return -ENODEV;
2415
d538bbdf
DL		 2416 spin_lock_irq(&pipe_crc->lock);
2417
2418 if (pipe_crc->opened) {
2419 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2420 return -EBUSY; /* already open */
2421 }
2422
d538bbdf 2423 pipe_crc->opened = true;
07144428
DL		 2424 filep->private_data = inode->i_private;
2425
d538bbdf
DL		 2426 spin_unlock_irq(&pipe_crc->lock);
2427
07144428
DL		 2428 return 0;
2429}
2430
2431static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2432{
be5c7a90
DL		 2433 struct pipe_crc_info *info = inode->i_private;
2434 struct drm_i915_private *dev_priv = info->dev->dev_private;
2435 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2436
d538bbdf
DL		 2437 spin_lock_irq(&pipe_crc->lock);
2438 pipe_crc->opened = false;
2439 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2440
07144428
DL		 2441 return 0;
2442}
2443
2444/* (6 fields, 8 chars each, space separated (5) + '\n') */
2445#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2446/* account for \'0' */
2447#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2448
2449static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2450{
d538bbdf
DL		 2451 assert_spin_locked(&pipe_crc->lock);
2452 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2453 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2454}
2455
2456static ssize_t
2457i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2458 loff_t *pos)
2459{
2460 struct pipe_crc_info *info = filep->private_data;
2461 struct drm_device *dev = info->dev;
2462 struct drm_i915_private *dev_priv = dev->dev_private;
2463 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2464 char buf[PIPE_CRC_BUFFER_LEN];
2465 int head, tail, n_entries, n;
2466 ssize_t bytes_read;
2467
2468 /*
2469 * Don't allow user space to provide buffers not big enough to hold
2470 * a line of data.
2471 */
2472 if (count < PIPE_CRC_LINE_LEN)
2473 return -EINVAL;
2474
2475 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2476 return 0;
07144428
DL		 2477
2478 /* nothing to read */
d538bbdf 2479 spin_lock_irq(&pipe_crc->lock);
07144428 2480 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2481 int ret;
2482
2483 if (filep->f_flags & O_NONBLOCK) {
2484 spin_unlock_irq(&pipe_crc->lock);
07144428 2485 return -EAGAIN;
d538bbdf 2486 }
07144428 2487
d538bbdf
DL		 2488 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2489 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2490 if (ret) {
2491 spin_unlock_irq(&pipe_crc->lock);
2492 return ret;
2493 }
8bf1e9f1
SH		 2494 }
2495
07144428 2496 /* We now have one or more entries to read */
d538bbdf
DL		 2497 head = pipe_crc->head;
2498 tail = pipe_crc->tail;
07144428
DL		 2499 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2500 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2501 spin_unlock_irq(&pipe_crc->lock);
2502
07144428
DL		 2503 bytes_read = 0;
2504 n = 0;
2505 do {
b2c88f5b 2506 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2507 int ret;
8bf1e9f1 2508
07144428
DL		 2509 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2510 "%8u %8x %8x %8x %8x %8x\n",
2511 entry->frame, entry->crc[0],
2512 entry->crc[1], entry->crc[2],
2513 entry->crc[3], entry->crc[4]);
2514
2515 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2516 buf, PIPE_CRC_LINE_LEN);
2517 if (ret == PIPE_CRC_LINE_LEN)
2518 return -EFAULT;
b2c88f5b
DL		 2519
2520 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2521 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2522 n++;
2523 } while (--n_entries);
8bf1e9f1 2524
d538bbdf
DL		 2525 spin_lock_irq(&pipe_crc->lock);
2526 pipe_crc->tail = tail;
2527 spin_unlock_irq(&pipe_crc->lock);
2528
07144428
DL		 2529 return bytes_read;
2530}
2531
2532static const struct file_operations i915_pipe_crc_fops = {
2533 .owner = THIS_MODULE,
2534 .open = i915_pipe_crc_open,
2535 .read = i915_pipe_crc_read,
2536 .release = i915_pipe_crc_release,
2537};
2538
2539static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2540 {
2541 .name = "i915_pipe_A_crc",
2542 .pipe = PIPE_A,
2543 },
2544 {
2545 .name = "i915_pipe_B_crc",
2546 .pipe = PIPE_B,
2547 },
2548 {
2549 .name = "i915_pipe_C_crc",
2550 .pipe = PIPE_C,
2551 },
2552};
2553
2554static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2555 enum pipe pipe)
2556{
2557 struct drm_device *dev = minor->dev;
2558 struct dentry *ent;
2559 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2560
2561 info->dev = dev;
2562 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2563 &i915_pipe_crc_fops);
f3c5fe97
WY		 2564 if (!ent)
2565 return -ENOMEM;
07144428
DL		 2566
2567 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2568}
2569
e8dfcf78 2570static const char * const pipe_crc_sources[] = {
926321d5
DV		 2571 "none",
2572 "plane1",
2573 "plane2",
2574 "pf",
5b3a856b 2575 "pipe",
3d099a05
DV		 2576 "TV",
2577 "DP-B",
2578 "DP-C",
2579 "DP-D",
46a19188 2580 "auto",
926321d5
DV		 2581};
2582
2583static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2584{
2585 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2586 return pipe_crc_sources[source];
2587}
2588
bd9db02f 2589static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2590{
2591 struct drm_device *dev = m->private;
2592 struct drm_i915_private *dev_priv = dev->dev_private;
2593 int i;
2594
2595 for (i = 0; i < I915_MAX_PIPES; i++)
2596 seq_printf(m, "%c %s\n", pipe_name(i),
2597 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2598
2599 return 0;
2600}
2601
bd9db02f 2602static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2603{
2604 struct drm_device *dev = inode->i_private;
2605
bd9db02f 2606 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2607}
2608
46a19188 2609static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2610 uint32_t *val)
2611{
46a19188
DV		 2612 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2613 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2614
2615 switch (*source) {
52f843f6
DV		 2616 case INTEL_PIPE_CRC_SOURCE_PIPE:
2617 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2618 break;
2619 case INTEL_PIPE_CRC_SOURCE_NONE:
2620 *val = 0;
2621 break;
2622 default:
2623 return -EINVAL;
2624 }
2625
2626 return 0;
2627}
2628
46a19188
DV		 2629static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2630 enum intel_pipe_crc_source *source)
2631{
2632 struct intel_encoder *encoder;
2633 struct intel_crtc *crtc;
26756809 2634 struct intel_digital_port *dig_port;
46a19188
DV		 2635 int ret = 0;
2636
2637 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2638
6e9f798d 2639 drm_modeset_lock_all(dev);
46a19188
DV		 2640 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2641 base.head) {
2642 if (!encoder->base.crtc)
2643 continue;
2644
2645 crtc = to_intel_crtc(encoder->base.crtc);
2646
2647 if (crtc->pipe != pipe)
2648 continue;
2649
2650 switch (encoder->type) {
2651 case INTEL_OUTPUT_TVOUT:
2652 *source = INTEL_PIPE_CRC_SOURCE_TV;
2653 break;
2654 case INTEL_OUTPUT_DISPLAYPORT:
2655 case INTEL_OUTPUT_EDP:
26756809
DV		 2656 dig_port = enc_to_dig_port(&encoder->base);
2657 switch (dig_port->port) {
2658 case PORT_B:
2659 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2660 break;
2661 case PORT_C:
2662 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2663 break;
2664 case PORT_D:
2665 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2666 break;
2667 default:
2668 WARN(1, "nonexisting DP port %c\n",
2669 port_name(dig_port->port));
2670 break;
2671 }
46a19188
DV		 2672 break;
2673 }
2674 }
6e9f798d 2675 drm_modeset_unlock_all(dev);
46a19188
DV		 2676
2677 return ret;
2678}
2679
2680static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2681 enum pipe pipe,
2682 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2683 uint32_t *val)
2684{
8d2f24ca
DV		 2685 struct drm_i915_private *dev_priv = dev->dev_private;
2686 bool need_stable_symbols = false;
2687
46a19188
DV		 2688 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2689 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2690 if (ret)
2691 return ret;
2692 }
2693
2694 switch (*source) {
7ac0129b
DV		 2695 case INTEL_PIPE_CRC_SOURCE_PIPE:
2696 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2697 break;
2698 case INTEL_PIPE_CRC_SOURCE_DP_B:
2699 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2700 need_stable_symbols = true;
7ac0129b
DV		 2701 break;
2702 case INTEL_PIPE_CRC_SOURCE_DP_C:
2703 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2704 need_stable_symbols = true;
7ac0129b
DV		 2705 break;
2706 case INTEL_PIPE_CRC_SOURCE_NONE:
2707 *val = 0;
2708 break;
2709 default:
2710 return -EINVAL;
2711 }
2712
8d2f24ca
DV		 2713 /*
2714 * When the pipe CRC tap point is after the transcoders we need
2715 * to tweak symbol-level features to produce a deterministic series of
2716 * symbols for a given frame. We need to reset those features only once
2717 * a frame (instead of every nth symbol):
2718 * - DC-balance: used to ensure a better clock recovery from the data
2719 * link (SDVO)
2720 * - DisplayPort scrambling: used for EMI reduction
2721 */
2722 if (need_stable_symbols) {
2723 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2724
8d2f24ca
DV		 2725 tmp |= DC_BALANCE_RESET_VLV;
2726 if (pipe == PIPE_A)
2727 tmp |= PIPE_A_SCRAMBLE_RESET;
2728 else
2729 tmp |= PIPE_B_SCRAMBLE_RESET;
2730
2731 I915_WRITE(PORT_DFT2_G4X, tmp);
2732 }
2733
7ac0129b
DV		 2734 return 0;
2735}
2736
4b79ebf7 2737static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2738 enum pipe pipe,
2739 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2740 uint32_t *val)
2741{
84093603
DV		 2742 struct drm_i915_private *dev_priv = dev->dev_private;
2743 bool need_stable_symbols = false;
2744
46a19188
DV		 2745 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2746 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2747 if (ret)
2748 return ret;
2749 }
2750
2751 switch (*source) {
4b79ebf7
DV		 2752 case INTEL_PIPE_CRC_SOURCE_PIPE:
2753 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2754 break;
2755 case INTEL_PIPE_CRC_SOURCE_TV:
2756 if (!SUPPORTS_TV(dev))
2757 return -EINVAL;
2758 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2759 break;
2760 case INTEL_PIPE_CRC_SOURCE_DP_B:
2761 if (!IS_G4X(dev))
2762 return -EINVAL;
2763 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2764 need_stable_symbols = true;
4b79ebf7
DV		 2765 break;
2766 case INTEL_PIPE_CRC_SOURCE_DP_C:
2767 if (!IS_G4X(dev))
2768 return -EINVAL;
2769 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2770 need_stable_symbols = true;
4b79ebf7
DV		 2771 break;
2772 case INTEL_PIPE_CRC_SOURCE_DP_D:
2773 if (!IS_G4X(dev))
2774 return -EINVAL;
2775 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2776 need_stable_symbols = true;
4b79ebf7
DV		 2777 break;
2778 case INTEL_PIPE_CRC_SOURCE_NONE:
2779 *val = 0;
2780 break;
2781 default:
2782 return -EINVAL;
2783 }
2784
84093603
DV		 2785 /*
2786 * When the pipe CRC tap point is after the transcoders we need
2787 * to tweak symbol-level features to produce a deterministic series of
2788 * symbols for a given frame. We need to reset those features only once
2789 * a frame (instead of every nth symbol):
2790 * - DC-balance: used to ensure a better clock recovery from the data
2791 * link (SDVO)
2792 * - DisplayPort scrambling: used for EMI reduction
2793 */
2794 if (need_stable_symbols) {
2795 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2796
2797 WARN_ON(!IS_G4X(dev));
2798
2799 I915_WRITE(PORT_DFT_I9XX,
2800 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2801
2802 if (pipe == PIPE_A)
2803 tmp |= PIPE_A_SCRAMBLE_RESET;
2804 else
2805 tmp |= PIPE_B_SCRAMBLE_RESET;
2806
2807 I915_WRITE(PORT_DFT2_G4X, tmp);
2808 }
2809
4b79ebf7
DV		 2810 return 0;
2811}
2812
8d2f24ca
DV		 2813static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2814 enum pipe pipe)
2815{
2816 struct drm_i915_private *dev_priv = dev->dev_private;
2817 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2818
2819 if (pipe == PIPE_A)
2820 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2821 else
2822 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2823 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2824 tmp &= ~DC_BALANCE_RESET_VLV;
2825 I915_WRITE(PORT_DFT2_G4X, tmp);
2826
2827}
2828
84093603
DV		 2829static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2830 enum pipe pipe)
2831{
2832 struct drm_i915_private *dev_priv = dev->dev_private;
2833 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2834
2835 if (pipe == PIPE_A)
2836 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2837 else
2838 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2839 I915_WRITE(PORT_DFT2_G4X, tmp);
2840
2841 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2842 I915_WRITE(PORT_DFT_I9XX,
2843 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2844 }
2845}
2846
46a19188 2847static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2848 uint32_t *val)
2849{
46a19188
DV		 2850 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2851 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2852
2853 switch (*source) {
5b3a856b
DV		 2854 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2855 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2856 break;
2857 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2858 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2859 break;
5b3a856b
DV		 2860 case INTEL_PIPE_CRC_SOURCE_PIPE:
2861 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2862 break;
3d099a05 2863 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2864 *val = 0;
2865 break;
3d099a05
DV		 2866 default:
2867 return -EINVAL;
5b3a856b
DV		 2868 }
2869
2870 return 0;
2871}
2872
fabf6e51
DV		 2873static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
2874{
2875 struct drm_i915_private *dev_priv = dev->dev_private;
2876 struct intel_crtc *crtc =
2877 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
2878
2879 drm_modeset_lock_all(dev);
2880 /*
2881 * If we use the eDP transcoder we need to make sure that we don't
2882 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
2883 * relevant on hsw with pipe A when using the always-on power well
2884 * routing.
2885 */
2886 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
2887 !crtc->config.pch_pfit.enabled) {
2888 crtc->config.pch_pfit.force_thru = true;
2889
2890 intel_display_power_get(dev_priv,
2891 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
2892
2893 dev_priv->display.crtc_disable(&crtc->base);
2894 dev_priv->display.crtc_enable(&crtc->base);
2895 }
2896 drm_modeset_unlock_all(dev);
2897}
2898
2899static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
2900{
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 struct intel_crtc *crtc =
2903 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
2904
2905 drm_modeset_lock_all(dev);
2906 /*
2907 * If we use the eDP transcoder we need to make sure that we don't
2908 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
2909 * relevant on hsw with pipe A when using the always-on power well
2910 * routing.
2911 */
2912 if (crtc->config.pch_pfit.force_thru) {
2913 crtc->config.pch_pfit.force_thru = false;
2914
2915 dev_priv->display.crtc_disable(&crtc->base);
2916 dev_priv->display.crtc_enable(&crtc->base);
2917
2918 intel_display_power_put(dev_priv,
2919 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
2920 }
2921 drm_modeset_unlock_all(dev);
2922}
2923
2924static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
2925 enum pipe pipe,
2926 enum intel_pipe_crc_source *source,
5b3a856b
DV		 2927 uint32_t *val)
2928{
46a19188
DV		 2929 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2930 *source = INTEL_PIPE_CRC_SOURCE_PF;
2931
2932 switch (*source) {
5b3a856b
DV		 2933 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2934 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2935 break;
2936 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2937 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2938 break;
2939 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 2940 if (IS_HASWELL(dev) && pipe == PIPE_A)
2941 hsw_trans_edp_pipe_A_crc_wa(dev);
2942
5b3a856b
DV		 2943 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2944 break;
3d099a05 2945 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2946 *val = 0;
2947 break;
3d099a05
DV		 2948 default:
2949 return -EINVAL;
5b3a856b
DV		 2950 }
2951
2952 return 0;
2953}
2954
926321d5
DV		 2955static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2956 enum intel_pipe_crc_source source)
2957{
2958 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2959 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 2960 u32 val = 0; /* shut up gcc */
5b3a856b 2961 int ret;
926321d5 2962
cc3da175
DL		 2963 if (pipe_crc->source == source)
2964 return 0;
2965
ae676fcd
DL		 2966 /* forbid changing the source without going back to 'none' */
2967 if (pipe_crc->source && source)
2968 return -EINVAL;
2969
52f843f6 2970 if (IS_GEN2(dev))
46a19188 2971 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2972 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2973 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2974 else if (IS_VALLEYVIEW(dev))
fabf6e51 2975 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 2976 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2977 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2978 else
fabf6e51 2979 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 2980
2981 if (ret != 0)
2982 return ret;
2983
4b584369
DL		 2984 /* none -> real source transition */
2985 if (source) {
7cd6ccff
DL		 2986 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2987 pipe_name(pipe), pipe_crc_source_name(source));
2988
e5f75aca
DL		 2989 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2990 INTEL_PIPE_CRC_ENTRIES_NR,
2991 GFP_KERNEL);
2992 if (!pipe_crc->entries)
2993 return -ENOMEM;
2994
d538bbdf
DL		 2995 spin_lock_irq(&pipe_crc->lock);
2996 pipe_crc->head = 0;
2997 pipe_crc->tail = 0;
2998 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2999 }
3000
cc3da175 3001 pipe_crc->source = source;
926321d5 3002
926321d5
DV		 3003 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3004 POSTING_READ(PIPE_CRC_CTL(pipe));
3005
e5f75aca
DL		 3006 /* real source -> none transition */
3007 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3008 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3009 struct intel_crtc *crtc =
3010 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3011
7cd6ccff
DL		 3012 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3013 pipe_name(pipe));
3014
a33d7105
DV		 3015 drm_modeset_lock(&crtc->base.mutex, NULL);
3016 if (crtc->active)
3017 intel_wait_for_vblank(dev, pipe);
3018 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3019
d538bbdf
DL		 3020 spin_lock_irq(&pipe_crc->lock);
3021 entries = pipe_crc->entries;
e5f75aca 3022 pipe_crc->entries = NULL;
d538bbdf
DL		 3023 spin_unlock_irq(&pipe_crc->lock);
3024
3025 kfree(entries);
84093603
DV		 3026
3027 if (IS_G4X(dev))
3028 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3029 else if (IS_VALLEYVIEW(dev))
3030 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3031 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3032 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
e5f75aca
DL		 3033 }
3034
926321d5
DV		 3035 return 0;
3036}
3037
3038/*
3039 * Parse pipe CRC command strings:
b94dec87
DL		 3040 * command: wsp* object wsp+ name wsp+ source wsp*
3041 * object: 'pipe'
3042 * name: (A | B | C)
926321d5
DV		 3043 * source: (none | plane1 | plane2 | pf)
3044 * wsp: (#0x20 | #0x9 | #0xA)+
3045 *
3046 * eg.:
b94dec87
DL		 3047 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3048 * "pipe A none" -> Stop CRC
926321d5 3049 */
bd9db02f 3050static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3051{
3052 int n_words = 0;
3053
3054 while (*buf) {
3055 char *end;
3056
3057 /* skip leading white space */
3058 buf = skip_spaces(buf);
3059 if (!*buf)
3060 break; /* end of buffer */
3061
3062 /* find end of word */
3063 for (end = buf; *end && !isspace(*end); end++)
3064 ;
3065
3066 if (n_words == max_words) {
3067 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3068 max_words);
3069 return -EINVAL; /* ran out of words[] before bytes */
3070 }
3071
3072 if (*end)
3073 *end++ = '\0';
3074 words[n_words++] = buf;
3075 buf = end;
3076 }
3077
3078 return n_words;
3079}
3080
b94dec87
DL		 3081enum intel_pipe_crc_object {
3082 PIPE_CRC_OBJECT_PIPE,
3083};
3084
e8dfcf78 3085static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3086 "pipe",
3087};
3088
3089static int
bd9db02f 3090display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3091{
3092 int i;
3093
3094 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3095 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3096 *o = i;
b94dec87
DL		 3097 return 0;
3098 }
3099
3100 return -EINVAL;
3101}
3102
bd9db02f 3103static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3104{
3105 const char name = buf[0];
3106
3107 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3108 return -EINVAL;
3109
3110 *pipe = name - 'A';
3111
3112 return 0;
3113}
3114
3115static int
bd9db02f 3116display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3117{
3118 int i;
3119
3120 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3121 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3122 *s = i;
926321d5
DV		 3123 return 0;
3124 }
3125
3126 return -EINVAL;
3127}
3128
bd9db02f 3129static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3130{
b94dec87 3131#define N_WORDS 3
926321d5 3132 int n_words;
b94dec87 3133 char *words[N_WORDS];
926321d5 3134 enum pipe pipe;
b94dec87 3135 enum intel_pipe_crc_object object;
926321d5
DV		 3136 enum intel_pipe_crc_source source;
3137
bd9db02f 3138 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3139 if (n_words != N_WORDS) {
3140 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3141 N_WORDS);
3142 return -EINVAL;
3143 }
3144
bd9db02f 3145 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3146 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3147 return -EINVAL;
3148 }
3149
bd9db02f 3150 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3151 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3152 return -EINVAL;
3153 }
3154
bd9db02f 3155 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3156 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3157 return -EINVAL;
3158 }
3159
3160 return pipe_crc_set_source(dev, pipe, source);
3161}
3162
bd9db02f
DL		 3163static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3164 size_t len, loff_t *offp)
926321d5
DV		 3165{
3166 struct seq_file *m = file->private_data;
3167 struct drm_device *dev = m->private;
3168 char *tmpbuf;
3169 int ret;
3170
3171 if (len == 0)
3172 return 0;
3173
3174 if (len > PAGE_SIZE - 1) {
3175 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3176 PAGE_SIZE);
3177 return -E2BIG;
3178 }
3179
3180 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3181 if (!tmpbuf)
3182 return -ENOMEM;
3183
3184 if (copy_from_user(tmpbuf, ubuf, len)) {
3185 ret = -EFAULT;
3186 goto out;
3187 }
3188 tmpbuf[len] = '\0';
3189
bd9db02f 3190 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3191
3192out:
3193 kfree(tmpbuf);
3194 if (ret < 0)
3195 return ret;
3196
3197 *offp += len;
3198 return len;
3199}
3200
bd9db02f 3201static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3202 .owner = THIS_MODULE,
bd9db02f 3203 .open = display_crc_ctl_open,
926321d5
DV		 3204 .read = seq_read,
3205 .llseek = seq_lseek,
3206 .release = single_release,
bd9db02f 3207 .write = display_crc_ctl_write
926321d5
DV		 3208};
3209
369a1342
VS		 3210static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3211{
3212 struct drm_device *dev = m->private;
546c81fd 3213 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3214 int level;
3215
3216 drm_modeset_lock_all(dev);
3217
3218 for (level = 0; level < num_levels; level++) {
3219 unsigned int latency = wm[level];
3220
3221 /* WM1+ latency values in 0.5us units */
3222 if (level > 0)
3223 latency *= 5;
3224
3225 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3226 level, wm[level],
3227 latency / 10, latency % 10);
3228 }
3229
3230 drm_modeset_unlock_all(dev);
3231}
3232
3233static int pri_wm_latency_show(struct seq_file *m, void *data)
3234{
3235 struct drm_device *dev = m->private;
3236
3237 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3238
3239 return 0;
3240}
3241
3242static int spr_wm_latency_show(struct seq_file *m, void *data)
3243{
3244 struct drm_device *dev = m->private;
3245
3246 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3247
3248 return 0;
3249}
3250
3251static int cur_wm_latency_show(struct seq_file *m, void *data)
3252{
3253 struct drm_device *dev = m->private;
3254
3255 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3256
3257 return 0;
3258}
3259
3260static int pri_wm_latency_open(struct inode *inode, struct file *file)
3261{
3262 struct drm_device *dev = inode->i_private;
3263
3264 if (!HAS_PCH_SPLIT(dev))
3265 return -ENODEV;
3266
3267 return single_open(file, pri_wm_latency_show, dev);
3268}
3269
3270static int spr_wm_latency_open(struct inode *inode, struct file *file)
3271{
3272 struct drm_device *dev = inode->i_private;
3273
3274 if (!HAS_PCH_SPLIT(dev))
3275 return -ENODEV;
3276
3277 return single_open(file, spr_wm_latency_show, dev);
3278}
3279
3280static int cur_wm_latency_open(struct inode *inode, struct file *file)
3281{
3282 struct drm_device *dev = inode->i_private;
3283
3284 if (!HAS_PCH_SPLIT(dev))
3285 return -ENODEV;
3286
3287 return single_open(file, cur_wm_latency_show, dev);
3288}
3289
3290static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3291 size_t len, loff_t *offp, uint16_t wm[5])
3292{
3293 struct seq_file *m = file->private_data;
3294 struct drm_device *dev = m->private;
3295 uint16_t new[5] = { 0 };
546c81fd 3296 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3297 int level;
3298 int ret;
3299 char tmp[32];
3300
3301 if (len >= sizeof(tmp))
3302 return -EINVAL;
3303
3304 if (copy_from_user(tmp, ubuf, len))
3305 return -EFAULT;
3306
3307 tmp[len] = '\0';
3308
3309 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3310 if (ret != num_levels)
3311 return -EINVAL;
3312
3313 drm_modeset_lock_all(dev);
3314
3315 for (level = 0; level < num_levels; level++)
3316 wm[level] = new[level];
3317
3318 drm_modeset_unlock_all(dev);
3319
3320 return len;
3321}
3322
3323
3324static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3325 size_t len, loff_t *offp)
3326{
3327 struct seq_file *m = file->private_data;
3328 struct drm_device *dev = m->private;
3329
3330 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3331}
3332
3333static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3334 size_t len, loff_t *offp)
3335{
3336 struct seq_file *m = file->private_data;
3337 struct drm_device *dev = m->private;
3338
3339 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3340}
3341
3342static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3343 size_t len, loff_t *offp)
3344{
3345 struct seq_file *m = file->private_data;
3346 struct drm_device *dev = m->private;
3347
3348 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3349}
3350
3351static const struct file_operations i915_pri_wm_latency_fops = {
3352 .owner = THIS_MODULE,
3353 .open = pri_wm_latency_open,
3354 .read = seq_read,
3355 .llseek = seq_lseek,
3356 .release = single_release,
3357 .write = pri_wm_latency_write
3358};
3359
3360static const struct file_operations i915_spr_wm_latency_fops = {
3361 .owner = THIS_MODULE,
3362 .open = spr_wm_latency_open,
3363 .read = seq_read,
3364 .llseek = seq_lseek,
3365 .release = single_release,
3366 .write = spr_wm_latency_write
3367};
3368
3369static const struct file_operations i915_cur_wm_latency_fops = {
3370 .owner = THIS_MODULE,
3371 .open = cur_wm_latency_open,
3372 .read = seq_read,
3373 .llseek = seq_lseek,
3374 .release = single_release,
3375 .write = cur_wm_latency_write
3376};
3377
647416f9
KC		 3378static int
3379i915_wedged_get(void *data, u64 *val)
f3cd474b 3380{
647416f9 3381 struct drm_device *dev = data;
e277a1f8 3382 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3383
647416f9 3384 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3385
647416f9 3386 return 0;
f3cd474b
CW		 3387}
3388
647416f9
KC		 3389static int
3390i915_wedged_set(void *data, u64 val)
f3cd474b 3391{
647416f9 3392 struct drm_device *dev = data;
d46c0517
ID		 3393 struct drm_i915_private *dev_priv = dev->dev_private;
3394
3395 intel_runtime_pm_get(dev_priv);
f3cd474b 3396
58174462
MK		 3397 i915_handle_error(dev, val,
3398 "Manually setting wedged to %llu", val);
d46c0517
ID		 3399
3400 intel_runtime_pm_put(dev_priv);
3401
647416f9 3402 return 0;
f3cd474b
CW		 3403}
3404
647416f9
KC		 3405DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3406 i915_wedged_get, i915_wedged_set,
3a3b4f98 3407 "%llu\n");
f3cd474b 3408
647416f9
KC		 3409static int
3410i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3411{
647416f9 3412 struct drm_device *dev = data;
e277a1f8 3413 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3414
647416f9 3415 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3416
647416f9 3417 return 0;
e5eb3d63
DV		 3418}
3419
647416f9
KC		 3420static int
3421i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3422{
647416f9 3423 struct drm_device *dev = data;
e5eb3d63 3424 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3425 int ret;
e5eb3d63 3426
647416f9 3427 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3428
22bcfc6a
DV		 3429 ret = mutex_lock_interruptible(&dev->struct_mutex);
3430 if (ret)
3431 return ret;
3432
99584db3 3433 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3434 mutex_unlock(&dev->struct_mutex);
3435
647416f9 3436 return 0;
e5eb3d63
DV		 3437}
3438
647416f9
KC		 3439DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3440 i915_ring_stop_get, i915_ring_stop_set,
3441 "0x%08llx\n");
d5442303 3442
094f9a54
CW		 3443static int
3444i915_ring_missed_irq_get(void *data, u64 *val)
3445{
3446 struct drm_device *dev = data;
3447 struct drm_i915_private *dev_priv = dev->dev_private;
3448
3449 *val = dev_priv->gpu_error.missed_irq_rings;
3450 return 0;
3451}
3452
3453static int
3454i915_ring_missed_irq_set(void *data, u64 val)
3455{
3456 struct drm_device *dev = data;
3457 struct drm_i915_private *dev_priv = dev->dev_private;
3458 int ret;
3459
3460 /* Lock against concurrent debugfs callers */
3461 ret = mutex_lock_interruptible(&dev->struct_mutex);
3462 if (ret)
3463 return ret;
3464 dev_priv->gpu_error.missed_irq_rings = val;
3465 mutex_unlock(&dev->struct_mutex);
3466
3467 return 0;
3468}
3469
3470DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3471 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3472 "0x%08llx\n");
3473
3474static int
3475i915_ring_test_irq_get(void *data, u64 *val)
3476{
3477 struct drm_device *dev = data;
3478 struct drm_i915_private *dev_priv = dev->dev_private;
3479
3480 *val = dev_priv->gpu_error.test_irq_rings;
3481
3482 return 0;
3483}
3484
3485static int
3486i915_ring_test_irq_set(void *data, u64 val)
3487{
3488 struct drm_device *dev = data;
3489 struct drm_i915_private *dev_priv = dev->dev_private;
3490 int ret;
3491
3492 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3493
3494 /* Lock against concurrent debugfs callers */
3495 ret = mutex_lock_interruptible(&dev->struct_mutex);
3496 if (ret)
3497 return ret;
3498
3499 dev_priv->gpu_error.test_irq_rings = val;
3500 mutex_unlock(&dev->struct_mutex);
3501
3502 return 0;
3503}
3504
3505DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3506 i915_ring_test_irq_get, i915_ring_test_irq_set,
3507 "0x%08llx\n");
3508
dd624afd
CW		 3509#define DROP_UNBOUND 0x1
3510#define DROP_BOUND 0x2
3511#define DROP_RETIRE 0x4
3512#define DROP_ACTIVE 0x8
3513#define DROP_ALL (DROP_UNBOUND | \
3514 DROP_BOUND | \
3515 DROP_RETIRE | \
3516 DROP_ACTIVE)
647416f9
KC		 3517static int
3518i915_drop_caches_get(void *data, u64 *val)
dd624afd 3519{
647416f9 3520 *val = DROP_ALL;
dd624afd 3521
647416f9 3522 return 0;
dd624afd
CW		 3523}
3524
647416f9
KC		 3525static int
3526i915_drop_caches_set(void *data, u64 val)
dd624afd 3527{
647416f9 3528 struct drm_device *dev = data;
dd624afd
CW		 3529 struct drm_i915_private *dev_priv = dev->dev_private;
3530 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 3531 struct i915_address_space *vm;
3532 struct i915_vma *vma, *x;
647416f9 3533 int ret;
dd624afd 3534
2f9fe5ff 3535 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 3536
3537 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3538 * on ioctls on -EAGAIN. */
3539 ret = mutex_lock_interruptible(&dev->struct_mutex);
3540 if (ret)
3541 return ret;
3542
3543 if (val & DROP_ACTIVE) {
3544 ret = i915_gpu_idle(dev);
3545 if (ret)
3546 goto unlock;
3547 }
3548
3549 if (val & (DROP_RETIRE | DROP_ACTIVE))
3550 i915_gem_retire_requests(dev);
3551
3552 if (val & DROP_BOUND) {
ca191b13
BW		 3553 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3554 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3555 mm_list) {
d7f46fc4 3556 if (vma->pin_count)
ca191b13
BW		 3557 continue;
3558
3559 ret = i915_vma_unbind(vma);
3560 if (ret)
3561 goto unlock;
3562 }
31a46c9c 3563 }
dd624afd
CW		 3564 }
3565
3566 if (val & DROP_UNBOUND) {
35c20a60
BW		 3567 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3568 global_list)
dd624afd
CW		 3569 if (obj->pages_pin_count == 0) {
3570 ret = i915_gem_object_put_pages(obj);
3571 if (ret)
3572 goto unlock;
3573 }
3574 }
3575
3576unlock:
3577 mutex_unlock(&dev->struct_mutex);
3578
647416f9 3579 return ret;
dd624afd
CW		 3580}
3581
647416f9
KC		 3582DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3583 i915_drop_caches_get, i915_drop_caches_set,
3584 "0x%08llx\n");
dd624afd 3585
647416f9
KC		 3586static int
3587i915_max_freq_get(void *data, u64 *val)
358733e9 3588{
647416f9 3589 struct drm_device *dev = data;
e277a1f8 3590 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3591 int ret;
004777cb 3592
daa3afb2 3593 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 3594 return -ENODEV;
3595
5c9669ce
TR		 3596 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3597
4fc688ce 3598 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3599 if (ret)
3600 return ret;
358733e9 3601
0a073b84 3602 if (IS_VALLEYVIEW(dev))
b39fb297 3603 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 3604 else
b39fb297 3605 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3606 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3607
647416f9 3608 return 0;
358733e9
JB		 3609}
3610
647416f9
KC		 3611static int
3612i915_max_freq_set(void *data, u64 val)
358733e9 3613{
647416f9 3614 struct drm_device *dev = data;
358733e9 3615 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3616 u32 rp_state_cap, hw_max, hw_min;
647416f9 3617 int ret;
004777cb 3618
daa3afb2 3619 if (INTEL_INFO(dev)->gen < 6)
004777cb 3620 return -ENODEV;
358733e9 3621
5c9669ce
TR		 3622 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3623
647416f9 3624 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 3625
4fc688ce 3626 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3627 if (ret)
3628 return ret;
3629
358733e9
JB		 3630 /*
3631 * Turbo will still be enabled, but won't go above the set value.
3632 */
0a073b84 3633 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3634 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 3635
03af2045
VS		 3636 hw_max = dev_priv->rps.max_freq;
3637 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 3638 } else {
3639 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3640
3641 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3642 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3643 hw_min = (rp_state_cap >> 16) & 0xff;
3644 }
3645
b39fb297 3646 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 3647 mutex_unlock(&dev_priv->rps.hw_lock);
3648 return -EINVAL;
0a073b84
JB		 3649 }
3650
b39fb297 3651 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 3652
3653 if (IS_VALLEYVIEW(dev))
3654 valleyview_set_rps(dev, val);
3655 else
3656 gen6_set_rps(dev, val);
3657
4fc688ce 3658 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3659
647416f9 3660 return 0;
358733e9
JB		 3661}
3662
647416f9
KC		 3663DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3664 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 3665 "%llu\n");
358733e9 3666
647416f9
KC		 3667static int
3668i915_min_freq_get(void *data, u64 *val)
1523c310 3669{
647416f9 3670 struct drm_device *dev = data;
e277a1f8 3671 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3672 int ret;
004777cb 3673
daa3afb2 3674 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 3675 return -ENODEV;
3676
5c9669ce
TR		 3677 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3678
4fc688ce 3679 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3680 if (ret)
3681 return ret;
1523c310 3682
0a073b84 3683 if (IS_VALLEYVIEW(dev))
b39fb297 3684 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 3685 else
b39fb297 3686 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3687 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3688
647416f9 3689 return 0;
1523c310
JB		 3690}
3691
647416f9
KC		 3692static int
3693i915_min_freq_set(void *data, u64 val)
1523c310 3694{
647416f9 3695 struct drm_device *dev = data;
1523c310 3696 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3697 u32 rp_state_cap, hw_max, hw_min;
647416f9 3698 int ret;
004777cb 3699
daa3afb2 3700 if (INTEL_INFO(dev)->gen < 6)
004777cb 3701 return -ENODEV;
1523c310 3702
5c9669ce
TR		 3703 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3704
647416f9 3705 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 3706
4fc688ce 3707 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3708 if (ret)
3709 return ret;
3710
1523c310
JB		 3711 /*
3712 * Turbo will still be enabled, but won't go below the set value.
3713 */
0a073b84 3714 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3715 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 3716
03af2045
VS		 3717 hw_max = dev_priv->rps.max_freq;
3718 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 3719 } else {
3720 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3721
3722 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3723 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3724 hw_min = (rp_state_cap >> 16) & 0xff;
3725 }
3726
b39fb297 3727 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 3728 mutex_unlock(&dev_priv->rps.hw_lock);
3729 return -EINVAL;
0a073b84 3730 }
dd0a1aa1 3731
b39fb297 3732 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 3733
3734 if (IS_VALLEYVIEW(dev))
3735 valleyview_set_rps(dev, val);
3736 else
3737 gen6_set_rps(dev, val);
3738
4fc688ce 3739 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3740
647416f9 3741 return 0;
1523c310
JB		 3742}
3743
647416f9
KC		 3744DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3745 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 3746 "%llu\n");
1523c310 3747
647416f9
KC		 3748static int
3749i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 3750{
647416f9 3751 struct drm_device *dev = data;
e277a1f8 3752 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3753 u32 snpcr;
647416f9 3754 int ret;
07b7ddd9 3755
004777cb
DV		 3756 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3757 return -ENODEV;
3758
22bcfc6a
DV		 3759 ret = mutex_lock_interruptible(&dev->struct_mutex);
3760 if (ret)
3761 return ret;
c8c8fb33 3762 intel_runtime_pm_get(dev_priv);
22bcfc6a 3763
07b7ddd9 3764 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 3765
3766 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 3767 mutex_unlock(&dev_priv->dev->struct_mutex);
3768
647416f9 3769 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 3770
647416f9 3771 return 0;
07b7ddd9
JB		 3772}
3773
647416f9
KC		 3774static int
3775i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 3776{
647416f9 3777 struct drm_device *dev = data;
07b7ddd9 3778 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3779 u32 snpcr;
07b7ddd9 3780
004777cb
DV		 3781 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3782 return -ENODEV;
3783
647416f9 3784 if (val > 3)
07b7ddd9
JB		 3785 return -EINVAL;
3786
c8c8fb33 3787 intel_runtime_pm_get(dev_priv);
647416f9 3788 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 3789
3790 /* Update the cache sharing policy here as well */
3791 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3792 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3793 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3794 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3795
c8c8fb33 3796 intel_runtime_pm_put(dev_priv);
647416f9 3797 return 0;
07b7ddd9
JB		 3798}
3799
647416f9
KC		 3800DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3801 i915_cache_sharing_get, i915_cache_sharing_set,
3802 "%llu\n");
07b7ddd9 3803
6d794d42
BW		 3804static int i915_forcewake_open(struct inode *inode, struct file *file)
3805{
3806 struct drm_device *dev = inode->i_private;
3807 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 3808
075edca4 3809 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3810 return 0;
3811
c8d9a590 3812 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3813
3814 return 0;
3815}
3816
c43b5634 3817static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 3818{
3819 struct drm_device *dev = inode->i_private;
3820 struct drm_i915_private *dev_priv = dev->dev_private;
3821
075edca4 3822 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3823 return 0;
3824
c8d9a590 3825 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3826
3827 return 0;
3828}
3829
3830static const struct file_operations i915_forcewake_fops = {
3831 .owner = THIS_MODULE,
3832 .open = i915_forcewake_open,
3833 .release = i915_forcewake_release,
3834};
3835
3836static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3837{
3838 struct drm_device *dev = minor->dev;
3839 struct dentry *ent;
3840
3841 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 3842 S_IRUSR,
6d794d42
BW		 3843 root, dev,
3844 &i915_forcewake_fops);
f3c5fe97
WY		 3845 if (!ent)
3846 return -ENOMEM;
6d794d42 3847
8eb57294 3848 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 3849}
3850
6a9c308d
DV		 3851static int i915_debugfs_create(struct dentry *root,
3852 struct drm_minor *minor,
3853 const char *name,
3854 const struct file_operations *fops)
07b7ddd9
JB		 3855{
3856 struct drm_device *dev = minor->dev;
3857 struct dentry *ent;
3858
6a9c308d 3859 ent = debugfs_create_file(name,
07b7ddd9
JB		 3860 S_IRUGO | S_IWUSR,
3861 root, dev,
6a9c308d 3862 fops);
f3c5fe97
WY		 3863 if (!ent)
3864 return -ENOMEM;
07b7ddd9 3865
6a9c308d 3866 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 3867}
3868
06c5bf8c 3869static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 3870 {"i915_capabilities", i915_capabilities, 0},
73aa808f 3871 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 3872 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 3873 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 3874 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 3875 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 3876 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 3877 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 3878 {"i915_gem_request", i915_gem_request_info, 0},
3879 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 3880 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 3881 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 3882 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3883 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3884 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 3885 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
adb4bd12 3886 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1 3887 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 3888 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 3889 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 3890 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 3891 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 3892 {"i915_sr_status", i915_sr_status, 0},
44834a67 3893 {"i915_opregion", i915_opregion, 0},
37811fcc 3894 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 3895 {"i915_context_status", i915_context_status, 0},
6d794d42 3896 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 3897 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 3898 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 3899 {"i915_llc", i915_llc, 0},
e91fd8c6 3900 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 3901 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 3902 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 3903 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 3904 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 3905 {"i915_display_info", i915_display_info, 0},
e04934cf 3906 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 3907 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
2017263e 3908};
27c202ad 3909#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 3910
06c5bf8c 3911static const struct i915_debugfs_files {
34b9674c
DV		 3912 const char *name;
3913 const struct file_operations *fops;
3914} i915_debugfs_files[] = {
3915 {"i915_wedged", &i915_wedged_fops},
3916 {"i915_max_freq", &i915_max_freq_fops},
3917 {"i915_min_freq", &i915_min_freq_fops},
3918 {"i915_cache_sharing", &i915_cache_sharing_fops},
3919 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3920 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3921 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3922 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3923 {"i915_error_state", &i915_error_state_fops},
3924 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3925 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 3926 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3927 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3928 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
34b9674c
DV		 3929};
3930
07144428
DL		 3931void intel_display_crc_init(struct drm_device *dev)
3932{
3933 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 3934 enum pipe pipe;
07144428 3935
b378360e
DV		 3936 for_each_pipe(pipe) {
3937 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 3938
d538bbdf
DL		 3939 pipe_crc->opened = false;
3940 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3941 init_waitqueue_head(&pipe_crc->wq);
3942 }
3943}
3944
27c202ad 3945int i915_debugfs_init(struct drm_minor *minor)
2017263e 3946{
34b9674c 3947 int ret, i;
f3cd474b 3948
6d794d42 3949 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3950 if (ret)
3951 return ret;
6a9c308d 3952
07144428
DL		 3953 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3954 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3955 if (ret)
3956 return ret;
3957 }
3958
34b9674c
DV		 3959 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3960 ret = i915_debugfs_create(minor->debugfs_root, minor,
3961 i915_debugfs_files[i].name,
3962 i915_debugfs_files[i].fops);
3963 if (ret)
3964 return ret;
3965 }
40633219 3966
27c202ad
BG		 3967 return drm_debugfs_create_files(i915_debugfs_list,
3968 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3969 minor->debugfs_root, minor);
3970}
3971
27c202ad 3972void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3973{
34b9674c
DV		 3974 int i;
3975
27c202ad
BG		 3976 drm_debugfs_remove_files(i915_debugfs_list,
3977 I915_DEBUGFS_ENTRIES, minor);
07144428 3978
6d794d42
BW		 3979 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3980 1, minor);
07144428 3981
e309a997 3982 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3983 struct drm_info_list *info_list =
3984 (struct drm_info_list *)&i915_pipe_crc_data[i];
3985
3986 drm_debugfs_remove_files(info_list, 1, minor);
3987 }
3988
34b9674c
DV		 3989 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3990 struct drm_info_list *info_list =
3991 (struct drm_info_list *) i915_debugfs_files[i].fops;
3992
3993 drm_debugfs_remove_files(info_list, 1, minor);
3994 }
2017263e 3995}
Linux kernel - Deliverables
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