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drm/i915: move functions around
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
f3cd474b 30#include <linux/debugfs.h>
5a0e3ad6 31#include <linux/slab.h>
2d1a8a48 32#include <linux/export.h>
2017263e
BG		 33#include "drmP.h"
34#include "drm.h"
4e5359cd 35#include "intel_drv.h"
e5c65260 36#include "intel_ringbuffer.h"
2017263e
BG		 37#include "i915_drm.h"
38#include "i915_drv.h"
39
40#define DRM_I915_RING_DEBUG 1
41
42
43#if defined(CONFIG_DEBUG_FS)
44
f13d3f73 45enum {
69dc4987 46 ACTIVE_LIST,
f13d3f73 47 INACTIVE_LIST,
d21d5975 48 PINNED_LIST,
f13d3f73 49};
2017263e 50
70d39fe4
CW		 51static const char *yesno(int v)
52{
53 return v ? "yes" : "no";
54}
55
56static int i915_capabilities(struct seq_file *m, void *data)
57{
58 struct drm_info_node *node = (struct drm_info_node *) m->private;
59 struct drm_device *dev = node->minor->dev;
60 const struct intel_device_info *info = INTEL_INFO(dev);
61
62 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
c96ea64e
DV		 64#define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
65#define DEV_INFO_SEP ;
66 DEV_INFO_FLAGS;
67#undef DEV_INFO_FLAG
68#undef DEV_INFO_SEP
70d39fe4
CW		 69
70 return 0;
71}
2017263e 72
05394f39 73static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 74{
05394f39 75 if (obj->user_pin_count > 0)
a6172a80 76 return "P";
05394f39 77 else if (obj->pin_count > 0)
a6172a80
CW		 78 return "p";
79 else
80 return " ";
81}
82
05394f39 83static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 84{
0206e353
AJ		 85 switch (obj->tiling_mode) {
86 default:
87 case I915_TILING_NONE: return " ";
88 case I915_TILING_X: return "X";
89 case I915_TILING_Y: return "Y";
90 }
a6172a80
CW		 91}
92
93dfb40c 93static const char *cache_level_str(int type)
08c18323
CW		 94{
95 switch (type) {
93dfb40c
CW		 96 case I915_CACHE_NONE: return " uncached";
97 case I915_CACHE_LLC: return " snooped (LLC)";
98 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
08c18323
CW		 99 default: return "";
100 }
101}
102
37811fcc
CW		 103static void
104describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
105{
0201f1ec 106 seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d %d%s%s%s",
37811fcc
CW		 107 &obj->base,
108 get_pin_flag(obj),
109 get_tiling_flag(obj),
a05a5862 110 obj->base.size / 1024,
37811fcc
CW		 111 obj->base.read_domains,
112 obj->base.write_domain,
0201f1ec
CW		 113 obj->last_read_seqno,
114 obj->last_write_seqno,
caea7476 115 obj->last_fenced_seqno,
93dfb40c 116 cache_level_str(obj->cache_level),
37811fcc
CW		 117 obj->dirty ? " dirty" : "",
118 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
119 if (obj->base.name)
120 seq_printf(m, " (name: %d)", obj->base.name);
121 if (obj->fence_reg != I915_FENCE_REG_NONE)
122 seq_printf(m, " (fence: %d)", obj->fence_reg);
123 if (obj->gtt_space != NULL)
a00b10c3
CW		 124 seq_printf(m, " (gtt offset: %08x, size: %08x)",
125 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
6299f992
CW		 126 if (obj->pin_mappable || obj->fault_mappable) {
127 char s[3], *t = s;
128 if (obj->pin_mappable)
129 *t++ = 'p';
130 if (obj->fault_mappable)
131 *t++ = 'f';
132 *t = '\0';
133 seq_printf(m, " (%s mappable)", s);
134 }
69dc4987
CW		 135 if (obj->ring != NULL)
136 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 137}
138
433e12f7 139static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 140{
141 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 142 uintptr_t list = (uintptr_t) node->info_ent->data;
143 struct list_head *head;
2017263e
BG		 144 struct drm_device *dev = node->minor->dev;
145 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 146 struct drm_i915_gem_object *obj;
8f2480fb
CW		 147 size_t total_obj_size, total_gtt_size;
148 int count, ret;
de227ef0
CW		 149
150 ret = mutex_lock_interruptible(&dev->struct_mutex);
151 if (ret)
152 return ret;
2017263e 153
433e12f7
BG		 154 switch (list) {
155 case ACTIVE_LIST:
156 seq_printf(m, "Active:\n");
69dc4987 157 head = &dev_priv->mm.active_list;
433e12f7
BG		 158 break;
159 case INACTIVE_LIST:
a17458fc 160 seq_printf(m, "Inactive:\n");
433e12f7
BG		 161 head = &dev_priv->mm.inactive_list;
162 break;
433e12f7 163 default:
de227ef0
CW		 164 mutex_unlock(&dev->struct_mutex);
165 return -EINVAL;
2017263e 166 }
2017263e 167
8f2480fb 168 total_obj_size = total_gtt_size = count = 0;
05394f39 169 list_for_each_entry(obj, head, mm_list) {
37811fcc 170 seq_printf(m, " ");
05394f39 171 describe_obj(m, obj);
f4ceda89 172 seq_printf(m, "\n");
05394f39
CW		 173 total_obj_size += obj->base.size;
174 total_gtt_size += obj->gtt_space->size;
8f2480fb 175 count++;
2017263e 176 }
de227ef0 177 mutex_unlock(&dev->struct_mutex);
5e118f41 178
8f2480fb
CW		 179 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
180 count, total_obj_size, total_gtt_size);
2017263e
BG		 181 return 0;
182}
183
6299f992
CW		 184#define count_objects(list, member) do { \
185 list_for_each_entry(obj, list, member) { \
186 size += obj->gtt_space->size; \
187 ++count; \
188 if (obj->map_and_fenceable) { \
189 mappable_size += obj->gtt_space->size; \
190 ++mappable_count; \
191 } \
192 } \
0206e353 193} while (0)
6299f992 194
73aa808f
CW		 195static int i915_gem_object_info(struct seq_file *m, void* data)
196{
197 struct drm_info_node *node = (struct drm_info_node *) m->private;
198 struct drm_device *dev = node->minor->dev;
199 struct drm_i915_private *dev_priv = dev->dev_private;
6299f992
CW		 200 u32 count, mappable_count;
201 size_t size, mappable_size;
202 struct drm_i915_gem_object *obj;
73aa808f
CW		 203 int ret;
204
205 ret = mutex_lock_interruptible(&dev->struct_mutex);
206 if (ret)
207 return ret;
208
6299f992
CW		 209 seq_printf(m, "%u objects, %zu bytes\n",
210 dev_priv->mm.object_count,
211 dev_priv->mm.object_memory);
212
213 size = count = mappable_size = mappable_count = 0;
214 count_objects(&dev_priv->mm.gtt_list, gtt_list);
215 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
216 count, mappable_count, size, mappable_size);
217
218 size = count = mappable_size = mappable_count = 0;
219 count_objects(&dev_priv->mm.active_list, mm_list);
6299f992
CW		 220 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
221 count, mappable_count, size, mappable_size);
222
6299f992
CW		 223 size = count = mappable_size = mappable_count = 0;
224 count_objects(&dev_priv->mm.inactive_list, mm_list);
225 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
226 count, mappable_count, size, mappable_size);
227
6299f992
CW		 228 size = count = mappable_size = mappable_count = 0;
229 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
230 if (obj->fault_mappable) {
231 size += obj->gtt_space->size;
232 ++count;
233 }
234 if (obj->pin_mappable) {
235 mappable_size += obj->gtt_space->size;
236 ++mappable_count;
237 }
238 }
239 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
240 mappable_count, mappable_size);
241 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
242 count, size);
243
244 seq_printf(m, "%zu [%zu] gtt total\n",
245 dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
73aa808f
CW		 246
247 mutex_unlock(&dev->struct_mutex);
248
249 return 0;
250}
251
08c18323
CW		 252static int i915_gem_gtt_info(struct seq_file *m, void* data)
253{
254 struct drm_info_node *node = (struct drm_info_node *) m->private;
255 struct drm_device *dev = node->minor->dev;
1b50247a 256 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 257 struct drm_i915_private *dev_priv = dev->dev_private;
258 struct drm_i915_gem_object *obj;
259 size_t total_obj_size, total_gtt_size;
260 int count, ret;
261
262 ret = mutex_lock_interruptible(&dev->struct_mutex);
263 if (ret)
264 return ret;
265
266 total_obj_size = total_gtt_size = count = 0;
267 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
1b50247a
CW		 268 if (list == PINNED_LIST && obj->pin_count == 0)
269 continue;
270
08c18323
CW		 271 seq_printf(m, " ");
272 describe_obj(m, obj);
273 seq_printf(m, "\n");
274 total_obj_size += obj->base.size;
275 total_gtt_size += obj->gtt_space->size;
276 count++;
277 }
278
279 mutex_unlock(&dev->struct_mutex);
280
281 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
282 count, total_obj_size, total_gtt_size);
283
284 return 0;
285}
286
4e5359cd
SF		 287static int i915_gem_pageflip_info(struct seq_file *m, void *data)
288{
289 struct drm_info_node *node = (struct drm_info_node *) m->private;
290 struct drm_device *dev = node->minor->dev;
291 unsigned long flags;
292 struct intel_crtc *crtc;
293
294 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 295 const char pipe = pipe_name(crtc->pipe);
296 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 297 struct intel_unpin_work *work;
298
299 spin_lock_irqsave(&dev->event_lock, flags);
300 work = crtc->unpin_work;
301 if (work == NULL) {
9db4a9c7 302 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 303 pipe, plane);
304 } else {
305 if (!work->pending) {
9db4a9c7 306 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 307 pipe, plane);
308 } else {
9db4a9c7 309 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 310 pipe, plane);
311 }
312 if (work->enable_stall_check)
313 seq_printf(m, "Stall check enabled, ");
314 else
315 seq_printf(m, "Stall check waiting for page flip ioctl, ");
316 seq_printf(m, "%d prepares\n", work->pending);
317
318 if (work->old_fb_obj) {
05394f39
CW		 319 struct drm_i915_gem_object *obj = work->old_fb_obj;
320 if (obj)
321 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF		 322 }
323 if (work->pending_flip_obj) {
05394f39
CW		 324 struct drm_i915_gem_object *obj = work->pending_flip_obj;
325 if (obj)
326 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF		 327 }
328 }
329 spin_unlock_irqrestore(&dev->event_lock, flags);
330 }
331
332 return 0;
333}
334
2017263e
BG		 335static int i915_gem_request_info(struct seq_file *m, void *data)
336{
337 struct drm_info_node *node = (struct drm_info_node *) m->private;
338 struct drm_device *dev = node->minor->dev;
339 drm_i915_private_t *dev_priv = dev->dev_private;
340 struct drm_i915_gem_request *gem_request;
c2c347a9 341 int ret, count;
de227ef0
CW		 342
343 ret = mutex_lock_interruptible(&dev->struct_mutex);
344 if (ret)
345 return ret;
2017263e 346
c2c347a9 347 count = 0;
1ec14ad3 348 if (!list_empty(&dev_priv->ring[RCS].request_list)) {
c2c347a9
CW		 349 seq_printf(m, "Render requests:\n");
350 list_for_each_entry(gem_request,
1ec14ad3 351 &dev_priv->ring[RCS].request_list,
c2c347a9
CW		 352 list) {
353 seq_printf(m, " %d @ %d\n",
354 gem_request->seqno,
355 (int) (jiffies - gem_request->emitted_jiffies));
356 }
357 count++;
358 }
1ec14ad3 359 if (!list_empty(&dev_priv->ring[VCS].request_list)) {
c2c347a9
CW		 360 seq_printf(m, "BSD requests:\n");
361 list_for_each_entry(gem_request,
1ec14ad3 362 &dev_priv->ring[VCS].request_list,
c2c347a9
CW		 363 list) {
364 seq_printf(m, " %d @ %d\n",
365 gem_request->seqno,
366 (int) (jiffies - gem_request->emitted_jiffies));
367 }
368 count++;
369 }
1ec14ad3 370 if (!list_empty(&dev_priv->ring[BCS].request_list)) {
c2c347a9
CW		 371 seq_printf(m, "BLT requests:\n");
372 list_for_each_entry(gem_request,
1ec14ad3 373 &dev_priv->ring[BCS].request_list,
c2c347a9
CW		 374 list) {
375 seq_printf(m, " %d @ %d\n",
376 gem_request->seqno,
377 (int) (jiffies - gem_request->emitted_jiffies));
378 }
379 count++;
2017263e 380 }
de227ef0
CW		 381 mutex_unlock(&dev->struct_mutex);
382
c2c347a9
CW		 383 if (count == 0)
384 seq_printf(m, "No requests\n");
385
2017263e
BG		 386 return 0;
387}
388
b2223497
CW		 389static void i915_ring_seqno_info(struct seq_file *m,
390 struct intel_ring_buffer *ring)
391{
392 if (ring->get_seqno) {
393 seq_printf(m, "Current sequence (%s): %d\n",
b2eadbc8 394 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 395 }
396}
397
2017263e
BG		 398static int i915_gem_seqno_info(struct seq_file *m, void *data)
399{
400 struct drm_info_node *node = (struct drm_info_node *) m->private;
401 struct drm_device *dev = node->minor->dev;
402 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 403 int ret, i;
de227ef0
CW		 404
405 ret = mutex_lock_interruptible(&dev->struct_mutex);
406 if (ret)
407 return ret;
2017263e 408
1ec14ad3
CW		 409 for (i = 0; i < I915_NUM_RINGS; i++)
410 i915_ring_seqno_info(m, &dev_priv->ring[i]);
de227ef0
CW		 411
412 mutex_unlock(&dev->struct_mutex);
413
2017263e
BG		 414 return 0;
415}
416
417
418static int i915_interrupt_info(struct seq_file *m, void *data)
419{
420 struct drm_info_node *node = (struct drm_info_node *) m->private;
421 struct drm_device *dev = node->minor->dev;
422 drm_i915_private_t *dev_priv = dev->dev_private;
9db4a9c7 423 int ret, i, pipe;
de227ef0
CW		 424
425 ret = mutex_lock_interruptible(&dev->struct_mutex);
426 if (ret)
427 return ret;
2017263e 428
7e231dbe
JB		 429 if (IS_VALLEYVIEW(dev)) {
430 seq_printf(m, "Display IER:\t%08x\n",
431 I915_READ(VLV_IER));
432 seq_printf(m, "Display IIR:\t%08x\n",
433 I915_READ(VLV_IIR));
434 seq_printf(m, "Display IIR_RW:\t%08x\n",
435 I915_READ(VLV_IIR_RW));
436 seq_printf(m, "Display IMR:\t%08x\n",
437 I915_READ(VLV_IMR));
438 for_each_pipe(pipe)
439 seq_printf(m, "Pipe %c stat:\t%08x\n",
440 pipe_name(pipe),
441 I915_READ(PIPESTAT(pipe)));
442
443 seq_printf(m, "Master IER:\t%08x\n",
444 I915_READ(VLV_MASTER_IER));
445
446 seq_printf(m, "Render IER:\t%08x\n",
447 I915_READ(GTIER));
448 seq_printf(m, "Render IIR:\t%08x\n",
449 I915_READ(GTIIR));
450 seq_printf(m, "Render IMR:\t%08x\n",
451 I915_READ(GTIMR));
452
453 seq_printf(m, "PM IER:\t\t%08x\n",
454 I915_READ(GEN6_PMIER));
455 seq_printf(m, "PM IIR:\t\t%08x\n",
456 I915_READ(GEN6_PMIIR));
457 seq_printf(m, "PM IMR:\t\t%08x\n",
458 I915_READ(GEN6_PMIMR));
459
460 seq_printf(m, "Port hotplug:\t%08x\n",
461 I915_READ(PORT_HOTPLUG_EN));
462 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
463 I915_READ(VLV_DPFLIPSTAT));
464 seq_printf(m, "DPINVGTT:\t%08x\n",
465 I915_READ(DPINVGTT));
466
467 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 468 seq_printf(m, "Interrupt enable: %08x\n",
469 I915_READ(IER));
470 seq_printf(m, "Interrupt identity: %08x\n",
471 I915_READ(IIR));
472 seq_printf(m, "Interrupt mask: %08x\n",
473 I915_READ(IMR));
9db4a9c7
JB		 474 for_each_pipe(pipe)
475 seq_printf(m, "Pipe %c stat: %08x\n",
476 pipe_name(pipe),
477 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 478 } else {
479 seq_printf(m, "North Display Interrupt enable: %08x\n",
480 I915_READ(DEIER));
481 seq_printf(m, "North Display Interrupt identity: %08x\n",
482 I915_READ(DEIIR));
483 seq_printf(m, "North Display Interrupt mask: %08x\n",
484 I915_READ(DEIMR));
485 seq_printf(m, "South Display Interrupt enable: %08x\n",
486 I915_READ(SDEIER));
487 seq_printf(m, "South Display Interrupt identity: %08x\n",
488 I915_READ(SDEIIR));
489 seq_printf(m, "South Display Interrupt mask: %08x\n",
490 I915_READ(SDEIMR));
491 seq_printf(m, "Graphics Interrupt enable: %08x\n",
492 I915_READ(GTIER));
493 seq_printf(m, "Graphics Interrupt identity: %08x\n",
494 I915_READ(GTIIR));
495 seq_printf(m, "Graphics Interrupt mask: %08x\n",
496 I915_READ(GTIMR));
497 }
2017263e
BG		 498 seq_printf(m, "Interrupts received: %d\n",
499 atomic_read(&dev_priv->irq_received));
9862e600 500 for (i = 0; i < I915_NUM_RINGS; i++) {
da64c6fc 501 if (IS_GEN6(dev) || IS_GEN7(dev)) {
9862e600
CW		 502 seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
503 dev_priv->ring[i].name,
504 I915_READ_IMR(&dev_priv->ring[i]));
505 }
1ec14ad3 506 i915_ring_seqno_info(m, &dev_priv->ring[i]);
9862e600 507 }
de227ef0
CW		 508 mutex_unlock(&dev->struct_mutex);
509
2017263e
BG		 510 return 0;
511}
512
a6172a80
CW		 513static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
514{
515 struct drm_info_node *node = (struct drm_info_node *) m->private;
516 struct drm_device *dev = node->minor->dev;
517 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 518 int i, ret;
519
520 ret = mutex_lock_interruptible(&dev->struct_mutex);
521 if (ret)
522 return ret;
a6172a80
CW		 523
524 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
525 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
526 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 527 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 528
c2c347a9
CW		 529 seq_printf(m, "Fenced object[%2d] = ", i);
530 if (obj == NULL)
531 seq_printf(m, "unused");
532 else
05394f39 533 describe_obj(m, obj);
c2c347a9 534 seq_printf(m, "\n");
a6172a80
CW		 535 }
536
05394f39 537 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 538 return 0;
539}
540
2017263e
BG		 541static int i915_hws_info(struct seq_file *m, void *data)
542{
543 struct drm_info_node *node = (struct drm_info_node *) m->private;
544 struct drm_device *dev = node->minor->dev;
545 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 546 struct intel_ring_buffer *ring;
311bd68e 547 const volatile u32 __iomem *hws;
4066c0ae
CW		 548 int i;
549
1ec14ad3 550 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
311bd68e 551 hws = (volatile u32 __iomem *)ring->status_page.page_addr;
2017263e
BG		 552 if (hws == NULL)
553 return 0;
554
555 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
556 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
557 i * 4,
558 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
559 }
560 return 0;
561}
562
e5c65260
CW		 563static const char *ring_str(int ring)
564{
565 switch (ring) {
96154f2f
DV		 566 case RCS: return "render";
567 case VCS: return "bsd";
568 case BCS: return "blt";
e5c65260
CW		 569 default: return "";
570 }
571}
572
9df30794
CW		 573static const char *pin_flag(int pinned)
574{
575 if (pinned > 0)
576 return " P";
577 else if (pinned < 0)
578 return " p";
579 else
580 return "";
581}
582
583static const char *tiling_flag(int tiling)
584{
585 switch (tiling) {
586 default:
587 case I915_TILING_NONE: return "";
588 case I915_TILING_X: return " X";
589 case I915_TILING_Y: return " Y";
590 }
591}
592
593static const char *dirty_flag(int dirty)
594{
595 return dirty ? " dirty" : "";
596}
597
598static const char *purgeable_flag(int purgeable)
599{
600 return purgeable ? " purgeable" : "";
601}
602
c724e8a9
CW		 603static void print_error_buffers(struct seq_file *m,
604 const char *name,
605 struct drm_i915_error_buffer *err,
606 int count)
607{
608 seq_printf(m, "%s [%d]:\n", name, count);
609
610 while (count--) {
0201f1ec 611 seq_printf(m, " %08x %8u %04x %04x %x %x%s%s%s%s%s%s%s",
c724e8a9
CW		 612 err->gtt_offset,
613 err->size,
614 err->read_domains,
615 err->write_domain,
0201f1ec 616 err->rseqno, err->wseqno,
c724e8a9
CW		 617 pin_flag(err->pinned),
618 tiling_flag(err->tiling),
619 dirty_flag(err->dirty),
620 purgeable_flag(err->purgeable),
96154f2f 621 err->ring != -1 ? " " : "",
a779e5ab 622 ring_str(err->ring),
93dfb40c 623 cache_level_str(err->cache_level));
c724e8a9
CW		 624
625 if (err->name)
626 seq_printf(m, " (name: %d)", err->name);
627 if (err->fence_reg != I915_FENCE_REG_NONE)
628 seq_printf(m, " (fence: %d)", err->fence_reg);
629
630 seq_printf(m, "\n");
631 err++;
632 }
633}
634
d27b1e0e
DV		 635static void i915_ring_error_state(struct seq_file *m,
636 struct drm_device *dev,
637 struct drm_i915_error_state *error,
638 unsigned ring)
639{
ec34a01d 640 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
d27b1e0e 641 seq_printf(m, "%s command stream:\n", ring_str(ring));
c1cd90ed
DV		 642 seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
643 seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
d27b1e0e
DV		 644 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
645 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
646 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
647 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
c1cd90ed
DV		 648 if (ring == RCS && INTEL_INFO(dev)->gen >= 4) {
649 seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
650 seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
d27b1e0e 651 }
c1cd90ed
DV		 652 if (INTEL_INFO(dev)->gen >= 4)
653 seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
654 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
9d2f41fa 655 seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
33f3f518 656 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 657 seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
33f3f518 658 seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
7e3b8737
DV		 659 seq_printf(m, " SYNC_0: 0x%08x\n",
660 error->semaphore_mboxes[ring][0]);
661 seq_printf(m, " SYNC_1: 0x%08x\n",
662 error->semaphore_mboxes[ring][1]);
33f3f518 663 }
d27b1e0e 664 seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
9574b3fe 665 seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
7e3b8737
DV		 666 seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
667 seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
d27b1e0e
DV		 668}
669
d5442303
DV		 670struct i915_error_state_file_priv {
671 struct drm_device *dev;
672 struct drm_i915_error_state *error;
673};
674
63eeaf38
JB		 675static int i915_error_state(struct seq_file *m, void *unused)
676{
d5442303
DV		 677 struct i915_error_state_file_priv *error_priv = m->private;
678 struct drm_device *dev = error_priv->dev;
63eeaf38 679 drm_i915_private_t *dev_priv = dev->dev_private;
d5442303 680 struct drm_i915_error_state *error = error_priv->error;
b4519513 681 struct intel_ring_buffer *ring;
52d39a21 682 int i, j, page, offset, elt;
63eeaf38 683
742cbee8 684 if (!error) {
63eeaf38 685 seq_printf(m, "no error state collected\n");
742cbee8 686 return 0;
63eeaf38
JB		 687 }
688
8a905236
JB		 689 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
690 error->time.tv_usec);
9df30794 691 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
1d8f38f4 692 seq_printf(m, "EIR: 0x%08x\n", error->eir);
be998e2e 693 seq_printf(m, "IER: 0x%08x\n", error->ier);
1d8f38f4 694 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
b9a3906b 695 seq_printf(m, "CCID: 0x%08x\n", error->ccid);
9df30794 696
bf3301ab 697 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 698 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
699
33f3f518 700 if (INTEL_INFO(dev)->gen >= 6) {
d27b1e0e 701 seq_printf(m, "ERROR: 0x%08x\n", error->error);
33f3f518
DV		 702 seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
703 }
d27b1e0e 704
b4519513
CW		 705 for_each_ring(ring, dev_priv, i)
706 i915_ring_error_state(m, dev, error, i);
d27b1e0e 707
c724e8a9
CW		 708 if (error->active_bo)
709 print_error_buffers(m, "Active",
710 error->active_bo,
711 error->active_bo_count);
712
713 if (error->pinned_bo)
714 print_error_buffers(m, "Pinned",
715 error->pinned_bo,
716 error->pinned_bo_count);
9df30794 717
52d39a21
CW		 718 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
719 struct drm_i915_error_object *obj;
9df30794 720
52d39a21 721 if ((obj = error->ring[i].batchbuffer)) {
bcfb2e28
CW		 722 seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
723 dev_priv->ring[i].name,
724 obj->gtt_offset);
9df30794
CW		 725 offset = 0;
726 for (page = 0; page < obj->page_count; page++) {
727 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
728 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
729 offset += 4;
730 }
731 }
732 }
9df30794 733
52d39a21
CW		 734 if (error->ring[i].num_requests) {
735 seq_printf(m, "%s --- %d requests\n",
736 dev_priv->ring[i].name,
737 error->ring[i].num_requests);
738 for (j = 0; j < error->ring[i].num_requests; j++) {
ee4f42b1 739 seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
52d39a21 740 error->ring[i].requests[j].seqno,
ee4f42b1
CW		 741 error->ring[i].requests[j].jiffies,
742 error->ring[i].requests[j].tail);
52d39a21
CW		 743 }
744 }
745
746 if ((obj = error->ring[i].ringbuffer)) {
e2f973d5
CW		 747 seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
748 dev_priv->ring[i].name,
749 obj->gtt_offset);
750 offset = 0;
751 for (page = 0; page < obj->page_count; page++) {
752 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
753 seq_printf(m, "%08x : %08x\n",
754 offset,
755 obj->pages[page][elt]);
756 offset += 4;
757 }
9df30794
CW		 758 }
759 }
760 }
63eeaf38 761
6ef3d427
CW		 762 if (error->overlay)
763 intel_overlay_print_error_state(m, error->overlay);
764
c4a1d9e4
CW		 765 if (error->display)
766 intel_display_print_error_state(m, dev, error->display);
767
63eeaf38
JB		 768 return 0;
769}
6911a9b8 770
d5442303
DV		 771static ssize_t
772i915_error_state_write(struct file *filp,
773 const char __user *ubuf,
774 size_t cnt,
775 loff_t *ppos)
776{
777 struct seq_file *m = filp->private_data;
778 struct i915_error_state_file_priv *error_priv = m->private;
779 struct drm_device *dev = error_priv->dev;
22bcfc6a 780 int ret;
d5442303
DV		 781
782 DRM_DEBUG_DRIVER("Resetting error state\n");
783
22bcfc6a
DV		 784 ret = mutex_lock_interruptible(&dev->struct_mutex);
785 if (ret)
786 return ret;
787
d5442303
DV		 788 i915_destroy_error_state(dev);
789 mutex_unlock(&dev->struct_mutex);
790
791 return cnt;
792}
793
794static int i915_error_state_open(struct inode *inode, struct file *file)
795{
796 struct drm_device *dev = inode->i_private;
797 drm_i915_private_t *dev_priv = dev->dev_private;
798 struct i915_error_state_file_priv *error_priv;
799 unsigned long flags;
800
801 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
802 if (!error_priv)
803 return -ENOMEM;
804
805 error_priv->dev = dev;
806
807 spin_lock_irqsave(&dev_priv->error_lock, flags);
808 error_priv->error = dev_priv->first_error;
809 if (error_priv->error)
810 kref_get(&error_priv->error->ref);
811 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
812
813 return single_open(file, i915_error_state, error_priv);
814}
815
816static int i915_error_state_release(struct inode *inode, struct file *file)
817{
818 struct seq_file *m = file->private_data;
819 struct i915_error_state_file_priv *error_priv = m->private;
820
821 if (error_priv->error)
822 kref_put(&error_priv->error->ref, i915_error_state_free);
823 kfree(error_priv);
824
825 return single_release(inode, file);
826}
827
828static const struct file_operations i915_error_state_fops = {
829 .owner = THIS_MODULE,
830 .open = i915_error_state_open,
831 .read = seq_read,
832 .write = i915_error_state_write,
833 .llseek = default_llseek,
834 .release = i915_error_state_release,
835};
836
f97108d1
JB		 837static int i915_rstdby_delays(struct seq_file *m, void *unused)
838{
839 struct drm_info_node *node = (struct drm_info_node *) m->private;
840 struct drm_device *dev = node->minor->dev;
841 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 842 u16 crstanddelay;
843 int ret;
844
845 ret = mutex_lock_interruptible(&dev->struct_mutex);
846 if (ret)
847 return ret;
848
849 crstanddelay = I915_READ16(CRSTANDVID);
850
851 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 852
853 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
854
855 return 0;
856}
857
858static int i915_cur_delayinfo(struct seq_file *m, void *unused)
859{
860 struct drm_info_node *node = (struct drm_info_node *) m->private;
861 struct drm_device *dev = node->minor->dev;
862 drm_i915_private_t *dev_priv = dev->dev_private;
d1ebd816 863 int ret;
3b8d8d91
JB		 864
865 if (IS_GEN5(dev)) {
866 u16 rgvswctl = I915_READ16(MEMSWCTL);
867 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
868
869 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
870 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
871 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
872 MEMSTAT_VID_SHIFT);
873 seq_printf(m, "Current P-state: %d\n",
874 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1c70c0ce 875 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91
JB		 876 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
877 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
878 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
ccab5c82
JB		 879 u32 rpstat;
880 u32 rpupei, rpcurup, rpprevup;
881 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 882 int max_freq;
883
884 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 885 ret = mutex_lock_interruptible(&dev->struct_mutex);
886 if (ret)
887 return ret;
888
fcca7926 889 gen6_gt_force_wake_get(dev_priv);
3b8d8d91 890
ccab5c82
JB		 891 rpstat = I915_READ(GEN6_RPSTAT1);
892 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
893 rpcurup = I915_READ(GEN6_RP_CUR_UP);
894 rpprevup = I915_READ(GEN6_RP_PREV_UP);
895 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
896 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
897 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
898
d1ebd816
BW		 899 gen6_gt_force_wake_put(dev_priv);
900 mutex_unlock(&dev->struct_mutex);
901
3b8d8d91 902 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 903 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 904 seq_printf(m, "Render p-state ratio: %d\n",
905 (gt_perf_status & 0xff00) >> 8);
906 seq_printf(m, "Render p-state VID: %d\n",
907 gt_perf_status & 0xff);
908 seq_printf(m, "Render p-state limit: %d\n",
909 rp_state_limits & 0xff);
ccab5c82 910 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
e281fcaa 911 GEN6_CAGF_SHIFT) * 50);
ccab5c82
JB		 912 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
913 GEN6_CURICONT_MASK);
914 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
915 GEN6_CURBSYTAVG_MASK);
916 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
917 GEN6_CURBSYTAVG_MASK);
918 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
919 GEN6_CURIAVG_MASK);
920 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
921 GEN6_CURBSYTAVG_MASK);
922 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
923 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 924
925 max_freq = (rp_state_cap & 0xff0000) >> 16;
926 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
e281fcaa 927 max_freq * 50);
3b8d8d91
JB		 928
929 max_freq = (rp_state_cap & 0xff00) >> 8;
930 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
e281fcaa 931 max_freq * 50);
3b8d8d91
JB		 932
933 max_freq = rp_state_cap & 0xff;
934 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
e281fcaa 935 max_freq * 50);
3b8d8d91
JB		 936 } else {
937 seq_printf(m, "no P-state info available\n");
938 }
f97108d1
JB		 939
940 return 0;
941}
942
943static int i915_delayfreq_table(struct seq_file *m, void *unused)
944{
945 struct drm_info_node *node = (struct drm_info_node *) m->private;
946 struct drm_device *dev = node->minor->dev;
947 drm_i915_private_t *dev_priv = dev->dev_private;
948 u32 delayfreq;
616fdb5a
BW		 949 int ret, i;
950
951 ret = mutex_lock_interruptible(&dev->struct_mutex);
952 if (ret)
953 return ret;
f97108d1
JB		 954
955 for (i = 0; i < 16; i++) {
956 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 957 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
958 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 959 }
960
616fdb5a
BW		 961 mutex_unlock(&dev->struct_mutex);
962
f97108d1
JB		 963 return 0;
964}
965
966static inline int MAP_TO_MV(int map)
967{
968 return 1250 - (map * 25);
969}
970
971static int i915_inttoext_table(struct seq_file *m, void *unused)
972{
973 struct drm_info_node *node = (struct drm_info_node *) m->private;
974 struct drm_device *dev = node->minor->dev;
975 drm_i915_private_t *dev_priv = dev->dev_private;
976 u32 inttoext;
616fdb5a
BW		 977 int ret, i;
978
979 ret = mutex_lock_interruptible(&dev->struct_mutex);
980 if (ret)
981 return ret;
f97108d1
JB		 982
983 for (i = 1; i <= 32; i++) {
984 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
985 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
986 }
987
616fdb5a
BW		 988 mutex_unlock(&dev->struct_mutex);
989
f97108d1
JB		 990 return 0;
991}
992
4d85529d 993static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 994{
995 struct drm_info_node *node = (struct drm_info_node *) m->private;
996 struct drm_device *dev = node->minor->dev;
997 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 998 u32 rgvmodectl, rstdbyctl;
999 u16 crstandvid;
1000 int ret;
1001
1002 ret = mutex_lock_interruptible(&dev->struct_mutex);
1003 if (ret)
1004 return ret;
1005
1006 rgvmodectl = I915_READ(MEMMODECTL);
1007 rstdbyctl = I915_READ(RSTDBYCTL);
1008 crstandvid = I915_READ16(CRSTANDVID);
1009
1010 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1011
1012 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1013 "yes" : "no");
1014 seq_printf(m, "Boost freq: %d\n",
1015 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1016 MEMMODE_BOOST_FREQ_SHIFT);
1017 seq_printf(m, "HW control enabled: %s\n",
1018 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1019 seq_printf(m, "SW control enabled: %s\n",
1020 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1021 seq_printf(m, "Gated voltage change: %s\n",
1022 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1023 seq_printf(m, "Starting frequency: P%d\n",
1024 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1025 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1026 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1027 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1028 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1029 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1030 seq_printf(m, "Render standby enabled: %s\n",
1031 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
88271da3
JB		 1032 seq_printf(m, "Current RS state: ");
1033 switch (rstdbyctl & RSX_STATUS_MASK) {
1034 case RSX_STATUS_ON:
1035 seq_printf(m, "on\n");
1036 break;
1037 case RSX_STATUS_RC1:
1038 seq_printf(m, "RC1\n");
1039 break;
1040 case RSX_STATUS_RC1E:
1041 seq_printf(m, "RC1E\n");
1042 break;
1043 case RSX_STATUS_RS1:
1044 seq_printf(m, "RS1\n");
1045 break;
1046 case RSX_STATUS_RS2:
1047 seq_printf(m, "RS2 (RC6)\n");
1048 break;
1049 case RSX_STATUS_RS3:
1050 seq_printf(m, "RC3 (RC6+)\n");
1051 break;
1052 default:
1053 seq_printf(m, "unknown\n");
1054 break;
1055 }
f97108d1
JB		 1056
1057 return 0;
1058}
1059
4d85529d
BW		 1060static int gen6_drpc_info(struct seq_file *m)
1061{
1062
1063 struct drm_info_node *node = (struct drm_info_node *) m->private;
1064 struct drm_device *dev = node->minor->dev;
1065 struct drm_i915_private *dev_priv = dev->dev_private;
1066 u32 rpmodectl1, gt_core_status, rcctl1;
93b525dc 1067 unsigned forcewake_count;
4d85529d
BW		 1068 int count=0, ret;
1069
1070
1071 ret = mutex_lock_interruptible(&dev->struct_mutex);
1072 if (ret)
1073 return ret;
1074
93b525dc
DV		 1075 spin_lock_irq(&dev_priv->gt_lock);
1076 forcewake_count = dev_priv->forcewake_count;
1077 spin_unlock_irq(&dev_priv->gt_lock);
1078
1079 if (forcewake_count) {
1080 seq_printf(m, "RC information inaccurate because somebody "
1081 "holds a forcewake reference \n");
4d85529d
BW		 1082 } else {
1083 /* NB: we cannot use forcewake, else we read the wrong values */
1084 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1085 udelay(10);
1086 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1087 }
1088
1089 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1090 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1091
1092 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1093 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1094 mutex_unlock(&dev->struct_mutex);
1095
1096 seq_printf(m, "Video Turbo Mode: %s\n",
1097 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1098 seq_printf(m, "HW control enabled: %s\n",
1099 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1100 seq_printf(m, "SW control enabled: %s\n",
1101 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1102 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1103 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1104 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1105 seq_printf(m, "RC6 Enabled: %s\n",
1106 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1107 seq_printf(m, "Deep RC6 Enabled: %s\n",
1108 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1109 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1110 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1111 seq_printf(m, "Current RC state: ");
1112 switch (gt_core_status & GEN6_RCn_MASK) {
1113 case GEN6_RC0:
1114 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1115 seq_printf(m, "Core Power Down\n");
1116 else
1117 seq_printf(m, "on\n");
1118 break;
1119 case GEN6_RC3:
1120 seq_printf(m, "RC3\n");
1121 break;
1122 case GEN6_RC6:
1123 seq_printf(m, "RC6\n");
1124 break;
1125 case GEN6_RC7:
1126 seq_printf(m, "RC7\n");
1127 break;
1128 default:
1129 seq_printf(m, "Unknown\n");
1130 break;
1131 }
1132
1133 seq_printf(m, "Core Power Down: %s\n",
1134 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1135
1136 /* Not exactly sure what this is */
1137 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1138 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1139 seq_printf(m, "RC6 residency since boot: %u\n",
1140 I915_READ(GEN6_GT_GFX_RC6));
1141 seq_printf(m, "RC6+ residency since boot: %u\n",
1142 I915_READ(GEN6_GT_GFX_RC6p));
1143 seq_printf(m, "RC6++ residency since boot: %u\n",
1144 I915_READ(GEN6_GT_GFX_RC6pp));
1145
4d85529d
BW		 1146 return 0;
1147}
1148
1149static int i915_drpc_info(struct seq_file *m, void *unused)
1150{
1151 struct drm_info_node *node = (struct drm_info_node *) m->private;
1152 struct drm_device *dev = node->minor->dev;
1153
1154 if (IS_GEN6(dev) || IS_GEN7(dev))
1155 return gen6_drpc_info(m);
1156 else
1157 return ironlake_drpc_info(m);
1158}
1159
b5e50c3f
JB		 1160static int i915_fbc_status(struct seq_file *m, void *unused)
1161{
1162 struct drm_info_node *node = (struct drm_info_node *) m->private;
1163 struct drm_device *dev = node->minor->dev;
b5e50c3f 1164 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1165
ee5382ae 1166 if (!I915_HAS_FBC(dev)) {
b5e50c3f
JB		 1167 seq_printf(m, "FBC unsupported on this chipset\n");
1168 return 0;
1169 }
1170
ee5382ae 1171 if (intel_fbc_enabled(dev)) {
b5e50c3f
JB		 1172 seq_printf(m, "FBC enabled\n");
1173 } else {
1174 seq_printf(m, "FBC disabled: ");
1175 switch (dev_priv->no_fbc_reason) {
bed4a673
CW		 1176 case FBC_NO_OUTPUT:
1177 seq_printf(m, "no outputs");
1178 break;
b5e50c3f
JB		 1179 case FBC_STOLEN_TOO_SMALL:
1180 seq_printf(m, "not enough stolen memory");
1181 break;
1182 case FBC_UNSUPPORTED_MODE:
1183 seq_printf(m, "mode not supported");
1184 break;
1185 case FBC_MODE_TOO_LARGE:
1186 seq_printf(m, "mode too large");
1187 break;
1188 case FBC_BAD_PLANE:
1189 seq_printf(m, "FBC unsupported on plane");
1190 break;
1191 case FBC_NOT_TILED:
1192 seq_printf(m, "scanout buffer not tiled");
1193 break;
9c928d16
JB		 1194 case FBC_MULTIPLE_PIPES:
1195 seq_printf(m, "multiple pipes are enabled");
1196 break;
c1a9f047
JB		 1197 case FBC_MODULE_PARAM:
1198 seq_printf(m, "disabled per module param (default off)");
1199 break;
b5e50c3f
JB		 1200 default:
1201 seq_printf(m, "unknown reason");
1202 }
1203 seq_printf(m, "\n");
1204 }
1205 return 0;
1206}
1207
4a9bef37
JB		 1208static int i915_sr_status(struct seq_file *m, void *unused)
1209{
1210 struct drm_info_node *node = (struct drm_info_node *) m->private;
1211 struct drm_device *dev = node->minor->dev;
1212 drm_i915_private_t *dev_priv = dev->dev_private;
1213 bool sr_enabled = false;
1214
1398261a 1215 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1216 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1217 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1218 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1219 else if (IS_I915GM(dev))
1220 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1221 else if (IS_PINEVIEW(dev))
1222 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1223
5ba2aaaa
CW		 1224 seq_printf(m, "self-refresh: %s\n",
1225 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1226
1227 return 0;
1228}
1229
7648fa99
JB		 1230static int i915_emon_status(struct seq_file *m, void *unused)
1231{
1232 struct drm_info_node *node = (struct drm_info_node *) m->private;
1233 struct drm_device *dev = node->minor->dev;
1234 drm_i915_private_t *dev_priv = dev->dev_private;
1235 unsigned long temp, chipset, gfx;
de227ef0
CW		 1236 int ret;
1237
582be6b4
CW		 1238 if (!IS_GEN5(dev))
1239 return -ENODEV;
1240
de227ef0
CW		 1241 ret = mutex_lock_interruptible(&dev->struct_mutex);
1242 if (ret)
1243 return ret;
7648fa99
JB		 1244
1245 temp = i915_mch_val(dev_priv);
1246 chipset = i915_chipset_val(dev_priv);
1247 gfx = i915_gfx_val(dev_priv);
de227ef0 1248 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1249
1250 seq_printf(m, "GMCH temp: %ld\n", temp);
1251 seq_printf(m, "Chipset power: %ld\n", chipset);
1252 seq_printf(m, "GFX power: %ld\n", gfx);
1253 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1254
1255 return 0;
1256}
1257
23b2f8bb
JB		 1258static int i915_ring_freq_table(struct seq_file *m, void *unused)
1259{
1260 struct drm_info_node *node = (struct drm_info_node *) m->private;
1261 struct drm_device *dev = node->minor->dev;
1262 drm_i915_private_t *dev_priv = dev->dev_private;
1263 int ret;
1264 int gpu_freq, ia_freq;
1265
1c70c0ce 1266 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
23b2f8bb
JB		 1267 seq_printf(m, "unsupported on this chipset\n");
1268 return 0;
1269 }
1270
1271 ret = mutex_lock_interruptible(&dev->struct_mutex);
1272 if (ret)
1273 return ret;
1274
1275 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1276
c6a828d3
DV		 1277 for (gpu_freq = dev_priv->rps.min_delay;
1278 gpu_freq <= dev_priv->rps.max_delay;
23b2f8bb
JB		 1279 gpu_freq++) {
1280 I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
1281 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
1282 GEN6_PCODE_READ_MIN_FREQ_TABLE);
1283 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
1284 GEN6_PCODE_READY) == 0, 10)) {
1285 DRM_ERROR("pcode read of freq table timed out\n");
1286 continue;
1287 }
1288 ia_freq = I915_READ(GEN6_PCODE_DATA);
1289 seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
1290 }
1291
1292 mutex_unlock(&dev->struct_mutex);
1293
1294 return 0;
1295}
1296
7648fa99
JB		 1297static int i915_gfxec(struct seq_file *m, void *unused)
1298{
1299 struct drm_info_node *node = (struct drm_info_node *) m->private;
1300 struct drm_device *dev = node->minor->dev;
1301 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1302 int ret;
1303
1304 ret = mutex_lock_interruptible(&dev->struct_mutex);
1305 if (ret)
1306 return ret;
7648fa99
JB		 1307
1308 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1309
616fdb5a
BW		 1310 mutex_unlock(&dev->struct_mutex);
1311
7648fa99
JB		 1312 return 0;
1313}
1314
44834a67
CW		 1315static int i915_opregion(struct seq_file *m, void *unused)
1316{
1317 struct drm_info_node *node = (struct drm_info_node *) m->private;
1318 struct drm_device *dev = node->minor->dev;
1319 drm_i915_private_t *dev_priv = dev->dev_private;
1320 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1321 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1322 int ret;
1323
0d38f009
DV		 1324 if (data == NULL)
1325 return -ENOMEM;
1326
44834a67
CW		 1327 ret = mutex_lock_interruptible(&dev->struct_mutex);
1328 if (ret)
0d38f009 1329 goto out;
44834a67 1330
0d38f009
DV		 1331 if (opregion->header) {
1332 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1333 seq_write(m, data, OPREGION_SIZE);
1334 }
44834a67
CW		 1335
1336 mutex_unlock(&dev->struct_mutex);
1337
0d38f009
DV		 1338out:
1339 kfree(data);
44834a67
CW		 1340 return 0;
1341}
1342
37811fcc
CW		 1343static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1344{
1345 struct drm_info_node *node = (struct drm_info_node *) m->private;
1346 struct drm_device *dev = node->minor->dev;
1347 drm_i915_private_t *dev_priv = dev->dev_private;
1348 struct intel_fbdev *ifbdev;
1349 struct intel_framebuffer *fb;
1350 int ret;
1351
1352 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1353 if (ret)
1354 return ret;
1355
1356 ifbdev = dev_priv->fbdev;
1357 fb = to_intel_framebuffer(ifbdev->helper.fb);
1358
1359 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1360 fb->base.width,
1361 fb->base.height,
1362 fb->base.depth,
1363 fb->base.bits_per_pixel);
05394f39 1364 describe_obj(m, fb->obj);
37811fcc
CW		 1365 seq_printf(m, "\n");
1366
1367 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1368 if (&fb->base == ifbdev->helper.fb)
1369 continue;
1370
1371 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1372 fb->base.width,
1373 fb->base.height,
1374 fb->base.depth,
1375 fb->base.bits_per_pixel);
05394f39 1376 describe_obj(m, fb->obj);
37811fcc
CW		 1377 seq_printf(m, "\n");
1378 }
1379
1380 mutex_unlock(&dev->mode_config.mutex);
1381
1382 return 0;
1383}
1384
e76d3630
BW		 1385static int i915_context_status(struct seq_file *m, void *unused)
1386{
1387 struct drm_info_node *node = (struct drm_info_node *) m->private;
1388 struct drm_device *dev = node->minor->dev;
1389 drm_i915_private_t *dev_priv = dev->dev_private;
1390 int ret;
1391
1392 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1393 if (ret)
1394 return ret;
1395
dc501fbc
BW		 1396 if (dev_priv->pwrctx) {
1397 seq_printf(m, "power context ");
1398 describe_obj(m, dev_priv->pwrctx);
1399 seq_printf(m, "\n");
1400 }
e76d3630 1401
dc501fbc
BW		 1402 if (dev_priv->renderctx) {
1403 seq_printf(m, "render context ");
1404 describe_obj(m, dev_priv->renderctx);
1405 seq_printf(m, "\n");
1406 }
e76d3630
BW		 1407
1408 mutex_unlock(&dev->mode_config.mutex);
1409
1410 return 0;
1411}
1412
6d794d42
BW		 1413static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1414{
1415 struct drm_info_node *node = (struct drm_info_node *) m->private;
1416 struct drm_device *dev = node->minor->dev;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
9f1f46a4 1418 unsigned forcewake_count;
6d794d42 1419
9f1f46a4
DV		 1420 spin_lock_irq(&dev_priv->gt_lock);
1421 forcewake_count = dev_priv->forcewake_count;
1422 spin_unlock_irq(&dev_priv->gt_lock);
6d794d42 1423
9f1f46a4 1424 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1425
1426 return 0;
1427}
1428
ea16a3cd
DV		 1429static const char *swizzle_string(unsigned swizzle)
1430{
1431 switch(swizzle) {
1432 case I915_BIT_6_SWIZZLE_NONE:
1433 return "none";
1434 case I915_BIT_6_SWIZZLE_9:
1435 return "bit9";
1436 case I915_BIT_6_SWIZZLE_9_10:
1437 return "bit9/bit10";
1438 case I915_BIT_6_SWIZZLE_9_11:
1439 return "bit9/bit11";
1440 case I915_BIT_6_SWIZZLE_9_10_11:
1441 return "bit9/bit10/bit11";
1442 case I915_BIT_6_SWIZZLE_9_17:
1443 return "bit9/bit17";
1444 case I915_BIT_6_SWIZZLE_9_10_17:
1445 return "bit9/bit10/bit17";
1446 case I915_BIT_6_SWIZZLE_UNKNOWN:
1447 return "unkown";
1448 }
1449
1450 return "bug";
1451}
1452
1453static int i915_swizzle_info(struct seq_file *m, void *data)
1454{
1455 struct drm_info_node *node = (struct drm_info_node *) m->private;
1456 struct drm_device *dev = node->minor->dev;
1457 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1458 int ret;
1459
1460 ret = mutex_lock_interruptible(&dev->struct_mutex);
1461 if (ret)
1462 return ret;
ea16a3cd 1463
ea16a3cd
DV		 1464 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1465 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1466 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1467 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1468
1469 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1470 seq_printf(m, "DDC = 0x%08x\n",
1471 I915_READ(DCC));
1472 seq_printf(m, "C0DRB3 = 0x%04x\n",
1473 I915_READ16(C0DRB3));
1474 seq_printf(m, "C1DRB3 = 0x%04x\n",
1475 I915_READ16(C1DRB3));
3fa7d235
DV		 1476 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1477 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1478 I915_READ(MAD_DIMM_C0));
1479 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1480 I915_READ(MAD_DIMM_C1));
1481 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1482 I915_READ(MAD_DIMM_C2));
1483 seq_printf(m, "TILECTL = 0x%08x\n",
1484 I915_READ(TILECTL));
1485 seq_printf(m, "ARB_MODE = 0x%08x\n",
1486 I915_READ(ARB_MODE));
1487 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1488 I915_READ(DISP_ARB_CTL));
ea16a3cd
DV		 1489 }
1490 mutex_unlock(&dev->struct_mutex);
1491
1492 return 0;
1493}
1494
3cf17fc5
DV		 1495static int i915_ppgtt_info(struct seq_file *m, void *data)
1496{
1497 struct drm_info_node *node = (struct drm_info_node *) m->private;
1498 struct drm_device *dev = node->minor->dev;
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 struct intel_ring_buffer *ring;
1501 int i, ret;
1502
1503
1504 ret = mutex_lock_interruptible(&dev->struct_mutex);
1505 if (ret)
1506 return ret;
1507 if (INTEL_INFO(dev)->gen == 6)
1508 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1509
1510 for (i = 0; i < I915_NUM_RINGS; i++) {
1511 ring = &dev_priv->ring[i];
1512
1513 seq_printf(m, "%s\n", ring->name);
1514 if (INTEL_INFO(dev)->gen == 7)
1515 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1516 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1517 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1518 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1519 }
1520 if (dev_priv->mm.aliasing_ppgtt) {
1521 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1522
1523 seq_printf(m, "aliasing PPGTT:\n");
1524 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1525 }
1526 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1527 mutex_unlock(&dev->struct_mutex);
1528
1529 return 0;
1530}
1531
57f350b6
JB		 1532static int i915_dpio_info(struct seq_file *m, void *data)
1533{
1534 struct drm_info_node *node = (struct drm_info_node *) m->private;
1535 struct drm_device *dev = node->minor->dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 int ret;
1538
1539
1540 if (!IS_VALLEYVIEW(dev)) {
1541 seq_printf(m, "unsupported\n");
1542 return 0;
1543 }
1544
1545 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1546 if (ret)
1547 return ret;
1548
1549 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1550
1551 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1552 intel_dpio_read(dev_priv, _DPIO_DIV_A));
1553 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1554 intel_dpio_read(dev_priv, _DPIO_DIV_B));
1555
1556 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1557 intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
1558 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1559 intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
1560
1561 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1562 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1563 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1564 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1565
1566 seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
1567 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
1568 seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
1569 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
1570
1571 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1572 intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1573
1574 mutex_unlock(&dev->mode_config.mutex);
1575
1576 return 0;
1577}
1578
f3cd474b
CW		 1579static ssize_t
1580i915_wedged_read(struct file *filp,
1581 char __user *ubuf,
1582 size_t max,
1583 loff_t *ppos)
1584{
1585 struct drm_device *dev = filp->private_data;
1586 drm_i915_private_t *dev_priv = dev->dev_private;
1587 char buf[80];
1588 int len;
1589
0206e353 1590 len = snprintf(buf, sizeof(buf),
f3cd474b
CW		 1591 "wedged : %d\n",
1592 atomic_read(&dev_priv->mm.wedged));
1593
0206e353
AJ		 1594 if (len > sizeof(buf))
1595 len = sizeof(buf);
f4433a8d 1596
f3cd474b
CW		 1597 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1598}
1599
1600static ssize_t
1601i915_wedged_write(struct file *filp,
1602 const char __user *ubuf,
1603 size_t cnt,
1604 loff_t *ppos)
1605{
1606 struct drm_device *dev = filp->private_data;
f3cd474b
CW		 1607 char buf[20];
1608 int val = 1;
1609
1610 if (cnt > 0) {
0206e353 1611 if (cnt > sizeof(buf) - 1)
f3cd474b
CW		 1612 return -EINVAL;
1613
1614 if (copy_from_user(buf, ubuf, cnt))
1615 return -EFAULT;
1616 buf[cnt] = 0;
1617
1618 val = simple_strtoul(buf, NULL, 0);
1619 }
1620
1621 DRM_INFO("Manually setting wedged to %d\n", val);
527f9e90 1622 i915_handle_error(dev, val);
f3cd474b
CW		 1623
1624 return cnt;
1625}
1626
1627static const struct file_operations i915_wedged_fops = {
1628 .owner = THIS_MODULE,
234e3405 1629 .open = simple_open,
f3cd474b
CW		 1630 .read = i915_wedged_read,
1631 .write = i915_wedged_write,
6038f373 1632 .llseek = default_llseek,
f3cd474b
CW		 1633};
1634
e5eb3d63
DV		 1635static ssize_t
1636i915_ring_stop_read(struct file *filp,
1637 char __user *ubuf,
1638 size_t max,
1639 loff_t *ppos)
1640{
1641 struct drm_device *dev = filp->private_data;
1642 drm_i915_private_t *dev_priv = dev->dev_private;
1643 char buf[20];
1644 int len;
1645
1646 len = snprintf(buf, sizeof(buf),
1647 "0x%08x\n", dev_priv->stop_rings);
1648
1649 if (len > sizeof(buf))
1650 len = sizeof(buf);
1651
1652 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1653}
1654
1655static ssize_t
1656i915_ring_stop_write(struct file *filp,
1657 const char __user *ubuf,
1658 size_t cnt,
1659 loff_t *ppos)
1660{
1661 struct drm_device *dev = filp->private_data;
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 char buf[20];
22bcfc6a 1664 int val = 0, ret;
e5eb3d63
DV		 1665
1666 if (cnt > 0) {
1667 if (cnt > sizeof(buf) - 1)
1668 return -EINVAL;
1669
1670 if (copy_from_user(buf, ubuf, cnt))
1671 return -EFAULT;
1672 buf[cnt] = 0;
1673
1674 val = simple_strtoul(buf, NULL, 0);
1675 }
1676
1677 DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val);
1678
22bcfc6a
DV		 1679 ret = mutex_lock_interruptible(&dev->struct_mutex);
1680 if (ret)
1681 return ret;
1682
e5eb3d63
DV		 1683 dev_priv->stop_rings = val;
1684 mutex_unlock(&dev->struct_mutex);
1685
1686 return cnt;
1687}
1688
1689static const struct file_operations i915_ring_stop_fops = {
1690 .owner = THIS_MODULE,
1691 .open = simple_open,
1692 .read = i915_ring_stop_read,
1693 .write = i915_ring_stop_write,
1694 .llseek = default_llseek,
1695};
d5442303 1696
358733e9
JB		 1697static ssize_t
1698i915_max_freq_read(struct file *filp,
1699 char __user *ubuf,
1700 size_t max,
1701 loff_t *ppos)
1702{
1703 struct drm_device *dev = filp->private_data;
1704 drm_i915_private_t *dev_priv = dev->dev_private;
1705 char buf[80];
004777cb
DV		 1706 int len, ret;
1707
1708 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1709 return -ENODEV;
1710
1711 ret = mutex_lock_interruptible(&dev->struct_mutex);
1712 if (ret)
1713 return ret;
358733e9 1714
0206e353 1715 len = snprintf(buf, sizeof(buf),
c6a828d3 1716 "max freq: %d\n", dev_priv->rps.max_delay * 50);
004777cb 1717 mutex_unlock(&dev->struct_mutex);
358733e9 1718
0206e353
AJ		 1719 if (len > sizeof(buf))
1720 len = sizeof(buf);
358733e9
JB		 1721
1722 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1723}
1724
1725static ssize_t
1726i915_max_freq_write(struct file *filp,
1727 const char __user *ubuf,
1728 size_t cnt,
1729 loff_t *ppos)
1730{
1731 struct drm_device *dev = filp->private_data;
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733 char buf[20];
004777cb
DV		 1734 int val = 1, ret;
1735
1736 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1737 return -ENODEV;
358733e9
JB		 1738
1739 if (cnt > 0) {
0206e353 1740 if (cnt > sizeof(buf) - 1)
358733e9
JB		 1741 return -EINVAL;
1742
1743 if (copy_from_user(buf, ubuf, cnt))
1744 return -EFAULT;
1745 buf[cnt] = 0;
1746
1747 val = simple_strtoul(buf, NULL, 0);
1748 }
1749
1750 DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
1751
004777cb
DV		 1752 ret = mutex_lock_interruptible(&dev->struct_mutex);
1753 if (ret)
1754 return ret;
1755
358733e9
JB		 1756 /*
1757 * Turbo will still be enabled, but won't go above the set value.
1758 */
c6a828d3 1759 dev_priv->rps.max_delay = val / 50;
358733e9
JB		 1760
1761 gen6_set_rps(dev, val / 50);
004777cb 1762 mutex_unlock(&dev->struct_mutex);
358733e9
JB		 1763
1764 return cnt;
1765}
1766
1767static const struct file_operations i915_max_freq_fops = {
1768 .owner = THIS_MODULE,
234e3405 1769 .open = simple_open,
358733e9
JB		 1770 .read = i915_max_freq_read,
1771 .write = i915_max_freq_write,
1772 .llseek = default_llseek,
1773};
1774
1523c310
JB		 1775static ssize_t
1776i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max,
1777 loff_t *ppos)
1778{
1779 struct drm_device *dev = filp->private_data;
1780 drm_i915_private_t *dev_priv = dev->dev_private;
1781 char buf[80];
004777cb
DV		 1782 int len, ret;
1783
1784 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1785 return -ENODEV;
1786
1787 ret = mutex_lock_interruptible(&dev->struct_mutex);
1788 if (ret)
1789 return ret;
1523c310
JB		 1790
1791 len = snprintf(buf, sizeof(buf),
c6a828d3 1792 "min freq: %d\n", dev_priv->rps.min_delay * 50);
004777cb 1793 mutex_unlock(&dev->struct_mutex);
1523c310
JB		 1794
1795 if (len > sizeof(buf))
1796 len = sizeof(buf);
1797
1798 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1799}
1800
1801static ssize_t
1802i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt,
1803 loff_t *ppos)
1804{
1805 struct drm_device *dev = filp->private_data;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 char buf[20];
004777cb
DV		 1808 int val = 1, ret;
1809
1810 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1811 return -ENODEV;
1523c310
JB		 1812
1813 if (cnt > 0) {
1814 if (cnt > sizeof(buf) - 1)
1815 return -EINVAL;
1816
1817 if (copy_from_user(buf, ubuf, cnt))
1818 return -EFAULT;
1819 buf[cnt] = 0;
1820
1821 val = simple_strtoul(buf, NULL, 0);
1822 }
1823
1824 DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val);
1825
004777cb
DV		 1826 ret = mutex_lock_interruptible(&dev->struct_mutex);
1827 if (ret)
1828 return ret;
1829
1523c310
JB		 1830 /*
1831 * Turbo will still be enabled, but won't go below the set value.
1832 */
c6a828d3 1833 dev_priv->rps.min_delay = val / 50;
1523c310
JB		 1834
1835 gen6_set_rps(dev, val / 50);
004777cb 1836 mutex_unlock(&dev->struct_mutex);
1523c310
JB		 1837
1838 return cnt;
1839}
1840
1841static const struct file_operations i915_min_freq_fops = {
1842 .owner = THIS_MODULE,
1843 .open = simple_open,
1844 .read = i915_min_freq_read,
1845 .write = i915_min_freq_write,
1846 .llseek = default_llseek,
1847};
1848
07b7ddd9
JB		 1849static ssize_t
1850i915_cache_sharing_read(struct file *filp,
1851 char __user *ubuf,
1852 size_t max,
1853 loff_t *ppos)
1854{
1855 struct drm_device *dev = filp->private_data;
1856 drm_i915_private_t *dev_priv = dev->dev_private;
1857 char buf[80];
1858 u32 snpcr;
22bcfc6a 1859 int len, ret;
07b7ddd9 1860
004777cb
DV		 1861 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1862 return -ENODEV;
1863
22bcfc6a
DV		 1864 ret = mutex_lock_interruptible(&dev->struct_mutex);
1865 if (ret)
1866 return ret;
1867
07b7ddd9
JB		 1868 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1869 mutex_unlock(&dev_priv->dev->struct_mutex);
1870
0206e353 1871 len = snprintf(buf, sizeof(buf),
07b7ddd9
JB		 1872 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
1873 GEN6_MBC_SNPCR_SHIFT);
1874
0206e353
AJ		 1875 if (len > sizeof(buf))
1876 len = sizeof(buf);
07b7ddd9
JB		 1877
1878 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1879}
1880
1881static ssize_t
1882i915_cache_sharing_write(struct file *filp,
1883 const char __user *ubuf,
1884 size_t cnt,
1885 loff_t *ppos)
1886{
1887 struct drm_device *dev = filp->private_data;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 char buf[20];
1890 u32 snpcr;
1891 int val = 1;
1892
004777cb
DV		 1893 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1894 return -ENODEV;
1895
07b7ddd9 1896 if (cnt > 0) {
0206e353 1897 if (cnt > sizeof(buf) - 1)
07b7ddd9
JB		 1898 return -EINVAL;
1899
1900 if (copy_from_user(buf, ubuf, cnt))
1901 return -EFAULT;
1902 buf[cnt] = 0;
1903
1904 val = simple_strtoul(buf, NULL, 0);
1905 }
1906
1907 if (val < 0 || val > 3)
1908 return -EINVAL;
1909
1910 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
1911
1912 /* Update the cache sharing policy here as well */
1913 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1914 snpcr &= ~GEN6_MBC_SNPCR_MASK;
1915 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
1916 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1917
1918 return cnt;
1919}
1920
1921static const struct file_operations i915_cache_sharing_fops = {
1922 .owner = THIS_MODULE,
234e3405 1923 .open = simple_open,
07b7ddd9
JB		 1924 .read = i915_cache_sharing_read,
1925 .write = i915_cache_sharing_write,
1926 .llseek = default_llseek,
1927};
1928
f3cd474b
CW		 1929/* As the drm_debugfs_init() routines are called before dev->dev_private is
1930 * allocated we need to hook into the minor for release. */
1931static int
1932drm_add_fake_info_node(struct drm_minor *minor,
1933 struct dentry *ent,
1934 const void *key)
1935{
1936 struct drm_info_node *node;
1937
1938 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
1939 if (node == NULL) {
1940 debugfs_remove(ent);
1941 return -ENOMEM;
1942 }
1943
1944 node->minor = minor;
1945 node->dent = ent;
1946 node->info_ent = (void *) key;
b3e067c0
MS		 1947
1948 mutex_lock(&minor->debugfs_lock);
1949 list_add(&node->list, &minor->debugfs_list);
1950 mutex_unlock(&minor->debugfs_lock);
f3cd474b
CW		 1951
1952 return 0;
1953}
1954
6d794d42
BW		 1955static int i915_forcewake_open(struct inode *inode, struct file *file)
1956{
1957 struct drm_device *dev = inode->i_private;
1958 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 1959
075edca4 1960 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 1961 return 0;
1962
6d794d42 1963 gen6_gt_force_wake_get(dev_priv);
6d794d42
BW		 1964
1965 return 0;
1966}
1967
c43b5634 1968static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 1969{
1970 struct drm_device *dev = inode->i_private;
1971 struct drm_i915_private *dev_priv = dev->dev_private;
1972
075edca4 1973 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 1974 return 0;
1975
6d794d42 1976 gen6_gt_force_wake_put(dev_priv);
6d794d42
BW		 1977
1978 return 0;
1979}
1980
1981static const struct file_operations i915_forcewake_fops = {
1982 .owner = THIS_MODULE,
1983 .open = i915_forcewake_open,
1984 .release = i915_forcewake_release,
1985};
1986
1987static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
1988{
1989 struct drm_device *dev = minor->dev;
1990 struct dentry *ent;
1991
1992 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 1993 S_IRUSR,
6d794d42
BW		 1994 root, dev,
1995 &i915_forcewake_fops);
1996 if (IS_ERR(ent))
1997 return PTR_ERR(ent);
1998
8eb57294 1999 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 2000}
2001
6a9c308d
DV		 2002static int i915_debugfs_create(struct dentry *root,
2003 struct drm_minor *minor,
2004 const char *name,
2005 const struct file_operations *fops)
07b7ddd9
JB		 2006{
2007 struct drm_device *dev = minor->dev;
2008 struct dentry *ent;
2009
6a9c308d 2010 ent = debugfs_create_file(name,
07b7ddd9
JB		 2011 S_IRUGO | S_IWUSR,
2012 root, dev,
6a9c308d 2013 fops);
07b7ddd9
JB		 2014 if (IS_ERR(ent))
2015 return PTR_ERR(ent);
2016
6a9c308d 2017 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 2018}
2019
27c202ad 2020static struct drm_info_list i915_debugfs_list[] = {
311bd68e 2021 {"i915_capabilities", i915_capabilities, 0},
73aa808f 2022 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 2023 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 2024 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 2025 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 2026 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4e5359cd 2027 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 2028 {"i915_gem_request", i915_gem_request_info, 0},
2029 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 2030 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 2031 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 2032 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2033 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2034 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
f97108d1
JB		 2035 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2036 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2037 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2038 {"i915_inttoext_table", i915_inttoext_table, 0},
2039 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 2040 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 2041 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 2042 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 2043 {"i915_fbc_status", i915_fbc_status, 0},
4a9bef37 2044 {"i915_sr_status", i915_sr_status, 0},
44834a67 2045 {"i915_opregion", i915_opregion, 0},
37811fcc 2046 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 2047 {"i915_context_status", i915_context_status, 0},
6d794d42 2048 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 2049 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 2050 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 2051 {"i915_dpio", i915_dpio_info, 0},
2017263e 2052};
27c202ad 2053#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 2054
27c202ad 2055int i915_debugfs_init(struct drm_minor *minor)
2017263e 2056{
f3cd474b
CW		 2057 int ret;
2058
6a9c308d
DV		 2059 ret = i915_debugfs_create(minor->debugfs_root, minor,
2060 "i915_wedged",
2061 &i915_wedged_fops);
f3cd474b
CW		 2062 if (ret)
2063 return ret;
2064
6d794d42 2065 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 2066 if (ret)
2067 return ret;
6a9c308d
DV		 2068
2069 ret = i915_debugfs_create(minor->debugfs_root, minor,
2070 "i915_max_freq",
2071 &i915_max_freq_fops);
07b7ddd9
JB		 2072 if (ret)
2073 return ret;
6a9c308d 2074
1523c310
JB		 2075 ret = i915_debugfs_create(minor->debugfs_root, minor,
2076 "i915_min_freq",
2077 &i915_min_freq_fops);
2078 if (ret)
2079 return ret;
2080
6a9c308d
DV		 2081 ret = i915_debugfs_create(minor->debugfs_root, minor,
2082 "i915_cache_sharing",
2083 &i915_cache_sharing_fops);
6d794d42
BW		 2084 if (ret)
2085 return ret;
004777cb 2086
e5eb3d63
DV		 2087 ret = i915_debugfs_create(minor->debugfs_root, minor,
2088 "i915_ring_stop",
2089 &i915_ring_stop_fops);
2090 if (ret)
2091 return ret;
6d794d42 2092
d5442303
DV		 2093 ret = i915_debugfs_create(minor->debugfs_root, minor,
2094 "i915_error_state",
2095 &i915_error_state_fops);
2096 if (ret)
2097 return ret;
2098
27c202ad
BG		 2099 return drm_debugfs_create_files(i915_debugfs_list,
2100 I915_DEBUGFS_ENTRIES,
2017263e
BG		 2101 minor->debugfs_root, minor);
2102}
2103
27c202ad 2104void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 2105{
27c202ad
BG		 2106 drm_debugfs_remove_files(i915_debugfs_list,
2107 I915_DEBUGFS_ENTRIES, minor);
6d794d42
BW		 2108 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2109 1, minor);
33db679b
KH		 2110 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
2111 1, minor);
358733e9
JB		 2112 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
2113 1, minor);
1523c310
JB		 2114 drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
2115 1, minor);
07b7ddd9
JB		 2116 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
2117 1, minor);
e5eb3d63
DV		 2118 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
2119 1, minor);
6bd459df
DV		 2120 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
2121 1, minor);
2017263e
BG		 2122}
2123
2124#endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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