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drm/i915: Prepare i915_gem_active for annotations
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
497666d8
DL		 49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
70d39fe4
CW		 75static int i915_capabilities(struct seq_file *m, void *data)
76{
9f25d007 77 struct drm_info_node *node = m->private;
70d39fe4
CW		 78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
70d39fe4
CW		 88
89 return 0;
90}
2017263e 91
a7363de7 92static char get_active_flag(struct drm_i915_gem_object *obj)
a6172a80 93{
be12a86b 94 return obj->active ? '*' : ' ';
a6172a80
CW		 95}
96
a7363de7 97static char get_pin_flag(struct drm_i915_gem_object *obj)
be12a86b
TU		 98{
99 return obj->pin_display ? 'p' : ' ';
100}
101
a7363de7 102static char get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 103{
0206e353
AJ		 104 switch (obj->tiling_mode) {
105 default:
be12a86b
TU		 106 case I915_TILING_NONE: return ' ';
107 case I915_TILING_X: return 'X';
108 case I915_TILING_Y: return 'Y';
0206e353 109 }
a6172a80
CW		 110}
111
a7363de7 112static char get_global_flag(struct drm_i915_gem_object *obj)
be12a86b
TU		 113{
114 return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
115}
116
a7363de7 117static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
1d693bcc 118{
be12a86b 119 return obj->mapping ? 'M' : ' ';
1d693bcc
BW		 120}
121
ca1543be
TU		 122static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
123{
124 u64 size = 0;
125 struct i915_vma *vma;
126
1c7f4bca 127 list_for_each_entry(vma, &obj->vma_list, obj_link) {
596c5923 128 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
ca1543be
TU		 129 size += vma->node.size;
130 }
131
132 return size;
133}
134
37811fcc
CW		 135static void
136describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137{
b4716185 138 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
e2f80391 139 struct intel_engine_cs *engine;
1d693bcc 140 struct i915_vma *vma;
d7f46fc4 141 int pin_count = 0;
c3232b18 142 enum intel_engine_id id;
d7f46fc4 143
188c1ab7
CW		 144 lockdep_assert_held(&obj->base.dev->struct_mutex);
145
be12a86b 146 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
37811fcc 147 &obj->base,
be12a86b 148 get_active_flag(obj),
37811fcc
CW		 149 get_pin_flag(obj),
150 get_tiling_flag(obj),
1d693bcc 151 get_global_flag(obj),
be12a86b 152 get_pin_mapped_flag(obj),
a05a5862 153 obj->base.size / 1024,
37811fcc 154 obj->base.read_domains,
b4716185 155 obj->base.write_domain);
c3232b18 156 for_each_engine_id(engine, dev_priv, id)
b4716185 157 seq_printf(m, "%x ",
27c01aae 158 i915_gem_active_get_seqno(&obj->last_read[id]));
b4716185 159 seq_printf(m, "] %x %x%s%s%s",
27c01aae
CW		 160 i915_gem_active_get_seqno(&obj->last_write),
161 i915_gem_active_get_seqno(&obj->last_fence),
0a4cd7c8 162 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
1c7f4bca 167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
d7f46fc4
BW		 168 if (vma->pin_count > 0)
169 pin_count++;
ba0635ff
DC		 170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 172 if (obj->pin_display)
173 seq_printf(m, " (display)");
37811fcc
CW		 174 if (obj->fence_reg != I915_FENCE_REG_NONE)
175 seq_printf(m, " (fence: %d)", obj->fence_reg);
1c7f4bca 176 list_for_each_entry(vma, &obj->vma_list, obj_link) {
15717de2
CW		 177 if (!drm_mm_node_allocated(&vma->node))
178 continue;
179
8d2fdc3f 180 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
596c5923 181 vma->is_ggtt ? "g" : "pp",
8d2fdc3f 182 vma->node.start, vma->node.size);
596c5923
CW		 183 if (vma->is_ggtt)
184 seq_printf(m, ", type: %u", vma->ggtt_view.type);
185 seq_puts(m, ")");
1d693bcc 186 }
c1ad11fc 187 if (obj->stolen)
440fd528 188 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 189 if (obj->pin_display || obj->fault_mappable) {
6299f992 190 char s[3], *t = s;
30154650 191 if (obj->pin_display)
6299f992
CW		 192 *t++ = 'p';
193 if (obj->fault_mappable)
194 *t++ = 'f';
195 *t = '\0';
196 seq_printf(m, " (%s mappable)", s);
197 }
27c01aae
CW		 198
199 engine = i915_gem_active_get_engine(&obj->last_write);
200 if (engine)
201 seq_printf(m, " (%s)", engine->name);
202
d5a81ef1
DV		 203 if (obj->frontbuffer_bits)
204 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 205}
206
433e12f7 207static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 208{
9f25d007 209 struct drm_info_node *node = m->private;
433e12f7
BG		 210 uintptr_t list = (uintptr_t) node->info_ent->data;
211 struct list_head *head;
2017263e 212 struct drm_device *dev = node->minor->dev;
72e96d64
JL		 213 struct drm_i915_private *dev_priv = to_i915(dev);
214 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ca191b13 215 struct i915_vma *vma;
c44ef60e 216 u64 total_obj_size, total_gtt_size;
8f2480fb 217 int count, ret;
de227ef0
CW		 218
219 ret = mutex_lock_interruptible(&dev->struct_mutex);
220 if (ret)
221 return ret;
2017263e 222
ca191b13 223 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 224 switch (list) {
225 case ACTIVE_LIST:
267f0c90 226 seq_puts(m, "Active:\n");
72e96d64 227 head = &ggtt->base.active_list;
433e12f7
BG		 228 break;
229 case INACTIVE_LIST:
267f0c90 230 seq_puts(m, "Inactive:\n");
72e96d64 231 head = &ggtt->base.inactive_list;
433e12f7 232 break;
433e12f7 233 default:
de227ef0
CW		 234 mutex_unlock(&dev->struct_mutex);
235 return -EINVAL;
2017263e 236 }
2017263e 237
8f2480fb 238 total_obj_size = total_gtt_size = count = 0;
1c7f4bca 239 list_for_each_entry(vma, head, vm_link) {
ca191b13
BW		 240 seq_printf(m, " ");
241 describe_obj(m, vma->obj);
242 seq_printf(m, "\n");
243 total_obj_size += vma->obj->base.size;
244 total_gtt_size += vma->node.size;
8f2480fb 245 count++;
2017263e 246 }
de227ef0 247 mutex_unlock(&dev->struct_mutex);
5e118f41 248
c44ef60e 249 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 250 count, total_obj_size, total_gtt_size);
2017263e
BG		 251 return 0;
252}
253
6d2b8885
CW		 254static int obj_rank_by_stolen(void *priv,
255 struct list_head *A, struct list_head *B)
256{
257 struct drm_i915_gem_object *a =
b25cb2f8 258 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 259 struct drm_i915_gem_object *b =
b25cb2f8 260 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 261
2d05fa16
RV		 262 if (a->stolen->start < b->stolen->start)
263 return -1;
264 if (a->stolen->start > b->stolen->start)
265 return 1;
266 return 0;
6d2b8885
CW		 267}
268
269static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
270{
9f25d007 271 struct drm_info_node *node = m->private;
6d2b8885 272 struct drm_device *dev = node->minor->dev;
fac5e23e 273 struct drm_i915_private *dev_priv = to_i915(dev);
6d2b8885 274 struct drm_i915_gem_object *obj;
c44ef60e 275 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 276 LIST_HEAD(stolen);
277 int count, ret;
278
279 ret = mutex_lock_interruptible(&dev->struct_mutex);
280 if (ret)
281 return ret;
282
283 total_obj_size = total_gtt_size = count = 0;
284 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
285 if (obj->stolen == NULL)
286 continue;
287
b25cb2f8 288 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 289
290 total_obj_size += obj->base.size;
ca1543be 291 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 292 count++;
293 }
294 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
295 if (obj->stolen == NULL)
296 continue;
297
b25cb2f8 298 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 299
300 total_obj_size += obj->base.size;
301 count++;
302 }
303 list_sort(NULL, &stolen, obj_rank_by_stolen);
304 seq_puts(m, "Stolen:\n");
305 while (!list_empty(&stolen)) {
b25cb2f8 306 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 307 seq_puts(m, " ");
308 describe_obj(m, obj);
309 seq_putc(m, '\n');
b25cb2f8 310 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 311 }
312 mutex_unlock(&dev->struct_mutex);
313
c44ef60e 314 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 315 count, total_obj_size, total_gtt_size);
316 return 0;
317}
318
6299f992
CW		 319#define count_objects(list, member) do { \
320 list_for_each_entry(obj, list, member) { \
ca1543be 321 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 322 ++count; \
323 if (obj->map_and_fenceable) { \
f343c5f6 324 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 325 ++mappable_count; \
326 } \
327 } \
0206e353 328} while (0)
6299f992 329
2db8e9d6 330struct file_stats {
6313c204 331 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 332 unsigned long count;
333 u64 total, unbound;
334 u64 global, shared;
335 u64 active, inactive;
2db8e9d6
CW		 336};
337
338static int per_file_stats(int id, void *ptr, void *data)
339{
340 struct drm_i915_gem_object *obj = ptr;
341 struct file_stats *stats = data;
6313c204 342 struct i915_vma *vma;
2db8e9d6
CW		 343
344 stats->count++;
345 stats->total += obj->base.size;
15717de2
CW		 346 if (!obj->bind_count)
347 stats->unbound += obj->base.size;
c67a17e9
CW		 348 if (obj->base.name || obj->base.dma_buf)
349 stats->shared += obj->base.size;
350
894eeecc
CW		 351 list_for_each_entry(vma, &obj->vma_list, obj_link) {
352 if (!drm_mm_node_allocated(&vma->node))
353 continue;
6313c204 354
894eeecc
CW		 355 if (vma->is_ggtt) {
356 stats->global += vma->node.size;
357 } else {
358 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
6313c204 359
2bfa996e 360 if (ppgtt->base.file != stats->file_priv)
6313c204 361 continue;
6313c204 362 }
894eeecc
CW		 363
364 if (obj->active) /* XXX per-vma statistic */
365 stats->active += vma->node.size;
366 else
367 stats->inactive += vma->node.size;
2db8e9d6
CW		 368 }
369
370 return 0;
371}
372
b0da1b79
CW		 373#define print_file_stats(m, name, stats) do { \
374 if (stats.count) \
c44ef60e 375 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 376 name, \
377 stats.count, \
378 stats.total, \
379 stats.active, \
380 stats.inactive, \
381 stats.global, \
382 stats.shared, \
383 stats.unbound); \
384} while (0)
493018dc
BV		 385
386static void print_batch_pool_stats(struct seq_file *m,
387 struct drm_i915_private *dev_priv)
388{
389 struct drm_i915_gem_object *obj;
390 struct file_stats stats;
e2f80391 391 struct intel_engine_cs *engine;
b4ac5afc 392 int j;
493018dc
BV		 393
394 memset(&stats, 0, sizeof(stats));
395
b4ac5afc 396 for_each_engine(engine, dev_priv) {
e2f80391 397 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744 398 list_for_each_entry(obj,
e2f80391 399 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 400 batch_pool_link)
401 per_file_stats(0, obj, &stats);
402 }
06fbca71 403 }
493018dc 404
b0da1b79 405 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 406}
407
15da9565
CW		 408static int per_file_ctx_stats(int id, void *ptr, void *data)
409{
410 struct i915_gem_context *ctx = ptr;
411 int n;
412
413 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
414 if (ctx->engine[n].state)
415 per_file_stats(0, ctx->engine[n].state, data);
dca33ecc
CW		 416 if (ctx->engine[n].ring)
417 per_file_stats(0, ctx->engine[n].ring->obj, data);
15da9565
CW		 418 }
419
420 return 0;
421}
422
423static void print_context_stats(struct seq_file *m,
424 struct drm_i915_private *dev_priv)
425{
426 struct file_stats stats;
427 struct drm_file *file;
428
429 memset(&stats, 0, sizeof(stats));
430
91c8a326 431 mutex_lock(&dev_priv->drm.struct_mutex);
15da9565
CW		 432 if (dev_priv->kernel_context)
433 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
434
91c8a326 435 list_for_each_entry(file, &dev_priv->drm.filelist, lhead) {
15da9565
CW		 436 struct drm_i915_file_private *fpriv = file->driver_priv;
437 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
438 }
91c8a326 439 mutex_unlock(&dev_priv->drm.struct_mutex);
15da9565
CW		 440
441 print_file_stats(m, "[k]contexts", stats);
442}
443
ca191b13
BW		 444#define count_vmas(list, member) do { \
445 list_for_each_entry(vma, list, member) { \
ca1543be 446 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 447 ++count; \
448 if (vma->obj->map_and_fenceable) { \
449 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
450 ++mappable_count; \
451 } \
452 } \
453} while (0)
454
455static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 456{
9f25d007 457 struct drm_info_node *node = m->private;
73aa808f 458 struct drm_device *dev = node->minor->dev;
72e96d64
JL		 459 struct drm_i915_private *dev_priv = to_i915(dev);
460 struct i915_ggtt *ggtt = &dev_priv->ggtt;
b7abb714 461 u32 count, mappable_count, purgeable_count;
c44ef60e 462 u64 size, mappable_size, purgeable_size;
be19b10d
TU		 463 unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
464 u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
6299f992 465 struct drm_i915_gem_object *obj;
2db8e9d6 466 struct drm_file *file;
ca191b13 467 struct i915_vma *vma;
73aa808f
CW		 468 int ret;
469
470 ret = mutex_lock_interruptible(&dev->struct_mutex);
471 if (ret)
472 return ret;
473
6299f992
CW		 474 seq_printf(m, "%u objects, %zu bytes\n",
475 dev_priv->mm.object_count,
476 dev_priv->mm.object_memory);
477
478 size = count = mappable_size = mappable_count = 0;
35c20a60 479 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 480 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 481 count, mappable_count, size, mappable_size);
482
483 size = count = mappable_size = mappable_count = 0;
72e96d64 484 count_vmas(&ggtt->base.active_list, vm_link);
c44ef60e 485 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 486 count, mappable_count, size, mappable_size);
487
6299f992 488 size = count = mappable_size = mappable_count = 0;
72e96d64 489 count_vmas(&ggtt->base.inactive_list, vm_link);
c44ef60e 490 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 491 count, mappable_count, size, mappable_size);
492
b7abb714 493 size = count = purgeable_size = purgeable_count = 0;
35c20a60 494 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 495 size += obj->base.size, ++count;
b7abb714
CW		 496 if (obj->madv == I915_MADV_DONTNEED)
497 purgeable_size += obj->base.size, ++purgeable_count;
be19b10d
TU		 498 if (obj->mapping) {
499 pin_mapped_count++;
500 pin_mapped_size += obj->base.size;
501 if (obj->pages_pin_count == 0) {
502 pin_mapped_purgeable_count++;
503 pin_mapped_purgeable_size += obj->base.size;
504 }
505 }
b7abb714 506 }
c44ef60e 507 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 508
6299f992 509 size = count = mappable_size = mappable_count = 0;
35c20a60 510 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 511 if (obj->fault_mappable) {
f343c5f6 512 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 513 ++count;
514 }
30154650 515 if (obj->pin_display) {
f343c5f6 516 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 517 ++mappable_count;
518 }
b7abb714
CW		 519 if (obj->madv == I915_MADV_DONTNEED) {
520 purgeable_size += obj->base.size;
521 ++purgeable_count;
522 }
be19b10d
TU		 523 if (obj->mapping) {
524 pin_mapped_count++;
525 pin_mapped_size += obj->base.size;
526 if (obj->pages_pin_count == 0) {
527 pin_mapped_purgeable_count++;
528 pin_mapped_purgeable_size += obj->base.size;
529 }
530 }
6299f992 531 }
c44ef60e 532 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 533 purgeable_count, purgeable_size);
c44ef60e 534 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 535 mappable_count, mappable_size);
c44ef60e 536 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992 537 count, size);
be19b10d
TU		 538 seq_printf(m,
539 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
540 pin_mapped_count, pin_mapped_purgeable_count,
541 pin_mapped_size, pin_mapped_purgeable_size);
6299f992 542
c44ef60e 543 seq_printf(m, "%llu [%llu] gtt total\n",
72e96d64 544 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
73aa808f 545
493018dc
BV		 546 seq_putc(m, '\n');
547 print_batch_pool_stats(m, dev_priv);
1d2ac403
DV		 548 mutex_unlock(&dev->struct_mutex);
549
550 mutex_lock(&dev->filelist_mutex);
15da9565 551 print_context_stats(m, dev_priv);
2db8e9d6
CW		 552 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
553 struct file_stats stats;
3ec2f427 554 struct task_struct *task;
2db8e9d6
CW		 555
556 memset(&stats, 0, sizeof(stats));
6313c204 557 stats.file_priv = file->driver_priv;
5b5ffff0 558 spin_lock(&file->table_lock);
2db8e9d6 559 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 560 spin_unlock(&file->table_lock);
3ec2f427
TH		 561 /*
562 * Although we have a valid reference on file->pid, that does
563 * not guarantee that the task_struct who called get_pid() is
564 * still alive (e.g. get_pid(current) => fork() => exit()).
565 * Therefore, we need to protect this ->comm access using RCU.
566 */
567 rcu_read_lock();
568 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 569 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 570 rcu_read_unlock();
2db8e9d6 571 }
1d2ac403 572 mutex_unlock(&dev->filelist_mutex);
73aa808f
CW		 573
574 return 0;
575}
576
aee56cff 577static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 578{
9f25d007 579 struct drm_info_node *node = m->private;
08c18323 580 struct drm_device *dev = node->minor->dev;
1b50247a 581 uintptr_t list = (uintptr_t) node->info_ent->data;
fac5e23e 582 struct drm_i915_private *dev_priv = to_i915(dev);
08c18323 583 struct drm_i915_gem_object *obj;
c44ef60e 584 u64 total_obj_size, total_gtt_size;
08c18323
CW		 585 int count, ret;
586
587 ret = mutex_lock_interruptible(&dev->struct_mutex);
588 if (ret)
589 return ret;
590
591 total_obj_size = total_gtt_size = count = 0;
35c20a60 592 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 593 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 594 continue;
595
267f0c90 596 seq_puts(m, " ");
08c18323 597 describe_obj(m, obj);
267f0c90 598 seq_putc(m, '\n');
08c18323 599 total_obj_size += obj->base.size;
ca1543be 600 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 601 count++;
602 }
603
604 mutex_unlock(&dev->struct_mutex);
605
c44ef60e 606 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 607 count, total_obj_size, total_gtt_size);
608
609 return 0;
610}
611
4e5359cd
SF		 612static int i915_gem_pageflip_info(struct seq_file *m, void *data)
613{
9f25d007 614 struct drm_info_node *node = m->private;
4e5359cd 615 struct drm_device *dev = node->minor->dev;
fac5e23e 616 struct drm_i915_private *dev_priv = to_i915(dev);
4e5359cd 617 struct intel_crtc *crtc;
8a270ebf
DV		 618 int ret;
619
620 ret = mutex_lock_interruptible(&dev->struct_mutex);
621 if (ret)
622 return ret;
4e5359cd 623
d3fcc808 624 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 625 const char pipe = pipe_name(crtc->pipe);
626 const char plane = plane_name(crtc->plane);
51cbaf01 627 struct intel_flip_work *work;
4e5359cd 628
5e2d7afc 629 spin_lock_irq(&dev->event_lock);
5a21b665
DV		 630 work = crtc->flip_work;
631 if (work == NULL) {
9db4a9c7 632 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 633 pipe, plane);
634 } else {
5a21b665
DV		 635 u32 pending;
636 u32 addr;
637
638 pending = atomic_read(&work->pending);
639 if (pending) {
640 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
641 pipe, plane);
642 } else {
643 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
644 pipe, plane);
645 }
646 if (work->flip_queued_req) {
647 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
648
649 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
650 engine->name,
651 i915_gem_request_get_seqno(work->flip_queued_req),
652 dev_priv->next_seqno,
1b7744e7 653 intel_engine_get_seqno(engine),
f69a02c9 654 i915_gem_request_completed(work->flip_queued_req));
5a21b665
DV		 655 } else
656 seq_printf(m, "Flip not associated with any ring\n");
657 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
658 work->flip_queued_vblank,
659 work->flip_ready_vblank,
660 intel_crtc_get_vblank_counter(crtc));
661 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
662
663 if (INTEL_INFO(dev)->gen >= 4)
664 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
665 else
666 addr = I915_READ(DSPADDR(crtc->plane));
667 seq_printf(m, "Current scanout address 0x%08x\n", addr);
668
669 if (work->pending_flip_obj) {
670 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
671 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 672 }
673 }
5e2d7afc 674 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 675 }
676
8a270ebf
DV		 677 mutex_unlock(&dev->struct_mutex);
678
4e5359cd
SF		 679 return 0;
680}
681
493018dc
BV		 682static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
683{
684 struct drm_info_node *node = m->private;
685 struct drm_device *dev = node->minor->dev;
fac5e23e 686 struct drm_i915_private *dev_priv = to_i915(dev);
493018dc 687 struct drm_i915_gem_object *obj;
e2f80391 688 struct intel_engine_cs *engine;
8d9d5744 689 int total = 0;
b4ac5afc 690 int ret, j;
493018dc
BV		 691
692 ret = mutex_lock_interruptible(&dev->struct_mutex);
693 if (ret)
694 return ret;
695
b4ac5afc 696 for_each_engine(engine, dev_priv) {
e2f80391 697 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744
CW		 698 int count;
699
700 count = 0;
701 list_for_each_entry(obj,
e2f80391 702 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 703 batch_pool_link)
704 count++;
705 seq_printf(m, "%s cache[%d]: %d objects\n",
e2f80391 706 engine->name, j, count);
8d9d5744
CW		 707
708 list_for_each_entry(obj,
e2f80391 709 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 710 batch_pool_link) {
711 seq_puts(m, " ");
712 describe_obj(m, obj);
713 seq_putc(m, '\n');
714 }
715
716 total += count;
06fbca71 717 }
493018dc
BV		 718 }
719
8d9d5744 720 seq_printf(m, "total: %d\n", total);
493018dc
BV		 721
722 mutex_unlock(&dev->struct_mutex);
723
724 return 0;
725}
726
2017263e
BG		 727static int i915_gem_request_info(struct seq_file *m, void *data)
728{
9f25d007 729 struct drm_info_node *node = m->private;
2017263e 730 struct drm_device *dev = node->minor->dev;
fac5e23e 731 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 732 struct intel_engine_cs *engine;
eed29a5b 733 struct drm_i915_gem_request *req;
b4ac5afc 734 int ret, any;
de227ef0
CW		 735
736 ret = mutex_lock_interruptible(&dev->struct_mutex);
737 if (ret)
738 return ret;
2017263e 739
2d1070b2 740 any = 0;
b4ac5afc 741 for_each_engine(engine, dev_priv) {
2d1070b2
CW		 742 int count;
743
744 count = 0;
e2f80391 745 list_for_each_entry(req, &engine->request_list, list)
2d1070b2
CW		 746 count++;
747 if (count == 0)
a2c7f6fd
CW		 748 continue;
749
e2f80391
TU		 750 seq_printf(m, "%s requests: %d\n", engine->name, count);
751 list_for_each_entry(req, &engine->request_list, list) {
2d1070b2
CW		 752 struct task_struct *task;
753
754 rcu_read_lock();
755 task = NULL;
eed29a5b
DV		 756 if (req->pid)
757 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 758 seq_printf(m, " %x @ %d: %s [%d]\n",
04769652 759 req->fence.seqno,
eed29a5b 760 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 761 task ? task->comm : "<unknown>",
762 task ? task->pid : -1);
763 rcu_read_unlock();
c2c347a9 764 }
2d1070b2
CW		 765
766 any++;
2017263e 767 }
de227ef0
CW		 768 mutex_unlock(&dev->struct_mutex);
769
2d1070b2 770 if (any == 0)
267f0c90 771 seq_puts(m, "No requests\n");
c2c347a9 772
2017263e
BG		 773 return 0;
774}
775
b2223497 776static void i915_ring_seqno_info(struct seq_file *m,
0bc40be8 777 struct intel_engine_cs *engine)
b2223497 778{
688e6c72
CW		 779 struct intel_breadcrumbs *b = &engine->breadcrumbs;
780 struct rb_node *rb;
781
12471ba8 782 seq_printf(m, "Current sequence (%s): %x\n",
1b7744e7 783 engine->name, intel_engine_get_seqno(engine));
aca34b6e
CW		 784 seq_printf(m, "Current user interrupts (%s): %lx\n",
785 engine->name, READ_ONCE(engine->breadcrumbs.irq_wakeups));
688e6c72
CW		 786
787 spin_lock(&b->lock);
788 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
789 struct intel_wait *w = container_of(rb, typeof(*w), node);
790
791 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
792 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
793 }
794 spin_unlock(&b->lock);
b2223497
CW		 795}
796
2017263e
BG		 797static int i915_gem_seqno_info(struct seq_file *m, void *data)
798{
9f25d007 799 struct drm_info_node *node = m->private;
2017263e 800 struct drm_device *dev = node->minor->dev;
fac5e23e 801 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 802 struct intel_engine_cs *engine;
b4ac5afc 803 int ret;
de227ef0
CW		 804
805 ret = mutex_lock_interruptible(&dev->struct_mutex);
806 if (ret)
807 return ret;
c8c8fb33 808 intel_runtime_pm_get(dev_priv);
2017263e 809
b4ac5afc 810 for_each_engine(engine, dev_priv)
e2f80391 811 i915_ring_seqno_info(m, engine);
de227ef0 812
c8c8fb33 813 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 814 mutex_unlock(&dev->struct_mutex);
815
2017263e
BG		 816 return 0;
817}
818
819
820static int i915_interrupt_info(struct seq_file *m, void *data)
821{
9f25d007 822 struct drm_info_node *node = m->private;
2017263e 823 struct drm_device *dev = node->minor->dev;
fac5e23e 824 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 825 struct intel_engine_cs *engine;
9db4a9c7 826 int ret, i, pipe;
de227ef0
CW		 827
828 ret = mutex_lock_interruptible(&dev->struct_mutex);
829 if (ret)
830 return ret;
c8c8fb33 831 intel_runtime_pm_get(dev_priv);
2017263e 832
74e1ca8c 833 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 834 seq_printf(m, "Master Interrupt Control:\t%08x\n",
835 I915_READ(GEN8_MASTER_IRQ));
836
837 seq_printf(m, "Display IER:\t%08x\n",
838 I915_READ(VLV_IER));
839 seq_printf(m, "Display IIR:\t%08x\n",
840 I915_READ(VLV_IIR));
841 seq_printf(m, "Display IIR_RW:\t%08x\n",
842 I915_READ(VLV_IIR_RW));
843 seq_printf(m, "Display IMR:\t%08x\n",
844 I915_READ(VLV_IMR));
055e393f 845 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 846 seq_printf(m, "Pipe %c stat:\t%08x\n",
847 pipe_name(pipe),
848 I915_READ(PIPESTAT(pipe)));
849
850 seq_printf(m, "Port hotplug:\t%08x\n",
851 I915_READ(PORT_HOTPLUG_EN));
852 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
853 I915_READ(VLV_DPFLIPSTAT));
854 seq_printf(m, "DPINVGTT:\t%08x\n",
855 I915_READ(DPINVGTT));
856
857 for (i = 0; i < 4; i++) {
858 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
859 i, I915_READ(GEN8_GT_IMR(i)));
860 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
861 i, I915_READ(GEN8_GT_IIR(i)));
862 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
863 i, I915_READ(GEN8_GT_IER(i)));
864 }
865
866 seq_printf(m, "PCU interrupt mask:\t%08x\n",
867 I915_READ(GEN8_PCU_IMR));
868 seq_printf(m, "PCU interrupt identity:\t%08x\n",
869 I915_READ(GEN8_PCU_IIR));
870 seq_printf(m, "PCU interrupt enable:\t%08x\n",
871 I915_READ(GEN8_PCU_IER));
872 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 873 seq_printf(m, "Master Interrupt Control:\t%08x\n",
874 I915_READ(GEN8_MASTER_IRQ));
875
876 for (i = 0; i < 4; i++) {
877 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
878 i, I915_READ(GEN8_GT_IMR(i)));
879 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
880 i, I915_READ(GEN8_GT_IIR(i)));
881 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
882 i, I915_READ(GEN8_GT_IER(i)));
883 }
884
055e393f 885 for_each_pipe(dev_priv, pipe) {
e129649b
ID		 886 enum intel_display_power_domain power_domain;
887
888 power_domain = POWER_DOMAIN_PIPE(pipe);
889 if (!intel_display_power_get_if_enabled(dev_priv,
890 power_domain)) {
22c59960
PZ		 891 seq_printf(m, "Pipe %c power disabled\n",
892 pipe_name(pipe));
893 continue;
894 }
a123f157 895 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 896 pipe_name(pipe),
897 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 898 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 899 pipe_name(pipe),
900 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 901 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 902 pipe_name(pipe),
903 I915_READ(GEN8_DE_PIPE_IER(pipe)));
e129649b
ID		 904
905 intel_display_power_put(dev_priv, power_domain);
a123f157
BW		 906 }
907
908 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
909 I915_READ(GEN8_DE_PORT_IMR));
910 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
911 I915_READ(GEN8_DE_PORT_IIR));
912 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
913 I915_READ(GEN8_DE_PORT_IER));
914
915 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
916 I915_READ(GEN8_DE_MISC_IMR));
917 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
918 I915_READ(GEN8_DE_MISC_IIR));
919 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
920 I915_READ(GEN8_DE_MISC_IER));
921
922 seq_printf(m, "PCU interrupt mask:\t%08x\n",
923 I915_READ(GEN8_PCU_IMR));
924 seq_printf(m, "PCU interrupt identity:\t%08x\n",
925 I915_READ(GEN8_PCU_IIR));
926 seq_printf(m, "PCU interrupt enable:\t%08x\n",
927 I915_READ(GEN8_PCU_IER));
928 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 929 seq_printf(m, "Display IER:\t%08x\n",
930 I915_READ(VLV_IER));
931 seq_printf(m, "Display IIR:\t%08x\n",
932 I915_READ(VLV_IIR));
933 seq_printf(m, "Display IIR_RW:\t%08x\n",
934 I915_READ(VLV_IIR_RW));
935 seq_printf(m, "Display IMR:\t%08x\n",
936 I915_READ(VLV_IMR));
055e393f 937 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 938 seq_printf(m, "Pipe %c stat:\t%08x\n",
939 pipe_name(pipe),
940 I915_READ(PIPESTAT(pipe)));
941
942 seq_printf(m, "Master IER:\t%08x\n",
943 I915_READ(VLV_MASTER_IER));
944
945 seq_printf(m, "Render IER:\t%08x\n",
946 I915_READ(GTIER));
947 seq_printf(m, "Render IIR:\t%08x\n",
948 I915_READ(GTIIR));
949 seq_printf(m, "Render IMR:\t%08x\n",
950 I915_READ(GTIMR));
951
952 seq_printf(m, "PM IER:\t\t%08x\n",
953 I915_READ(GEN6_PMIER));
954 seq_printf(m, "PM IIR:\t\t%08x\n",
955 I915_READ(GEN6_PMIIR));
956 seq_printf(m, "PM IMR:\t\t%08x\n",
957 I915_READ(GEN6_PMIMR));
958
959 seq_printf(m, "Port hotplug:\t%08x\n",
960 I915_READ(PORT_HOTPLUG_EN));
961 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
962 I915_READ(VLV_DPFLIPSTAT));
963 seq_printf(m, "DPINVGTT:\t%08x\n",
964 I915_READ(DPINVGTT));
965
966 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 967 seq_printf(m, "Interrupt enable: %08x\n",
968 I915_READ(IER));
969 seq_printf(m, "Interrupt identity: %08x\n",
970 I915_READ(IIR));
971 seq_printf(m, "Interrupt mask: %08x\n",
972 I915_READ(IMR));
055e393f 973 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 974 seq_printf(m, "Pipe %c stat: %08x\n",
975 pipe_name(pipe),
976 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 977 } else {
978 seq_printf(m, "North Display Interrupt enable: %08x\n",
979 I915_READ(DEIER));
980 seq_printf(m, "North Display Interrupt identity: %08x\n",
981 I915_READ(DEIIR));
982 seq_printf(m, "North Display Interrupt mask: %08x\n",
983 I915_READ(DEIMR));
984 seq_printf(m, "South Display Interrupt enable: %08x\n",
985 I915_READ(SDEIER));
986 seq_printf(m, "South Display Interrupt identity: %08x\n",
987 I915_READ(SDEIIR));
988 seq_printf(m, "South Display Interrupt mask: %08x\n",
989 I915_READ(SDEIMR));
990 seq_printf(m, "Graphics Interrupt enable: %08x\n",
991 I915_READ(GTIER));
992 seq_printf(m, "Graphics Interrupt identity: %08x\n",
993 I915_READ(GTIIR));
994 seq_printf(m, "Graphics Interrupt mask: %08x\n",
995 I915_READ(GTIMR));
996 }
b4ac5afc 997 for_each_engine(engine, dev_priv) {
a123f157 998 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 999 seq_printf(m,
1000 "Graphics Interrupt mask (%s): %08x\n",
e2f80391 1001 engine->name, I915_READ_IMR(engine));
9862e600 1002 }
e2f80391 1003 i915_ring_seqno_info(m, engine);
9862e600 1004 }
c8c8fb33 1005 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 1006 mutex_unlock(&dev->struct_mutex);
1007
2017263e
BG		 1008 return 0;
1009}
1010
a6172a80
CW		 1011static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
1012{
9f25d007 1013 struct drm_info_node *node = m->private;
a6172a80 1014 struct drm_device *dev = node->minor->dev;
fac5e23e 1015 struct drm_i915_private *dev_priv = to_i915(dev);
de227ef0
CW		 1016 int i, ret;
1017
1018 ret = mutex_lock_interruptible(&dev->struct_mutex);
1019 if (ret)
1020 return ret;
a6172a80 1021
a6172a80
CW		 1022 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1023 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 1024 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 1025
6c085a72
CW		 1026 seq_printf(m, "Fence %d, pin count = %d, object = ",
1027 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 1028 if (obj == NULL)
267f0c90 1029 seq_puts(m, "unused");
c2c347a9 1030 else
05394f39 1031 describe_obj(m, obj);
267f0c90 1032 seq_putc(m, '\n');
a6172a80
CW		 1033 }
1034
05394f39 1035 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 1036 return 0;
1037}
1038
2017263e
BG		 1039static int i915_hws_info(struct seq_file *m, void *data)
1040{
9f25d007 1041 struct drm_info_node *node = m->private;
2017263e 1042 struct drm_device *dev = node->minor->dev;
fac5e23e 1043 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 1044 struct intel_engine_cs *engine;
1a240d4d 1045 const u32 *hws;
4066c0ae
CW		 1046 int i;
1047
4a570db5 1048 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
e2f80391 1049 hws = engine->status_page.page_addr;
2017263e
BG		 1050 if (hws == NULL)
1051 return 0;
1052
1053 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1054 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1055 i * 4,
1056 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1057 }
1058 return 0;
1059}
1060
d5442303
DV		 1061static ssize_t
1062i915_error_state_write(struct file *filp,
1063 const char __user *ubuf,
1064 size_t cnt,
1065 loff_t *ppos)
1066{
edc3d884 1067 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1068 struct drm_device *dev = error_priv->dev;
22bcfc6a 1069 int ret;
d5442303
DV		 1070
1071 DRM_DEBUG_DRIVER("Resetting error state\n");
1072
22bcfc6a
DV		 1073 ret = mutex_lock_interruptible(&dev->struct_mutex);
1074 if (ret)
1075 return ret;
1076
d5442303
DV		 1077 i915_destroy_error_state(dev);
1078 mutex_unlock(&dev->struct_mutex);
1079
1080 return cnt;
1081}
1082
1083static int i915_error_state_open(struct inode *inode, struct file *file)
1084{
1085 struct drm_device *dev = inode->i_private;
d5442303 1086 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1087
1088 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1089 if (!error_priv)
1090 return -ENOMEM;
1091
1092 error_priv->dev = dev;
1093
95d5bfb3 1094 i915_error_state_get(dev, error_priv);
d5442303 1095
edc3d884
MK		 1096 file->private_data = error_priv;
1097
1098 return 0;
d5442303
DV		 1099}
1100
1101static int i915_error_state_release(struct inode *inode, struct file *file)
1102{
edc3d884 1103 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1104
95d5bfb3 1105 i915_error_state_put(error_priv);
d5442303
DV		 1106 kfree(error_priv);
1107
edc3d884
MK		 1108 return 0;
1109}
1110
4dc955f7
MK		 1111static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1112 size_t count, loff_t *pos)
1113{
1114 struct i915_error_state_file_priv *error_priv = file->private_data;
1115 struct drm_i915_error_state_buf error_str;
1116 loff_t tmp_pos = 0;
1117 ssize_t ret_count = 0;
1118 int ret;
1119
0a4cd7c8 1120 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1121 if (ret)
1122 return ret;
edc3d884 1123
fc16b48b 1124 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1125 if (ret)
1126 goto out;
1127
edc3d884
MK		 1128 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1129 error_str.buf,
1130 error_str.bytes);
1131
1132 if (ret_count < 0)
1133 ret = ret_count;
1134 else
1135 *pos = error_str.start + ret_count;
1136out:
4dc955f7 1137 i915_error_state_buf_release(&error_str);
edc3d884 1138 return ret ?: ret_count;
d5442303
DV		 1139}
1140
1141static const struct file_operations i915_error_state_fops = {
1142 .owner = THIS_MODULE,
1143 .open = i915_error_state_open,
edc3d884 1144 .read = i915_error_state_read,
d5442303
DV		 1145 .write = i915_error_state_write,
1146 .llseek = default_llseek,
1147 .release = i915_error_state_release,
1148};
1149
647416f9
KC		 1150static int
1151i915_next_seqno_get(void *data, u64 *val)
40633219 1152{
647416f9 1153 struct drm_device *dev = data;
fac5e23e 1154 struct drm_i915_private *dev_priv = to_i915(dev);
40633219
MK		 1155 int ret;
1156
1157 ret = mutex_lock_interruptible(&dev->struct_mutex);
1158 if (ret)
1159 return ret;
1160
647416f9 1161 *val = dev_priv->next_seqno;
40633219
MK		 1162 mutex_unlock(&dev->struct_mutex);
1163
647416f9 1164 return 0;
40633219
MK		 1165}
1166
647416f9
KC		 1167static int
1168i915_next_seqno_set(void *data, u64 val)
1169{
1170 struct drm_device *dev = data;
40633219
MK		 1171 int ret;
1172
40633219
MK		 1173 ret = mutex_lock_interruptible(&dev->struct_mutex);
1174 if (ret)
1175 return ret;
1176
e94fbaa8 1177 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1178 mutex_unlock(&dev->struct_mutex);
1179
647416f9 1180 return ret;
40633219
MK		 1181}
1182
647416f9
KC		 1183DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1184 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1185 "0x%llx\n");
40633219 1186
adb4bd12 1187static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1188{
9f25d007 1189 struct drm_info_node *node = m->private;
f97108d1 1190 struct drm_device *dev = node->minor->dev;
fac5e23e 1191 struct drm_i915_private *dev_priv = to_i915(dev);
c8c8fb33
PZ		 1192 int ret = 0;
1193
1194 intel_runtime_pm_get(dev_priv);
3b8d8d91
JB		 1195
1196 if (IS_GEN5(dev)) {
1197 u16 rgvswctl = I915_READ16(MEMSWCTL);
1198 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1199
1200 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1201 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1202 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1203 MEMSTAT_VID_SHIFT);
1204 seq_printf(m, "Current P-state: %d\n",
1205 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
666a4537
WB		 1206 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1207 u32 freq_sts;
1208
1209 mutex_lock(&dev_priv->rps.hw_lock);
1210 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1211 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1212 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1213
1214 seq_printf(m, "actual GPU freq: %d MHz\n",
1215 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1216
1217 seq_printf(m, "current GPU freq: %d MHz\n",
1218 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1219
1220 seq_printf(m, "max GPU freq: %d MHz\n",
1221 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1222
1223 seq_printf(m, "min GPU freq: %d MHz\n",
1224 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1225
1226 seq_printf(m, "idle GPU freq: %d MHz\n",
1227 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1228
1229 seq_printf(m,
1230 "efficient (RPe) frequency: %d MHz\n",
1231 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1232 mutex_unlock(&dev_priv->rps.hw_lock);
1233 } else if (INTEL_INFO(dev)->gen >= 6) {
35040562
BP		 1234 u32 rp_state_limits;
1235 u32 gt_perf_status;
1236 u32 rp_state_cap;
0d8f9491 1237 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1238 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1239 u32 rpupei, rpcurup, rpprevup;
1240 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1241 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1242 int max_freq;
1243
35040562
BP		 1244 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1245 if (IS_BROXTON(dev)) {
1246 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1247 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1248 } else {
1249 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1250 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1251 }
1252
3b8d8d91 1253 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1254 ret = mutex_lock_interruptible(&dev->struct_mutex);
1255 if (ret)
c8c8fb33 1256 goto out;
d1ebd816 1257
59bad947 1258 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1259
8e8c06cd 1260 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1261 if (IS_GEN9(dev))
1262 reqf >>= 23;
1263 else {
1264 reqf &= ~GEN6_TURBO_DISABLE;
1265 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1266 reqf >>= 24;
1267 else
1268 reqf >>= 25;
1269 }
7c59a9c1 1270 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1271
0d8f9491
CW		 1272 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1273 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1274 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1275
ccab5c82 1276 rpstat = I915_READ(GEN6_RPSTAT1);
d6cda9c7
AG		 1277 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1278 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1279 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1280 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1281 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1282 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
60260a5b
AG		 1283 if (IS_GEN9(dev))
1284 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1285 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1286 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1287 else
1288 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1289 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1290
59bad947 1291 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1292 mutex_unlock(&dev->struct_mutex);
1293
9dd3c605
PZ		 1294 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1295 pm_ier = I915_READ(GEN6_PMIER);
1296 pm_imr = I915_READ(GEN6_PMIMR);
1297 pm_isr = I915_READ(GEN6_PMISR);
1298 pm_iir = I915_READ(GEN6_PMIIR);
1299 pm_mask = I915_READ(GEN6_PMINTRMSK);
1300 } else {
1301 pm_ier = I915_READ(GEN8_GT_IER(2));
1302 pm_imr = I915_READ(GEN8_GT_IMR(2));
1303 pm_isr = I915_READ(GEN8_GT_ISR(2));
1304 pm_iir = I915_READ(GEN8_GT_IIR(2));
1305 pm_mask = I915_READ(GEN6_PMINTRMSK);
1306 }
0d8f9491 1307 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1308 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1800ad25 1309 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
3b8d8d91 1310 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1311 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1312 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1313 seq_printf(m, "Render p-state VID: %d\n",
1314 gt_perf_status & 0xff);
1315 seq_printf(m, "Render p-state limit: %d\n",
1316 rp_state_limits & 0xff);
0d8f9491
CW		 1317 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1318 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1319 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1320 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1321 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1322 seq_printf(m, "CAGF: %dMHz\n", cagf);
d6cda9c7
AG		 1323 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1324 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1325 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1326 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1327 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1328 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
d86ed34a
CW		 1329 seq_printf(m, "Up threshold: %d%%\n",
1330 dev_priv->rps.up_threshold);
1331
d6cda9c7
AG		 1332 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1333 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1334 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1335 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1336 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1337 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
d86ed34a
CW		 1338 seq_printf(m, "Down threshold: %d%%\n",
1339 dev_priv->rps.down_threshold);
3b8d8d91 1340
35040562
BP		 1341 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1342 rp_state_cap >> 16) & 0xff;
ef11bdb3
RV		 1343 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1344 GEN9_FREQ_SCALER : 1);
3b8d8d91 1345 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1346 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1347
1348 max_freq = (rp_state_cap & 0xff00) >> 8;
ef11bdb3
RV		 1349 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1350 GEN9_FREQ_SCALER : 1);
3b8d8d91 1351 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1352 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1353
35040562
BP		 1354 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1355 rp_state_cap >> 0) & 0xff;
ef11bdb3
RV		 1356 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1357 GEN9_FREQ_SCALER : 1);
3b8d8d91 1358 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1359 intel_gpu_freq(dev_priv, max_freq));
31c77388 1360 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1361 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1362
d86ed34a
CW		 1363 seq_printf(m, "Current freq: %d MHz\n",
1364 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1365 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1366 seq_printf(m, "Idle freq: %d MHz\n",
1367 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1368 seq_printf(m, "Min freq: %d MHz\n",
1369 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
29ecd78d
CW		 1370 seq_printf(m, "Boost freq: %d MHz\n",
1371 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
d86ed34a
CW		 1372 seq_printf(m, "Max freq: %d MHz\n",
1373 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1374 seq_printf(m,
1375 "efficient (RPe) frequency: %d MHz\n",
1376 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
3b8d8d91 1377 } else {
267f0c90 1378 seq_puts(m, "no P-state info available\n");
3b8d8d91 1379 }
f97108d1 1380
1170f28c
MK		 1381 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1382 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1383 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1384
c8c8fb33
PZ		 1385out:
1386 intel_runtime_pm_put(dev_priv);
1387 return ret;
f97108d1
JB		 1388}
1389
f654449a
CW		 1390static int i915_hangcheck_info(struct seq_file *m, void *unused)
1391{
1392 struct drm_info_node *node = m->private;
ebbc7546 1393 struct drm_device *dev = node->minor->dev;
fac5e23e 1394 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 1395 struct intel_engine_cs *engine;
666796da
TU		 1396 u64 acthd[I915_NUM_ENGINES];
1397 u32 seqno[I915_NUM_ENGINES];
61642ff0 1398 u32 instdone[I915_NUM_INSTDONE_REG];
c3232b18
DG		 1399 enum intel_engine_id id;
1400 int j;
f654449a
CW		 1401
1402 if (!i915.enable_hangcheck) {
1403 seq_printf(m, "Hangcheck disabled\n");
1404 return 0;
1405 }
1406
ebbc7546
MK		 1407 intel_runtime_pm_get(dev_priv);
1408
c3232b18 1409 for_each_engine_id(engine, dev_priv, id) {
7e37f889 1410 acthd[id] = intel_engine_get_active_head(engine);
1b7744e7 1411 seqno[id] = intel_engine_get_seqno(engine);
ebbc7546
MK		 1412 }
1413
c033666a 1414 i915_get_extra_instdone(dev_priv, instdone);
61642ff0 1415
ebbc7546
MK		 1416 intel_runtime_pm_put(dev_priv);
1417
f654449a
CW		 1418 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1419 seq_printf(m, "Hangcheck active, fires in %dms\n",
1420 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1421 jiffies));
1422 } else
1423 seq_printf(m, "Hangcheck inactive\n");
1424
c3232b18 1425 for_each_engine_id(engine, dev_priv, id) {
e2f80391 1426 seq_printf(m, "%s:\n", engine->name);
14fd0d6d
CW		 1427 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1428 engine->hangcheck.seqno,
1429 seqno[id],
1430 engine->last_submitted_seqno);
688e6c72
CW		 1431 seq_printf(m, "\twaiters? %d\n",
1432 intel_engine_has_waiter(engine));
aca34b6e 1433 seq_printf(m, "\tuser interrupts = %lx [current %lx]\n",
12471ba8 1434 engine->hangcheck.user_interrupts,
aca34b6e 1435 READ_ONCE(engine->breadcrumbs.irq_wakeups));
f654449a 1436 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
e2f80391 1437 (long long)engine->hangcheck.acthd,
c3232b18 1438 (long long)acthd[id]);
e2f80391
TU		 1439 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1440 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
61642ff0 1441
e2f80391 1442 if (engine->id == RCS) {
61642ff0
MK		 1443 seq_puts(m, "\tinstdone read =");
1444
1445 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1446 seq_printf(m, " 0x%08x", instdone[j]);
1447
1448 seq_puts(m, "\n\tinstdone accu =");
1449
1450 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1451 seq_printf(m, " 0x%08x",
e2f80391 1452 engine->hangcheck.instdone[j]);
61642ff0
MK		 1453
1454 seq_puts(m, "\n");
1455 }
f654449a
CW		 1456 }
1457
1458 return 0;
1459}
1460
4d85529d 1461static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1462{
9f25d007 1463 struct drm_info_node *node = m->private;
f97108d1 1464 struct drm_device *dev = node->minor->dev;
fac5e23e 1465 struct drm_i915_private *dev_priv = to_i915(dev);
616fdb5a
BW		 1466 u32 rgvmodectl, rstdbyctl;
1467 u16 crstandvid;
1468 int ret;
1469
1470 ret = mutex_lock_interruptible(&dev->struct_mutex);
1471 if (ret)
1472 return ret;
c8c8fb33 1473 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1474
1475 rgvmodectl = I915_READ(MEMMODECTL);
1476 rstdbyctl = I915_READ(RSTDBYCTL);
1477 crstandvid = I915_READ16(CRSTANDVID);
1478
c8c8fb33 1479 intel_runtime_pm_put(dev_priv);
616fdb5a 1480 mutex_unlock(&dev->struct_mutex);
f97108d1 1481
742f491d 1482 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1483 seq_printf(m, "Boost freq: %d\n",
1484 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1485 MEMMODE_BOOST_FREQ_SHIFT);
1486 seq_printf(m, "HW control enabled: %s\n",
742f491d 1487 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1488 seq_printf(m, "SW control enabled: %s\n",
742f491d 1489 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1490 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1491 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1492 seq_printf(m, "Starting frequency: P%d\n",
1493 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1494 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1495 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1496 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1497 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1498 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1499 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1500 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1501 seq_puts(m, "Current RS state: ");
88271da3
JB		 1502 switch (rstdbyctl & RSX_STATUS_MASK) {
1503 case RSX_STATUS_ON:
267f0c90 1504 seq_puts(m, "on\n");
88271da3
JB		 1505 break;
1506 case RSX_STATUS_RC1:
267f0c90 1507 seq_puts(m, "RC1\n");
88271da3
JB		 1508 break;
1509 case RSX_STATUS_RC1E:
267f0c90 1510 seq_puts(m, "RC1E\n");
88271da3
JB		 1511 break;
1512 case RSX_STATUS_RS1:
267f0c90 1513 seq_puts(m, "RS1\n");
88271da3
JB		 1514 break;
1515 case RSX_STATUS_RS2:
267f0c90 1516 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1517 break;
1518 case RSX_STATUS_RS3:
267f0c90 1519 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1520 break;
1521 default:
267f0c90 1522 seq_puts(m, "unknown\n");
88271da3
JB		 1523 break;
1524 }
f97108d1
JB		 1525
1526 return 0;
1527}
1528
f65367b5 1529static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1530{
b2cff0db
CW		 1531 struct drm_info_node *node = m->private;
1532 struct drm_device *dev = node->minor->dev;
fac5e23e 1533 struct drm_i915_private *dev_priv = to_i915(dev);
b2cff0db 1534 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1535
1536 spin_lock_irq(&dev_priv->uncore.lock);
33c582c1 1537 for_each_fw_domain(fw_domain, dev_priv) {
b2cff0db 1538 seq_printf(m, "%s.wake_count = %u\n",
33c582c1 1539 intel_uncore_forcewake_domain_to_str(fw_domain->id),
b2cff0db
CW		 1540 fw_domain->wake_count);
1541 }
1542 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1543
b2cff0db
CW		 1544 return 0;
1545}
1546
1547static int vlv_drpc_info(struct seq_file *m)
1548{
9f25d007 1549 struct drm_info_node *node = m->private;
669ab5aa 1550 struct drm_device *dev = node->minor->dev;
fac5e23e 1551 struct drm_i915_private *dev_priv = to_i915(dev);
6b312cd3 1552 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1553
d46c0517
ID		 1554 intel_runtime_pm_get(dev_priv);
1555
6b312cd3 1556 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1557 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1558 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1559
d46c0517
ID		 1560 intel_runtime_pm_put(dev_priv);
1561
669ab5aa
D		 1562 seq_printf(m, "Video Turbo Mode: %s\n",
1563 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1564 seq_printf(m, "Turbo enabled: %s\n",
1565 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1566 seq_printf(m, "HW control enabled: %s\n",
1567 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1568 seq_printf(m, "SW control enabled: %s\n",
1569 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1570 GEN6_RP_MEDIA_SW_MODE));
1571 seq_printf(m, "RC6 Enabled: %s\n",
1572 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1573 GEN6_RC_CTL_EI_MODE(1))));
1574 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1575 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1576 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1577 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1578
9cc19be5
ID		 1579 seq_printf(m, "Render RC6 residency since boot: %u\n",
1580 I915_READ(VLV_GT_RENDER_RC6));
1581 seq_printf(m, "Media RC6 residency since boot: %u\n",
1582 I915_READ(VLV_GT_MEDIA_RC6));
1583
f65367b5 1584 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1585}
1586
4d85529d
BW		 1587static int gen6_drpc_info(struct seq_file *m)
1588{
9f25d007 1589 struct drm_info_node *node = m->private;
4d85529d 1590 struct drm_device *dev = node->minor->dev;
fac5e23e 1591 struct drm_i915_private *dev_priv = to_i915(dev);
ecd8faea 1592 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
f2dd7578 1593 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
93b525dc 1594 unsigned forcewake_count;
aee56cff 1595 int count = 0, ret;
4d85529d
BW		 1596
1597 ret = mutex_lock_interruptible(&dev->struct_mutex);
1598 if (ret)
1599 return ret;
c8c8fb33 1600 intel_runtime_pm_get(dev_priv);
4d85529d 1601
907b28c5 1602 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1603 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1604 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1605
1606 if (forcewake_count) {
267f0c90
DL		 1607 seq_puts(m, "RC information inaccurate because somebody "
1608 "holds a forcewake reference \n");
4d85529d
BW		 1609 } else {
1610 /* NB: we cannot use forcewake, else we read the wrong values */
1611 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1612 udelay(10);
1613 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1614 }
1615
75aa3f63 1616 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
ed71f1b4 1617 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1618
1619 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1620 rcctl1 = I915_READ(GEN6_RC_CONTROL);
f2dd7578
AG		 1621 if (INTEL_INFO(dev)->gen >= 9) {
1622 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1623 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1624 }
4d85529d 1625 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1626 mutex_lock(&dev_priv->rps.hw_lock);
1627 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1628 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1629
c8c8fb33
PZ		 1630 intel_runtime_pm_put(dev_priv);
1631
4d85529d
BW		 1632 seq_printf(m, "Video Turbo Mode: %s\n",
1633 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1634 seq_printf(m, "HW control enabled: %s\n",
1635 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1636 seq_printf(m, "SW control enabled: %s\n",
1637 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1638 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1639 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1640 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1641 seq_printf(m, "RC6 Enabled: %s\n",
1642 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
f2dd7578
AG		 1643 if (INTEL_INFO(dev)->gen >= 9) {
1644 seq_printf(m, "Render Well Gating Enabled: %s\n",
1645 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1646 seq_printf(m, "Media Well Gating Enabled: %s\n",
1647 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1648 }
4d85529d
BW		 1649 seq_printf(m, "Deep RC6 Enabled: %s\n",
1650 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1651 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1652 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1653 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1654 switch (gt_core_status & GEN6_RCn_MASK) {
1655 case GEN6_RC0:
1656 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1657 seq_puts(m, "Core Power Down\n");
4d85529d 1658 else
267f0c90 1659 seq_puts(m, "on\n");
4d85529d
BW		 1660 break;
1661 case GEN6_RC3:
267f0c90 1662 seq_puts(m, "RC3\n");
4d85529d
BW		 1663 break;
1664 case GEN6_RC6:
267f0c90 1665 seq_puts(m, "RC6\n");
4d85529d
BW		 1666 break;
1667 case GEN6_RC7:
267f0c90 1668 seq_puts(m, "RC7\n");
4d85529d
BW		 1669 break;
1670 default:
267f0c90 1671 seq_puts(m, "Unknown\n");
4d85529d
BW		 1672 break;
1673 }
1674
1675 seq_printf(m, "Core Power Down: %s\n",
1676 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
f2dd7578
AG		 1677 if (INTEL_INFO(dev)->gen >= 9) {
1678 seq_printf(m, "Render Power Well: %s\n",
1679 (gen9_powergate_status &
1680 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1681 seq_printf(m, "Media Power Well: %s\n",
1682 (gen9_powergate_status &
1683 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1684 }
cce66a28
BW		 1685
1686 /* Not exactly sure what this is */
1687 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1688 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1689 seq_printf(m, "RC6 residency since boot: %u\n",
1690 I915_READ(GEN6_GT_GFX_RC6));
1691 seq_printf(m, "RC6+ residency since boot: %u\n",
1692 I915_READ(GEN6_GT_GFX_RC6p));
1693 seq_printf(m, "RC6++ residency since boot: %u\n",
1694 I915_READ(GEN6_GT_GFX_RC6pp));
1695
ecd8faea
BW		 1696 seq_printf(m, "RC6 voltage: %dmV\n",
1697 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1698 seq_printf(m, "RC6+ voltage: %dmV\n",
1699 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1700 seq_printf(m, "RC6++ voltage: %dmV\n",
1701 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
f2dd7578 1702 return i915_forcewake_domains(m, NULL);
4d85529d
BW		 1703}
1704
1705static int i915_drpc_info(struct seq_file *m, void *unused)
1706{
9f25d007 1707 struct drm_info_node *node = m->private;
4d85529d
BW		 1708 struct drm_device *dev = node->minor->dev;
1709
666a4537 1710 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
669ab5aa 1711 return vlv_drpc_info(m);
ac66cf4b 1712 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1713 return gen6_drpc_info(m);
1714 else
1715 return ironlake_drpc_info(m);
1716}
1717
9a851789
DV		 1718static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1719{
1720 struct drm_info_node *node = m->private;
1721 struct drm_device *dev = node->minor->dev;
fac5e23e 1722 struct drm_i915_private *dev_priv = to_i915(dev);
9a851789
DV		 1723
1724 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1725 dev_priv->fb_tracking.busy_bits);
1726
1727 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1728 dev_priv->fb_tracking.flip_bits);
1729
1730 return 0;
1731}
1732
b5e50c3f
JB		 1733static int i915_fbc_status(struct seq_file *m, void *unused)
1734{
9f25d007 1735 struct drm_info_node *node = m->private;
b5e50c3f 1736 struct drm_device *dev = node->minor->dev;
fac5e23e 1737 struct drm_i915_private *dev_priv = to_i915(dev);
b5e50c3f 1738
3a77c4c4 1739 if (!HAS_FBC(dev)) {
267f0c90 1740 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1741 return 0;
1742 }
1743
36623ef8 1744 intel_runtime_pm_get(dev_priv);
25ad93fd 1745 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1746
0e631adc 1747 if (intel_fbc_is_active(dev_priv))
267f0c90 1748 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1749 else
1750 seq_printf(m, "FBC disabled: %s\n",
bf6189c6 1751 dev_priv->fbc.no_fbc_reason);
36623ef8 1752
31b9df10
PZ		 1753 if (INTEL_INFO(dev_priv)->gen >= 7)
1754 seq_printf(m, "Compressing: %s\n",
1755 yesno(I915_READ(FBC_STATUS2) &
1756 FBC_COMPRESSION_MASK));
1757
25ad93fd 1758 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1759 intel_runtime_pm_put(dev_priv);
1760
b5e50c3f
JB		 1761 return 0;
1762}
1763
da46f936
RV		 1764static int i915_fbc_fc_get(void *data, u64 *val)
1765{
1766 struct drm_device *dev = data;
fac5e23e 1767 struct drm_i915_private *dev_priv = to_i915(dev);
da46f936
RV		 1768
1769 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1770 return -ENODEV;
1771
da46f936 1772 *val = dev_priv->fbc.false_color;
da46f936
RV		 1773
1774 return 0;
1775}
1776
1777static int i915_fbc_fc_set(void *data, u64 val)
1778{
1779 struct drm_device *dev = data;
fac5e23e 1780 struct drm_i915_private *dev_priv = to_i915(dev);
da46f936
RV		 1781 u32 reg;
1782
1783 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1784 return -ENODEV;
1785
25ad93fd 1786 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1787
1788 reg = I915_READ(ILK_DPFC_CONTROL);
1789 dev_priv->fbc.false_color = val;
1790
1791 I915_WRITE(ILK_DPFC_CONTROL, val ?
1792 (reg | FBC_CTL_FALSE_COLOR) :
1793 (reg & ~FBC_CTL_FALSE_COLOR));
1794
25ad93fd 1795 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1796 return 0;
1797}
1798
1799DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1800 i915_fbc_fc_get, i915_fbc_fc_set,
1801 "%llu\n");
1802
92d44621
PZ		 1803static int i915_ips_status(struct seq_file *m, void *unused)
1804{
9f25d007 1805 struct drm_info_node *node = m->private;
92d44621 1806 struct drm_device *dev = node->minor->dev;
fac5e23e 1807 struct drm_i915_private *dev_priv = to_i915(dev);
92d44621 1808
f5adf94e 1809 if (!HAS_IPS(dev)) {
92d44621
PZ		 1810 seq_puts(m, "not supported\n");
1811 return 0;
1812 }
1813
36623ef8
PZ		 1814 intel_runtime_pm_get(dev_priv);
1815
0eaa53f0
RV		 1816 seq_printf(m, "Enabled by kernel parameter: %s\n",
1817 yesno(i915.enable_ips));
1818
1819 if (INTEL_INFO(dev)->gen >= 8) {
1820 seq_puts(m, "Currently: unknown\n");
1821 } else {
1822 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1823 seq_puts(m, "Currently: enabled\n");
1824 else
1825 seq_puts(m, "Currently: disabled\n");
1826 }
92d44621 1827
36623ef8
PZ		 1828 intel_runtime_pm_put(dev_priv);
1829
92d44621
PZ		 1830 return 0;
1831}
1832
4a9bef37
JB		 1833static int i915_sr_status(struct seq_file *m, void *unused)
1834{
9f25d007 1835 struct drm_info_node *node = m->private;
4a9bef37 1836 struct drm_device *dev = node->minor->dev;
fac5e23e 1837 struct drm_i915_private *dev_priv = to_i915(dev);
4a9bef37
JB		 1838 bool sr_enabled = false;
1839
36623ef8
PZ		 1840 intel_runtime_pm_get(dev_priv);
1841
1398261a 1842 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1843 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1844 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1845 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1846 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1847 else if (IS_I915GM(dev))
1848 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1849 else if (IS_PINEVIEW(dev))
1850 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
666a4537 1851 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
77b64555 1852 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1853
36623ef8
PZ		 1854 intel_runtime_pm_put(dev_priv);
1855
5ba2aaaa
CW		 1856 seq_printf(m, "self-refresh: %s\n",
1857 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1858
1859 return 0;
1860}
1861
7648fa99
JB		 1862static int i915_emon_status(struct seq_file *m, void *unused)
1863{
9f25d007 1864 struct drm_info_node *node = m->private;
7648fa99 1865 struct drm_device *dev = node->minor->dev;
fac5e23e 1866 struct drm_i915_private *dev_priv = to_i915(dev);
7648fa99 1867 unsigned long temp, chipset, gfx;
de227ef0
CW		 1868 int ret;
1869
582be6b4
CW		 1870 if (!IS_GEN5(dev))
1871 return -ENODEV;
1872
de227ef0
CW		 1873 ret = mutex_lock_interruptible(&dev->struct_mutex);
1874 if (ret)
1875 return ret;
7648fa99
JB		 1876
1877 temp = i915_mch_val(dev_priv);
1878 chipset = i915_chipset_val(dev_priv);
1879 gfx = i915_gfx_val(dev_priv);
de227ef0 1880 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1881
1882 seq_printf(m, "GMCH temp: %ld\n", temp);
1883 seq_printf(m, "Chipset power: %ld\n", chipset);
1884 seq_printf(m, "GFX power: %ld\n", gfx);
1885 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1886
1887 return 0;
1888}
1889
23b2f8bb
JB		 1890static int i915_ring_freq_table(struct seq_file *m, void *unused)
1891{
9f25d007 1892 struct drm_info_node *node = m->private;
23b2f8bb 1893 struct drm_device *dev = node->minor->dev;
fac5e23e 1894 struct drm_i915_private *dev_priv = to_i915(dev);
5bfa0199 1895 int ret = 0;
23b2f8bb 1896 int gpu_freq, ia_freq;
f936ec34 1897 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1898
97d3308a 1899 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1900 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1901 return 0;
1902 }
1903
5bfa0199
PZ		 1904 intel_runtime_pm_get(dev_priv);
1905
4fc688ce 1906 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1907 if (ret)
5bfa0199 1908 goto out;
23b2f8bb 1909
ef11bdb3 1910 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
f936ec34
AG		 1911 /* Convert GT frequency to 50 HZ units */
1912 min_gpu_freq =
1913 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1914 max_gpu_freq =
1915 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1916 } else {
1917 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1918 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1919 }
1920
267f0c90 1921 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1922
f936ec34 1923 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1924 ia_freq = gpu_freq;
1925 sandybridge_pcode_read(dev_priv,
1926 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1927 &ia_freq);
3ebecd07 1928 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34 1929 intel_gpu_freq(dev_priv, (gpu_freq *
ef11bdb3
RV		 1930 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1931 GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1932 ((ia_freq >> 0) & 0xff) * 100,
1933 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1934 }
1935
4fc688ce 1936 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1937
5bfa0199
PZ		 1938out:
1939 intel_runtime_pm_put(dev_priv);
1940 return ret;
23b2f8bb
JB		 1941}
1942
44834a67
CW		 1943static int i915_opregion(struct seq_file *m, void *unused)
1944{
9f25d007 1945 struct drm_info_node *node = m->private;
44834a67 1946 struct drm_device *dev = node->minor->dev;
fac5e23e 1947 struct drm_i915_private *dev_priv = to_i915(dev);
44834a67
CW		 1948 struct intel_opregion *opregion = &dev_priv->opregion;
1949 int ret;
1950
1951 ret = mutex_lock_interruptible(&dev->struct_mutex);
1952 if (ret)
0d38f009 1953 goto out;
44834a67 1954
2455a8e4
JN		 1955 if (opregion->header)
1956 seq_write(m, opregion->header, OPREGION_SIZE);
44834a67
CW		 1957
1958 mutex_unlock(&dev->struct_mutex);
1959
0d38f009 1960out:
44834a67
CW		 1961 return 0;
1962}
1963
ada8f955
JN		 1964static int i915_vbt(struct seq_file *m, void *unused)
1965{
1966 struct drm_info_node *node = m->private;
1967 struct drm_device *dev = node->minor->dev;
fac5e23e 1968 struct drm_i915_private *dev_priv = to_i915(dev);
ada8f955
JN		 1969 struct intel_opregion *opregion = &dev_priv->opregion;
1970
1971 if (opregion->vbt)
1972 seq_write(m, opregion->vbt, opregion->vbt_size);
1973
1974 return 0;
1975}
1976
37811fcc
CW		 1977static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1978{
9f25d007 1979 struct drm_info_node *node = m->private;
37811fcc 1980 struct drm_device *dev = node->minor->dev;
b13b8402 1981 struct intel_framebuffer *fbdev_fb = NULL;
3a58ee10 1982 struct drm_framebuffer *drm_fb;
188c1ab7
CW		 1983 int ret;
1984
1985 ret = mutex_lock_interruptible(&dev->struct_mutex);
1986 if (ret)
1987 return ret;
37811fcc 1988
0695726e 1989#ifdef CONFIG_DRM_FBDEV_EMULATION
25bcce94
CW		 1990 if (to_i915(dev)->fbdev) {
1991 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1992
1993 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1994 fbdev_fb->base.width,
1995 fbdev_fb->base.height,
1996 fbdev_fb->base.depth,
1997 fbdev_fb->base.bits_per_pixel,
1998 fbdev_fb->base.modifier[0],
1999 drm_framebuffer_read_refcount(&fbdev_fb->base));
2000 describe_obj(m, fbdev_fb->obj);
2001 seq_putc(m, '\n');
2002 }
4520f53a 2003#endif
37811fcc 2004
4b096ac1 2005 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10 2006 drm_for_each_fb(drm_fb, dev) {
b13b8402
NS		 2007 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
2008 if (fb == fbdev_fb)
37811fcc
CW		 2009 continue;
2010
c1ca506d 2011 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 2012 fb->base.width,
2013 fb->base.height,
2014 fb->base.depth,
623f9783 2015 fb->base.bits_per_pixel,
c1ca506d 2016 fb->base.modifier[0],
747a598f 2017 drm_framebuffer_read_refcount(&fb->base));
05394f39 2018 describe_obj(m, fb->obj);
267f0c90 2019 seq_putc(m, '\n');
37811fcc 2020 }
4b096ac1 2021 mutex_unlock(&dev->mode_config.fb_lock);
188c1ab7 2022 mutex_unlock(&dev->struct_mutex);
37811fcc
CW		 2023
2024 return 0;
2025}
2026
7e37f889 2027static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
c9fe99bd
OM		 2028{
2029 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
7e37f889
CW		 2030 ring->space, ring->head, ring->tail,
2031 ring->last_retired_head);
c9fe99bd
OM		 2032}
2033
e76d3630
BW		 2034static int i915_context_status(struct seq_file *m, void *unused)
2035{
9f25d007 2036 struct drm_info_node *node = m->private;
e76d3630 2037 struct drm_device *dev = node->minor->dev;
fac5e23e 2038 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 2039 struct intel_engine_cs *engine;
e2efd130 2040 struct i915_gem_context *ctx;
c3232b18 2041 int ret;
e76d3630 2042
f3d28878 2043 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 2044 if (ret)
2045 return ret;
2046
a33afea5 2047 list_for_each_entry(ctx, &dev_priv->context_list, link) {
5d1808ec 2048 seq_printf(m, "HW context %u ", ctx->hw_id);
d28b99ab
CW		 2049 if (IS_ERR(ctx->file_priv)) {
2050 seq_puts(m, "(deleted) ");
2051 } else if (ctx->file_priv) {
2052 struct pid *pid = ctx->file_priv->file->pid;
2053 struct task_struct *task;
2054
2055 task = get_pid_task(pid, PIDTYPE_PID);
2056 if (task) {
2057 seq_printf(m, "(%s [%d]) ",
2058 task->comm, task->pid);
2059 put_task_struct(task);
2060 }
2061 } else {
2062 seq_puts(m, "(kernel) ");
2063 }
2064
bca44d80
CW		 2065 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
2066 seq_putc(m, '\n');
c9fe99bd 2067
bca44d80
CW		 2068 for_each_engine(engine, dev_priv) {
2069 struct intel_context *ce = &ctx->engine[engine->id];
2070
2071 seq_printf(m, "%s: ", engine->name);
2072 seq_putc(m, ce->initialised ? 'I' : 'i');
2073 if (ce->state)
2074 describe_obj(m, ce->state);
dca33ecc 2075 if (ce->ring)
7e37f889 2076 describe_ctx_ring(m, ce->ring);
c9fe99bd 2077 seq_putc(m, '\n');
c9fe99bd 2078 }
a33afea5 2079
a33afea5 2080 seq_putc(m, '\n');
a168c293
BW		 2081 }
2082
f3d28878 2083 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 2084
2085 return 0;
2086}
2087
064ca1d2 2088static void i915_dump_lrc_obj(struct seq_file *m,
e2efd130 2089 struct i915_gem_context *ctx,
0bc40be8 2090 struct intel_engine_cs *engine)
064ca1d2 2091{
bca44d80 2092 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
064ca1d2
TD		 2093 struct page *page;
2094 uint32_t *reg_state;
2095 int j;
2096 unsigned long ggtt_offset = 0;
2097
7069b144
CW		 2098 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2099
064ca1d2 2100 if (ctx_obj == NULL) {
7069b144 2101 seq_puts(m, "\tNot allocated\n");
064ca1d2
TD		 2102 return;
2103 }
2104
064ca1d2
TD		 2105 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2106 seq_puts(m, "\tNot bound in GGTT\n");
2107 else
2108 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2109
2110 if (i915_gem_object_get_pages(ctx_obj)) {
2111 seq_puts(m, "\tFailed to get pages for context object\n");
2112 return;
2113 }
2114
d1675198 2115 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
064ca1d2
TD		 2116 if (!WARN_ON(page == NULL)) {
2117 reg_state = kmap_atomic(page);
2118
2119 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2120 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2121 ggtt_offset + 4096 + (j * 4),
2122 reg_state[j], reg_state[j + 1],
2123 reg_state[j + 2], reg_state[j + 3]);
2124 }
2125 kunmap_atomic(reg_state);
2126 }
2127
2128 seq_putc(m, '\n');
2129}
2130
c0ab1ae9
BW		 2131static int i915_dump_lrc(struct seq_file *m, void *unused)
2132{
2133 struct drm_info_node *node = (struct drm_info_node *) m->private;
2134 struct drm_device *dev = node->minor->dev;
fac5e23e 2135 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 2136 struct intel_engine_cs *engine;
e2efd130 2137 struct i915_gem_context *ctx;
b4ac5afc 2138 int ret;
c0ab1ae9
BW		 2139
2140 if (!i915.enable_execlists) {
2141 seq_printf(m, "Logical Ring Contexts are disabled\n");
2142 return 0;
2143 }
2144
2145 ret = mutex_lock_interruptible(&dev->struct_mutex);
2146 if (ret)
2147 return ret;
2148
e28e404c 2149 list_for_each_entry(ctx, &dev_priv->context_list, link)
24f1d3cc
CW		 2150 for_each_engine(engine, dev_priv)
2151 i915_dump_lrc_obj(m, ctx, engine);
c0ab1ae9
BW		 2152
2153 mutex_unlock(&dev->struct_mutex);
2154
2155 return 0;
2156}
2157
4ba70e44
OM		 2158static int i915_execlists(struct seq_file *m, void *data)
2159{
2160 struct drm_info_node *node = (struct drm_info_node *)m->private;
2161 struct drm_device *dev = node->minor->dev;
fac5e23e 2162 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 2163 struct intel_engine_cs *engine;
4ba70e44
OM		 2164 u32 status_pointer;
2165 u8 read_pointer;
2166 u8 write_pointer;
2167 u32 status;
2168 u32 ctx_id;
2169 struct list_head *cursor;
b4ac5afc 2170 int i, ret;
4ba70e44
OM		 2171
2172 if (!i915.enable_execlists) {
2173 seq_puts(m, "Logical Ring Contexts are disabled\n");
2174 return 0;
2175 }
2176
2177 ret = mutex_lock_interruptible(&dev->struct_mutex);
2178 if (ret)
2179 return ret;
2180
fc0412ec
MT		 2181 intel_runtime_pm_get(dev_priv);
2182
b4ac5afc 2183 for_each_engine(engine, dev_priv) {
6d3d8274 2184 struct drm_i915_gem_request *head_req = NULL;
4ba70e44 2185 int count = 0;
4ba70e44 2186
e2f80391 2187 seq_printf(m, "%s\n", engine->name);
4ba70e44 2188
e2f80391
TU		 2189 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2190 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
4ba70e44
OM		 2191 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2192 status, ctx_id);
2193
e2f80391 2194 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
4ba70e44
OM		 2195 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2196
e2f80391 2197 read_pointer = engine->next_context_status_buffer;
5590a5f0 2198 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
4ba70e44 2199 if (read_pointer > write_pointer)
5590a5f0 2200 write_pointer += GEN8_CSB_ENTRIES;
4ba70e44
OM		 2201 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2202 read_pointer, write_pointer);
2203
5590a5f0 2204 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
e2f80391
TU		 2205 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2206 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
4ba70e44
OM		 2207
2208 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2209 i, status, ctx_id);
2210 }
2211
27af5eea 2212 spin_lock_bh(&engine->execlist_lock);
e2f80391 2213 list_for_each(cursor, &engine->execlist_queue)
4ba70e44 2214 count++;
e2f80391
TU		 2215 head_req = list_first_entry_or_null(&engine->execlist_queue,
2216 struct drm_i915_gem_request,
2217 execlist_link);
27af5eea 2218 spin_unlock_bh(&engine->execlist_lock);
4ba70e44
OM		 2219
2220 seq_printf(m, "\t%d requests in queue\n", count);
2221 if (head_req) {
7069b144
CW		 2222 seq_printf(m, "\tHead request context: %u\n",
2223 head_req->ctx->hw_id);
4ba70e44 2224 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2225 head_req->tail);
4ba70e44
OM		 2226 }
2227
2228 seq_putc(m, '\n');
2229 }
2230
fc0412ec 2231 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2232 mutex_unlock(&dev->struct_mutex);
2233
2234 return 0;
2235}
2236
ea16a3cd
DV		 2237static const char *swizzle_string(unsigned swizzle)
2238{
aee56cff 2239 switch (swizzle) {
ea16a3cd
DV		 2240 case I915_BIT_6_SWIZZLE_NONE:
2241 return "none";
2242 case I915_BIT_6_SWIZZLE_9:
2243 return "bit9";
2244 case I915_BIT_6_SWIZZLE_9_10:
2245 return "bit9/bit10";
2246 case I915_BIT_6_SWIZZLE_9_11:
2247 return "bit9/bit11";
2248 case I915_BIT_6_SWIZZLE_9_10_11:
2249 return "bit9/bit10/bit11";
2250 case I915_BIT_6_SWIZZLE_9_17:
2251 return "bit9/bit17";
2252 case I915_BIT_6_SWIZZLE_9_10_17:
2253 return "bit9/bit10/bit17";
2254 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2255 return "unknown";
ea16a3cd
DV		 2256 }
2257
2258 return "bug";
2259}
2260
2261static int i915_swizzle_info(struct seq_file *m, void *data)
2262{
9f25d007 2263 struct drm_info_node *node = m->private;
ea16a3cd 2264 struct drm_device *dev = node->minor->dev;
fac5e23e 2265 struct drm_i915_private *dev_priv = to_i915(dev);
22bcfc6a
DV		 2266 int ret;
2267
2268 ret = mutex_lock_interruptible(&dev->struct_mutex);
2269 if (ret)
2270 return ret;
c8c8fb33 2271 intel_runtime_pm_get(dev_priv);
ea16a3cd 2272
ea16a3cd
DV		 2273 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2274 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2275 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2276 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2277
2278 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2279 seq_printf(m, "DDC = 0x%08x\n",
2280 I915_READ(DCC));
656bfa3a
DV		 2281 seq_printf(m, "DDC2 = 0x%08x\n",
2282 I915_READ(DCC2));
ea16a3cd
DV		 2283 seq_printf(m, "C0DRB3 = 0x%04x\n",
2284 I915_READ16(C0DRB3));
2285 seq_printf(m, "C1DRB3 = 0x%04x\n",
2286 I915_READ16(C1DRB3));
9d3203e1 2287 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2288 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2289 I915_READ(MAD_DIMM_C0));
2290 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2291 I915_READ(MAD_DIMM_C1));
2292 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2293 I915_READ(MAD_DIMM_C2));
2294 seq_printf(m, "TILECTL = 0x%08x\n",
2295 I915_READ(TILECTL));
5907f5fb 2296 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2297 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2298 I915_READ(GAMTARBMODE));
2299 else
2300 seq_printf(m, "ARB_MODE = 0x%08x\n",
2301 I915_READ(ARB_MODE));
3fa7d235
DV		 2302 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2303 I915_READ(DISP_ARB_CTL));
ea16a3cd 2304 }
656bfa3a
DV		 2305
2306 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2307 seq_puts(m, "L-shaped memory detected\n");
2308
c8c8fb33 2309 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2310 mutex_unlock(&dev->struct_mutex);
2311
2312 return 0;
2313}
2314
1c60fef5
BW		 2315static int per_file_ctx(int id, void *ptr, void *data)
2316{
e2efd130 2317 struct i915_gem_context *ctx = ptr;
1c60fef5 2318 struct seq_file *m = data;
ae6c4806
DV		 2319 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2320
2321 if (!ppgtt) {
2322 seq_printf(m, " no ppgtt for context %d\n",
2323 ctx->user_handle);
2324 return 0;
2325 }
1c60fef5 2326
f83d6518
OM		 2327 if (i915_gem_context_is_default(ctx))
2328 seq_puts(m, " default context:\n");
2329 else
821d66dd 2330 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2331 ppgtt->debug_dump(ppgtt, m);
2332
2333 return 0;
2334}
2335
77df6772 2336static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2337{
fac5e23e 2338 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 2339 struct intel_engine_cs *engine;
77df6772 2340 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
b4ac5afc 2341 int i;
3cf17fc5 2342
77df6772
BW		 2343 if (!ppgtt)
2344 return;
2345
b4ac5afc 2346 for_each_engine(engine, dev_priv) {
e2f80391 2347 seq_printf(m, "%s\n", engine->name);
77df6772 2348 for (i = 0; i < 4; i++) {
e2f80391 2349 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
77df6772 2350 pdp <<= 32;
e2f80391 2351 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
a2a5b15c 2352 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2353 }
2354 }
2355}
2356
2357static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2358{
fac5e23e 2359 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 2360 struct intel_engine_cs *engine;
3cf17fc5 2361
7e22dbbb 2362 if (IS_GEN6(dev_priv))
3cf17fc5
DV		 2363 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2364
b4ac5afc 2365 for_each_engine(engine, dev_priv) {
e2f80391 2366 seq_printf(m, "%s\n", engine->name);
7e22dbbb 2367 if (IS_GEN7(dev_priv))
e2f80391
TU		 2368 seq_printf(m, "GFX_MODE: 0x%08x\n",
2369 I915_READ(RING_MODE_GEN7(engine)));
2370 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2371 I915_READ(RING_PP_DIR_BASE(engine)));
2372 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2373 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2374 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2375 I915_READ(RING_PP_DIR_DCLV(engine)));
3cf17fc5
DV		 2376 }
2377 if (dev_priv->mm.aliasing_ppgtt) {
2378 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2379
267f0c90 2380 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2381 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2382
87d60b63 2383 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2384 }
1c60fef5 2385
3cf17fc5 2386 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2387}
2388
2389static int i915_ppgtt_info(struct seq_file *m, void *data)
2390{
9f25d007 2391 struct drm_info_node *node = m->private;
77df6772 2392 struct drm_device *dev = node->minor->dev;
fac5e23e 2393 struct drm_i915_private *dev_priv = to_i915(dev);
ea91e401 2394 struct drm_file *file;
77df6772
BW		 2395
2396 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2397 if (ret)
2398 return ret;
c8c8fb33 2399 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2400
2401 if (INTEL_INFO(dev)->gen >= 8)
2402 gen8_ppgtt_info(m, dev);
2403 else if (INTEL_INFO(dev)->gen >= 6)
2404 gen6_ppgtt_info(m, dev);
2405
1d2ac403 2406 mutex_lock(&dev->filelist_mutex);
ea91e401
MT		 2407 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2408 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2409 struct task_struct *task;
ea91e401 2410
7cb5dff8 2411 task = get_pid_task(file->pid, PIDTYPE_PID);
06812760
DC		 2412 if (!task) {
2413 ret = -ESRCH;
b0212486 2414 goto out_unlock;
06812760 2415 }
7cb5dff8
GT		 2416 seq_printf(m, "\nproc: %s\n", task->comm);
2417 put_task_struct(task);
ea91e401
MT		 2418 idr_for_each(&file_priv->context_idr, per_file_ctx,
2419 (void *)(unsigned long)m);
2420 }
b0212486 2421out_unlock:
1d2ac403 2422 mutex_unlock(&dev->filelist_mutex);
ea91e401 2423
c8c8fb33 2424 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2425 mutex_unlock(&dev->struct_mutex);
2426
06812760 2427 return ret;
3cf17fc5
DV		 2428}
2429
f5a4c67d
CW		 2430static int count_irq_waiters(struct drm_i915_private *i915)
2431{
e2f80391 2432 struct intel_engine_cs *engine;
f5a4c67d 2433 int count = 0;
f5a4c67d 2434
b4ac5afc 2435 for_each_engine(engine, i915)
688e6c72 2436 count += intel_engine_has_waiter(engine);
f5a4c67d
CW		 2437
2438 return count;
2439}
2440
1854d5ca
CW		 2441static int i915_rps_boost_info(struct seq_file *m, void *data)
2442{
2443 struct drm_info_node *node = m->private;
2444 struct drm_device *dev = node->minor->dev;
fac5e23e 2445 struct drm_i915_private *dev_priv = to_i915(dev);
1854d5ca 2446 struct drm_file *file;
1854d5ca 2447
f5a4c67d 2448 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
67d97da3
CW		 2449 seq_printf(m, "GPU busy? %s [%x]\n",
2450 yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
f5a4c67d
CW		 2451 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2452 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2453 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2454 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2455 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2456 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2457 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1d2ac403
DV		 2458
2459 mutex_lock(&dev->filelist_mutex);
8d3afd7d 2460 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2461 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2462 struct drm_i915_file_private *file_priv = file->driver_priv;
2463 struct task_struct *task;
2464
2465 rcu_read_lock();
2466 task = pid_task(file->pid, PIDTYPE_PID);
2467 seq_printf(m, "%s [%d]: %d boosts%s\n",
2468 task ? task->comm : "<unknown>",
2469 task ? task->pid : -1,
2e1b8730
CW		 2470 file_priv->rps.boosts,
2471 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2472 rcu_read_unlock();
2473 }
197be2ae 2474 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2475 spin_unlock(&dev_priv->rps.client_lock);
1d2ac403 2476 mutex_unlock(&dev->filelist_mutex);
1854d5ca 2477
8d3afd7d 2478 return 0;
1854d5ca
CW		 2479}
2480
63573eb7
BW		 2481static int i915_llc(struct seq_file *m, void *data)
2482{
9f25d007 2483 struct drm_info_node *node = m->private;
63573eb7 2484 struct drm_device *dev = node->minor->dev;
fac5e23e 2485 struct drm_i915_private *dev_priv = to_i915(dev);
3accaf7e 2486 const bool edram = INTEL_GEN(dev_priv) > 8;
63573eb7 2487
63573eb7 2488 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
3accaf7e
MK		 2489 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2490 intel_uncore_edram_size(dev_priv)/1024/1024);
63573eb7
BW		 2491
2492 return 0;
2493}
2494
fdf5d357
AD		 2495static int i915_guc_load_status_info(struct seq_file *m, void *data)
2496{
2497 struct drm_info_node *node = m->private;
fac5e23e 2498 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
fdf5d357
AD		 2499 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2500 u32 tmp, i;
2501
2d1fe073 2502 if (!HAS_GUC_UCODE(dev_priv))
fdf5d357
AD		 2503 return 0;
2504
2505 seq_printf(m, "GuC firmware status:\n");
2506 seq_printf(m, "\tpath: %s\n",
2507 guc_fw->guc_fw_path);
2508 seq_printf(m, "\tfetch: %s\n",
2509 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2510 seq_printf(m, "\tload: %s\n",
2511 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2512 seq_printf(m, "\tversion wanted: %d.%d\n",
2513 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2514 seq_printf(m, "\tversion found: %d.%d\n",
2515 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
feda33ef
AD		 2516 seq_printf(m, "\theader: offset is %d; size = %d\n",
2517 guc_fw->header_offset, guc_fw->header_size);
2518 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2519 guc_fw->ucode_offset, guc_fw->ucode_size);
2520 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2521 guc_fw->rsa_offset, guc_fw->rsa_size);
fdf5d357
AD		 2522
2523 tmp = I915_READ(GUC_STATUS);
2524
2525 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2526 seq_printf(m, "\tBootrom status = 0x%x\n",
2527 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2528 seq_printf(m, "\tuKernel status = 0x%x\n",
2529 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2530 seq_printf(m, "\tMIA Core status = 0x%x\n",
2531 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2532 seq_puts(m, "\nScratch registers:\n");
2533 for (i = 0; i < 16; i++)
2534 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2535
2536 return 0;
2537}
2538
8b417c26
DG		 2539static void i915_guc_client_info(struct seq_file *m,
2540 struct drm_i915_private *dev_priv,
2541 struct i915_guc_client *client)
2542{
e2f80391 2543 struct intel_engine_cs *engine;
8b417c26 2544 uint64_t tot = 0;
8b417c26
DG		 2545
2546 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2547 client->priority, client->ctx_index, client->proc_desc_offset);
2548 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2549 client->doorbell_id, client->doorbell_offset, client->cookie);
2550 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2551 client->wq_size, client->wq_offset, client->wq_tail);
2552
551aaecd 2553 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
8b417c26
DG		 2554 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2555 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2556 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2557
b4ac5afc 2558 for_each_engine(engine, dev_priv) {
8b417c26 2559 seq_printf(m, "\tSubmissions: %llu %s\n",
0b63bb14 2560 client->submissions[engine->id],
e2f80391 2561 engine->name);
0b63bb14 2562 tot += client->submissions[engine->id];
8b417c26
DG		 2563 }
2564 seq_printf(m, "\tTotal: %llu\n", tot);
2565}
2566
2567static int i915_guc_info(struct seq_file *m, void *data)
2568{
2569 struct drm_info_node *node = m->private;
2570 struct drm_device *dev = node->minor->dev;
fac5e23e 2571 struct drm_i915_private *dev_priv = to_i915(dev);
8b417c26 2572 struct intel_guc guc;
0a0b457f 2573 struct i915_guc_client client = {};
e2f80391 2574 struct intel_engine_cs *engine;
8b417c26
DG		 2575 u64 total = 0;
2576
2d1fe073 2577 if (!HAS_GUC_SCHED(dev_priv))
8b417c26
DG		 2578 return 0;
2579
5a843307
AD		 2580 if (mutex_lock_interruptible(&dev->struct_mutex))
2581 return 0;
2582
8b417c26 2583 /* Take a local copy of the GuC data, so we can dump it at leisure */
8b417c26 2584 guc = dev_priv->guc;
5a843307 2585 if (guc.execbuf_client)
8b417c26 2586 client = *guc.execbuf_client;
5a843307
AD		 2587
2588 mutex_unlock(&dev->struct_mutex);
8b417c26 2589
9636f6db
DG		 2590 seq_printf(m, "Doorbell map:\n");
2591 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2592 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2593
8b417c26
DG		 2594 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2595 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2596 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2597 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2598 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2599
2600 seq_printf(m, "\nGuC submissions:\n");
b4ac5afc 2601 for_each_engine(engine, dev_priv) {
397097b0 2602 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
0b63bb14
DG		 2603 engine->name, guc.submissions[engine->id],
2604 guc.last_seqno[engine->id]);
2605 total += guc.submissions[engine->id];
8b417c26
DG		 2606 }
2607 seq_printf(m, "\t%s: %llu\n", "Total", total);
2608
2609 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2610 i915_guc_client_info(m, dev_priv, &client);
2611
2612 /* Add more as required ... */
2613
2614 return 0;
2615}
2616
4c7e77fc
AD		 2617static int i915_guc_log_dump(struct seq_file *m, void *data)
2618{
2619 struct drm_info_node *node = m->private;
2620 struct drm_device *dev = node->minor->dev;
fac5e23e 2621 struct drm_i915_private *dev_priv = to_i915(dev);
4c7e77fc
AD		 2622 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2623 u32 *log;
2624 int i = 0, pg;
2625
2626 if (!log_obj)
2627 return 0;
2628
2629 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2630 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2631
2632 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2633 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2634 *(log + i), *(log + i + 1),
2635 *(log + i + 2), *(log + i + 3));
2636
2637 kunmap_atomic(log);
2638 }
2639
2640 seq_putc(m, '\n');
2641
2642 return 0;
2643}
2644
e91fd8c6
RV		 2645static int i915_edp_psr_status(struct seq_file *m, void *data)
2646{
2647 struct drm_info_node *node = m->private;
2648 struct drm_device *dev = node->minor->dev;
fac5e23e 2649 struct drm_i915_private *dev_priv = to_i915(dev);
a031d709 2650 u32 psrperf = 0;
a6cbdb8e
RV		 2651 u32 stat[3];
2652 enum pipe pipe;
a031d709 2653 bool enabled = false;
e91fd8c6 2654
3553a8ea
DL		 2655 if (!HAS_PSR(dev)) {
2656 seq_puts(m, "PSR not supported\n");
2657 return 0;
2658 }
2659
c8c8fb33
PZ		 2660 intel_runtime_pm_get(dev_priv);
2661
fa128fa6 2662 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2663 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2664 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2665 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2666 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2667 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2668 dev_priv->psr.busy_frontbuffer_bits);
2669 seq_printf(m, "Re-enable work scheduled: %s\n",
2670 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2671
3553a8ea 2672 if (HAS_DDI(dev))
443a389f 2673 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
3553a8ea
DL		 2674 else {
2675 for_each_pipe(dev_priv, pipe) {
2676 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2677 VLV_EDP_PSR_CURR_STATE_MASK;
2678 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2679 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2680 enabled = true;
a6cbdb8e
RV		 2681 }
2682 }
60e5ffe3
RV		 2683
2684 seq_printf(m, "Main link in standby mode: %s\n",
2685 yesno(dev_priv->psr.link_standby));
2686
a6cbdb8e
RV		 2687 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2688
2689 if (!HAS_DDI(dev))
2690 for_each_pipe(dev_priv, pipe) {
2691 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2692 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2693 seq_printf(m, " pipe %c", pipe_name(pipe));
2694 }
2695 seq_puts(m, "\n");
e91fd8c6 2696
05eec3c2
RV		 2697 /*
2698 * VLV/CHV PSR has no kind of performance counter
2699 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2700 */
2701 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
443a389f 2702 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
a031d709 2703 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2704
2705 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2706 }
fa128fa6 2707 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2708
c8c8fb33 2709 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2710 return 0;
2711}
2712
d2e216d0
RV		 2713static int i915_sink_crc(struct seq_file *m, void *data)
2714{
2715 struct drm_info_node *node = m->private;
2716 struct drm_device *dev = node->minor->dev;
d2e216d0
RV		 2717 struct intel_connector *connector;
2718 struct intel_dp *intel_dp = NULL;
2719 int ret;
2720 u8 crc[6];
2721
2722 drm_modeset_lock_all(dev);
aca5e361 2723 for_each_intel_connector(dev, connector) {
26c17cf6 2724 struct drm_crtc *crtc;
d2e216d0 2725
26c17cf6 2726 if (!connector->base.state->best_encoder)
d2e216d0
RV		 2727 continue;
2728
26c17cf6
ML		 2729 crtc = connector->base.state->crtc;
2730 if (!crtc->state->active)
b6ae3c7c
PZ		 2731 continue;
2732
26c17cf6 2733 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
d2e216d0
RV		 2734 continue;
2735
26c17cf6 2736 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
d2e216d0
RV		 2737
2738 ret = intel_dp_sink_crc(intel_dp, crc);
2739 if (ret)
2740 goto out;
2741
2742 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2743 crc[0], crc[1], crc[2],
2744 crc[3], crc[4], crc[5]);
2745 goto out;
2746 }
2747 ret = -ENODEV;
2748out:
2749 drm_modeset_unlock_all(dev);
2750 return ret;
2751}
2752
ec013e7f
JB		 2753static int i915_energy_uJ(struct seq_file *m, void *data)
2754{
2755 struct drm_info_node *node = m->private;
2756 struct drm_device *dev = node->minor->dev;
fac5e23e 2757 struct drm_i915_private *dev_priv = to_i915(dev);
ec013e7f
JB		 2758 u64 power;
2759 u32 units;
2760
2761 if (INTEL_INFO(dev)->gen < 6)
2762 return -ENODEV;
2763
36623ef8
PZ		 2764 intel_runtime_pm_get(dev_priv);
2765
ec013e7f
JB		 2766 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2767 power = (power & 0x1f00) >> 8;
2768 units = 1000000 / (1 << power); /* convert to uJ */
2769 power = I915_READ(MCH_SECP_NRG_STTS);
2770 power *= units;
2771
36623ef8
PZ		 2772 intel_runtime_pm_put(dev_priv);
2773
ec013e7f 2774 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2775
2776 return 0;
2777}
2778
6455c870 2779static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2780{
9f25d007 2781 struct drm_info_node *node = m->private;
371db66a 2782 struct drm_device *dev = node->minor->dev;
fac5e23e 2783 struct drm_i915_private *dev_priv = to_i915(dev);
371db66a 2784
a156e64d
CW		 2785 if (!HAS_RUNTIME_PM(dev_priv))
2786 seq_puts(m, "Runtime power management not supported\n");
371db66a 2787
67d97da3 2788 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
371db66a 2789 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2790 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2791#ifdef CONFIG_PM
a6aaec8b
DL		 2792 seq_printf(m, "Usage count: %d\n",
2793 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2794#else
2795 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2796#endif
a156e64d 2797 seq_printf(m, "PCI device power state: %s [%d]\n",
91c8a326
CW		 2798 pci_power_name(dev_priv->drm.pdev->current_state),
2799 dev_priv->drm.pdev->current_state);
371db66a 2800
ec013e7f
JB		 2801 return 0;
2802}
2803
1da51581
ID		 2804static int i915_power_domain_info(struct seq_file *m, void *unused)
2805{
9f25d007 2806 struct drm_info_node *node = m->private;
1da51581 2807 struct drm_device *dev = node->minor->dev;
fac5e23e 2808 struct drm_i915_private *dev_priv = to_i915(dev);
1da51581
ID		 2809 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2810 int i;
2811
2812 mutex_lock(&power_domains->lock);
2813
2814 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2815 for (i = 0; i < power_domains->power_well_count; i++) {
2816 struct i915_power_well *power_well;
2817 enum intel_display_power_domain power_domain;
2818
2819 power_well = &power_domains->power_wells[i];
2820 seq_printf(m, "%-25s %d\n", power_well->name,
2821 power_well->count);
2822
2823 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2824 power_domain++) {
2825 if (!(BIT(power_domain) & power_well->domains))
2826 continue;
2827
2828 seq_printf(m, " %-23s %d\n",
9895ad03 2829 intel_display_power_domain_str(power_domain),
1da51581
ID		 2830 power_domains->domain_use_count[power_domain]);
2831 }
2832 }
2833
2834 mutex_unlock(&power_domains->lock);
2835
2836 return 0;
2837}
2838
b7cec66d
DL		 2839static int i915_dmc_info(struct seq_file *m, void *unused)
2840{
2841 struct drm_info_node *node = m->private;
2842 struct drm_device *dev = node->minor->dev;
fac5e23e 2843 struct drm_i915_private *dev_priv = to_i915(dev);
b7cec66d
DL		 2844 struct intel_csr *csr;
2845
2846 if (!HAS_CSR(dev)) {
2847 seq_puts(m, "not supported\n");
2848 return 0;
2849 }
2850
2851 csr = &dev_priv->csr;
2852
6fb403de
MK		 2853 intel_runtime_pm_get(dev_priv);
2854
b7cec66d
DL		 2855 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2856 seq_printf(m, "path: %s\n", csr->fw_path);
2857
2858 if (!csr->dmc_payload)
6fb403de 2859 goto out;
b7cec66d
DL		 2860
2861 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2862 CSR_VERSION_MINOR(csr->version));
2863
8337206d
DL		 2864 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2865 seq_printf(m, "DC3 -> DC5 count: %d\n",
2866 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2867 seq_printf(m, "DC5 -> DC6 count: %d\n",
2868 I915_READ(SKL_CSR_DC5_DC6_COUNT));
16e11b99
MK		 2869 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2870 seq_printf(m, "DC3 -> DC5 count: %d\n",
2871 I915_READ(BXT_CSR_DC3_DC5_COUNT));
8337206d
DL		 2872 }
2873
6fb403de
MK		 2874out:
2875 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2876 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2877 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2878
8337206d
DL		 2879 intel_runtime_pm_put(dev_priv);
2880
b7cec66d
DL		 2881 return 0;
2882}
2883
53f5e3ca
JB		 2884static void intel_seq_print_mode(struct seq_file *m, int tabs,
2885 struct drm_display_mode *mode)
2886{
2887 int i;
2888
2889 for (i = 0; i < tabs; i++)
2890 seq_putc(m, '\t');
2891
2892 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2893 mode->base.id, mode->name,
2894 mode->vrefresh, mode->clock,
2895 mode->hdisplay, mode->hsync_start,
2896 mode->hsync_end, mode->htotal,
2897 mode->vdisplay, mode->vsync_start,
2898 mode->vsync_end, mode->vtotal,
2899 mode->type, mode->flags);
2900}
2901
2902static void intel_encoder_info(struct seq_file *m,
2903 struct intel_crtc *intel_crtc,
2904 struct intel_encoder *intel_encoder)
2905{
9f25d007 2906 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2907 struct drm_device *dev = node->minor->dev;
2908 struct drm_crtc *crtc = &intel_crtc->base;
2909 struct intel_connector *intel_connector;
2910 struct drm_encoder *encoder;
2911
2912 encoder = &intel_encoder->base;
2913 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2914 encoder->base.id, encoder->name);
53f5e3ca
JB		 2915 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2916 struct drm_connector *connector = &intel_connector->base;
2917 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2918 connector->base.id,
c23cc417 2919 connector->name,
53f5e3ca
JB		 2920 drm_get_connector_status_name(connector->status));
2921 if (connector->status == connector_status_connected) {
2922 struct drm_display_mode *mode = &crtc->mode;
2923 seq_printf(m, ", mode:\n");
2924 intel_seq_print_mode(m, 2, mode);
2925 } else {
2926 seq_putc(m, '\n');
2927 }
2928 }
2929}
2930
2931static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2932{
9f25d007 2933 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2934 struct drm_device *dev = node->minor->dev;
2935 struct drm_crtc *crtc = &intel_crtc->base;
2936 struct intel_encoder *intel_encoder;
23a48d53
ML		 2937 struct drm_plane_state *plane_state = crtc->primary->state;
2938 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2939
23a48d53 2940 if (fb)
5aa8a937 2941 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2942 fb->base.id, plane_state->src_x >> 16,
2943 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2944 else
2945 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2946 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2947 intel_encoder_info(m, intel_crtc, intel_encoder);
2948}
2949
2950static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2951{
2952 struct drm_display_mode *mode = panel->fixed_mode;
2953
2954 seq_printf(m, "\tfixed mode:\n");
2955 intel_seq_print_mode(m, 2, mode);
2956}
2957
2958static void intel_dp_info(struct seq_file *m,
2959 struct intel_connector *intel_connector)
2960{
2961 struct intel_encoder *intel_encoder = intel_connector->encoder;
2962 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2963
2964 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2965 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
b6dabe3b 2966 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
53f5e3ca
JB		 2967 intel_panel_info(m, &intel_connector->panel);
2968}
2969
2970static void intel_hdmi_info(struct seq_file *m,
2971 struct intel_connector *intel_connector)
2972{
2973 struct intel_encoder *intel_encoder = intel_connector->encoder;
2974 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2975
742f491d 2976 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2977}
2978
2979static void intel_lvds_info(struct seq_file *m,
2980 struct intel_connector *intel_connector)
2981{
2982 intel_panel_info(m, &intel_connector->panel);
2983}
2984
2985static void intel_connector_info(struct seq_file *m,
2986 struct drm_connector *connector)
2987{
2988 struct intel_connector *intel_connector = to_intel_connector(connector);
2989 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2990 struct drm_display_mode *mode;
53f5e3ca
JB		 2991
2992 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2993 connector->base.id, connector->name,
53f5e3ca
JB		 2994 drm_get_connector_status_name(connector->status));
2995 if (connector->status == connector_status_connected) {
2996 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2997 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2998 connector->display_info.width_mm,
2999 connector->display_info.height_mm);
3000 seq_printf(m, "\tsubpixel order: %s\n",
3001 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3002 seq_printf(m, "\tCEA rev: %d\n",
3003 connector->display_info.cea_rev);
3004 }
ee648a74
ML		 3005
3006 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3007 return;
3008
3009 switch (connector->connector_type) {
3010 case DRM_MODE_CONNECTOR_DisplayPort:
3011 case DRM_MODE_CONNECTOR_eDP:
3012 intel_dp_info(m, intel_connector);
3013 break;
3014 case DRM_MODE_CONNECTOR_LVDS:
3015 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
36cd7444 3016 intel_lvds_info(m, intel_connector);
ee648a74
ML		 3017 break;
3018 case DRM_MODE_CONNECTOR_HDMIA:
3019 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3020 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3021 intel_hdmi_info(m, intel_connector);
3022 break;
3023 default:
3024 break;
36cd7444 3025 }
53f5e3ca 3026
f103fc7d
JB		 3027 seq_printf(m, "\tmodes:\n");
3028 list_for_each_entry(mode, &connector->modes, head)
3029 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 3030}
3031
065f2ec2
CW		 3032static bool cursor_active(struct drm_device *dev, int pipe)
3033{
fac5e23e 3034 struct drm_i915_private *dev_priv = to_i915(dev);
065f2ec2
CW		 3035 u32 state;
3036
3037 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 3038 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
065f2ec2 3039 else
5efb3e28 3040 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 3041
3042 return state;
3043}
3044
3045static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3046{
fac5e23e 3047 struct drm_i915_private *dev_priv = to_i915(dev);
065f2ec2
CW		 3048 u32 pos;
3049
5efb3e28 3050 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 3051
3052 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3053 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3054 *x = -*x;
3055
3056 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3057 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3058 *y = -*y;
3059
3060 return cursor_active(dev, pipe);
3061}
3062
3abc4e09
RF		 3063static const char *plane_type(enum drm_plane_type type)
3064{
3065 switch (type) {
3066 case DRM_PLANE_TYPE_OVERLAY:
3067 return "OVL";
3068 case DRM_PLANE_TYPE_PRIMARY:
3069 return "PRI";
3070 case DRM_PLANE_TYPE_CURSOR:
3071 return "CUR";
3072 /*
3073 * Deliberately omitting default: to generate compiler warnings
3074 * when a new drm_plane_type gets added.
3075 */
3076 }
3077
3078 return "unknown";
3079}
3080
3081static const char *plane_rotation(unsigned int rotation)
3082{
3083 static char buf[48];
3084 /*
3085 * According to doc only one DRM_ROTATE_ is allowed but this
3086 * will print them all to visualize if the values are misused
3087 */
3088 snprintf(buf, sizeof(buf),
3089 "%s%s%s%s%s%s(0x%08x)",
3090 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3091 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3092 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3093 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3094 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3095 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3096 rotation);
3097
3098 return buf;
3099}
3100
3101static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3102{
3103 struct drm_info_node *node = m->private;
3104 struct drm_device *dev = node->minor->dev;
3105 struct intel_plane *intel_plane;
3106
3107 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3108 struct drm_plane_state *state;
3109 struct drm_plane *plane = &intel_plane->base;
3110
3111 if (!plane->state) {
3112 seq_puts(m, "plane->state is NULL!\n");
3113 continue;
3114 }
3115
3116 state = plane->state;
3117
3118 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3119 plane->base.id,
3120 plane_type(intel_plane->base.type),
3121 state->crtc_x, state->crtc_y,
3122 state->crtc_w, state->crtc_h,
3123 (state->src_x >> 16),
3124 ((state->src_x & 0xffff) * 15625) >> 10,
3125 (state->src_y >> 16),
3126 ((state->src_y & 0xffff) * 15625) >> 10,
3127 (state->src_w >> 16),
3128 ((state->src_w & 0xffff) * 15625) >> 10,
3129 (state->src_h >> 16),
3130 ((state->src_h & 0xffff) * 15625) >> 10,
3131 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3132 plane_rotation(state->rotation));
3133 }
3134}
3135
3136static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3137{
3138 struct intel_crtc_state *pipe_config;
3139 int num_scalers = intel_crtc->num_scalers;
3140 int i;
3141
3142 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3143
3144 /* Not all platformas have a scaler */
3145 if (num_scalers) {
3146 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3147 num_scalers,
3148 pipe_config->scaler_state.scaler_users,
3149 pipe_config->scaler_state.scaler_id);
3150
3151 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3152 struct intel_scaler *sc =
3153 &pipe_config->scaler_state.scalers[i];
3154
3155 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3156 i, yesno(sc->in_use), sc->mode);
3157 }
3158 seq_puts(m, "\n");
3159 } else {
3160 seq_puts(m, "\tNo scalers available on this platform\n");
3161 }
3162}
3163
53f5e3ca
JB		 3164static int i915_display_info(struct seq_file *m, void *unused)
3165{
9f25d007 3166 struct drm_info_node *node = m->private;
53f5e3ca 3167 struct drm_device *dev = node->minor->dev;
fac5e23e 3168 struct drm_i915_private *dev_priv = to_i915(dev);
065f2ec2 3169 struct intel_crtc *crtc;
53f5e3ca
JB		 3170 struct drm_connector *connector;
3171
b0e5ddf3 3172 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 3173 drm_modeset_lock_all(dev);
3174 seq_printf(m, "CRTC info\n");
3175 seq_printf(m, "---------\n");
d3fcc808 3176 for_each_intel_crtc(dev, crtc) {
065f2ec2 3177 bool active;
f77076c9 3178 struct intel_crtc_state *pipe_config;
065f2ec2 3179 int x, y;
53f5e3ca 3180
f77076c9
ML		 3181 pipe_config = to_intel_crtc_state(crtc->base.state);
3182
3abc4e09 3183 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
065f2ec2 3184 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9 3185 yesno(pipe_config->base.active),
3abc4e09
RF		 3186 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3187 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3188
f77076c9 3189 if (pipe_config->base.active) {
065f2ec2
CW		 3190 intel_crtc_info(m, crtc);
3191
a23dc658 3192 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 3193 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 3194 yesno(crtc->cursor_base),
3dd512fb
MR		 3195 x, y, crtc->base.cursor->state->crtc_w,
3196 crtc->base.cursor->state->crtc_h,
57127efa 3197 crtc->cursor_addr, yesno(active));
3abc4e09
RF		 3198 intel_scaler_info(m, crtc);
3199 intel_plane_info(m, crtc);
a23dc658 3200 }
cace841c
DV		 3201
3202 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3203 yesno(!crtc->cpu_fifo_underrun_disabled),
3204 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 3205 }
3206
3207 seq_printf(m, "\n");
3208 seq_printf(m, "Connector info\n");
3209 seq_printf(m, "--------------\n");
3210 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3211 intel_connector_info(m, connector);
3212 }
3213 drm_modeset_unlock_all(dev);
b0e5ddf3 3214 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 3215
3216 return 0;
3217}
3218
e04934cf
BW		 3219static int i915_semaphore_status(struct seq_file *m, void *unused)
3220{
3221 struct drm_info_node *node = (struct drm_info_node *) m->private;
3222 struct drm_device *dev = node->minor->dev;
fac5e23e 3223 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 3224 struct intel_engine_cs *engine;
e04934cf 3225 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
c3232b18
DG		 3226 enum intel_engine_id id;
3227 int j, ret;
e04934cf 3228
39df9190 3229 if (!i915.semaphores) {
e04934cf
BW		 3230 seq_puts(m, "Semaphores are disabled\n");
3231 return 0;
3232 }
3233
3234 ret = mutex_lock_interruptible(&dev->struct_mutex);
3235 if (ret)
3236 return ret;
03872064 3237 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 3238
3239 if (IS_BROADWELL(dev)) {
3240 struct page *page;
3241 uint64_t *seqno;
3242
3243 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3244
3245 seqno = (uint64_t *)kmap_atomic(page);
c3232b18 3246 for_each_engine_id(engine, dev_priv, id) {
e04934cf
BW		 3247 uint64_t offset;
3248
e2f80391 3249 seq_printf(m, "%s\n", engine->name);
e04934cf
BW		 3250
3251 seq_puts(m, " Last signal:");
3252 for (j = 0; j < num_rings; j++) {
c3232b18 3253 offset = id * I915_NUM_ENGINES + j;
e04934cf
BW		 3254 seq_printf(m, "0x%08llx (0x%02llx) ",
3255 seqno[offset], offset * 8);
3256 }
3257 seq_putc(m, '\n');
3258
3259 seq_puts(m, " Last wait: ");
3260 for (j = 0; j < num_rings; j++) {
c3232b18 3261 offset = id + (j * I915_NUM_ENGINES);
e04934cf
BW		 3262 seq_printf(m, "0x%08llx (0x%02llx) ",
3263 seqno[offset], offset * 8);
3264 }
3265 seq_putc(m, '\n');
3266
3267 }
3268 kunmap_atomic(seqno);
3269 } else {
3270 seq_puts(m, " Last signal:");
b4ac5afc 3271 for_each_engine(engine, dev_priv)
e04934cf
BW		 3272 for (j = 0; j < num_rings; j++)
3273 seq_printf(m, "0x%08x\n",
e2f80391 3274 I915_READ(engine->semaphore.mbox.signal[j]));
e04934cf
BW		 3275 seq_putc(m, '\n');
3276 }
3277
3278 seq_puts(m, "\nSync seqno:\n");
b4ac5afc
DG		 3279 for_each_engine(engine, dev_priv) {
3280 for (j = 0; j < num_rings; j++)
e2f80391
TU		 3281 seq_printf(m, " 0x%08x ",
3282 engine->semaphore.sync_seqno[j]);
e04934cf
BW		 3283 seq_putc(m, '\n');
3284 }
3285 seq_putc(m, '\n');
3286
03872064 3287 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3288 mutex_unlock(&dev->struct_mutex);
3289 return 0;
3290}
3291
728e29d7
DV		 3292static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3293{
3294 struct drm_info_node *node = (struct drm_info_node *) m->private;
3295 struct drm_device *dev = node->minor->dev;
fac5e23e 3296 struct drm_i915_private *dev_priv = to_i915(dev);
728e29d7
DV		 3297 int i;
3298
3299 drm_modeset_lock_all(dev);
3300 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3301 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3302
3303 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2dd66ebd
ML		 3304 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3305 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
728e29d7 3306 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3307 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3308 seq_printf(m, " dpll_md: 0x%08x\n",
3309 pll->config.hw_state.dpll_md);
3310 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3311 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3312 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3313 }
3314 drm_modeset_unlock_all(dev);
3315
3316 return 0;
3317}
3318
1ed1ef9d 3319static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3320{
3321 int i;
3322 int ret;
e2f80391 3323 struct intel_engine_cs *engine;
888b5995
AS		 3324 struct drm_info_node *node = (struct drm_info_node *) m->private;
3325 struct drm_device *dev = node->minor->dev;
fac5e23e 3326 struct drm_i915_private *dev_priv = to_i915(dev);
33136b06 3327 struct i915_workarounds *workarounds = &dev_priv->workarounds;
c3232b18 3328 enum intel_engine_id id;
888b5995 3329
888b5995
AS		 3330 ret = mutex_lock_interruptible(&dev->struct_mutex);
3331 if (ret)
3332 return ret;
3333
3334 intel_runtime_pm_get(dev_priv);
3335
33136b06 3336 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
c3232b18 3337 for_each_engine_id(engine, dev_priv, id)
33136b06 3338 seq_printf(m, "HW whitelist count for %s: %d\n",
c3232b18 3339 engine->name, workarounds->hw_whitelist_count[id]);
33136b06 3340 for (i = 0; i < workarounds->count; ++i) {
f0f59a00
VS		 3341 i915_reg_t addr;
3342 u32 mask, value, read;
2fa60f6d 3343 bool ok;
888b5995 3344
33136b06
AS		 3345 addr = workarounds->reg[i].addr;
3346 mask = workarounds->reg[i].mask;
3347 value = workarounds->reg[i].value;
2fa60f6d
MK		 3348 read = I915_READ(addr);
3349 ok = (value & mask) == (read & mask);
3350 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
f0f59a00 3351 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3352 }
3353
3354 intel_runtime_pm_put(dev_priv);
3355 mutex_unlock(&dev->struct_mutex);
3356
3357 return 0;
3358}
3359
c5511e44
DL		 3360static int i915_ddb_info(struct seq_file *m, void *unused)
3361{
3362 struct drm_info_node *node = m->private;
3363 struct drm_device *dev = node->minor->dev;
fac5e23e 3364 struct drm_i915_private *dev_priv = to_i915(dev);
c5511e44
DL		 3365 struct skl_ddb_allocation *ddb;
3366 struct skl_ddb_entry *entry;
3367 enum pipe pipe;
3368 int plane;
3369
2fcffe19
DL		 3370 if (INTEL_INFO(dev)->gen < 9)
3371 return 0;
3372
c5511e44
DL		 3373 drm_modeset_lock_all(dev);
3374
3375 ddb = &dev_priv->wm.skl_hw.ddb;
3376
3377 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3378
3379 for_each_pipe(dev_priv, pipe) {
3380 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3381
dd740780 3382 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3383 entry = &ddb->plane[pipe][plane];
3384 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3385 entry->start, entry->end,
3386 skl_ddb_entry_size(entry));
3387 }
3388
4969d33e 3389 entry = &ddb->plane[pipe][PLANE_CURSOR];
c5511e44
DL		 3390 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3391 entry->end, skl_ddb_entry_size(entry));
3392 }
3393
3394 drm_modeset_unlock_all(dev);
3395
3396 return 0;
3397}
3398
a54746e3
VK		 3399static void drrs_status_per_crtc(struct seq_file *m,
3400 struct drm_device *dev, struct intel_crtc *intel_crtc)
3401{
fac5e23e 3402 struct drm_i915_private *dev_priv = to_i915(dev);
a54746e3
VK		 3403 struct i915_drrs *drrs = &dev_priv->drrs;
3404 int vrefresh = 0;
26875fe5 3405 struct drm_connector *connector;
a54746e3 3406
26875fe5
ML		 3407 drm_for_each_connector(connector, dev) {
3408 if (connector->state->crtc != &intel_crtc->base)
3409 continue;
3410
3411 seq_printf(m, "%s:\n", connector->name);
a54746e3
VK		 3412 }
3413
3414 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3415 seq_puts(m, "\tVBT: DRRS_type: Static");
3416 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3417 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3418 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3419 seq_puts(m, "\tVBT: DRRS_type: None");
3420 else
3421 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3422
3423 seq_puts(m, "\n\n");
3424
f77076c9 3425 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3426 struct intel_panel *panel;
3427
3428 mutex_lock(&drrs->mutex);
3429 /* DRRS Supported */
3430 seq_puts(m, "\tDRRS Supported: Yes\n");
3431
3432 /* disable_drrs() will make drrs->dp NULL */
3433 if (!drrs->dp) {
3434 seq_puts(m, "Idleness DRRS: Disabled");
3435 mutex_unlock(&drrs->mutex);
3436 return;
3437 }
3438
3439 panel = &drrs->dp->attached_connector->panel;
3440 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3441 drrs->busy_frontbuffer_bits);
3442
3443 seq_puts(m, "\n\t\t");
3444 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3445 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3446 vrefresh = panel->fixed_mode->vrefresh;
3447 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3448 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3449 vrefresh = panel->downclock_mode->vrefresh;
3450 } else {
3451 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3452 drrs->refresh_rate_type);
3453 mutex_unlock(&drrs->mutex);
3454 return;
3455 }
3456 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3457
3458 seq_puts(m, "\n\t\t");
3459 mutex_unlock(&drrs->mutex);
3460 } else {
3461 /* DRRS not supported. Print the VBT parameter*/
3462 seq_puts(m, "\tDRRS Supported : No");
3463 }
3464 seq_puts(m, "\n");
3465}
3466
3467static int i915_drrs_status(struct seq_file *m, void *unused)
3468{
3469 struct drm_info_node *node = m->private;
3470 struct drm_device *dev = node->minor->dev;
3471 struct intel_crtc *intel_crtc;
3472 int active_crtc_cnt = 0;
3473
26875fe5 3474 drm_modeset_lock_all(dev);
a54746e3 3475 for_each_intel_crtc(dev, intel_crtc) {
f77076c9 3476 if (intel_crtc->base.state->active) {
a54746e3
VK		 3477 active_crtc_cnt++;
3478 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3479
3480 drrs_status_per_crtc(m, dev, intel_crtc);
3481 }
a54746e3 3482 }
26875fe5 3483 drm_modeset_unlock_all(dev);
a54746e3
VK		 3484
3485 if (!active_crtc_cnt)
3486 seq_puts(m, "No active crtc found\n");
3487
3488 return 0;
3489}
3490
07144428
DL		 3491struct pipe_crc_info {
3492 const char *name;
3493 struct drm_device *dev;
3494 enum pipe pipe;
3495};
3496
11bed958
DA		 3497static int i915_dp_mst_info(struct seq_file *m, void *unused)
3498{
3499 struct drm_info_node *node = (struct drm_info_node *) m->private;
3500 struct drm_device *dev = node->minor->dev;
11bed958
DA		 3501 struct intel_encoder *intel_encoder;
3502 struct intel_digital_port *intel_dig_port;
b6dabe3b
ML		 3503 struct drm_connector *connector;
3504
11bed958 3505 drm_modeset_lock_all(dev);
b6dabe3b
ML		 3506 drm_for_each_connector(connector, dev) {
3507 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
11bed958 3508 continue;
b6dabe3b
ML		 3509
3510 intel_encoder = intel_attached_encoder(connector);
3511 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3512 continue;
3513
3514 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
11bed958
DA		 3515 if (!intel_dig_port->dp.can_mst)
3516 continue;
b6dabe3b 3517
40ae80cc
JB		 3518 seq_printf(m, "MST Source Port %c\n",
3519 port_name(intel_dig_port->port));
11bed958
DA		 3520 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3521 }
3522 drm_modeset_unlock_all(dev);
3523 return 0;
3524}
3525
07144428
DL		 3526static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3527{
be5c7a90 3528 struct pipe_crc_info *info = inode->i_private;
fac5e23e 3529 struct drm_i915_private *dev_priv = to_i915(info->dev);
be5c7a90
DL		 3530 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3531
7eb1c496
DV		 3532 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3533 return -ENODEV;
3534
d538bbdf
DL		 3535 spin_lock_irq(&pipe_crc->lock);
3536
3537 if (pipe_crc->opened) {
3538 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3539 return -EBUSY; /* already open */
3540 }
3541
d538bbdf 3542 pipe_crc->opened = true;
07144428
DL		 3543 filep->private_data = inode->i_private;
3544
d538bbdf
DL		 3545 spin_unlock_irq(&pipe_crc->lock);
3546
07144428
DL		 3547 return 0;
3548}
3549
3550static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3551{
be5c7a90 3552 struct pipe_crc_info *info = inode->i_private;
fac5e23e 3553 struct drm_i915_private *dev_priv = to_i915(info->dev);
be5c7a90
DL		 3554 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3555
d538bbdf
DL		 3556 spin_lock_irq(&pipe_crc->lock);
3557 pipe_crc->opened = false;
3558 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3559
07144428
DL		 3560 return 0;
3561}
3562
3563/* (6 fields, 8 chars each, space separated (5) + '\n') */
3564#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3565/* account for \'0' */
3566#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3567
3568static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3569{
d538bbdf
DL		 3570 assert_spin_locked(&pipe_crc->lock);
3571 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3572 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3573}
3574
3575static ssize_t
3576i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3577 loff_t *pos)
3578{
3579 struct pipe_crc_info *info = filep->private_data;
3580 struct drm_device *dev = info->dev;
fac5e23e 3581 struct drm_i915_private *dev_priv = to_i915(dev);
07144428
DL		 3582 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3583 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3584 int n_entries;
07144428
DL		 3585 ssize_t bytes_read;
3586
3587 /*
3588 * Don't allow user space to provide buffers not big enough to hold
3589 * a line of data.
3590 */
3591 if (count < PIPE_CRC_LINE_LEN)
3592 return -EINVAL;
3593
3594 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3595 return 0;
07144428
DL		 3596
3597 /* nothing to read */
d538bbdf 3598 spin_lock_irq(&pipe_crc->lock);
07144428 3599 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3600 int ret;
3601
3602 if (filep->f_flags & O_NONBLOCK) {
3603 spin_unlock_irq(&pipe_crc->lock);
07144428 3604 return -EAGAIN;
d538bbdf 3605 }
07144428 3606
d538bbdf
DL		 3607 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3608 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3609 if (ret) {
3610 spin_unlock_irq(&pipe_crc->lock);
3611 return ret;
3612 }
8bf1e9f1
SH		 3613 }
3614
07144428 3615 /* We now have one or more entries to read */
9ad6d99f 3616 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3617
07144428 3618 bytes_read = 0;
9ad6d99f
VS		 3619 while (n_entries > 0) {
3620 struct intel_pipe_crc_entry *entry =
3621 &pipe_crc->entries[pipe_crc->tail];
07144428 3622 int ret;
8bf1e9f1 3623
9ad6d99f
VS		 3624 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3625 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3626 break;
3627
3628 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3629 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3630
07144428
DL		 3631 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3632 "%8u %8x %8x %8x %8x %8x\n",
3633 entry->frame, entry->crc[0],
3634 entry->crc[1], entry->crc[2],
3635 entry->crc[3], entry->crc[4]);
3636
9ad6d99f
VS		 3637 spin_unlock_irq(&pipe_crc->lock);
3638
3639 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3640 if (ret == PIPE_CRC_LINE_LEN)
3641 return -EFAULT;
b2c88f5b 3642
9ad6d99f
VS		 3643 user_buf += PIPE_CRC_LINE_LEN;
3644 n_entries--;
3645
3646 spin_lock_irq(&pipe_crc->lock);
3647 }
8bf1e9f1 3648
d538bbdf
DL		 3649 spin_unlock_irq(&pipe_crc->lock);
3650
07144428
DL		 3651 return bytes_read;
3652}
3653
3654static const struct file_operations i915_pipe_crc_fops = {
3655 .owner = THIS_MODULE,
3656 .open = i915_pipe_crc_open,
3657 .read = i915_pipe_crc_read,
3658 .release = i915_pipe_crc_release,
3659};
3660
3661static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3662 {
3663 .name = "i915_pipe_A_crc",
3664 .pipe = PIPE_A,
3665 },
3666 {
3667 .name = "i915_pipe_B_crc",
3668 .pipe = PIPE_B,
3669 },
3670 {
3671 .name = "i915_pipe_C_crc",
3672 .pipe = PIPE_C,
3673 },
3674};
3675
3676static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3677 enum pipe pipe)
3678{
3679 struct drm_device *dev = minor->dev;
3680 struct dentry *ent;
3681 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3682
3683 info->dev = dev;
3684 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3685 &i915_pipe_crc_fops);
f3c5fe97
WY		 3686 if (!ent)
3687 return -ENOMEM;
07144428
DL		 3688
3689 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3690}
3691
e8dfcf78 3692static const char * const pipe_crc_sources[] = {
926321d5
DV		 3693 "none",
3694 "plane1",
3695 "plane2",
3696 "pf",
5b3a856b 3697 "pipe",
3d099a05
DV		 3698 "TV",
3699 "DP-B",
3700 "DP-C",
3701 "DP-D",
46a19188 3702 "auto",
926321d5
DV		 3703};
3704
3705static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3706{
3707 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3708 return pipe_crc_sources[source];
3709}
3710
bd9db02f 3711static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3712{
3713 struct drm_device *dev = m->private;
fac5e23e 3714 struct drm_i915_private *dev_priv = to_i915(dev);
926321d5
DV		 3715 int i;
3716
3717 for (i = 0; i < I915_MAX_PIPES; i++)
3718 seq_printf(m, "%c %s\n", pipe_name(i),
3719 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3720
3721 return 0;
3722}
3723
bd9db02f 3724static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3725{
3726 struct drm_device *dev = inode->i_private;
3727
bd9db02f 3728 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3729}
3730
46a19188 3731static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3732 uint32_t *val)
3733{
46a19188
DV		 3734 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3735 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3736
3737 switch (*source) {
52f843f6
DV		 3738 case INTEL_PIPE_CRC_SOURCE_PIPE:
3739 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3740 break;
3741 case INTEL_PIPE_CRC_SOURCE_NONE:
3742 *val = 0;
3743 break;
3744 default:
3745 return -EINVAL;
3746 }
3747
3748 return 0;
3749}
3750
46a19188
DV		 3751static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3752 enum intel_pipe_crc_source *source)
3753{
3754 struct intel_encoder *encoder;
3755 struct intel_crtc *crtc;
26756809 3756 struct intel_digital_port *dig_port;
46a19188
DV		 3757 int ret = 0;
3758
3759 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3760
6e9f798d 3761 drm_modeset_lock_all(dev);
b2784e15 3762 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3763 if (!encoder->base.crtc)
3764 continue;
3765
3766 crtc = to_intel_crtc(encoder->base.crtc);
3767
3768 if (crtc->pipe != pipe)
3769 continue;
3770
3771 switch (encoder->type) {
3772 case INTEL_OUTPUT_TVOUT:
3773 *source = INTEL_PIPE_CRC_SOURCE_TV;
3774 break;
cca0502b 3775 case INTEL_OUTPUT_DP:
46a19188 3776 case INTEL_OUTPUT_EDP:
26756809
DV		 3777 dig_port = enc_to_dig_port(&encoder->base);
3778 switch (dig_port->port) {
3779 case PORT_B:
3780 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3781 break;
3782 case PORT_C:
3783 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3784 break;
3785 case PORT_D:
3786 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3787 break;
3788 default:
3789 WARN(1, "nonexisting DP port %c\n",
3790 port_name(dig_port->port));
3791 break;
3792 }
46a19188 3793 break;
6847d71b
PZ		 3794 default:
3795 break;
46a19188
DV		 3796 }
3797 }
6e9f798d 3798 drm_modeset_unlock_all(dev);
46a19188
DV		 3799
3800 return ret;
3801}
3802
3803static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3804 enum pipe pipe,
3805 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3806 uint32_t *val)
3807{
fac5e23e 3808 struct drm_i915_private *dev_priv = to_i915(dev);
8d2f24ca
DV		 3809 bool need_stable_symbols = false;
3810
46a19188
DV		 3811 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3812 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3813 if (ret)
3814 return ret;
3815 }
3816
3817 switch (*source) {
7ac0129b
DV		 3818 case INTEL_PIPE_CRC_SOURCE_PIPE:
3819 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3820 break;
3821 case INTEL_PIPE_CRC_SOURCE_DP_B:
3822 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3823 need_stable_symbols = true;
7ac0129b
DV		 3824 break;
3825 case INTEL_PIPE_CRC_SOURCE_DP_C:
3826 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3827 need_stable_symbols = true;
7ac0129b 3828 break;
2be57922
VS		 3829 case INTEL_PIPE_CRC_SOURCE_DP_D:
3830 if (!IS_CHERRYVIEW(dev))
3831 return -EINVAL;
3832 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3833 need_stable_symbols = true;
3834 break;
7ac0129b
DV		 3835 case INTEL_PIPE_CRC_SOURCE_NONE:
3836 *val = 0;
3837 break;
3838 default:
3839 return -EINVAL;
3840 }
3841
8d2f24ca
DV		 3842 /*
3843 * When the pipe CRC tap point is after the transcoders we need
3844 * to tweak symbol-level features to produce a deterministic series of
3845 * symbols for a given frame. We need to reset those features only once
3846 * a frame (instead of every nth symbol):
3847 * - DC-balance: used to ensure a better clock recovery from the data
3848 * link (SDVO)
3849 * - DisplayPort scrambling: used for EMI reduction
3850 */
3851 if (need_stable_symbols) {
3852 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3853
8d2f24ca 3854 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3855 switch (pipe) {
3856 case PIPE_A:
8d2f24ca 3857 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3858 break;
3859 case PIPE_B:
8d2f24ca 3860 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3861 break;
3862 case PIPE_C:
3863 tmp |= PIPE_C_SCRAMBLE_RESET;
3864 break;
3865 default:
3866 return -EINVAL;
3867 }
8d2f24ca
DV		 3868 I915_WRITE(PORT_DFT2_G4X, tmp);
3869 }
3870
7ac0129b
DV		 3871 return 0;
3872}
3873
4b79ebf7 3874static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3875 enum pipe pipe,
3876 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3877 uint32_t *val)
3878{
fac5e23e 3879 struct drm_i915_private *dev_priv = to_i915(dev);
84093603
DV		 3880 bool need_stable_symbols = false;
3881
46a19188
DV		 3882 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3883 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3884 if (ret)
3885 return ret;
3886 }
3887
3888 switch (*source) {
4b79ebf7
DV		 3889 case INTEL_PIPE_CRC_SOURCE_PIPE:
3890 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3891 break;
3892 case INTEL_PIPE_CRC_SOURCE_TV:
3893 if (!SUPPORTS_TV(dev))
3894 return -EINVAL;
3895 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3896 break;
3897 case INTEL_PIPE_CRC_SOURCE_DP_B:
3898 if (!IS_G4X(dev))
3899 return -EINVAL;
3900 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3901 need_stable_symbols = true;
4b79ebf7
DV		 3902 break;
3903 case INTEL_PIPE_CRC_SOURCE_DP_C:
3904 if (!IS_G4X(dev))
3905 return -EINVAL;
3906 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3907 need_stable_symbols = true;
4b79ebf7
DV		 3908 break;
3909 case INTEL_PIPE_CRC_SOURCE_DP_D:
3910 if (!IS_G4X(dev))
3911 return -EINVAL;
3912 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3913 need_stable_symbols = true;
4b79ebf7
DV		 3914 break;
3915 case INTEL_PIPE_CRC_SOURCE_NONE:
3916 *val = 0;
3917 break;
3918 default:
3919 return -EINVAL;
3920 }
3921
84093603
DV		 3922 /*
3923 * When the pipe CRC tap point is after the transcoders we need
3924 * to tweak symbol-level features to produce a deterministic series of
3925 * symbols for a given frame. We need to reset those features only once
3926 * a frame (instead of every nth symbol):
3927 * - DC-balance: used to ensure a better clock recovery from the data
3928 * link (SDVO)
3929 * - DisplayPort scrambling: used for EMI reduction
3930 */
3931 if (need_stable_symbols) {
3932 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3933
3934 WARN_ON(!IS_G4X(dev));
3935
3936 I915_WRITE(PORT_DFT_I9XX,
3937 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3938
3939 if (pipe == PIPE_A)
3940 tmp |= PIPE_A_SCRAMBLE_RESET;
3941 else
3942 tmp |= PIPE_B_SCRAMBLE_RESET;
3943
3944 I915_WRITE(PORT_DFT2_G4X, tmp);
3945 }
3946
4b79ebf7
DV		 3947 return 0;
3948}
3949
8d2f24ca
DV		 3950static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3951 enum pipe pipe)
3952{
fac5e23e 3953 struct drm_i915_private *dev_priv = to_i915(dev);
8d2f24ca
DV		 3954 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3955
eb736679
VS		 3956 switch (pipe) {
3957 case PIPE_A:
8d2f24ca 3958 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3959 break;
3960 case PIPE_B:
8d2f24ca 3961 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3962 break;
3963 case PIPE_C:
3964 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3965 break;
3966 default:
3967 return;
3968 }
8d2f24ca
DV		 3969 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3970 tmp &= ~DC_BALANCE_RESET_VLV;
3971 I915_WRITE(PORT_DFT2_G4X, tmp);
3972
3973}
3974
84093603
DV		 3975static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3976 enum pipe pipe)
3977{
fac5e23e 3978 struct drm_i915_private *dev_priv = to_i915(dev);
84093603
DV		 3979 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3980
3981 if (pipe == PIPE_A)
3982 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3983 else
3984 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3985 I915_WRITE(PORT_DFT2_G4X, tmp);
3986
3987 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3988 I915_WRITE(PORT_DFT_I9XX,
3989 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3990 }
3991}
3992
46a19188 3993static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3994 uint32_t *val)
3995{
46a19188
DV		 3996 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3997 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3998
3999 switch (*source) {
5b3a856b
DV		 4000 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4001 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4002 break;
4003 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4004 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4005 break;
5b3a856b
DV		 4006 case INTEL_PIPE_CRC_SOURCE_PIPE:
4007 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4008 break;
3d099a05 4009 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 4010 *val = 0;
4011 break;
3d099a05
DV		 4012 default:
4013 return -EINVAL;
5b3a856b
DV		 4014 }
4015
4016 return 0;
4017}
4018
c4e2d043 4019static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51 4020{
fac5e23e 4021 struct drm_i915_private *dev_priv = to_i915(dev);
fabf6e51
DV		 4022 struct intel_crtc *crtc =
4023 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 4024 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 4025 struct drm_atomic_state *state;
4026 int ret = 0;
fabf6e51
DV		 4027
4028 drm_modeset_lock_all(dev);
c4e2d043
ML		 4029 state = drm_atomic_state_alloc(dev);
4030 if (!state) {
4031 ret = -ENOMEM;
4032 goto out;
fabf6e51 4033 }
fabf6e51 4034
c4e2d043
ML		 4035 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4036 pipe_config = intel_atomic_get_crtc_state(state, crtc);
4037 if (IS_ERR(pipe_config)) {
4038 ret = PTR_ERR(pipe_config);
4039 goto out;
4040 }
fabf6e51 4041
c4e2d043
ML		 4042 pipe_config->pch_pfit.force_thru = enable;
4043 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4044 pipe_config->pch_pfit.enabled != enable)
4045 pipe_config->base.connectors_changed = true;
1b509259 4046
c4e2d043
ML		 4047 ret = drm_atomic_commit(state);
4048out:
fabf6e51 4049 drm_modeset_unlock_all(dev);
c4e2d043
ML		 4050 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4051 if (ret)
4052 drm_atomic_state_free(state);
fabf6e51
DV		 4053}
4054
4055static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4056 enum pipe pipe,
4057 enum intel_pipe_crc_source *source,
5b3a856b
DV		 4058 uint32_t *val)
4059{
46a19188
DV		 4060 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4061 *source = INTEL_PIPE_CRC_SOURCE_PF;
4062
4063 switch (*source) {
5b3a856b
DV		 4064 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4065 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4066 break;
4067 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4068 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4069 break;
4070 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 4071 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4072 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 4073
5b3a856b
DV		 4074 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4075 break;
3d099a05 4076 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 4077 *val = 0;
4078 break;
3d099a05
DV		 4079 default:
4080 return -EINVAL;
5b3a856b
DV		 4081 }
4082
4083 return 0;
4084}
4085
926321d5
DV		 4086static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4087 enum intel_pipe_crc_source source)
4088{
fac5e23e 4089 struct drm_i915_private *dev_priv = to_i915(dev);
cc3da175 4090 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 4091 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4092 pipe));
e129649b 4093 enum intel_display_power_domain power_domain;
432f3342 4094 u32 val = 0; /* shut up gcc */
5b3a856b 4095 int ret;
926321d5 4096
cc3da175
DL		 4097 if (pipe_crc->source == source)
4098 return 0;
4099
ae676fcd
DL		 4100 /* forbid changing the source without going back to 'none' */
4101 if (pipe_crc->source && source)
4102 return -EINVAL;
4103
e129649b
ID		 4104 power_domain = POWER_DOMAIN_PIPE(pipe);
4105 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9d8b0588
DV		 4106 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4107 return -EIO;
4108 }
4109
52f843f6 4110 if (IS_GEN2(dev))
46a19188 4111 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 4112 else if (INTEL_INFO(dev)->gen < 5)
46a19188 4113 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
666a4537 4114 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
fabf6e51 4115 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 4116 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 4117 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 4118 else
fabf6e51 4119 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 4120
4121 if (ret != 0)
e129649b 4122 goto out;
5b3a856b 4123
4b584369
DL		 4124 /* none -> real source transition */
4125 if (source) {
4252fbc3
VS		 4126 struct intel_pipe_crc_entry *entries;
4127
7cd6ccff
DL		 4128 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4129 pipe_name(pipe), pipe_crc_source_name(source));
4130
3cf54b34
VS		 4131 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4132 sizeof(pipe_crc->entries[0]),
4252fbc3 4133 GFP_KERNEL);
e129649b
ID		 4134 if (!entries) {
4135 ret = -ENOMEM;
4136 goto out;
4137 }
e5f75aca 4138
8c740dce
PZ		 4139 /*
4140 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4141 * enabled and disabled dynamically based on package C states,
4142 * user space can't make reliable use of the CRCs, so let's just
4143 * completely disable it.
4144 */
4145 hsw_disable_ips(crtc);
4146
d538bbdf 4147 spin_lock_irq(&pipe_crc->lock);
64387b61 4148 kfree(pipe_crc->entries);
4252fbc3 4149 pipe_crc->entries = entries;
d538bbdf
DL		 4150 pipe_crc->head = 0;
4151 pipe_crc->tail = 0;
4152 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 4153 }
4154
cc3da175 4155 pipe_crc->source = source;
926321d5 4156
926321d5
DV		 4157 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4158 POSTING_READ(PIPE_CRC_CTL(pipe));
4159
e5f75aca
DL		 4160 /* real source -> none transition */
4161 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 4162 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 4163 struct intel_crtc *crtc =
4164 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 4165
7cd6ccff
DL		 4166 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4167 pipe_name(pipe));
4168
a33d7105 4169 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 4170 if (crtc->base.state->active)
a33d7105
DV		 4171 intel_wait_for_vblank(dev, pipe);
4172 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 4173
d538bbdf
DL		 4174 spin_lock_irq(&pipe_crc->lock);
4175 entries = pipe_crc->entries;
e5f75aca 4176 pipe_crc->entries = NULL;
9ad6d99f
VS		 4177 pipe_crc->head = 0;
4178 pipe_crc->tail = 0;
d538bbdf
DL		 4179 spin_unlock_irq(&pipe_crc->lock);
4180
4181 kfree(entries);
84093603
DV		 4182
4183 if (IS_G4X(dev))
4184 g4x_undo_pipe_scramble_reset(dev, pipe);
666a4537 4185 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
8d2f24ca 4186 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 4187 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4188 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 4189
4190 hsw_enable_ips(crtc);
e5f75aca
DL		 4191 }
4192
e129649b
ID		 4193 ret = 0;
4194
4195out:
4196 intel_display_power_put(dev_priv, power_domain);
4197
4198 return ret;
926321d5
DV		 4199}
4200
4201/*
4202 * Parse pipe CRC command strings:
b94dec87
DL		 4203 * command: wsp* object wsp+ name wsp+ source wsp*
4204 * object: 'pipe'
4205 * name: (A | B | C)
926321d5
DV		 4206 * source: (none | plane1 | plane2 | pf)
4207 * wsp: (#0x20 | #0x9 | #0xA)+
4208 *
4209 * eg.:
b94dec87
DL		 4210 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4211 * "pipe A none" -> Stop CRC
926321d5 4212 */
bd9db02f 4213static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 4214{
4215 int n_words = 0;
4216
4217 while (*buf) {
4218 char *end;
4219
4220 /* skip leading white space */
4221 buf = skip_spaces(buf);
4222 if (!*buf)
4223 break; /* end of buffer */
4224
4225 /* find end of word */
4226 for (end = buf; *end && !isspace(*end); end++)
4227 ;
4228
4229 if (n_words == max_words) {
4230 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4231 max_words);
4232 return -EINVAL; /* ran out of words[] before bytes */
4233 }
4234
4235 if (*end)
4236 *end++ = '\0';
4237 words[n_words++] = buf;
4238 buf = end;
4239 }
4240
4241 return n_words;
4242}
4243
b94dec87
DL		 4244enum intel_pipe_crc_object {
4245 PIPE_CRC_OBJECT_PIPE,
4246};
4247
e8dfcf78 4248static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4249 "pipe",
4250};
4251
4252static int
bd9db02f 4253display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4254{
4255 int i;
4256
4257 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4258 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4259 *o = i;
b94dec87
DL		 4260 return 0;
4261 }
4262
4263 return -EINVAL;
4264}
4265
bd9db02f 4266static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4267{
4268 const char name = buf[0];
4269
4270 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4271 return -EINVAL;
4272
4273 *pipe = name - 'A';
4274
4275 return 0;
4276}
4277
4278static int
bd9db02f 4279display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4280{
4281 int i;
4282
4283 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4284 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4285 *s = i;
926321d5
DV		 4286 return 0;
4287 }
4288
4289 return -EINVAL;
4290}
4291
bd9db02f 4292static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 4293{
b94dec87 4294#define N_WORDS 3
926321d5 4295 int n_words;
b94dec87 4296 char *words[N_WORDS];
926321d5 4297 enum pipe pipe;
b94dec87 4298 enum intel_pipe_crc_object object;
926321d5
DV		 4299 enum intel_pipe_crc_source source;
4300
bd9db02f 4301 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4302 if (n_words != N_WORDS) {
4303 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4304 N_WORDS);
4305 return -EINVAL;
4306 }
4307
bd9db02f 4308 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4309 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4310 return -EINVAL;
4311 }
4312
bd9db02f 4313 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4314 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4315 return -EINVAL;
4316 }
4317
bd9db02f 4318 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4319 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4320 return -EINVAL;
4321 }
4322
4323 return pipe_crc_set_source(dev, pipe, source);
4324}
4325
bd9db02f
DL		 4326static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4327 size_t len, loff_t *offp)
926321d5
DV		 4328{
4329 struct seq_file *m = file->private_data;
4330 struct drm_device *dev = m->private;
4331 char *tmpbuf;
4332 int ret;
4333
4334 if (len == 0)
4335 return 0;
4336
4337 if (len > PAGE_SIZE - 1) {
4338 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4339 PAGE_SIZE);
4340 return -E2BIG;
4341 }
4342
4343 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4344 if (!tmpbuf)
4345 return -ENOMEM;
4346
4347 if (copy_from_user(tmpbuf, ubuf, len)) {
4348 ret = -EFAULT;
4349 goto out;
4350 }
4351 tmpbuf[len] = '\0';
4352
bd9db02f 4353 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4354
4355out:
4356 kfree(tmpbuf);
4357 if (ret < 0)
4358 return ret;
4359
4360 *offp += len;
4361 return len;
4362}
4363
bd9db02f 4364static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4365 .owner = THIS_MODULE,
bd9db02f 4366 .open = display_crc_ctl_open,
926321d5
DV		 4367 .read = seq_read,
4368 .llseek = seq_lseek,
4369 .release = single_release,
bd9db02f 4370 .write = display_crc_ctl_write
926321d5
DV		 4371};
4372
eb3394fa
TP		 4373static ssize_t i915_displayport_test_active_write(struct file *file,
4374 const char __user *ubuf,
4375 size_t len, loff_t *offp)
4376{
4377 char *input_buffer;
4378 int status = 0;
eb3394fa
TP		 4379 struct drm_device *dev;
4380 struct drm_connector *connector;
4381 struct list_head *connector_list;
4382 struct intel_dp *intel_dp;
4383 int val = 0;
4384
9aaffa34 4385 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4386
eb3394fa
TP		 4387 connector_list = &dev->mode_config.connector_list;
4388
4389 if (len == 0)
4390 return 0;
4391
4392 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4393 if (!input_buffer)
4394 return -ENOMEM;
4395
4396 if (copy_from_user(input_buffer, ubuf, len)) {
4397 status = -EFAULT;
4398 goto out;
4399 }
4400
4401 input_buffer[len] = '\0';
4402 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4403
4404 list_for_each_entry(connector, connector_list, head) {
4405
4406 if (connector->connector_type !=
4407 DRM_MODE_CONNECTOR_DisplayPort)
4408 continue;
4409
b8bb08ec 4410 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4411 connector->encoder != NULL) {
4412 intel_dp = enc_to_intel_dp(connector->encoder);
4413 status = kstrtoint(input_buffer, 10, &val);
4414 if (status < 0)
4415 goto out;
4416 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4417 /* To prevent erroneous activation of the compliance
4418 * testing code, only accept an actual value of 1 here
4419 */
4420 if (val == 1)
4421 intel_dp->compliance_test_active = 1;
4422 else
4423 intel_dp->compliance_test_active = 0;
4424 }
4425 }
4426out:
4427 kfree(input_buffer);
4428 if (status < 0)
4429 return status;
4430
4431 *offp += len;
4432 return len;
4433}
4434
4435static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4436{
4437 struct drm_device *dev = m->private;
4438 struct drm_connector *connector;
4439 struct list_head *connector_list = &dev->mode_config.connector_list;
4440 struct intel_dp *intel_dp;
4441
eb3394fa
TP		 4442 list_for_each_entry(connector, connector_list, head) {
4443
4444 if (connector->connector_type !=
4445 DRM_MODE_CONNECTOR_DisplayPort)
4446 continue;
4447
4448 if (connector->status == connector_status_connected &&
4449 connector->encoder != NULL) {
4450 intel_dp = enc_to_intel_dp(connector->encoder);
4451 if (intel_dp->compliance_test_active)
4452 seq_puts(m, "1");
4453 else
4454 seq_puts(m, "0");
4455 } else
4456 seq_puts(m, "0");
4457 }
4458
4459 return 0;
4460}
4461
4462static int i915_displayport_test_active_open(struct inode *inode,
4463 struct file *file)
4464{
4465 struct drm_device *dev = inode->i_private;
4466
4467 return single_open(file, i915_displayport_test_active_show, dev);
4468}
4469
4470static const struct file_operations i915_displayport_test_active_fops = {
4471 .owner = THIS_MODULE,
4472 .open = i915_displayport_test_active_open,
4473 .read = seq_read,
4474 .llseek = seq_lseek,
4475 .release = single_release,
4476 .write = i915_displayport_test_active_write
4477};
4478
4479static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4480{
4481 struct drm_device *dev = m->private;
4482 struct drm_connector *connector;
4483 struct list_head *connector_list = &dev->mode_config.connector_list;
4484 struct intel_dp *intel_dp;
4485
eb3394fa
TP		 4486 list_for_each_entry(connector, connector_list, head) {
4487
4488 if (connector->connector_type !=
4489 DRM_MODE_CONNECTOR_DisplayPort)
4490 continue;
4491
4492 if (connector->status == connector_status_connected &&
4493 connector->encoder != NULL) {
4494 intel_dp = enc_to_intel_dp(connector->encoder);
4495 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4496 } else
4497 seq_puts(m, "0");
4498 }
4499
4500 return 0;
4501}
4502static int i915_displayport_test_data_open(struct inode *inode,
4503 struct file *file)
4504{
4505 struct drm_device *dev = inode->i_private;
4506
4507 return single_open(file, i915_displayport_test_data_show, dev);
4508}
4509
4510static const struct file_operations i915_displayport_test_data_fops = {
4511 .owner = THIS_MODULE,
4512 .open = i915_displayport_test_data_open,
4513 .read = seq_read,
4514 .llseek = seq_lseek,
4515 .release = single_release
4516};
4517
4518static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4519{
4520 struct drm_device *dev = m->private;
4521 struct drm_connector *connector;
4522 struct list_head *connector_list = &dev->mode_config.connector_list;
4523 struct intel_dp *intel_dp;
4524
eb3394fa
TP		 4525 list_for_each_entry(connector, connector_list, head) {
4526
4527 if (connector->connector_type !=
4528 DRM_MODE_CONNECTOR_DisplayPort)
4529 continue;
4530
4531 if (connector->status == connector_status_connected &&
4532 connector->encoder != NULL) {
4533 intel_dp = enc_to_intel_dp(connector->encoder);
4534 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4535 } else
4536 seq_puts(m, "0");
4537 }
4538
4539 return 0;
4540}
4541
4542static int i915_displayport_test_type_open(struct inode *inode,
4543 struct file *file)
4544{
4545 struct drm_device *dev = inode->i_private;
4546
4547 return single_open(file, i915_displayport_test_type_show, dev);
4548}
4549
4550static const struct file_operations i915_displayport_test_type_fops = {
4551 .owner = THIS_MODULE,
4552 .open = i915_displayport_test_type_open,
4553 .read = seq_read,
4554 .llseek = seq_lseek,
4555 .release = single_release
4556};
4557
97e94b22 4558static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4559{
4560 struct drm_device *dev = m->private;
369a1342 4561 int level;
de38b95c
VS		 4562 int num_levels;
4563
4564 if (IS_CHERRYVIEW(dev))
4565 num_levels = 3;
4566 else if (IS_VALLEYVIEW(dev))
4567 num_levels = 1;
4568 else
4569 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4570
4571 drm_modeset_lock_all(dev);
4572
4573 for (level = 0; level < num_levels; level++) {
4574 unsigned int latency = wm[level];
4575
97e94b22
DL		 4576 /*
4577 * - WM1+ latency values in 0.5us units
de38b95c 4578 * - latencies are in us on gen9/vlv/chv
97e94b22 4579 */
666a4537
WB		 4580 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4581 IS_CHERRYVIEW(dev))
97e94b22
DL		 4582 latency *= 10;
4583 else if (level > 0)
369a1342
VS		 4584 latency *= 5;
4585
4586 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4587 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4588 }
4589
4590 drm_modeset_unlock_all(dev);
4591}
4592
4593static int pri_wm_latency_show(struct seq_file *m, void *data)
4594{
4595 struct drm_device *dev = m->private;
fac5e23e 4596 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22
DL		 4597 const uint16_t *latencies;
4598
4599 if (INTEL_INFO(dev)->gen >= 9)
4600 latencies = dev_priv->wm.skl_latency;
4601 else
4602 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4603
97e94b22 4604 wm_latency_show(m, latencies);
369a1342
VS		 4605
4606 return 0;
4607}
4608
4609static int spr_wm_latency_show(struct seq_file *m, void *data)
4610{
4611 struct drm_device *dev = m->private;
fac5e23e 4612 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22
DL		 4613 const uint16_t *latencies;
4614
4615 if (INTEL_INFO(dev)->gen >= 9)
4616 latencies = dev_priv->wm.skl_latency;
4617 else
4618 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4619
97e94b22 4620 wm_latency_show(m, latencies);
369a1342
VS		 4621
4622 return 0;
4623}
4624
4625static int cur_wm_latency_show(struct seq_file *m, void *data)
4626{
4627 struct drm_device *dev = m->private;
fac5e23e 4628 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22
DL		 4629 const uint16_t *latencies;
4630
4631 if (INTEL_INFO(dev)->gen >= 9)
4632 latencies = dev_priv->wm.skl_latency;
4633 else
4634 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4635
97e94b22 4636 wm_latency_show(m, latencies);
369a1342
VS		 4637
4638 return 0;
4639}
4640
4641static int pri_wm_latency_open(struct inode *inode, struct file *file)
4642{
4643 struct drm_device *dev = inode->i_private;
4644
de38b95c 4645 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4646 return -ENODEV;
4647
4648 return single_open(file, pri_wm_latency_show, dev);
4649}
4650
4651static int spr_wm_latency_open(struct inode *inode, struct file *file)
4652{
4653 struct drm_device *dev = inode->i_private;
4654
9ad0257c 4655 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4656 return -ENODEV;
4657
4658 return single_open(file, spr_wm_latency_show, dev);
4659}
4660
4661static int cur_wm_latency_open(struct inode *inode, struct file *file)
4662{
4663 struct drm_device *dev = inode->i_private;
4664
9ad0257c 4665 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4666 return -ENODEV;
4667
4668 return single_open(file, cur_wm_latency_show, dev);
4669}
4670
4671static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4672 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4673{
4674 struct seq_file *m = file->private_data;
4675 struct drm_device *dev = m->private;
97e94b22 4676 uint16_t new[8] = { 0 };
de38b95c 4677 int num_levels;
369a1342
VS		 4678 int level;
4679 int ret;
4680 char tmp[32];
4681
de38b95c
VS		 4682 if (IS_CHERRYVIEW(dev))
4683 num_levels = 3;
4684 else if (IS_VALLEYVIEW(dev))
4685 num_levels = 1;
4686 else
4687 num_levels = ilk_wm_max_level(dev) + 1;
4688
369a1342
VS		 4689 if (len >= sizeof(tmp))
4690 return -EINVAL;
4691
4692 if (copy_from_user(tmp, ubuf, len))
4693 return -EFAULT;
4694
4695 tmp[len] = '\0';
4696
97e94b22
DL		 4697 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4698 &new[0], &new[1], &new[2], &new[3],
4699 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4700 if (ret != num_levels)
4701 return -EINVAL;
4702
4703 drm_modeset_lock_all(dev);
4704
4705 for (level = 0; level < num_levels; level++)
4706 wm[level] = new[level];
4707
4708 drm_modeset_unlock_all(dev);
4709
4710 return len;
4711}
4712
4713
4714static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4715 size_t len, loff_t *offp)
4716{
4717 struct seq_file *m = file->private_data;
4718 struct drm_device *dev = m->private;
fac5e23e 4719 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22 4720 uint16_t *latencies;
369a1342 4721
97e94b22
DL		 4722 if (INTEL_INFO(dev)->gen >= 9)
4723 latencies = dev_priv->wm.skl_latency;
4724 else
4725 latencies = to_i915(dev)->wm.pri_latency;
4726
4727 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4728}
4729
4730static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4731 size_t len, loff_t *offp)
4732{
4733 struct seq_file *m = file->private_data;
4734 struct drm_device *dev = m->private;
fac5e23e 4735 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22 4736 uint16_t *latencies;
369a1342 4737
97e94b22
DL		 4738 if (INTEL_INFO(dev)->gen >= 9)
4739 latencies = dev_priv->wm.skl_latency;
4740 else
4741 latencies = to_i915(dev)->wm.spr_latency;
4742
4743 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4744}
4745
4746static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4747 size_t len, loff_t *offp)
4748{
4749 struct seq_file *m = file->private_data;
4750 struct drm_device *dev = m->private;
fac5e23e 4751 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22
DL		 4752 uint16_t *latencies;
4753
4754 if (INTEL_INFO(dev)->gen >= 9)
4755 latencies = dev_priv->wm.skl_latency;
4756 else
4757 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4758
97e94b22 4759 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4760}
4761
4762static const struct file_operations i915_pri_wm_latency_fops = {
4763 .owner = THIS_MODULE,
4764 .open = pri_wm_latency_open,
4765 .read = seq_read,
4766 .llseek = seq_lseek,
4767 .release = single_release,
4768 .write = pri_wm_latency_write
4769};
4770
4771static const struct file_operations i915_spr_wm_latency_fops = {
4772 .owner = THIS_MODULE,
4773 .open = spr_wm_latency_open,
4774 .read = seq_read,
4775 .llseek = seq_lseek,
4776 .release = single_release,
4777 .write = spr_wm_latency_write
4778};
4779
4780static const struct file_operations i915_cur_wm_latency_fops = {
4781 .owner = THIS_MODULE,
4782 .open = cur_wm_latency_open,
4783 .read = seq_read,
4784 .llseek = seq_lseek,
4785 .release = single_release,
4786 .write = cur_wm_latency_write
4787};
4788
647416f9
KC		 4789static int
4790i915_wedged_get(void *data, u64 *val)
f3cd474b 4791{
647416f9 4792 struct drm_device *dev = data;
fac5e23e 4793 struct drm_i915_private *dev_priv = to_i915(dev);
f3cd474b 4794
d98c52cf 4795 *val = i915_terminally_wedged(&dev_priv->gpu_error);
f3cd474b 4796
647416f9 4797 return 0;
f3cd474b
CW		 4798}
4799
647416f9
KC		 4800static int
4801i915_wedged_set(void *data, u64 val)
f3cd474b 4802{
647416f9 4803 struct drm_device *dev = data;
fac5e23e 4804 struct drm_i915_private *dev_priv = to_i915(dev);
d46c0517 4805
b8d24a06
MK		 4806 /*
4807 * There is no safeguard against this debugfs entry colliding
4808 * with the hangcheck calling same i915_handle_error() in
4809 * parallel, causing an explosion. For now we assume that the
4810 * test harness is responsible enough not to inject gpu hangs
4811 * while it is writing to 'i915_wedged'
4812 */
4813
d98c52cf 4814 if (i915_reset_in_progress(&dev_priv->gpu_error))
b8d24a06
MK		 4815 return -EAGAIN;
4816
d46c0517 4817 intel_runtime_pm_get(dev_priv);
f3cd474b 4818
c033666a 4819 i915_handle_error(dev_priv, val,
58174462 4820 "Manually setting wedged to %llu", val);
d46c0517
ID		 4821
4822 intel_runtime_pm_put(dev_priv);
4823
647416f9 4824 return 0;
f3cd474b
CW		 4825}
4826
647416f9
KC		 4827DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4828 i915_wedged_get, i915_wedged_set,
3a3b4f98 4829 "%llu\n");
f3cd474b 4830
094f9a54
CW		 4831static int
4832i915_ring_missed_irq_get(void *data, u64 *val)
4833{
4834 struct drm_device *dev = data;
fac5e23e 4835 struct drm_i915_private *dev_priv = to_i915(dev);
094f9a54
CW		 4836
4837 *val = dev_priv->gpu_error.missed_irq_rings;
4838 return 0;
4839}
4840
4841static int
4842i915_ring_missed_irq_set(void *data, u64 val)
4843{
4844 struct drm_device *dev = data;
fac5e23e 4845 struct drm_i915_private *dev_priv = to_i915(dev);
094f9a54
CW		 4846 int ret;
4847
4848 /* Lock against concurrent debugfs callers */
4849 ret = mutex_lock_interruptible(&dev->struct_mutex);
4850 if (ret)
4851 return ret;
4852 dev_priv->gpu_error.missed_irq_rings = val;
4853 mutex_unlock(&dev->struct_mutex);
4854
4855 return 0;
4856}
4857
4858DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4859 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4860 "0x%08llx\n");
4861
4862static int
4863i915_ring_test_irq_get(void *data, u64 *val)
4864{
4865 struct drm_device *dev = data;
fac5e23e 4866 struct drm_i915_private *dev_priv = to_i915(dev);
094f9a54
CW		 4867
4868 *val = dev_priv->gpu_error.test_irq_rings;
4869
4870 return 0;
4871}
4872
4873static int
4874i915_ring_test_irq_set(void *data, u64 val)
4875{
4876 struct drm_device *dev = data;
fac5e23e 4877 struct drm_i915_private *dev_priv = to_i915(dev);
094f9a54 4878
3a122c27 4879 val &= INTEL_INFO(dev_priv)->ring_mask;
094f9a54 4880 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
094f9a54 4881 dev_priv->gpu_error.test_irq_rings = val;
094f9a54
CW		 4882
4883 return 0;
4884}
4885
4886DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4887 i915_ring_test_irq_get, i915_ring_test_irq_set,
4888 "0x%08llx\n");
4889
dd624afd
CW		 4890#define DROP_UNBOUND 0x1
4891#define DROP_BOUND 0x2
4892#define DROP_RETIRE 0x4
4893#define DROP_ACTIVE 0x8
4894#define DROP_ALL (DROP_UNBOUND | \
4895 DROP_BOUND | \
4896 DROP_RETIRE | \
4897 DROP_ACTIVE)
647416f9
KC		 4898static int
4899i915_drop_caches_get(void *data, u64 *val)
dd624afd 4900{
647416f9 4901 *val = DROP_ALL;
dd624afd 4902
647416f9 4903 return 0;
dd624afd
CW		 4904}
4905
647416f9
KC		 4906static int
4907i915_drop_caches_set(void *data, u64 val)
dd624afd 4908{
647416f9 4909 struct drm_device *dev = data;
fac5e23e 4910 struct drm_i915_private *dev_priv = to_i915(dev);
647416f9 4911 int ret;
dd624afd 4912
2f9fe5ff 4913 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4914
4915 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4916 * on ioctls on -EAGAIN. */
4917 ret = mutex_lock_interruptible(&dev->struct_mutex);
4918 if (ret)
4919 return ret;
4920
4921 if (val & DROP_ACTIVE) {
6e5a5beb 4922 ret = i915_gem_wait_for_idle(dev_priv);
dd624afd
CW		 4923 if (ret)
4924 goto unlock;
4925 }
4926
4927 if (val & (DROP_RETIRE | DROP_ACTIVE))
c033666a 4928 i915_gem_retire_requests(dev_priv);
dd624afd 4929
21ab4e74
CW		 4930 if (val & DROP_BOUND)
4931 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4932
21ab4e74
CW		 4933 if (val & DROP_UNBOUND)
4934 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4935
4936unlock:
4937 mutex_unlock(&dev->struct_mutex);
4938
647416f9 4939 return ret;
dd624afd
CW		 4940}
4941
647416f9
KC		 4942DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4943 i915_drop_caches_get, i915_drop_caches_set,
4944 "0x%08llx\n");
dd624afd 4945
647416f9
KC		 4946static int
4947i915_max_freq_get(void *data, u64 *val)
358733e9 4948{
647416f9 4949 struct drm_device *dev = data;
fac5e23e 4950 struct drm_i915_private *dev_priv = to_i915(dev);
004777cb 4951
daa3afb2 4952 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4953 return -ENODEV;
4954
7c59a9c1 4955 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
647416f9 4956 return 0;
358733e9
JB		 4957}
4958
647416f9
KC		 4959static int
4960i915_max_freq_set(void *data, u64 val)
358733e9 4961{
647416f9 4962 struct drm_device *dev = data;
fac5e23e 4963 struct drm_i915_private *dev_priv = to_i915(dev);
bc4d91f6 4964 u32 hw_max, hw_min;
647416f9 4965 int ret;
004777cb 4966
daa3afb2 4967 if (INTEL_INFO(dev)->gen < 6)
004777cb 4968 return -ENODEV;
358733e9 4969
647416f9 4970 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4971
4fc688ce 4972 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4973 if (ret)
4974 return ret;
4975
358733e9
JB		 4976 /*
4977 * Turbo will still be enabled, but won't go above the set value.
4978 */
bc4d91f6 4979 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4980
bc4d91f6
AG		 4981 hw_max = dev_priv->rps.max_freq;
4982 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4983
b39fb297 4984 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4985 mutex_unlock(&dev_priv->rps.hw_lock);
4986 return -EINVAL;
0a073b84
JB		 4987 }
4988
b39fb297 4989 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4990
dc97997a 4991 intel_set_rps(dev_priv, val);
dd0a1aa1 4992
4fc688ce 4993 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4994
647416f9 4995 return 0;
358733e9
JB		 4996}
4997
647416f9
KC		 4998DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4999 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 5000 "%llu\n");
358733e9 5001
647416f9
KC		 5002static int
5003i915_min_freq_get(void *data, u64 *val)
1523c310 5004{
647416f9 5005 struct drm_device *dev = data;
fac5e23e 5006 struct drm_i915_private *dev_priv = to_i915(dev);
004777cb 5007
62e1baa1 5008 if (INTEL_GEN(dev_priv) < 6)
004777cb
DV		 5009 return -ENODEV;
5010
7c59a9c1 5011 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
647416f9 5012 return 0;
1523c310
JB		 5013}
5014
647416f9
KC		 5015static int
5016i915_min_freq_set(void *data, u64 val)
1523c310 5017{
647416f9 5018 struct drm_device *dev = data;
fac5e23e 5019 struct drm_i915_private *dev_priv = to_i915(dev);
bc4d91f6 5020 u32 hw_max, hw_min;
647416f9 5021 int ret;
004777cb 5022
62e1baa1 5023 if (INTEL_GEN(dev_priv) < 6)
004777cb 5024 return -ENODEV;
1523c310 5025
647416f9 5026 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 5027
4fc688ce 5028 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 5029 if (ret)
5030 return ret;
5031
1523c310
JB		 5032 /*
5033 * Turbo will still be enabled, but won't go below the set value.
5034 */
bc4d91f6 5035 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 5036
bc4d91f6
AG		 5037 hw_max = dev_priv->rps.max_freq;
5038 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 5039
b39fb297 5040 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 5041 mutex_unlock(&dev_priv->rps.hw_lock);
5042 return -EINVAL;
0a073b84 5043 }
dd0a1aa1 5044
b39fb297 5045 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 5046
dc97997a 5047 intel_set_rps(dev_priv, val);
dd0a1aa1 5048
4fc688ce 5049 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 5050
647416f9 5051 return 0;
1523c310
JB		 5052}
5053
647416f9
KC		 5054DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5055 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 5056 "%llu\n");
1523c310 5057
647416f9
KC		 5058static int
5059i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 5060{
647416f9 5061 struct drm_device *dev = data;
fac5e23e 5062 struct drm_i915_private *dev_priv = to_i915(dev);
07b7ddd9 5063 u32 snpcr;
647416f9 5064 int ret;
07b7ddd9 5065
004777cb
DV		 5066 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5067 return -ENODEV;
5068
22bcfc6a
DV		 5069 ret = mutex_lock_interruptible(&dev->struct_mutex);
5070 if (ret)
5071 return ret;
c8c8fb33 5072 intel_runtime_pm_get(dev_priv);
22bcfc6a 5073
07b7ddd9 5074 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 5075
5076 intel_runtime_pm_put(dev_priv);
91c8a326 5077 mutex_unlock(&dev_priv->drm.struct_mutex);
07b7ddd9 5078
647416f9 5079 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 5080
647416f9 5081 return 0;
07b7ddd9
JB		 5082}
5083
647416f9
KC		 5084static int
5085i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 5086{
647416f9 5087 struct drm_device *dev = data;
fac5e23e 5088 struct drm_i915_private *dev_priv = to_i915(dev);
07b7ddd9 5089 u32 snpcr;
07b7ddd9 5090
004777cb
DV		 5091 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5092 return -ENODEV;
5093
647416f9 5094 if (val > 3)
07b7ddd9
JB		 5095 return -EINVAL;
5096
c8c8fb33 5097 intel_runtime_pm_get(dev_priv);
647416f9 5098 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 5099
5100 /* Update the cache sharing policy here as well */
5101 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5102 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5103 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5104 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5105
c8c8fb33 5106 intel_runtime_pm_put(dev_priv);
647416f9 5107 return 0;
07b7ddd9
JB		 5108}
5109
647416f9
KC		 5110DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5111 i915_cache_sharing_get, i915_cache_sharing_set,
5112 "%llu\n");
07b7ddd9 5113
5d39525a
JM		 5114struct sseu_dev_status {
5115 unsigned int slice_total;
5116 unsigned int subslice_total;
5117 unsigned int subslice_per_slice;
5118 unsigned int eu_total;
5119 unsigned int eu_per_subslice;
5120};
5121
5122static void cherryview_sseu_device_status(struct drm_device *dev,
5123 struct sseu_dev_status *stat)
5124{
fac5e23e 5125 struct drm_i915_private *dev_priv = to_i915(dev);
0a0b457f 5126 int ss_max = 2;
5d39525a
JM		 5127 int ss;
5128 u32 sig1[ss_max], sig2[ss_max];
5129
5130 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5131 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5132 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5133 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5134
5135 for (ss = 0; ss < ss_max; ss++) {
5136 unsigned int eu_cnt;
5137
5138 if (sig1[ss] & CHV_SS_PG_ENABLE)
5139 /* skip disabled subslice */
5140 continue;
5141
5142 stat->slice_total = 1;
5143 stat->subslice_per_slice++;
5144 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5145 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5146 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5147 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5148 stat->eu_total += eu_cnt;
5149 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5150 }
5151 stat->subslice_total = stat->subslice_per_slice;
5152}
5153
5154static void gen9_sseu_device_status(struct drm_device *dev,
5155 struct sseu_dev_status *stat)
5156{
fac5e23e 5157 struct drm_i915_private *dev_priv = to_i915(dev);
1c046bc1 5158 int s_max = 3, ss_max = 4;
5d39525a
JM		 5159 int s, ss;
5160 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5161
1c046bc1
JM		 5162 /* BXT has a single slice and at most 3 subslices. */
5163 if (IS_BROXTON(dev)) {
5164 s_max = 1;
5165 ss_max = 3;
5166 }
5167
5168 for (s = 0; s < s_max; s++) {
5169 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5170 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5171 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5172 }
5173
5d39525a
JM		 5174 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5175 GEN9_PGCTL_SSA_EU19_ACK |
5176 GEN9_PGCTL_SSA_EU210_ACK |
5177 GEN9_PGCTL_SSA_EU311_ACK;
5178 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5179 GEN9_PGCTL_SSB_EU19_ACK |
5180 GEN9_PGCTL_SSB_EU210_ACK |
5181 GEN9_PGCTL_SSB_EU311_ACK;
5182
5183 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 5184 unsigned int ss_cnt = 0;
5185
5d39525a
JM		 5186 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5187 /* skip disabled slice */
5188 continue;
5189
5190 stat->slice_total++;
1c046bc1 5191
ef11bdb3 5192 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1c046bc1
JM		 5193 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5194
5d39525a
JM		 5195 for (ss = 0; ss < ss_max; ss++) {
5196 unsigned int eu_cnt;
5197
1c046bc1
JM		 5198 if (IS_BROXTON(dev) &&
5199 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5200 /* skip disabled subslice */
5201 continue;
5202
5203 if (IS_BROXTON(dev))
5204 ss_cnt++;
5205
5d39525a
JM		 5206 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5207 eu_mask[ss%2]);
5208 stat->eu_total += eu_cnt;
5209 stat->eu_per_subslice = max(stat->eu_per_subslice,
5210 eu_cnt);
5211 }
1c046bc1
JM		 5212
5213 stat->subslice_total += ss_cnt;
5214 stat->subslice_per_slice = max(stat->subslice_per_slice,
5215 ss_cnt);
5d39525a
JM		 5216 }
5217}
5218
91bedd34
ŁD		 5219static void broadwell_sseu_device_status(struct drm_device *dev,
5220 struct sseu_dev_status *stat)
5221{
fac5e23e 5222 struct drm_i915_private *dev_priv = to_i915(dev);
91bedd34
ŁD		 5223 int s;
5224 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5225
5226 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5227
5228 if (stat->slice_total) {
5229 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5230 stat->subslice_total = stat->slice_total *
5231 stat->subslice_per_slice;
5232 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5233 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5234
5235 /* subtract fused off EU(s) from enabled slice(s) */
5236 for (s = 0; s < stat->slice_total; s++) {
5237 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5238
5239 stat->eu_total -= hweight8(subslice_7eu);
5240 }
5241 }
5242}
5243
3873218f
JM		 5244static int i915_sseu_status(struct seq_file *m, void *unused)
5245{
5246 struct drm_info_node *node = (struct drm_info_node *) m->private;
238010ed
DW		 5247 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
5248 struct drm_device *dev = &dev_priv->drm;
5d39525a 5249 struct sseu_dev_status stat;
3873218f 5250
91bedd34 5251 if (INTEL_INFO(dev)->gen < 8)
3873218f
JM		 5252 return -ENODEV;
5253
5254 seq_puts(m, "SSEU Device Info\n");
5255 seq_printf(m, " Available Slice Total: %u\n",
5256 INTEL_INFO(dev)->slice_total);
5257 seq_printf(m, " Available Subslice Total: %u\n",
5258 INTEL_INFO(dev)->subslice_total);
5259 seq_printf(m, " Available Subslice Per Slice: %u\n",
5260 INTEL_INFO(dev)->subslice_per_slice);
5261 seq_printf(m, " Available EU Total: %u\n",
5262 INTEL_INFO(dev)->eu_total);
5263 seq_printf(m, " Available EU Per Subslice: %u\n",
5264 INTEL_INFO(dev)->eu_per_subslice);
33e141ed 5265 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5266 if (HAS_POOLED_EU(dev))
5267 seq_printf(m, " Min EU in pool: %u\n",
5268 INTEL_INFO(dev)->min_eu_in_pool);
3873218f
JM		 5269 seq_printf(m, " Has Slice Power Gating: %s\n",
5270 yesno(INTEL_INFO(dev)->has_slice_pg));
5271 seq_printf(m, " Has Subslice Power Gating: %s\n",
5272 yesno(INTEL_INFO(dev)->has_subslice_pg));
5273 seq_printf(m, " Has EU Power Gating: %s\n",
5274 yesno(INTEL_INFO(dev)->has_eu_pg));
5275
7f992aba 5276 seq_puts(m, "SSEU Device Status\n");
5d39525a 5277 memset(&stat, 0, sizeof(stat));
238010ed
DW		 5278
5279 intel_runtime_pm_get(dev_priv);
5280
5575f03a 5281 if (IS_CHERRYVIEW(dev)) {
5d39525a 5282 cherryview_sseu_device_status(dev, &stat);
91bedd34
ŁD		 5283 } else if (IS_BROADWELL(dev)) {
5284 broadwell_sseu_device_status(dev, &stat);
1c046bc1 5285 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 5286 gen9_sseu_device_status(dev, &stat);
7f992aba 5287 }
238010ed
DW		 5288
5289 intel_runtime_pm_put(dev_priv);
5290
5d39525a
JM		 5291 seq_printf(m, " Enabled Slice Total: %u\n",
5292 stat.slice_total);
5293 seq_printf(m, " Enabled Subslice Total: %u\n",
5294 stat.subslice_total);
5295 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5296 stat.subslice_per_slice);
5297 seq_printf(m, " Enabled EU Total: %u\n",
5298 stat.eu_total);
5299 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5300 stat.eu_per_subslice);
7f992aba 5301
3873218f
JM		 5302 return 0;
5303}
5304
6d794d42
BW		 5305static int i915_forcewake_open(struct inode *inode, struct file *file)
5306{
5307 struct drm_device *dev = inode->i_private;
fac5e23e 5308 struct drm_i915_private *dev_priv = to_i915(dev);
6d794d42 5309
075edca4 5310 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5311 return 0;
5312
6daccb0b 5313 intel_runtime_pm_get(dev_priv);
59bad947 5314 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5315
5316 return 0;
5317}
5318
c43b5634 5319static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5320{
5321 struct drm_device *dev = inode->i_private;
fac5e23e 5322 struct drm_i915_private *dev_priv = to_i915(dev);
6d794d42 5323
075edca4 5324 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5325 return 0;
5326
59bad947 5327 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5328 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5329
5330 return 0;
5331}
5332
5333static const struct file_operations i915_forcewake_fops = {
5334 .owner = THIS_MODULE,
5335 .open = i915_forcewake_open,
5336 .release = i915_forcewake_release,
5337};
5338
5339static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5340{
5341 struct drm_device *dev = minor->dev;
5342 struct dentry *ent;
5343
5344 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5345 S_IRUSR,
6d794d42
BW		 5346 root, dev,
5347 &i915_forcewake_fops);
f3c5fe97
WY		 5348 if (!ent)
5349 return -ENOMEM;
6d794d42 5350
8eb57294 5351 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5352}
5353
6a9c308d
DV		 5354static int i915_debugfs_create(struct dentry *root,
5355 struct drm_minor *minor,
5356 const char *name,
5357 const struct file_operations *fops)
07b7ddd9
JB		 5358{
5359 struct drm_device *dev = minor->dev;
5360 struct dentry *ent;
5361
6a9c308d 5362 ent = debugfs_create_file(name,
07b7ddd9
JB		 5363 S_IRUGO | S_IWUSR,
5364 root, dev,
6a9c308d 5365 fops);
f3c5fe97
WY		 5366 if (!ent)
5367 return -ENOMEM;
07b7ddd9 5368
6a9c308d 5369 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5370}
5371
06c5bf8c 5372static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5373 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5374 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5375 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5376 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5377 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5378 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5379 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5380 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5381 {"i915_gem_request", i915_gem_request_info, 0},
5382 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5383 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5384 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5385 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5386 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5387 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5388 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5389 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5390 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5391 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5392 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5393 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5394 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5395 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5396 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5397 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5398 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5399 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5400 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5401 {"i915_sr_status", i915_sr_status, 0},
44834a67 5402 {"i915_opregion", i915_opregion, 0},
ada8f955 5403 {"i915_vbt", i915_vbt, 0},
37811fcc 5404 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5405 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5406 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5407 {"i915_execlists", i915_execlists, 0},
f65367b5 5408 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5409 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5410 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5411 {"i915_llc", i915_llc, 0},
e91fd8c6 5412 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5413 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5414 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5415 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5416 {"i915_power_domain_info", i915_power_domain_info, 0},
b7cec66d 5417 {"i915_dmc_info", i915_dmc_info, 0},
53f5e3ca 5418 {"i915_display_info", i915_display_info, 0},
e04934cf 5419 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5420 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5421 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5422 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5423 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5424 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5425 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5426 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5427};
27c202ad 5428#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5429
06c5bf8c 5430static const struct i915_debugfs_files {
34b9674c
DV		 5431 const char *name;
5432 const struct file_operations *fops;
5433} i915_debugfs_files[] = {
5434 {"i915_wedged", &i915_wedged_fops},
5435 {"i915_max_freq", &i915_max_freq_fops},
5436 {"i915_min_freq", &i915_min_freq_fops},
5437 {"i915_cache_sharing", &i915_cache_sharing_fops},
094f9a54
CW		 5438 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5439 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5440 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5441 {"i915_error_state", &i915_error_state_fops},
5442 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5443 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5444 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5445 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5446 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5447 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5448 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5449 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5450 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5451};
5452
07144428
DL		 5453void intel_display_crc_init(struct drm_device *dev)
5454{
fac5e23e 5455 struct drm_i915_private *dev_priv = to_i915(dev);
b378360e 5456 enum pipe pipe;
07144428 5457
055e393f 5458 for_each_pipe(dev_priv, pipe) {
b378360e 5459 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5460
d538bbdf
DL		 5461 pipe_crc->opened = false;
5462 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5463 init_waitqueue_head(&pipe_crc->wq);
5464 }
5465}
5466
1dac891c 5467int i915_debugfs_register(struct drm_i915_private *dev_priv)
2017263e 5468{
91c8a326 5469 struct drm_minor *minor = dev_priv->drm.primary;
34b9674c 5470 int ret, i;
f3cd474b 5471
6d794d42 5472 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5473 if (ret)
5474 return ret;
6a9c308d 5475
07144428
DL		 5476 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5477 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5478 if (ret)
5479 return ret;
5480 }
5481
34b9674c
DV		 5482 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5483 ret = i915_debugfs_create(minor->debugfs_root, minor,
5484 i915_debugfs_files[i].name,
5485 i915_debugfs_files[i].fops);
5486 if (ret)
5487 return ret;
5488 }
40633219 5489
27c202ad
BG		 5490 return drm_debugfs_create_files(i915_debugfs_list,
5491 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5492 minor->debugfs_root, minor);
5493}
5494
1dac891c 5495void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
2017263e 5496{
91c8a326 5497 struct drm_minor *minor = dev_priv->drm.primary;
34b9674c
DV		 5498 int i;
5499
27c202ad
BG		 5500 drm_debugfs_remove_files(i915_debugfs_list,
5501 I915_DEBUGFS_ENTRIES, minor);
07144428 5502
6d794d42
BW		 5503 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5504 1, minor);
07144428 5505
e309a997 5506 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5507 struct drm_info_list *info_list =
5508 (struct drm_info_list *)&i915_pipe_crc_data[i];
5509
5510 drm_debugfs_remove_files(info_list, 1, minor);
5511 }
5512
34b9674c
DV		 5513 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5514 struct drm_info_list *info_list =
5515 (struct drm_info_list *) i915_debugfs_files[i].fops;
5516
5517 drm_debugfs_remove_files(info_list, 1, minor);
5518 }
2017263e 5519}
aa7471d2
JN		 5520
5521struct dpcd_block {
5522 /* DPCD dump start address. */
5523 unsigned int offset;
5524 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5525 unsigned int end;
5526 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5527 size_t size;
5528 /* Only valid for eDP. */
5529 bool edp;
5530};
5531
5532static const struct dpcd_block i915_dpcd_debug[] = {
5533 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5534 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5535 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5536 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5537 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5538 { .offset = DP_SET_POWER },
5539 { .offset = DP_EDP_DPCD_REV },
5540 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5541 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5542 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5543};
5544
5545static int i915_dpcd_show(struct seq_file *m, void *data)
5546{
5547 struct drm_connector *connector = m->private;
5548 struct intel_dp *intel_dp =
5549 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5550 uint8_t buf[16];
5551 ssize_t err;
5552 int i;
5553
5c1a8875
MK		 5554 if (connector->status != connector_status_connected)
5555 return -ENODEV;
5556
aa7471d2
JN		 5557 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5558 const struct dpcd_block *b = &i915_dpcd_debug[i];
5559 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5560
5561 if (b->edp &&
5562 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5563 continue;
5564
5565 /* low tech for now */
5566 if (WARN_ON(size > sizeof(buf)))
5567 continue;
5568
5569 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5570 if (err <= 0) {
5571 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5572 size, b->offset, err);
5573 continue;
5574 }
5575
5576 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5577 }
aa7471d2
JN		 5578
5579 return 0;
5580}
5581
5582static int i915_dpcd_open(struct inode *inode, struct file *file)
5583{
5584 return single_open(file, i915_dpcd_show, inode->i_private);
5585}
5586
5587static const struct file_operations i915_dpcd_fops = {
5588 .owner = THIS_MODULE,
5589 .open = i915_dpcd_open,
5590 .read = seq_read,
5591 .llseek = seq_lseek,
5592 .release = single_release,
5593};
5594
5595/**
5596 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5597 * @connector: pointer to a registered drm_connector
5598 *
5599 * Cleanup will be done by drm_connector_unregister() through a call to
5600 * drm_debugfs_connector_remove().
5601 *
5602 * Returns 0 on success, negative error codes on error.
5603 */
5604int i915_debugfs_connector_add(struct drm_connector *connector)
5605{
5606 struct dentry *root = connector->debugfs_entry;
5607
5608 /* The connector must have been registered beforehands. */
5609 if (!root)
5610 return -ENODEV;
5611
5612 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5613 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5614 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5615 &i915_dpcd_fops);
5616
5617 return 0;
5618}
Linux kernel - Deliverables
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