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drm/i915/edp: use lane count and link rate from DPCD for eDP
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
d7f46fc4 101 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
d7f46fc4
BW		 126 int pin_count = 0;
127
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
0a4cd7c8 139 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
c1ad11fc
CW		 160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
69dc4987
CW		 171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
d5a81ef1
DV		 173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 175}
176
273497e5 177static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 178{
ea0c76f8 179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 185{
9f25d007 186 struct drm_info_node *node = m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
9f25d007 244 struct drm_info_node *node = m->private;
6d2b8885
CW		 245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6 303struct file_stats {
6313c204 304 struct drm_i915_file_private *file_priv;
2db8e9d6 305 int count;
c67a17e9
CW		 306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
2db8e9d6
CW		 309};
310
311static int per_file_stats(int id, void *ptr, void *data)
312{
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
6313c204 315 struct i915_vma *vma;
2db8e9d6
CW		 316
317 stats->count++;
318 stats->total += obj->base.size;
319
c67a17e9
CW		 320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
6313c204
CW		 323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 336 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 337 continue;
338
339 if (obj->ring) /* XXX per-vma statistic */
340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
2db8e9d6 346 } else {
6313c204
CW		 347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
349 if (obj->ring)
350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
2db8e9d6
CW		 355 }
356
6313c204
CW		 357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
2db8e9d6
CW		 360 return 0;
361}
362
ca191b13
BW		 363#define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
366 ++count; \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
369 ++mappable_count; \
370 } \
371 } \
372} while (0)
373
374static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 375{
9f25d007 376 struct drm_info_node *node = m->private;
73aa808f
CW		 377 struct drm_device *dev = node->minor->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 379 u32 count, mappable_count, purgeable_count;
380 size_t size, mappable_size, purgeable_size;
6299f992 381 struct drm_i915_gem_object *obj;
5cef07e1 382 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 383 struct drm_file *file;
ca191b13 384 struct i915_vma *vma;
73aa808f
CW		 385 int ret;
386
387 ret = mutex_lock_interruptible(&dev->struct_mutex);
388 if (ret)
389 return ret;
390
6299f992
CW		 391 seq_printf(m, "%u objects, %zu bytes\n",
392 dev_priv->mm.object_count,
393 dev_priv->mm.object_memory);
394
395 size = count = mappable_size = mappable_count = 0;
35c20a60 396 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 397 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count, mappable_count, size, mappable_size);
399
400 size = count = mappable_size = mappable_count = 0;
ca191b13 401 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 402 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count, mappable_count, size, mappable_size);
404
6299f992 405 size = count = mappable_size = mappable_count = 0;
ca191b13 406 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 407 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count, mappable_count, size, mappable_size);
409
b7abb714 410 size = count = purgeable_size = purgeable_count = 0;
35c20a60 411 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 412 size += obj->base.size, ++count;
b7abb714
CW		 413 if (obj->madv == I915_MADV_DONTNEED)
414 purgeable_size += obj->base.size, ++purgeable_count;
415 }
6c085a72
CW		 416 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
417
6299f992 418 size = count = mappable_size = mappable_count = 0;
35c20a60 419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 420 if (obj->fault_mappable) {
f343c5f6 421 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 422 ++count;
423 }
424 if (obj->pin_mappable) {
f343c5f6 425 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 426 ++mappable_count;
427 }
b7abb714
CW		 428 if (obj->madv == I915_MADV_DONTNEED) {
429 purgeable_size += obj->base.size;
430 ++purgeable_count;
431 }
6299f992 432 }
b7abb714
CW		 433 seq_printf(m, "%u purgeable objects, %zu bytes\n",
434 purgeable_count, purgeable_size);
6299f992
CW		 435 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count, mappable_size);
437 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
438 count, size);
439
93d18799 440 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 441 dev_priv->gtt.base.total,
442 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 443
267f0c90 444 seq_putc(m, '\n');
2db8e9d6
CW		 445 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
446 struct file_stats stats;
3ec2f427 447 struct task_struct *task;
2db8e9d6
CW		 448
449 memset(&stats, 0, sizeof(stats));
6313c204 450 stats.file_priv = file->driver_priv;
5b5ffff0 451 spin_lock(&file->table_lock);
2db8e9d6 452 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 453 spin_unlock(&file->table_lock);
3ec2f427
TH		 454 /*
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
459 */
460 rcu_read_lock();
461 task = pid_task(file->pid, PIDTYPE_PID);
c67a17e9 462 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
3ec2f427 463 task ? task->comm : "<unknown>",
2db8e9d6
CW		 464 stats.count,
465 stats.total,
466 stats.active,
467 stats.inactive,
6313c204 468 stats.global,
c67a17e9 469 stats.shared,
2db8e9d6 470 stats.unbound);
3ec2f427 471 rcu_read_unlock();
2db8e9d6
CW		 472 }
473
73aa808f
CW		 474 mutex_unlock(&dev->struct_mutex);
475
476 return 0;
477}
478
aee56cff 479static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 480{
9f25d007 481 struct drm_info_node *node = m->private;
08c18323 482 struct drm_device *dev = node->minor->dev;
1b50247a 483 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_i915_gem_object *obj;
486 size_t total_obj_size, total_gtt_size;
487 int count, ret;
488
489 ret = mutex_lock_interruptible(&dev->struct_mutex);
490 if (ret)
491 return ret;
492
493 total_obj_size = total_gtt_size = count = 0;
35c20a60 494 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 495 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 496 continue;
497
267f0c90 498 seq_puts(m, " ");
08c18323 499 describe_obj(m, obj);
267f0c90 500 seq_putc(m, '\n');
08c18323 501 total_obj_size += obj->base.size;
f343c5f6 502 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 503 count++;
504 }
505
506 mutex_unlock(&dev->struct_mutex);
507
508 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count, total_obj_size, total_gtt_size);
510
511 return 0;
512}
513
4e5359cd
SF		 514static int i915_gem_pageflip_info(struct seq_file *m, void *data)
515{
9f25d007 516 struct drm_info_node *node = m->private;
4e5359cd 517 struct drm_device *dev = node->minor->dev;
d6bbafa1 518 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd
SF		 519 unsigned long flags;
520 struct intel_crtc *crtc;
8a270ebf
DV		 521 int ret;
522
523 ret = mutex_lock_interruptible(&dev->struct_mutex);
524 if (ret)
525 return ret;
4e5359cd 526
d3fcc808 527 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 528 const char pipe = pipe_name(crtc->pipe);
529 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 530 struct intel_unpin_work *work;
531
532 spin_lock_irqsave(&dev->event_lock, flags);
533 work = crtc->unpin_work;
534 if (work == NULL) {
9db4a9c7 535 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 536 pipe, plane);
537 } else {
d6bbafa1
CW		 538 u32 addr;
539
e7d841ca 540 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 541 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 542 pipe, plane);
543 } else {
9db4a9c7 544 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 545 pipe, plane);
546 }
d6bbafa1
CW		 547 if (work->flip_queued_ring) {
548 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
549 work->flip_queued_ring->name,
550 work->flip_queued_seqno,
551 dev_priv->next_seqno,
552 work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
553 i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
554 work->flip_queued_seqno));
555 } else
556 seq_printf(m, "Flip not associated with any ring\n");
557 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
558 work->flip_queued_vblank,
559 work->flip_ready_vblank,
560 drm_vblank_count(dev, crtc->pipe));
4e5359cd 561 if (work->enable_stall_check)
267f0c90 562 seq_puts(m, "Stall check enabled, ");
4e5359cd 563 else
267f0c90 564 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 565 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 566
d6bbafa1
CW		 567 if (INTEL_INFO(dev)->gen >= 4)
568 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
569 else
570 addr = I915_READ(DSPADDR(crtc->plane));
571 seq_printf(m, "Current scanout address 0x%08x\n", addr);
572
4e5359cd 573 if (work->pending_flip_obj) {
d6bbafa1
CW		 574 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
575 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 576 }
577 }
578 spin_unlock_irqrestore(&dev->event_lock, flags);
579 }
580
8a270ebf
DV		 581 mutex_unlock(&dev->struct_mutex);
582
4e5359cd
SF		 583 return 0;
584}
585
2017263e
BG		 586static int i915_gem_request_info(struct seq_file *m, void *data)
587{
9f25d007 588 struct drm_info_node *node = m->private;
2017263e 589 struct drm_device *dev = node->minor->dev;
e277a1f8 590 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 591 struct intel_engine_cs *ring;
2017263e 592 struct drm_i915_gem_request *gem_request;
a2c7f6fd 593 int ret, count, i;
de227ef0
CW		 594
595 ret = mutex_lock_interruptible(&dev->struct_mutex);
596 if (ret)
597 return ret;
2017263e 598
c2c347a9 599 count = 0;
a2c7f6fd
CW		 600 for_each_ring(ring, dev_priv, i) {
601 if (list_empty(&ring->request_list))
602 continue;
603
604 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 605 list_for_each_entry(gem_request,
a2c7f6fd 606 &ring->request_list,
c2c347a9
CW		 607 list) {
608 seq_printf(m, " %d @ %d\n",
609 gem_request->seqno,
610 (int) (jiffies - gem_request->emitted_jiffies));
611 }
612 count++;
2017263e 613 }
de227ef0
CW		 614 mutex_unlock(&dev->struct_mutex);
615
c2c347a9 616 if (count == 0)
267f0c90 617 seq_puts(m, "No requests\n");
c2c347a9 618
2017263e
BG		 619 return 0;
620}
621
b2223497 622static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 623 struct intel_engine_cs *ring)
b2223497
CW		 624{
625 if (ring->get_seqno) {
43a7b924 626 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 627 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 628 }
629}
630
2017263e
BG		 631static int i915_gem_seqno_info(struct seq_file *m, void *data)
632{
9f25d007 633 struct drm_info_node *node = m->private;
2017263e 634 struct drm_device *dev = node->minor->dev;
e277a1f8 635 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 636 struct intel_engine_cs *ring;
1ec14ad3 637 int ret, i;
de227ef0
CW		 638
639 ret = mutex_lock_interruptible(&dev->struct_mutex);
640 if (ret)
641 return ret;
c8c8fb33 642 intel_runtime_pm_get(dev_priv);
2017263e 643
a2c7f6fd
CW		 644 for_each_ring(ring, dev_priv, i)
645 i915_ring_seqno_info(m, ring);
de227ef0 646
c8c8fb33 647 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 648 mutex_unlock(&dev->struct_mutex);
649
2017263e
BG		 650 return 0;
651}
652
653
654static int i915_interrupt_info(struct seq_file *m, void *data)
655{
9f25d007 656 struct drm_info_node *node = m->private;
2017263e 657 struct drm_device *dev = node->minor->dev;
e277a1f8 658 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 659 struct intel_engine_cs *ring;
9db4a9c7 660 int ret, i, pipe;
de227ef0
CW		 661
662 ret = mutex_lock_interruptible(&dev->struct_mutex);
663 if (ret)
664 return ret;
c8c8fb33 665 intel_runtime_pm_get(dev_priv);
2017263e 666
74e1ca8c 667 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 668 seq_printf(m, "Master Interrupt Control:\t%08x\n",
669 I915_READ(GEN8_MASTER_IRQ));
670
671 seq_printf(m, "Display IER:\t%08x\n",
672 I915_READ(VLV_IER));
673 seq_printf(m, "Display IIR:\t%08x\n",
674 I915_READ(VLV_IIR));
675 seq_printf(m, "Display IIR_RW:\t%08x\n",
676 I915_READ(VLV_IIR_RW));
677 seq_printf(m, "Display IMR:\t%08x\n",
678 I915_READ(VLV_IMR));
055e393f 679 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 680 seq_printf(m, "Pipe %c stat:\t%08x\n",
681 pipe_name(pipe),
682 I915_READ(PIPESTAT(pipe)));
683
684 seq_printf(m, "Port hotplug:\t%08x\n",
685 I915_READ(PORT_HOTPLUG_EN));
686 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
687 I915_READ(VLV_DPFLIPSTAT));
688 seq_printf(m, "DPINVGTT:\t%08x\n",
689 I915_READ(DPINVGTT));
690
691 for (i = 0; i < 4; i++) {
692 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
693 i, I915_READ(GEN8_GT_IMR(i)));
694 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
695 i, I915_READ(GEN8_GT_IIR(i)));
696 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
697 i, I915_READ(GEN8_GT_IER(i)));
698 }
699
700 seq_printf(m, "PCU interrupt mask:\t%08x\n",
701 I915_READ(GEN8_PCU_IMR));
702 seq_printf(m, "PCU interrupt identity:\t%08x\n",
703 I915_READ(GEN8_PCU_IIR));
704 seq_printf(m, "PCU interrupt enable:\t%08x\n",
705 I915_READ(GEN8_PCU_IER));
706 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 707 seq_printf(m, "Master Interrupt Control:\t%08x\n",
708 I915_READ(GEN8_MASTER_IRQ));
709
710 for (i = 0; i < 4; i++) {
711 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
712 i, I915_READ(GEN8_GT_IMR(i)));
713 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
714 i, I915_READ(GEN8_GT_IIR(i)));
715 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
716 i, I915_READ(GEN8_GT_IER(i)));
717 }
718
055e393f 719 for_each_pipe(dev_priv, pipe) {
22c59960
PZ		 720 if (!intel_display_power_enabled(dev_priv,
721 POWER_DOMAIN_PIPE(pipe))) {
722 seq_printf(m, "Pipe %c power disabled\n",
723 pipe_name(pipe));
724 continue;
725 }
a123f157 726 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 727 pipe_name(pipe),
728 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 729 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 730 pipe_name(pipe),
731 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 732 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 733 pipe_name(pipe),
734 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 735 }
736
737 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
738 I915_READ(GEN8_DE_PORT_IMR));
739 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
740 I915_READ(GEN8_DE_PORT_IIR));
741 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
742 I915_READ(GEN8_DE_PORT_IER));
743
744 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
745 I915_READ(GEN8_DE_MISC_IMR));
746 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
747 I915_READ(GEN8_DE_MISC_IIR));
748 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
749 I915_READ(GEN8_DE_MISC_IER));
750
751 seq_printf(m, "PCU interrupt mask:\t%08x\n",
752 I915_READ(GEN8_PCU_IMR));
753 seq_printf(m, "PCU interrupt identity:\t%08x\n",
754 I915_READ(GEN8_PCU_IIR));
755 seq_printf(m, "PCU interrupt enable:\t%08x\n",
756 I915_READ(GEN8_PCU_IER));
757 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 758 seq_printf(m, "Display IER:\t%08x\n",
759 I915_READ(VLV_IER));
760 seq_printf(m, "Display IIR:\t%08x\n",
761 I915_READ(VLV_IIR));
762 seq_printf(m, "Display IIR_RW:\t%08x\n",
763 I915_READ(VLV_IIR_RW));
764 seq_printf(m, "Display IMR:\t%08x\n",
765 I915_READ(VLV_IMR));
055e393f 766 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 767 seq_printf(m, "Pipe %c stat:\t%08x\n",
768 pipe_name(pipe),
769 I915_READ(PIPESTAT(pipe)));
770
771 seq_printf(m, "Master IER:\t%08x\n",
772 I915_READ(VLV_MASTER_IER));
773
774 seq_printf(m, "Render IER:\t%08x\n",
775 I915_READ(GTIER));
776 seq_printf(m, "Render IIR:\t%08x\n",
777 I915_READ(GTIIR));
778 seq_printf(m, "Render IMR:\t%08x\n",
779 I915_READ(GTIMR));
780
781 seq_printf(m, "PM IER:\t\t%08x\n",
782 I915_READ(GEN6_PMIER));
783 seq_printf(m, "PM IIR:\t\t%08x\n",
784 I915_READ(GEN6_PMIIR));
785 seq_printf(m, "PM IMR:\t\t%08x\n",
786 I915_READ(GEN6_PMIMR));
787
788 seq_printf(m, "Port hotplug:\t%08x\n",
789 I915_READ(PORT_HOTPLUG_EN));
790 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
791 I915_READ(VLV_DPFLIPSTAT));
792 seq_printf(m, "DPINVGTT:\t%08x\n",
793 I915_READ(DPINVGTT));
794
795 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 796 seq_printf(m, "Interrupt enable: %08x\n",
797 I915_READ(IER));
798 seq_printf(m, "Interrupt identity: %08x\n",
799 I915_READ(IIR));
800 seq_printf(m, "Interrupt mask: %08x\n",
801 I915_READ(IMR));
055e393f 802 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 803 seq_printf(m, "Pipe %c stat: %08x\n",
804 pipe_name(pipe),
805 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 806 } else {
807 seq_printf(m, "North Display Interrupt enable: %08x\n",
808 I915_READ(DEIER));
809 seq_printf(m, "North Display Interrupt identity: %08x\n",
810 I915_READ(DEIIR));
811 seq_printf(m, "North Display Interrupt mask: %08x\n",
812 I915_READ(DEIMR));
813 seq_printf(m, "South Display Interrupt enable: %08x\n",
814 I915_READ(SDEIER));
815 seq_printf(m, "South Display Interrupt identity: %08x\n",
816 I915_READ(SDEIIR));
817 seq_printf(m, "South Display Interrupt mask: %08x\n",
818 I915_READ(SDEIMR));
819 seq_printf(m, "Graphics Interrupt enable: %08x\n",
820 I915_READ(GTIER));
821 seq_printf(m, "Graphics Interrupt identity: %08x\n",
822 I915_READ(GTIIR));
823 seq_printf(m, "Graphics Interrupt mask: %08x\n",
824 I915_READ(GTIMR));
825 }
a2c7f6fd 826 for_each_ring(ring, dev_priv, i) {
a123f157 827 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 828 seq_printf(m,
829 "Graphics Interrupt mask (%s): %08x\n",
830 ring->name, I915_READ_IMR(ring));
9862e600 831 }
a2c7f6fd 832 i915_ring_seqno_info(m, ring);
9862e600 833 }
c8c8fb33 834 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 835 mutex_unlock(&dev->struct_mutex);
836
2017263e
BG		 837 return 0;
838}
839
a6172a80
CW		 840static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
841{
9f25d007 842 struct drm_info_node *node = m->private;
a6172a80 843 struct drm_device *dev = node->minor->dev;
e277a1f8 844 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 845 int i, ret;
846
847 ret = mutex_lock_interruptible(&dev->struct_mutex);
848 if (ret)
849 return ret;
a6172a80
CW		 850
851 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
852 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
853 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 854 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 855
6c085a72
CW		 856 seq_printf(m, "Fence %d, pin count = %d, object = ",
857 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 858 if (obj == NULL)
267f0c90 859 seq_puts(m, "unused");
c2c347a9 860 else
05394f39 861 describe_obj(m, obj);
267f0c90 862 seq_putc(m, '\n');
a6172a80
CW		 863 }
864
05394f39 865 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 866 return 0;
867}
868
2017263e
BG		 869static int i915_hws_info(struct seq_file *m, void *data)
870{
9f25d007 871 struct drm_info_node *node = m->private;
2017263e 872 struct drm_device *dev = node->minor->dev;
e277a1f8 873 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 874 struct intel_engine_cs *ring;
1a240d4d 875 const u32 *hws;
4066c0ae
CW		 876 int i;
877
1ec14ad3 878 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 879 hws = ring->status_page.page_addr;
2017263e
BG		 880 if (hws == NULL)
881 return 0;
882
883 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
884 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
885 i * 4,
886 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
887 }
888 return 0;
889}
890
d5442303
DV		 891static ssize_t
892i915_error_state_write(struct file *filp,
893 const char __user *ubuf,
894 size_t cnt,
895 loff_t *ppos)
896{
edc3d884 897 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 898 struct drm_device *dev = error_priv->dev;
22bcfc6a 899 int ret;
d5442303
DV		 900
901 DRM_DEBUG_DRIVER("Resetting error state\n");
902
22bcfc6a
DV		 903 ret = mutex_lock_interruptible(&dev->struct_mutex);
904 if (ret)
905 return ret;
906
d5442303
DV		 907 i915_destroy_error_state(dev);
908 mutex_unlock(&dev->struct_mutex);
909
910 return cnt;
911}
912
913static int i915_error_state_open(struct inode *inode, struct file *file)
914{
915 struct drm_device *dev = inode->i_private;
d5442303 916 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 917
918 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
919 if (!error_priv)
920 return -ENOMEM;
921
922 error_priv->dev = dev;
923
95d5bfb3 924 i915_error_state_get(dev, error_priv);
d5442303 925
edc3d884
MK		 926 file->private_data = error_priv;
927
928 return 0;
d5442303
DV		 929}
930
931static int i915_error_state_release(struct inode *inode, struct file *file)
932{
edc3d884 933 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 934
95d5bfb3 935 i915_error_state_put(error_priv);
d5442303
DV		 936 kfree(error_priv);
937
edc3d884
MK		 938 return 0;
939}
940
4dc955f7
MK		 941static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
942 size_t count, loff_t *pos)
943{
944 struct i915_error_state_file_priv *error_priv = file->private_data;
945 struct drm_i915_error_state_buf error_str;
946 loff_t tmp_pos = 0;
947 ssize_t ret_count = 0;
948 int ret;
949
0a4cd7c8 950 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 951 if (ret)
952 return ret;
edc3d884 953
fc16b48b 954 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 955 if (ret)
956 goto out;
957
edc3d884
MK		 958 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
959 error_str.buf,
960 error_str.bytes);
961
962 if (ret_count < 0)
963 ret = ret_count;
964 else
965 *pos = error_str.start + ret_count;
966out:
4dc955f7 967 i915_error_state_buf_release(&error_str);
edc3d884 968 return ret ?: ret_count;
d5442303
DV		 969}
970
971static const struct file_operations i915_error_state_fops = {
972 .owner = THIS_MODULE,
973 .open = i915_error_state_open,
edc3d884 974 .read = i915_error_state_read,
d5442303
DV		 975 .write = i915_error_state_write,
976 .llseek = default_llseek,
977 .release = i915_error_state_release,
978};
979
647416f9
KC		 980static int
981i915_next_seqno_get(void *data, u64 *val)
40633219 982{
647416f9 983 struct drm_device *dev = data;
e277a1f8 984 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 985 int ret;
986
987 ret = mutex_lock_interruptible(&dev->struct_mutex);
988 if (ret)
989 return ret;
990
647416f9 991 *val = dev_priv->next_seqno;
40633219
MK		 992 mutex_unlock(&dev->struct_mutex);
993
647416f9 994 return 0;
40633219
MK		 995}
996
647416f9
KC		 997static int
998i915_next_seqno_set(void *data, u64 val)
999{
1000 struct drm_device *dev = data;
40633219
MK		 1001 int ret;
1002
40633219
MK		 1003 ret = mutex_lock_interruptible(&dev->struct_mutex);
1004 if (ret)
1005 return ret;
1006
e94fbaa8 1007 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1008 mutex_unlock(&dev->struct_mutex);
1009
647416f9 1010 return ret;
40633219
MK		 1011}
1012
647416f9
KC		 1013DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1014 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1015 "0x%llx\n");
40633219 1016
adb4bd12 1017static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1018{
9f25d007 1019 struct drm_info_node *node = m->private;
f97108d1 1020 struct drm_device *dev = node->minor->dev;
e277a1f8 1021 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1022 int ret = 0;
1023
1024 intel_runtime_pm_get(dev_priv);
3b8d8d91 1025
5c9669ce
TR		 1026 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1027
3b8d8d91
JB		 1028 if (IS_GEN5(dev)) {
1029 u16 rgvswctl = I915_READ16(MEMSWCTL);
1030 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1031
1032 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1033 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1034 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1035 MEMSTAT_VID_SHIFT);
1036 seq_printf(m, "Current P-state: %d\n",
1037 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1038 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1039 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1040 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1041 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1042 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1043 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1044 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1045 u32 rpupei, rpcurup, rpprevup;
1046 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1047 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1048 int max_freq;
1049
1050 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1051 ret = mutex_lock_interruptible(&dev->struct_mutex);
1052 if (ret)
c8c8fb33 1053 goto out;
d1ebd816 1054
c8d9a590 1055 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1056
8e8c06cd
CW		 1057 reqf = I915_READ(GEN6_RPNSWREQ);
1058 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1059 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1060 reqf >>= 24;
1061 else
1062 reqf >>= 25;
1063 reqf *= GT_FREQUENCY_MULTIPLIER;
1064
0d8f9491
CW		 1065 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1066 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1067 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1068
ccab5c82
JB		 1069 rpstat = I915_READ(GEN6_RPSTAT1);
1070 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1071 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1072 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1073 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1074 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1075 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1076 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1077 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1078 else
1079 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1080 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1081
c8d9a590 1082 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1083 mutex_unlock(&dev->struct_mutex);
1084
9dd3c605
PZ		 1085 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1086 pm_ier = I915_READ(GEN6_PMIER);
1087 pm_imr = I915_READ(GEN6_PMIMR);
1088 pm_isr = I915_READ(GEN6_PMISR);
1089 pm_iir = I915_READ(GEN6_PMIIR);
1090 pm_mask = I915_READ(GEN6_PMINTRMSK);
1091 } else {
1092 pm_ier = I915_READ(GEN8_GT_IER(2));
1093 pm_imr = I915_READ(GEN8_GT_IMR(2));
1094 pm_isr = I915_READ(GEN8_GT_ISR(2));
1095 pm_iir = I915_READ(GEN8_GT_IIR(2));
1096 pm_mask = I915_READ(GEN6_PMINTRMSK);
1097 }
0d8f9491 1098 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1099 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1100 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1101 seq_printf(m, "Render p-state ratio: %d\n",
1102 (gt_perf_status & 0xff00) >> 8);
1103 seq_printf(m, "Render p-state VID: %d\n",
1104 gt_perf_status & 0xff);
1105 seq_printf(m, "Render p-state limit: %d\n",
1106 rp_state_limits & 0xff);
0d8f9491
CW		 1107 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1108 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1109 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1110 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1111 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1112 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1113 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1114 GEN6_CURICONT_MASK);
1115 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1116 GEN6_CURBSYTAVG_MASK);
1117 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1118 GEN6_CURBSYTAVG_MASK);
1119 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1120 GEN6_CURIAVG_MASK);
1121 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1122 GEN6_CURBSYTAVG_MASK);
1123 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1124 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1125
1126 max_freq = (rp_state_cap & 0xff0000) >> 16;
1127 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1128 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1129
1130 max_freq = (rp_state_cap & 0xff00) >> 8;
1131 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1132 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1133
1134 max_freq = rp_state_cap & 0xff;
1135 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1136 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1137
1138 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1139 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84 1140 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1141 u32 freq_sts;
0a073b84 1142
259bd5d4 1143 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1144 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1145 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1146 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1147
0a073b84 1148 seq_printf(m, "max GPU freq: %d MHz\n",
b2435c94 1149 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1150
0a073b84 1151 seq_printf(m, "min GPU freq: %d MHz\n",
b2435c94 1152 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045
VS		 1153
1154 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
b2435c94 1155 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1156
1157 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1158 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1159 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1160 } else {
267f0c90 1161 seq_puts(m, "no P-state info available\n");
3b8d8d91 1162 }
f97108d1 1163
c8c8fb33
PZ		 1164out:
1165 intel_runtime_pm_put(dev_priv);
1166 return ret;
f97108d1
JB		 1167}
1168
4d85529d 1169static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1170{
9f25d007 1171 struct drm_info_node *node = m->private;
f97108d1 1172 struct drm_device *dev = node->minor->dev;
e277a1f8 1173 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1174 u32 rgvmodectl, rstdbyctl;
1175 u16 crstandvid;
1176 int ret;
1177
1178 ret = mutex_lock_interruptible(&dev->struct_mutex);
1179 if (ret)
1180 return ret;
c8c8fb33 1181 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1182
1183 rgvmodectl = I915_READ(MEMMODECTL);
1184 rstdbyctl = I915_READ(RSTDBYCTL);
1185 crstandvid = I915_READ16(CRSTANDVID);
1186
c8c8fb33 1187 intel_runtime_pm_put(dev_priv);
616fdb5a 1188 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1189
1190 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1191 "yes" : "no");
1192 seq_printf(m, "Boost freq: %d\n",
1193 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1194 MEMMODE_BOOST_FREQ_SHIFT);
1195 seq_printf(m, "HW control enabled: %s\n",
1196 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1197 seq_printf(m, "SW control enabled: %s\n",
1198 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1199 seq_printf(m, "Gated voltage change: %s\n",
1200 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1201 seq_printf(m, "Starting frequency: P%d\n",
1202 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1203 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1204 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1205 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1206 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1207 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1208 seq_printf(m, "Render standby enabled: %s\n",
1209 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1210 seq_puts(m, "Current RS state: ");
88271da3
JB		 1211 switch (rstdbyctl & RSX_STATUS_MASK) {
1212 case RSX_STATUS_ON:
267f0c90 1213 seq_puts(m, "on\n");
88271da3
JB		 1214 break;
1215 case RSX_STATUS_RC1:
267f0c90 1216 seq_puts(m, "RC1\n");
88271da3
JB		 1217 break;
1218 case RSX_STATUS_RC1E:
267f0c90 1219 seq_puts(m, "RC1E\n");
88271da3
JB		 1220 break;
1221 case RSX_STATUS_RS1:
267f0c90 1222 seq_puts(m, "RS1\n");
88271da3
JB		 1223 break;
1224 case RSX_STATUS_RS2:
267f0c90 1225 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1226 break;
1227 case RSX_STATUS_RS3:
267f0c90 1228 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1229 break;
1230 default:
267f0c90 1231 seq_puts(m, "unknown\n");
88271da3
JB		 1232 break;
1233 }
f97108d1
JB		 1234
1235 return 0;
1236}
1237
669ab5aa
D		 1238static int vlv_drpc_info(struct seq_file *m)
1239{
1240
9f25d007 1241 struct drm_info_node *node = m->private;
669ab5aa
D		 1242 struct drm_device *dev = node->minor->dev;
1243 struct drm_i915_private *dev_priv = dev->dev_private;
1244 u32 rpmodectl1, rcctl1;
1245 unsigned fw_rendercount = 0, fw_mediacount = 0;
1246
d46c0517
ID		 1247 intel_runtime_pm_get(dev_priv);
1248
669ab5aa
D		 1249 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1250 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1251
d46c0517
ID		 1252 intel_runtime_pm_put(dev_priv);
1253
669ab5aa
D		 1254 seq_printf(m, "Video Turbo Mode: %s\n",
1255 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1256 seq_printf(m, "Turbo enabled: %s\n",
1257 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1258 seq_printf(m, "HW control enabled: %s\n",
1259 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1260 seq_printf(m, "SW control enabled: %s\n",
1261 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1262 GEN6_RP_MEDIA_SW_MODE));
1263 seq_printf(m, "RC6 Enabled: %s\n",
1264 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1265 GEN6_RC_CTL_EI_MODE(1))));
1266 seq_printf(m, "Render Power Well: %s\n",
1267 (I915_READ(VLV_GTLC_PW_STATUS) &
1268 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1269 seq_printf(m, "Media Power Well: %s\n",
1270 (I915_READ(VLV_GTLC_PW_STATUS) &
1271 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1272
9cc19be5
ID		 1273 seq_printf(m, "Render RC6 residency since boot: %u\n",
1274 I915_READ(VLV_GT_RENDER_RC6));
1275 seq_printf(m, "Media RC6 residency since boot: %u\n",
1276 I915_READ(VLV_GT_MEDIA_RC6));
1277
669ab5aa
D		 1278 spin_lock_irq(&dev_priv->uncore.lock);
1279 fw_rendercount = dev_priv->uncore.fw_rendercount;
1280 fw_mediacount = dev_priv->uncore.fw_mediacount;
1281 spin_unlock_irq(&dev_priv->uncore.lock);
1282
1283 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1284 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1285
1286
1287 return 0;
1288}
1289
1290
4d85529d
BW		 1291static int gen6_drpc_info(struct seq_file *m)
1292{
1293
9f25d007 1294 struct drm_info_node *node = m->private;
4d85529d
BW		 1295 struct drm_device *dev = node->minor->dev;
1296 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1297 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1298 unsigned forcewake_count;
aee56cff 1299 int count = 0, ret;
4d85529d
BW		 1300
1301 ret = mutex_lock_interruptible(&dev->struct_mutex);
1302 if (ret)
1303 return ret;
c8c8fb33 1304 intel_runtime_pm_get(dev_priv);
4d85529d 1305
907b28c5
CW		 1306 spin_lock_irq(&dev_priv->uncore.lock);
1307 forcewake_count = dev_priv->uncore.forcewake_count;
1308 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1309
1310 if (forcewake_count) {
267f0c90
DL		 1311 seq_puts(m, "RC information inaccurate because somebody "
1312 "holds a forcewake reference \n");
4d85529d
BW		 1313 } else {
1314 /* NB: we cannot use forcewake, else we read the wrong values */
1315 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1316 udelay(10);
1317 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1318 }
1319
1320 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1321 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1322
1323 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1324 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1325 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1326 mutex_lock(&dev_priv->rps.hw_lock);
1327 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1328 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1329
c8c8fb33
PZ		 1330 intel_runtime_pm_put(dev_priv);
1331
4d85529d
BW		 1332 seq_printf(m, "Video Turbo Mode: %s\n",
1333 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1334 seq_printf(m, "HW control enabled: %s\n",
1335 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1336 seq_printf(m, "SW control enabled: %s\n",
1337 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1338 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1339 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1340 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1341 seq_printf(m, "RC6 Enabled: %s\n",
1342 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1343 seq_printf(m, "Deep RC6 Enabled: %s\n",
1344 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1345 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1346 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1347 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1348 switch (gt_core_status & GEN6_RCn_MASK) {
1349 case GEN6_RC0:
1350 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1351 seq_puts(m, "Core Power Down\n");
4d85529d 1352 else
267f0c90 1353 seq_puts(m, "on\n");
4d85529d
BW		 1354 break;
1355 case GEN6_RC3:
267f0c90 1356 seq_puts(m, "RC3\n");
4d85529d
BW		 1357 break;
1358 case GEN6_RC6:
267f0c90 1359 seq_puts(m, "RC6\n");
4d85529d
BW		 1360 break;
1361 case GEN6_RC7:
267f0c90 1362 seq_puts(m, "RC7\n");
4d85529d
BW		 1363 break;
1364 default:
267f0c90 1365 seq_puts(m, "Unknown\n");
4d85529d
BW		 1366 break;
1367 }
1368
1369 seq_printf(m, "Core Power Down: %s\n",
1370 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1371
1372 /* Not exactly sure what this is */
1373 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1374 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1375 seq_printf(m, "RC6 residency since boot: %u\n",
1376 I915_READ(GEN6_GT_GFX_RC6));
1377 seq_printf(m, "RC6+ residency since boot: %u\n",
1378 I915_READ(GEN6_GT_GFX_RC6p));
1379 seq_printf(m, "RC6++ residency since boot: %u\n",
1380 I915_READ(GEN6_GT_GFX_RC6pp));
1381
ecd8faea
BW		 1382 seq_printf(m, "RC6 voltage: %dmV\n",
1383 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1384 seq_printf(m, "RC6+ voltage: %dmV\n",
1385 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1386 seq_printf(m, "RC6++ voltage: %dmV\n",
1387 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1388 return 0;
1389}
1390
1391static int i915_drpc_info(struct seq_file *m, void *unused)
1392{
9f25d007 1393 struct drm_info_node *node = m->private;
4d85529d
BW		 1394 struct drm_device *dev = node->minor->dev;
1395
669ab5aa
D		 1396 if (IS_VALLEYVIEW(dev))
1397 return vlv_drpc_info(m);
ac66cf4b 1398 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1399 return gen6_drpc_info(m);
1400 else
1401 return ironlake_drpc_info(m);
1402}
1403
b5e50c3f
JB		 1404static int i915_fbc_status(struct seq_file *m, void *unused)
1405{
9f25d007 1406 struct drm_info_node *node = m->private;
b5e50c3f 1407 struct drm_device *dev = node->minor->dev;
e277a1f8 1408 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1409
3a77c4c4 1410 if (!HAS_FBC(dev)) {
267f0c90 1411 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1412 return 0;
1413 }
1414
36623ef8
PZ		 1415 intel_runtime_pm_get(dev_priv);
1416
ee5382ae 1417 if (intel_fbc_enabled(dev)) {
267f0c90 1418 seq_puts(m, "FBC enabled\n");
b5e50c3f 1419 } else {
267f0c90 1420 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1421 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1422 case FBC_OK:
1423 seq_puts(m, "FBC actived, but currently disabled in hardware");
1424 break;
1425 case FBC_UNSUPPORTED:
1426 seq_puts(m, "unsupported by this chipset");
1427 break;
bed4a673 1428 case FBC_NO_OUTPUT:
267f0c90 1429 seq_puts(m, "no outputs");
bed4a673 1430 break;
b5e50c3f 1431 case FBC_STOLEN_TOO_SMALL:
267f0c90 1432 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1433 break;
1434 case FBC_UNSUPPORTED_MODE:
267f0c90 1435 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1436 break;
1437 case FBC_MODE_TOO_LARGE:
267f0c90 1438 seq_puts(m, "mode too large");
b5e50c3f
JB		 1439 break;
1440 case FBC_BAD_PLANE:
267f0c90 1441 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1442 break;
1443 case FBC_NOT_TILED:
267f0c90 1444 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1445 break;
9c928d16 1446 case FBC_MULTIPLE_PIPES:
267f0c90 1447 seq_puts(m, "multiple pipes are enabled");
9c928d16 1448 break;
c1a9f047 1449 case FBC_MODULE_PARAM:
267f0c90 1450 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1451 break;
8a5729a3 1452 case FBC_CHIP_DEFAULT:
267f0c90 1453 seq_puts(m, "disabled per chip default");
8a5729a3 1454 break;
b5e50c3f 1455 default:
267f0c90 1456 seq_puts(m, "unknown reason");
b5e50c3f 1457 }
267f0c90 1458 seq_putc(m, '\n');
b5e50c3f 1459 }
36623ef8
PZ		 1460
1461 intel_runtime_pm_put(dev_priv);
1462
b5e50c3f
JB		 1463 return 0;
1464}
1465
da46f936
RV		 1466static int i915_fbc_fc_get(void *data, u64 *val)
1467{
1468 struct drm_device *dev = data;
1469 struct drm_i915_private *dev_priv = dev->dev_private;
1470
1471 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1472 return -ENODEV;
1473
1474 drm_modeset_lock_all(dev);
1475 *val = dev_priv->fbc.false_color;
1476 drm_modeset_unlock_all(dev);
1477
1478 return 0;
1479}
1480
1481static int i915_fbc_fc_set(void *data, u64 val)
1482{
1483 struct drm_device *dev = data;
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 u32 reg;
1486
1487 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1488 return -ENODEV;
1489
1490 drm_modeset_lock_all(dev);
1491
1492 reg = I915_READ(ILK_DPFC_CONTROL);
1493 dev_priv->fbc.false_color = val;
1494
1495 I915_WRITE(ILK_DPFC_CONTROL, val ?
1496 (reg | FBC_CTL_FALSE_COLOR) :
1497 (reg & ~FBC_CTL_FALSE_COLOR));
1498
1499 drm_modeset_unlock_all(dev);
1500 return 0;
1501}
1502
1503DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1504 i915_fbc_fc_get, i915_fbc_fc_set,
1505 "%llu\n");
1506
92d44621
PZ		 1507static int i915_ips_status(struct seq_file *m, void *unused)
1508{
9f25d007 1509 struct drm_info_node *node = m->private;
92d44621
PZ		 1510 struct drm_device *dev = node->minor->dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512
f5adf94e 1513 if (!HAS_IPS(dev)) {
92d44621
PZ		 1514 seq_puts(m, "not supported\n");
1515 return 0;
1516 }
1517
36623ef8
PZ		 1518 intel_runtime_pm_get(dev_priv);
1519
0eaa53f0
RV		 1520 seq_printf(m, "Enabled by kernel parameter: %s\n",
1521 yesno(i915.enable_ips));
1522
1523 if (INTEL_INFO(dev)->gen >= 8) {
1524 seq_puts(m, "Currently: unknown\n");
1525 } else {
1526 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1527 seq_puts(m, "Currently: enabled\n");
1528 else
1529 seq_puts(m, "Currently: disabled\n");
1530 }
92d44621 1531
36623ef8
PZ		 1532 intel_runtime_pm_put(dev_priv);
1533
92d44621
PZ		 1534 return 0;
1535}
1536
4a9bef37
JB		 1537static int i915_sr_status(struct seq_file *m, void *unused)
1538{
9f25d007 1539 struct drm_info_node *node = m->private;
4a9bef37 1540 struct drm_device *dev = node->minor->dev;
e277a1f8 1541 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1542 bool sr_enabled = false;
1543
36623ef8
PZ		 1544 intel_runtime_pm_get(dev_priv);
1545
1398261a 1546 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1547 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1548 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1549 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1550 else if (IS_I915GM(dev))
1551 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1552 else if (IS_PINEVIEW(dev))
1553 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1554
36623ef8
PZ		 1555 intel_runtime_pm_put(dev_priv);
1556
5ba2aaaa
CW		 1557 seq_printf(m, "self-refresh: %s\n",
1558 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1559
1560 return 0;
1561}
1562
7648fa99
JB		 1563static int i915_emon_status(struct seq_file *m, void *unused)
1564{
9f25d007 1565 struct drm_info_node *node = m->private;
7648fa99 1566 struct drm_device *dev = node->minor->dev;
e277a1f8 1567 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1568 unsigned long temp, chipset, gfx;
de227ef0
CW		 1569 int ret;
1570
582be6b4
CW		 1571 if (!IS_GEN5(dev))
1572 return -ENODEV;
1573
de227ef0
CW		 1574 ret = mutex_lock_interruptible(&dev->struct_mutex);
1575 if (ret)
1576 return ret;
7648fa99
JB		 1577
1578 temp = i915_mch_val(dev_priv);
1579 chipset = i915_chipset_val(dev_priv);
1580 gfx = i915_gfx_val(dev_priv);
de227ef0 1581 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1582
1583 seq_printf(m, "GMCH temp: %ld\n", temp);
1584 seq_printf(m, "Chipset power: %ld\n", chipset);
1585 seq_printf(m, "GFX power: %ld\n", gfx);
1586 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1587
1588 return 0;
1589}
1590
23b2f8bb
JB		 1591static int i915_ring_freq_table(struct seq_file *m, void *unused)
1592{
9f25d007 1593 struct drm_info_node *node = m->private;
23b2f8bb 1594 struct drm_device *dev = node->minor->dev;
e277a1f8 1595 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1596 int ret = 0;
23b2f8bb
JB		 1597 int gpu_freq, ia_freq;
1598
1c70c0ce 1599 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1600 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1601 return 0;
1602 }
1603
5bfa0199
PZ		 1604 intel_runtime_pm_get(dev_priv);
1605
5c9669ce
TR		 1606 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1607
4fc688ce 1608 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1609 if (ret)
5bfa0199 1610 goto out;
23b2f8bb 1611
267f0c90 1612 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1613
b39fb297
BW		 1614 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1615 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1616 gpu_freq++) {
42c0526c
BW		 1617 ia_freq = gpu_freq;
1618 sandybridge_pcode_read(dev_priv,
1619 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1620 &ia_freq);
3ebecd07
CW		 1621 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1622 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1623 ((ia_freq >> 0) & 0xff) * 100,
1624 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1625 }
1626
4fc688ce 1627 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1628
5bfa0199
PZ		 1629out:
1630 intel_runtime_pm_put(dev_priv);
1631 return ret;
23b2f8bb
JB		 1632}
1633
44834a67
CW		 1634static int i915_opregion(struct seq_file *m, void *unused)
1635{
9f25d007 1636 struct drm_info_node *node = m->private;
44834a67 1637 struct drm_device *dev = node->minor->dev;
e277a1f8 1638 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1639 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1640 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1641 int ret;
1642
0d38f009
DV		 1643 if (data == NULL)
1644 return -ENOMEM;
1645
44834a67
CW		 1646 ret = mutex_lock_interruptible(&dev->struct_mutex);
1647 if (ret)
0d38f009 1648 goto out;
44834a67 1649
0d38f009
DV		 1650 if (opregion->header) {
1651 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1652 seq_write(m, data, OPREGION_SIZE);
1653 }
44834a67
CW		 1654
1655 mutex_unlock(&dev->struct_mutex);
1656
0d38f009
DV		 1657out:
1658 kfree(data);
44834a67
CW		 1659 return 0;
1660}
1661
37811fcc
CW		 1662static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1663{
9f25d007 1664 struct drm_info_node *node = m->private;
37811fcc 1665 struct drm_device *dev = node->minor->dev;
4520f53a 1666 struct intel_fbdev *ifbdev = NULL;
37811fcc 1667 struct intel_framebuffer *fb;
37811fcc 1668
4520f53a
DV		 1669#ifdef CONFIG_DRM_I915_FBDEV
1670 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1671
1672 ifbdev = dev_priv->fbdev;
1673 fb = to_intel_framebuffer(ifbdev->helper.fb);
1674
623f9783 1675 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1676 fb->base.width,
1677 fb->base.height,
1678 fb->base.depth,
623f9783
DV		 1679 fb->base.bits_per_pixel,
1680 atomic_read(&fb->base.refcount.refcount));
05394f39 1681 describe_obj(m, fb->obj);
267f0c90 1682 seq_putc(m, '\n');
4520f53a 1683#endif
37811fcc 1684
4b096ac1 1685 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1686 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1687 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1688 continue;
1689
623f9783 1690 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1691 fb->base.width,
1692 fb->base.height,
1693 fb->base.depth,
623f9783
DV		 1694 fb->base.bits_per_pixel,
1695 atomic_read(&fb->base.refcount.refcount));
05394f39 1696 describe_obj(m, fb->obj);
267f0c90 1697 seq_putc(m, '\n');
37811fcc 1698 }
4b096ac1 1699 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1700
1701 return 0;
1702}
1703
c9fe99bd
OM		 1704static void describe_ctx_ringbuf(struct seq_file *m,
1705 struct intel_ringbuffer *ringbuf)
1706{
1707 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1708 ringbuf->space, ringbuf->head, ringbuf->tail,
1709 ringbuf->last_retired_head);
1710}
1711
e76d3630
BW		 1712static int i915_context_status(struct seq_file *m, void *unused)
1713{
9f25d007 1714 struct drm_info_node *node = m->private;
e76d3630 1715 struct drm_device *dev = node->minor->dev;
e277a1f8 1716 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1717 struct intel_engine_cs *ring;
273497e5 1718 struct intel_context *ctx;
a168c293 1719 int ret, i;
e76d3630 1720
f3d28878 1721 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1722 if (ret)
1723 return ret;
1724
3e373948 1725 if (dev_priv->ips.pwrctx) {
267f0c90 1726 seq_puts(m, "power context ");
3e373948 1727 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1728 seq_putc(m, '\n');
dc501fbc 1729 }
e76d3630 1730
3e373948 1731 if (dev_priv->ips.renderctx) {
267f0c90 1732 seq_puts(m, "render context ");
3e373948 1733 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1734 seq_putc(m, '\n');
dc501fbc 1735 }
e76d3630 1736
a33afea5 1737 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1738 if (!i915.enable_execlists &&
1739 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1740 continue;
1741
a33afea5 1742 seq_puts(m, "HW context ");
3ccfd19d 1743 describe_ctx(m, ctx);
c9fe99bd 1744 for_each_ring(ring, dev_priv, i) {
a33afea5 1745 if (ring->default_context == ctx)
c9fe99bd
OM		 1746 seq_printf(m, "(default context %s) ",
1747 ring->name);
1748 }
1749
1750 if (i915.enable_execlists) {
1751 seq_putc(m, '\n');
1752 for_each_ring(ring, dev_priv, i) {
1753 struct drm_i915_gem_object *ctx_obj =
1754 ctx->engine[i].state;
1755 struct intel_ringbuffer *ringbuf =
1756 ctx->engine[i].ringbuf;
1757
1758 seq_printf(m, "%s: ", ring->name);
1759 if (ctx_obj)
1760 describe_obj(m, ctx_obj);
1761 if (ringbuf)
1762 describe_ctx_ringbuf(m, ringbuf);
1763 seq_putc(m, '\n');
1764 }
1765 } else {
1766 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1767 }
a33afea5 1768
a33afea5 1769 seq_putc(m, '\n');
a168c293
BW		 1770 }
1771
f3d28878 1772 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1773
1774 return 0;
1775}
1776
c0ab1ae9
BW		 1777static int i915_dump_lrc(struct seq_file *m, void *unused)
1778{
1779 struct drm_info_node *node = (struct drm_info_node *) m->private;
1780 struct drm_device *dev = node->minor->dev;
1781 struct drm_i915_private *dev_priv = dev->dev_private;
1782 struct intel_engine_cs *ring;
1783 struct intel_context *ctx;
1784 int ret, i;
1785
1786 if (!i915.enable_execlists) {
1787 seq_printf(m, "Logical Ring Contexts are disabled\n");
1788 return 0;
1789 }
1790
1791 ret = mutex_lock_interruptible(&dev->struct_mutex);
1792 if (ret)
1793 return ret;
1794
1795 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1796 for_each_ring(ring, dev_priv, i) {
1797 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1798
1799 if (ring->default_context == ctx)
1800 continue;
1801
1802 if (ctx_obj) {
1803 struct page *page = i915_gem_object_get_page(ctx_obj, 1);
1804 uint32_t *reg_state = kmap_atomic(page);
1805 int j;
1806
1807 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1808 intel_execlists_ctx_id(ctx_obj));
1809
1810 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1811 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1812 i915_gem_obj_ggtt_offset(ctx_obj) + 4096 + (j * 4),
1813 reg_state[j], reg_state[j + 1],
1814 reg_state[j + 2], reg_state[j + 3]);
1815 }
1816 kunmap_atomic(reg_state);
1817
1818 seq_putc(m, '\n');
1819 }
1820 }
1821 }
1822
1823 mutex_unlock(&dev->struct_mutex);
1824
1825 return 0;
1826}
1827
4ba70e44
OM		 1828static int i915_execlists(struct seq_file *m, void *data)
1829{
1830 struct drm_info_node *node = (struct drm_info_node *)m->private;
1831 struct drm_device *dev = node->minor->dev;
1832 struct drm_i915_private *dev_priv = dev->dev_private;
1833 struct intel_engine_cs *ring;
1834 u32 status_pointer;
1835 u8 read_pointer;
1836 u8 write_pointer;
1837 u32 status;
1838 u32 ctx_id;
1839 struct list_head *cursor;
1840 int ring_id, i;
1841 int ret;
1842
1843 if (!i915.enable_execlists) {
1844 seq_puts(m, "Logical Ring Contexts are disabled\n");
1845 return 0;
1846 }
1847
1848 ret = mutex_lock_interruptible(&dev->struct_mutex);
1849 if (ret)
1850 return ret;
1851
1852 for_each_ring(ring, dev_priv, ring_id) {
1853 struct intel_ctx_submit_request *head_req = NULL;
1854 int count = 0;
1855 unsigned long flags;
1856
1857 seq_printf(m, "%s\n", ring->name);
1858
1859 status = I915_READ(RING_EXECLIST_STATUS(ring));
1860 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1861 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1862 status, ctx_id);
1863
1864 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1865 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1866
1867 read_pointer = ring->next_context_status_buffer;
1868 write_pointer = status_pointer & 0x07;
1869 if (read_pointer > write_pointer)
1870 write_pointer += 6;
1871 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1872 read_pointer, write_pointer);
1873
1874 for (i = 0; i < 6; i++) {
1875 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1876 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1877
1878 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1879 i, status, ctx_id);
1880 }
1881
1882 spin_lock_irqsave(&ring->execlist_lock, flags);
1883 list_for_each(cursor, &ring->execlist_queue)
1884 count++;
1885 head_req = list_first_entry_or_null(&ring->execlist_queue,
1886 struct intel_ctx_submit_request, execlist_link);
1887 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1888
1889 seq_printf(m, "\t%d requests in queue\n", count);
1890 if (head_req) {
1891 struct drm_i915_gem_object *ctx_obj;
1892
1893 ctx_obj = head_req->ctx->engine[ring_id].state;
1894 seq_printf(m, "\tHead request id: %u\n",
1895 intel_execlists_ctx_id(ctx_obj));
1896 seq_printf(m, "\tHead request tail: %u\n",
1897 head_req->tail);
1898 }
1899
1900 seq_putc(m, '\n');
1901 }
1902
1903 mutex_unlock(&dev->struct_mutex);
1904
1905 return 0;
1906}
1907
6d794d42
BW		 1908static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1909{
9f25d007 1910 struct drm_info_node *node = m->private;
6d794d42
BW		 1911 struct drm_device *dev = node->minor->dev;
1912 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1913 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1914
907b28c5 1915 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1916 if (IS_VALLEYVIEW(dev)) {
1917 fw_rendercount = dev_priv->uncore.fw_rendercount;
1918 fw_mediacount = dev_priv->uncore.fw_mediacount;
1919 } else
1920 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1921 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1922
43709ba0
D		 1923 if (IS_VALLEYVIEW(dev)) {
1924 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1925 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1926 } else
1927 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1928
1929 return 0;
1930}
1931
ea16a3cd
DV		 1932static const char *swizzle_string(unsigned swizzle)
1933{
aee56cff 1934 switch (swizzle) {
ea16a3cd
DV		 1935 case I915_BIT_6_SWIZZLE_NONE:
1936 return "none";
1937 case I915_BIT_6_SWIZZLE_9:
1938 return "bit9";
1939 case I915_BIT_6_SWIZZLE_9_10:
1940 return "bit9/bit10";
1941 case I915_BIT_6_SWIZZLE_9_11:
1942 return "bit9/bit11";
1943 case I915_BIT_6_SWIZZLE_9_10_11:
1944 return "bit9/bit10/bit11";
1945 case I915_BIT_6_SWIZZLE_9_17:
1946 return "bit9/bit17";
1947 case I915_BIT_6_SWIZZLE_9_10_17:
1948 return "bit9/bit10/bit17";
1949 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1950 return "unknown";
ea16a3cd
DV		 1951 }
1952
1953 return "bug";
1954}
1955
1956static int i915_swizzle_info(struct seq_file *m, void *data)
1957{
9f25d007 1958 struct drm_info_node *node = m->private;
ea16a3cd
DV		 1959 struct drm_device *dev = node->minor->dev;
1960 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1961 int ret;
1962
1963 ret = mutex_lock_interruptible(&dev->struct_mutex);
1964 if (ret)
1965 return ret;
c8c8fb33 1966 intel_runtime_pm_get(dev_priv);
ea16a3cd 1967
ea16a3cd
DV		 1968 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1969 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1970 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1971 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1972
1973 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1974 seq_printf(m, "DDC = 0x%08x\n",
1975 I915_READ(DCC));
1976 seq_printf(m, "C0DRB3 = 0x%04x\n",
1977 I915_READ16(C0DRB3));
1978 seq_printf(m, "C1DRB3 = 0x%04x\n",
1979 I915_READ16(C1DRB3));
9d3203e1 1980 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1981 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1982 I915_READ(MAD_DIMM_C0));
1983 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1984 I915_READ(MAD_DIMM_C1));
1985 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1986 I915_READ(MAD_DIMM_C2));
1987 seq_printf(m, "TILECTL = 0x%08x\n",
1988 I915_READ(TILECTL));
9d3203e1
BW		 1989 if (IS_GEN8(dev))
1990 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1991 I915_READ(GAMTARBMODE));
1992 else
1993 seq_printf(m, "ARB_MODE = 0x%08x\n",
1994 I915_READ(ARB_MODE));
3fa7d235
DV		 1995 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1996 I915_READ(DISP_ARB_CTL));
ea16a3cd 1997 }
c8c8fb33 1998 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 1999 mutex_unlock(&dev->struct_mutex);
2000
2001 return 0;
2002}
2003
1c60fef5
BW		 2004static int per_file_ctx(int id, void *ptr, void *data)
2005{
273497e5 2006 struct intel_context *ctx = ptr;
1c60fef5 2007 struct seq_file *m = data;
ae6c4806
DV		 2008 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2009
2010 if (!ppgtt) {
2011 seq_printf(m, " no ppgtt for context %d\n",
2012 ctx->user_handle);
2013 return 0;
2014 }
1c60fef5 2015
f83d6518
OM		 2016 if (i915_gem_context_is_default(ctx))
2017 seq_puts(m, " default context:\n");
2018 else
821d66dd 2019 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2020 ppgtt->debug_dump(ppgtt, m);
2021
2022 return 0;
2023}
2024
77df6772 2025static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2026{
3cf17fc5 2027 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2028 struct intel_engine_cs *ring;
77df6772
BW		 2029 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2030 int unused, i;
3cf17fc5 2031
77df6772
BW		 2032 if (!ppgtt)
2033 return;
2034
2035 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2036 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2037 for_each_ring(ring, dev_priv, unused) {
2038 seq_printf(m, "%s\n", ring->name);
2039 for (i = 0; i < 4; i++) {
2040 u32 offset = 0x270 + i * 8;
2041 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2042 pdp <<= 32;
2043 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2044 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2045 }
2046 }
2047}
2048
2049static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2050{
2051 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2052 struct intel_engine_cs *ring;
1c60fef5 2053 struct drm_file *file;
77df6772 2054 int i;
3cf17fc5 2055
3cf17fc5
DV		 2056 if (INTEL_INFO(dev)->gen == 6)
2057 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2058
a2c7f6fd 2059 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2060 seq_printf(m, "%s\n", ring->name);
2061 if (INTEL_INFO(dev)->gen == 7)
2062 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2063 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2064 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2065 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2066 }
2067 if (dev_priv->mm.aliasing_ppgtt) {
2068 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2069
267f0c90 2070 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 2071 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 2072
87d60b63 2073 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2074 }
1c60fef5
BW		 2075
2076 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2077 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2078
1c60fef5
BW		 2079 seq_printf(m, "proc: %s\n",
2080 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2081 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2082 }
2083 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2084}
2085
2086static int i915_ppgtt_info(struct seq_file *m, void *data)
2087{
9f25d007 2088 struct drm_info_node *node = m->private;
77df6772 2089 struct drm_device *dev = node->minor->dev;
c8c8fb33 2090 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2091
2092 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2093 if (ret)
2094 return ret;
c8c8fb33 2095 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2096
2097 if (INTEL_INFO(dev)->gen >= 8)
2098 gen8_ppgtt_info(m, dev);
2099 else if (INTEL_INFO(dev)->gen >= 6)
2100 gen6_ppgtt_info(m, dev);
2101
c8c8fb33 2102 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2103 mutex_unlock(&dev->struct_mutex);
2104
2105 return 0;
2106}
2107
63573eb7
BW		 2108static int i915_llc(struct seq_file *m, void *data)
2109{
9f25d007 2110 struct drm_info_node *node = m->private;
63573eb7
BW		 2111 struct drm_device *dev = node->minor->dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113
2114 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2115 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2116 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2117
2118 return 0;
2119}
2120
e91fd8c6
RV		 2121static int i915_edp_psr_status(struct seq_file *m, void *data)
2122{
2123 struct drm_info_node *node = m->private;
2124 struct drm_device *dev = node->minor->dev;
2125 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 2126 u32 psrperf = 0;
2127 bool enabled = false;
e91fd8c6 2128
c8c8fb33
PZ		 2129 intel_runtime_pm_get(dev_priv);
2130
fa128fa6 2131 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2132 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2133 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2134 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2135 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2136 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2137 dev_priv->psr.busy_frontbuffer_bits);
2138 seq_printf(m, "Re-enable work scheduled: %s\n",
2139 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2140
a031d709
RV		 2141 enabled = HAS_PSR(dev) &&
2142 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
5755c78f 2143 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
e91fd8c6 2144
a031d709
RV		 2145 if (HAS_PSR(dev))
2146 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2147 EDP_PSR_PERF_CNT_MASK;
2148 seq_printf(m, "Performance_Counter: %u\n", psrperf);
fa128fa6 2149 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2150
c8c8fb33 2151 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2152 return 0;
2153}
2154
d2e216d0
RV		 2155static int i915_sink_crc(struct seq_file *m, void *data)
2156{
2157 struct drm_info_node *node = m->private;
2158 struct drm_device *dev = node->minor->dev;
2159 struct intel_encoder *encoder;
2160 struct intel_connector *connector;
2161 struct intel_dp *intel_dp = NULL;
2162 int ret;
2163 u8 crc[6];
2164
2165 drm_modeset_lock_all(dev);
2166 list_for_each_entry(connector, &dev->mode_config.connector_list,
2167 base.head) {
2168
2169 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2170 continue;
2171
b6ae3c7c
PZ		 2172 if (!connector->base.encoder)
2173 continue;
2174
d2e216d0
RV		 2175 encoder = to_intel_encoder(connector->base.encoder);
2176 if (encoder->type != INTEL_OUTPUT_EDP)
2177 continue;
2178
2179 intel_dp = enc_to_intel_dp(&encoder->base);
2180
2181 ret = intel_dp_sink_crc(intel_dp, crc);
2182 if (ret)
2183 goto out;
2184
2185 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2186 crc[0], crc[1], crc[2],
2187 crc[3], crc[4], crc[5]);
2188 goto out;
2189 }
2190 ret = -ENODEV;
2191out:
2192 drm_modeset_unlock_all(dev);
2193 return ret;
2194}
2195
ec013e7f
JB		 2196static int i915_energy_uJ(struct seq_file *m, void *data)
2197{
2198 struct drm_info_node *node = m->private;
2199 struct drm_device *dev = node->minor->dev;
2200 struct drm_i915_private *dev_priv = dev->dev_private;
2201 u64 power;
2202 u32 units;
2203
2204 if (INTEL_INFO(dev)->gen < 6)
2205 return -ENODEV;
2206
36623ef8
PZ		 2207 intel_runtime_pm_get(dev_priv);
2208
ec013e7f
JB		 2209 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2210 power = (power & 0x1f00) >> 8;
2211 units = 1000000 / (1 << power); /* convert to uJ */
2212 power = I915_READ(MCH_SECP_NRG_STTS);
2213 power *= units;
2214
36623ef8
PZ		 2215 intel_runtime_pm_put(dev_priv);
2216
ec013e7f 2217 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2218
2219 return 0;
2220}
2221
2222static int i915_pc8_status(struct seq_file *m, void *unused)
2223{
9f25d007 2224 struct drm_info_node *node = m->private;
371db66a
PZ		 2225 struct drm_device *dev = node->minor->dev;
2226 struct drm_i915_private *dev_priv = dev->dev_private;
2227
85b8d5c2 2228 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2229 seq_puts(m, "not supported\n");
2230 return 0;
2231 }
2232
86c4ec0d 2233 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2234 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2235 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2236
ec013e7f
JB		 2237 return 0;
2238}
2239
1da51581
ID		 2240static const char *power_domain_str(enum intel_display_power_domain domain)
2241{
2242 switch (domain) {
2243 case POWER_DOMAIN_PIPE_A:
2244 return "PIPE_A";
2245 case POWER_DOMAIN_PIPE_B:
2246 return "PIPE_B";
2247 case POWER_DOMAIN_PIPE_C:
2248 return "PIPE_C";
2249 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2250 return "PIPE_A_PANEL_FITTER";
2251 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2252 return "PIPE_B_PANEL_FITTER";
2253 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2254 return "PIPE_C_PANEL_FITTER";
2255 case POWER_DOMAIN_TRANSCODER_A:
2256 return "TRANSCODER_A";
2257 case POWER_DOMAIN_TRANSCODER_B:
2258 return "TRANSCODER_B";
2259 case POWER_DOMAIN_TRANSCODER_C:
2260 return "TRANSCODER_C";
2261 case POWER_DOMAIN_TRANSCODER_EDP:
2262 return "TRANSCODER_EDP";
319be8ae
ID		 2263 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2264 return "PORT_DDI_A_2_LANES";
2265 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2266 return "PORT_DDI_A_4_LANES";
2267 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2268 return "PORT_DDI_B_2_LANES";
2269 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2270 return "PORT_DDI_B_4_LANES";
2271 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2272 return "PORT_DDI_C_2_LANES";
2273 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2274 return "PORT_DDI_C_4_LANES";
2275 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2276 return "PORT_DDI_D_2_LANES";
2277 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2278 return "PORT_DDI_D_4_LANES";
2279 case POWER_DOMAIN_PORT_DSI:
2280 return "PORT_DSI";
2281 case POWER_DOMAIN_PORT_CRT:
2282 return "PORT_CRT";
2283 case POWER_DOMAIN_PORT_OTHER:
2284 return "PORT_OTHER";
1da51581
ID		 2285 case POWER_DOMAIN_VGA:
2286 return "VGA";
2287 case POWER_DOMAIN_AUDIO:
2288 return "AUDIO";
bd2bb1b9
PZ		 2289 case POWER_DOMAIN_PLLS:
2290 return "PLLS";
1da51581
ID		 2291 case POWER_DOMAIN_INIT:
2292 return "INIT";
2293 default:
2294 WARN_ON(1);
2295 return "?";
2296 }
2297}
2298
2299static int i915_power_domain_info(struct seq_file *m, void *unused)
2300{
9f25d007 2301 struct drm_info_node *node = m->private;
1da51581
ID		 2302 struct drm_device *dev = node->minor->dev;
2303 struct drm_i915_private *dev_priv = dev->dev_private;
2304 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2305 int i;
2306
2307 mutex_lock(&power_domains->lock);
2308
2309 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2310 for (i = 0; i < power_domains->power_well_count; i++) {
2311 struct i915_power_well *power_well;
2312 enum intel_display_power_domain power_domain;
2313
2314 power_well = &power_domains->power_wells[i];
2315 seq_printf(m, "%-25s %d\n", power_well->name,
2316 power_well->count);
2317
2318 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2319 power_domain++) {
2320 if (!(BIT(power_domain) & power_well->domains))
2321 continue;
2322
2323 seq_printf(m, " %-23s %d\n",
2324 power_domain_str(power_domain),
2325 power_domains->domain_use_count[power_domain]);
2326 }
2327 }
2328
2329 mutex_unlock(&power_domains->lock);
2330
2331 return 0;
2332}
2333
53f5e3ca
JB		 2334static void intel_seq_print_mode(struct seq_file *m, int tabs,
2335 struct drm_display_mode *mode)
2336{
2337 int i;
2338
2339 for (i = 0; i < tabs; i++)
2340 seq_putc(m, '\t');
2341
2342 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2343 mode->base.id, mode->name,
2344 mode->vrefresh, mode->clock,
2345 mode->hdisplay, mode->hsync_start,
2346 mode->hsync_end, mode->htotal,
2347 mode->vdisplay, mode->vsync_start,
2348 mode->vsync_end, mode->vtotal,
2349 mode->type, mode->flags);
2350}
2351
2352static void intel_encoder_info(struct seq_file *m,
2353 struct intel_crtc *intel_crtc,
2354 struct intel_encoder *intel_encoder)
2355{
9f25d007 2356 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2357 struct drm_device *dev = node->minor->dev;
2358 struct drm_crtc *crtc = &intel_crtc->base;
2359 struct intel_connector *intel_connector;
2360 struct drm_encoder *encoder;
2361
2362 encoder = &intel_encoder->base;
2363 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2364 encoder->base.id, encoder->name);
53f5e3ca
JB		 2365 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2366 struct drm_connector *connector = &intel_connector->base;
2367 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2368 connector->base.id,
c23cc417 2369 connector->name,
53f5e3ca
JB		 2370 drm_get_connector_status_name(connector->status));
2371 if (connector->status == connector_status_connected) {
2372 struct drm_display_mode *mode = &crtc->mode;
2373 seq_printf(m, ", mode:\n");
2374 intel_seq_print_mode(m, 2, mode);
2375 } else {
2376 seq_putc(m, '\n');
2377 }
2378 }
2379}
2380
2381static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2382{
9f25d007 2383 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2384 struct drm_device *dev = node->minor->dev;
2385 struct drm_crtc *crtc = &intel_crtc->base;
2386 struct intel_encoder *intel_encoder;
2387
5aa8a937
MR		 2388 if (crtc->primary->fb)
2389 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2390 crtc->primary->fb->base.id, crtc->x, crtc->y,
2391 crtc->primary->fb->width, crtc->primary->fb->height);
2392 else
2393 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2394 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2395 intel_encoder_info(m, intel_crtc, intel_encoder);
2396}
2397
2398static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2399{
2400 struct drm_display_mode *mode = panel->fixed_mode;
2401
2402 seq_printf(m, "\tfixed mode:\n");
2403 intel_seq_print_mode(m, 2, mode);
2404}
2405
2406static void intel_dp_info(struct seq_file *m,
2407 struct intel_connector *intel_connector)
2408{
2409 struct intel_encoder *intel_encoder = intel_connector->encoder;
2410 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2411
2412 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2413 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2414 "no");
2415 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2416 intel_panel_info(m, &intel_connector->panel);
2417}
2418
2419static void intel_hdmi_info(struct seq_file *m,
2420 struct intel_connector *intel_connector)
2421{
2422 struct intel_encoder *intel_encoder = intel_connector->encoder;
2423 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2424
2425 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2426 "no");
2427}
2428
2429static void intel_lvds_info(struct seq_file *m,
2430 struct intel_connector *intel_connector)
2431{
2432 intel_panel_info(m, &intel_connector->panel);
2433}
2434
2435static void intel_connector_info(struct seq_file *m,
2436 struct drm_connector *connector)
2437{
2438 struct intel_connector *intel_connector = to_intel_connector(connector);
2439 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2440 struct drm_display_mode *mode;
53f5e3ca
JB		 2441
2442 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2443 connector->base.id, connector->name,
53f5e3ca
JB		 2444 drm_get_connector_status_name(connector->status));
2445 if (connector->status == connector_status_connected) {
2446 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2447 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2448 connector->display_info.width_mm,
2449 connector->display_info.height_mm);
2450 seq_printf(m, "\tsubpixel order: %s\n",
2451 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2452 seq_printf(m, "\tCEA rev: %d\n",
2453 connector->display_info.cea_rev);
2454 }
36cd7444
DA		 2455 if (intel_encoder) {
2456 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2457 intel_encoder->type == INTEL_OUTPUT_EDP)
2458 intel_dp_info(m, intel_connector);
2459 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2460 intel_hdmi_info(m, intel_connector);
2461 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2462 intel_lvds_info(m, intel_connector);
2463 }
53f5e3ca 2464
f103fc7d
JB		 2465 seq_printf(m, "\tmodes:\n");
2466 list_for_each_entry(mode, &connector->modes, head)
2467 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2468}
2469
065f2ec2
CW		 2470static bool cursor_active(struct drm_device *dev, int pipe)
2471{
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473 u32 state;
2474
2475 if (IS_845G(dev) || IS_I865G(dev))
2476 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2477 else
5efb3e28 2478 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2479
2480 return state;
2481}
2482
2483static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2484{
2485 struct drm_i915_private *dev_priv = dev->dev_private;
2486 u32 pos;
2487
5efb3e28 2488 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2489
2490 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2491 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2492 *x = -*x;
2493
2494 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2495 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2496 *y = -*y;
2497
2498 return cursor_active(dev, pipe);
2499}
2500
53f5e3ca
JB		 2501static int i915_display_info(struct seq_file *m, void *unused)
2502{
9f25d007 2503 struct drm_info_node *node = m->private;
53f5e3ca 2504 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2505 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2506 struct intel_crtc *crtc;
53f5e3ca
JB		 2507 struct drm_connector *connector;
2508
b0e5ddf3 2509 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2510 drm_modeset_lock_all(dev);
2511 seq_printf(m, "CRTC info\n");
2512 seq_printf(m, "---------\n");
d3fcc808 2513 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2514 bool active;
2515 int x, y;
53f5e3ca 2516
57127efa 2517 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2518 crtc->base.base.id, pipe_name(crtc->pipe),
57127efa 2519 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
a23dc658 2520 if (crtc->active) {
065f2ec2
CW		 2521 intel_crtc_info(m, crtc);
2522
a23dc658 2523 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2524 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2525 yesno(crtc->cursor_base),
57127efa
CW		 2526 x, y, crtc->cursor_width, crtc->cursor_height,
2527 crtc->cursor_addr, yesno(active));
a23dc658 2528 }
cace841c
DV		 2529
2530 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2531 yesno(!crtc->cpu_fifo_underrun_disabled),
2532 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2533 }
2534
2535 seq_printf(m, "\n");
2536 seq_printf(m, "Connector info\n");
2537 seq_printf(m, "--------------\n");
2538 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2539 intel_connector_info(m, connector);
2540 }
2541 drm_modeset_unlock_all(dev);
b0e5ddf3 2542 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2543
2544 return 0;
2545}
2546
e04934cf
BW		 2547static int i915_semaphore_status(struct seq_file *m, void *unused)
2548{
2549 struct drm_info_node *node = (struct drm_info_node *) m->private;
2550 struct drm_device *dev = node->minor->dev;
2551 struct drm_i915_private *dev_priv = dev->dev_private;
2552 struct intel_engine_cs *ring;
2553 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2554 int i, j, ret;
2555
2556 if (!i915_semaphore_is_enabled(dev)) {
2557 seq_puts(m, "Semaphores are disabled\n");
2558 return 0;
2559 }
2560
2561 ret = mutex_lock_interruptible(&dev->struct_mutex);
2562 if (ret)
2563 return ret;
03872064 2564 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2565
2566 if (IS_BROADWELL(dev)) {
2567 struct page *page;
2568 uint64_t *seqno;
2569
2570 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2571
2572 seqno = (uint64_t *)kmap_atomic(page);
2573 for_each_ring(ring, dev_priv, i) {
2574 uint64_t offset;
2575
2576 seq_printf(m, "%s\n", ring->name);
2577
2578 seq_puts(m, " Last signal:");
2579 for (j = 0; j < num_rings; j++) {
2580 offset = i * I915_NUM_RINGS + j;
2581 seq_printf(m, "0x%08llx (0x%02llx) ",
2582 seqno[offset], offset * 8);
2583 }
2584 seq_putc(m, '\n');
2585
2586 seq_puts(m, " Last wait: ");
2587 for (j = 0; j < num_rings; j++) {
2588 offset = i + (j * I915_NUM_RINGS);
2589 seq_printf(m, "0x%08llx (0x%02llx) ",
2590 seqno[offset], offset * 8);
2591 }
2592 seq_putc(m, '\n');
2593
2594 }
2595 kunmap_atomic(seqno);
2596 } else {
2597 seq_puts(m, " Last signal:");
2598 for_each_ring(ring, dev_priv, i)
2599 for (j = 0; j < num_rings; j++)
2600 seq_printf(m, "0x%08x\n",
2601 I915_READ(ring->semaphore.mbox.signal[j]));
2602 seq_putc(m, '\n');
2603 }
2604
2605 seq_puts(m, "\nSync seqno:\n");
2606 for_each_ring(ring, dev_priv, i) {
2607 for (j = 0; j < num_rings; j++) {
2608 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2609 }
2610 seq_putc(m, '\n');
2611 }
2612 seq_putc(m, '\n');
2613
03872064 2614 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2615 mutex_unlock(&dev->struct_mutex);
2616 return 0;
2617}
2618
728e29d7
DV		 2619static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2620{
2621 struct drm_info_node *node = (struct drm_info_node *) m->private;
2622 struct drm_device *dev = node->minor->dev;
2623 struct drm_i915_private *dev_priv = dev->dev_private;
2624 int i;
2625
2626 drm_modeset_lock_all(dev);
2627 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2628 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2629
2630 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2631 seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount,
2632 pll->active, yesno(pll->on));
2633 seq_printf(m, " tracked hardware state:\n");
2634 seq_printf(m, " dpll: 0x%08x\n", pll->hw_state.dpll);
2635 seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);
2636 seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0);
2637 seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1);
d452c5b6 2638 seq_printf(m, " wrpll: 0x%08x\n", pll->hw_state.wrpll);
728e29d7
DV		 2639 }
2640 drm_modeset_unlock_all(dev);
2641
2642 return 0;
2643}
2644
1ed1ef9d 2645static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2646{
2647 int i;
2648 int ret;
2649 struct drm_info_node *node = (struct drm_info_node *) m->private;
2650 struct drm_device *dev = node->minor->dev;
2651 struct drm_i915_private *dev_priv = dev->dev_private;
2652
888b5995
AS		 2653 ret = mutex_lock_interruptible(&dev->struct_mutex);
2654 if (ret)
2655 return ret;
2656
2657 intel_runtime_pm_get(dev_priv);
2658
2659 seq_printf(m, "Workarounds applied: %d\n", dev_priv->num_wa_regs);
2660 for (i = 0; i < dev_priv->num_wa_regs; ++i) {
2661 u32 addr, mask;
2662
2663 addr = dev_priv->intel_wa_regs[i].addr;
2664 mask = dev_priv->intel_wa_regs[i].mask;
2665 dev_priv->intel_wa_regs[i].value = I915_READ(addr) | mask;
2666 if (dev_priv->intel_wa_regs[i].addr)
2667 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
2668 dev_priv->intel_wa_regs[i].addr,
2669 dev_priv->intel_wa_regs[i].value,
2670 dev_priv->intel_wa_regs[i].mask);
2671 }
2672
2673 intel_runtime_pm_put(dev_priv);
2674 mutex_unlock(&dev->struct_mutex);
2675
2676 return 0;
2677}
2678
07144428
DL		 2679struct pipe_crc_info {
2680 const char *name;
2681 struct drm_device *dev;
2682 enum pipe pipe;
2683};
2684
11bed958
DA		 2685static int i915_dp_mst_info(struct seq_file *m, void *unused)
2686{
2687 struct drm_info_node *node = (struct drm_info_node *) m->private;
2688 struct drm_device *dev = node->minor->dev;
2689 struct drm_encoder *encoder;
2690 struct intel_encoder *intel_encoder;
2691 struct intel_digital_port *intel_dig_port;
2692 drm_modeset_lock_all(dev);
2693 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2694 intel_encoder = to_intel_encoder(encoder);
2695 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2696 continue;
2697 intel_dig_port = enc_to_dig_port(encoder);
2698 if (!intel_dig_port->dp.can_mst)
2699 continue;
2700
2701 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2702 }
2703 drm_modeset_unlock_all(dev);
2704 return 0;
2705}
2706
07144428
DL		 2707static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2708{
be5c7a90
DL		 2709 struct pipe_crc_info *info = inode->i_private;
2710 struct drm_i915_private *dev_priv = info->dev->dev_private;
2711 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2712
7eb1c496
DV		 2713 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2714 return -ENODEV;
2715
d538bbdf
DL		 2716 spin_lock_irq(&pipe_crc->lock);
2717
2718 if (pipe_crc->opened) {
2719 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2720 return -EBUSY; /* already open */
2721 }
2722
d538bbdf 2723 pipe_crc->opened = true;
07144428
DL		 2724 filep->private_data = inode->i_private;
2725
d538bbdf
DL		 2726 spin_unlock_irq(&pipe_crc->lock);
2727
07144428
DL		 2728 return 0;
2729}
2730
2731static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2732{
be5c7a90
DL		 2733 struct pipe_crc_info *info = inode->i_private;
2734 struct drm_i915_private *dev_priv = info->dev->dev_private;
2735 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2736
d538bbdf
DL		 2737 spin_lock_irq(&pipe_crc->lock);
2738 pipe_crc->opened = false;
2739 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2740
07144428
DL		 2741 return 0;
2742}
2743
2744/* (6 fields, 8 chars each, space separated (5) + '\n') */
2745#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2746/* account for \'0' */
2747#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2748
2749static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2750{
d538bbdf
DL		 2751 assert_spin_locked(&pipe_crc->lock);
2752 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2753 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2754}
2755
2756static ssize_t
2757i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2758 loff_t *pos)
2759{
2760 struct pipe_crc_info *info = filep->private_data;
2761 struct drm_device *dev = info->dev;
2762 struct drm_i915_private *dev_priv = dev->dev_private;
2763 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2764 char buf[PIPE_CRC_BUFFER_LEN];
2765 int head, tail, n_entries, n;
2766 ssize_t bytes_read;
2767
2768 /*
2769 * Don't allow user space to provide buffers not big enough to hold
2770 * a line of data.
2771 */
2772 if (count < PIPE_CRC_LINE_LEN)
2773 return -EINVAL;
2774
2775 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2776 return 0;
07144428
DL		 2777
2778 /* nothing to read */
d538bbdf 2779 spin_lock_irq(&pipe_crc->lock);
07144428 2780 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2781 int ret;
2782
2783 if (filep->f_flags & O_NONBLOCK) {
2784 spin_unlock_irq(&pipe_crc->lock);
07144428 2785 return -EAGAIN;
d538bbdf 2786 }
07144428 2787
d538bbdf
DL		 2788 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2789 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2790 if (ret) {
2791 spin_unlock_irq(&pipe_crc->lock);
2792 return ret;
2793 }
8bf1e9f1
SH		 2794 }
2795
07144428 2796 /* We now have one or more entries to read */
d538bbdf
DL		 2797 head = pipe_crc->head;
2798 tail = pipe_crc->tail;
07144428
DL		 2799 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2800 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2801 spin_unlock_irq(&pipe_crc->lock);
2802
07144428
DL		 2803 bytes_read = 0;
2804 n = 0;
2805 do {
b2c88f5b 2806 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2807 int ret;
8bf1e9f1 2808
07144428
DL		 2809 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2810 "%8u %8x %8x %8x %8x %8x\n",
2811 entry->frame, entry->crc[0],
2812 entry->crc[1], entry->crc[2],
2813 entry->crc[3], entry->crc[4]);
2814
2815 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2816 buf, PIPE_CRC_LINE_LEN);
2817 if (ret == PIPE_CRC_LINE_LEN)
2818 return -EFAULT;
b2c88f5b
DL		 2819
2820 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2821 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2822 n++;
2823 } while (--n_entries);
8bf1e9f1 2824
d538bbdf
DL		 2825 spin_lock_irq(&pipe_crc->lock);
2826 pipe_crc->tail = tail;
2827 spin_unlock_irq(&pipe_crc->lock);
2828
07144428
DL		 2829 return bytes_read;
2830}
2831
2832static const struct file_operations i915_pipe_crc_fops = {
2833 .owner = THIS_MODULE,
2834 .open = i915_pipe_crc_open,
2835 .read = i915_pipe_crc_read,
2836 .release = i915_pipe_crc_release,
2837};
2838
2839static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2840 {
2841 .name = "i915_pipe_A_crc",
2842 .pipe = PIPE_A,
2843 },
2844 {
2845 .name = "i915_pipe_B_crc",
2846 .pipe = PIPE_B,
2847 },
2848 {
2849 .name = "i915_pipe_C_crc",
2850 .pipe = PIPE_C,
2851 },
2852};
2853
2854static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2855 enum pipe pipe)
2856{
2857 struct drm_device *dev = minor->dev;
2858 struct dentry *ent;
2859 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2860
2861 info->dev = dev;
2862 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2863 &i915_pipe_crc_fops);
f3c5fe97
WY		 2864 if (!ent)
2865 return -ENOMEM;
07144428
DL		 2866
2867 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2868}
2869
e8dfcf78 2870static const char * const pipe_crc_sources[] = {
926321d5
DV		 2871 "none",
2872 "plane1",
2873 "plane2",
2874 "pf",
5b3a856b 2875 "pipe",
3d099a05
DV		 2876 "TV",
2877 "DP-B",
2878 "DP-C",
2879 "DP-D",
46a19188 2880 "auto",
926321d5
DV		 2881};
2882
2883static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2884{
2885 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2886 return pipe_crc_sources[source];
2887}
2888
bd9db02f 2889static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2890{
2891 struct drm_device *dev = m->private;
2892 struct drm_i915_private *dev_priv = dev->dev_private;
2893 int i;
2894
2895 for (i = 0; i < I915_MAX_PIPES; i++)
2896 seq_printf(m, "%c %s\n", pipe_name(i),
2897 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2898
2899 return 0;
2900}
2901
bd9db02f 2902static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2903{
2904 struct drm_device *dev = inode->i_private;
2905
bd9db02f 2906 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2907}
2908
46a19188 2909static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2910 uint32_t *val)
2911{
46a19188
DV		 2912 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2913 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2914
2915 switch (*source) {
52f843f6
DV		 2916 case INTEL_PIPE_CRC_SOURCE_PIPE:
2917 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2918 break;
2919 case INTEL_PIPE_CRC_SOURCE_NONE:
2920 *val = 0;
2921 break;
2922 default:
2923 return -EINVAL;
2924 }
2925
2926 return 0;
2927}
2928
46a19188
DV		 2929static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2930 enum intel_pipe_crc_source *source)
2931{
2932 struct intel_encoder *encoder;
2933 struct intel_crtc *crtc;
26756809 2934 struct intel_digital_port *dig_port;
46a19188
DV		 2935 int ret = 0;
2936
2937 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2938
6e9f798d 2939 drm_modeset_lock_all(dev);
b2784e15 2940 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 2941 if (!encoder->base.crtc)
2942 continue;
2943
2944 crtc = to_intel_crtc(encoder->base.crtc);
2945
2946 if (crtc->pipe != pipe)
2947 continue;
2948
2949 switch (encoder->type) {
2950 case INTEL_OUTPUT_TVOUT:
2951 *source = INTEL_PIPE_CRC_SOURCE_TV;
2952 break;
2953 case INTEL_OUTPUT_DISPLAYPORT:
2954 case INTEL_OUTPUT_EDP:
26756809
DV		 2955 dig_port = enc_to_dig_port(&encoder->base);
2956 switch (dig_port->port) {
2957 case PORT_B:
2958 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2959 break;
2960 case PORT_C:
2961 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2962 break;
2963 case PORT_D:
2964 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2965 break;
2966 default:
2967 WARN(1, "nonexisting DP port %c\n",
2968 port_name(dig_port->port));
2969 break;
2970 }
46a19188
DV		 2971 break;
2972 }
2973 }
6e9f798d 2974 drm_modeset_unlock_all(dev);
46a19188
DV		 2975
2976 return ret;
2977}
2978
2979static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2980 enum pipe pipe,
2981 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2982 uint32_t *val)
2983{
8d2f24ca
DV		 2984 struct drm_i915_private *dev_priv = dev->dev_private;
2985 bool need_stable_symbols = false;
2986
46a19188
DV		 2987 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2988 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2989 if (ret)
2990 return ret;
2991 }
2992
2993 switch (*source) {
7ac0129b
DV		 2994 case INTEL_PIPE_CRC_SOURCE_PIPE:
2995 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2996 break;
2997 case INTEL_PIPE_CRC_SOURCE_DP_B:
2998 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2999 need_stable_symbols = true;
7ac0129b
DV		 3000 break;
3001 case INTEL_PIPE_CRC_SOURCE_DP_C:
3002 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3003 need_stable_symbols = true;
7ac0129b
DV		 3004 break;
3005 case INTEL_PIPE_CRC_SOURCE_NONE:
3006 *val = 0;
3007 break;
3008 default:
3009 return -EINVAL;
3010 }
3011
8d2f24ca
DV		 3012 /*
3013 * When the pipe CRC tap point is after the transcoders we need
3014 * to tweak symbol-level features to produce a deterministic series of
3015 * symbols for a given frame. We need to reset those features only once
3016 * a frame (instead of every nth symbol):
3017 * - DC-balance: used to ensure a better clock recovery from the data
3018 * link (SDVO)
3019 * - DisplayPort scrambling: used for EMI reduction
3020 */
3021 if (need_stable_symbols) {
3022 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3023
8d2f24ca
DV		 3024 tmp |= DC_BALANCE_RESET_VLV;
3025 if (pipe == PIPE_A)
3026 tmp |= PIPE_A_SCRAMBLE_RESET;
3027 else
3028 tmp |= PIPE_B_SCRAMBLE_RESET;
3029
3030 I915_WRITE(PORT_DFT2_G4X, tmp);
3031 }
3032
7ac0129b
DV		 3033 return 0;
3034}
3035
4b79ebf7 3036static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3037 enum pipe pipe,
3038 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3039 uint32_t *val)
3040{
84093603
DV		 3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 bool need_stable_symbols = false;
3043
46a19188
DV		 3044 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3045 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3046 if (ret)
3047 return ret;
3048 }
3049
3050 switch (*source) {
4b79ebf7
DV		 3051 case INTEL_PIPE_CRC_SOURCE_PIPE:
3052 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3053 break;
3054 case INTEL_PIPE_CRC_SOURCE_TV:
3055 if (!SUPPORTS_TV(dev))
3056 return -EINVAL;
3057 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3058 break;
3059 case INTEL_PIPE_CRC_SOURCE_DP_B:
3060 if (!IS_G4X(dev))
3061 return -EINVAL;
3062 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3063 need_stable_symbols = true;
4b79ebf7
DV		 3064 break;
3065 case INTEL_PIPE_CRC_SOURCE_DP_C:
3066 if (!IS_G4X(dev))
3067 return -EINVAL;
3068 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3069 need_stable_symbols = true;
4b79ebf7
DV		 3070 break;
3071 case INTEL_PIPE_CRC_SOURCE_DP_D:
3072 if (!IS_G4X(dev))
3073 return -EINVAL;
3074 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3075 need_stable_symbols = true;
4b79ebf7
DV		 3076 break;
3077 case INTEL_PIPE_CRC_SOURCE_NONE:
3078 *val = 0;
3079 break;
3080 default:
3081 return -EINVAL;
3082 }
3083
84093603
DV		 3084 /*
3085 * When the pipe CRC tap point is after the transcoders we need
3086 * to tweak symbol-level features to produce a deterministic series of
3087 * symbols for a given frame. We need to reset those features only once
3088 * a frame (instead of every nth symbol):
3089 * - DC-balance: used to ensure a better clock recovery from the data
3090 * link (SDVO)
3091 * - DisplayPort scrambling: used for EMI reduction
3092 */
3093 if (need_stable_symbols) {
3094 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3095
3096 WARN_ON(!IS_G4X(dev));
3097
3098 I915_WRITE(PORT_DFT_I9XX,
3099 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3100
3101 if (pipe == PIPE_A)
3102 tmp |= PIPE_A_SCRAMBLE_RESET;
3103 else
3104 tmp |= PIPE_B_SCRAMBLE_RESET;
3105
3106 I915_WRITE(PORT_DFT2_G4X, tmp);
3107 }
3108
4b79ebf7
DV		 3109 return 0;
3110}
3111
8d2f24ca
DV		 3112static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3113 enum pipe pipe)
3114{
3115 struct drm_i915_private *dev_priv = dev->dev_private;
3116 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3117
3118 if (pipe == PIPE_A)
3119 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3120 else
3121 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3122 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3123 tmp &= ~DC_BALANCE_RESET_VLV;
3124 I915_WRITE(PORT_DFT2_G4X, tmp);
3125
3126}
3127
84093603
DV		 3128static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3129 enum pipe pipe)
3130{
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3133
3134 if (pipe == PIPE_A)
3135 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3136 else
3137 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3138 I915_WRITE(PORT_DFT2_G4X, tmp);
3139
3140 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3141 I915_WRITE(PORT_DFT_I9XX,
3142 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3143 }
3144}
3145
46a19188 3146static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3147 uint32_t *val)
3148{
46a19188
DV		 3149 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3150 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3151
3152 switch (*source) {
5b3a856b
DV		 3153 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3154 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3155 break;
3156 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3157 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3158 break;
5b3a856b
DV		 3159 case INTEL_PIPE_CRC_SOURCE_PIPE:
3160 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3161 break;
3d099a05 3162 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3163 *val = 0;
3164 break;
3d099a05
DV		 3165 default:
3166 return -EINVAL;
5b3a856b
DV		 3167 }
3168
3169 return 0;
3170}
3171
fabf6e51
DV		 3172static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3173{
3174 struct drm_i915_private *dev_priv = dev->dev_private;
3175 struct intel_crtc *crtc =
3176 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3177
3178 drm_modeset_lock_all(dev);
3179 /*
3180 * If we use the eDP transcoder we need to make sure that we don't
3181 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3182 * relevant on hsw with pipe A when using the always-on power well
3183 * routing.
3184 */
3185 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
3186 !crtc->config.pch_pfit.enabled) {
3187 crtc->config.pch_pfit.force_thru = true;
3188
3189 intel_display_power_get(dev_priv,
3190 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3191
3192 dev_priv->display.crtc_disable(&crtc->base);
3193 dev_priv->display.crtc_enable(&crtc->base);
3194 }
3195 drm_modeset_unlock_all(dev);
3196}
3197
3198static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3199{
3200 struct drm_i915_private *dev_priv = dev->dev_private;
3201 struct intel_crtc *crtc =
3202 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3203
3204 drm_modeset_lock_all(dev);
3205 /*
3206 * If we use the eDP transcoder we need to make sure that we don't
3207 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3208 * relevant on hsw with pipe A when using the always-on power well
3209 * routing.
3210 */
3211 if (crtc->config.pch_pfit.force_thru) {
3212 crtc->config.pch_pfit.force_thru = false;
3213
3214 dev_priv->display.crtc_disable(&crtc->base);
3215 dev_priv->display.crtc_enable(&crtc->base);
3216
3217 intel_display_power_put(dev_priv,
3218 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3219 }
3220 drm_modeset_unlock_all(dev);
3221}
3222
3223static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3224 enum pipe pipe,
3225 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3226 uint32_t *val)
3227{
46a19188
DV		 3228 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3229 *source = INTEL_PIPE_CRC_SOURCE_PF;
3230
3231 switch (*source) {
5b3a856b
DV		 3232 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3233 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3234 break;
3235 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3236 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3237 break;
3238 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3239 if (IS_HASWELL(dev) && pipe == PIPE_A)
3240 hsw_trans_edp_pipe_A_crc_wa(dev);
3241
5b3a856b
DV		 3242 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3243 break;
3d099a05 3244 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3245 *val = 0;
3246 break;
3d099a05
DV		 3247 default:
3248 return -EINVAL;
5b3a856b
DV		 3249 }
3250
3251 return 0;
3252}
3253
926321d5
DV		 3254static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3255 enum intel_pipe_crc_source source)
3256{
3257 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3258 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 3259 u32 val = 0; /* shut up gcc */
5b3a856b 3260 int ret;
926321d5 3261
cc3da175
DL		 3262 if (pipe_crc->source == source)
3263 return 0;
3264
ae676fcd
DL		 3265 /* forbid changing the source without going back to 'none' */
3266 if (pipe_crc->source && source)
3267 return -EINVAL;
3268
52f843f6 3269 if (IS_GEN2(dev))
46a19188 3270 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3271 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3272 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3273 else if (IS_VALLEYVIEW(dev))
fabf6e51 3274 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3275 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3276 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3277 else
fabf6e51 3278 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3279
3280 if (ret != 0)
3281 return ret;
3282
4b584369
DL		 3283 /* none -> real source transition */
3284 if (source) {
7cd6ccff
DL		 3285 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3286 pipe_name(pipe), pipe_crc_source_name(source));
3287
e5f75aca
DL		 3288 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
3289 INTEL_PIPE_CRC_ENTRIES_NR,
3290 GFP_KERNEL);
3291 if (!pipe_crc->entries)
3292 return -ENOMEM;
3293
d538bbdf
DL		 3294 spin_lock_irq(&pipe_crc->lock);
3295 pipe_crc->head = 0;
3296 pipe_crc->tail = 0;
3297 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3298 }
3299
cc3da175 3300 pipe_crc->source = source;
926321d5 3301
926321d5
DV		 3302 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3303 POSTING_READ(PIPE_CRC_CTL(pipe));
3304
e5f75aca
DL		 3305 /* real source -> none transition */
3306 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3307 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3308 struct intel_crtc *crtc =
3309 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3310
7cd6ccff
DL		 3311 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3312 pipe_name(pipe));
3313
a33d7105
DV		 3314 drm_modeset_lock(&crtc->base.mutex, NULL);
3315 if (crtc->active)
3316 intel_wait_for_vblank(dev, pipe);
3317 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3318
d538bbdf
DL		 3319 spin_lock_irq(&pipe_crc->lock);
3320 entries = pipe_crc->entries;
e5f75aca 3321 pipe_crc->entries = NULL;
d538bbdf
DL		 3322 spin_unlock_irq(&pipe_crc->lock);
3323
3324 kfree(entries);
84093603
DV		 3325
3326 if (IS_G4X(dev))
3327 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3328 else if (IS_VALLEYVIEW(dev))
3329 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3330 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3331 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
e5f75aca
DL		 3332 }
3333
926321d5
DV		 3334 return 0;
3335}
3336
3337/*
3338 * Parse pipe CRC command strings:
b94dec87
DL		 3339 * command: wsp* object wsp+ name wsp+ source wsp*
3340 * object: 'pipe'
3341 * name: (A | B | C)
926321d5
DV		 3342 * source: (none | plane1 | plane2 | pf)
3343 * wsp: (#0x20 | #0x9 | #0xA)+
3344 *
3345 * eg.:
b94dec87
DL		 3346 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3347 * "pipe A none" -> Stop CRC
926321d5 3348 */
bd9db02f 3349static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3350{
3351 int n_words = 0;
3352
3353 while (*buf) {
3354 char *end;
3355
3356 /* skip leading white space */
3357 buf = skip_spaces(buf);
3358 if (!*buf)
3359 break; /* end of buffer */
3360
3361 /* find end of word */
3362 for (end = buf; *end && !isspace(*end); end++)
3363 ;
3364
3365 if (n_words == max_words) {
3366 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3367 max_words);
3368 return -EINVAL; /* ran out of words[] before bytes */
3369 }
3370
3371 if (*end)
3372 *end++ = '\0';
3373 words[n_words++] = buf;
3374 buf = end;
3375 }
3376
3377 return n_words;
3378}
3379
b94dec87
DL		 3380enum intel_pipe_crc_object {
3381 PIPE_CRC_OBJECT_PIPE,
3382};
3383
e8dfcf78 3384static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3385 "pipe",
3386};
3387
3388static int
bd9db02f 3389display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3390{
3391 int i;
3392
3393 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3394 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3395 *o = i;
b94dec87
DL		 3396 return 0;
3397 }
3398
3399 return -EINVAL;
3400}
3401
bd9db02f 3402static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3403{
3404 const char name = buf[0];
3405
3406 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3407 return -EINVAL;
3408
3409 *pipe = name - 'A';
3410
3411 return 0;
3412}
3413
3414static int
bd9db02f 3415display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3416{
3417 int i;
3418
3419 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3420 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3421 *s = i;
926321d5
DV		 3422 return 0;
3423 }
3424
3425 return -EINVAL;
3426}
3427
bd9db02f 3428static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3429{
b94dec87 3430#define N_WORDS 3
926321d5 3431 int n_words;
b94dec87 3432 char *words[N_WORDS];
926321d5 3433 enum pipe pipe;
b94dec87 3434 enum intel_pipe_crc_object object;
926321d5
DV		 3435 enum intel_pipe_crc_source source;
3436
bd9db02f 3437 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3438 if (n_words != N_WORDS) {
3439 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3440 N_WORDS);
3441 return -EINVAL;
3442 }
3443
bd9db02f 3444 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3445 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3446 return -EINVAL;
3447 }
3448
bd9db02f 3449 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3450 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3451 return -EINVAL;
3452 }
3453
bd9db02f 3454 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3455 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3456 return -EINVAL;
3457 }
3458
3459 return pipe_crc_set_source(dev, pipe, source);
3460}
3461
bd9db02f
DL		 3462static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3463 size_t len, loff_t *offp)
926321d5
DV		 3464{
3465 struct seq_file *m = file->private_data;
3466 struct drm_device *dev = m->private;
3467 char *tmpbuf;
3468 int ret;
3469
3470 if (len == 0)
3471 return 0;
3472
3473 if (len > PAGE_SIZE - 1) {
3474 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3475 PAGE_SIZE);
3476 return -E2BIG;
3477 }
3478
3479 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3480 if (!tmpbuf)
3481 return -ENOMEM;
3482
3483 if (copy_from_user(tmpbuf, ubuf, len)) {
3484 ret = -EFAULT;
3485 goto out;
3486 }
3487 tmpbuf[len] = '\0';
3488
bd9db02f 3489 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3490
3491out:
3492 kfree(tmpbuf);
3493 if (ret < 0)
3494 return ret;
3495
3496 *offp += len;
3497 return len;
3498}
3499
bd9db02f 3500static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3501 .owner = THIS_MODULE,
bd9db02f 3502 .open = display_crc_ctl_open,
926321d5
DV		 3503 .read = seq_read,
3504 .llseek = seq_lseek,
3505 .release = single_release,
bd9db02f 3506 .write = display_crc_ctl_write
926321d5
DV		 3507};
3508
369a1342
VS		 3509static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3510{
3511 struct drm_device *dev = m->private;
546c81fd 3512 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3513 int level;
3514
3515 drm_modeset_lock_all(dev);
3516
3517 for (level = 0; level < num_levels; level++) {
3518 unsigned int latency = wm[level];
3519
3520 /* WM1+ latency values in 0.5us units */
3521 if (level > 0)
3522 latency *= 5;
3523
3524 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3525 level, wm[level],
3526 latency / 10, latency % 10);
3527 }
3528
3529 drm_modeset_unlock_all(dev);
3530}
3531
3532static int pri_wm_latency_show(struct seq_file *m, void *data)
3533{
3534 struct drm_device *dev = m->private;
3535
3536 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3537
3538 return 0;
3539}
3540
3541static int spr_wm_latency_show(struct seq_file *m, void *data)
3542{
3543 struct drm_device *dev = m->private;
3544
3545 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3546
3547 return 0;
3548}
3549
3550static int cur_wm_latency_show(struct seq_file *m, void *data)
3551{
3552 struct drm_device *dev = m->private;
3553
3554 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3555
3556 return 0;
3557}
3558
3559static int pri_wm_latency_open(struct inode *inode, struct file *file)
3560{
3561 struct drm_device *dev = inode->i_private;
3562
9ad0257c 3563 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3564 return -ENODEV;
3565
3566 return single_open(file, pri_wm_latency_show, dev);
3567}
3568
3569static int spr_wm_latency_open(struct inode *inode, struct file *file)
3570{
3571 struct drm_device *dev = inode->i_private;
3572
9ad0257c 3573 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3574 return -ENODEV;
3575
3576 return single_open(file, spr_wm_latency_show, dev);
3577}
3578
3579static int cur_wm_latency_open(struct inode *inode, struct file *file)
3580{
3581 struct drm_device *dev = inode->i_private;
3582
9ad0257c 3583 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3584 return -ENODEV;
3585
3586 return single_open(file, cur_wm_latency_show, dev);
3587}
3588
3589static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3590 size_t len, loff_t *offp, uint16_t wm[5])
3591{
3592 struct seq_file *m = file->private_data;
3593 struct drm_device *dev = m->private;
3594 uint16_t new[5] = { 0 };
546c81fd 3595 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3596 int level;
3597 int ret;
3598 char tmp[32];
3599
3600 if (len >= sizeof(tmp))
3601 return -EINVAL;
3602
3603 if (copy_from_user(tmp, ubuf, len))
3604 return -EFAULT;
3605
3606 tmp[len] = '\0';
3607
3608 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3609 if (ret != num_levels)
3610 return -EINVAL;
3611
3612 drm_modeset_lock_all(dev);
3613
3614 for (level = 0; level < num_levels; level++)
3615 wm[level] = new[level];
3616
3617 drm_modeset_unlock_all(dev);
3618
3619 return len;
3620}
3621
3622
3623static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3624 size_t len, loff_t *offp)
3625{
3626 struct seq_file *m = file->private_data;
3627 struct drm_device *dev = m->private;
3628
3629 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3630}
3631
3632static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3633 size_t len, loff_t *offp)
3634{
3635 struct seq_file *m = file->private_data;
3636 struct drm_device *dev = m->private;
3637
3638 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3639}
3640
3641static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3642 size_t len, loff_t *offp)
3643{
3644 struct seq_file *m = file->private_data;
3645 struct drm_device *dev = m->private;
3646
3647 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3648}
3649
3650static const struct file_operations i915_pri_wm_latency_fops = {
3651 .owner = THIS_MODULE,
3652 .open = pri_wm_latency_open,
3653 .read = seq_read,
3654 .llseek = seq_lseek,
3655 .release = single_release,
3656 .write = pri_wm_latency_write
3657};
3658
3659static const struct file_operations i915_spr_wm_latency_fops = {
3660 .owner = THIS_MODULE,
3661 .open = spr_wm_latency_open,
3662 .read = seq_read,
3663 .llseek = seq_lseek,
3664 .release = single_release,
3665 .write = spr_wm_latency_write
3666};
3667
3668static const struct file_operations i915_cur_wm_latency_fops = {
3669 .owner = THIS_MODULE,
3670 .open = cur_wm_latency_open,
3671 .read = seq_read,
3672 .llseek = seq_lseek,
3673 .release = single_release,
3674 .write = cur_wm_latency_write
3675};
3676
647416f9
KC		 3677static int
3678i915_wedged_get(void *data, u64 *val)
f3cd474b 3679{
647416f9 3680 struct drm_device *dev = data;
e277a1f8 3681 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3682
647416f9 3683 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3684
647416f9 3685 return 0;
f3cd474b
CW		 3686}
3687
647416f9
KC		 3688static int
3689i915_wedged_set(void *data, u64 val)
f3cd474b 3690{
647416f9 3691 struct drm_device *dev = data;
d46c0517
ID		 3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693
3694 intel_runtime_pm_get(dev_priv);
f3cd474b 3695
58174462
MK		 3696 i915_handle_error(dev, val,
3697 "Manually setting wedged to %llu", val);
d46c0517
ID		 3698
3699 intel_runtime_pm_put(dev_priv);
3700
647416f9 3701 return 0;
f3cd474b
CW		 3702}
3703
647416f9
KC		 3704DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3705 i915_wedged_get, i915_wedged_set,
3a3b4f98 3706 "%llu\n");
f3cd474b 3707
647416f9
KC		 3708static int
3709i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3710{
647416f9 3711 struct drm_device *dev = data;
e277a1f8 3712 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3713
647416f9 3714 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3715
647416f9 3716 return 0;
e5eb3d63
DV		 3717}
3718
647416f9
KC		 3719static int
3720i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3721{
647416f9 3722 struct drm_device *dev = data;
e5eb3d63 3723 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3724 int ret;
e5eb3d63 3725
647416f9 3726 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3727
22bcfc6a
DV		 3728 ret = mutex_lock_interruptible(&dev->struct_mutex);
3729 if (ret)
3730 return ret;
3731
99584db3 3732 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3733 mutex_unlock(&dev->struct_mutex);
3734
647416f9 3735 return 0;
e5eb3d63
DV		 3736}
3737
647416f9
KC		 3738DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3739 i915_ring_stop_get, i915_ring_stop_set,
3740 "0x%08llx\n");
d5442303 3741
094f9a54
CW		 3742static int
3743i915_ring_missed_irq_get(void *data, u64 *val)
3744{
3745 struct drm_device *dev = data;
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747
3748 *val = dev_priv->gpu_error.missed_irq_rings;
3749 return 0;
3750}
3751
3752static int
3753i915_ring_missed_irq_set(void *data, u64 val)
3754{
3755 struct drm_device *dev = data;
3756 struct drm_i915_private *dev_priv = dev->dev_private;
3757 int ret;
3758
3759 /* Lock against concurrent debugfs callers */
3760 ret = mutex_lock_interruptible(&dev->struct_mutex);
3761 if (ret)
3762 return ret;
3763 dev_priv->gpu_error.missed_irq_rings = val;
3764 mutex_unlock(&dev->struct_mutex);
3765
3766 return 0;
3767}
3768
3769DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3770 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3771 "0x%08llx\n");
3772
3773static int
3774i915_ring_test_irq_get(void *data, u64 *val)
3775{
3776 struct drm_device *dev = data;
3777 struct drm_i915_private *dev_priv = dev->dev_private;
3778
3779 *val = dev_priv->gpu_error.test_irq_rings;
3780
3781 return 0;
3782}
3783
3784static int
3785i915_ring_test_irq_set(void *data, u64 val)
3786{
3787 struct drm_device *dev = data;
3788 struct drm_i915_private *dev_priv = dev->dev_private;
3789 int ret;
3790
3791 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3792
3793 /* Lock against concurrent debugfs callers */
3794 ret = mutex_lock_interruptible(&dev->struct_mutex);
3795 if (ret)
3796 return ret;
3797
3798 dev_priv->gpu_error.test_irq_rings = val;
3799 mutex_unlock(&dev->struct_mutex);
3800
3801 return 0;
3802}
3803
3804DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3805 i915_ring_test_irq_get, i915_ring_test_irq_set,
3806 "0x%08llx\n");
3807
dd624afd
CW		 3808#define DROP_UNBOUND 0x1
3809#define DROP_BOUND 0x2
3810#define DROP_RETIRE 0x4
3811#define DROP_ACTIVE 0x8
3812#define DROP_ALL (DROP_UNBOUND | \
3813 DROP_BOUND | \
3814 DROP_RETIRE | \
3815 DROP_ACTIVE)
647416f9
KC		 3816static int
3817i915_drop_caches_get(void *data, u64 *val)
dd624afd 3818{
647416f9 3819 *val = DROP_ALL;
dd624afd 3820
647416f9 3821 return 0;
dd624afd
CW		 3822}
3823
647416f9
KC		 3824static int
3825i915_drop_caches_set(void *data, u64 val)
dd624afd 3826{
647416f9 3827 struct drm_device *dev = data;
dd624afd
CW		 3828 struct drm_i915_private *dev_priv = dev->dev_private;
3829 struct drm_i915_gem_object *obj, *next;
647416f9 3830 int ret;
dd624afd 3831
2f9fe5ff 3832 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 3833
3834 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3835 * on ioctls on -EAGAIN. */
3836 ret = mutex_lock_interruptible(&dev->struct_mutex);
3837 if (ret)
3838 return ret;
3839
3840 if (val & DROP_ACTIVE) {
3841 ret = i915_gpu_idle(dev);
3842 if (ret)
3843 goto unlock;
3844 }
3845
3846 if (val & (DROP_RETIRE | DROP_ACTIVE))
3847 i915_gem_retire_requests(dev);
3848
3849 if (val & DROP_BOUND) {
4ad72b7f
CW		 3850 list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list,
3851 global_list) {
3852 struct i915_vma *vma, *v;
3853
3854 ret = 0;
3855 drm_gem_object_reference(&obj->base);
3856 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) {
d7f46fc4 3857 if (vma->pin_count)
ca191b13
BW		 3858 continue;
3859
3860 ret = i915_vma_unbind(vma);
3861 if (ret)
4ad72b7f 3862 break;
ca191b13 3863 }
4ad72b7f
CW		 3864 drm_gem_object_unreference(&obj->base);
3865 if (ret)
3866 goto unlock;
31a46c9c 3867 }
dd624afd
CW		 3868 }
3869
3870 if (val & DROP_UNBOUND) {
35c20a60
BW		 3871 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3872 global_list)
dd624afd
CW		 3873 if (obj->pages_pin_count == 0) {
3874 ret = i915_gem_object_put_pages(obj);
3875 if (ret)
3876 goto unlock;
3877 }
3878 }
3879
3880unlock:
3881 mutex_unlock(&dev->struct_mutex);
3882
647416f9 3883 return ret;
dd624afd
CW		 3884}
3885
647416f9
KC		 3886DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3887 i915_drop_caches_get, i915_drop_caches_set,
3888 "0x%08llx\n");
dd624afd 3889
647416f9
KC		 3890static int
3891i915_max_freq_get(void *data, u64 *val)
358733e9 3892{
647416f9 3893 struct drm_device *dev = data;
e277a1f8 3894 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3895 int ret;
004777cb 3896
daa3afb2 3897 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 3898 return -ENODEV;
3899
5c9669ce
TR		 3900 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3901
4fc688ce 3902 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3903 if (ret)
3904 return ret;
358733e9 3905
0a073b84 3906 if (IS_VALLEYVIEW(dev))
b39fb297 3907 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 3908 else
b39fb297 3909 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3910 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3911
647416f9 3912 return 0;
358733e9
JB		 3913}
3914
647416f9
KC		 3915static int
3916i915_max_freq_set(void *data, u64 val)
358733e9 3917{
647416f9 3918 struct drm_device *dev = data;
358733e9 3919 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3920 u32 rp_state_cap, hw_max, hw_min;
647416f9 3921 int ret;
004777cb 3922
daa3afb2 3923 if (INTEL_INFO(dev)->gen < 6)
004777cb 3924 return -ENODEV;
358733e9 3925
5c9669ce
TR		 3926 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3927
647416f9 3928 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 3929
4fc688ce 3930 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3931 if (ret)
3932 return ret;
3933
358733e9
JB		 3934 /*
3935 * Turbo will still be enabled, but won't go above the set value.
3936 */
0a073b84 3937 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3938 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 3939
03af2045
VS		 3940 hw_max = dev_priv->rps.max_freq;
3941 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 3942 } else {
3943 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3944
3945 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3946 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3947 hw_min = (rp_state_cap >> 16) & 0xff;
3948 }
3949
b39fb297 3950 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 3951 mutex_unlock(&dev_priv->rps.hw_lock);
3952 return -EINVAL;
0a073b84
JB		 3953 }
3954
b39fb297 3955 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 3956
3957 if (IS_VALLEYVIEW(dev))
3958 valleyview_set_rps(dev, val);
3959 else
3960 gen6_set_rps(dev, val);
3961
4fc688ce 3962 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3963
647416f9 3964 return 0;
358733e9
JB		 3965}
3966
647416f9
KC		 3967DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3968 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 3969 "%llu\n");
358733e9 3970
647416f9
KC		 3971static int
3972i915_min_freq_get(void *data, u64 *val)
1523c310 3973{
647416f9 3974 struct drm_device *dev = data;
e277a1f8 3975 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3976 int ret;
004777cb 3977
daa3afb2 3978 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 3979 return -ENODEV;
3980
5c9669ce
TR		 3981 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3982
4fc688ce 3983 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3984 if (ret)
3985 return ret;
1523c310 3986
0a073b84 3987 if (IS_VALLEYVIEW(dev))
b39fb297 3988 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 3989 else
b39fb297 3990 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3991 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3992
647416f9 3993 return 0;
1523c310
JB		 3994}
3995
647416f9
KC		 3996static int
3997i915_min_freq_set(void *data, u64 val)
1523c310 3998{
647416f9 3999 struct drm_device *dev = data;
1523c310 4000 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4001 u32 rp_state_cap, hw_max, hw_min;
647416f9 4002 int ret;
004777cb 4003
daa3afb2 4004 if (INTEL_INFO(dev)->gen < 6)
004777cb 4005 return -ENODEV;
1523c310 4006
5c9669ce
TR		 4007 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4008
647416f9 4009 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4010
4fc688ce 4011 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4012 if (ret)
4013 return ret;
4014
1523c310
JB		 4015 /*
4016 * Turbo will still be enabled, but won't go below the set value.
4017 */
0a073b84 4018 if (IS_VALLEYVIEW(dev)) {
2ec3815f 4019 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 4020
03af2045
VS		 4021 hw_max = dev_priv->rps.max_freq;
4022 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 4023 } else {
4024 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 4025
4026 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4027 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4028 hw_min = (rp_state_cap >> 16) & 0xff;
4029 }
4030
b39fb297 4031 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4032 mutex_unlock(&dev_priv->rps.hw_lock);
4033 return -EINVAL;
0a073b84 4034 }
dd0a1aa1 4035
b39fb297 4036 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 4037
4038 if (IS_VALLEYVIEW(dev))
4039 valleyview_set_rps(dev, val);
4040 else
4041 gen6_set_rps(dev, val);
4042
4fc688ce 4043 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4044
647416f9 4045 return 0;
1523c310
JB		 4046}
4047
647416f9
KC		 4048DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4049 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4050 "%llu\n");
1523c310 4051
647416f9
KC		 4052static int
4053i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4054{
647416f9 4055 struct drm_device *dev = data;
e277a1f8 4056 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4057 u32 snpcr;
647416f9 4058 int ret;
07b7ddd9 4059
004777cb
DV		 4060 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4061 return -ENODEV;
4062
22bcfc6a
DV		 4063 ret = mutex_lock_interruptible(&dev->struct_mutex);
4064 if (ret)
4065 return ret;
c8c8fb33 4066 intel_runtime_pm_get(dev_priv);
22bcfc6a 4067
07b7ddd9 4068 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4069
4070 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4071 mutex_unlock(&dev_priv->dev->struct_mutex);
4072
647416f9 4073 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4074
647416f9 4075 return 0;
07b7ddd9
JB		 4076}
4077
647416f9
KC		 4078static int
4079i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4080{
647416f9 4081 struct drm_device *dev = data;
07b7ddd9 4082 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4083 u32 snpcr;
07b7ddd9 4084
004777cb
DV		 4085 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4086 return -ENODEV;
4087
647416f9 4088 if (val > 3)
07b7ddd9
JB		 4089 return -EINVAL;
4090
c8c8fb33 4091 intel_runtime_pm_get(dev_priv);
647416f9 4092 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4093
4094 /* Update the cache sharing policy here as well */
4095 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4096 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4097 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4098 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4099
c8c8fb33 4100 intel_runtime_pm_put(dev_priv);
647416f9 4101 return 0;
07b7ddd9
JB		 4102}
4103
647416f9
KC		 4104DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4105 i915_cache_sharing_get, i915_cache_sharing_set,
4106 "%llu\n");
07b7ddd9 4107
6d794d42
BW		 4108static int i915_forcewake_open(struct inode *inode, struct file *file)
4109{
4110 struct drm_device *dev = inode->i_private;
4111 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4112
075edca4 4113 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4114 return 0;
4115
c8d9a590 4116 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4117
4118 return 0;
4119}
4120
c43b5634 4121static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4122{
4123 struct drm_device *dev = inode->i_private;
4124 struct drm_i915_private *dev_priv = dev->dev_private;
4125
075edca4 4126 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4127 return 0;
4128
c8d9a590 4129 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4130
4131 return 0;
4132}
4133
4134static const struct file_operations i915_forcewake_fops = {
4135 .owner = THIS_MODULE,
4136 .open = i915_forcewake_open,
4137 .release = i915_forcewake_release,
4138};
4139
4140static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4141{
4142 struct drm_device *dev = minor->dev;
4143 struct dentry *ent;
4144
4145 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4146 S_IRUSR,
6d794d42
BW		 4147 root, dev,
4148 &i915_forcewake_fops);
f3c5fe97
WY		 4149 if (!ent)
4150 return -ENOMEM;
6d794d42 4151
8eb57294 4152 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4153}
4154
6a9c308d
DV		 4155static int i915_debugfs_create(struct dentry *root,
4156 struct drm_minor *minor,
4157 const char *name,
4158 const struct file_operations *fops)
07b7ddd9
JB		 4159{
4160 struct drm_device *dev = minor->dev;
4161 struct dentry *ent;
4162
6a9c308d 4163 ent = debugfs_create_file(name,
07b7ddd9
JB		 4164 S_IRUGO | S_IWUSR,
4165 root, dev,
6a9c308d 4166 fops);
f3c5fe97
WY		 4167 if (!ent)
4168 return -ENOMEM;
07b7ddd9 4169
6a9c308d 4170 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4171}
4172
06c5bf8c 4173static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4174 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4175 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4176 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4177 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4178 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4179 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4180 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4181 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4182 {"i915_gem_request", i915_gem_request_info, 0},
4183 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4184 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4185 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4186 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4187 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4188 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4189 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
adb4bd12 4190 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1 4191 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4192 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4193 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4194 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4195 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4196 {"i915_sr_status", i915_sr_status, 0},
44834a67 4197 {"i915_opregion", i915_opregion, 0},
37811fcc 4198 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4199 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4200 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4201 {"i915_execlists", i915_execlists, 0},
6d794d42 4202 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 4203 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4204 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4205 {"i915_llc", i915_llc, 0},
e91fd8c6 4206 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4207 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4208 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4209 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4210 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4211 {"i915_display_info", i915_display_info, 0},
e04934cf 4212 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4213 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4214 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4215 {"i915_wa_registers", i915_wa_registers, 0},
2017263e 4216};
27c202ad 4217#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4218
06c5bf8c 4219static const struct i915_debugfs_files {
34b9674c
DV		 4220 const char *name;
4221 const struct file_operations *fops;
4222} i915_debugfs_files[] = {
4223 {"i915_wedged", &i915_wedged_fops},
4224 {"i915_max_freq", &i915_max_freq_fops},
4225 {"i915_min_freq", &i915_min_freq_fops},
4226 {"i915_cache_sharing", &i915_cache_sharing_fops},
4227 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4228 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4229 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4230 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4231 {"i915_error_state", &i915_error_state_fops},
4232 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4233 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4234 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4235 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4236 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4237 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4238};
4239
07144428
DL		 4240void intel_display_crc_init(struct drm_device *dev)
4241{
4242 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4243 enum pipe pipe;
07144428 4244
055e393f 4245 for_each_pipe(dev_priv, pipe) {
b378360e 4246 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4247
d538bbdf
DL		 4248 pipe_crc->opened = false;
4249 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4250 init_waitqueue_head(&pipe_crc->wq);
4251 }
4252}
4253
27c202ad 4254int i915_debugfs_init(struct drm_minor *minor)
2017263e 4255{
34b9674c 4256 int ret, i;
f3cd474b 4257
6d794d42 4258 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4259 if (ret)
4260 return ret;
6a9c308d 4261
07144428
DL		 4262 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4263 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4264 if (ret)
4265 return ret;
4266 }
4267
34b9674c
DV		 4268 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4269 ret = i915_debugfs_create(minor->debugfs_root, minor,
4270 i915_debugfs_files[i].name,
4271 i915_debugfs_files[i].fops);
4272 if (ret)
4273 return ret;
4274 }
40633219 4275
27c202ad
BG		 4276 return drm_debugfs_create_files(i915_debugfs_list,
4277 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4278 minor->debugfs_root, minor);
4279}
4280
27c202ad 4281void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4282{
34b9674c
DV		 4283 int i;
4284
27c202ad
BG		 4285 drm_debugfs_remove_files(i915_debugfs_list,
4286 I915_DEBUGFS_ENTRIES, minor);
07144428 4287
6d794d42
BW		 4288 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4289 1, minor);
07144428 4290
e309a997 4291 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4292 struct drm_info_list *info_list =
4293 (struct drm_info_list *)&i915_pipe_crc_data[i];
4294
4295 drm_debugfs_remove_files(info_list, 1, minor);
4296 }
4297
34b9674c
DV		 4298 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4299 struct drm_info_list *info_list =
4300 (struct drm_info_list *) i915_debugfs_files[i].fops;
4301
4302 drm_debugfs_remove_files(info_list, 1, minor);
4303 }
2017263e 4304}
Linux kernel - Deliverables
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