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drm/i915: Free batch pool when idle
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
4feb7659 99 if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
20e28fba 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
37811fcc
CW		 127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
1d693bcc 130 get_global_flag(obj),
a05a5862 131 obj->base.size / 1024,
37811fcc
CW		 132 obj->base.read_domains,
133 obj->base.write_domain,
97b2a6a1
JH		 134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 142 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 143 if (vma->pin_count > 0)
144 pin_count++;
ba0635ff
DC		 145 }
146 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 147 if (obj->pin_display)
148 seq_printf(m, " (display)");
37811fcc
CW		 149 if (obj->fence_reg != I915_FENCE_REG_NONE)
150 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 151 list_for_each_entry(vma, &obj->vma_list, vma_link) {
152 if (!i915_is_ggtt(vma->vm))
153 seq_puts(m, " (pp");
154 else
155 seq_puts(m, " (g");
440fd528 156 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
fe14d5f4
TU		 157 vma->node.start, vma->node.size,
158 vma->ggtt_view.type);
1d693bcc 159 }
c1ad11fc 160 if (obj->stolen)
440fd528 161 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
41c52415
JH		 171 if (obj->last_read_req != NULL)
172 seq_printf(m, " (%s)",
173 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 174 if (obj->frontbuffer_bits)
175 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 176}
177
273497e5 178static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 179{
ea0c76f8 180 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 181 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
182 seq_putc(m, ' ');
183}
184
433e12f7 185static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 186{
9f25d007 187 struct drm_info_node *node = m->private;
433e12f7
BG		 188 uintptr_t list = (uintptr_t) node->info_ent->data;
189 struct list_head *head;
2017263e 190 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 193 struct i915_vma *vma;
8f2480fb
CW		 194 size_t total_obj_size, total_gtt_size;
195 int count, ret;
de227ef0
CW		 196
197 ret = mutex_lock_interruptible(&dev->struct_mutex);
198 if (ret)
199 return ret;
2017263e 200
ca191b13 201 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 202 switch (list) {
203 case ACTIVE_LIST:
267f0c90 204 seq_puts(m, "Active:\n");
5cef07e1 205 head = &vm->active_list;
433e12f7
BG		 206 break;
207 case INACTIVE_LIST:
267f0c90 208 seq_puts(m, "Inactive:\n");
5cef07e1 209 head = &vm->inactive_list;
433e12f7 210 break;
433e12f7 211 default:
de227ef0
CW		 212 mutex_unlock(&dev->struct_mutex);
213 return -EINVAL;
2017263e 214 }
2017263e 215
8f2480fb 216 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 217 list_for_each_entry(vma, head, mm_list) {
218 seq_printf(m, " ");
219 describe_obj(m, vma->obj);
220 seq_printf(m, "\n");
221 total_obj_size += vma->obj->base.size;
222 total_gtt_size += vma->node.size;
8f2480fb 223 count++;
2017263e 224 }
de227ef0 225 mutex_unlock(&dev->struct_mutex);
5e118f41 226
8f2480fb
CW		 227 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
228 count, total_obj_size, total_gtt_size);
2017263e
BG		 229 return 0;
230}
231
6d2b8885
CW		 232static int obj_rank_by_stolen(void *priv,
233 struct list_head *A, struct list_head *B)
234{
235 struct drm_i915_gem_object *a =
b25cb2f8 236 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 237 struct drm_i915_gem_object *b =
b25cb2f8 238 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 239
240 return a->stolen->start - b->stolen->start;
241}
242
243static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
244{
9f25d007 245 struct drm_info_node *node = m->private;
6d2b8885
CW		 246 struct drm_device *dev = node->minor->dev;
247 struct drm_i915_private *dev_priv = dev->dev_private;
248 struct drm_i915_gem_object *obj;
249 size_t total_obj_size, total_gtt_size;
250 LIST_HEAD(stolen);
251 int count, ret;
252
253 ret = mutex_lock_interruptible(&dev->struct_mutex);
254 if (ret)
255 return ret;
256
257 total_obj_size = total_gtt_size = count = 0;
258 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
259 if (obj->stolen == NULL)
260 continue;
261
b25cb2f8 262 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 263
264 total_obj_size += obj->base.size;
265 total_gtt_size += i915_gem_obj_ggtt_size(obj);
266 count++;
267 }
268 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
269 if (obj->stolen == NULL)
270 continue;
271
b25cb2f8 272 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 273
274 total_obj_size += obj->base.size;
275 count++;
276 }
277 list_sort(NULL, &stolen, obj_rank_by_stolen);
278 seq_puts(m, "Stolen:\n");
279 while (!list_empty(&stolen)) {
b25cb2f8 280 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 281 seq_puts(m, " ");
282 describe_obj(m, obj);
283 seq_putc(m, '\n');
b25cb2f8 284 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 285 }
286 mutex_unlock(&dev->struct_mutex);
287
288 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
289 count, total_obj_size, total_gtt_size);
290 return 0;
291}
292
6299f992
CW		 293#define count_objects(list, member) do { \
294 list_for_each_entry(obj, list, member) { \
f343c5f6 295 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 296 ++count; \
297 if (obj->map_and_fenceable) { \
f343c5f6 298 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 299 ++mappable_count; \
300 } \
301 } \
0206e353 302} while (0)
6299f992 303
2db8e9d6 304struct file_stats {
6313c204 305 struct drm_i915_file_private *file_priv;
2db8e9d6 306 int count;
c67a17e9
CW		 307 size_t total, unbound;
308 size_t global, shared;
309 size_t active, inactive;
2db8e9d6
CW		 310};
311
312static int per_file_stats(int id, void *ptr, void *data)
313{
314 struct drm_i915_gem_object *obj = ptr;
315 struct file_stats *stats = data;
6313c204 316 struct i915_vma *vma;
2db8e9d6
CW		 317
318 stats->count++;
319 stats->total += obj->base.size;
320
c67a17e9
CW		 321 if (obj->base.name || obj->base.dma_buf)
322 stats->shared += obj->base.size;
323
6313c204
CW		 324 if (USES_FULL_PPGTT(obj->base.dev)) {
325 list_for_each_entry(vma, &obj->vma_list, vma_link) {
326 struct i915_hw_ppgtt *ppgtt;
327
328 if (!drm_mm_node_allocated(&vma->node))
329 continue;
330
331 if (i915_is_ggtt(vma->vm)) {
332 stats->global += obj->base.size;
333 continue;
334 }
335
336 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 337 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 338 continue;
339
41c52415 340 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 341 stats->active += obj->base.size;
342 else
343 stats->inactive += obj->base.size;
344
345 return 0;
346 }
2db8e9d6 347 } else {
6313c204
CW		 348 if (i915_gem_obj_ggtt_bound(obj)) {
349 stats->global += obj->base.size;
41c52415 350 if (obj->active)
6313c204
CW		 351 stats->active += obj->base.size;
352 else
353 stats->inactive += obj->base.size;
354 return 0;
355 }
2db8e9d6
CW		 356 }
357
6313c204
CW		 358 if (!list_empty(&obj->global_list))
359 stats->unbound += obj->base.size;
360
2db8e9d6
CW		 361 return 0;
362}
363
493018dc
BV		 364#define print_file_stats(m, name, stats) \
365 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
366 name, \
367 stats.count, \
368 stats.total, \
369 stats.active, \
370 stats.inactive, \
371 stats.global, \
372 stats.shared, \
373 stats.unbound)
374
375static void print_batch_pool_stats(struct seq_file *m,
376 struct drm_i915_private *dev_priv)
377{
378 struct drm_i915_gem_object *obj;
379 struct file_stats stats;
06fbca71
CW		 380 struct intel_engine_cs *ring;
381 int i;
493018dc
BV		 382
383 memset(&stats, 0, sizeof(stats));
384
06fbca71
CW		 385 for_each_ring(ring, dev_priv, i) {
386 list_for_each_entry(obj,
387 &ring->batch_pool.cache_list,
388 batch_pool_list)
389 per_file_stats(0, obj, &stats);
390 }
493018dc
BV		 391
392 print_file_stats(m, "batch pool", stats);
393}
394
ca191b13
BW		 395#define count_vmas(list, member) do { \
396 list_for_each_entry(vma, list, member) { \
397 size += i915_gem_obj_ggtt_size(vma->obj); \
398 ++count; \
399 if (vma->obj->map_and_fenceable) { \
400 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
401 ++mappable_count; \
402 } \
403 } \
404} while (0)
405
406static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 407{
9f25d007 408 struct drm_info_node *node = m->private;
73aa808f
CW		 409 struct drm_device *dev = node->minor->dev;
410 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 411 u32 count, mappable_count, purgeable_count;
412 size_t size, mappable_size, purgeable_size;
6299f992 413 struct drm_i915_gem_object *obj;
5cef07e1 414 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 415 struct drm_file *file;
ca191b13 416 struct i915_vma *vma;
73aa808f
CW		 417 int ret;
418
419 ret = mutex_lock_interruptible(&dev->struct_mutex);
420 if (ret)
421 return ret;
422
6299f992
CW		 423 seq_printf(m, "%u objects, %zu bytes\n",
424 dev_priv->mm.object_count,
425 dev_priv->mm.object_memory);
426
427 size = count = mappable_size = mappable_count = 0;
35c20a60 428 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 429 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
430 count, mappable_count, size, mappable_size);
431
432 size = count = mappable_size = mappable_count = 0;
ca191b13 433 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 434 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
435 count, mappable_count, size, mappable_size);
436
6299f992 437 size = count = mappable_size = mappable_count = 0;
ca191b13 438 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 439 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
440 count, mappable_count, size, mappable_size);
441
b7abb714 442 size = count = purgeable_size = purgeable_count = 0;
35c20a60 443 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 444 size += obj->base.size, ++count;
b7abb714
CW		 445 if (obj->madv == I915_MADV_DONTNEED)
446 purgeable_size += obj->base.size, ++purgeable_count;
447 }
6c085a72
CW		 448 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
449
6299f992 450 size = count = mappable_size = mappable_count = 0;
35c20a60 451 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 452 if (obj->fault_mappable) {
f343c5f6 453 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 454 ++count;
455 }
456 if (obj->pin_mappable) {
f343c5f6 457 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 458 ++mappable_count;
459 }
b7abb714
CW		 460 if (obj->madv == I915_MADV_DONTNEED) {
461 purgeable_size += obj->base.size;
462 ++purgeable_count;
463 }
6299f992 464 }
b7abb714
CW		 465 seq_printf(m, "%u purgeable objects, %zu bytes\n",
466 purgeable_count, purgeable_size);
6299f992
CW		 467 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
468 mappable_count, mappable_size);
469 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
470 count, size);
471
93d18799 472 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 473 dev_priv->gtt.base.total,
474 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 475
493018dc
BV		 476 seq_putc(m, '\n');
477 print_batch_pool_stats(m, dev_priv);
478
267f0c90 479 seq_putc(m, '\n');
2db8e9d6
CW		 480 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
481 struct file_stats stats;
3ec2f427 482 struct task_struct *task;
2db8e9d6
CW		 483
484 memset(&stats, 0, sizeof(stats));
6313c204 485 stats.file_priv = file->driver_priv;
5b5ffff0 486 spin_lock(&file->table_lock);
2db8e9d6 487 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 488 spin_unlock(&file->table_lock);
3ec2f427
TH		 489 /*
490 * Although we have a valid reference on file->pid, that does
491 * not guarantee that the task_struct who called get_pid() is
492 * still alive (e.g. get_pid(current) => fork() => exit()).
493 * Therefore, we need to protect this ->comm access using RCU.
494 */
495 rcu_read_lock();
496 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 497 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 498 rcu_read_unlock();
2db8e9d6
CW		 499 }
500
73aa808f
CW		 501 mutex_unlock(&dev->struct_mutex);
502
503 return 0;
504}
505
aee56cff 506static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 507{
9f25d007 508 struct drm_info_node *node = m->private;
08c18323 509 struct drm_device *dev = node->minor->dev;
1b50247a 510 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 511 struct drm_i915_private *dev_priv = dev->dev_private;
512 struct drm_i915_gem_object *obj;
513 size_t total_obj_size, total_gtt_size;
514 int count, ret;
515
516 ret = mutex_lock_interruptible(&dev->struct_mutex);
517 if (ret)
518 return ret;
519
520 total_obj_size = total_gtt_size = count = 0;
35c20a60 521 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 522 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 523 continue;
524
267f0c90 525 seq_puts(m, " ");
08c18323 526 describe_obj(m, obj);
267f0c90 527 seq_putc(m, '\n');
08c18323 528 total_obj_size += obj->base.size;
f343c5f6 529 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 530 count++;
531 }
532
533 mutex_unlock(&dev->struct_mutex);
534
535 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
536 count, total_obj_size, total_gtt_size);
537
538 return 0;
539}
540
4e5359cd
SF		 541static int i915_gem_pageflip_info(struct seq_file *m, void *data)
542{
9f25d007 543 struct drm_info_node *node = m->private;
4e5359cd 544 struct drm_device *dev = node->minor->dev;
d6bbafa1 545 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 546 struct intel_crtc *crtc;
8a270ebf
DV		 547 int ret;
548
549 ret = mutex_lock_interruptible(&dev->struct_mutex);
550 if (ret)
551 return ret;
4e5359cd 552
d3fcc808 553 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 554 const char pipe = pipe_name(crtc->pipe);
555 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 556 struct intel_unpin_work *work;
557
5e2d7afc 558 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 559 work = crtc->unpin_work;
560 if (work == NULL) {
9db4a9c7 561 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 562 pipe, plane);
563 } else {
d6bbafa1
CW		 564 u32 addr;
565
e7d841ca 566 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 567 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 568 pipe, plane);
569 } else {
9db4a9c7 570 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 571 pipe, plane);
572 }
3a8a946e
DV		 573 if (work->flip_queued_req) {
574 struct intel_engine_cs *ring =
575 i915_gem_request_get_ring(work->flip_queued_req);
576
20e28fba 577 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 578 ring->name,
f06cc1b9 579 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 580 dev_priv->next_seqno,
3a8a946e 581 ring->get_seqno(ring, true),
1b5a433a 582 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 583 } else
584 seq_printf(m, "Flip not associated with any ring\n");
585 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
586 work->flip_queued_vblank,
587 work->flip_ready_vblank,
1e3feefd 588 drm_crtc_vblank_count(&crtc->base));
4e5359cd 589 if (work->enable_stall_check)
267f0c90 590 seq_puts(m, "Stall check enabled, ");
4e5359cd 591 else
267f0c90 592 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 593 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 594
d6bbafa1
CW		 595 if (INTEL_INFO(dev)->gen >= 4)
596 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
597 else
598 addr = I915_READ(DSPADDR(crtc->plane));
599 seq_printf(m, "Current scanout address 0x%08x\n", addr);
600
4e5359cd 601 if (work->pending_flip_obj) {
d6bbafa1
CW		 602 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
603 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 604 }
605 }
5e2d7afc 606 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 607 }
608
8a270ebf
DV		 609 mutex_unlock(&dev->struct_mutex);
610
4e5359cd
SF		 611 return 0;
612}
613
493018dc
BV		 614static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
615{
616 struct drm_info_node *node = m->private;
617 struct drm_device *dev = node->minor->dev;
618 struct drm_i915_private *dev_priv = dev->dev_private;
619 struct drm_i915_gem_object *obj;
06fbca71 620 struct intel_engine_cs *ring;
493018dc 621 int count = 0;
06fbca71 622 int ret, i;
493018dc
BV		 623
624 ret = mutex_lock_interruptible(&dev->struct_mutex);
625 if (ret)
626 return ret;
627
06fbca71
CW		 628 for_each_ring(ring, dev_priv, i) {
629 seq_printf(m, "%s cache:\n", ring->name);
630 list_for_each_entry(obj,
631 &ring->batch_pool.cache_list,
632 batch_pool_list) {
633 seq_puts(m, " ");
634 describe_obj(m, obj);
635 seq_putc(m, '\n');
636 count++;
637 }
493018dc
BV		 638 }
639
640 seq_printf(m, "total: %d\n", count);
641
642 mutex_unlock(&dev->struct_mutex);
643
644 return 0;
645}
646
2017263e
BG		 647static int i915_gem_request_info(struct seq_file *m, void *data)
648{
9f25d007 649 struct drm_info_node *node = m->private;
2017263e 650 struct drm_device *dev = node->minor->dev;
e277a1f8 651 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 652 struct intel_engine_cs *ring;
2d1070b2
CW		 653 struct drm_i915_gem_request *rq;
654 int ret, any, i;
de227ef0
CW		 655
656 ret = mutex_lock_interruptible(&dev->struct_mutex);
657 if (ret)
658 return ret;
2017263e 659
2d1070b2 660 any = 0;
a2c7f6fd 661 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 662 int count;
663
664 count = 0;
665 list_for_each_entry(rq, &ring->request_list, list)
666 count++;
667 if (count == 0)
a2c7f6fd
CW		 668 continue;
669
2d1070b2
CW		 670 seq_printf(m, "%s requests: %d\n", ring->name, count);
671 list_for_each_entry(rq, &ring->request_list, list) {
672 struct task_struct *task;
673
674 rcu_read_lock();
675 task = NULL;
676 if (rq->pid)
677 task = pid_task(rq->pid, PIDTYPE_PID);
678 seq_printf(m, " %x @ %d: %s [%d]\n",
679 rq->seqno,
680 (int) (jiffies - rq->emitted_jiffies),
681 task ? task->comm : "<unknown>",
682 task ? task->pid : -1);
683 rcu_read_unlock();
c2c347a9 684 }
2d1070b2
CW		 685
686 any++;
2017263e 687 }
de227ef0
CW		 688 mutex_unlock(&dev->struct_mutex);
689
2d1070b2 690 if (any == 0)
267f0c90 691 seq_puts(m, "No requests\n");
c2c347a9 692
2017263e
BG		 693 return 0;
694}
695
b2223497 696static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 697 struct intel_engine_cs *ring)
b2223497
CW		 698{
699 if (ring->get_seqno) {
20e28fba 700 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 701 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 702 }
703}
704
2017263e
BG		 705static int i915_gem_seqno_info(struct seq_file *m, void *data)
706{
9f25d007 707 struct drm_info_node *node = m->private;
2017263e 708 struct drm_device *dev = node->minor->dev;
e277a1f8 709 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 710 struct intel_engine_cs *ring;
1ec14ad3 711 int ret, i;
de227ef0
CW		 712
713 ret = mutex_lock_interruptible(&dev->struct_mutex);
714 if (ret)
715 return ret;
c8c8fb33 716 intel_runtime_pm_get(dev_priv);
2017263e 717
a2c7f6fd
CW		 718 for_each_ring(ring, dev_priv, i)
719 i915_ring_seqno_info(m, ring);
de227ef0 720
c8c8fb33 721 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 722 mutex_unlock(&dev->struct_mutex);
723
2017263e
BG		 724 return 0;
725}
726
727
728static int i915_interrupt_info(struct seq_file *m, void *data)
729{
9f25d007 730 struct drm_info_node *node = m->private;
2017263e 731 struct drm_device *dev = node->minor->dev;
e277a1f8 732 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 733 struct intel_engine_cs *ring;
9db4a9c7 734 int ret, i, pipe;
de227ef0
CW		 735
736 ret = mutex_lock_interruptible(&dev->struct_mutex);
737 if (ret)
738 return ret;
c8c8fb33 739 intel_runtime_pm_get(dev_priv);
2017263e 740
74e1ca8c 741 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 742 seq_printf(m, "Master Interrupt Control:\t%08x\n",
743 I915_READ(GEN8_MASTER_IRQ));
744
745 seq_printf(m, "Display IER:\t%08x\n",
746 I915_READ(VLV_IER));
747 seq_printf(m, "Display IIR:\t%08x\n",
748 I915_READ(VLV_IIR));
749 seq_printf(m, "Display IIR_RW:\t%08x\n",
750 I915_READ(VLV_IIR_RW));
751 seq_printf(m, "Display IMR:\t%08x\n",
752 I915_READ(VLV_IMR));
055e393f 753 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 754 seq_printf(m, "Pipe %c stat:\t%08x\n",
755 pipe_name(pipe),
756 I915_READ(PIPESTAT(pipe)));
757
758 seq_printf(m, "Port hotplug:\t%08x\n",
759 I915_READ(PORT_HOTPLUG_EN));
760 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
761 I915_READ(VLV_DPFLIPSTAT));
762 seq_printf(m, "DPINVGTT:\t%08x\n",
763 I915_READ(DPINVGTT));
764
765 for (i = 0; i < 4; i++) {
766 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
767 i, I915_READ(GEN8_GT_IMR(i)));
768 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
769 i, I915_READ(GEN8_GT_IIR(i)));
770 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
771 i, I915_READ(GEN8_GT_IER(i)));
772 }
773
774 seq_printf(m, "PCU interrupt mask:\t%08x\n",
775 I915_READ(GEN8_PCU_IMR));
776 seq_printf(m, "PCU interrupt identity:\t%08x\n",
777 I915_READ(GEN8_PCU_IIR));
778 seq_printf(m, "PCU interrupt enable:\t%08x\n",
779 I915_READ(GEN8_PCU_IER));
780 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 781 seq_printf(m, "Master Interrupt Control:\t%08x\n",
782 I915_READ(GEN8_MASTER_IRQ));
783
784 for (i = 0; i < 4; i++) {
785 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
786 i, I915_READ(GEN8_GT_IMR(i)));
787 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
788 i, I915_READ(GEN8_GT_IIR(i)));
789 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
790 i, I915_READ(GEN8_GT_IER(i)));
791 }
792
055e393f 793 for_each_pipe(dev_priv, pipe) {
f458ebbc 794 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 795 POWER_DOMAIN_PIPE(pipe))) {
796 seq_printf(m, "Pipe %c power disabled\n",
797 pipe_name(pipe));
798 continue;
799 }
a123f157 800 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 801 pipe_name(pipe),
802 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 803 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 804 pipe_name(pipe),
805 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 806 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 807 pipe_name(pipe),
808 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 809 }
810
811 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
812 I915_READ(GEN8_DE_PORT_IMR));
813 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
814 I915_READ(GEN8_DE_PORT_IIR));
815 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
816 I915_READ(GEN8_DE_PORT_IER));
817
818 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
819 I915_READ(GEN8_DE_MISC_IMR));
820 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
821 I915_READ(GEN8_DE_MISC_IIR));
822 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
823 I915_READ(GEN8_DE_MISC_IER));
824
825 seq_printf(m, "PCU interrupt mask:\t%08x\n",
826 I915_READ(GEN8_PCU_IMR));
827 seq_printf(m, "PCU interrupt identity:\t%08x\n",
828 I915_READ(GEN8_PCU_IIR));
829 seq_printf(m, "PCU interrupt enable:\t%08x\n",
830 I915_READ(GEN8_PCU_IER));
831 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 832 seq_printf(m, "Display IER:\t%08x\n",
833 I915_READ(VLV_IER));
834 seq_printf(m, "Display IIR:\t%08x\n",
835 I915_READ(VLV_IIR));
836 seq_printf(m, "Display IIR_RW:\t%08x\n",
837 I915_READ(VLV_IIR_RW));
838 seq_printf(m, "Display IMR:\t%08x\n",
839 I915_READ(VLV_IMR));
055e393f 840 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 841 seq_printf(m, "Pipe %c stat:\t%08x\n",
842 pipe_name(pipe),
843 I915_READ(PIPESTAT(pipe)));
844
845 seq_printf(m, "Master IER:\t%08x\n",
846 I915_READ(VLV_MASTER_IER));
847
848 seq_printf(m, "Render IER:\t%08x\n",
849 I915_READ(GTIER));
850 seq_printf(m, "Render IIR:\t%08x\n",
851 I915_READ(GTIIR));
852 seq_printf(m, "Render IMR:\t%08x\n",
853 I915_READ(GTIMR));
854
855 seq_printf(m, "PM IER:\t\t%08x\n",
856 I915_READ(GEN6_PMIER));
857 seq_printf(m, "PM IIR:\t\t%08x\n",
858 I915_READ(GEN6_PMIIR));
859 seq_printf(m, "PM IMR:\t\t%08x\n",
860 I915_READ(GEN6_PMIMR));
861
862 seq_printf(m, "Port hotplug:\t%08x\n",
863 I915_READ(PORT_HOTPLUG_EN));
864 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
865 I915_READ(VLV_DPFLIPSTAT));
866 seq_printf(m, "DPINVGTT:\t%08x\n",
867 I915_READ(DPINVGTT));
868
869 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 870 seq_printf(m, "Interrupt enable: %08x\n",
871 I915_READ(IER));
872 seq_printf(m, "Interrupt identity: %08x\n",
873 I915_READ(IIR));
874 seq_printf(m, "Interrupt mask: %08x\n",
875 I915_READ(IMR));
055e393f 876 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 877 seq_printf(m, "Pipe %c stat: %08x\n",
878 pipe_name(pipe),
879 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 880 } else {
881 seq_printf(m, "North Display Interrupt enable: %08x\n",
882 I915_READ(DEIER));
883 seq_printf(m, "North Display Interrupt identity: %08x\n",
884 I915_READ(DEIIR));
885 seq_printf(m, "North Display Interrupt mask: %08x\n",
886 I915_READ(DEIMR));
887 seq_printf(m, "South Display Interrupt enable: %08x\n",
888 I915_READ(SDEIER));
889 seq_printf(m, "South Display Interrupt identity: %08x\n",
890 I915_READ(SDEIIR));
891 seq_printf(m, "South Display Interrupt mask: %08x\n",
892 I915_READ(SDEIMR));
893 seq_printf(m, "Graphics Interrupt enable: %08x\n",
894 I915_READ(GTIER));
895 seq_printf(m, "Graphics Interrupt identity: %08x\n",
896 I915_READ(GTIIR));
897 seq_printf(m, "Graphics Interrupt mask: %08x\n",
898 I915_READ(GTIMR));
899 }
a2c7f6fd 900 for_each_ring(ring, dev_priv, i) {
a123f157 901 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 902 seq_printf(m,
903 "Graphics Interrupt mask (%s): %08x\n",
904 ring->name, I915_READ_IMR(ring));
9862e600 905 }
a2c7f6fd 906 i915_ring_seqno_info(m, ring);
9862e600 907 }
c8c8fb33 908 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 909 mutex_unlock(&dev->struct_mutex);
910
2017263e
BG		 911 return 0;
912}
913
a6172a80
CW		 914static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
915{
9f25d007 916 struct drm_info_node *node = m->private;
a6172a80 917 struct drm_device *dev = node->minor->dev;
e277a1f8 918 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 919 int i, ret;
920
921 ret = mutex_lock_interruptible(&dev->struct_mutex);
922 if (ret)
923 return ret;
a6172a80
CW		 924
925 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
926 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
927 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 928 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 929
6c085a72
CW		 930 seq_printf(m, "Fence %d, pin count = %d, object = ",
931 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 932 if (obj == NULL)
267f0c90 933 seq_puts(m, "unused");
c2c347a9 934 else
05394f39 935 describe_obj(m, obj);
267f0c90 936 seq_putc(m, '\n');
a6172a80
CW		 937 }
938
05394f39 939 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 940 return 0;
941}
942
2017263e
BG		 943static int i915_hws_info(struct seq_file *m, void *data)
944{
9f25d007 945 struct drm_info_node *node = m->private;
2017263e 946 struct drm_device *dev = node->minor->dev;
e277a1f8 947 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 948 struct intel_engine_cs *ring;
1a240d4d 949 const u32 *hws;
4066c0ae
CW		 950 int i;
951
1ec14ad3 952 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 953 hws = ring->status_page.page_addr;
2017263e
BG		 954 if (hws == NULL)
955 return 0;
956
957 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
958 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
959 i * 4,
960 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
961 }
962 return 0;
963}
964
d5442303
DV		 965static ssize_t
966i915_error_state_write(struct file *filp,
967 const char __user *ubuf,
968 size_t cnt,
969 loff_t *ppos)
970{
edc3d884 971 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 972 struct drm_device *dev = error_priv->dev;
22bcfc6a 973 int ret;
d5442303
DV		 974
975 DRM_DEBUG_DRIVER("Resetting error state\n");
976
22bcfc6a
DV		 977 ret = mutex_lock_interruptible(&dev->struct_mutex);
978 if (ret)
979 return ret;
980
d5442303
DV		 981 i915_destroy_error_state(dev);
982 mutex_unlock(&dev->struct_mutex);
983
984 return cnt;
985}
986
987static int i915_error_state_open(struct inode *inode, struct file *file)
988{
989 struct drm_device *dev = inode->i_private;
d5442303 990 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 991
992 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
993 if (!error_priv)
994 return -ENOMEM;
995
996 error_priv->dev = dev;
997
95d5bfb3 998 i915_error_state_get(dev, error_priv);
d5442303 999
edc3d884
MK		 1000 file->private_data = error_priv;
1001
1002 return 0;
d5442303
DV		 1003}
1004
1005static int i915_error_state_release(struct inode *inode, struct file *file)
1006{
edc3d884 1007 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1008
95d5bfb3 1009 i915_error_state_put(error_priv);
d5442303
DV		 1010 kfree(error_priv);
1011
edc3d884
MK		 1012 return 0;
1013}
1014
4dc955f7
MK		 1015static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1016 size_t count, loff_t *pos)
1017{
1018 struct i915_error_state_file_priv *error_priv = file->private_data;
1019 struct drm_i915_error_state_buf error_str;
1020 loff_t tmp_pos = 0;
1021 ssize_t ret_count = 0;
1022 int ret;
1023
0a4cd7c8 1024 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1025 if (ret)
1026 return ret;
edc3d884 1027
fc16b48b 1028 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1029 if (ret)
1030 goto out;
1031
edc3d884
MK		 1032 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1033 error_str.buf,
1034 error_str.bytes);
1035
1036 if (ret_count < 0)
1037 ret = ret_count;
1038 else
1039 *pos = error_str.start + ret_count;
1040out:
4dc955f7 1041 i915_error_state_buf_release(&error_str);
edc3d884 1042 return ret ?: ret_count;
d5442303
DV		 1043}
1044
1045static const struct file_operations i915_error_state_fops = {
1046 .owner = THIS_MODULE,
1047 .open = i915_error_state_open,
edc3d884 1048 .read = i915_error_state_read,
d5442303
DV		 1049 .write = i915_error_state_write,
1050 .llseek = default_llseek,
1051 .release = i915_error_state_release,
1052};
1053
647416f9
KC		 1054static int
1055i915_next_seqno_get(void *data, u64 *val)
40633219 1056{
647416f9 1057 struct drm_device *dev = data;
e277a1f8 1058 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1059 int ret;
1060
1061 ret = mutex_lock_interruptible(&dev->struct_mutex);
1062 if (ret)
1063 return ret;
1064
647416f9 1065 *val = dev_priv->next_seqno;
40633219
MK		 1066 mutex_unlock(&dev->struct_mutex);
1067
647416f9 1068 return 0;
40633219
MK		 1069}
1070
647416f9
KC		 1071static int
1072i915_next_seqno_set(void *data, u64 val)
1073{
1074 struct drm_device *dev = data;
40633219
MK		 1075 int ret;
1076
40633219
MK		 1077 ret = mutex_lock_interruptible(&dev->struct_mutex);
1078 if (ret)
1079 return ret;
1080
e94fbaa8 1081 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1082 mutex_unlock(&dev->struct_mutex);
1083
647416f9 1084 return ret;
40633219
MK		 1085}
1086
647416f9
KC		 1087DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1088 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1089 "0x%llx\n");
40633219 1090
adb4bd12 1091static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1092{
9f25d007 1093 struct drm_info_node *node = m->private;
f97108d1 1094 struct drm_device *dev = node->minor->dev;
e277a1f8 1095 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1096 int ret = 0;
1097
1098 intel_runtime_pm_get(dev_priv);
3b8d8d91 1099
5c9669ce
TR		 1100 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1101
3b8d8d91
JB		 1102 if (IS_GEN5(dev)) {
1103 u16 rgvswctl = I915_READ16(MEMSWCTL);
1104 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1105
1106 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1107 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1108 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1109 MEMSTAT_VID_SHIFT);
1110 seq_printf(m, "Current P-state: %d\n",
1111 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2 1112 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
60260a5b 1113 IS_BROADWELL(dev) || IS_GEN9(dev)) {
3b8d8d91
JB		 1114 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1115 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1116 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1117 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1118 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1119 u32 rpupei, rpcurup, rpprevup;
1120 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1121 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1122 int max_freq;
1123
1124 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1125 ret = mutex_lock_interruptible(&dev->struct_mutex);
1126 if (ret)
c8c8fb33 1127 goto out;
d1ebd816 1128
59bad947 1129 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1130
8e8c06cd 1131 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1132 if (IS_GEN9(dev))
1133 reqf >>= 23;
1134 else {
1135 reqf &= ~GEN6_TURBO_DISABLE;
1136 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1137 reqf >>= 24;
1138 else
1139 reqf >>= 25;
1140 }
7c59a9c1 1141 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1142
0d8f9491
CW		 1143 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1144 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1145 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1146
ccab5c82
JB		 1147 rpstat = I915_READ(GEN6_RPSTAT1);
1148 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1149 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1150 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1151 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1152 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1153 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1154 if (IS_GEN9(dev))
1155 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1156 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1157 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1158 else
1159 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1160 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1161
59bad947 1162 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1163 mutex_unlock(&dev->struct_mutex);
1164
9dd3c605
PZ		 1165 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1166 pm_ier = I915_READ(GEN6_PMIER);
1167 pm_imr = I915_READ(GEN6_PMIMR);
1168 pm_isr = I915_READ(GEN6_PMISR);
1169 pm_iir = I915_READ(GEN6_PMIIR);
1170 pm_mask = I915_READ(GEN6_PMINTRMSK);
1171 } else {
1172 pm_ier = I915_READ(GEN8_GT_IER(2));
1173 pm_imr = I915_READ(GEN8_GT_IMR(2));
1174 pm_isr = I915_READ(GEN8_GT_ISR(2));
1175 pm_iir = I915_READ(GEN8_GT_IIR(2));
1176 pm_mask = I915_READ(GEN6_PMINTRMSK);
1177 }
0d8f9491 1178 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1179 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1180 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1181 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1182 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1183 seq_printf(m, "Render p-state VID: %d\n",
1184 gt_perf_status & 0xff);
1185 seq_printf(m, "Render p-state limit: %d\n",
1186 rp_state_limits & 0xff);
0d8f9491
CW		 1187 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1188 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1189 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1190 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1191 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1192 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1193 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1194 GEN6_CURICONT_MASK);
1195 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1196 GEN6_CURBSYTAVG_MASK);
1197 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1198 GEN6_CURBSYTAVG_MASK);
1199 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1200 GEN6_CURIAVG_MASK);
1201 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1202 GEN6_CURBSYTAVG_MASK);
1203 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1204 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1205
1206 max_freq = (rp_state_cap & 0xff0000) >> 16;
60260a5b 1207 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1208 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1209 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1210
1211 max_freq = (rp_state_cap & 0xff00) >> 8;
60260a5b 1212 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1213 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1214 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1215
1216 max_freq = rp_state_cap & 0xff;
60260a5b 1217 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1218 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1219 intel_gpu_freq(dev_priv, max_freq));
31c77388
BW		 1220
1221 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1222 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff
CW		 1223
1224 seq_printf(m, "Idle freq: %d MHz\n",
1225 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
0a073b84 1226 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1227 u32 freq_sts;
0a073b84 1228
259bd5d4 1229 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1230 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1231 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1232 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1233
0a073b84 1234 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1235 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1236
0a073b84 1237 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1238 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1239
aed242ff
CW		 1240 seq_printf(m, "idle GPU freq: %d MHz\n",
1241 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1242
7c59a9c1
VS		 1243 seq_printf(m,
1244 "efficient (RPe) frequency: %d MHz\n",
1245 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1246
1247 seq_printf(m, "current GPU freq: %d MHz\n",
7c59a9c1 1248 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1249 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1250 } else {
267f0c90 1251 seq_puts(m, "no P-state info available\n");
3b8d8d91 1252 }
f97108d1 1253
c8c8fb33
PZ		 1254out:
1255 intel_runtime_pm_put(dev_priv);
1256 return ret;
f97108d1
JB		 1257}
1258
f654449a
CW		 1259static int i915_hangcheck_info(struct seq_file *m, void *unused)
1260{
1261 struct drm_info_node *node = m->private;
ebbc7546
MK		 1262 struct drm_device *dev = node->minor->dev;
1263 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1264 struct intel_engine_cs *ring;
ebbc7546
MK		 1265 u64 acthd[I915_NUM_RINGS];
1266 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1267 int i;
1268
1269 if (!i915.enable_hangcheck) {
1270 seq_printf(m, "Hangcheck disabled\n");
1271 return 0;
1272 }
1273
ebbc7546
MK		 1274 intel_runtime_pm_get(dev_priv);
1275
1276 for_each_ring(ring, dev_priv, i) {
1277 seqno[i] = ring->get_seqno(ring, false);
1278 acthd[i] = intel_ring_get_active_head(ring);
1279 }
1280
1281 intel_runtime_pm_put(dev_priv);
1282
f654449a
CW		 1283 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1284 seq_printf(m, "Hangcheck active, fires in %dms\n",
1285 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1286 jiffies));
1287 } else
1288 seq_printf(m, "Hangcheck inactive\n");
1289
1290 for_each_ring(ring, dev_priv, i) {
1291 seq_printf(m, "%s:\n", ring->name);
1292 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1293 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1294 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1295 (long long)ring->hangcheck.acthd,
ebbc7546 1296 (long long)acthd[i]);
f654449a
CW		 1297 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1298 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1299 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1300 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1301 }
1302
1303 return 0;
1304}
1305
4d85529d 1306static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1307{
9f25d007 1308 struct drm_info_node *node = m->private;
f97108d1 1309 struct drm_device *dev = node->minor->dev;
e277a1f8 1310 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1311 u32 rgvmodectl, rstdbyctl;
1312 u16 crstandvid;
1313 int ret;
1314
1315 ret = mutex_lock_interruptible(&dev->struct_mutex);
1316 if (ret)
1317 return ret;
c8c8fb33 1318 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1319
1320 rgvmodectl = I915_READ(MEMMODECTL);
1321 rstdbyctl = I915_READ(RSTDBYCTL);
1322 crstandvid = I915_READ16(CRSTANDVID);
1323
c8c8fb33 1324 intel_runtime_pm_put(dev_priv);
616fdb5a 1325 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1326
1327 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1328 "yes" : "no");
1329 seq_printf(m, "Boost freq: %d\n",
1330 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1331 MEMMODE_BOOST_FREQ_SHIFT);
1332 seq_printf(m, "HW control enabled: %s\n",
1333 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1334 seq_printf(m, "SW control enabled: %s\n",
1335 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1336 seq_printf(m, "Gated voltage change: %s\n",
1337 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1338 seq_printf(m, "Starting frequency: P%d\n",
1339 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1340 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1341 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1342 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1343 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1344 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1345 seq_printf(m, "Render standby enabled: %s\n",
1346 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1347 seq_puts(m, "Current RS state: ");
88271da3
JB		 1348 switch (rstdbyctl & RSX_STATUS_MASK) {
1349 case RSX_STATUS_ON:
267f0c90 1350 seq_puts(m, "on\n");
88271da3
JB		 1351 break;
1352 case RSX_STATUS_RC1:
267f0c90 1353 seq_puts(m, "RC1\n");
88271da3
JB		 1354 break;
1355 case RSX_STATUS_RC1E:
267f0c90 1356 seq_puts(m, "RC1E\n");
88271da3
JB		 1357 break;
1358 case RSX_STATUS_RS1:
267f0c90 1359 seq_puts(m, "RS1\n");
88271da3
JB		 1360 break;
1361 case RSX_STATUS_RS2:
267f0c90 1362 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1363 break;
1364 case RSX_STATUS_RS3:
267f0c90 1365 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1366 break;
1367 default:
267f0c90 1368 seq_puts(m, "unknown\n");
88271da3
JB		 1369 break;
1370 }
f97108d1
JB		 1371
1372 return 0;
1373}
1374
f65367b5 1375static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1376{
b2cff0db
CW		 1377 struct drm_info_node *node = m->private;
1378 struct drm_device *dev = node->minor->dev;
1379 struct drm_i915_private *dev_priv = dev->dev_private;
1380 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1381 int i;
1382
1383 spin_lock_irq(&dev_priv->uncore.lock);
1384 for_each_fw_domain(fw_domain, dev_priv, i) {
1385 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1386 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1387 fw_domain->wake_count);
1388 }
1389 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1390
b2cff0db
CW		 1391 return 0;
1392}
1393
1394static int vlv_drpc_info(struct seq_file *m)
1395{
9f25d007 1396 struct drm_info_node *node = m->private;
669ab5aa
D		 1397 struct drm_device *dev = node->minor->dev;
1398 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1399 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1400
d46c0517
ID		 1401 intel_runtime_pm_get(dev_priv);
1402
6b312cd3 1403 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1404 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1405 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1406
d46c0517
ID		 1407 intel_runtime_pm_put(dev_priv);
1408
669ab5aa
D		 1409 seq_printf(m, "Video Turbo Mode: %s\n",
1410 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1411 seq_printf(m, "Turbo enabled: %s\n",
1412 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1413 seq_printf(m, "HW control enabled: %s\n",
1414 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1415 seq_printf(m, "SW control enabled: %s\n",
1416 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1417 GEN6_RP_MEDIA_SW_MODE));
1418 seq_printf(m, "RC6 Enabled: %s\n",
1419 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1420 GEN6_RC_CTL_EI_MODE(1))));
1421 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1422 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1423 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1424 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1425
9cc19be5
ID		 1426 seq_printf(m, "Render RC6 residency since boot: %u\n",
1427 I915_READ(VLV_GT_RENDER_RC6));
1428 seq_printf(m, "Media RC6 residency since boot: %u\n",
1429 I915_READ(VLV_GT_MEDIA_RC6));
1430
f65367b5 1431 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1432}
1433
4d85529d
BW		 1434static int gen6_drpc_info(struct seq_file *m)
1435{
9f25d007 1436 struct drm_info_node *node = m->private;
4d85529d
BW		 1437 struct drm_device *dev = node->minor->dev;
1438 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1439 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1440 unsigned forcewake_count;
aee56cff 1441 int count = 0, ret;
4d85529d
BW		 1442
1443 ret = mutex_lock_interruptible(&dev->struct_mutex);
1444 if (ret)
1445 return ret;
c8c8fb33 1446 intel_runtime_pm_get(dev_priv);
4d85529d 1447
907b28c5 1448 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1449 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1450 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1451
1452 if (forcewake_count) {
267f0c90
DL		 1453 seq_puts(m, "RC information inaccurate because somebody "
1454 "holds a forcewake reference \n");
4d85529d
BW		 1455 } else {
1456 /* NB: we cannot use forcewake, else we read the wrong values */
1457 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1458 udelay(10);
1459 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1460 }
1461
1462 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1463 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1464
1465 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1466 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1467 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1468 mutex_lock(&dev_priv->rps.hw_lock);
1469 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1470 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1471
c8c8fb33
PZ		 1472 intel_runtime_pm_put(dev_priv);
1473
4d85529d
BW		 1474 seq_printf(m, "Video Turbo Mode: %s\n",
1475 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1476 seq_printf(m, "HW control enabled: %s\n",
1477 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1478 seq_printf(m, "SW control enabled: %s\n",
1479 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1480 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1481 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1482 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1483 seq_printf(m, "RC6 Enabled: %s\n",
1484 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1485 seq_printf(m, "Deep RC6 Enabled: %s\n",
1486 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1487 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1488 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1489 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1490 switch (gt_core_status & GEN6_RCn_MASK) {
1491 case GEN6_RC0:
1492 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1493 seq_puts(m, "Core Power Down\n");
4d85529d 1494 else
267f0c90 1495 seq_puts(m, "on\n");
4d85529d
BW		 1496 break;
1497 case GEN6_RC3:
267f0c90 1498 seq_puts(m, "RC3\n");
4d85529d
BW		 1499 break;
1500 case GEN6_RC6:
267f0c90 1501 seq_puts(m, "RC6\n");
4d85529d
BW		 1502 break;
1503 case GEN6_RC7:
267f0c90 1504 seq_puts(m, "RC7\n");
4d85529d
BW		 1505 break;
1506 default:
267f0c90 1507 seq_puts(m, "Unknown\n");
4d85529d
BW		 1508 break;
1509 }
1510
1511 seq_printf(m, "Core Power Down: %s\n",
1512 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1513
1514 /* Not exactly sure what this is */
1515 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1516 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1517 seq_printf(m, "RC6 residency since boot: %u\n",
1518 I915_READ(GEN6_GT_GFX_RC6));
1519 seq_printf(m, "RC6+ residency since boot: %u\n",
1520 I915_READ(GEN6_GT_GFX_RC6p));
1521 seq_printf(m, "RC6++ residency since boot: %u\n",
1522 I915_READ(GEN6_GT_GFX_RC6pp));
1523
ecd8faea
BW		 1524 seq_printf(m, "RC6 voltage: %dmV\n",
1525 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1526 seq_printf(m, "RC6+ voltage: %dmV\n",
1527 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1528 seq_printf(m, "RC6++ voltage: %dmV\n",
1529 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1530 return 0;
1531}
1532
1533static int i915_drpc_info(struct seq_file *m, void *unused)
1534{
9f25d007 1535 struct drm_info_node *node = m->private;
4d85529d
BW		 1536 struct drm_device *dev = node->minor->dev;
1537
669ab5aa
D		 1538 if (IS_VALLEYVIEW(dev))
1539 return vlv_drpc_info(m);
ac66cf4b 1540 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1541 return gen6_drpc_info(m);
1542 else
1543 return ironlake_drpc_info(m);
1544}
1545
b5e50c3f
JB		 1546static int i915_fbc_status(struct seq_file *m, void *unused)
1547{
9f25d007 1548 struct drm_info_node *node = m->private;
b5e50c3f 1549 struct drm_device *dev = node->minor->dev;
e277a1f8 1550 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1551
3a77c4c4 1552 if (!HAS_FBC(dev)) {
267f0c90 1553 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1554 return 0;
1555 }
1556
36623ef8
PZ		 1557 intel_runtime_pm_get(dev_priv);
1558
ee5382ae 1559 if (intel_fbc_enabled(dev)) {
267f0c90 1560 seq_puts(m, "FBC enabled\n");
b5e50c3f 1561 } else {
267f0c90 1562 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1563 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1564 case FBC_OK:
1565 seq_puts(m, "FBC actived, but currently disabled in hardware");
1566 break;
1567 case FBC_UNSUPPORTED:
1568 seq_puts(m, "unsupported by this chipset");
1569 break;
bed4a673 1570 case FBC_NO_OUTPUT:
267f0c90 1571 seq_puts(m, "no outputs");
bed4a673 1572 break;
b5e50c3f 1573 case FBC_STOLEN_TOO_SMALL:
267f0c90 1574 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1575 break;
1576 case FBC_UNSUPPORTED_MODE:
267f0c90 1577 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1578 break;
1579 case FBC_MODE_TOO_LARGE:
267f0c90 1580 seq_puts(m, "mode too large");
b5e50c3f
JB		 1581 break;
1582 case FBC_BAD_PLANE:
267f0c90 1583 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1584 break;
1585 case FBC_NOT_TILED:
267f0c90 1586 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1587 break;
9c928d16 1588 case FBC_MULTIPLE_PIPES:
267f0c90 1589 seq_puts(m, "multiple pipes are enabled");
9c928d16 1590 break;
c1a9f047 1591 case FBC_MODULE_PARAM:
267f0c90 1592 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1593 break;
8a5729a3 1594 case FBC_CHIP_DEFAULT:
267f0c90 1595 seq_puts(m, "disabled per chip default");
8a5729a3 1596 break;
b5e50c3f 1597 default:
267f0c90 1598 seq_puts(m, "unknown reason");
b5e50c3f 1599 }
267f0c90 1600 seq_putc(m, '\n');
b5e50c3f 1601 }
36623ef8
PZ		 1602
1603 intel_runtime_pm_put(dev_priv);
1604
b5e50c3f
JB		 1605 return 0;
1606}
1607
da46f936
RV		 1608static int i915_fbc_fc_get(void *data, u64 *val)
1609{
1610 struct drm_device *dev = data;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612
1613 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1614 return -ENODEV;
1615
1616 drm_modeset_lock_all(dev);
1617 *val = dev_priv->fbc.false_color;
1618 drm_modeset_unlock_all(dev);
1619
1620 return 0;
1621}
1622
1623static int i915_fbc_fc_set(void *data, u64 val)
1624{
1625 struct drm_device *dev = data;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 u32 reg;
1628
1629 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1630 return -ENODEV;
1631
1632 drm_modeset_lock_all(dev);
1633
1634 reg = I915_READ(ILK_DPFC_CONTROL);
1635 dev_priv->fbc.false_color = val;
1636
1637 I915_WRITE(ILK_DPFC_CONTROL, val ?
1638 (reg | FBC_CTL_FALSE_COLOR) :
1639 (reg & ~FBC_CTL_FALSE_COLOR));
1640
1641 drm_modeset_unlock_all(dev);
1642 return 0;
1643}
1644
1645DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1646 i915_fbc_fc_get, i915_fbc_fc_set,
1647 "%llu\n");
1648
92d44621
PZ		 1649static int i915_ips_status(struct seq_file *m, void *unused)
1650{
9f25d007 1651 struct drm_info_node *node = m->private;
92d44621
PZ		 1652 struct drm_device *dev = node->minor->dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654
f5adf94e 1655 if (!HAS_IPS(dev)) {
92d44621
PZ		 1656 seq_puts(m, "not supported\n");
1657 return 0;
1658 }
1659
36623ef8
PZ		 1660 intel_runtime_pm_get(dev_priv);
1661
0eaa53f0
RV		 1662 seq_printf(m, "Enabled by kernel parameter: %s\n",
1663 yesno(i915.enable_ips));
1664
1665 if (INTEL_INFO(dev)->gen >= 8) {
1666 seq_puts(m, "Currently: unknown\n");
1667 } else {
1668 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1669 seq_puts(m, "Currently: enabled\n");
1670 else
1671 seq_puts(m, "Currently: disabled\n");
1672 }
92d44621 1673
36623ef8
PZ		 1674 intel_runtime_pm_put(dev_priv);
1675
92d44621
PZ		 1676 return 0;
1677}
1678
4a9bef37
JB		 1679static int i915_sr_status(struct seq_file *m, void *unused)
1680{
9f25d007 1681 struct drm_info_node *node = m->private;
4a9bef37 1682 struct drm_device *dev = node->minor->dev;
e277a1f8 1683 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1684 bool sr_enabled = false;
1685
36623ef8
PZ		 1686 intel_runtime_pm_get(dev_priv);
1687
1398261a 1688 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1689 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1690 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1691 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1692 else if (IS_I915GM(dev))
1693 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1694 else if (IS_PINEVIEW(dev))
1695 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1696
36623ef8
PZ		 1697 intel_runtime_pm_put(dev_priv);
1698
5ba2aaaa
CW		 1699 seq_printf(m, "self-refresh: %s\n",
1700 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1701
1702 return 0;
1703}
1704
7648fa99
JB		 1705static int i915_emon_status(struct seq_file *m, void *unused)
1706{
9f25d007 1707 struct drm_info_node *node = m->private;
7648fa99 1708 struct drm_device *dev = node->minor->dev;
e277a1f8 1709 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1710 unsigned long temp, chipset, gfx;
de227ef0
CW		 1711 int ret;
1712
582be6b4
CW		 1713 if (!IS_GEN5(dev))
1714 return -ENODEV;
1715
de227ef0
CW		 1716 ret = mutex_lock_interruptible(&dev->struct_mutex);
1717 if (ret)
1718 return ret;
7648fa99
JB		 1719
1720 temp = i915_mch_val(dev_priv);
1721 chipset = i915_chipset_val(dev_priv);
1722 gfx = i915_gfx_val(dev_priv);
de227ef0 1723 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1724
1725 seq_printf(m, "GMCH temp: %ld\n", temp);
1726 seq_printf(m, "Chipset power: %ld\n", chipset);
1727 seq_printf(m, "GFX power: %ld\n", gfx);
1728 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1729
1730 return 0;
1731}
1732
23b2f8bb
JB		 1733static int i915_ring_freq_table(struct seq_file *m, void *unused)
1734{
9f25d007 1735 struct drm_info_node *node = m->private;
23b2f8bb 1736 struct drm_device *dev = node->minor->dev;
e277a1f8 1737 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1738 int ret = 0;
23b2f8bb
JB		 1739 int gpu_freq, ia_freq;
1740
1c70c0ce 1741 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1742 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1743 return 0;
1744 }
1745
5bfa0199
PZ		 1746 intel_runtime_pm_get(dev_priv);
1747
5c9669ce
TR		 1748 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1749
4fc688ce 1750 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1751 if (ret)
5bfa0199 1752 goto out;
23b2f8bb 1753
267f0c90 1754 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1755
b39fb297
BW		 1756 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1757 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1758 gpu_freq++) {
42c0526c
BW		 1759 ia_freq = gpu_freq;
1760 sandybridge_pcode_read(dev_priv,
1761 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1762 &ia_freq);
3ebecd07 1763 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
7c59a9c1 1764 intel_gpu_freq(dev_priv, gpu_freq),
3ebecd07
CW		 1765 ((ia_freq >> 0) & 0xff) * 100,
1766 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1767 }
1768
4fc688ce 1769 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1770
5bfa0199
PZ		 1771out:
1772 intel_runtime_pm_put(dev_priv);
1773 return ret;
23b2f8bb
JB		 1774}
1775
44834a67
CW		 1776static int i915_opregion(struct seq_file *m, void *unused)
1777{
9f25d007 1778 struct drm_info_node *node = m->private;
44834a67 1779 struct drm_device *dev = node->minor->dev;
e277a1f8 1780 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1781 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1782 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1783 int ret;
1784
0d38f009
DV		 1785 if (data == NULL)
1786 return -ENOMEM;
1787
44834a67
CW		 1788 ret = mutex_lock_interruptible(&dev->struct_mutex);
1789 if (ret)
0d38f009 1790 goto out;
44834a67 1791
0d38f009
DV		 1792 if (opregion->header) {
1793 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1794 seq_write(m, data, OPREGION_SIZE);
1795 }
44834a67
CW		 1796
1797 mutex_unlock(&dev->struct_mutex);
1798
0d38f009
DV		 1799out:
1800 kfree(data);
44834a67
CW		 1801 return 0;
1802}
1803
37811fcc
CW		 1804static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1805{
9f25d007 1806 struct drm_info_node *node = m->private;
37811fcc 1807 struct drm_device *dev = node->minor->dev;
4520f53a 1808 struct intel_fbdev *ifbdev = NULL;
37811fcc 1809 struct intel_framebuffer *fb;
37811fcc 1810
4520f53a
DV		 1811#ifdef CONFIG_DRM_I915_FBDEV
1812 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1813
1814 ifbdev = dev_priv->fbdev;
1815 fb = to_intel_framebuffer(ifbdev->helper.fb);
1816
c1ca506d 1817 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1818 fb->base.width,
1819 fb->base.height,
1820 fb->base.depth,
623f9783 1821 fb->base.bits_per_pixel,
c1ca506d 1822 fb->base.modifier[0],
623f9783 1823 atomic_read(&fb->base.refcount.refcount));
05394f39 1824 describe_obj(m, fb->obj);
267f0c90 1825 seq_putc(m, '\n');
4520f53a 1826#endif
37811fcc 1827
4b096ac1 1828 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1829 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1830 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1831 continue;
1832
c1ca506d 1833 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1834 fb->base.width,
1835 fb->base.height,
1836 fb->base.depth,
623f9783 1837 fb->base.bits_per_pixel,
c1ca506d 1838 fb->base.modifier[0],
623f9783 1839 atomic_read(&fb->base.refcount.refcount));
05394f39 1840 describe_obj(m, fb->obj);
267f0c90 1841 seq_putc(m, '\n');
37811fcc 1842 }
4b096ac1 1843 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1844
1845 return 0;
1846}
1847
c9fe99bd
OM		 1848static void describe_ctx_ringbuf(struct seq_file *m,
1849 struct intel_ringbuffer *ringbuf)
1850{
1851 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1852 ringbuf->space, ringbuf->head, ringbuf->tail,
1853 ringbuf->last_retired_head);
1854}
1855
e76d3630
BW		 1856static int i915_context_status(struct seq_file *m, void *unused)
1857{
9f25d007 1858 struct drm_info_node *node = m->private;
e76d3630 1859 struct drm_device *dev = node->minor->dev;
e277a1f8 1860 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1861 struct intel_engine_cs *ring;
273497e5 1862 struct intel_context *ctx;
a168c293 1863 int ret, i;
e76d3630 1864
f3d28878 1865 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1866 if (ret)
1867 return ret;
1868
a33afea5 1869 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1870 if (!i915.enable_execlists &&
1871 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1872 continue;
1873
a33afea5 1874 seq_puts(m, "HW context ");
3ccfd19d 1875 describe_ctx(m, ctx);
c9fe99bd 1876 for_each_ring(ring, dev_priv, i) {
a33afea5 1877 if (ring->default_context == ctx)
c9fe99bd
OM		 1878 seq_printf(m, "(default context %s) ",
1879 ring->name);
1880 }
1881
1882 if (i915.enable_execlists) {
1883 seq_putc(m, '\n');
1884 for_each_ring(ring, dev_priv, i) {
1885 struct drm_i915_gem_object *ctx_obj =
1886 ctx->engine[i].state;
1887 struct intel_ringbuffer *ringbuf =
1888 ctx->engine[i].ringbuf;
1889
1890 seq_printf(m, "%s: ", ring->name);
1891 if (ctx_obj)
1892 describe_obj(m, ctx_obj);
1893 if (ringbuf)
1894 describe_ctx_ringbuf(m, ringbuf);
1895 seq_putc(m, '\n');
1896 }
1897 } else {
1898 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1899 }
a33afea5 1900
a33afea5 1901 seq_putc(m, '\n');
a168c293
BW		 1902 }
1903
f3d28878 1904 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1905
1906 return 0;
1907}
1908
064ca1d2
TD		 1909static void i915_dump_lrc_obj(struct seq_file *m,
1910 struct intel_engine_cs *ring,
1911 struct drm_i915_gem_object *ctx_obj)
1912{
1913 struct page *page;
1914 uint32_t *reg_state;
1915 int j;
1916 unsigned long ggtt_offset = 0;
1917
1918 if (ctx_obj == NULL) {
1919 seq_printf(m, "Context on %s with no gem object\n",
1920 ring->name);
1921 return;
1922 }
1923
1924 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1925 intel_execlists_ctx_id(ctx_obj));
1926
1927 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1928 seq_puts(m, "\tNot bound in GGTT\n");
1929 else
1930 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1931
1932 if (i915_gem_object_get_pages(ctx_obj)) {
1933 seq_puts(m, "\tFailed to get pages for context object\n");
1934 return;
1935 }
1936
1937 page = i915_gem_object_get_page(ctx_obj, 1);
1938 if (!WARN_ON(page == NULL)) {
1939 reg_state = kmap_atomic(page);
1940
1941 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1942 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1943 ggtt_offset + 4096 + (j * 4),
1944 reg_state[j], reg_state[j + 1],
1945 reg_state[j + 2], reg_state[j + 3]);
1946 }
1947 kunmap_atomic(reg_state);
1948 }
1949
1950 seq_putc(m, '\n');
1951}
1952
c0ab1ae9
BW		 1953static int i915_dump_lrc(struct seq_file *m, void *unused)
1954{
1955 struct drm_info_node *node = (struct drm_info_node *) m->private;
1956 struct drm_device *dev = node->minor->dev;
1957 struct drm_i915_private *dev_priv = dev->dev_private;
1958 struct intel_engine_cs *ring;
1959 struct intel_context *ctx;
1960 int ret, i;
1961
1962 if (!i915.enable_execlists) {
1963 seq_printf(m, "Logical Ring Contexts are disabled\n");
1964 return 0;
1965 }
1966
1967 ret = mutex_lock_interruptible(&dev->struct_mutex);
1968 if (ret)
1969 return ret;
1970
1971 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1972 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 1973 if (ring->default_context != ctx)
1974 i915_dump_lrc_obj(m, ring,
1975 ctx->engine[i].state);
c0ab1ae9
BW		 1976 }
1977 }
1978
1979 mutex_unlock(&dev->struct_mutex);
1980
1981 return 0;
1982}
1983
4ba70e44
OM		 1984static int i915_execlists(struct seq_file *m, void *data)
1985{
1986 struct drm_info_node *node = (struct drm_info_node *)m->private;
1987 struct drm_device *dev = node->minor->dev;
1988 struct drm_i915_private *dev_priv = dev->dev_private;
1989 struct intel_engine_cs *ring;
1990 u32 status_pointer;
1991 u8 read_pointer;
1992 u8 write_pointer;
1993 u32 status;
1994 u32 ctx_id;
1995 struct list_head *cursor;
1996 int ring_id, i;
1997 int ret;
1998
1999 if (!i915.enable_execlists) {
2000 seq_puts(m, "Logical Ring Contexts are disabled\n");
2001 return 0;
2002 }
2003
2004 ret = mutex_lock_interruptible(&dev->struct_mutex);
2005 if (ret)
2006 return ret;
2007
fc0412ec
MT		 2008 intel_runtime_pm_get(dev_priv);
2009
4ba70e44 2010 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2011 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2012 int count = 0;
2013 unsigned long flags;
2014
2015 seq_printf(m, "%s\n", ring->name);
2016
2017 status = I915_READ(RING_EXECLIST_STATUS(ring));
2018 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2019 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2020 status, ctx_id);
2021
2022 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2023 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2024
2025 read_pointer = ring->next_context_status_buffer;
2026 write_pointer = status_pointer & 0x07;
2027 if (read_pointer > write_pointer)
2028 write_pointer += 6;
2029 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2030 read_pointer, write_pointer);
2031
2032 for (i = 0; i < 6; i++) {
2033 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2034 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2035
2036 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2037 i, status, ctx_id);
2038 }
2039
2040 spin_lock_irqsave(&ring->execlist_lock, flags);
2041 list_for_each(cursor, &ring->execlist_queue)
2042 count++;
2043 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2044 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2045 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2046
2047 seq_printf(m, "\t%d requests in queue\n", count);
2048 if (head_req) {
2049 struct drm_i915_gem_object *ctx_obj;
2050
6d3d8274 2051 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2052 seq_printf(m, "\tHead request id: %u\n",
2053 intel_execlists_ctx_id(ctx_obj));
2054 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2055 head_req->tail);
4ba70e44
OM		 2056 }
2057
2058 seq_putc(m, '\n');
2059 }
2060
fc0412ec 2061 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2062 mutex_unlock(&dev->struct_mutex);
2063
2064 return 0;
2065}
2066
ea16a3cd
DV		 2067static const char *swizzle_string(unsigned swizzle)
2068{
aee56cff 2069 switch (swizzle) {
ea16a3cd
DV		 2070 case I915_BIT_6_SWIZZLE_NONE:
2071 return "none";
2072 case I915_BIT_6_SWIZZLE_9:
2073 return "bit9";
2074 case I915_BIT_6_SWIZZLE_9_10:
2075 return "bit9/bit10";
2076 case I915_BIT_6_SWIZZLE_9_11:
2077 return "bit9/bit11";
2078 case I915_BIT_6_SWIZZLE_9_10_11:
2079 return "bit9/bit10/bit11";
2080 case I915_BIT_6_SWIZZLE_9_17:
2081 return "bit9/bit17";
2082 case I915_BIT_6_SWIZZLE_9_10_17:
2083 return "bit9/bit10/bit17";
2084 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2085 return "unknown";
ea16a3cd
DV		 2086 }
2087
2088 return "bug";
2089}
2090
2091static int i915_swizzle_info(struct seq_file *m, void *data)
2092{
9f25d007 2093 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2094 struct drm_device *dev = node->minor->dev;
2095 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2096 int ret;
2097
2098 ret = mutex_lock_interruptible(&dev->struct_mutex);
2099 if (ret)
2100 return ret;
c8c8fb33 2101 intel_runtime_pm_get(dev_priv);
ea16a3cd 2102
ea16a3cd
DV		 2103 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2104 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2105 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2106 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2107
2108 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2109 seq_printf(m, "DDC = 0x%08x\n",
2110 I915_READ(DCC));
656bfa3a
DV		 2111 seq_printf(m, "DDC2 = 0x%08x\n",
2112 I915_READ(DCC2));
ea16a3cd
DV		 2113 seq_printf(m, "C0DRB3 = 0x%04x\n",
2114 I915_READ16(C0DRB3));
2115 seq_printf(m, "C1DRB3 = 0x%04x\n",
2116 I915_READ16(C1DRB3));
9d3203e1 2117 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2118 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2119 I915_READ(MAD_DIMM_C0));
2120 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2121 I915_READ(MAD_DIMM_C1));
2122 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2123 I915_READ(MAD_DIMM_C2));
2124 seq_printf(m, "TILECTL = 0x%08x\n",
2125 I915_READ(TILECTL));
5907f5fb 2126 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2127 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2128 I915_READ(GAMTARBMODE));
2129 else
2130 seq_printf(m, "ARB_MODE = 0x%08x\n",
2131 I915_READ(ARB_MODE));
3fa7d235
DV		 2132 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2133 I915_READ(DISP_ARB_CTL));
ea16a3cd 2134 }
656bfa3a
DV		 2135
2136 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2137 seq_puts(m, "L-shaped memory detected\n");
2138
c8c8fb33 2139 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2140 mutex_unlock(&dev->struct_mutex);
2141
2142 return 0;
2143}
2144
1c60fef5
BW		 2145static int per_file_ctx(int id, void *ptr, void *data)
2146{
273497e5 2147 struct intel_context *ctx = ptr;
1c60fef5 2148 struct seq_file *m = data;
ae6c4806
DV		 2149 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2150
2151 if (!ppgtt) {
2152 seq_printf(m, " no ppgtt for context %d\n",
2153 ctx->user_handle);
2154 return 0;
2155 }
1c60fef5 2156
f83d6518
OM		 2157 if (i915_gem_context_is_default(ctx))
2158 seq_puts(m, " default context:\n");
2159 else
821d66dd 2160 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2161 ppgtt->debug_dump(ppgtt, m);
2162
2163 return 0;
2164}
2165
77df6772 2166static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2167{
3cf17fc5 2168 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2169 struct intel_engine_cs *ring;
77df6772
BW		 2170 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2171 int unused, i;
3cf17fc5 2172
77df6772
BW		 2173 if (!ppgtt)
2174 return;
2175
2176 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2177 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2178 for_each_ring(ring, dev_priv, unused) {
2179 seq_printf(m, "%s\n", ring->name);
2180 for (i = 0; i < 4; i++) {
2181 u32 offset = 0x270 + i * 8;
2182 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2183 pdp <<= 32;
2184 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2185 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2186 }
2187 }
2188}
2189
2190static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2191{
2192 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2193 struct intel_engine_cs *ring;
1c60fef5 2194 struct drm_file *file;
77df6772 2195 int i;
3cf17fc5 2196
3cf17fc5
DV		 2197 if (INTEL_INFO(dev)->gen == 6)
2198 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2199
a2c7f6fd 2200 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2201 seq_printf(m, "%s\n", ring->name);
2202 if (INTEL_INFO(dev)->gen == 7)
2203 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2204 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2205 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2206 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2207 }
2208 if (dev_priv->mm.aliasing_ppgtt) {
2209 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2210
267f0c90 2211 seq_puts(m, "aliasing PPGTT:\n");
7324cc04 2212 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
1c60fef5 2213
87d60b63 2214 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2215 }
1c60fef5
BW		 2216
2217 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2218 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2219
1c60fef5
BW		 2220 seq_printf(m, "proc: %s\n",
2221 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2222 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2223 }
2224 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2225}
2226
2227static int i915_ppgtt_info(struct seq_file *m, void *data)
2228{
9f25d007 2229 struct drm_info_node *node = m->private;
77df6772 2230 struct drm_device *dev = node->minor->dev;
c8c8fb33 2231 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2232
2233 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2234 if (ret)
2235 return ret;
c8c8fb33 2236 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2237
2238 if (INTEL_INFO(dev)->gen >= 8)
2239 gen8_ppgtt_info(m, dev);
2240 else if (INTEL_INFO(dev)->gen >= 6)
2241 gen6_ppgtt_info(m, dev);
2242
c8c8fb33 2243 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2244 mutex_unlock(&dev->struct_mutex);
2245
2246 return 0;
2247}
2248
1854d5ca
CW		 2249static int i915_rps_boost_info(struct seq_file *m, void *data)
2250{
2251 struct drm_info_node *node = m->private;
2252 struct drm_device *dev = node->minor->dev;
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254 struct drm_file *file;
2255 int ret;
2256
2257 ret = mutex_lock_interruptible(&dev->struct_mutex);
2258 if (ret)
2259 return ret;
2260
2261 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2262 if (ret)
2263 goto unlock;
2264
2265 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2266 struct drm_i915_file_private *file_priv = file->driver_priv;
2267 struct task_struct *task;
2268
2269 rcu_read_lock();
2270 task = pid_task(file->pid, PIDTYPE_PID);
2271 seq_printf(m, "%s [%d]: %d boosts%s\n",
2272 task ? task->comm : "<unknown>",
2273 task ? task->pid : -1,
2274 file_priv->rps_boosts,
2275 list_empty(&file_priv->rps_boost) ? "" : ", active");
2276 rcu_read_unlock();
2277 }
2278 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2279
2280 mutex_unlock(&dev_priv->rps.hw_lock);
2281unlock:
2282 mutex_unlock(&dev->struct_mutex);
2283
2284 return ret;
2285}
2286
63573eb7
BW		 2287static int i915_llc(struct seq_file *m, void *data)
2288{
9f25d007 2289 struct drm_info_node *node = m->private;
63573eb7
BW		 2290 struct drm_device *dev = node->minor->dev;
2291 struct drm_i915_private *dev_priv = dev->dev_private;
2292
2293 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2294 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2295 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2296
2297 return 0;
2298}
2299
e91fd8c6
RV		 2300static int i915_edp_psr_status(struct seq_file *m, void *data)
2301{
2302 struct drm_info_node *node = m->private;
2303 struct drm_device *dev = node->minor->dev;
2304 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2305 u32 psrperf = 0;
a6cbdb8e
RV		 2306 u32 stat[3];
2307 enum pipe pipe;
a031d709 2308 bool enabled = false;
e91fd8c6 2309
3553a8ea
DL		 2310 if (!HAS_PSR(dev)) {
2311 seq_puts(m, "PSR not supported\n");
2312 return 0;
2313 }
2314
c8c8fb33
PZ		 2315 intel_runtime_pm_get(dev_priv);
2316
fa128fa6 2317 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2318 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2319 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2320 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2321 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2322 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2323 dev_priv->psr.busy_frontbuffer_bits);
2324 seq_printf(m, "Re-enable work scheduled: %s\n",
2325 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2326
3553a8ea
DL		 2327 if (HAS_DDI(dev))
2328 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2329 else {
2330 for_each_pipe(dev_priv, pipe) {
2331 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2332 VLV_EDP_PSR_CURR_STATE_MASK;
2333 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2334 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2335 enabled = true;
a6cbdb8e
RV		 2336 }
2337 }
2338 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2339
2340 if (!HAS_DDI(dev))
2341 for_each_pipe(dev_priv, pipe) {
2342 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2343 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2344 seq_printf(m, " pipe %c", pipe_name(pipe));
2345 }
2346 seq_puts(m, "\n");
e91fd8c6 2347
fb495814
RV		 2348 seq_printf(m, "Link standby: %s\n",
2349 yesno((bool)dev_priv->psr.link_standby));
2350
a6cbdb8e 2351 /* CHV PSR has no kind of performance counter */
3553a8ea 2352 if (HAS_DDI(dev)) {
a031d709
RV		 2353 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2354 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2355
2356 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2357 }
fa128fa6 2358 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2359
c8c8fb33 2360 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2361 return 0;
2362}
2363
d2e216d0
RV		 2364static int i915_sink_crc(struct seq_file *m, void *data)
2365{
2366 struct drm_info_node *node = m->private;
2367 struct drm_device *dev = node->minor->dev;
2368 struct intel_encoder *encoder;
2369 struct intel_connector *connector;
2370 struct intel_dp *intel_dp = NULL;
2371 int ret;
2372 u8 crc[6];
2373
2374 drm_modeset_lock_all(dev);
aca5e361 2375 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2376
2377 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2378 continue;
2379
b6ae3c7c
PZ		 2380 if (!connector->base.encoder)
2381 continue;
2382
d2e216d0
RV		 2383 encoder = to_intel_encoder(connector->base.encoder);
2384 if (encoder->type != INTEL_OUTPUT_EDP)
2385 continue;
2386
2387 intel_dp = enc_to_intel_dp(&encoder->base);
2388
2389 ret = intel_dp_sink_crc(intel_dp, crc);
2390 if (ret)
2391 goto out;
2392
2393 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2394 crc[0], crc[1], crc[2],
2395 crc[3], crc[4], crc[5]);
2396 goto out;
2397 }
2398 ret = -ENODEV;
2399out:
2400 drm_modeset_unlock_all(dev);
2401 return ret;
2402}
2403
ec013e7f
JB		 2404static int i915_energy_uJ(struct seq_file *m, void *data)
2405{
2406 struct drm_info_node *node = m->private;
2407 struct drm_device *dev = node->minor->dev;
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409 u64 power;
2410 u32 units;
2411
2412 if (INTEL_INFO(dev)->gen < 6)
2413 return -ENODEV;
2414
36623ef8
PZ		 2415 intel_runtime_pm_get(dev_priv);
2416
ec013e7f
JB		 2417 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2418 power = (power & 0x1f00) >> 8;
2419 units = 1000000 / (1 << power); /* convert to uJ */
2420 power = I915_READ(MCH_SECP_NRG_STTS);
2421 power *= units;
2422
36623ef8
PZ		 2423 intel_runtime_pm_put(dev_priv);
2424
ec013e7f 2425 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2426
2427 return 0;
2428}
2429
2430static int i915_pc8_status(struct seq_file *m, void *unused)
2431{
9f25d007 2432 struct drm_info_node *node = m->private;
371db66a
PZ		 2433 struct drm_device *dev = node->minor->dev;
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435
85b8d5c2 2436 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2437 seq_puts(m, "not supported\n");
2438 return 0;
2439 }
2440
86c4ec0d 2441 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2442 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2443 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2444
ec013e7f
JB		 2445 return 0;
2446}
2447
1da51581
ID		 2448static const char *power_domain_str(enum intel_display_power_domain domain)
2449{
2450 switch (domain) {
2451 case POWER_DOMAIN_PIPE_A:
2452 return "PIPE_A";
2453 case POWER_DOMAIN_PIPE_B:
2454 return "PIPE_B";
2455 case POWER_DOMAIN_PIPE_C:
2456 return "PIPE_C";
2457 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2458 return "PIPE_A_PANEL_FITTER";
2459 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2460 return "PIPE_B_PANEL_FITTER";
2461 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2462 return "PIPE_C_PANEL_FITTER";
2463 case POWER_DOMAIN_TRANSCODER_A:
2464 return "TRANSCODER_A";
2465 case POWER_DOMAIN_TRANSCODER_B:
2466 return "TRANSCODER_B";
2467 case POWER_DOMAIN_TRANSCODER_C:
2468 return "TRANSCODER_C";
2469 case POWER_DOMAIN_TRANSCODER_EDP:
2470 return "TRANSCODER_EDP";
319be8ae
ID		 2471 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2472 return "PORT_DDI_A_2_LANES";
2473 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2474 return "PORT_DDI_A_4_LANES";
2475 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2476 return "PORT_DDI_B_2_LANES";
2477 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2478 return "PORT_DDI_B_4_LANES";
2479 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2480 return "PORT_DDI_C_2_LANES";
2481 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2482 return "PORT_DDI_C_4_LANES";
2483 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2484 return "PORT_DDI_D_2_LANES";
2485 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2486 return "PORT_DDI_D_4_LANES";
2487 case POWER_DOMAIN_PORT_DSI:
2488 return "PORT_DSI";
2489 case POWER_DOMAIN_PORT_CRT:
2490 return "PORT_CRT";
2491 case POWER_DOMAIN_PORT_OTHER:
2492 return "PORT_OTHER";
1da51581
ID		 2493 case POWER_DOMAIN_VGA:
2494 return "VGA";
2495 case POWER_DOMAIN_AUDIO:
2496 return "AUDIO";
bd2bb1b9
PZ		 2497 case POWER_DOMAIN_PLLS:
2498 return "PLLS";
1407121a
S		 2499 case POWER_DOMAIN_AUX_A:
2500 return "AUX_A";
2501 case POWER_DOMAIN_AUX_B:
2502 return "AUX_B";
2503 case POWER_DOMAIN_AUX_C:
2504 return "AUX_C";
2505 case POWER_DOMAIN_AUX_D:
2506 return "AUX_D";
1da51581
ID		 2507 case POWER_DOMAIN_INIT:
2508 return "INIT";
2509 default:
5f77eeb0 2510 MISSING_CASE(domain);
1da51581
ID		 2511 return "?";
2512 }
2513}
2514
2515static int i915_power_domain_info(struct seq_file *m, void *unused)
2516{
9f25d007 2517 struct drm_info_node *node = m->private;
1da51581
ID		 2518 struct drm_device *dev = node->minor->dev;
2519 struct drm_i915_private *dev_priv = dev->dev_private;
2520 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2521 int i;
2522
2523 mutex_lock(&power_domains->lock);
2524
2525 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2526 for (i = 0; i < power_domains->power_well_count; i++) {
2527 struct i915_power_well *power_well;
2528 enum intel_display_power_domain power_domain;
2529
2530 power_well = &power_domains->power_wells[i];
2531 seq_printf(m, "%-25s %d\n", power_well->name,
2532 power_well->count);
2533
2534 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2535 power_domain++) {
2536 if (!(BIT(power_domain) & power_well->domains))
2537 continue;
2538
2539 seq_printf(m, " %-23s %d\n",
2540 power_domain_str(power_domain),
2541 power_domains->domain_use_count[power_domain]);
2542 }
2543 }
2544
2545 mutex_unlock(&power_domains->lock);
2546
2547 return 0;
2548}
2549
53f5e3ca
JB		 2550static void intel_seq_print_mode(struct seq_file *m, int tabs,
2551 struct drm_display_mode *mode)
2552{
2553 int i;
2554
2555 for (i = 0; i < tabs; i++)
2556 seq_putc(m, '\t');
2557
2558 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2559 mode->base.id, mode->name,
2560 mode->vrefresh, mode->clock,
2561 mode->hdisplay, mode->hsync_start,
2562 mode->hsync_end, mode->htotal,
2563 mode->vdisplay, mode->vsync_start,
2564 mode->vsync_end, mode->vtotal,
2565 mode->type, mode->flags);
2566}
2567
2568static void intel_encoder_info(struct seq_file *m,
2569 struct intel_crtc *intel_crtc,
2570 struct intel_encoder *intel_encoder)
2571{
9f25d007 2572 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2573 struct drm_device *dev = node->minor->dev;
2574 struct drm_crtc *crtc = &intel_crtc->base;
2575 struct intel_connector *intel_connector;
2576 struct drm_encoder *encoder;
2577
2578 encoder = &intel_encoder->base;
2579 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2580 encoder->base.id, encoder->name);
53f5e3ca
JB		 2581 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2582 struct drm_connector *connector = &intel_connector->base;
2583 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2584 connector->base.id,
c23cc417 2585 connector->name,
53f5e3ca
JB		 2586 drm_get_connector_status_name(connector->status));
2587 if (connector->status == connector_status_connected) {
2588 struct drm_display_mode *mode = &crtc->mode;
2589 seq_printf(m, ", mode:\n");
2590 intel_seq_print_mode(m, 2, mode);
2591 } else {
2592 seq_putc(m, '\n');
2593 }
2594 }
2595}
2596
2597static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2598{
9f25d007 2599 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2600 struct drm_device *dev = node->minor->dev;
2601 struct drm_crtc *crtc = &intel_crtc->base;
2602 struct intel_encoder *intel_encoder;
2603
5aa8a937
MR		 2604 if (crtc->primary->fb)
2605 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2606 crtc->primary->fb->base.id, crtc->x, crtc->y,
2607 crtc->primary->fb->width, crtc->primary->fb->height);
2608 else
2609 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2610 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2611 intel_encoder_info(m, intel_crtc, intel_encoder);
2612}
2613
2614static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2615{
2616 struct drm_display_mode *mode = panel->fixed_mode;
2617
2618 seq_printf(m, "\tfixed mode:\n");
2619 intel_seq_print_mode(m, 2, mode);
2620}
2621
2622static void intel_dp_info(struct seq_file *m,
2623 struct intel_connector *intel_connector)
2624{
2625 struct intel_encoder *intel_encoder = intel_connector->encoder;
2626 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2627
2628 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2629 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2630 "no");
2631 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2632 intel_panel_info(m, &intel_connector->panel);
2633}
2634
2635static void intel_hdmi_info(struct seq_file *m,
2636 struct intel_connector *intel_connector)
2637{
2638 struct intel_encoder *intel_encoder = intel_connector->encoder;
2639 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2640
2641 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2642 "no");
2643}
2644
2645static void intel_lvds_info(struct seq_file *m,
2646 struct intel_connector *intel_connector)
2647{
2648 intel_panel_info(m, &intel_connector->panel);
2649}
2650
2651static void intel_connector_info(struct seq_file *m,
2652 struct drm_connector *connector)
2653{
2654 struct intel_connector *intel_connector = to_intel_connector(connector);
2655 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2656 struct drm_display_mode *mode;
53f5e3ca
JB		 2657
2658 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2659 connector->base.id, connector->name,
53f5e3ca
JB		 2660 drm_get_connector_status_name(connector->status));
2661 if (connector->status == connector_status_connected) {
2662 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2663 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2664 connector->display_info.width_mm,
2665 connector->display_info.height_mm);
2666 seq_printf(m, "\tsubpixel order: %s\n",
2667 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2668 seq_printf(m, "\tCEA rev: %d\n",
2669 connector->display_info.cea_rev);
2670 }
36cd7444
DA		 2671 if (intel_encoder) {
2672 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2673 intel_encoder->type == INTEL_OUTPUT_EDP)
2674 intel_dp_info(m, intel_connector);
2675 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2676 intel_hdmi_info(m, intel_connector);
2677 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2678 intel_lvds_info(m, intel_connector);
2679 }
53f5e3ca 2680
f103fc7d
JB		 2681 seq_printf(m, "\tmodes:\n");
2682 list_for_each_entry(mode, &connector->modes, head)
2683 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2684}
2685
065f2ec2
CW		 2686static bool cursor_active(struct drm_device *dev, int pipe)
2687{
2688 struct drm_i915_private *dev_priv = dev->dev_private;
2689 u32 state;
2690
2691 if (IS_845G(dev) || IS_I865G(dev))
2692 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2693 else
5efb3e28 2694 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2695
2696 return state;
2697}
2698
2699static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2700{
2701 struct drm_i915_private *dev_priv = dev->dev_private;
2702 u32 pos;
2703
5efb3e28 2704 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2705
2706 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2707 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2708 *x = -*x;
2709
2710 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2711 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2712 *y = -*y;
2713
2714 return cursor_active(dev, pipe);
2715}
2716
53f5e3ca
JB		 2717static int i915_display_info(struct seq_file *m, void *unused)
2718{
9f25d007 2719 struct drm_info_node *node = m->private;
53f5e3ca 2720 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2721 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2722 struct intel_crtc *crtc;
53f5e3ca
JB		 2723 struct drm_connector *connector;
2724
b0e5ddf3 2725 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2726 drm_modeset_lock_all(dev);
2727 seq_printf(m, "CRTC info\n");
2728 seq_printf(m, "---------\n");
d3fcc808 2729 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2730 bool active;
2731 int x, y;
53f5e3ca 2732
57127efa 2733 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2734 crtc->base.base.id, pipe_name(crtc->pipe),
6e3c9717
ACO		 2735 yesno(crtc->active), crtc->config->pipe_src_w,
2736 crtc->config->pipe_src_h);
a23dc658 2737 if (crtc->active) {
065f2ec2
CW		 2738 intel_crtc_info(m, crtc);
2739
a23dc658 2740 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2741 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2742 yesno(crtc->cursor_base),
3dd512fb
MR		 2743 x, y, crtc->base.cursor->state->crtc_w,
2744 crtc->base.cursor->state->crtc_h,
57127efa 2745 crtc->cursor_addr, yesno(active));
a23dc658 2746 }
cace841c
DV		 2747
2748 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2749 yesno(!crtc->cpu_fifo_underrun_disabled),
2750 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2751 }
2752
2753 seq_printf(m, "\n");
2754 seq_printf(m, "Connector info\n");
2755 seq_printf(m, "--------------\n");
2756 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2757 intel_connector_info(m, connector);
2758 }
2759 drm_modeset_unlock_all(dev);
b0e5ddf3 2760 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2761
2762 return 0;
2763}
2764
e04934cf
BW		 2765static int i915_semaphore_status(struct seq_file *m, void *unused)
2766{
2767 struct drm_info_node *node = (struct drm_info_node *) m->private;
2768 struct drm_device *dev = node->minor->dev;
2769 struct drm_i915_private *dev_priv = dev->dev_private;
2770 struct intel_engine_cs *ring;
2771 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2772 int i, j, ret;
2773
2774 if (!i915_semaphore_is_enabled(dev)) {
2775 seq_puts(m, "Semaphores are disabled\n");
2776 return 0;
2777 }
2778
2779 ret = mutex_lock_interruptible(&dev->struct_mutex);
2780 if (ret)
2781 return ret;
03872064 2782 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2783
2784 if (IS_BROADWELL(dev)) {
2785 struct page *page;
2786 uint64_t *seqno;
2787
2788 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2789
2790 seqno = (uint64_t *)kmap_atomic(page);
2791 for_each_ring(ring, dev_priv, i) {
2792 uint64_t offset;
2793
2794 seq_printf(m, "%s\n", ring->name);
2795
2796 seq_puts(m, " Last signal:");
2797 for (j = 0; j < num_rings; j++) {
2798 offset = i * I915_NUM_RINGS + j;
2799 seq_printf(m, "0x%08llx (0x%02llx) ",
2800 seqno[offset], offset * 8);
2801 }
2802 seq_putc(m, '\n');
2803
2804 seq_puts(m, " Last wait: ");
2805 for (j = 0; j < num_rings; j++) {
2806 offset = i + (j * I915_NUM_RINGS);
2807 seq_printf(m, "0x%08llx (0x%02llx) ",
2808 seqno[offset], offset * 8);
2809 }
2810 seq_putc(m, '\n');
2811
2812 }
2813 kunmap_atomic(seqno);
2814 } else {
2815 seq_puts(m, " Last signal:");
2816 for_each_ring(ring, dev_priv, i)
2817 for (j = 0; j < num_rings; j++)
2818 seq_printf(m, "0x%08x\n",
2819 I915_READ(ring->semaphore.mbox.signal[j]));
2820 seq_putc(m, '\n');
2821 }
2822
2823 seq_puts(m, "\nSync seqno:\n");
2824 for_each_ring(ring, dev_priv, i) {
2825 for (j = 0; j < num_rings; j++) {
2826 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2827 }
2828 seq_putc(m, '\n');
2829 }
2830 seq_putc(m, '\n');
2831
03872064 2832 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2833 mutex_unlock(&dev->struct_mutex);
2834 return 0;
2835}
2836
728e29d7
DV		 2837static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2838{
2839 struct drm_info_node *node = (struct drm_info_node *) m->private;
2840 struct drm_device *dev = node->minor->dev;
2841 struct drm_i915_private *dev_priv = dev->dev_private;
2842 int i;
2843
2844 drm_modeset_lock_all(dev);
2845 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2846 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2847
2848 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2849 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2850 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2851 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2852 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2853 seq_printf(m, " dpll_md: 0x%08x\n",
2854 pll->config.hw_state.dpll_md);
2855 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2856 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2857 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2858 }
2859 drm_modeset_unlock_all(dev);
2860
2861 return 0;
2862}
2863
1ed1ef9d 2864static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2865{
2866 int i;
2867 int ret;
2868 struct drm_info_node *node = (struct drm_info_node *) m->private;
2869 struct drm_device *dev = node->minor->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871
888b5995
AS		 2872 ret = mutex_lock_interruptible(&dev->struct_mutex);
2873 if (ret)
2874 return ret;
2875
2876 intel_runtime_pm_get(dev_priv);
2877
7225342a
MK		 2878 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2879 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2880 u32 addr, mask, value, read;
2881 bool ok;
888b5995 2882
7225342a
MK		 2883 addr = dev_priv->workarounds.reg[i].addr;
2884 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2885 value = dev_priv->workarounds.reg[i].value;
2886 read = I915_READ(addr);
2887 ok = (value & mask) == (read & mask);
2888 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2889 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2890 }
2891
2892 intel_runtime_pm_put(dev_priv);
2893 mutex_unlock(&dev->struct_mutex);
2894
2895 return 0;
2896}
2897
c5511e44
DL		 2898static int i915_ddb_info(struct seq_file *m, void *unused)
2899{
2900 struct drm_info_node *node = m->private;
2901 struct drm_device *dev = node->minor->dev;
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 struct skl_ddb_allocation *ddb;
2904 struct skl_ddb_entry *entry;
2905 enum pipe pipe;
2906 int plane;
2907
2fcffe19
DL		 2908 if (INTEL_INFO(dev)->gen < 9)
2909 return 0;
2910
c5511e44
DL		 2911 drm_modeset_lock_all(dev);
2912
2913 ddb = &dev_priv->wm.skl_hw.ddb;
2914
2915 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2916
2917 for_each_pipe(dev_priv, pipe) {
2918 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2919
dd740780 2920 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 2921 entry = &ddb->plane[pipe][plane];
2922 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2923 entry->start, entry->end,
2924 skl_ddb_entry_size(entry));
2925 }
2926
2927 entry = &ddb->cursor[pipe];
2928 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2929 entry->end, skl_ddb_entry_size(entry));
2930 }
2931
2932 drm_modeset_unlock_all(dev);
2933
2934 return 0;
2935}
2936
a54746e3
VK		 2937static void drrs_status_per_crtc(struct seq_file *m,
2938 struct drm_device *dev, struct intel_crtc *intel_crtc)
2939{
2940 struct intel_encoder *intel_encoder;
2941 struct drm_i915_private *dev_priv = dev->dev_private;
2942 struct i915_drrs *drrs = &dev_priv->drrs;
2943 int vrefresh = 0;
2944
2945 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
2946 /* Encoder connected on this CRTC */
2947 switch (intel_encoder->type) {
2948 case INTEL_OUTPUT_EDP:
2949 seq_puts(m, "eDP:\n");
2950 break;
2951 case INTEL_OUTPUT_DSI:
2952 seq_puts(m, "DSI:\n");
2953 break;
2954 case INTEL_OUTPUT_HDMI:
2955 seq_puts(m, "HDMI:\n");
2956 break;
2957 case INTEL_OUTPUT_DISPLAYPORT:
2958 seq_puts(m, "DP:\n");
2959 break;
2960 default:
2961 seq_printf(m, "Other encoder (id=%d).\n",
2962 intel_encoder->type);
2963 return;
2964 }
2965 }
2966
2967 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
2968 seq_puts(m, "\tVBT: DRRS_type: Static");
2969 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
2970 seq_puts(m, "\tVBT: DRRS_type: Seamless");
2971 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
2972 seq_puts(m, "\tVBT: DRRS_type: None");
2973 else
2974 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
2975
2976 seq_puts(m, "\n\n");
2977
2978 if (intel_crtc->config->has_drrs) {
2979 struct intel_panel *panel;
2980
2981 mutex_lock(&drrs->mutex);
2982 /* DRRS Supported */
2983 seq_puts(m, "\tDRRS Supported: Yes\n");
2984
2985 /* disable_drrs() will make drrs->dp NULL */
2986 if (!drrs->dp) {
2987 seq_puts(m, "Idleness DRRS: Disabled");
2988 mutex_unlock(&drrs->mutex);
2989 return;
2990 }
2991
2992 panel = &drrs->dp->attached_connector->panel;
2993 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
2994 drrs->busy_frontbuffer_bits);
2995
2996 seq_puts(m, "\n\t\t");
2997 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
2998 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
2999 vrefresh = panel->fixed_mode->vrefresh;
3000 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3001 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3002 vrefresh = panel->downclock_mode->vrefresh;
3003 } else {
3004 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3005 drrs->refresh_rate_type);
3006 mutex_unlock(&drrs->mutex);
3007 return;
3008 }
3009 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3010
3011 seq_puts(m, "\n\t\t");
3012 mutex_unlock(&drrs->mutex);
3013 } else {
3014 /* DRRS not supported. Print the VBT parameter*/
3015 seq_puts(m, "\tDRRS Supported : No");
3016 }
3017 seq_puts(m, "\n");
3018}
3019
3020static int i915_drrs_status(struct seq_file *m, void *unused)
3021{
3022 struct drm_info_node *node = m->private;
3023 struct drm_device *dev = node->minor->dev;
3024 struct intel_crtc *intel_crtc;
3025 int active_crtc_cnt = 0;
3026
3027 for_each_intel_crtc(dev, intel_crtc) {
3028 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3029
3030 if (intel_crtc->active) {
3031 active_crtc_cnt++;
3032 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3033
3034 drrs_status_per_crtc(m, dev, intel_crtc);
3035 }
3036
3037 drm_modeset_unlock(&intel_crtc->base.mutex);
3038 }
3039
3040 if (!active_crtc_cnt)
3041 seq_puts(m, "No active crtc found\n");
3042
3043 return 0;
3044}
3045
07144428
DL		 3046struct pipe_crc_info {
3047 const char *name;
3048 struct drm_device *dev;
3049 enum pipe pipe;
3050};
3051
11bed958
DA		 3052static int i915_dp_mst_info(struct seq_file *m, void *unused)
3053{
3054 struct drm_info_node *node = (struct drm_info_node *) m->private;
3055 struct drm_device *dev = node->minor->dev;
3056 struct drm_encoder *encoder;
3057 struct intel_encoder *intel_encoder;
3058 struct intel_digital_port *intel_dig_port;
3059 drm_modeset_lock_all(dev);
3060 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3061 intel_encoder = to_intel_encoder(encoder);
3062 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3063 continue;
3064 intel_dig_port = enc_to_dig_port(encoder);
3065 if (!intel_dig_port->dp.can_mst)
3066 continue;
3067
3068 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3069 }
3070 drm_modeset_unlock_all(dev);
3071 return 0;
3072}
3073
07144428
DL		 3074static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3075{
be5c7a90
DL		 3076 struct pipe_crc_info *info = inode->i_private;
3077 struct drm_i915_private *dev_priv = info->dev->dev_private;
3078 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3079
7eb1c496
DV		 3080 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3081 return -ENODEV;
3082
d538bbdf
DL		 3083 spin_lock_irq(&pipe_crc->lock);
3084
3085 if (pipe_crc->opened) {
3086 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3087 return -EBUSY; /* already open */
3088 }
3089
d538bbdf 3090 pipe_crc->opened = true;
07144428
DL		 3091 filep->private_data = inode->i_private;
3092
d538bbdf
DL		 3093 spin_unlock_irq(&pipe_crc->lock);
3094
07144428
DL		 3095 return 0;
3096}
3097
3098static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3099{
be5c7a90
DL		 3100 struct pipe_crc_info *info = inode->i_private;
3101 struct drm_i915_private *dev_priv = info->dev->dev_private;
3102 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3103
d538bbdf
DL		 3104 spin_lock_irq(&pipe_crc->lock);
3105 pipe_crc->opened = false;
3106 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3107
07144428
DL		 3108 return 0;
3109}
3110
3111/* (6 fields, 8 chars each, space separated (5) + '\n') */
3112#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3113/* account for \'0' */
3114#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3115
3116static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3117{
d538bbdf
DL		 3118 assert_spin_locked(&pipe_crc->lock);
3119 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3120 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3121}
3122
3123static ssize_t
3124i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3125 loff_t *pos)
3126{
3127 struct pipe_crc_info *info = filep->private_data;
3128 struct drm_device *dev = info->dev;
3129 struct drm_i915_private *dev_priv = dev->dev_private;
3130 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3131 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3132 int n_entries;
07144428
DL		 3133 ssize_t bytes_read;
3134
3135 /*
3136 * Don't allow user space to provide buffers not big enough to hold
3137 * a line of data.
3138 */
3139 if (count < PIPE_CRC_LINE_LEN)
3140 return -EINVAL;
3141
3142 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3143 return 0;
07144428
DL		 3144
3145 /* nothing to read */
d538bbdf 3146 spin_lock_irq(&pipe_crc->lock);
07144428 3147 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3148 int ret;
3149
3150 if (filep->f_flags & O_NONBLOCK) {
3151 spin_unlock_irq(&pipe_crc->lock);
07144428 3152 return -EAGAIN;
d538bbdf 3153 }
07144428 3154
d538bbdf
DL		 3155 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3156 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3157 if (ret) {
3158 spin_unlock_irq(&pipe_crc->lock);
3159 return ret;
3160 }
8bf1e9f1
SH		 3161 }
3162
07144428 3163 /* We now have one or more entries to read */
9ad6d99f 3164 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3165
07144428 3166 bytes_read = 0;
9ad6d99f
VS		 3167 while (n_entries > 0) {
3168 struct intel_pipe_crc_entry *entry =
3169 &pipe_crc->entries[pipe_crc->tail];
07144428 3170 int ret;
8bf1e9f1 3171
9ad6d99f
VS		 3172 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3173 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3174 break;
3175
3176 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3177 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3178
07144428
DL		 3179 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3180 "%8u %8x %8x %8x %8x %8x\n",
3181 entry->frame, entry->crc[0],
3182 entry->crc[1], entry->crc[2],
3183 entry->crc[3], entry->crc[4]);
3184
9ad6d99f
VS		 3185 spin_unlock_irq(&pipe_crc->lock);
3186
3187 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3188 if (ret == PIPE_CRC_LINE_LEN)
3189 return -EFAULT;
b2c88f5b 3190
9ad6d99f
VS		 3191 user_buf += PIPE_CRC_LINE_LEN;
3192 n_entries--;
3193
3194 spin_lock_irq(&pipe_crc->lock);
3195 }
8bf1e9f1 3196
d538bbdf
DL		 3197 spin_unlock_irq(&pipe_crc->lock);
3198
07144428
DL		 3199 return bytes_read;
3200}
3201
3202static const struct file_operations i915_pipe_crc_fops = {
3203 .owner = THIS_MODULE,
3204 .open = i915_pipe_crc_open,
3205 .read = i915_pipe_crc_read,
3206 .release = i915_pipe_crc_release,
3207};
3208
3209static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3210 {
3211 .name = "i915_pipe_A_crc",
3212 .pipe = PIPE_A,
3213 },
3214 {
3215 .name = "i915_pipe_B_crc",
3216 .pipe = PIPE_B,
3217 },
3218 {
3219 .name = "i915_pipe_C_crc",
3220 .pipe = PIPE_C,
3221 },
3222};
3223
3224static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3225 enum pipe pipe)
3226{
3227 struct drm_device *dev = minor->dev;
3228 struct dentry *ent;
3229 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3230
3231 info->dev = dev;
3232 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3233 &i915_pipe_crc_fops);
f3c5fe97
WY		 3234 if (!ent)
3235 return -ENOMEM;
07144428
DL		 3236
3237 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3238}
3239
e8dfcf78 3240static const char * const pipe_crc_sources[] = {
926321d5
DV		 3241 "none",
3242 "plane1",
3243 "plane2",
3244 "pf",
5b3a856b 3245 "pipe",
3d099a05
DV		 3246 "TV",
3247 "DP-B",
3248 "DP-C",
3249 "DP-D",
46a19188 3250 "auto",
926321d5
DV		 3251};
3252
3253static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3254{
3255 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3256 return pipe_crc_sources[source];
3257}
3258
bd9db02f 3259static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3260{
3261 struct drm_device *dev = m->private;
3262 struct drm_i915_private *dev_priv = dev->dev_private;
3263 int i;
3264
3265 for (i = 0; i < I915_MAX_PIPES; i++)
3266 seq_printf(m, "%c %s\n", pipe_name(i),
3267 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3268
3269 return 0;
3270}
3271
bd9db02f 3272static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3273{
3274 struct drm_device *dev = inode->i_private;
3275
bd9db02f 3276 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3277}
3278
46a19188 3279static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3280 uint32_t *val)
3281{
46a19188
DV		 3282 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3283 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3284
3285 switch (*source) {
52f843f6
DV		 3286 case INTEL_PIPE_CRC_SOURCE_PIPE:
3287 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3288 break;
3289 case INTEL_PIPE_CRC_SOURCE_NONE:
3290 *val = 0;
3291 break;
3292 default:
3293 return -EINVAL;
3294 }
3295
3296 return 0;
3297}
3298
46a19188
DV		 3299static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3300 enum intel_pipe_crc_source *source)
3301{
3302 struct intel_encoder *encoder;
3303 struct intel_crtc *crtc;
26756809 3304 struct intel_digital_port *dig_port;
46a19188
DV		 3305 int ret = 0;
3306
3307 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3308
6e9f798d 3309 drm_modeset_lock_all(dev);
b2784e15 3310 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3311 if (!encoder->base.crtc)
3312 continue;
3313
3314 crtc = to_intel_crtc(encoder->base.crtc);
3315
3316 if (crtc->pipe != pipe)
3317 continue;
3318
3319 switch (encoder->type) {
3320 case INTEL_OUTPUT_TVOUT:
3321 *source = INTEL_PIPE_CRC_SOURCE_TV;
3322 break;
3323 case INTEL_OUTPUT_DISPLAYPORT:
3324 case INTEL_OUTPUT_EDP:
26756809
DV		 3325 dig_port = enc_to_dig_port(&encoder->base);
3326 switch (dig_port->port) {
3327 case PORT_B:
3328 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3329 break;
3330 case PORT_C:
3331 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3332 break;
3333 case PORT_D:
3334 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3335 break;
3336 default:
3337 WARN(1, "nonexisting DP port %c\n",
3338 port_name(dig_port->port));
3339 break;
3340 }
46a19188 3341 break;
6847d71b
PZ		 3342 default:
3343 break;
46a19188
DV		 3344 }
3345 }
6e9f798d 3346 drm_modeset_unlock_all(dev);
46a19188
DV		 3347
3348 return ret;
3349}
3350
3351static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3352 enum pipe pipe,
3353 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3354 uint32_t *val)
3355{
8d2f24ca
DV		 3356 struct drm_i915_private *dev_priv = dev->dev_private;
3357 bool need_stable_symbols = false;
3358
46a19188
DV		 3359 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3360 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3361 if (ret)
3362 return ret;
3363 }
3364
3365 switch (*source) {
7ac0129b
DV		 3366 case INTEL_PIPE_CRC_SOURCE_PIPE:
3367 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3368 break;
3369 case INTEL_PIPE_CRC_SOURCE_DP_B:
3370 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3371 need_stable_symbols = true;
7ac0129b
DV		 3372 break;
3373 case INTEL_PIPE_CRC_SOURCE_DP_C:
3374 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3375 need_stable_symbols = true;
7ac0129b 3376 break;
2be57922
VS		 3377 case INTEL_PIPE_CRC_SOURCE_DP_D:
3378 if (!IS_CHERRYVIEW(dev))
3379 return -EINVAL;
3380 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3381 need_stable_symbols = true;
3382 break;
7ac0129b
DV		 3383 case INTEL_PIPE_CRC_SOURCE_NONE:
3384 *val = 0;
3385 break;
3386 default:
3387 return -EINVAL;
3388 }
3389
8d2f24ca
DV		 3390 /*
3391 * When the pipe CRC tap point is after the transcoders we need
3392 * to tweak symbol-level features to produce a deterministic series of
3393 * symbols for a given frame. We need to reset those features only once
3394 * a frame (instead of every nth symbol):
3395 * - DC-balance: used to ensure a better clock recovery from the data
3396 * link (SDVO)
3397 * - DisplayPort scrambling: used for EMI reduction
3398 */
3399 if (need_stable_symbols) {
3400 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3401
8d2f24ca 3402 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3403 switch (pipe) {
3404 case PIPE_A:
8d2f24ca 3405 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3406 break;
3407 case PIPE_B:
8d2f24ca 3408 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3409 break;
3410 case PIPE_C:
3411 tmp |= PIPE_C_SCRAMBLE_RESET;
3412 break;
3413 default:
3414 return -EINVAL;
3415 }
8d2f24ca
DV		 3416 I915_WRITE(PORT_DFT2_G4X, tmp);
3417 }
3418
7ac0129b
DV		 3419 return 0;
3420}
3421
4b79ebf7 3422static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3423 enum pipe pipe,
3424 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3425 uint32_t *val)
3426{
84093603
DV		 3427 struct drm_i915_private *dev_priv = dev->dev_private;
3428 bool need_stable_symbols = false;
3429
46a19188
DV		 3430 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3431 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3432 if (ret)
3433 return ret;
3434 }
3435
3436 switch (*source) {
4b79ebf7
DV		 3437 case INTEL_PIPE_CRC_SOURCE_PIPE:
3438 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3439 break;
3440 case INTEL_PIPE_CRC_SOURCE_TV:
3441 if (!SUPPORTS_TV(dev))
3442 return -EINVAL;
3443 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3444 break;
3445 case INTEL_PIPE_CRC_SOURCE_DP_B:
3446 if (!IS_G4X(dev))
3447 return -EINVAL;
3448 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3449 need_stable_symbols = true;
4b79ebf7
DV		 3450 break;
3451 case INTEL_PIPE_CRC_SOURCE_DP_C:
3452 if (!IS_G4X(dev))
3453 return -EINVAL;
3454 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3455 need_stable_symbols = true;
4b79ebf7
DV		 3456 break;
3457 case INTEL_PIPE_CRC_SOURCE_DP_D:
3458 if (!IS_G4X(dev))
3459 return -EINVAL;
3460 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3461 need_stable_symbols = true;
4b79ebf7
DV		 3462 break;
3463 case INTEL_PIPE_CRC_SOURCE_NONE:
3464 *val = 0;
3465 break;
3466 default:
3467 return -EINVAL;
3468 }
3469
84093603
DV		 3470 /*
3471 * When the pipe CRC tap point is after the transcoders we need
3472 * to tweak symbol-level features to produce a deterministic series of
3473 * symbols for a given frame. We need to reset those features only once
3474 * a frame (instead of every nth symbol):
3475 * - DC-balance: used to ensure a better clock recovery from the data
3476 * link (SDVO)
3477 * - DisplayPort scrambling: used for EMI reduction
3478 */
3479 if (need_stable_symbols) {
3480 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3481
3482 WARN_ON(!IS_G4X(dev));
3483
3484 I915_WRITE(PORT_DFT_I9XX,
3485 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3486
3487 if (pipe == PIPE_A)
3488 tmp |= PIPE_A_SCRAMBLE_RESET;
3489 else
3490 tmp |= PIPE_B_SCRAMBLE_RESET;
3491
3492 I915_WRITE(PORT_DFT2_G4X, tmp);
3493 }
3494
4b79ebf7
DV		 3495 return 0;
3496}
3497
8d2f24ca
DV		 3498static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3499 enum pipe pipe)
3500{
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3502 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3503
eb736679
VS		 3504 switch (pipe) {
3505 case PIPE_A:
8d2f24ca 3506 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3507 break;
3508 case PIPE_B:
8d2f24ca 3509 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3510 break;
3511 case PIPE_C:
3512 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3513 break;
3514 default:
3515 return;
3516 }
8d2f24ca
DV		 3517 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3518 tmp &= ~DC_BALANCE_RESET_VLV;
3519 I915_WRITE(PORT_DFT2_G4X, tmp);
3520
3521}
3522
84093603
DV		 3523static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3524 enum pipe pipe)
3525{
3526 struct drm_i915_private *dev_priv = dev->dev_private;
3527 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3528
3529 if (pipe == PIPE_A)
3530 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3531 else
3532 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3533 I915_WRITE(PORT_DFT2_G4X, tmp);
3534
3535 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3536 I915_WRITE(PORT_DFT_I9XX,
3537 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3538 }
3539}
3540
46a19188 3541static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3542 uint32_t *val)
3543{
46a19188
DV		 3544 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3545 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3546
3547 switch (*source) {
5b3a856b
DV		 3548 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3549 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3550 break;
3551 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3552 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3553 break;
5b3a856b
DV		 3554 case INTEL_PIPE_CRC_SOURCE_PIPE:
3555 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3556 break;
3d099a05 3557 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3558 *val = 0;
3559 break;
3d099a05
DV		 3560 default:
3561 return -EINVAL;
5b3a856b
DV		 3562 }
3563
3564 return 0;
3565}
3566
fabf6e51
DV		 3567static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3568{
3569 struct drm_i915_private *dev_priv = dev->dev_private;
3570 struct intel_crtc *crtc =
3571 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3572
3573 drm_modeset_lock_all(dev);
3574 /*
3575 * If we use the eDP transcoder we need to make sure that we don't
3576 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3577 * relevant on hsw with pipe A when using the always-on power well
3578 * routing.
3579 */
6e3c9717
ACO		 3580 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3581 !crtc->config->pch_pfit.enabled) {
3582 crtc->config->pch_pfit.force_thru = true;
fabf6e51
DV		 3583
3584 intel_display_power_get(dev_priv,
3585 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3586
3587 dev_priv->display.crtc_disable(&crtc->base);
3588 dev_priv->display.crtc_enable(&crtc->base);
3589 }
3590 drm_modeset_unlock_all(dev);
3591}
3592
3593static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3594{
3595 struct drm_i915_private *dev_priv = dev->dev_private;
3596 struct intel_crtc *crtc =
3597 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3598
3599 drm_modeset_lock_all(dev);
3600 /*
3601 * If we use the eDP transcoder we need to make sure that we don't
3602 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3603 * relevant on hsw with pipe A when using the always-on power well
3604 * routing.
3605 */
6e3c9717
ACO		 3606 if (crtc->config->pch_pfit.force_thru) {
3607 crtc->config->pch_pfit.force_thru = false;
fabf6e51
DV		 3608
3609 dev_priv->display.crtc_disable(&crtc->base);
3610 dev_priv->display.crtc_enable(&crtc->base);
3611
3612 intel_display_power_put(dev_priv,
3613 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3614 }
3615 drm_modeset_unlock_all(dev);
3616}
3617
3618static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3619 enum pipe pipe,
3620 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3621 uint32_t *val)
3622{
46a19188
DV		 3623 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3624 *source = INTEL_PIPE_CRC_SOURCE_PF;
3625
3626 switch (*source) {
5b3a856b
DV		 3627 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3628 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3629 break;
3630 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3631 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3632 break;
3633 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3634 if (IS_HASWELL(dev) && pipe == PIPE_A)
3635 hsw_trans_edp_pipe_A_crc_wa(dev);
3636
5b3a856b
DV		 3637 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3638 break;
3d099a05 3639 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3640 *val = 0;
3641 break;
3d099a05
DV		 3642 default:
3643 return -EINVAL;
5b3a856b
DV		 3644 }
3645
3646 return 0;
3647}
3648
926321d5
DV		 3649static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3650 enum intel_pipe_crc_source source)
3651{
3652 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3653 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3654 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3655 pipe));
432f3342 3656 u32 val = 0; /* shut up gcc */
5b3a856b 3657 int ret;
926321d5 3658
cc3da175
DL		 3659 if (pipe_crc->source == source)
3660 return 0;
3661
ae676fcd
DL		 3662 /* forbid changing the source without going back to 'none' */
3663 if (pipe_crc->source && source)
3664 return -EINVAL;
3665
9d8b0588
DV		 3666 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3667 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3668 return -EIO;
3669 }
3670
52f843f6 3671 if (IS_GEN2(dev))
46a19188 3672 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3673 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3674 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3675 else if (IS_VALLEYVIEW(dev))
fabf6e51 3676 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3677 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3678 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3679 else
fabf6e51 3680 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3681
3682 if (ret != 0)
3683 return ret;
3684
4b584369
DL		 3685 /* none -> real source transition */
3686 if (source) {
4252fbc3
VS		 3687 struct intel_pipe_crc_entry *entries;
3688
7cd6ccff
DL		 3689 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3690 pipe_name(pipe), pipe_crc_source_name(source));
3691
3cf54b34
VS		 3692 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3693 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3694 GFP_KERNEL);
3695 if (!entries)
e5f75aca
DL		 3696 return -ENOMEM;
3697
8c740dce
PZ		 3698 /*
3699 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3700 * enabled and disabled dynamically based on package C states,
3701 * user space can't make reliable use of the CRCs, so let's just
3702 * completely disable it.
3703 */
3704 hsw_disable_ips(crtc);
3705
d538bbdf 3706 spin_lock_irq(&pipe_crc->lock);
64387b61 3707 kfree(pipe_crc->entries);
4252fbc3 3708 pipe_crc->entries = entries;
d538bbdf
DL		 3709 pipe_crc->head = 0;
3710 pipe_crc->tail = 0;
3711 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3712 }
3713
cc3da175 3714 pipe_crc->source = source;
926321d5 3715
926321d5
DV		 3716 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3717 POSTING_READ(PIPE_CRC_CTL(pipe));
3718
e5f75aca
DL		 3719 /* real source -> none transition */
3720 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3721 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3722 struct intel_crtc *crtc =
3723 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3724
7cd6ccff
DL		 3725 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3726 pipe_name(pipe));
3727
a33d7105
DV		 3728 drm_modeset_lock(&crtc->base.mutex, NULL);
3729 if (crtc->active)
3730 intel_wait_for_vblank(dev, pipe);
3731 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3732
d538bbdf
DL		 3733 spin_lock_irq(&pipe_crc->lock);
3734 entries = pipe_crc->entries;
e5f75aca 3735 pipe_crc->entries = NULL;
9ad6d99f
VS		 3736 pipe_crc->head = 0;
3737 pipe_crc->tail = 0;
d538bbdf
DL		 3738 spin_unlock_irq(&pipe_crc->lock);
3739
3740 kfree(entries);
84093603
DV		 3741
3742 if (IS_G4X(dev))
3743 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3744 else if (IS_VALLEYVIEW(dev))
3745 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3746 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3747 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3748
3749 hsw_enable_ips(crtc);
e5f75aca
DL		 3750 }
3751
926321d5
DV		 3752 return 0;
3753}
3754
3755/*
3756 * Parse pipe CRC command strings:
b94dec87
DL		 3757 * command: wsp* object wsp+ name wsp+ source wsp*
3758 * object: 'pipe'
3759 * name: (A | B | C)
926321d5
DV		 3760 * source: (none | plane1 | plane2 | pf)
3761 * wsp: (#0x20 | #0x9 | #0xA)+
3762 *
3763 * eg.:
b94dec87
DL		 3764 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3765 * "pipe A none" -> Stop CRC
926321d5 3766 */
bd9db02f 3767static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3768{
3769 int n_words = 0;
3770
3771 while (*buf) {
3772 char *end;
3773
3774 /* skip leading white space */
3775 buf = skip_spaces(buf);
3776 if (!*buf)
3777 break; /* end of buffer */
3778
3779 /* find end of word */
3780 for (end = buf; *end && !isspace(*end); end++)
3781 ;
3782
3783 if (n_words == max_words) {
3784 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3785 max_words);
3786 return -EINVAL; /* ran out of words[] before bytes */
3787 }
3788
3789 if (*end)
3790 *end++ = '\0';
3791 words[n_words++] = buf;
3792 buf = end;
3793 }
3794
3795 return n_words;
3796}
3797
b94dec87
DL		 3798enum intel_pipe_crc_object {
3799 PIPE_CRC_OBJECT_PIPE,
3800};
3801
e8dfcf78 3802static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3803 "pipe",
3804};
3805
3806static int
bd9db02f 3807display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3808{
3809 int i;
3810
3811 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3812 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3813 *o = i;
b94dec87
DL		 3814 return 0;
3815 }
3816
3817 return -EINVAL;
3818}
3819
bd9db02f 3820static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3821{
3822 const char name = buf[0];
3823
3824 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3825 return -EINVAL;
3826
3827 *pipe = name - 'A';
3828
3829 return 0;
3830}
3831
3832static int
bd9db02f 3833display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3834{
3835 int i;
3836
3837 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3838 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3839 *s = i;
926321d5
DV		 3840 return 0;
3841 }
3842
3843 return -EINVAL;
3844}
3845
bd9db02f 3846static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3847{
b94dec87 3848#define N_WORDS 3
926321d5 3849 int n_words;
b94dec87 3850 char *words[N_WORDS];
926321d5 3851 enum pipe pipe;
b94dec87 3852 enum intel_pipe_crc_object object;
926321d5
DV		 3853 enum intel_pipe_crc_source source;
3854
bd9db02f 3855 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3856 if (n_words != N_WORDS) {
3857 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3858 N_WORDS);
3859 return -EINVAL;
3860 }
3861
bd9db02f 3862 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3863 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3864 return -EINVAL;
3865 }
3866
bd9db02f 3867 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3868 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3869 return -EINVAL;
3870 }
3871
bd9db02f 3872 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3873 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3874 return -EINVAL;
3875 }
3876
3877 return pipe_crc_set_source(dev, pipe, source);
3878}
3879
bd9db02f
DL		 3880static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3881 size_t len, loff_t *offp)
926321d5
DV		 3882{
3883 struct seq_file *m = file->private_data;
3884 struct drm_device *dev = m->private;
3885 char *tmpbuf;
3886 int ret;
3887
3888 if (len == 0)
3889 return 0;
3890
3891 if (len > PAGE_SIZE - 1) {
3892 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3893 PAGE_SIZE);
3894 return -E2BIG;
3895 }
3896
3897 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3898 if (!tmpbuf)
3899 return -ENOMEM;
3900
3901 if (copy_from_user(tmpbuf, ubuf, len)) {
3902 ret = -EFAULT;
3903 goto out;
3904 }
3905 tmpbuf[len] = '\0';
3906
bd9db02f 3907 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3908
3909out:
3910 kfree(tmpbuf);
3911 if (ret < 0)
3912 return ret;
3913
3914 *offp += len;
3915 return len;
3916}
3917
bd9db02f 3918static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3919 .owner = THIS_MODULE,
bd9db02f 3920 .open = display_crc_ctl_open,
926321d5
DV		 3921 .read = seq_read,
3922 .llseek = seq_lseek,
3923 .release = single_release,
bd9db02f 3924 .write = display_crc_ctl_write
926321d5
DV		 3925};
3926
97e94b22 3927static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3928{
3929 struct drm_device *dev = m->private;
546c81fd 3930 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3931 int level;
3932
3933 drm_modeset_lock_all(dev);
3934
3935 for (level = 0; level < num_levels; level++) {
3936 unsigned int latency = wm[level];
3937
97e94b22
DL		 3938 /*
3939 * - WM1+ latency values in 0.5us units
3940 * - latencies are in us on gen9
3941 */
3942 if (INTEL_INFO(dev)->gen >= 9)
3943 latency *= 10;
3944 else if (level > 0)
369a1342
VS		 3945 latency *= 5;
3946
3947 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3948 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3949 }
3950
3951 drm_modeset_unlock_all(dev);
3952}
3953
3954static int pri_wm_latency_show(struct seq_file *m, void *data)
3955{
3956 struct drm_device *dev = m->private;
97e94b22
DL		 3957 struct drm_i915_private *dev_priv = dev->dev_private;
3958 const uint16_t *latencies;
3959
3960 if (INTEL_INFO(dev)->gen >= 9)
3961 latencies = dev_priv->wm.skl_latency;
3962 else
3963 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3964
97e94b22 3965 wm_latency_show(m, latencies);
369a1342
VS		 3966
3967 return 0;
3968}
3969
3970static int spr_wm_latency_show(struct seq_file *m, void *data)
3971{
3972 struct drm_device *dev = m->private;
97e94b22
DL		 3973 struct drm_i915_private *dev_priv = dev->dev_private;
3974 const uint16_t *latencies;
3975
3976 if (INTEL_INFO(dev)->gen >= 9)
3977 latencies = dev_priv->wm.skl_latency;
3978 else
3979 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3980
97e94b22 3981 wm_latency_show(m, latencies);
369a1342
VS		 3982
3983 return 0;
3984}
3985
3986static int cur_wm_latency_show(struct seq_file *m, void *data)
3987{
3988 struct drm_device *dev = m->private;
97e94b22
DL		 3989 struct drm_i915_private *dev_priv = dev->dev_private;
3990 const uint16_t *latencies;
3991
3992 if (INTEL_INFO(dev)->gen >= 9)
3993 latencies = dev_priv->wm.skl_latency;
3994 else
3995 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3996
97e94b22 3997 wm_latency_show(m, latencies);
369a1342
VS		 3998
3999 return 0;
4000}
4001
4002static int pri_wm_latency_open(struct inode *inode, struct file *file)
4003{
4004 struct drm_device *dev = inode->i_private;
4005
9ad0257c 4006 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4007 return -ENODEV;
4008
4009 return single_open(file, pri_wm_latency_show, dev);
4010}
4011
4012static int spr_wm_latency_open(struct inode *inode, struct file *file)
4013{
4014 struct drm_device *dev = inode->i_private;
4015
9ad0257c 4016 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4017 return -ENODEV;
4018
4019 return single_open(file, spr_wm_latency_show, dev);
4020}
4021
4022static int cur_wm_latency_open(struct inode *inode, struct file *file)
4023{
4024 struct drm_device *dev = inode->i_private;
4025
9ad0257c 4026 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4027 return -ENODEV;
4028
4029 return single_open(file, cur_wm_latency_show, dev);
4030}
4031
4032static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4033 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4034{
4035 struct seq_file *m = file->private_data;
4036 struct drm_device *dev = m->private;
97e94b22 4037 uint16_t new[8] = { 0 };
546c81fd 4038 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4039 int level;
4040 int ret;
4041 char tmp[32];
4042
4043 if (len >= sizeof(tmp))
4044 return -EINVAL;
4045
4046 if (copy_from_user(tmp, ubuf, len))
4047 return -EFAULT;
4048
4049 tmp[len] = '\0';
4050
97e94b22
DL		 4051 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4052 &new[0], &new[1], &new[2], &new[3],
4053 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4054 if (ret != num_levels)
4055 return -EINVAL;
4056
4057 drm_modeset_lock_all(dev);
4058
4059 for (level = 0; level < num_levels; level++)
4060 wm[level] = new[level];
4061
4062 drm_modeset_unlock_all(dev);
4063
4064 return len;
4065}
4066
4067
4068static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4069 size_t len, loff_t *offp)
4070{
4071 struct seq_file *m = file->private_data;
4072 struct drm_device *dev = m->private;
97e94b22
DL		 4073 struct drm_i915_private *dev_priv = dev->dev_private;
4074 uint16_t *latencies;
369a1342 4075
97e94b22
DL		 4076 if (INTEL_INFO(dev)->gen >= 9)
4077 latencies = dev_priv->wm.skl_latency;
4078 else
4079 latencies = to_i915(dev)->wm.pri_latency;
4080
4081 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4082}
4083
4084static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4085 size_t len, loff_t *offp)
4086{
4087 struct seq_file *m = file->private_data;
4088 struct drm_device *dev = m->private;
97e94b22
DL		 4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 uint16_t *latencies;
369a1342 4091
97e94b22
DL		 4092 if (INTEL_INFO(dev)->gen >= 9)
4093 latencies = dev_priv->wm.skl_latency;
4094 else
4095 latencies = to_i915(dev)->wm.spr_latency;
4096
4097 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4098}
4099
4100static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4101 size_t len, loff_t *offp)
4102{
4103 struct seq_file *m = file->private_data;
4104 struct drm_device *dev = m->private;
97e94b22
DL		 4105 struct drm_i915_private *dev_priv = dev->dev_private;
4106 uint16_t *latencies;
4107
4108 if (INTEL_INFO(dev)->gen >= 9)
4109 latencies = dev_priv->wm.skl_latency;
4110 else
4111 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4112
97e94b22 4113 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4114}
4115
4116static const struct file_operations i915_pri_wm_latency_fops = {
4117 .owner = THIS_MODULE,
4118 .open = pri_wm_latency_open,
4119 .read = seq_read,
4120 .llseek = seq_lseek,
4121 .release = single_release,
4122 .write = pri_wm_latency_write
4123};
4124
4125static const struct file_operations i915_spr_wm_latency_fops = {
4126 .owner = THIS_MODULE,
4127 .open = spr_wm_latency_open,
4128 .read = seq_read,
4129 .llseek = seq_lseek,
4130 .release = single_release,
4131 .write = spr_wm_latency_write
4132};
4133
4134static const struct file_operations i915_cur_wm_latency_fops = {
4135 .owner = THIS_MODULE,
4136 .open = cur_wm_latency_open,
4137 .read = seq_read,
4138 .llseek = seq_lseek,
4139 .release = single_release,
4140 .write = cur_wm_latency_write
4141};
4142
647416f9
KC		 4143static int
4144i915_wedged_get(void *data, u64 *val)
f3cd474b 4145{
647416f9 4146 struct drm_device *dev = data;
e277a1f8 4147 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4148
647416f9 4149 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4150
647416f9 4151 return 0;
f3cd474b
CW		 4152}
4153
647416f9
KC		 4154static int
4155i915_wedged_set(void *data, u64 val)
f3cd474b 4156{
647416f9 4157 struct drm_device *dev = data;
d46c0517
ID		 4158 struct drm_i915_private *dev_priv = dev->dev_private;
4159
b8d24a06
MK		 4160 /*
4161 * There is no safeguard against this debugfs entry colliding
4162 * with the hangcheck calling same i915_handle_error() in
4163 * parallel, causing an explosion. For now we assume that the
4164 * test harness is responsible enough not to inject gpu hangs
4165 * while it is writing to 'i915_wedged'
4166 */
4167
4168 if (i915_reset_in_progress(&dev_priv->gpu_error))
4169 return -EAGAIN;
4170
d46c0517 4171 intel_runtime_pm_get(dev_priv);
f3cd474b 4172
58174462
MK		 4173 i915_handle_error(dev, val,
4174 "Manually setting wedged to %llu", val);
d46c0517
ID		 4175
4176 intel_runtime_pm_put(dev_priv);
4177
647416f9 4178 return 0;
f3cd474b
CW		 4179}
4180
647416f9
KC		 4181DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4182 i915_wedged_get, i915_wedged_set,
3a3b4f98 4183 "%llu\n");
f3cd474b 4184
647416f9
KC		 4185static int
4186i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4187{
647416f9 4188 struct drm_device *dev = data;
e277a1f8 4189 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4190
647416f9 4191 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4192
647416f9 4193 return 0;
e5eb3d63
DV		 4194}
4195
647416f9
KC		 4196static int
4197i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4198{
647416f9 4199 struct drm_device *dev = data;
e5eb3d63 4200 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4201 int ret;
e5eb3d63 4202
647416f9 4203 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4204
22bcfc6a
DV		 4205 ret = mutex_lock_interruptible(&dev->struct_mutex);
4206 if (ret)
4207 return ret;
4208
99584db3 4209 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4210 mutex_unlock(&dev->struct_mutex);
4211
647416f9 4212 return 0;
e5eb3d63
DV		 4213}
4214
647416f9
KC		 4215DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4216 i915_ring_stop_get, i915_ring_stop_set,
4217 "0x%08llx\n");
d5442303 4218
094f9a54
CW		 4219static int
4220i915_ring_missed_irq_get(void *data, u64 *val)
4221{
4222 struct drm_device *dev = data;
4223 struct drm_i915_private *dev_priv = dev->dev_private;
4224
4225 *val = dev_priv->gpu_error.missed_irq_rings;
4226 return 0;
4227}
4228
4229static int
4230i915_ring_missed_irq_set(void *data, u64 val)
4231{
4232 struct drm_device *dev = data;
4233 struct drm_i915_private *dev_priv = dev->dev_private;
4234 int ret;
4235
4236 /* Lock against concurrent debugfs callers */
4237 ret = mutex_lock_interruptible(&dev->struct_mutex);
4238 if (ret)
4239 return ret;
4240 dev_priv->gpu_error.missed_irq_rings = val;
4241 mutex_unlock(&dev->struct_mutex);
4242
4243 return 0;
4244}
4245
4246DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4247 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4248 "0x%08llx\n");
4249
4250static int
4251i915_ring_test_irq_get(void *data, u64 *val)
4252{
4253 struct drm_device *dev = data;
4254 struct drm_i915_private *dev_priv = dev->dev_private;
4255
4256 *val = dev_priv->gpu_error.test_irq_rings;
4257
4258 return 0;
4259}
4260
4261static int
4262i915_ring_test_irq_set(void *data, u64 val)
4263{
4264 struct drm_device *dev = data;
4265 struct drm_i915_private *dev_priv = dev->dev_private;
4266 int ret;
4267
4268 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4269
4270 /* Lock against concurrent debugfs callers */
4271 ret = mutex_lock_interruptible(&dev->struct_mutex);
4272 if (ret)
4273 return ret;
4274
4275 dev_priv->gpu_error.test_irq_rings = val;
4276 mutex_unlock(&dev->struct_mutex);
4277
4278 return 0;
4279}
4280
4281DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4282 i915_ring_test_irq_get, i915_ring_test_irq_set,
4283 "0x%08llx\n");
4284
dd624afd
CW		 4285#define DROP_UNBOUND 0x1
4286#define DROP_BOUND 0x2
4287#define DROP_RETIRE 0x4
4288#define DROP_ACTIVE 0x8
4289#define DROP_ALL (DROP_UNBOUND | \
4290 DROP_BOUND | \
4291 DROP_RETIRE | \
4292 DROP_ACTIVE)
647416f9
KC		 4293static int
4294i915_drop_caches_get(void *data, u64 *val)
dd624afd 4295{
647416f9 4296 *val = DROP_ALL;
dd624afd 4297
647416f9 4298 return 0;
dd624afd
CW		 4299}
4300
647416f9
KC		 4301static int
4302i915_drop_caches_set(void *data, u64 val)
dd624afd 4303{
647416f9 4304 struct drm_device *dev = data;
dd624afd 4305 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4306 int ret;
dd624afd 4307
2f9fe5ff 4308 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4309
4310 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4311 * on ioctls on -EAGAIN. */
4312 ret = mutex_lock_interruptible(&dev->struct_mutex);
4313 if (ret)
4314 return ret;
4315
4316 if (val & DROP_ACTIVE) {
4317 ret = i915_gpu_idle(dev);
4318 if (ret)
4319 goto unlock;
4320 }
4321
4322 if (val & (DROP_RETIRE | DROP_ACTIVE))
4323 i915_gem_retire_requests(dev);
4324
21ab4e74
CW		 4325 if (val & DROP_BOUND)
4326 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4327
21ab4e74
CW		 4328 if (val & DROP_UNBOUND)
4329 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4330
4331unlock:
4332 mutex_unlock(&dev->struct_mutex);
4333
647416f9 4334 return ret;
dd624afd
CW		 4335}
4336
647416f9
KC		 4337DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4338 i915_drop_caches_get, i915_drop_caches_set,
4339 "0x%08llx\n");
dd624afd 4340
647416f9
KC		 4341static int
4342i915_max_freq_get(void *data, u64 *val)
358733e9 4343{
647416f9 4344 struct drm_device *dev = data;
e277a1f8 4345 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4346 int ret;
004777cb 4347
daa3afb2 4348 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4349 return -ENODEV;
4350
5c9669ce
TR		 4351 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4352
4fc688ce 4353 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4354 if (ret)
4355 return ret;
358733e9 4356
7c59a9c1 4357 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4358 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4359
647416f9 4360 return 0;
358733e9
JB		 4361}
4362
647416f9
KC		 4363static int
4364i915_max_freq_set(void *data, u64 val)
358733e9 4365{
647416f9 4366 struct drm_device *dev = data;
358733e9 4367 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4368 u32 hw_max, hw_min;
647416f9 4369 int ret;
004777cb 4370
daa3afb2 4371 if (INTEL_INFO(dev)->gen < 6)
004777cb 4372 return -ENODEV;
358733e9 4373
5c9669ce
TR		 4374 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4375
647416f9 4376 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4377
4fc688ce 4378 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4379 if (ret)
4380 return ret;
4381
358733e9
JB		 4382 /*
4383 * Turbo will still be enabled, but won't go above the set value.
4384 */
bc4d91f6 4385 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4386
bc4d91f6
AG		 4387 hw_max = dev_priv->rps.max_freq;
4388 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4389
b39fb297 4390 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4391 mutex_unlock(&dev_priv->rps.hw_lock);
4392 return -EINVAL;
0a073b84
JB		 4393 }
4394
b39fb297 4395 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4396
ffe02b40 4397 intel_set_rps(dev, val);
dd0a1aa1 4398
4fc688ce 4399 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4400
647416f9 4401 return 0;
358733e9
JB		 4402}
4403
647416f9
KC		 4404DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4405 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4406 "%llu\n");
358733e9 4407
647416f9
KC		 4408static int
4409i915_min_freq_get(void *data, u64 *val)
1523c310 4410{
647416f9 4411 struct drm_device *dev = data;
e277a1f8 4412 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4413 int ret;
004777cb 4414
daa3afb2 4415 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4416 return -ENODEV;
4417
5c9669ce
TR		 4418 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4419
4fc688ce 4420 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4421 if (ret)
4422 return ret;
1523c310 4423
7c59a9c1 4424 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4425 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4426
647416f9 4427 return 0;
1523c310
JB		 4428}
4429
647416f9
KC		 4430static int
4431i915_min_freq_set(void *data, u64 val)
1523c310 4432{
647416f9 4433 struct drm_device *dev = data;
1523c310 4434 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4435 u32 hw_max, hw_min;
647416f9 4436 int ret;
004777cb 4437
daa3afb2 4438 if (INTEL_INFO(dev)->gen < 6)
004777cb 4439 return -ENODEV;
1523c310 4440
5c9669ce
TR		 4441 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4442
647416f9 4443 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4444
4fc688ce 4445 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4446 if (ret)
4447 return ret;
4448
1523c310
JB		 4449 /*
4450 * Turbo will still be enabled, but won't go below the set value.
4451 */
bc4d91f6 4452 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4453
bc4d91f6
AG		 4454 hw_max = dev_priv->rps.max_freq;
4455 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4456
b39fb297 4457 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4458 mutex_unlock(&dev_priv->rps.hw_lock);
4459 return -EINVAL;
0a073b84 4460 }
dd0a1aa1 4461
b39fb297 4462 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4463
ffe02b40 4464 intel_set_rps(dev, val);
dd0a1aa1 4465
4fc688ce 4466 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4467
647416f9 4468 return 0;
1523c310
JB		 4469}
4470
647416f9
KC		 4471DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4472 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4473 "%llu\n");
1523c310 4474
647416f9
KC		 4475static int
4476i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4477{
647416f9 4478 struct drm_device *dev = data;
e277a1f8 4479 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4480 u32 snpcr;
647416f9 4481 int ret;
07b7ddd9 4482
004777cb
DV		 4483 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4484 return -ENODEV;
4485
22bcfc6a
DV		 4486 ret = mutex_lock_interruptible(&dev->struct_mutex);
4487 if (ret)
4488 return ret;
c8c8fb33 4489 intel_runtime_pm_get(dev_priv);
22bcfc6a 4490
07b7ddd9 4491 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4492
4493 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4494 mutex_unlock(&dev_priv->dev->struct_mutex);
4495
647416f9 4496 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4497
647416f9 4498 return 0;
07b7ddd9
JB		 4499}
4500
647416f9
KC		 4501static int
4502i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4503{
647416f9 4504 struct drm_device *dev = data;
07b7ddd9 4505 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4506 u32 snpcr;
07b7ddd9 4507
004777cb
DV		 4508 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4509 return -ENODEV;
4510
647416f9 4511 if (val > 3)
07b7ddd9
JB		 4512 return -EINVAL;
4513
c8c8fb33 4514 intel_runtime_pm_get(dev_priv);
647416f9 4515 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4516
4517 /* Update the cache sharing policy here as well */
4518 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4519 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4520 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4521 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4522
c8c8fb33 4523 intel_runtime_pm_put(dev_priv);
647416f9 4524 return 0;
07b7ddd9
JB		 4525}
4526
647416f9
KC		 4527DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4528 i915_cache_sharing_get, i915_cache_sharing_set,
4529 "%llu\n");
07b7ddd9 4530
3873218f
JM		 4531static int i915_sseu_status(struct seq_file *m, void *unused)
4532{
4533 struct drm_info_node *node = (struct drm_info_node *) m->private;
4534 struct drm_device *dev = node->minor->dev;
7f992aba
JM		 4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536 unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
3873218f 4537
5575f03a 4538 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
3873218f
JM		 4539 return -ENODEV;
4540
4541 seq_puts(m, "SSEU Device Info\n");
4542 seq_printf(m, " Available Slice Total: %u\n",
4543 INTEL_INFO(dev)->slice_total);
4544 seq_printf(m, " Available Subslice Total: %u\n",
4545 INTEL_INFO(dev)->subslice_total);
4546 seq_printf(m, " Available Subslice Per Slice: %u\n",
4547 INTEL_INFO(dev)->subslice_per_slice);
4548 seq_printf(m, " Available EU Total: %u\n",
4549 INTEL_INFO(dev)->eu_total);
4550 seq_printf(m, " Available EU Per Subslice: %u\n",
4551 INTEL_INFO(dev)->eu_per_subslice);
4552 seq_printf(m, " Has Slice Power Gating: %s\n",
4553 yesno(INTEL_INFO(dev)->has_slice_pg));
4554 seq_printf(m, " Has Subslice Power Gating: %s\n",
4555 yesno(INTEL_INFO(dev)->has_subslice_pg));
4556 seq_printf(m, " Has EU Power Gating: %s\n",
4557 yesno(INTEL_INFO(dev)->has_eu_pg));
4558
7f992aba 4559 seq_puts(m, "SSEU Device Status\n");
5575f03a
JM		 4560 if (IS_CHERRYVIEW(dev)) {
4561 const int ss_max = 2;
4562 int ss;
4563 u32 sig1[ss_max], sig2[ss_max];
4564
4565 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4566 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4567 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4568 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4569
4570 for (ss = 0; ss < ss_max; ss++) {
4571 unsigned int eu_cnt;
4572
4573 if (sig1[ss] & CHV_SS_PG_ENABLE)
4574 /* skip disabled subslice */
4575 continue;
4576
4577 s_tot = 1;
4578 ss_per++;
4579 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4580 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4581 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4582 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4583 eu_tot += eu_cnt;
4584 eu_per = max(eu_per, eu_cnt);
4585 }
4586 ss_tot = ss_per;
4587 } else if (IS_SKYLAKE(dev)) {
7f992aba
JM		 4588 const int s_max = 3, ss_max = 4;
4589 int s, ss;
4590 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4591
4592 s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
4593 s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
4594 s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
4595 eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
4596 eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
4597 eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
4598 eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
4599 eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
4600 eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
4601 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4602 GEN9_PGCTL_SSA_EU19_ACK |
4603 GEN9_PGCTL_SSA_EU210_ACK |
4604 GEN9_PGCTL_SSA_EU311_ACK;
4605 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4606 GEN9_PGCTL_SSB_EU19_ACK |
4607 GEN9_PGCTL_SSB_EU210_ACK |
4608 GEN9_PGCTL_SSB_EU311_ACK;
4609
4610 for (s = 0; s < s_max; s++) {
4611 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4612 /* skip disabled slice */
4613 continue;
4614
4615 s_tot++;
4616 ss_per = INTEL_INFO(dev)->subslice_per_slice;
4617 ss_tot += ss_per;
4618 for (ss = 0; ss < ss_max; ss++) {
4619 unsigned int eu_cnt;
4620
4621 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4622 eu_mask[ss%2]);
4623 eu_tot += eu_cnt;
4624 eu_per = max(eu_per, eu_cnt);
4625 }
4626 }
4627 }
4628 seq_printf(m, " Enabled Slice Total: %u\n", s_tot);
4629 seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot);
4630 seq_printf(m, " Enabled Subslice Per Slice: %u\n", ss_per);
4631 seq_printf(m, " Enabled EU Total: %u\n", eu_tot);
4632 seq_printf(m, " Enabled EU Per Subslice: %u\n", eu_per);
4633
3873218f
JM		 4634 return 0;
4635}
4636
6d794d42
BW		 4637static int i915_forcewake_open(struct inode *inode, struct file *file)
4638{
4639 struct drm_device *dev = inode->i_private;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4641
075edca4 4642 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4643 return 0;
4644
6daccb0b 4645 intel_runtime_pm_get(dev_priv);
59bad947 4646 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4647
4648 return 0;
4649}
4650
c43b5634 4651static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4652{
4653 struct drm_device *dev = inode->i_private;
4654 struct drm_i915_private *dev_priv = dev->dev_private;
4655
075edca4 4656 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4657 return 0;
4658
59bad947 4659 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4660 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4661
4662 return 0;
4663}
4664
4665static const struct file_operations i915_forcewake_fops = {
4666 .owner = THIS_MODULE,
4667 .open = i915_forcewake_open,
4668 .release = i915_forcewake_release,
4669};
4670
4671static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4672{
4673 struct drm_device *dev = minor->dev;
4674 struct dentry *ent;
4675
4676 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4677 S_IRUSR,
6d794d42
BW		 4678 root, dev,
4679 &i915_forcewake_fops);
f3c5fe97
WY		 4680 if (!ent)
4681 return -ENOMEM;
6d794d42 4682
8eb57294 4683 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4684}
4685
6a9c308d
DV		 4686static int i915_debugfs_create(struct dentry *root,
4687 struct drm_minor *minor,
4688 const char *name,
4689 const struct file_operations *fops)
07b7ddd9
JB		 4690{
4691 struct drm_device *dev = minor->dev;
4692 struct dentry *ent;
4693
6a9c308d 4694 ent = debugfs_create_file(name,
07b7ddd9
JB		 4695 S_IRUGO | S_IWUSR,
4696 root, dev,
6a9c308d 4697 fops);
f3c5fe97
WY		 4698 if (!ent)
4699 return -ENOMEM;
07b7ddd9 4700
6a9c308d 4701 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4702}
4703
06c5bf8c 4704static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4705 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4706 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4707 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4708 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4709 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4710 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4711 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4712 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4713 {"i915_gem_request", i915_gem_request_info, 0},
4714 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4715 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4716 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4717 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4718 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4719 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4720 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 4721 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 4722 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 4723 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 4724 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4725 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4726 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4727 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4728 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4729 {"i915_sr_status", i915_sr_status, 0},
44834a67 4730 {"i915_opregion", i915_opregion, 0},
37811fcc 4731 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4732 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4733 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4734 {"i915_execlists", i915_execlists, 0},
f65367b5 4735 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 4736 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4737 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4738 {"i915_llc", i915_llc, 0},
e91fd8c6 4739 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4740 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4741 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4742 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4743 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4744 {"i915_display_info", i915_display_info, 0},
e04934cf 4745 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4746 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4747 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4748 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4749 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 4750 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 4751 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 4752 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 4753};
27c202ad 4754#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4755
06c5bf8c 4756static const struct i915_debugfs_files {
34b9674c
DV		 4757 const char *name;
4758 const struct file_operations *fops;
4759} i915_debugfs_files[] = {
4760 {"i915_wedged", &i915_wedged_fops},
4761 {"i915_max_freq", &i915_max_freq_fops},
4762 {"i915_min_freq", &i915_min_freq_fops},
4763 {"i915_cache_sharing", &i915_cache_sharing_fops},
4764 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4765 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4766 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4767 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4768 {"i915_error_state", &i915_error_state_fops},
4769 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4770 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4771 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4772 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4773 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4774 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4775};
4776
07144428
DL		 4777void intel_display_crc_init(struct drm_device *dev)
4778{
4779 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4780 enum pipe pipe;
07144428 4781
055e393f 4782 for_each_pipe(dev_priv, pipe) {
b378360e 4783 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4784
d538bbdf
DL		 4785 pipe_crc->opened = false;
4786 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4787 init_waitqueue_head(&pipe_crc->wq);
4788 }
4789}
4790
27c202ad 4791int i915_debugfs_init(struct drm_minor *minor)
2017263e 4792{
34b9674c 4793 int ret, i;
f3cd474b 4794
6d794d42 4795 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4796 if (ret)
4797 return ret;
6a9c308d 4798
07144428
DL		 4799 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4800 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4801 if (ret)
4802 return ret;
4803 }
4804
34b9674c
DV		 4805 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4806 ret = i915_debugfs_create(minor->debugfs_root, minor,
4807 i915_debugfs_files[i].name,
4808 i915_debugfs_files[i].fops);
4809 if (ret)
4810 return ret;
4811 }
40633219 4812
27c202ad
BG		 4813 return drm_debugfs_create_files(i915_debugfs_list,
4814 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4815 minor->debugfs_root, minor);
4816}
4817
27c202ad 4818void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4819{
34b9674c
DV		 4820 int i;
4821
27c202ad
BG		 4822 drm_debugfs_remove_files(i915_debugfs_list,
4823 I915_DEBUGFS_ENTRIES, minor);
07144428 4824
6d794d42
BW		 4825 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4826 1, minor);
07144428 4827
e309a997 4828 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4829 struct drm_info_list *info_list =
4830 (struct drm_info_list *)&i915_pipe_crc_data[i];
4831
4832 drm_debugfs_remove_files(info_list, 1, minor);
4833 }
4834
34b9674c
DV		 4835 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4836 struct drm_info_list *info_list =
4837 (struct drm_info_list *) i915_debugfs_files[i].fops;
4838
4839 drm_debugfs_remove_files(info_list, 1, minor);
4840 }
2017263e 4841}
aa7471d2
JN		 4842
4843struct dpcd_block {
4844 /* DPCD dump start address. */
4845 unsigned int offset;
4846 /* DPCD dump end address, inclusive. If unset, .size will be used. */
4847 unsigned int end;
4848 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
4849 size_t size;
4850 /* Only valid for eDP. */
4851 bool edp;
4852};
4853
4854static const struct dpcd_block i915_dpcd_debug[] = {
4855 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
4856 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
4857 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
4858 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
4859 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
4860 { .offset = DP_SET_POWER },
4861 { .offset = DP_EDP_DPCD_REV },
4862 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
4863 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
4864 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
4865};
4866
4867static int i915_dpcd_show(struct seq_file *m, void *data)
4868{
4869 struct drm_connector *connector = m->private;
4870 struct intel_dp *intel_dp =
4871 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
4872 uint8_t buf[16];
4873 ssize_t err;
4874 int i;
4875
4876 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
4877 const struct dpcd_block *b = &i915_dpcd_debug[i];
4878 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
4879
4880 if (b->edp &&
4881 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
4882 continue;
4883
4884 /* low tech for now */
4885 if (WARN_ON(size > sizeof(buf)))
4886 continue;
4887
4888 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
4889 if (err <= 0) {
4890 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
4891 size, b->offset, err);
4892 continue;
4893 }
4894
4895 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
4896 };
4897
4898 return 0;
4899}
4900
4901static int i915_dpcd_open(struct inode *inode, struct file *file)
4902{
4903 return single_open(file, i915_dpcd_show, inode->i_private);
4904}
4905
4906static const struct file_operations i915_dpcd_fops = {
4907 .owner = THIS_MODULE,
4908 .open = i915_dpcd_open,
4909 .read = seq_read,
4910 .llseek = seq_lseek,
4911 .release = single_release,
4912};
4913
4914/**
4915 * i915_debugfs_connector_add - add i915 specific connector debugfs files
4916 * @connector: pointer to a registered drm_connector
4917 *
4918 * Cleanup will be done by drm_connector_unregister() through a call to
4919 * drm_debugfs_connector_remove().
4920 *
4921 * Returns 0 on success, negative error codes on error.
4922 */
4923int i915_debugfs_connector_add(struct drm_connector *connector)
4924{
4925 struct dentry *root = connector->debugfs_entry;
4926
4927 /* The connector must have been registered beforehands. */
4928 if (!root)
4929 return -ENODEV;
4930
4931 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4932 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4933 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
4934 &i915_dpcd_fops);
4935
4936 return 0;
4937}
Linux kernel - Deliverables
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