Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
f3cd474b | 30 | #include <linux/debugfs.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
2d1a8a48 | 32 | #include <linux/export.h> |
760285e7 | 33 | #include <drm/drmP.h> |
4e5359cd | 34 | #include "intel_drv.h" |
e5c65260 | 35 | #include "intel_ringbuffer.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
2017263e BG |
37 | #include "i915_drv.h" |
38 | ||
39 | #define DRM_I915_RING_DEBUG 1 | |
40 | ||
41 | ||
42 | #if defined(CONFIG_DEBUG_FS) | |
43 | ||
f13d3f73 | 44 | enum { |
69dc4987 | 45 | ACTIVE_LIST, |
f13d3f73 | 46 | INACTIVE_LIST, |
d21d5975 | 47 | PINNED_LIST, |
f13d3f73 | 48 | }; |
2017263e | 49 | |
70d39fe4 CW |
50 | static const char *yesno(int v) |
51 | { | |
52 | return v ? "yes" : "no"; | |
53 | } | |
54 | ||
55 | static int i915_capabilities(struct seq_file *m, void *data) | |
56 | { | |
57 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
58 | struct drm_device *dev = node->minor->dev; | |
59 | const struct intel_device_info *info = INTEL_INFO(dev); | |
60 | ||
61 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 62 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
63 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
64 | #define SEP_SEMICOLON ; | |
65 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
66 | #undef PRINT_FLAG | |
67 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
68 | |
69 | return 0; | |
70 | } | |
2017263e | 71 | |
05394f39 | 72 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 73 | { |
05394f39 | 74 | if (obj->user_pin_count > 0) |
a6172a80 | 75 | return "P"; |
05394f39 | 76 | else if (obj->pin_count > 0) |
a6172a80 CW |
77 | return "p"; |
78 | else | |
79 | return " "; | |
80 | } | |
81 | ||
05394f39 | 82 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 83 | { |
0206e353 AJ |
84 | switch (obj->tiling_mode) { |
85 | default: | |
86 | case I915_TILING_NONE: return " "; | |
87 | case I915_TILING_X: return "X"; | |
88 | case I915_TILING_Y: return "Y"; | |
89 | } | |
a6172a80 CW |
90 | } |
91 | ||
37811fcc CW |
92 | static void |
93 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
94 | { | |
2563a452 | 95 | seq_printf(m, "%pK: %s%s %8zdKiB %02x %02x %d %d %d%s%s%s", |
37811fcc CW |
96 | &obj->base, |
97 | get_pin_flag(obj), | |
98 | get_tiling_flag(obj), | |
a05a5862 | 99 | obj->base.size / 1024, |
37811fcc CW |
100 | obj->base.read_domains, |
101 | obj->base.write_domain, | |
0201f1ec CW |
102 | obj->last_read_seqno, |
103 | obj->last_write_seqno, | |
caea7476 | 104 | obj->last_fenced_seqno, |
84734a04 | 105 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
106 | obj->dirty ? " dirty" : "", |
107 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
108 | if (obj->base.name) | |
109 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
110 | if (obj->pin_count) |
111 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
37811fcc CW |
112 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
113 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
f343c5f6 BW |
114 | if (i915_gem_obj_ggtt_bound(obj)) |
115 | seq_printf(m, " (gtt offset: %08lx, size: %08x)", | |
116 | i915_gem_obj_ggtt_offset(obj), (unsigned int)i915_gem_obj_ggtt_size(obj)); | |
c1ad11fc CW |
117 | if (obj->stolen) |
118 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
119 | if (obj->pin_mappable || obj->fault_mappable) { |
120 | char s[3], *t = s; | |
121 | if (obj->pin_mappable) | |
122 | *t++ = 'p'; | |
123 | if (obj->fault_mappable) | |
124 | *t++ = 'f'; | |
125 | *t = '\0'; | |
126 | seq_printf(m, " (%s mappable)", s); | |
127 | } | |
69dc4987 CW |
128 | if (obj->ring != NULL) |
129 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
130 | } |
131 | ||
433e12f7 | 132 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
133 | { |
134 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
135 | uintptr_t list = (uintptr_t) node->info_ent->data; |
136 | struct list_head *head; | |
2017263e | 137 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
138 | struct drm_i915_private *dev_priv = dev->dev_private; |
139 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
05394f39 | 140 | struct drm_i915_gem_object *obj; |
8f2480fb CW |
141 | size_t total_obj_size, total_gtt_size; |
142 | int count, ret; | |
de227ef0 CW |
143 | |
144 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
145 | if (ret) | |
146 | return ret; | |
2017263e | 147 | |
433e12f7 BG |
148 | switch (list) { |
149 | case ACTIVE_LIST: | |
267f0c90 | 150 | seq_puts(m, "Active:\n"); |
5cef07e1 | 151 | head = &vm->active_list; |
433e12f7 BG |
152 | break; |
153 | case INACTIVE_LIST: | |
267f0c90 | 154 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 155 | head = &vm->inactive_list; |
433e12f7 | 156 | break; |
433e12f7 | 157 | default: |
de227ef0 CW |
158 | mutex_unlock(&dev->struct_mutex); |
159 | return -EINVAL; | |
2017263e | 160 | } |
2017263e | 161 | |
8f2480fb | 162 | total_obj_size = total_gtt_size = count = 0; |
05394f39 | 163 | list_for_each_entry(obj, head, mm_list) { |
267f0c90 | 164 | seq_puts(m, " "); |
05394f39 | 165 | describe_obj(m, obj); |
267f0c90 | 166 | seq_putc(m, '\n'); |
05394f39 | 167 | total_obj_size += obj->base.size; |
f343c5f6 | 168 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
8f2480fb | 169 | count++; |
2017263e | 170 | } |
de227ef0 | 171 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 172 | |
8f2480fb CW |
173 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
174 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
175 | return 0; |
176 | } | |
177 | ||
6299f992 CW |
178 | #define count_objects(list, member) do { \ |
179 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 180 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
181 | ++count; \ |
182 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 183 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
184 | ++mappable_count; \ |
185 | } \ | |
186 | } \ | |
0206e353 | 187 | } while (0) |
6299f992 | 188 | |
2db8e9d6 CW |
189 | struct file_stats { |
190 | int count; | |
191 | size_t total, active, inactive, unbound; | |
192 | }; | |
193 | ||
194 | static int per_file_stats(int id, void *ptr, void *data) | |
195 | { | |
196 | struct drm_i915_gem_object *obj = ptr; | |
197 | struct file_stats *stats = data; | |
198 | ||
199 | stats->count++; | |
200 | stats->total += obj->base.size; | |
201 | ||
f343c5f6 | 202 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
203 | if (!list_empty(&obj->ring_list)) |
204 | stats->active += obj->base.size; | |
205 | else | |
206 | stats->inactive += obj->base.size; | |
207 | } else { | |
208 | if (!list_empty(&obj->global_list)) | |
209 | stats->unbound += obj->base.size; | |
210 | } | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
aee56cff | 215 | static int i915_gem_object_info(struct seq_file *m, void *data) |
73aa808f CW |
216 | { |
217 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
218 | struct drm_device *dev = node->minor->dev; | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
220 | u32 count, mappable_count, purgeable_count; |
221 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 222 | struct drm_i915_gem_object *obj; |
5cef07e1 | 223 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 224 | struct drm_file *file; |
73aa808f CW |
225 | int ret; |
226 | ||
227 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
228 | if (ret) | |
229 | return ret; | |
230 | ||
6299f992 CW |
231 | seq_printf(m, "%u objects, %zu bytes\n", |
232 | dev_priv->mm.object_count, | |
233 | dev_priv->mm.object_memory); | |
234 | ||
235 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 236 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
237 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
238 | count, mappable_count, size, mappable_size); | |
239 | ||
240 | size = count = mappable_size = mappable_count = 0; | |
5cef07e1 | 241 | count_objects(&vm->active_list, mm_list); |
6299f992 CW |
242 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
243 | count, mappable_count, size, mappable_size); | |
244 | ||
6299f992 | 245 | size = count = mappable_size = mappable_count = 0; |
5cef07e1 | 246 | count_objects(&vm->inactive_list, mm_list); |
6299f992 CW |
247 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
248 | count, mappable_count, size, mappable_size); | |
249 | ||
b7abb714 | 250 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 251 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 252 | size += obj->base.size, ++count; |
b7abb714 CW |
253 | if (obj->madv == I915_MADV_DONTNEED) |
254 | purgeable_size += obj->base.size, ++purgeable_count; | |
255 | } | |
6c085a72 CW |
256 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
257 | ||
6299f992 | 258 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 259 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 260 | if (obj->fault_mappable) { |
f343c5f6 | 261 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
262 | ++count; |
263 | } | |
264 | if (obj->pin_mappable) { | |
f343c5f6 | 265 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
266 | ++mappable_count; |
267 | } | |
b7abb714 CW |
268 | if (obj->madv == I915_MADV_DONTNEED) { |
269 | purgeable_size += obj->base.size; | |
270 | ++purgeable_count; | |
271 | } | |
6299f992 | 272 | } |
b7abb714 CW |
273 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
274 | purgeable_count, purgeable_size); | |
6299f992 CW |
275 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
276 | mappable_count, mappable_size); | |
277 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
278 | count, size); | |
279 | ||
93d18799 | 280 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
281 | dev_priv->gtt.base.total, |
282 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 283 | |
267f0c90 | 284 | seq_putc(m, '\n'); |
2db8e9d6 CW |
285 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
286 | struct file_stats stats; | |
287 | ||
288 | memset(&stats, 0, sizeof(stats)); | |
289 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
290 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
291 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
292 | stats.count, | |
293 | stats.total, | |
294 | stats.active, | |
295 | stats.inactive, | |
296 | stats.unbound); | |
297 | } | |
298 | ||
73aa808f CW |
299 | mutex_unlock(&dev->struct_mutex); |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
aee56cff | 304 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
305 | { |
306 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
307 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 308 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
309 | struct drm_i915_private *dev_priv = dev->dev_private; |
310 | struct drm_i915_gem_object *obj; | |
311 | size_t total_obj_size, total_gtt_size; | |
312 | int count, ret; | |
313 | ||
314 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
315 | if (ret) | |
316 | return ret; | |
317 | ||
318 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 319 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
320 | if (list == PINNED_LIST && obj->pin_count == 0) |
321 | continue; | |
322 | ||
267f0c90 | 323 | seq_puts(m, " "); |
08c18323 | 324 | describe_obj(m, obj); |
267f0c90 | 325 | seq_putc(m, '\n'); |
08c18323 | 326 | total_obj_size += obj->base.size; |
f343c5f6 | 327 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
328 | count++; |
329 | } | |
330 | ||
331 | mutex_unlock(&dev->struct_mutex); | |
332 | ||
333 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
334 | count, total_obj_size, total_gtt_size); | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
4e5359cd SF |
339 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
340 | { | |
341 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
342 | struct drm_device *dev = node->minor->dev; | |
343 | unsigned long flags; | |
344 | struct intel_crtc *crtc; | |
345 | ||
346 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
347 | const char pipe = pipe_name(crtc->pipe); |
348 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
349 | struct intel_unpin_work *work; |
350 | ||
351 | spin_lock_irqsave(&dev->event_lock, flags); | |
352 | work = crtc->unpin_work; | |
353 | if (work == NULL) { | |
9db4a9c7 | 354 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
355 | pipe, plane); |
356 | } else { | |
e7d841ca | 357 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 358 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
359 | pipe, plane); |
360 | } else { | |
9db4a9c7 | 361 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
362 | pipe, plane); |
363 | } | |
364 | if (work->enable_stall_check) | |
267f0c90 | 365 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 366 | else |
267f0c90 | 367 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 368 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
369 | |
370 | if (work->old_fb_obj) { | |
05394f39 CW |
371 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
372 | if (obj) | |
f343c5f6 BW |
373 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
374 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
375 | } |
376 | if (work->pending_flip_obj) { | |
05394f39 CW |
377 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
378 | if (obj) | |
f343c5f6 BW |
379 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
380 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
381 | } |
382 | } | |
383 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
384 | } | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
2017263e BG |
389 | static int i915_gem_request_info(struct seq_file *m, void *data) |
390 | { | |
391 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
392 | struct drm_device *dev = node->minor->dev; | |
393 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 394 | struct intel_ring_buffer *ring; |
2017263e | 395 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 396 | int ret, count, i; |
de227ef0 CW |
397 | |
398 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
399 | if (ret) | |
400 | return ret; | |
2017263e | 401 | |
c2c347a9 | 402 | count = 0; |
a2c7f6fd CW |
403 | for_each_ring(ring, dev_priv, i) { |
404 | if (list_empty(&ring->request_list)) | |
405 | continue; | |
406 | ||
407 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 408 | list_for_each_entry(gem_request, |
a2c7f6fd | 409 | &ring->request_list, |
c2c347a9 CW |
410 | list) { |
411 | seq_printf(m, " %d @ %d\n", | |
412 | gem_request->seqno, | |
413 | (int) (jiffies - gem_request->emitted_jiffies)); | |
414 | } | |
415 | count++; | |
2017263e | 416 | } |
de227ef0 CW |
417 | mutex_unlock(&dev->struct_mutex); |
418 | ||
c2c347a9 | 419 | if (count == 0) |
267f0c90 | 420 | seq_puts(m, "No requests\n"); |
c2c347a9 | 421 | |
2017263e BG |
422 | return 0; |
423 | } | |
424 | ||
b2223497 CW |
425 | static void i915_ring_seqno_info(struct seq_file *m, |
426 | struct intel_ring_buffer *ring) | |
427 | { | |
428 | if (ring->get_seqno) { | |
43a7b924 | 429 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 430 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
431 | } |
432 | } | |
433 | ||
2017263e BG |
434 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
435 | { | |
436 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
437 | struct drm_device *dev = node->minor->dev; | |
438 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 439 | struct intel_ring_buffer *ring; |
1ec14ad3 | 440 | int ret, i; |
de227ef0 CW |
441 | |
442 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
443 | if (ret) | |
444 | return ret; | |
2017263e | 445 | |
a2c7f6fd CW |
446 | for_each_ring(ring, dev_priv, i) |
447 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
448 | |
449 | mutex_unlock(&dev->struct_mutex); | |
450 | ||
2017263e BG |
451 | return 0; |
452 | } | |
453 | ||
454 | ||
455 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
456 | { | |
457 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
458 | struct drm_device *dev = node->minor->dev; | |
459 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 460 | struct intel_ring_buffer *ring; |
9db4a9c7 | 461 | int ret, i, pipe; |
de227ef0 CW |
462 | |
463 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
464 | if (ret) | |
465 | return ret; | |
2017263e | 466 | |
7e231dbe JB |
467 | if (IS_VALLEYVIEW(dev)) { |
468 | seq_printf(m, "Display IER:\t%08x\n", | |
469 | I915_READ(VLV_IER)); | |
470 | seq_printf(m, "Display IIR:\t%08x\n", | |
471 | I915_READ(VLV_IIR)); | |
472 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
473 | I915_READ(VLV_IIR_RW)); | |
474 | seq_printf(m, "Display IMR:\t%08x\n", | |
475 | I915_READ(VLV_IMR)); | |
476 | for_each_pipe(pipe) | |
477 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
478 | pipe_name(pipe), | |
479 | I915_READ(PIPESTAT(pipe))); | |
480 | ||
481 | seq_printf(m, "Master IER:\t%08x\n", | |
482 | I915_READ(VLV_MASTER_IER)); | |
483 | ||
484 | seq_printf(m, "Render IER:\t%08x\n", | |
485 | I915_READ(GTIER)); | |
486 | seq_printf(m, "Render IIR:\t%08x\n", | |
487 | I915_READ(GTIIR)); | |
488 | seq_printf(m, "Render IMR:\t%08x\n", | |
489 | I915_READ(GTIMR)); | |
490 | ||
491 | seq_printf(m, "PM IER:\t\t%08x\n", | |
492 | I915_READ(GEN6_PMIER)); | |
493 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
494 | I915_READ(GEN6_PMIIR)); | |
495 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
496 | I915_READ(GEN6_PMIMR)); | |
497 | ||
498 | seq_printf(m, "Port hotplug:\t%08x\n", | |
499 | I915_READ(PORT_HOTPLUG_EN)); | |
500 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
501 | I915_READ(VLV_DPFLIPSTAT)); | |
502 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
503 | I915_READ(DPINVGTT)); | |
504 | ||
505 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
506 | seq_printf(m, "Interrupt enable: %08x\n", |
507 | I915_READ(IER)); | |
508 | seq_printf(m, "Interrupt identity: %08x\n", | |
509 | I915_READ(IIR)); | |
510 | seq_printf(m, "Interrupt mask: %08x\n", | |
511 | I915_READ(IMR)); | |
9db4a9c7 JB |
512 | for_each_pipe(pipe) |
513 | seq_printf(m, "Pipe %c stat: %08x\n", | |
514 | pipe_name(pipe), | |
515 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
516 | } else { |
517 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
518 | I915_READ(DEIER)); | |
519 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
520 | I915_READ(DEIIR)); | |
521 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
522 | I915_READ(DEIMR)); | |
523 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
524 | I915_READ(SDEIER)); | |
525 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
526 | I915_READ(SDEIIR)); | |
527 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
528 | I915_READ(SDEIMR)); | |
529 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
530 | I915_READ(GTIER)); | |
531 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
532 | I915_READ(GTIIR)); | |
533 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
534 | I915_READ(GTIMR)); | |
535 | } | |
2017263e BG |
536 | seq_printf(m, "Interrupts received: %d\n", |
537 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 538 | for_each_ring(ring, dev_priv, i) { |
da64c6fc | 539 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
a2c7f6fd CW |
540 | seq_printf(m, |
541 | "Graphics Interrupt mask (%s): %08x\n", | |
542 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 543 | } |
a2c7f6fd | 544 | i915_ring_seqno_info(m, ring); |
9862e600 | 545 | } |
de227ef0 CW |
546 | mutex_unlock(&dev->struct_mutex); |
547 | ||
2017263e BG |
548 | return 0; |
549 | } | |
550 | ||
a6172a80 CW |
551 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
552 | { | |
553 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
554 | struct drm_device *dev = node->minor->dev; | |
555 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
556 | int i, ret; |
557 | ||
558 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
559 | if (ret) | |
560 | return ret; | |
a6172a80 CW |
561 | |
562 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
563 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
564 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 565 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 566 | |
6c085a72 CW |
567 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
568 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 569 | if (obj == NULL) |
267f0c90 | 570 | seq_puts(m, "unused"); |
c2c347a9 | 571 | else |
05394f39 | 572 | describe_obj(m, obj); |
267f0c90 | 573 | seq_putc(m, '\n'); |
a6172a80 CW |
574 | } |
575 | ||
05394f39 | 576 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
577 | return 0; |
578 | } | |
579 | ||
2017263e BG |
580 | static int i915_hws_info(struct seq_file *m, void *data) |
581 | { | |
582 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
583 | struct drm_device *dev = node->minor->dev; | |
584 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 585 | struct intel_ring_buffer *ring; |
1a240d4d | 586 | const u32 *hws; |
4066c0ae CW |
587 | int i; |
588 | ||
1ec14ad3 | 589 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 590 | hws = ring->status_page.page_addr; |
2017263e BG |
591 | if (hws == NULL) |
592 | return 0; | |
593 | ||
594 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
595 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
596 | i * 4, | |
597 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
598 | } | |
599 | return 0; | |
600 | } | |
601 | ||
d5442303 DV |
602 | static ssize_t |
603 | i915_error_state_write(struct file *filp, | |
604 | const char __user *ubuf, | |
605 | size_t cnt, | |
606 | loff_t *ppos) | |
607 | { | |
edc3d884 | 608 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 609 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 610 | int ret; |
d5442303 DV |
611 | |
612 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
613 | ||
22bcfc6a DV |
614 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
615 | if (ret) | |
616 | return ret; | |
617 | ||
d5442303 DV |
618 | i915_destroy_error_state(dev); |
619 | mutex_unlock(&dev->struct_mutex); | |
620 | ||
621 | return cnt; | |
622 | } | |
623 | ||
624 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
625 | { | |
626 | struct drm_device *dev = inode->i_private; | |
d5442303 | 627 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
628 | |
629 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
630 | if (!error_priv) | |
631 | return -ENOMEM; | |
632 | ||
633 | error_priv->dev = dev; | |
634 | ||
95d5bfb3 | 635 | i915_error_state_get(dev, error_priv); |
d5442303 | 636 | |
edc3d884 MK |
637 | file->private_data = error_priv; |
638 | ||
639 | return 0; | |
d5442303 DV |
640 | } |
641 | ||
642 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
643 | { | |
edc3d884 | 644 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 645 | |
95d5bfb3 | 646 | i915_error_state_put(error_priv); |
d5442303 DV |
647 | kfree(error_priv); |
648 | ||
edc3d884 MK |
649 | return 0; |
650 | } | |
651 | ||
4dc955f7 MK |
652 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
653 | size_t count, loff_t *pos) | |
654 | { | |
655 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
656 | struct drm_i915_error_state_buf error_str; | |
657 | loff_t tmp_pos = 0; | |
658 | ssize_t ret_count = 0; | |
659 | int ret; | |
660 | ||
661 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
662 | if (ret) | |
663 | return ret; | |
edc3d884 | 664 | |
fc16b48b | 665 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
666 | if (ret) |
667 | goto out; | |
668 | ||
edc3d884 MK |
669 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
670 | error_str.buf, | |
671 | error_str.bytes); | |
672 | ||
673 | if (ret_count < 0) | |
674 | ret = ret_count; | |
675 | else | |
676 | *pos = error_str.start + ret_count; | |
677 | out: | |
4dc955f7 | 678 | i915_error_state_buf_release(&error_str); |
edc3d884 | 679 | return ret ?: ret_count; |
d5442303 DV |
680 | } |
681 | ||
682 | static const struct file_operations i915_error_state_fops = { | |
683 | .owner = THIS_MODULE, | |
684 | .open = i915_error_state_open, | |
edc3d884 | 685 | .read = i915_error_state_read, |
d5442303 DV |
686 | .write = i915_error_state_write, |
687 | .llseek = default_llseek, | |
688 | .release = i915_error_state_release, | |
689 | }; | |
690 | ||
647416f9 KC |
691 | static int |
692 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 693 | { |
647416f9 | 694 | struct drm_device *dev = data; |
40633219 | 695 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
696 | int ret; |
697 | ||
698 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
699 | if (ret) | |
700 | return ret; | |
701 | ||
647416f9 | 702 | *val = dev_priv->next_seqno; |
40633219 MK |
703 | mutex_unlock(&dev->struct_mutex); |
704 | ||
647416f9 | 705 | return 0; |
40633219 MK |
706 | } |
707 | ||
647416f9 KC |
708 | static int |
709 | i915_next_seqno_set(void *data, u64 val) | |
710 | { | |
711 | struct drm_device *dev = data; | |
40633219 MK |
712 | int ret; |
713 | ||
40633219 MK |
714 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
715 | if (ret) | |
716 | return ret; | |
717 | ||
e94fbaa8 | 718 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
719 | mutex_unlock(&dev->struct_mutex); |
720 | ||
647416f9 | 721 | return ret; |
40633219 MK |
722 | } |
723 | ||
647416f9 KC |
724 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
725 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 726 | "0x%llx\n"); |
40633219 | 727 | |
f97108d1 JB |
728 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
729 | { | |
730 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
731 | struct drm_device *dev = node->minor->dev; | |
732 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
733 | u16 crstanddelay; |
734 | int ret; | |
735 | ||
736 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
737 | if (ret) | |
738 | return ret; | |
739 | ||
740 | crstanddelay = I915_READ16(CRSTANDVID); | |
741 | ||
742 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
743 | |
744 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
745 | ||
746 | return 0; | |
747 | } | |
748 | ||
749 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
750 | { | |
751 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
752 | struct drm_device *dev = node->minor->dev; | |
753 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 754 | int ret; |
3b8d8d91 JB |
755 | |
756 | if (IS_GEN5(dev)) { | |
757 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
758 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
759 | ||
760 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
761 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
762 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
763 | MEMSTAT_VID_SHIFT); | |
764 | seq_printf(m, "Current P-state: %d\n", | |
765 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 766 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
767 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
768 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
769 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
f82855d3 | 770 | u32 rpstat, cagf; |
ccab5c82 JB |
771 | u32 rpupei, rpcurup, rpprevup; |
772 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
773 | int max_freq; |
774 | ||
775 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
776 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
777 | if (ret) | |
778 | return ret; | |
779 | ||
fcca7926 | 780 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 | 781 | |
ccab5c82 JB |
782 | rpstat = I915_READ(GEN6_RPSTAT1); |
783 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
784 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
785 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
786 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
787 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
788 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
789 | if (IS_HASWELL(dev)) |
790 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
791 | else | |
792 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
793 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 794 | |
d1ebd816 BW |
795 | gen6_gt_force_wake_put(dev_priv); |
796 | mutex_unlock(&dev->struct_mutex); | |
797 | ||
3b8d8d91 | 798 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 799 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
800 | seq_printf(m, "Render p-state ratio: %d\n", |
801 | (gt_perf_status & 0xff00) >> 8); | |
802 | seq_printf(m, "Render p-state VID: %d\n", | |
803 | gt_perf_status & 0xff); | |
804 | seq_printf(m, "Render p-state limit: %d\n", | |
805 | rp_state_limits & 0xff); | |
f82855d3 | 806 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
807 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
808 | GEN6_CURICONT_MASK); | |
809 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
810 | GEN6_CURBSYTAVG_MASK); | |
811 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
812 | GEN6_CURBSYTAVG_MASK); | |
813 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
814 | GEN6_CURIAVG_MASK); | |
815 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
816 | GEN6_CURBSYTAVG_MASK); | |
817 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
818 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
819 | |
820 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
821 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 822 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
823 | |
824 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
825 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 826 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
827 | |
828 | max_freq = rp_state_cap & 0xff; | |
829 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 830 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
831 | |
832 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
833 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
834 | } else if (IS_VALLEYVIEW(dev)) { |
835 | u32 freq_sts, val; | |
836 | ||
259bd5d4 | 837 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 838 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
839 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
840 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
841 | ||
64936258 | 842 | val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); |
0a073b84 JB |
843 | seq_printf(m, "max GPU freq: %d MHz\n", |
844 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
845 | ||
64936258 | 846 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); |
0a073b84 JB |
847 | seq_printf(m, "min GPU freq: %d MHz\n", |
848 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
849 | ||
850 | seq_printf(m, "current GPU freq: %d MHz\n", | |
851 | vlv_gpu_freq(dev_priv->mem_freq, | |
852 | (freq_sts >> 8) & 0xff)); | |
259bd5d4 | 853 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 854 | } else { |
267f0c90 | 855 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 856 | } |
f97108d1 JB |
857 | |
858 | return 0; | |
859 | } | |
860 | ||
861 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
862 | { | |
863 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
864 | struct drm_device *dev = node->minor->dev; | |
865 | drm_i915_private_t *dev_priv = dev->dev_private; | |
866 | u32 delayfreq; | |
616fdb5a BW |
867 | int ret, i; |
868 | ||
869 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
870 | if (ret) | |
871 | return ret; | |
f97108d1 JB |
872 | |
873 | for (i = 0; i < 16; i++) { | |
874 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
875 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
876 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
877 | } |
878 | ||
616fdb5a BW |
879 | mutex_unlock(&dev->struct_mutex); |
880 | ||
f97108d1 JB |
881 | return 0; |
882 | } | |
883 | ||
884 | static inline int MAP_TO_MV(int map) | |
885 | { | |
886 | return 1250 - (map * 25); | |
887 | } | |
888 | ||
889 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
890 | { | |
891 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
892 | struct drm_device *dev = node->minor->dev; | |
893 | drm_i915_private_t *dev_priv = dev->dev_private; | |
894 | u32 inttoext; | |
616fdb5a BW |
895 | int ret, i; |
896 | ||
897 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
898 | if (ret) | |
899 | return ret; | |
f97108d1 JB |
900 | |
901 | for (i = 1; i <= 32; i++) { | |
902 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
903 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
904 | } | |
905 | ||
616fdb5a BW |
906 | mutex_unlock(&dev->struct_mutex); |
907 | ||
f97108d1 JB |
908 | return 0; |
909 | } | |
910 | ||
4d85529d | 911 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
912 | { |
913 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
914 | struct drm_device *dev = node->minor->dev; | |
915 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
916 | u32 rgvmodectl, rstdbyctl; |
917 | u16 crstandvid; | |
918 | int ret; | |
919 | ||
920 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
921 | if (ret) | |
922 | return ret; | |
923 | ||
924 | rgvmodectl = I915_READ(MEMMODECTL); | |
925 | rstdbyctl = I915_READ(RSTDBYCTL); | |
926 | crstandvid = I915_READ16(CRSTANDVID); | |
927 | ||
928 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
929 | |
930 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
931 | "yes" : "no"); | |
932 | seq_printf(m, "Boost freq: %d\n", | |
933 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
934 | MEMMODE_BOOST_FREQ_SHIFT); | |
935 | seq_printf(m, "HW control enabled: %s\n", | |
936 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
937 | seq_printf(m, "SW control enabled: %s\n", | |
938 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
939 | seq_printf(m, "Gated voltage change: %s\n", | |
940 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
941 | seq_printf(m, "Starting frequency: P%d\n", | |
942 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 943 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 944 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
945 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
946 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
947 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
948 | seq_printf(m, "Render standby enabled: %s\n", | |
949 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 950 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
951 | switch (rstdbyctl & RSX_STATUS_MASK) { |
952 | case RSX_STATUS_ON: | |
267f0c90 | 953 | seq_puts(m, "on\n"); |
88271da3 JB |
954 | break; |
955 | case RSX_STATUS_RC1: | |
267f0c90 | 956 | seq_puts(m, "RC1\n"); |
88271da3 JB |
957 | break; |
958 | case RSX_STATUS_RC1E: | |
267f0c90 | 959 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
960 | break; |
961 | case RSX_STATUS_RS1: | |
267f0c90 | 962 | seq_puts(m, "RS1\n"); |
88271da3 JB |
963 | break; |
964 | case RSX_STATUS_RS2: | |
267f0c90 | 965 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
966 | break; |
967 | case RSX_STATUS_RS3: | |
267f0c90 | 968 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
969 | break; |
970 | default: | |
267f0c90 | 971 | seq_puts(m, "unknown\n"); |
88271da3 JB |
972 | break; |
973 | } | |
f97108d1 JB |
974 | |
975 | return 0; | |
976 | } | |
977 | ||
4d85529d BW |
978 | static int gen6_drpc_info(struct seq_file *m) |
979 | { | |
980 | ||
981 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
982 | struct drm_device *dev = node->minor->dev; | |
983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 984 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 985 | unsigned forcewake_count; |
aee56cff | 986 | int count = 0, ret; |
4d85529d BW |
987 | |
988 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
989 | if (ret) | |
990 | return ret; | |
991 | ||
907b28c5 CW |
992 | spin_lock_irq(&dev_priv->uncore.lock); |
993 | forcewake_count = dev_priv->uncore.forcewake_count; | |
994 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
995 | |
996 | if (forcewake_count) { | |
267f0c90 DL |
997 | seq_puts(m, "RC information inaccurate because somebody " |
998 | "holds a forcewake reference \n"); | |
4d85529d BW |
999 | } else { |
1000 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1001 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1002 | udelay(10); | |
1003 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1004 | } | |
1005 | ||
1006 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1007 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1008 | |
1009 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1010 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1011 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1012 | mutex_lock(&dev_priv->rps.hw_lock); |
1013 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1014 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1015 | |
1016 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1017 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1018 | seq_printf(m, "HW control enabled: %s\n", | |
1019 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1020 | seq_printf(m, "SW control enabled: %s\n", | |
1021 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1022 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1023 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1024 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1025 | seq_printf(m, "RC6 Enabled: %s\n", | |
1026 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1027 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1028 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1029 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1030 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1031 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1032 | switch (gt_core_status & GEN6_RCn_MASK) { |
1033 | case GEN6_RC0: | |
1034 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1035 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1036 | else |
267f0c90 | 1037 | seq_puts(m, "on\n"); |
4d85529d BW |
1038 | break; |
1039 | case GEN6_RC3: | |
267f0c90 | 1040 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1041 | break; |
1042 | case GEN6_RC6: | |
267f0c90 | 1043 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1044 | break; |
1045 | case GEN6_RC7: | |
267f0c90 | 1046 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1047 | break; |
1048 | default: | |
267f0c90 | 1049 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1050 | break; |
1051 | } | |
1052 | ||
1053 | seq_printf(m, "Core Power Down: %s\n", | |
1054 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1055 | |
1056 | /* Not exactly sure what this is */ | |
1057 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1058 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1059 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1060 | I915_READ(GEN6_GT_GFX_RC6)); | |
1061 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1062 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1063 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1064 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1065 | ||
ecd8faea BW |
1066 | seq_printf(m, "RC6 voltage: %dmV\n", |
1067 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1068 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1069 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1070 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1071 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1072 | return 0; |
1073 | } | |
1074 | ||
1075 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1076 | { | |
1077 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1078 | struct drm_device *dev = node->minor->dev; | |
1079 | ||
1080 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1081 | return gen6_drpc_info(m); | |
1082 | else | |
1083 | return ironlake_drpc_info(m); | |
1084 | } | |
1085 | ||
b5e50c3f JB |
1086 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1087 | { | |
1088 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1089 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1090 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1091 | |
ee5382ae | 1092 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1093 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1094 | return 0; |
1095 | } | |
1096 | ||
ee5382ae | 1097 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1098 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1099 | } else { |
267f0c90 | 1100 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1101 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1102 | case FBC_OK: |
1103 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1104 | break; | |
1105 | case FBC_UNSUPPORTED: | |
1106 | seq_puts(m, "unsupported by this chipset"); | |
1107 | break; | |
bed4a673 | 1108 | case FBC_NO_OUTPUT: |
267f0c90 | 1109 | seq_puts(m, "no outputs"); |
bed4a673 | 1110 | break; |
b5e50c3f | 1111 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1112 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1113 | break; |
1114 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1115 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1116 | break; |
1117 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1118 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1119 | break; |
1120 | case FBC_BAD_PLANE: | |
267f0c90 | 1121 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1122 | break; |
1123 | case FBC_NOT_TILED: | |
267f0c90 | 1124 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1125 | break; |
9c928d16 | 1126 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1127 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1128 | break; |
c1a9f047 | 1129 | case FBC_MODULE_PARAM: |
267f0c90 | 1130 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1131 | break; |
8a5729a3 | 1132 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1133 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1134 | break; |
b5e50c3f | 1135 | default: |
267f0c90 | 1136 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1137 | } |
267f0c90 | 1138 | seq_putc(m, '\n'); |
b5e50c3f JB |
1139 | } |
1140 | return 0; | |
1141 | } | |
1142 | ||
92d44621 PZ |
1143 | static int i915_ips_status(struct seq_file *m, void *unused) |
1144 | { | |
1145 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1146 | struct drm_device *dev = node->minor->dev; | |
1147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1148 | ||
f5adf94e | 1149 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1150 | seq_puts(m, "not supported\n"); |
1151 | return 0; | |
1152 | } | |
1153 | ||
1154 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1155 | seq_puts(m, "enabled\n"); | |
1156 | else | |
1157 | seq_puts(m, "disabled\n"); | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | ||
4a9bef37 JB |
1162 | static int i915_sr_status(struct seq_file *m, void *unused) |
1163 | { | |
1164 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1165 | struct drm_device *dev = node->minor->dev; | |
1166 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1167 | bool sr_enabled = false; | |
1168 | ||
1398261a | 1169 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1170 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1171 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1172 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1173 | else if (IS_I915GM(dev)) | |
1174 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1175 | else if (IS_PINEVIEW(dev)) | |
1176 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1177 | ||
5ba2aaaa CW |
1178 | seq_printf(m, "self-refresh: %s\n", |
1179 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1180 | |
1181 | return 0; | |
1182 | } | |
1183 | ||
7648fa99 JB |
1184 | static int i915_emon_status(struct seq_file *m, void *unused) |
1185 | { | |
1186 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1187 | struct drm_device *dev = node->minor->dev; | |
1188 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1189 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1190 | int ret; |
1191 | ||
582be6b4 CW |
1192 | if (!IS_GEN5(dev)) |
1193 | return -ENODEV; | |
1194 | ||
de227ef0 CW |
1195 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1196 | if (ret) | |
1197 | return ret; | |
7648fa99 JB |
1198 | |
1199 | temp = i915_mch_val(dev_priv); | |
1200 | chipset = i915_chipset_val(dev_priv); | |
1201 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1202 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1203 | |
1204 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1205 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1206 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1207 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1208 | ||
1209 | return 0; | |
1210 | } | |
1211 | ||
23b2f8bb JB |
1212 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1213 | { | |
1214 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1215 | struct drm_device *dev = node->minor->dev; | |
1216 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1217 | int ret; | |
1218 | int gpu_freq, ia_freq; | |
1219 | ||
1c70c0ce | 1220 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1221 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1222 | return 0; |
1223 | } | |
1224 | ||
4fc688ce | 1225 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1226 | if (ret) |
1227 | return ret; | |
1228 | ||
267f0c90 | 1229 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1230 | |
c6a828d3 DV |
1231 | for (gpu_freq = dev_priv->rps.min_delay; |
1232 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1233 | gpu_freq++) { |
42c0526c BW |
1234 | ia_freq = gpu_freq; |
1235 | sandybridge_pcode_read(dev_priv, | |
1236 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1237 | &ia_freq); | |
3ebecd07 CW |
1238 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1239 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1240 | ((ia_freq >> 0) & 0xff) * 100, | |
1241 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1242 | } |
1243 | ||
4fc688ce | 1244 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1245 | |
1246 | return 0; | |
1247 | } | |
1248 | ||
7648fa99 JB |
1249 | static int i915_gfxec(struct seq_file *m, void *unused) |
1250 | { | |
1251 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1252 | struct drm_device *dev = node->minor->dev; | |
1253 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1254 | int ret; |
1255 | ||
1256 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1257 | if (ret) | |
1258 | return ret; | |
7648fa99 JB |
1259 | |
1260 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1261 | ||
616fdb5a BW |
1262 | mutex_unlock(&dev->struct_mutex); |
1263 | ||
7648fa99 JB |
1264 | return 0; |
1265 | } | |
1266 | ||
44834a67 CW |
1267 | static int i915_opregion(struct seq_file *m, void *unused) |
1268 | { | |
1269 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1270 | struct drm_device *dev = node->minor->dev; | |
1271 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1272 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1273 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1274 | int ret; |
1275 | ||
0d38f009 DV |
1276 | if (data == NULL) |
1277 | return -ENOMEM; | |
1278 | ||
44834a67 CW |
1279 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1280 | if (ret) | |
0d38f009 | 1281 | goto out; |
44834a67 | 1282 | |
0d38f009 DV |
1283 | if (opregion->header) { |
1284 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1285 | seq_write(m, data, OPREGION_SIZE); | |
1286 | } | |
44834a67 CW |
1287 | |
1288 | mutex_unlock(&dev->struct_mutex); | |
1289 | ||
0d38f009 DV |
1290 | out: |
1291 | kfree(data); | |
44834a67 CW |
1292 | return 0; |
1293 | } | |
1294 | ||
37811fcc CW |
1295 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1296 | { | |
1297 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1298 | struct drm_device *dev = node->minor->dev; | |
1299 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1300 | struct intel_fbdev *ifbdev; | |
1301 | struct intel_framebuffer *fb; | |
1302 | int ret; | |
1303 | ||
1304 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1305 | if (ret) | |
1306 | return ret; | |
1307 | ||
1308 | ifbdev = dev_priv->fbdev; | |
1309 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1310 | ||
623f9783 | 1311 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1312 | fb->base.width, |
1313 | fb->base.height, | |
1314 | fb->base.depth, | |
623f9783 DV |
1315 | fb->base.bits_per_pixel, |
1316 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1317 | describe_obj(m, fb->obj); |
267f0c90 | 1318 | seq_putc(m, '\n'); |
4b096ac1 | 1319 | mutex_unlock(&dev->mode_config.mutex); |
37811fcc | 1320 | |
4b096ac1 | 1321 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc CW |
1322 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
1323 | if (&fb->base == ifbdev->helper.fb) | |
1324 | continue; | |
1325 | ||
623f9783 | 1326 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1327 | fb->base.width, |
1328 | fb->base.height, | |
1329 | fb->base.depth, | |
623f9783 DV |
1330 | fb->base.bits_per_pixel, |
1331 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1332 | describe_obj(m, fb->obj); |
267f0c90 | 1333 | seq_putc(m, '\n'); |
37811fcc | 1334 | } |
4b096ac1 | 1335 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1336 | |
1337 | return 0; | |
1338 | } | |
1339 | ||
e76d3630 BW |
1340 | static int i915_context_status(struct seq_file *m, void *unused) |
1341 | { | |
1342 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1343 | struct drm_device *dev = node->minor->dev; | |
1344 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 BW |
1345 | struct intel_ring_buffer *ring; |
1346 | int ret, i; | |
e76d3630 BW |
1347 | |
1348 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1349 | if (ret) | |
1350 | return ret; | |
1351 | ||
3e373948 | 1352 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1353 | seq_puts(m, "power context "); |
3e373948 | 1354 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1355 | seq_putc(m, '\n'); |
dc501fbc | 1356 | } |
e76d3630 | 1357 | |
3e373948 | 1358 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1359 | seq_puts(m, "render context "); |
3e373948 | 1360 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1361 | seq_putc(m, '\n'); |
dc501fbc | 1362 | } |
e76d3630 | 1363 | |
a168c293 BW |
1364 | for_each_ring(ring, dev_priv, i) { |
1365 | if (ring->default_context) { | |
1366 | seq_printf(m, "HW default context %s ring ", ring->name); | |
1367 | describe_obj(m, ring->default_context->obj); | |
267f0c90 | 1368 | seq_putc(m, '\n'); |
a168c293 BW |
1369 | } |
1370 | } | |
1371 | ||
e76d3630 BW |
1372 | mutex_unlock(&dev->mode_config.mutex); |
1373 | ||
1374 | return 0; | |
1375 | } | |
1376 | ||
6d794d42 BW |
1377 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1378 | { | |
1379 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1380 | struct drm_device *dev = node->minor->dev; | |
1381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9f1f46a4 | 1382 | unsigned forcewake_count; |
6d794d42 | 1383 | |
907b28c5 CW |
1384 | spin_lock_irq(&dev_priv->uncore.lock); |
1385 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1386 | spin_unlock_irq(&dev_priv->uncore.lock); | |
6d794d42 | 1387 | |
9f1f46a4 | 1388 | seq_printf(m, "forcewake count = %u\n", forcewake_count); |
6d794d42 BW |
1389 | |
1390 | return 0; | |
1391 | } | |
1392 | ||
ea16a3cd DV |
1393 | static const char *swizzle_string(unsigned swizzle) |
1394 | { | |
aee56cff | 1395 | switch (swizzle) { |
ea16a3cd DV |
1396 | case I915_BIT_6_SWIZZLE_NONE: |
1397 | return "none"; | |
1398 | case I915_BIT_6_SWIZZLE_9: | |
1399 | return "bit9"; | |
1400 | case I915_BIT_6_SWIZZLE_9_10: | |
1401 | return "bit9/bit10"; | |
1402 | case I915_BIT_6_SWIZZLE_9_11: | |
1403 | return "bit9/bit11"; | |
1404 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1405 | return "bit9/bit10/bit11"; | |
1406 | case I915_BIT_6_SWIZZLE_9_17: | |
1407 | return "bit9/bit17"; | |
1408 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1409 | return "bit9/bit10/bit17"; | |
1410 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1411 | return "unknown"; |
ea16a3cd DV |
1412 | } |
1413 | ||
1414 | return "bug"; | |
1415 | } | |
1416 | ||
1417 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1418 | { | |
1419 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1420 | struct drm_device *dev = node->minor->dev; | |
1421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1422 | int ret; |
1423 | ||
1424 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1425 | if (ret) | |
1426 | return ret; | |
ea16a3cd | 1427 | |
ea16a3cd DV |
1428 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1429 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1430 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1431 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1432 | ||
1433 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1434 | seq_printf(m, "DDC = 0x%08x\n", | |
1435 | I915_READ(DCC)); | |
1436 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1437 | I915_READ16(C0DRB3)); | |
1438 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1439 | I915_READ16(C1DRB3)); | |
3fa7d235 DV |
1440 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1441 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", | |
1442 | I915_READ(MAD_DIMM_C0)); | |
1443 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1444 | I915_READ(MAD_DIMM_C1)); | |
1445 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1446 | I915_READ(MAD_DIMM_C2)); | |
1447 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1448 | I915_READ(TILECTL)); | |
1449 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1450 | I915_READ(ARB_MODE)); | |
1451 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", | |
1452 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1453 | } |
1454 | mutex_unlock(&dev->struct_mutex); | |
1455 | ||
1456 | return 0; | |
1457 | } | |
1458 | ||
3cf17fc5 DV |
1459 | static int i915_ppgtt_info(struct seq_file *m, void *data) |
1460 | { | |
1461 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1462 | struct drm_device *dev = node->minor->dev; | |
1463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1464 | struct intel_ring_buffer *ring; | |
1465 | int i, ret; | |
1466 | ||
1467 | ||
1468 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1469 | if (ret) | |
1470 | return ret; | |
1471 | if (INTEL_INFO(dev)->gen == 6) | |
1472 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1473 | ||
a2c7f6fd | 1474 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1475 | seq_printf(m, "%s\n", ring->name); |
1476 | if (INTEL_INFO(dev)->gen == 7) | |
1477 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1478 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1479 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1480 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1481 | } | |
1482 | if (dev_priv->mm.aliasing_ppgtt) { | |
1483 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1484 | ||
267f0c90 | 1485 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1486 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1487 | } | |
1488 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
1489 | mutex_unlock(&dev->struct_mutex); | |
1490 | ||
1491 | return 0; | |
1492 | } | |
1493 | ||
57f350b6 JB |
1494 | static int i915_dpio_info(struct seq_file *m, void *data) |
1495 | { | |
1496 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1497 | struct drm_device *dev = node->minor->dev; | |
1498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1499 | int ret; | |
1500 | ||
1501 | ||
1502 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1503 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1504 | return 0; |
1505 | } | |
1506 | ||
09153000 | 1507 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1508 | if (ret) |
1509 | return ret; | |
1510 | ||
1511 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1512 | ||
1513 | seq_printf(m, "DPIO_DIV_A: 0x%08x\n", | |
ae99258f | 1514 | vlv_dpio_read(dev_priv, _DPIO_DIV_A)); |
57f350b6 | 1515 | seq_printf(m, "DPIO_DIV_B: 0x%08x\n", |
ae99258f | 1516 | vlv_dpio_read(dev_priv, _DPIO_DIV_B)); |
57f350b6 JB |
1517 | |
1518 | seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", | |
ae99258f | 1519 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_A)); |
57f350b6 | 1520 | seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", |
ae99258f | 1521 | vlv_dpio_read(dev_priv, _DPIO_REFSFR_B)); |
57f350b6 JB |
1522 | |
1523 | seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", | |
ae99258f | 1524 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A)); |
57f350b6 | 1525 | seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", |
ae99258f | 1526 | vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B)); |
57f350b6 | 1527 | |
4abb2c39 VS |
1528 | seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", |
1529 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A)); | |
1530 | seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", | |
1531 | vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B)); | |
57f350b6 JB |
1532 | |
1533 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
ae99258f | 1534 | vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE)); |
57f350b6 | 1535 | |
09153000 | 1536 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1537 | |
1538 | return 0; | |
1539 | } | |
1540 | ||
63573eb7 BW |
1541 | static int i915_llc(struct seq_file *m, void *data) |
1542 | { | |
1543 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1544 | struct drm_device *dev = node->minor->dev; | |
1545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1546 | ||
1547 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1548 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1549 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1550 | ||
1551 | return 0; | |
1552 | } | |
1553 | ||
e91fd8c6 RV |
1554 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1555 | { | |
1556 | struct drm_info_node *node = m->private; | |
1557 | struct drm_device *dev = node->minor->dev; | |
1558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3f51e471 | 1559 | u32 psrstat, psrperf; |
e91fd8c6 RV |
1560 | |
1561 | if (!IS_HASWELL(dev)) { | |
1562 | seq_puts(m, "PSR not supported on this platform\n"); | |
3f51e471 RV |
1563 | } else if (IS_HASWELL(dev) && I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE) { |
1564 | seq_puts(m, "PSR enabled\n"); | |
1565 | } else { | |
1566 | seq_puts(m, "PSR disabled: "); | |
1567 | switch (dev_priv->no_psr_reason) { | |
1568 | case PSR_NO_SOURCE: | |
1569 | seq_puts(m, "not supported on this platform"); | |
1570 | break; | |
1571 | case PSR_NO_SINK: | |
1572 | seq_puts(m, "not supported by panel"); | |
1573 | break; | |
105b7c11 RV |
1574 | case PSR_MODULE_PARAM: |
1575 | seq_puts(m, "disabled by flag"); | |
1576 | break; | |
3f51e471 RV |
1577 | case PSR_CRTC_NOT_ACTIVE: |
1578 | seq_puts(m, "crtc not active"); | |
1579 | break; | |
1580 | case PSR_PWR_WELL_ENABLED: | |
1581 | seq_puts(m, "power well enabled"); | |
1582 | break; | |
1583 | case PSR_NOT_TILED: | |
1584 | seq_puts(m, "not tiled"); | |
1585 | break; | |
1586 | case PSR_SPRITE_ENABLED: | |
1587 | seq_puts(m, "sprite enabled"); | |
1588 | break; | |
1589 | case PSR_S3D_ENABLED: | |
1590 | seq_puts(m, "stereo 3d enabled"); | |
1591 | break; | |
1592 | case PSR_INTERLACED_ENABLED: | |
1593 | seq_puts(m, "interlaced enabled"); | |
1594 | break; | |
1595 | case PSR_HSW_NOT_DDIA: | |
1596 | seq_puts(m, "HSW ties PSR to DDI A (eDP)"); | |
1597 | break; | |
1598 | default: | |
1599 | seq_puts(m, "unknown reason"); | |
1600 | } | |
1601 | seq_puts(m, "\n"); | |
e91fd8c6 RV |
1602 | return 0; |
1603 | } | |
1604 | ||
e91fd8c6 RV |
1605 | psrstat = I915_READ(EDP_PSR_STATUS_CTL); |
1606 | ||
1607 | seq_puts(m, "PSR Current State: "); | |
1608 | switch (psrstat & EDP_PSR_STATUS_STATE_MASK) { | |
1609 | case EDP_PSR_STATUS_STATE_IDLE: | |
1610 | seq_puts(m, "Reset state\n"); | |
1611 | break; | |
1612 | case EDP_PSR_STATUS_STATE_SRDONACK: | |
1613 | seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n"); | |
1614 | break; | |
1615 | case EDP_PSR_STATUS_STATE_SRDENT: | |
1616 | seq_puts(m, "SRD entry\n"); | |
1617 | break; | |
1618 | case EDP_PSR_STATUS_STATE_BUFOFF: | |
1619 | seq_puts(m, "Wait for buffer turn off\n"); | |
1620 | break; | |
1621 | case EDP_PSR_STATUS_STATE_BUFON: | |
1622 | seq_puts(m, "Wait for buffer turn on\n"); | |
1623 | break; | |
1624 | case EDP_PSR_STATUS_STATE_AUXACK: | |
1625 | seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n"); | |
1626 | break; | |
1627 | case EDP_PSR_STATUS_STATE_SRDOFFACK: | |
1628 | seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n"); | |
1629 | break; | |
1630 | default: | |
1631 | seq_puts(m, "Unknown\n"); | |
1632 | break; | |
1633 | } | |
1634 | ||
1635 | seq_puts(m, "Link Status: "); | |
1636 | switch (psrstat & EDP_PSR_STATUS_LINK_MASK) { | |
1637 | case EDP_PSR_STATUS_LINK_FULL_OFF: | |
1638 | seq_puts(m, "Link is fully off\n"); | |
1639 | break; | |
1640 | case EDP_PSR_STATUS_LINK_FULL_ON: | |
1641 | seq_puts(m, "Link is fully on\n"); | |
1642 | break; | |
1643 | case EDP_PSR_STATUS_LINK_STANDBY: | |
1644 | seq_puts(m, "Link is in standby\n"); | |
1645 | break; | |
1646 | default: | |
1647 | seq_puts(m, "Unknown\n"); | |
1648 | break; | |
1649 | } | |
1650 | ||
1651 | seq_printf(m, "PSR Entry Count: %u\n", | |
1652 | psrstat >> EDP_PSR_STATUS_COUNT_SHIFT & | |
1653 | EDP_PSR_STATUS_COUNT_MASK); | |
1654 | ||
1655 | seq_printf(m, "Max Sleep Timer Counter: %u\n", | |
1656 | psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT & | |
1657 | EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK); | |
1658 | ||
1659 | seq_printf(m, "Had AUX error: %s\n", | |
1660 | yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR)); | |
1661 | ||
1662 | seq_printf(m, "Sending AUX: %s\n", | |
1663 | yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING)); | |
1664 | ||
1665 | seq_printf(m, "Sending Idle: %s\n", | |
1666 | yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE)); | |
1667 | ||
1668 | seq_printf(m, "Sending TP2 TP3: %s\n", | |
1669 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3)); | |
1670 | ||
1671 | seq_printf(m, "Sending TP1: %s\n", | |
1672 | yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1)); | |
1673 | ||
1674 | seq_printf(m, "Idle Count: %u\n", | |
1675 | psrstat & EDP_PSR_STATUS_IDLE_MASK); | |
1676 | ||
1677 | psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK; | |
1678 | seq_printf(m, "Performance Counter: %u\n", psrperf); | |
1679 | ||
1680 | return 0; | |
1681 | } | |
1682 | ||
647416f9 KC |
1683 | static int |
1684 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 1685 | { |
647416f9 | 1686 | struct drm_device *dev = data; |
f3cd474b | 1687 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 1688 | |
647416f9 | 1689 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 1690 | |
647416f9 | 1691 | return 0; |
f3cd474b CW |
1692 | } |
1693 | ||
647416f9 KC |
1694 | static int |
1695 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 1696 | { |
647416f9 | 1697 | struct drm_device *dev = data; |
f3cd474b | 1698 | |
647416f9 | 1699 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 1700 | i915_handle_error(dev, val); |
f3cd474b | 1701 | |
647416f9 | 1702 | return 0; |
f3cd474b CW |
1703 | } |
1704 | ||
647416f9 KC |
1705 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
1706 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 1707 | "%llu\n"); |
f3cd474b | 1708 | |
647416f9 KC |
1709 | static int |
1710 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 1711 | { |
647416f9 | 1712 | struct drm_device *dev = data; |
e5eb3d63 | 1713 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 1714 | |
647416f9 | 1715 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 1716 | |
647416f9 | 1717 | return 0; |
e5eb3d63 DV |
1718 | } |
1719 | ||
647416f9 KC |
1720 | static int |
1721 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 1722 | { |
647416f9 | 1723 | struct drm_device *dev = data; |
e5eb3d63 | 1724 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1725 | int ret; |
e5eb3d63 | 1726 | |
647416f9 | 1727 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 1728 | |
22bcfc6a DV |
1729 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1730 | if (ret) | |
1731 | return ret; | |
1732 | ||
99584db3 | 1733 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
1734 | mutex_unlock(&dev->struct_mutex); |
1735 | ||
647416f9 | 1736 | return 0; |
e5eb3d63 DV |
1737 | } |
1738 | ||
647416f9 KC |
1739 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
1740 | i915_ring_stop_get, i915_ring_stop_set, | |
1741 | "0x%08llx\n"); | |
d5442303 | 1742 | |
dd624afd CW |
1743 | #define DROP_UNBOUND 0x1 |
1744 | #define DROP_BOUND 0x2 | |
1745 | #define DROP_RETIRE 0x4 | |
1746 | #define DROP_ACTIVE 0x8 | |
1747 | #define DROP_ALL (DROP_UNBOUND | \ | |
1748 | DROP_BOUND | \ | |
1749 | DROP_RETIRE | \ | |
1750 | DROP_ACTIVE) | |
647416f9 KC |
1751 | static int |
1752 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 1753 | { |
647416f9 | 1754 | *val = DROP_ALL; |
dd624afd | 1755 | |
647416f9 | 1756 | return 0; |
dd624afd CW |
1757 | } |
1758 | ||
647416f9 KC |
1759 | static int |
1760 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 1761 | { |
647416f9 | 1762 | struct drm_device *dev = data; |
dd624afd CW |
1763 | struct drm_i915_private *dev_priv = dev->dev_private; |
1764 | struct drm_i915_gem_object *obj, *next; | |
5cef07e1 | 1765 | struct i915_address_space *vm = &dev_priv->gtt.base; |
647416f9 | 1766 | int ret; |
dd624afd | 1767 | |
647416f9 | 1768 | DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
1769 | |
1770 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
1771 | * on ioctls on -EAGAIN. */ | |
1772 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1773 | if (ret) | |
1774 | return ret; | |
1775 | ||
1776 | if (val & DROP_ACTIVE) { | |
1777 | ret = i915_gpu_idle(dev); | |
1778 | if (ret) | |
1779 | goto unlock; | |
1780 | } | |
1781 | ||
1782 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
1783 | i915_gem_retire_requests(dev); | |
1784 | ||
1785 | if (val & DROP_BOUND) { | |
5cef07e1 | 1786 | list_for_each_entry_safe(obj, next, &vm->inactive_list, |
31a46c9c BW |
1787 | mm_list) { |
1788 | if (obj->pin_count) | |
1789 | continue; | |
1790 | ||
1791 | ret = i915_gem_object_unbind(obj); | |
1792 | if (ret) | |
1793 | goto unlock; | |
1794 | } | |
dd624afd CW |
1795 | } |
1796 | ||
1797 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
1798 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
1799 | global_list) | |
dd624afd CW |
1800 | if (obj->pages_pin_count == 0) { |
1801 | ret = i915_gem_object_put_pages(obj); | |
1802 | if (ret) | |
1803 | goto unlock; | |
1804 | } | |
1805 | } | |
1806 | ||
1807 | unlock: | |
1808 | mutex_unlock(&dev->struct_mutex); | |
1809 | ||
647416f9 | 1810 | return ret; |
dd624afd CW |
1811 | } |
1812 | ||
647416f9 KC |
1813 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
1814 | i915_drop_caches_get, i915_drop_caches_set, | |
1815 | "0x%08llx\n"); | |
dd624afd | 1816 | |
647416f9 KC |
1817 | static int |
1818 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 1819 | { |
647416f9 | 1820 | struct drm_device *dev = data; |
358733e9 | 1821 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 1822 | int ret; |
004777cb DV |
1823 | |
1824 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1825 | return -ENODEV; | |
1826 | ||
4fc688ce | 1827 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1828 | if (ret) |
1829 | return ret; | |
358733e9 | 1830 | |
0a073b84 JB |
1831 | if (IS_VALLEYVIEW(dev)) |
1832 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
1833 | dev_priv->rps.max_delay); | |
1834 | else | |
1835 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 1836 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1837 | |
647416f9 | 1838 | return 0; |
358733e9 JB |
1839 | } |
1840 | ||
647416f9 KC |
1841 | static int |
1842 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 1843 | { |
647416f9 | 1844 | struct drm_device *dev = data; |
358733e9 | 1845 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1846 | int ret; |
004777cb DV |
1847 | |
1848 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1849 | return -ENODEV; | |
358733e9 | 1850 | |
647416f9 | 1851 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 1852 | |
4fc688ce | 1853 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1854 | if (ret) |
1855 | return ret; | |
1856 | ||
358733e9 JB |
1857 | /* |
1858 | * Turbo will still be enabled, but won't go above the set value. | |
1859 | */ | |
0a073b84 JB |
1860 | if (IS_VALLEYVIEW(dev)) { |
1861 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
1862 | dev_priv->rps.max_delay = val; | |
1863 | gen6_set_rps(dev, val); | |
1864 | } else { | |
1865 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
1866 | dev_priv->rps.max_delay = val; | |
1867 | gen6_set_rps(dev, val); | |
1868 | } | |
1869 | ||
4fc688ce | 1870 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 1871 | |
647416f9 | 1872 | return 0; |
358733e9 JB |
1873 | } |
1874 | ||
647416f9 KC |
1875 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
1876 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 1877 | "%llu\n"); |
358733e9 | 1878 | |
647416f9 KC |
1879 | static int |
1880 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 1881 | { |
647416f9 | 1882 | struct drm_device *dev = data; |
1523c310 | 1883 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 1884 | int ret; |
004777cb DV |
1885 | |
1886 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1887 | return -ENODEV; | |
1888 | ||
4fc688ce | 1889 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1890 | if (ret) |
1891 | return ret; | |
1523c310 | 1892 | |
0a073b84 JB |
1893 | if (IS_VALLEYVIEW(dev)) |
1894 | *val = vlv_gpu_freq(dev_priv->mem_freq, | |
1895 | dev_priv->rps.min_delay); | |
1896 | else | |
1897 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 1898 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 1899 | |
647416f9 | 1900 | return 0; |
1523c310 JB |
1901 | } |
1902 | ||
647416f9 KC |
1903 | static int |
1904 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 1905 | { |
647416f9 | 1906 | struct drm_device *dev = data; |
1523c310 | 1907 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 1908 | int ret; |
004777cb DV |
1909 | |
1910 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
1911 | return -ENODEV; | |
1523c310 | 1912 | |
647416f9 | 1913 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 1914 | |
4fc688ce | 1915 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
1916 | if (ret) |
1917 | return ret; | |
1918 | ||
1523c310 JB |
1919 | /* |
1920 | * Turbo will still be enabled, but won't go below the set value. | |
1921 | */ | |
0a073b84 JB |
1922 | if (IS_VALLEYVIEW(dev)) { |
1923 | val = vlv_freq_opcode(dev_priv->mem_freq, val); | |
1924 | dev_priv->rps.min_delay = val; | |
1925 | valleyview_set_rps(dev, val); | |
1926 | } else { | |
1927 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
1928 | dev_priv->rps.min_delay = val; | |
1929 | gen6_set_rps(dev, val); | |
1930 | } | |
4fc688ce | 1931 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 1932 | |
647416f9 | 1933 | return 0; |
1523c310 JB |
1934 | } |
1935 | ||
647416f9 KC |
1936 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
1937 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 1938 | "%llu\n"); |
1523c310 | 1939 | |
647416f9 KC |
1940 | static int |
1941 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 1942 | { |
647416f9 | 1943 | struct drm_device *dev = data; |
07b7ddd9 | 1944 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 1945 | u32 snpcr; |
647416f9 | 1946 | int ret; |
07b7ddd9 | 1947 | |
004777cb DV |
1948 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
1949 | return -ENODEV; | |
1950 | ||
22bcfc6a DV |
1951 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1952 | if (ret) | |
1953 | return ret; | |
1954 | ||
07b7ddd9 JB |
1955 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
1956 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
1957 | ||
647416f9 | 1958 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 1959 | |
647416f9 | 1960 | return 0; |
07b7ddd9 JB |
1961 | } |
1962 | ||
647416f9 KC |
1963 | static int |
1964 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 1965 | { |
647416f9 | 1966 | struct drm_device *dev = data; |
07b7ddd9 | 1967 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 1968 | u32 snpcr; |
07b7ddd9 | 1969 | |
004777cb DV |
1970 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
1971 | return -ENODEV; | |
1972 | ||
647416f9 | 1973 | if (val > 3) |
07b7ddd9 JB |
1974 | return -EINVAL; |
1975 | ||
647416f9 | 1976 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
1977 | |
1978 | /* Update the cache sharing policy here as well */ | |
1979 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
1980 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
1981 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
1982 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
1983 | ||
647416f9 | 1984 | return 0; |
07b7ddd9 JB |
1985 | } |
1986 | ||
647416f9 KC |
1987 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
1988 | i915_cache_sharing_get, i915_cache_sharing_set, | |
1989 | "%llu\n"); | |
07b7ddd9 | 1990 | |
f3cd474b CW |
1991 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
1992 | * allocated we need to hook into the minor for release. */ | |
1993 | static int | |
1994 | drm_add_fake_info_node(struct drm_minor *minor, | |
1995 | struct dentry *ent, | |
1996 | const void *key) | |
1997 | { | |
1998 | struct drm_info_node *node; | |
1999 | ||
2000 | node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL); | |
2001 | if (node == NULL) { | |
2002 | debugfs_remove(ent); | |
2003 | return -ENOMEM; | |
2004 | } | |
2005 | ||
2006 | node->minor = minor; | |
2007 | node->dent = ent; | |
2008 | node->info_ent = (void *) key; | |
b3e067c0 MS |
2009 | |
2010 | mutex_lock(&minor->debugfs_lock); | |
2011 | list_add(&node->list, &minor->debugfs_list); | |
2012 | mutex_unlock(&minor->debugfs_lock); | |
f3cd474b CW |
2013 | |
2014 | return 0; | |
2015 | } | |
2016 | ||
6d794d42 BW |
2017 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
2018 | { | |
2019 | struct drm_device *dev = inode->i_private; | |
2020 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 2021 | |
075edca4 | 2022 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2023 | return 0; |
2024 | ||
6d794d42 | 2025 | gen6_gt_force_wake_get(dev_priv); |
6d794d42 BW |
2026 | |
2027 | return 0; | |
2028 | } | |
2029 | ||
c43b5634 | 2030 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
2031 | { |
2032 | struct drm_device *dev = inode->i_private; | |
2033 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2034 | ||
075edca4 | 2035 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
2036 | return 0; |
2037 | ||
6d794d42 | 2038 | gen6_gt_force_wake_put(dev_priv); |
6d794d42 BW |
2039 | |
2040 | return 0; | |
2041 | } | |
2042 | ||
2043 | static const struct file_operations i915_forcewake_fops = { | |
2044 | .owner = THIS_MODULE, | |
2045 | .open = i915_forcewake_open, | |
2046 | .release = i915_forcewake_release, | |
2047 | }; | |
2048 | ||
2049 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
2050 | { | |
2051 | struct drm_device *dev = minor->dev; | |
2052 | struct dentry *ent; | |
2053 | ||
2054 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 2055 | S_IRUSR, |
6d794d42 BW |
2056 | root, dev, |
2057 | &i915_forcewake_fops); | |
2058 | if (IS_ERR(ent)) | |
2059 | return PTR_ERR(ent); | |
2060 | ||
8eb57294 | 2061 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
2062 | } |
2063 | ||
6a9c308d DV |
2064 | static int i915_debugfs_create(struct dentry *root, |
2065 | struct drm_minor *minor, | |
2066 | const char *name, | |
2067 | const struct file_operations *fops) | |
07b7ddd9 JB |
2068 | { |
2069 | struct drm_device *dev = minor->dev; | |
2070 | struct dentry *ent; | |
2071 | ||
6a9c308d | 2072 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
2073 | S_IRUGO | S_IWUSR, |
2074 | root, dev, | |
6a9c308d | 2075 | fops); |
07b7ddd9 JB |
2076 | if (IS_ERR(ent)) |
2077 | return PTR_ERR(ent); | |
2078 | ||
6a9c308d | 2079 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
2080 | } |
2081 | ||
27c202ad | 2082 | static struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 2083 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 2084 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 2085 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 2086 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 2087 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 2088 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
4e5359cd | 2089 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
2090 | {"i915_gem_request", i915_gem_request_info, 0}, |
2091 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 2092 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 2093 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
2094 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
2095 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
2096 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 2097 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
2098 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
2099 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
2100 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
2101 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
2102 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 2103 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 2104 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 2105 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 2106 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 2107 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 2108 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 2109 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 2110 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 2111 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 2112 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 2113 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 2114 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 2115 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 2116 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 2117 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
2017263e | 2118 | }; |
27c202ad | 2119 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 2120 | |
34b9674c DV |
2121 | struct i915_debugfs_files { |
2122 | const char *name; | |
2123 | const struct file_operations *fops; | |
2124 | } i915_debugfs_files[] = { | |
2125 | {"i915_wedged", &i915_wedged_fops}, | |
2126 | {"i915_max_freq", &i915_max_freq_fops}, | |
2127 | {"i915_min_freq", &i915_min_freq_fops}, | |
2128 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
2129 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
2130 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, | |
2131 | {"i915_error_state", &i915_error_state_fops}, | |
2132 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
2133 | }; | |
2134 | ||
27c202ad | 2135 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 2136 | { |
34b9674c | 2137 | int ret, i; |
f3cd474b | 2138 | |
6d794d42 | 2139 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
2140 | if (ret) |
2141 | return ret; | |
6a9c308d | 2142 | |
34b9674c DV |
2143 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2144 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
2145 | i915_debugfs_files[i].name, | |
2146 | i915_debugfs_files[i].fops); | |
2147 | if (ret) | |
2148 | return ret; | |
2149 | } | |
40633219 | 2150 | |
27c202ad BG |
2151 | return drm_debugfs_create_files(i915_debugfs_list, |
2152 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
2153 | minor->debugfs_root, minor); |
2154 | } | |
2155 | ||
27c202ad | 2156 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 2157 | { |
34b9674c DV |
2158 | int i; |
2159 | ||
27c202ad BG |
2160 | drm_debugfs_remove_files(i915_debugfs_list, |
2161 | I915_DEBUGFS_ENTRIES, minor); | |
6d794d42 BW |
2162 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
2163 | 1, minor); | |
34b9674c DV |
2164 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
2165 | struct drm_info_list *info_list = | |
2166 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
2167 | ||
2168 | drm_debugfs_remove_files(info_list, 1, minor); | |
2169 | } | |
2017263e BG |
2170 | } |
2171 | ||
2172 | #endif /* CONFIG_DEBUG_FS */ |