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drm/i915: Drop the 64k linear scanout alignment on gen2/3
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
baaa5cfb 99 if (obj->pin_display)
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
b4716185
CW		 123 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
124 struct intel_engine_cs *ring;
1d693bcc 125 struct i915_vma *vma;
d7f46fc4 126 int pin_count = 0;
b4716185 127 int i;
d7f46fc4 128
b4716185 129 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 130 &obj->base,
481a3d43 131 obj->active ? "*" : " ",
37811fcc
CW		 132 get_pin_flag(obj),
133 get_tiling_flag(obj),
1d693bcc 134 get_global_flag(obj),
a05a5862 135 obj->base.size / 1024,
37811fcc 136 obj->base.read_domains,
b4716185
CW		 137 obj->base.write_domain);
138 for_each_ring(ring, dev_priv, i)
139 seq_printf(m, "%x ",
140 i915_gem_request_get_seqno(obj->last_read_req[i]));
141 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 142 i915_gem_request_get_seqno(obj->last_write_req),
143 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 144 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 145 obj->dirty ? " dirty" : "",
146 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
147 if (obj->base.name)
148 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 149 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 150 if (vma->pin_count > 0)
151 pin_count++;
ba0635ff
DC		 152 }
153 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 154 if (obj->pin_display)
155 seq_printf(m, " (display)");
37811fcc
CW		 156 if (obj->fence_reg != I915_FENCE_REG_NONE)
157 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc 158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
8d2fdc3f
TU		 159 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
160 i915_is_ggtt(vma->vm) ? "g" : "pp",
161 vma->node.start, vma->node.size);
162 if (i915_is_ggtt(vma->vm))
163 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
1d693bcc 164 else
8d2fdc3f 165 seq_puts(m, ")");
1d693bcc 166 }
c1ad11fc 167 if (obj->stolen)
440fd528 168 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 169 if (obj->pin_display || obj->fault_mappable) {
6299f992 170 char s[3], *t = s;
30154650 171 if (obj->pin_display)
6299f992
CW		 172 *t++ = 'p';
173 if (obj->fault_mappable)
174 *t++ = 'f';
175 *t = '\0';
176 seq_printf(m, " (%s mappable)", s);
177 }
b4716185 178 if (obj->last_write_req != NULL)
41c52415 179 seq_printf(m, " (%s)",
b4716185 180 i915_gem_request_get_ring(obj->last_write_req)->name);
d5a81ef1
DV		 181 if (obj->frontbuffer_bits)
182 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 183}
184
273497e5 185static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 186{
ea0c76f8 187 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 188 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
189 seq_putc(m, ' ');
190}
191
433e12f7 192static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 193{
9f25d007 194 struct drm_info_node *node = m->private;
433e12f7
BG		 195 uintptr_t list = (uintptr_t) node->info_ent->data;
196 struct list_head *head;
2017263e 197 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 198 struct drm_i915_private *dev_priv = dev->dev_private;
199 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 200 struct i915_vma *vma;
8f2480fb
CW		 201 size_t total_obj_size, total_gtt_size;
202 int count, ret;
de227ef0
CW		 203
204 ret = mutex_lock_interruptible(&dev->struct_mutex);
205 if (ret)
206 return ret;
2017263e 207
ca191b13 208 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 209 switch (list) {
210 case ACTIVE_LIST:
267f0c90 211 seq_puts(m, "Active:\n");
5cef07e1 212 head = &vm->active_list;
433e12f7
BG		 213 break;
214 case INACTIVE_LIST:
267f0c90 215 seq_puts(m, "Inactive:\n");
5cef07e1 216 head = &vm->inactive_list;
433e12f7 217 break;
433e12f7 218 default:
de227ef0
CW		 219 mutex_unlock(&dev->struct_mutex);
220 return -EINVAL;
2017263e 221 }
2017263e 222
8f2480fb 223 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 224 list_for_each_entry(vma, head, mm_list) {
225 seq_printf(m, " ");
226 describe_obj(m, vma->obj);
227 seq_printf(m, "\n");
228 total_obj_size += vma->obj->base.size;
229 total_gtt_size += vma->node.size;
8f2480fb 230 count++;
2017263e 231 }
de227ef0 232 mutex_unlock(&dev->struct_mutex);
5e118f41 233
8f2480fb
CW		 234 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
235 count, total_obj_size, total_gtt_size);
2017263e
BG		 236 return 0;
237}
238
6d2b8885
CW		 239static int obj_rank_by_stolen(void *priv,
240 struct list_head *A, struct list_head *B)
241{
242 struct drm_i915_gem_object *a =
b25cb2f8 243 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 244 struct drm_i915_gem_object *b =
b25cb2f8 245 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 246
247 return a->stolen->start - b->stolen->start;
248}
249
250static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
251{
9f25d007 252 struct drm_info_node *node = m->private;
6d2b8885
CW		 253 struct drm_device *dev = node->minor->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 struct drm_i915_gem_object *obj;
256 size_t total_obj_size, total_gtt_size;
257 LIST_HEAD(stolen);
258 int count, ret;
259
260 ret = mutex_lock_interruptible(&dev->struct_mutex);
261 if (ret)
262 return ret;
263
264 total_obj_size = total_gtt_size = count = 0;
265 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
266 if (obj->stolen == NULL)
267 continue;
268
b25cb2f8 269 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 270
271 total_obj_size += obj->base.size;
272 total_gtt_size += i915_gem_obj_ggtt_size(obj);
273 count++;
274 }
275 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
276 if (obj->stolen == NULL)
277 continue;
278
b25cb2f8 279 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 280
281 total_obj_size += obj->base.size;
282 count++;
283 }
284 list_sort(NULL, &stolen, obj_rank_by_stolen);
285 seq_puts(m, "Stolen:\n");
286 while (!list_empty(&stolen)) {
b25cb2f8 287 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 288 seq_puts(m, " ");
289 describe_obj(m, obj);
290 seq_putc(m, '\n');
b25cb2f8 291 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 292 }
293 mutex_unlock(&dev->struct_mutex);
294
295 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
296 count, total_obj_size, total_gtt_size);
297 return 0;
298}
299
6299f992
CW		 300#define count_objects(list, member) do { \
301 list_for_each_entry(obj, list, member) { \
f343c5f6 302 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 303 ++count; \
304 if (obj->map_and_fenceable) { \
f343c5f6 305 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 306 ++mappable_count; \
307 } \
308 } \
0206e353 309} while (0)
6299f992 310
2db8e9d6 311struct file_stats {
6313c204 312 struct drm_i915_file_private *file_priv;
2db8e9d6 313 int count;
c67a17e9
CW		 314 size_t total, unbound;
315 size_t global, shared;
316 size_t active, inactive;
2db8e9d6
CW		 317};
318
319static int per_file_stats(int id, void *ptr, void *data)
320{
321 struct drm_i915_gem_object *obj = ptr;
322 struct file_stats *stats = data;
6313c204 323 struct i915_vma *vma;
2db8e9d6
CW		 324
325 stats->count++;
326 stats->total += obj->base.size;
327
c67a17e9
CW		 328 if (obj->base.name || obj->base.dma_buf)
329 stats->shared += obj->base.size;
330
6313c204
CW		 331 if (USES_FULL_PPGTT(obj->base.dev)) {
332 list_for_each_entry(vma, &obj->vma_list, vma_link) {
333 struct i915_hw_ppgtt *ppgtt;
334
335 if (!drm_mm_node_allocated(&vma->node))
336 continue;
337
338 if (i915_is_ggtt(vma->vm)) {
339 stats->global += obj->base.size;
340 continue;
341 }
342
343 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 344 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 345 continue;
346
41c52415 347 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 348 stats->active += obj->base.size;
349 else
350 stats->inactive += obj->base.size;
351
352 return 0;
353 }
2db8e9d6 354 } else {
6313c204
CW		 355 if (i915_gem_obj_ggtt_bound(obj)) {
356 stats->global += obj->base.size;
41c52415 357 if (obj->active)
6313c204
CW		 358 stats->active += obj->base.size;
359 else
360 stats->inactive += obj->base.size;
361 return 0;
362 }
2db8e9d6
CW		 363 }
364
6313c204
CW		 365 if (!list_empty(&obj->global_list))
366 stats->unbound += obj->base.size;
367
2db8e9d6
CW		 368 return 0;
369}
370
b0da1b79
CW		 371#define print_file_stats(m, name, stats) do { \
372 if (stats.count) \
373 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
374 name, \
375 stats.count, \
376 stats.total, \
377 stats.active, \
378 stats.inactive, \
379 stats.global, \
380 stats.shared, \
381 stats.unbound); \
382} while (0)
493018dc
BV		 383
384static void print_batch_pool_stats(struct seq_file *m,
385 struct drm_i915_private *dev_priv)
386{
387 struct drm_i915_gem_object *obj;
388 struct file_stats stats;
06fbca71 389 struct intel_engine_cs *ring;
8d9d5744 390 int i, j;
493018dc
BV		 391
392 memset(&stats, 0, sizeof(stats));
393
06fbca71 394 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 395 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
396 list_for_each_entry(obj,
397 &ring->batch_pool.cache_list[j],
398 batch_pool_link)
399 per_file_stats(0, obj, &stats);
400 }
06fbca71 401 }
493018dc 402
b0da1b79 403 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 404}
405
ca191b13
BW		 406#define count_vmas(list, member) do { \
407 list_for_each_entry(vma, list, member) { \
408 size += i915_gem_obj_ggtt_size(vma->obj); \
409 ++count; \
410 if (vma->obj->map_and_fenceable) { \
411 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
412 ++mappable_count; \
413 } \
414 } \
415} while (0)
416
417static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 418{
9f25d007 419 struct drm_info_node *node = m->private;
73aa808f
CW		 420 struct drm_device *dev = node->minor->dev;
421 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 422 u32 count, mappable_count, purgeable_count;
423 size_t size, mappable_size, purgeable_size;
6299f992 424 struct drm_i915_gem_object *obj;
5cef07e1 425 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 426 struct drm_file *file;
ca191b13 427 struct i915_vma *vma;
73aa808f
CW		 428 int ret;
429
430 ret = mutex_lock_interruptible(&dev->struct_mutex);
431 if (ret)
432 return ret;
433
6299f992
CW		 434 seq_printf(m, "%u objects, %zu bytes\n",
435 dev_priv->mm.object_count,
436 dev_priv->mm.object_memory);
437
438 size = count = mappable_size = mappable_count = 0;
35c20a60 439 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 440 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
441 count, mappable_count, size, mappable_size);
442
443 size = count = mappable_size = mappable_count = 0;
ca191b13 444 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 445 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
446 count, mappable_count, size, mappable_size);
447
6299f992 448 size = count = mappable_size = mappable_count = 0;
ca191b13 449 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 450 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
451 count, mappable_count, size, mappable_size);
452
b7abb714 453 size = count = purgeable_size = purgeable_count = 0;
35c20a60 454 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 455 size += obj->base.size, ++count;
b7abb714
CW		 456 if (obj->madv == I915_MADV_DONTNEED)
457 purgeable_size += obj->base.size, ++purgeable_count;
458 }
6c085a72
CW		 459 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
460
6299f992 461 size = count = mappable_size = mappable_count = 0;
35c20a60 462 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 463 if (obj->fault_mappable) {
f343c5f6 464 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 465 ++count;
466 }
30154650 467 if (obj->pin_display) {
f343c5f6 468 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 469 ++mappable_count;
470 }
b7abb714
CW		 471 if (obj->madv == I915_MADV_DONTNEED) {
472 purgeable_size += obj->base.size;
473 ++purgeable_count;
474 }
6299f992 475 }
b7abb714
CW		 476 seq_printf(m, "%u purgeable objects, %zu bytes\n",
477 purgeable_count, purgeable_size);
6299f992
CW		 478 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
479 mappable_count, mappable_size);
480 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
481 count, size);
482
93d18799 483 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 484 dev_priv->gtt.base.total,
485 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 486
493018dc
BV		 487 seq_putc(m, '\n');
488 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 489 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
490 struct file_stats stats;
3ec2f427 491 struct task_struct *task;
2db8e9d6
CW		 492
493 memset(&stats, 0, sizeof(stats));
6313c204 494 stats.file_priv = file->driver_priv;
5b5ffff0 495 spin_lock(&file->table_lock);
2db8e9d6 496 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 497 spin_unlock(&file->table_lock);
3ec2f427
TH		 498 /*
499 * Although we have a valid reference on file->pid, that does
500 * not guarantee that the task_struct who called get_pid() is
501 * still alive (e.g. get_pid(current) => fork() => exit()).
502 * Therefore, we need to protect this ->comm access using RCU.
503 */
504 rcu_read_lock();
505 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 506 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 507 rcu_read_unlock();
2db8e9d6
CW		 508 }
509
73aa808f
CW		 510 mutex_unlock(&dev->struct_mutex);
511
512 return 0;
513}
514
aee56cff 515static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 516{
9f25d007 517 struct drm_info_node *node = m->private;
08c18323 518 struct drm_device *dev = node->minor->dev;
1b50247a 519 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 520 struct drm_i915_private *dev_priv = dev->dev_private;
521 struct drm_i915_gem_object *obj;
522 size_t total_obj_size, total_gtt_size;
523 int count, ret;
524
525 ret = mutex_lock_interruptible(&dev->struct_mutex);
526 if (ret)
527 return ret;
528
529 total_obj_size = total_gtt_size = count = 0;
35c20a60 530 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 531 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 532 continue;
533
267f0c90 534 seq_puts(m, " ");
08c18323 535 describe_obj(m, obj);
267f0c90 536 seq_putc(m, '\n');
08c18323 537 total_obj_size += obj->base.size;
f343c5f6 538 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 539 count++;
540 }
541
542 mutex_unlock(&dev->struct_mutex);
543
544 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
545 count, total_obj_size, total_gtt_size);
546
547 return 0;
548}
549
4e5359cd
SF		 550static int i915_gem_pageflip_info(struct seq_file *m, void *data)
551{
9f25d007 552 struct drm_info_node *node = m->private;
4e5359cd 553 struct drm_device *dev = node->minor->dev;
d6bbafa1 554 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 555 struct intel_crtc *crtc;
8a270ebf
DV		 556 int ret;
557
558 ret = mutex_lock_interruptible(&dev->struct_mutex);
559 if (ret)
560 return ret;
4e5359cd 561
d3fcc808 562 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 563 const char pipe = pipe_name(crtc->pipe);
564 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 565 struct intel_unpin_work *work;
566
5e2d7afc 567 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 568 work = crtc->unpin_work;
569 if (work == NULL) {
9db4a9c7 570 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 571 pipe, plane);
572 } else {
d6bbafa1
CW		 573 u32 addr;
574
e7d841ca 575 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 576 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 577 pipe, plane);
578 } else {
9db4a9c7 579 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 580 pipe, plane);
581 }
3a8a946e
DV		 582 if (work->flip_queued_req) {
583 struct intel_engine_cs *ring =
584 i915_gem_request_get_ring(work->flip_queued_req);
585
20e28fba 586 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 587 ring->name,
f06cc1b9 588 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 589 dev_priv->next_seqno,
3a8a946e 590 ring->get_seqno(ring, true),
1b5a433a 591 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 592 } else
593 seq_printf(m, "Flip not associated with any ring\n");
594 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
595 work->flip_queued_vblank,
596 work->flip_ready_vblank,
1e3feefd 597 drm_crtc_vblank_count(&crtc->base));
4e5359cd 598 if (work->enable_stall_check)
267f0c90 599 seq_puts(m, "Stall check enabled, ");
4e5359cd 600 else
267f0c90 601 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 602 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 603
d6bbafa1
CW		 604 if (INTEL_INFO(dev)->gen >= 4)
605 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
606 else
607 addr = I915_READ(DSPADDR(crtc->plane));
608 seq_printf(m, "Current scanout address 0x%08x\n", addr);
609
4e5359cd 610 if (work->pending_flip_obj) {
d6bbafa1
CW		 611 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
612 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 613 }
614 }
5e2d7afc 615 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 616 }
617
8a270ebf
DV		 618 mutex_unlock(&dev->struct_mutex);
619
4e5359cd
SF		 620 return 0;
621}
622
493018dc
BV		 623static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
624{
625 struct drm_info_node *node = m->private;
626 struct drm_device *dev = node->minor->dev;
627 struct drm_i915_private *dev_priv = dev->dev_private;
628 struct drm_i915_gem_object *obj;
06fbca71 629 struct intel_engine_cs *ring;
8d9d5744
CW		 630 int total = 0;
631 int ret, i, j;
493018dc
BV		 632
633 ret = mutex_lock_interruptible(&dev->struct_mutex);
634 if (ret)
635 return ret;
636
06fbca71 637 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 638 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
639 int count;
640
641 count = 0;
642 list_for_each_entry(obj,
643 &ring->batch_pool.cache_list[j],
644 batch_pool_link)
645 count++;
646 seq_printf(m, "%s cache[%d]: %d objects\n",
647 ring->name, j, count);
648
649 list_for_each_entry(obj,
650 &ring->batch_pool.cache_list[j],
651 batch_pool_link) {
652 seq_puts(m, " ");
653 describe_obj(m, obj);
654 seq_putc(m, '\n');
655 }
656
657 total += count;
06fbca71 658 }
493018dc
BV		 659 }
660
8d9d5744 661 seq_printf(m, "total: %d\n", total);
493018dc
BV		 662
663 mutex_unlock(&dev->struct_mutex);
664
665 return 0;
666}
667
2017263e
BG		 668static int i915_gem_request_info(struct seq_file *m, void *data)
669{
9f25d007 670 struct drm_info_node *node = m->private;
2017263e 671 struct drm_device *dev = node->minor->dev;
e277a1f8 672 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 673 struct intel_engine_cs *ring;
eed29a5b 674 struct drm_i915_gem_request *req;
2d1070b2 675 int ret, any, i;
de227ef0
CW		 676
677 ret = mutex_lock_interruptible(&dev->struct_mutex);
678 if (ret)
679 return ret;
2017263e 680
2d1070b2 681 any = 0;
a2c7f6fd 682 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 683 int count;
684
685 count = 0;
eed29a5b 686 list_for_each_entry(req, &ring->request_list, list)
2d1070b2
CW		 687 count++;
688 if (count == 0)
a2c7f6fd
CW		 689 continue;
690
2d1070b2 691 seq_printf(m, "%s requests: %d\n", ring->name, count);
eed29a5b 692 list_for_each_entry(req, &ring->request_list, list) {
2d1070b2
CW		 693 struct task_struct *task;
694
695 rcu_read_lock();
696 task = NULL;
eed29a5b
DV		 697 if (req->pid)
698 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 699 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 700 req->seqno,
701 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 702 task ? task->comm : "<unknown>",
703 task ? task->pid : -1);
704 rcu_read_unlock();
c2c347a9 705 }
2d1070b2
CW		 706
707 any++;
2017263e 708 }
de227ef0
CW		 709 mutex_unlock(&dev->struct_mutex);
710
2d1070b2 711 if (any == 0)
267f0c90 712 seq_puts(m, "No requests\n");
c2c347a9 713
2017263e
BG		 714 return 0;
715}
716
b2223497 717static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 718 struct intel_engine_cs *ring)
b2223497
CW		 719{
720 if (ring->get_seqno) {
20e28fba 721 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 722 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 723 }
724}
725
2017263e
BG		 726static int i915_gem_seqno_info(struct seq_file *m, void *data)
727{
9f25d007 728 struct drm_info_node *node = m->private;
2017263e 729 struct drm_device *dev = node->minor->dev;
e277a1f8 730 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 731 struct intel_engine_cs *ring;
1ec14ad3 732 int ret, i;
de227ef0
CW		 733
734 ret = mutex_lock_interruptible(&dev->struct_mutex);
735 if (ret)
736 return ret;
c8c8fb33 737 intel_runtime_pm_get(dev_priv);
2017263e 738
a2c7f6fd
CW		 739 for_each_ring(ring, dev_priv, i)
740 i915_ring_seqno_info(m, ring);
de227ef0 741
c8c8fb33 742 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 743 mutex_unlock(&dev->struct_mutex);
744
2017263e
BG		 745 return 0;
746}
747
748
749static int i915_interrupt_info(struct seq_file *m, void *data)
750{
9f25d007 751 struct drm_info_node *node = m->private;
2017263e 752 struct drm_device *dev = node->minor->dev;
e277a1f8 753 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 754 struct intel_engine_cs *ring;
9db4a9c7 755 int ret, i, pipe;
de227ef0
CW		 756
757 ret = mutex_lock_interruptible(&dev->struct_mutex);
758 if (ret)
759 return ret;
c8c8fb33 760 intel_runtime_pm_get(dev_priv);
2017263e 761
74e1ca8c 762 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 763 seq_printf(m, "Master Interrupt Control:\t%08x\n",
764 I915_READ(GEN8_MASTER_IRQ));
765
766 seq_printf(m, "Display IER:\t%08x\n",
767 I915_READ(VLV_IER));
768 seq_printf(m, "Display IIR:\t%08x\n",
769 I915_READ(VLV_IIR));
770 seq_printf(m, "Display IIR_RW:\t%08x\n",
771 I915_READ(VLV_IIR_RW));
772 seq_printf(m, "Display IMR:\t%08x\n",
773 I915_READ(VLV_IMR));
055e393f 774 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 775 seq_printf(m, "Pipe %c stat:\t%08x\n",
776 pipe_name(pipe),
777 I915_READ(PIPESTAT(pipe)));
778
779 seq_printf(m, "Port hotplug:\t%08x\n",
780 I915_READ(PORT_HOTPLUG_EN));
781 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
782 I915_READ(VLV_DPFLIPSTAT));
783 seq_printf(m, "DPINVGTT:\t%08x\n",
784 I915_READ(DPINVGTT));
785
786 for (i = 0; i < 4; i++) {
787 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
788 i, I915_READ(GEN8_GT_IMR(i)));
789 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
790 i, I915_READ(GEN8_GT_IIR(i)));
791 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
792 i, I915_READ(GEN8_GT_IER(i)));
793 }
794
795 seq_printf(m, "PCU interrupt mask:\t%08x\n",
796 I915_READ(GEN8_PCU_IMR));
797 seq_printf(m, "PCU interrupt identity:\t%08x\n",
798 I915_READ(GEN8_PCU_IIR));
799 seq_printf(m, "PCU interrupt enable:\t%08x\n",
800 I915_READ(GEN8_PCU_IER));
801 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 802 seq_printf(m, "Master Interrupt Control:\t%08x\n",
803 I915_READ(GEN8_MASTER_IRQ));
804
805 for (i = 0; i < 4; i++) {
806 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
807 i, I915_READ(GEN8_GT_IMR(i)));
808 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
809 i, I915_READ(GEN8_GT_IIR(i)));
810 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
811 i, I915_READ(GEN8_GT_IER(i)));
812 }
813
055e393f 814 for_each_pipe(dev_priv, pipe) {
f458ebbc 815 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 816 POWER_DOMAIN_PIPE(pipe))) {
817 seq_printf(m, "Pipe %c power disabled\n",
818 pipe_name(pipe));
819 continue;
820 }
a123f157 821 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 822 pipe_name(pipe),
823 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 824 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 825 pipe_name(pipe),
826 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 827 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 828 pipe_name(pipe),
829 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 830 }
831
832 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
833 I915_READ(GEN8_DE_PORT_IMR));
834 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
835 I915_READ(GEN8_DE_PORT_IIR));
836 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
837 I915_READ(GEN8_DE_PORT_IER));
838
839 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
840 I915_READ(GEN8_DE_MISC_IMR));
841 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
842 I915_READ(GEN8_DE_MISC_IIR));
843 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
844 I915_READ(GEN8_DE_MISC_IER));
845
846 seq_printf(m, "PCU interrupt mask:\t%08x\n",
847 I915_READ(GEN8_PCU_IMR));
848 seq_printf(m, "PCU interrupt identity:\t%08x\n",
849 I915_READ(GEN8_PCU_IIR));
850 seq_printf(m, "PCU interrupt enable:\t%08x\n",
851 I915_READ(GEN8_PCU_IER));
852 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 853 seq_printf(m, "Display IER:\t%08x\n",
854 I915_READ(VLV_IER));
855 seq_printf(m, "Display IIR:\t%08x\n",
856 I915_READ(VLV_IIR));
857 seq_printf(m, "Display IIR_RW:\t%08x\n",
858 I915_READ(VLV_IIR_RW));
859 seq_printf(m, "Display IMR:\t%08x\n",
860 I915_READ(VLV_IMR));
055e393f 861 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 862 seq_printf(m, "Pipe %c stat:\t%08x\n",
863 pipe_name(pipe),
864 I915_READ(PIPESTAT(pipe)));
865
866 seq_printf(m, "Master IER:\t%08x\n",
867 I915_READ(VLV_MASTER_IER));
868
869 seq_printf(m, "Render IER:\t%08x\n",
870 I915_READ(GTIER));
871 seq_printf(m, "Render IIR:\t%08x\n",
872 I915_READ(GTIIR));
873 seq_printf(m, "Render IMR:\t%08x\n",
874 I915_READ(GTIMR));
875
876 seq_printf(m, "PM IER:\t\t%08x\n",
877 I915_READ(GEN6_PMIER));
878 seq_printf(m, "PM IIR:\t\t%08x\n",
879 I915_READ(GEN6_PMIIR));
880 seq_printf(m, "PM IMR:\t\t%08x\n",
881 I915_READ(GEN6_PMIMR));
882
883 seq_printf(m, "Port hotplug:\t%08x\n",
884 I915_READ(PORT_HOTPLUG_EN));
885 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
886 I915_READ(VLV_DPFLIPSTAT));
887 seq_printf(m, "DPINVGTT:\t%08x\n",
888 I915_READ(DPINVGTT));
889
890 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 891 seq_printf(m, "Interrupt enable: %08x\n",
892 I915_READ(IER));
893 seq_printf(m, "Interrupt identity: %08x\n",
894 I915_READ(IIR));
895 seq_printf(m, "Interrupt mask: %08x\n",
896 I915_READ(IMR));
055e393f 897 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 898 seq_printf(m, "Pipe %c stat: %08x\n",
899 pipe_name(pipe),
900 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 901 } else {
902 seq_printf(m, "North Display Interrupt enable: %08x\n",
903 I915_READ(DEIER));
904 seq_printf(m, "North Display Interrupt identity: %08x\n",
905 I915_READ(DEIIR));
906 seq_printf(m, "North Display Interrupt mask: %08x\n",
907 I915_READ(DEIMR));
908 seq_printf(m, "South Display Interrupt enable: %08x\n",
909 I915_READ(SDEIER));
910 seq_printf(m, "South Display Interrupt identity: %08x\n",
911 I915_READ(SDEIIR));
912 seq_printf(m, "South Display Interrupt mask: %08x\n",
913 I915_READ(SDEIMR));
914 seq_printf(m, "Graphics Interrupt enable: %08x\n",
915 I915_READ(GTIER));
916 seq_printf(m, "Graphics Interrupt identity: %08x\n",
917 I915_READ(GTIIR));
918 seq_printf(m, "Graphics Interrupt mask: %08x\n",
919 I915_READ(GTIMR));
920 }
a2c7f6fd 921 for_each_ring(ring, dev_priv, i) {
a123f157 922 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 923 seq_printf(m,
924 "Graphics Interrupt mask (%s): %08x\n",
925 ring->name, I915_READ_IMR(ring));
9862e600 926 }
a2c7f6fd 927 i915_ring_seqno_info(m, ring);
9862e600 928 }
c8c8fb33 929 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 930 mutex_unlock(&dev->struct_mutex);
931
2017263e
BG		 932 return 0;
933}
934
a6172a80
CW		 935static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
936{
9f25d007 937 struct drm_info_node *node = m->private;
a6172a80 938 struct drm_device *dev = node->minor->dev;
e277a1f8 939 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 940 int i, ret;
941
942 ret = mutex_lock_interruptible(&dev->struct_mutex);
943 if (ret)
944 return ret;
a6172a80
CW		 945
946 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
947 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
948 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 949 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 950
6c085a72
CW		 951 seq_printf(m, "Fence %d, pin count = %d, object = ",
952 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 953 if (obj == NULL)
267f0c90 954 seq_puts(m, "unused");
c2c347a9 955 else
05394f39 956 describe_obj(m, obj);
267f0c90 957 seq_putc(m, '\n');
a6172a80
CW		 958 }
959
05394f39 960 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 961 return 0;
962}
963
2017263e
BG		 964static int i915_hws_info(struct seq_file *m, void *data)
965{
9f25d007 966 struct drm_info_node *node = m->private;
2017263e 967 struct drm_device *dev = node->minor->dev;
e277a1f8 968 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 969 struct intel_engine_cs *ring;
1a240d4d 970 const u32 *hws;
4066c0ae
CW		 971 int i;
972
1ec14ad3 973 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 974 hws = ring->status_page.page_addr;
2017263e
BG		 975 if (hws == NULL)
976 return 0;
977
978 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
979 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
980 i * 4,
981 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
982 }
983 return 0;
984}
985
d5442303
DV		 986static ssize_t
987i915_error_state_write(struct file *filp,
988 const char __user *ubuf,
989 size_t cnt,
990 loff_t *ppos)
991{
edc3d884 992 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 993 struct drm_device *dev = error_priv->dev;
22bcfc6a 994 int ret;
d5442303
DV		 995
996 DRM_DEBUG_DRIVER("Resetting error state\n");
997
22bcfc6a
DV		 998 ret = mutex_lock_interruptible(&dev->struct_mutex);
999 if (ret)
1000 return ret;
1001
d5442303
DV		 1002 i915_destroy_error_state(dev);
1003 mutex_unlock(&dev->struct_mutex);
1004
1005 return cnt;
1006}
1007
1008static int i915_error_state_open(struct inode *inode, struct file *file)
1009{
1010 struct drm_device *dev = inode->i_private;
d5442303 1011 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1012
1013 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1014 if (!error_priv)
1015 return -ENOMEM;
1016
1017 error_priv->dev = dev;
1018
95d5bfb3 1019 i915_error_state_get(dev, error_priv);
d5442303 1020
edc3d884
MK		 1021 file->private_data = error_priv;
1022
1023 return 0;
d5442303
DV		 1024}
1025
1026static int i915_error_state_release(struct inode *inode, struct file *file)
1027{
edc3d884 1028 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1029
95d5bfb3 1030 i915_error_state_put(error_priv);
d5442303
DV		 1031 kfree(error_priv);
1032
edc3d884
MK		 1033 return 0;
1034}
1035
4dc955f7
MK		 1036static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1037 size_t count, loff_t *pos)
1038{
1039 struct i915_error_state_file_priv *error_priv = file->private_data;
1040 struct drm_i915_error_state_buf error_str;
1041 loff_t tmp_pos = 0;
1042 ssize_t ret_count = 0;
1043 int ret;
1044
0a4cd7c8 1045 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1046 if (ret)
1047 return ret;
edc3d884 1048
fc16b48b 1049 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1050 if (ret)
1051 goto out;
1052
edc3d884
MK		 1053 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1054 error_str.buf,
1055 error_str.bytes);
1056
1057 if (ret_count < 0)
1058 ret = ret_count;
1059 else
1060 *pos = error_str.start + ret_count;
1061out:
4dc955f7 1062 i915_error_state_buf_release(&error_str);
edc3d884 1063 return ret ?: ret_count;
d5442303
DV		 1064}
1065
1066static const struct file_operations i915_error_state_fops = {
1067 .owner = THIS_MODULE,
1068 .open = i915_error_state_open,
edc3d884 1069 .read = i915_error_state_read,
d5442303
DV		 1070 .write = i915_error_state_write,
1071 .llseek = default_llseek,
1072 .release = i915_error_state_release,
1073};
1074
647416f9
KC		 1075static int
1076i915_next_seqno_get(void *data, u64 *val)
40633219 1077{
647416f9 1078 struct drm_device *dev = data;
e277a1f8 1079 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1080 int ret;
1081
1082 ret = mutex_lock_interruptible(&dev->struct_mutex);
1083 if (ret)
1084 return ret;
1085
647416f9 1086 *val = dev_priv->next_seqno;
40633219
MK		 1087 mutex_unlock(&dev->struct_mutex);
1088
647416f9 1089 return 0;
40633219
MK		 1090}
1091
647416f9
KC		 1092static int
1093i915_next_seqno_set(void *data, u64 val)
1094{
1095 struct drm_device *dev = data;
40633219
MK		 1096 int ret;
1097
40633219
MK		 1098 ret = mutex_lock_interruptible(&dev->struct_mutex);
1099 if (ret)
1100 return ret;
1101
e94fbaa8 1102 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1103 mutex_unlock(&dev->struct_mutex);
1104
647416f9 1105 return ret;
40633219
MK		 1106}
1107
647416f9
KC		 1108DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1109 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1110 "0x%llx\n");
40633219 1111
adb4bd12 1112static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1113{
9f25d007 1114 struct drm_info_node *node = m->private;
f97108d1 1115 struct drm_device *dev = node->minor->dev;
e277a1f8 1116 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1117 int ret = 0;
1118
1119 intel_runtime_pm_get(dev_priv);
3b8d8d91 1120
5c9669ce
TR		 1121 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1122
3b8d8d91
JB		 1123 if (IS_GEN5(dev)) {
1124 u16 rgvswctl = I915_READ16(MEMSWCTL);
1125 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1126
1127 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1128 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1129 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1130 MEMSTAT_VID_SHIFT);
1131 seq_printf(m, "Current P-state: %d\n",
1132 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2 1133 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
60260a5b 1134 IS_BROADWELL(dev) || IS_GEN9(dev)) {
3b8d8d91
JB		 1135 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1136 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1137 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1138 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1139 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1140 u32 rpupei, rpcurup, rpprevup;
1141 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1142 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1143 int max_freq;
1144
1145 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1146 ret = mutex_lock_interruptible(&dev->struct_mutex);
1147 if (ret)
c8c8fb33 1148 goto out;
d1ebd816 1149
59bad947 1150 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1151
8e8c06cd 1152 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1153 if (IS_GEN9(dev))
1154 reqf >>= 23;
1155 else {
1156 reqf &= ~GEN6_TURBO_DISABLE;
1157 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1158 reqf >>= 24;
1159 else
1160 reqf >>= 25;
1161 }
7c59a9c1 1162 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1163
0d8f9491
CW		 1164 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1165 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1166 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1167
ccab5c82
JB		 1168 rpstat = I915_READ(GEN6_RPSTAT1);
1169 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1170 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1171 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1172 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1173 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1174 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1175 if (IS_GEN9(dev))
1176 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1177 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1178 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1179 else
1180 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1181 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1182
59bad947 1183 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1184 mutex_unlock(&dev->struct_mutex);
1185
9dd3c605
PZ		 1186 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1187 pm_ier = I915_READ(GEN6_PMIER);
1188 pm_imr = I915_READ(GEN6_PMIMR);
1189 pm_isr = I915_READ(GEN6_PMISR);
1190 pm_iir = I915_READ(GEN6_PMIIR);
1191 pm_mask = I915_READ(GEN6_PMINTRMSK);
1192 } else {
1193 pm_ier = I915_READ(GEN8_GT_IER(2));
1194 pm_imr = I915_READ(GEN8_GT_IMR(2));
1195 pm_isr = I915_READ(GEN8_GT_ISR(2));
1196 pm_iir = I915_READ(GEN8_GT_IIR(2));
1197 pm_mask = I915_READ(GEN6_PMINTRMSK);
1198 }
0d8f9491 1199 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1200 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1201 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1202 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1203 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1204 seq_printf(m, "Render p-state VID: %d\n",
1205 gt_perf_status & 0xff);
1206 seq_printf(m, "Render p-state limit: %d\n",
1207 rp_state_limits & 0xff);
0d8f9491
CW		 1208 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1209 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1210 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1211 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1212 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1213 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1214 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1215 GEN6_CURICONT_MASK);
1216 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1217 GEN6_CURBSYTAVG_MASK);
1218 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1219 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1220 seq_printf(m, "Up threshold: %d%%\n",
1221 dev_priv->rps.up_threshold);
1222
ccab5c82
JB		 1223 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1224 GEN6_CURIAVG_MASK);
1225 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1226 GEN6_CURBSYTAVG_MASK);
1227 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1228 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1229 seq_printf(m, "Down threshold: %d%%\n",
1230 dev_priv->rps.down_threshold);
3b8d8d91
JB		 1231
1232 max_freq = (rp_state_cap & 0xff0000) >> 16;
60260a5b 1233 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1234 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1235 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1236
1237 max_freq = (rp_state_cap & 0xff00) >> 8;
60260a5b 1238 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1239 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1240 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1241
1242 max_freq = rp_state_cap & 0xff;
60260a5b 1243 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1244 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1245 intel_gpu_freq(dev_priv, max_freq));
31c77388 1246 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1247 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1248
d86ed34a
CW		 1249 seq_printf(m, "Current freq: %d MHz\n",
1250 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1251 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1252 seq_printf(m, "Idle freq: %d MHz\n",
1253 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1254 seq_printf(m, "Min freq: %d MHz\n",
1255 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1256 seq_printf(m, "Max freq: %d MHz\n",
1257 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1258 seq_printf(m,
1259 "efficient (RPe) frequency: %d MHz\n",
1260 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84 1261 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1262 u32 freq_sts;
0a073b84 1263
259bd5d4 1264 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1265 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1266 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1267 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1268
d86ed34a
CW		 1269 seq_printf(m, "actual GPU freq: %d MHz\n",
1270 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1271
1272 seq_printf(m, "current GPU freq: %d MHz\n",
1273 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1274
0a073b84 1275 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1276 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1277
0a073b84 1278 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1279 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1280
aed242ff
CW		 1281 seq_printf(m, "idle GPU freq: %d MHz\n",
1282 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1283
7c59a9c1
VS		 1284 seq_printf(m,
1285 "efficient (RPe) frequency: %d MHz\n",
1286 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
259bd5d4 1287 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1288 } else {
267f0c90 1289 seq_puts(m, "no P-state info available\n");
3b8d8d91 1290 }
f97108d1 1291
c8c8fb33
PZ		 1292out:
1293 intel_runtime_pm_put(dev_priv);
1294 return ret;
f97108d1
JB		 1295}
1296
f654449a
CW		 1297static int i915_hangcheck_info(struct seq_file *m, void *unused)
1298{
1299 struct drm_info_node *node = m->private;
ebbc7546
MK		 1300 struct drm_device *dev = node->minor->dev;
1301 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1302 struct intel_engine_cs *ring;
ebbc7546
MK		 1303 u64 acthd[I915_NUM_RINGS];
1304 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1305 int i;
1306
1307 if (!i915.enable_hangcheck) {
1308 seq_printf(m, "Hangcheck disabled\n");
1309 return 0;
1310 }
1311
ebbc7546
MK		 1312 intel_runtime_pm_get(dev_priv);
1313
1314 for_each_ring(ring, dev_priv, i) {
1315 seqno[i] = ring->get_seqno(ring, false);
1316 acthd[i] = intel_ring_get_active_head(ring);
1317 }
1318
1319 intel_runtime_pm_put(dev_priv);
1320
f654449a
CW		 1321 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1322 seq_printf(m, "Hangcheck active, fires in %dms\n",
1323 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1324 jiffies));
1325 } else
1326 seq_printf(m, "Hangcheck inactive\n");
1327
1328 for_each_ring(ring, dev_priv, i) {
1329 seq_printf(m, "%s:\n", ring->name);
1330 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1331 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1332 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1333 (long long)ring->hangcheck.acthd,
ebbc7546 1334 (long long)acthd[i]);
f654449a
CW		 1335 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1336 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1337 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1338 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1339 }
1340
1341 return 0;
1342}
1343
4d85529d 1344static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1345{
9f25d007 1346 struct drm_info_node *node = m->private;
f97108d1 1347 struct drm_device *dev = node->minor->dev;
e277a1f8 1348 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1349 u32 rgvmodectl, rstdbyctl;
1350 u16 crstandvid;
1351 int ret;
1352
1353 ret = mutex_lock_interruptible(&dev->struct_mutex);
1354 if (ret)
1355 return ret;
c8c8fb33 1356 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1357
1358 rgvmodectl = I915_READ(MEMMODECTL);
1359 rstdbyctl = I915_READ(RSTDBYCTL);
1360 crstandvid = I915_READ16(CRSTANDVID);
1361
c8c8fb33 1362 intel_runtime_pm_put(dev_priv);
616fdb5a 1363 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1364
1365 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1366 "yes" : "no");
1367 seq_printf(m, "Boost freq: %d\n",
1368 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1369 MEMMODE_BOOST_FREQ_SHIFT);
1370 seq_printf(m, "HW control enabled: %s\n",
1371 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1372 seq_printf(m, "SW control enabled: %s\n",
1373 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1374 seq_printf(m, "Gated voltage change: %s\n",
1375 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1376 seq_printf(m, "Starting frequency: P%d\n",
1377 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1378 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1379 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1380 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1381 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1382 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1383 seq_printf(m, "Render standby enabled: %s\n",
1384 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1385 seq_puts(m, "Current RS state: ");
88271da3
JB		 1386 switch (rstdbyctl & RSX_STATUS_MASK) {
1387 case RSX_STATUS_ON:
267f0c90 1388 seq_puts(m, "on\n");
88271da3
JB		 1389 break;
1390 case RSX_STATUS_RC1:
267f0c90 1391 seq_puts(m, "RC1\n");
88271da3
JB		 1392 break;
1393 case RSX_STATUS_RC1E:
267f0c90 1394 seq_puts(m, "RC1E\n");
88271da3
JB		 1395 break;
1396 case RSX_STATUS_RS1:
267f0c90 1397 seq_puts(m, "RS1\n");
88271da3
JB		 1398 break;
1399 case RSX_STATUS_RS2:
267f0c90 1400 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1401 break;
1402 case RSX_STATUS_RS3:
267f0c90 1403 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1404 break;
1405 default:
267f0c90 1406 seq_puts(m, "unknown\n");
88271da3
JB		 1407 break;
1408 }
f97108d1
JB		 1409
1410 return 0;
1411}
1412
f65367b5 1413static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1414{
b2cff0db
CW		 1415 struct drm_info_node *node = m->private;
1416 struct drm_device *dev = node->minor->dev;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1419 int i;
1420
1421 spin_lock_irq(&dev_priv->uncore.lock);
1422 for_each_fw_domain(fw_domain, dev_priv, i) {
1423 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1424 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1425 fw_domain->wake_count);
1426 }
1427 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1428
b2cff0db
CW		 1429 return 0;
1430}
1431
1432static int vlv_drpc_info(struct seq_file *m)
1433{
9f25d007 1434 struct drm_info_node *node = m->private;
669ab5aa
D		 1435 struct drm_device *dev = node->minor->dev;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1437 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1438
d46c0517
ID		 1439 intel_runtime_pm_get(dev_priv);
1440
6b312cd3 1441 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1442 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1443 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1444
d46c0517
ID		 1445 intel_runtime_pm_put(dev_priv);
1446
669ab5aa
D		 1447 seq_printf(m, "Video Turbo Mode: %s\n",
1448 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1449 seq_printf(m, "Turbo enabled: %s\n",
1450 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1451 seq_printf(m, "HW control enabled: %s\n",
1452 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1453 seq_printf(m, "SW control enabled: %s\n",
1454 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1455 GEN6_RP_MEDIA_SW_MODE));
1456 seq_printf(m, "RC6 Enabled: %s\n",
1457 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1458 GEN6_RC_CTL_EI_MODE(1))));
1459 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1460 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1461 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1462 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1463
9cc19be5
ID		 1464 seq_printf(m, "Render RC6 residency since boot: %u\n",
1465 I915_READ(VLV_GT_RENDER_RC6));
1466 seq_printf(m, "Media RC6 residency since boot: %u\n",
1467 I915_READ(VLV_GT_MEDIA_RC6));
1468
f65367b5 1469 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1470}
1471
4d85529d
BW		 1472static int gen6_drpc_info(struct seq_file *m)
1473{
9f25d007 1474 struct drm_info_node *node = m->private;
4d85529d
BW		 1475 struct drm_device *dev = node->minor->dev;
1476 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1477 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1478 unsigned forcewake_count;
aee56cff 1479 int count = 0, ret;
4d85529d
BW		 1480
1481 ret = mutex_lock_interruptible(&dev->struct_mutex);
1482 if (ret)
1483 return ret;
c8c8fb33 1484 intel_runtime_pm_get(dev_priv);
4d85529d 1485
907b28c5 1486 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1487 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1488 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1489
1490 if (forcewake_count) {
267f0c90
DL		 1491 seq_puts(m, "RC information inaccurate because somebody "
1492 "holds a forcewake reference \n");
4d85529d
BW		 1493 } else {
1494 /* NB: we cannot use forcewake, else we read the wrong values */
1495 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1496 udelay(10);
1497 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1498 }
1499
1500 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1501 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1502
1503 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1504 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1505 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1506 mutex_lock(&dev_priv->rps.hw_lock);
1507 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1508 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1509
c8c8fb33
PZ		 1510 intel_runtime_pm_put(dev_priv);
1511
4d85529d
BW		 1512 seq_printf(m, "Video Turbo Mode: %s\n",
1513 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1514 seq_printf(m, "HW control enabled: %s\n",
1515 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1516 seq_printf(m, "SW control enabled: %s\n",
1517 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1518 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1519 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1520 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1521 seq_printf(m, "RC6 Enabled: %s\n",
1522 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1523 seq_printf(m, "Deep RC6 Enabled: %s\n",
1524 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1525 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1526 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1527 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1528 switch (gt_core_status & GEN6_RCn_MASK) {
1529 case GEN6_RC0:
1530 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1531 seq_puts(m, "Core Power Down\n");
4d85529d 1532 else
267f0c90 1533 seq_puts(m, "on\n");
4d85529d
BW		 1534 break;
1535 case GEN6_RC3:
267f0c90 1536 seq_puts(m, "RC3\n");
4d85529d
BW		 1537 break;
1538 case GEN6_RC6:
267f0c90 1539 seq_puts(m, "RC6\n");
4d85529d
BW		 1540 break;
1541 case GEN6_RC7:
267f0c90 1542 seq_puts(m, "RC7\n");
4d85529d
BW		 1543 break;
1544 default:
267f0c90 1545 seq_puts(m, "Unknown\n");
4d85529d
BW		 1546 break;
1547 }
1548
1549 seq_printf(m, "Core Power Down: %s\n",
1550 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1551
1552 /* Not exactly sure what this is */
1553 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1554 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1555 seq_printf(m, "RC6 residency since boot: %u\n",
1556 I915_READ(GEN6_GT_GFX_RC6));
1557 seq_printf(m, "RC6+ residency since boot: %u\n",
1558 I915_READ(GEN6_GT_GFX_RC6p));
1559 seq_printf(m, "RC6++ residency since boot: %u\n",
1560 I915_READ(GEN6_GT_GFX_RC6pp));
1561
ecd8faea
BW		 1562 seq_printf(m, "RC6 voltage: %dmV\n",
1563 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1564 seq_printf(m, "RC6+ voltage: %dmV\n",
1565 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1566 seq_printf(m, "RC6++ voltage: %dmV\n",
1567 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1568 return 0;
1569}
1570
1571static int i915_drpc_info(struct seq_file *m, void *unused)
1572{
9f25d007 1573 struct drm_info_node *node = m->private;
4d85529d
BW		 1574 struct drm_device *dev = node->minor->dev;
1575
669ab5aa
D		 1576 if (IS_VALLEYVIEW(dev))
1577 return vlv_drpc_info(m);
ac66cf4b 1578 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1579 return gen6_drpc_info(m);
1580 else
1581 return ironlake_drpc_info(m);
1582}
1583
b5e50c3f
JB		 1584static int i915_fbc_status(struct seq_file *m, void *unused)
1585{
9f25d007 1586 struct drm_info_node *node = m->private;
b5e50c3f 1587 struct drm_device *dev = node->minor->dev;
e277a1f8 1588 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1589
3a77c4c4 1590 if (!HAS_FBC(dev)) {
267f0c90 1591 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1592 return 0;
1593 }
1594
36623ef8
PZ		 1595 intel_runtime_pm_get(dev_priv);
1596
ee5382ae 1597 if (intel_fbc_enabled(dev)) {
267f0c90 1598 seq_puts(m, "FBC enabled\n");
b5e50c3f 1599 } else {
267f0c90 1600 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1601 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1602 case FBC_OK:
1603 seq_puts(m, "FBC actived, but currently disabled in hardware");
1604 break;
1605 case FBC_UNSUPPORTED:
1606 seq_puts(m, "unsupported by this chipset");
1607 break;
bed4a673 1608 case FBC_NO_OUTPUT:
267f0c90 1609 seq_puts(m, "no outputs");
bed4a673 1610 break;
b5e50c3f 1611 case FBC_STOLEN_TOO_SMALL:
267f0c90 1612 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1613 break;
1614 case FBC_UNSUPPORTED_MODE:
267f0c90 1615 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1616 break;
1617 case FBC_MODE_TOO_LARGE:
267f0c90 1618 seq_puts(m, "mode too large");
b5e50c3f
JB		 1619 break;
1620 case FBC_BAD_PLANE:
267f0c90 1621 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1622 break;
1623 case FBC_NOT_TILED:
267f0c90 1624 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1625 break;
9c928d16 1626 case FBC_MULTIPLE_PIPES:
267f0c90 1627 seq_puts(m, "multiple pipes are enabled");
9c928d16 1628 break;
c1a9f047 1629 case FBC_MODULE_PARAM:
267f0c90 1630 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1631 break;
8a5729a3 1632 case FBC_CHIP_DEFAULT:
267f0c90 1633 seq_puts(m, "disabled per chip default");
8a5729a3 1634 break;
b5e50c3f 1635 default:
267f0c90 1636 seq_puts(m, "unknown reason");
b5e50c3f 1637 }
267f0c90 1638 seq_putc(m, '\n');
b5e50c3f 1639 }
36623ef8
PZ		 1640
1641 intel_runtime_pm_put(dev_priv);
1642
b5e50c3f
JB		 1643 return 0;
1644}
1645
da46f936
RV		 1646static int i915_fbc_fc_get(void *data, u64 *val)
1647{
1648 struct drm_device *dev = data;
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650
1651 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1652 return -ENODEV;
1653
1654 drm_modeset_lock_all(dev);
1655 *val = dev_priv->fbc.false_color;
1656 drm_modeset_unlock_all(dev);
1657
1658 return 0;
1659}
1660
1661static int i915_fbc_fc_set(void *data, u64 val)
1662{
1663 struct drm_device *dev = data;
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1665 u32 reg;
1666
1667 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1668 return -ENODEV;
1669
1670 drm_modeset_lock_all(dev);
1671
1672 reg = I915_READ(ILK_DPFC_CONTROL);
1673 dev_priv->fbc.false_color = val;
1674
1675 I915_WRITE(ILK_DPFC_CONTROL, val ?
1676 (reg | FBC_CTL_FALSE_COLOR) :
1677 (reg & ~FBC_CTL_FALSE_COLOR));
1678
1679 drm_modeset_unlock_all(dev);
1680 return 0;
1681}
1682
1683DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1684 i915_fbc_fc_get, i915_fbc_fc_set,
1685 "%llu\n");
1686
92d44621
PZ		 1687static int i915_ips_status(struct seq_file *m, void *unused)
1688{
9f25d007 1689 struct drm_info_node *node = m->private;
92d44621
PZ		 1690 struct drm_device *dev = node->minor->dev;
1691 struct drm_i915_private *dev_priv = dev->dev_private;
1692
f5adf94e 1693 if (!HAS_IPS(dev)) {
92d44621
PZ		 1694 seq_puts(m, "not supported\n");
1695 return 0;
1696 }
1697
36623ef8
PZ		 1698 intel_runtime_pm_get(dev_priv);
1699
0eaa53f0
RV		 1700 seq_printf(m, "Enabled by kernel parameter: %s\n",
1701 yesno(i915.enable_ips));
1702
1703 if (INTEL_INFO(dev)->gen >= 8) {
1704 seq_puts(m, "Currently: unknown\n");
1705 } else {
1706 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1707 seq_puts(m, "Currently: enabled\n");
1708 else
1709 seq_puts(m, "Currently: disabled\n");
1710 }
92d44621 1711
36623ef8
PZ		 1712 intel_runtime_pm_put(dev_priv);
1713
92d44621
PZ		 1714 return 0;
1715}
1716
4a9bef37
JB		 1717static int i915_sr_status(struct seq_file *m, void *unused)
1718{
9f25d007 1719 struct drm_info_node *node = m->private;
4a9bef37 1720 struct drm_device *dev = node->minor->dev;
e277a1f8 1721 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1722 bool sr_enabled = false;
1723
36623ef8
PZ		 1724 intel_runtime_pm_get(dev_priv);
1725
1398261a 1726 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1727 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1728 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1729 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1730 else if (IS_I915GM(dev))
1731 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1732 else if (IS_PINEVIEW(dev))
1733 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1734
36623ef8
PZ		 1735 intel_runtime_pm_put(dev_priv);
1736
5ba2aaaa
CW		 1737 seq_printf(m, "self-refresh: %s\n",
1738 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1739
1740 return 0;
1741}
1742
7648fa99
JB		 1743static int i915_emon_status(struct seq_file *m, void *unused)
1744{
9f25d007 1745 struct drm_info_node *node = m->private;
7648fa99 1746 struct drm_device *dev = node->minor->dev;
e277a1f8 1747 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1748 unsigned long temp, chipset, gfx;
de227ef0
CW		 1749 int ret;
1750
582be6b4
CW		 1751 if (!IS_GEN5(dev))
1752 return -ENODEV;
1753
de227ef0
CW		 1754 ret = mutex_lock_interruptible(&dev->struct_mutex);
1755 if (ret)
1756 return ret;
7648fa99
JB		 1757
1758 temp = i915_mch_val(dev_priv);
1759 chipset = i915_chipset_val(dev_priv);
1760 gfx = i915_gfx_val(dev_priv);
de227ef0 1761 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1762
1763 seq_printf(m, "GMCH temp: %ld\n", temp);
1764 seq_printf(m, "Chipset power: %ld\n", chipset);
1765 seq_printf(m, "GFX power: %ld\n", gfx);
1766 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1767
1768 return 0;
1769}
1770
23b2f8bb
JB		 1771static int i915_ring_freq_table(struct seq_file *m, void *unused)
1772{
9f25d007 1773 struct drm_info_node *node = m->private;
23b2f8bb 1774 struct drm_device *dev = node->minor->dev;
e277a1f8 1775 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1776 int ret = 0;
23b2f8bb
JB		 1777 int gpu_freq, ia_freq;
1778
1c70c0ce 1779 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1780 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1781 return 0;
1782 }
1783
5bfa0199
PZ		 1784 intel_runtime_pm_get(dev_priv);
1785
5c9669ce
TR		 1786 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1787
4fc688ce 1788 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1789 if (ret)
5bfa0199 1790 goto out;
23b2f8bb 1791
267f0c90 1792 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1793
b39fb297
BW		 1794 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1795 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1796 gpu_freq++) {
42c0526c
BW		 1797 ia_freq = gpu_freq;
1798 sandybridge_pcode_read(dev_priv,
1799 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1800 &ia_freq);
3ebecd07 1801 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
7c59a9c1 1802 intel_gpu_freq(dev_priv, gpu_freq),
3ebecd07
CW		 1803 ((ia_freq >> 0) & 0xff) * 100,
1804 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1805 }
1806
4fc688ce 1807 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1808
5bfa0199
PZ		 1809out:
1810 intel_runtime_pm_put(dev_priv);
1811 return ret;
23b2f8bb
JB		 1812}
1813
44834a67
CW		 1814static int i915_opregion(struct seq_file *m, void *unused)
1815{
9f25d007 1816 struct drm_info_node *node = m->private;
44834a67 1817 struct drm_device *dev = node->minor->dev;
e277a1f8 1818 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1819 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1820 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1821 int ret;
1822
0d38f009
DV		 1823 if (data == NULL)
1824 return -ENOMEM;
1825
44834a67
CW		 1826 ret = mutex_lock_interruptible(&dev->struct_mutex);
1827 if (ret)
0d38f009 1828 goto out;
44834a67 1829
0d38f009
DV		 1830 if (opregion->header) {
1831 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1832 seq_write(m, data, OPREGION_SIZE);
1833 }
44834a67
CW		 1834
1835 mutex_unlock(&dev->struct_mutex);
1836
0d38f009
DV		 1837out:
1838 kfree(data);
44834a67
CW		 1839 return 0;
1840}
1841
37811fcc
CW		 1842static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1843{
9f25d007 1844 struct drm_info_node *node = m->private;
37811fcc 1845 struct drm_device *dev = node->minor->dev;
4520f53a 1846 struct intel_fbdev *ifbdev = NULL;
37811fcc 1847 struct intel_framebuffer *fb;
37811fcc 1848
4520f53a
DV		 1849#ifdef CONFIG_DRM_I915_FBDEV
1850 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1851
1852 ifbdev = dev_priv->fbdev;
1853 fb = to_intel_framebuffer(ifbdev->helper.fb);
1854
c1ca506d 1855 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1856 fb->base.width,
1857 fb->base.height,
1858 fb->base.depth,
623f9783 1859 fb->base.bits_per_pixel,
c1ca506d 1860 fb->base.modifier[0],
623f9783 1861 atomic_read(&fb->base.refcount.refcount));
05394f39 1862 describe_obj(m, fb->obj);
267f0c90 1863 seq_putc(m, '\n');
4520f53a 1864#endif
37811fcc 1865
4b096ac1 1866 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1867 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1868 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1869 continue;
1870
c1ca506d 1871 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1872 fb->base.width,
1873 fb->base.height,
1874 fb->base.depth,
623f9783 1875 fb->base.bits_per_pixel,
c1ca506d 1876 fb->base.modifier[0],
623f9783 1877 atomic_read(&fb->base.refcount.refcount));
05394f39 1878 describe_obj(m, fb->obj);
267f0c90 1879 seq_putc(m, '\n');
37811fcc 1880 }
4b096ac1 1881 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1882
1883 return 0;
1884}
1885
c9fe99bd
OM		 1886static void describe_ctx_ringbuf(struct seq_file *m,
1887 struct intel_ringbuffer *ringbuf)
1888{
1889 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1890 ringbuf->space, ringbuf->head, ringbuf->tail,
1891 ringbuf->last_retired_head);
1892}
1893
e76d3630
BW		 1894static int i915_context_status(struct seq_file *m, void *unused)
1895{
9f25d007 1896 struct drm_info_node *node = m->private;
e76d3630 1897 struct drm_device *dev = node->minor->dev;
e277a1f8 1898 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1899 struct intel_engine_cs *ring;
273497e5 1900 struct intel_context *ctx;
a168c293 1901 int ret, i;
e76d3630 1902
f3d28878 1903 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1904 if (ret)
1905 return ret;
1906
a33afea5 1907 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1908 if (!i915.enable_execlists &&
1909 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1910 continue;
1911
a33afea5 1912 seq_puts(m, "HW context ");
3ccfd19d 1913 describe_ctx(m, ctx);
c9fe99bd 1914 for_each_ring(ring, dev_priv, i) {
a33afea5 1915 if (ring->default_context == ctx)
c9fe99bd
OM		 1916 seq_printf(m, "(default context %s) ",
1917 ring->name);
1918 }
1919
1920 if (i915.enable_execlists) {
1921 seq_putc(m, '\n');
1922 for_each_ring(ring, dev_priv, i) {
1923 struct drm_i915_gem_object *ctx_obj =
1924 ctx->engine[i].state;
1925 struct intel_ringbuffer *ringbuf =
1926 ctx->engine[i].ringbuf;
1927
1928 seq_printf(m, "%s: ", ring->name);
1929 if (ctx_obj)
1930 describe_obj(m, ctx_obj);
1931 if (ringbuf)
1932 describe_ctx_ringbuf(m, ringbuf);
1933 seq_putc(m, '\n');
1934 }
1935 } else {
1936 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1937 }
a33afea5 1938
a33afea5 1939 seq_putc(m, '\n');
a168c293
BW		 1940 }
1941
f3d28878 1942 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1943
1944 return 0;
1945}
1946
064ca1d2
TD		 1947static void i915_dump_lrc_obj(struct seq_file *m,
1948 struct intel_engine_cs *ring,
1949 struct drm_i915_gem_object *ctx_obj)
1950{
1951 struct page *page;
1952 uint32_t *reg_state;
1953 int j;
1954 unsigned long ggtt_offset = 0;
1955
1956 if (ctx_obj == NULL) {
1957 seq_printf(m, "Context on %s with no gem object\n",
1958 ring->name);
1959 return;
1960 }
1961
1962 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1963 intel_execlists_ctx_id(ctx_obj));
1964
1965 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1966 seq_puts(m, "\tNot bound in GGTT\n");
1967 else
1968 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1969
1970 if (i915_gem_object_get_pages(ctx_obj)) {
1971 seq_puts(m, "\tFailed to get pages for context object\n");
1972 return;
1973 }
1974
1975 page = i915_gem_object_get_page(ctx_obj, 1);
1976 if (!WARN_ON(page == NULL)) {
1977 reg_state = kmap_atomic(page);
1978
1979 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1980 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1981 ggtt_offset + 4096 + (j * 4),
1982 reg_state[j], reg_state[j + 1],
1983 reg_state[j + 2], reg_state[j + 3]);
1984 }
1985 kunmap_atomic(reg_state);
1986 }
1987
1988 seq_putc(m, '\n');
1989}
1990
c0ab1ae9
BW		 1991static int i915_dump_lrc(struct seq_file *m, void *unused)
1992{
1993 struct drm_info_node *node = (struct drm_info_node *) m->private;
1994 struct drm_device *dev = node->minor->dev;
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 struct intel_engine_cs *ring;
1997 struct intel_context *ctx;
1998 int ret, i;
1999
2000 if (!i915.enable_execlists) {
2001 seq_printf(m, "Logical Ring Contexts are disabled\n");
2002 return 0;
2003 }
2004
2005 ret = mutex_lock_interruptible(&dev->struct_mutex);
2006 if (ret)
2007 return ret;
2008
2009 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2010 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 2011 if (ring->default_context != ctx)
2012 i915_dump_lrc_obj(m, ring,
2013 ctx->engine[i].state);
c0ab1ae9
BW		 2014 }
2015 }
2016
2017 mutex_unlock(&dev->struct_mutex);
2018
2019 return 0;
2020}
2021
4ba70e44
OM		 2022static int i915_execlists(struct seq_file *m, void *data)
2023{
2024 struct drm_info_node *node = (struct drm_info_node *)m->private;
2025 struct drm_device *dev = node->minor->dev;
2026 struct drm_i915_private *dev_priv = dev->dev_private;
2027 struct intel_engine_cs *ring;
2028 u32 status_pointer;
2029 u8 read_pointer;
2030 u8 write_pointer;
2031 u32 status;
2032 u32 ctx_id;
2033 struct list_head *cursor;
2034 int ring_id, i;
2035 int ret;
2036
2037 if (!i915.enable_execlists) {
2038 seq_puts(m, "Logical Ring Contexts are disabled\n");
2039 return 0;
2040 }
2041
2042 ret = mutex_lock_interruptible(&dev->struct_mutex);
2043 if (ret)
2044 return ret;
2045
fc0412ec
MT		 2046 intel_runtime_pm_get(dev_priv);
2047
4ba70e44 2048 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2049 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2050 int count = 0;
2051 unsigned long flags;
2052
2053 seq_printf(m, "%s\n", ring->name);
2054
2055 status = I915_READ(RING_EXECLIST_STATUS(ring));
2056 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2057 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2058 status, ctx_id);
2059
2060 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2061 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2062
2063 read_pointer = ring->next_context_status_buffer;
2064 write_pointer = status_pointer & 0x07;
2065 if (read_pointer > write_pointer)
2066 write_pointer += 6;
2067 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2068 read_pointer, write_pointer);
2069
2070 for (i = 0; i < 6; i++) {
2071 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2072 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2073
2074 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2075 i, status, ctx_id);
2076 }
2077
2078 spin_lock_irqsave(&ring->execlist_lock, flags);
2079 list_for_each(cursor, &ring->execlist_queue)
2080 count++;
2081 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2082 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2083 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2084
2085 seq_printf(m, "\t%d requests in queue\n", count);
2086 if (head_req) {
2087 struct drm_i915_gem_object *ctx_obj;
2088
6d3d8274 2089 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2090 seq_printf(m, "\tHead request id: %u\n",
2091 intel_execlists_ctx_id(ctx_obj));
2092 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2093 head_req->tail);
4ba70e44
OM		 2094 }
2095
2096 seq_putc(m, '\n');
2097 }
2098
fc0412ec 2099 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2100 mutex_unlock(&dev->struct_mutex);
2101
2102 return 0;
2103}
2104
ea16a3cd
DV		 2105static const char *swizzle_string(unsigned swizzle)
2106{
aee56cff 2107 switch (swizzle) {
ea16a3cd
DV		 2108 case I915_BIT_6_SWIZZLE_NONE:
2109 return "none";
2110 case I915_BIT_6_SWIZZLE_9:
2111 return "bit9";
2112 case I915_BIT_6_SWIZZLE_9_10:
2113 return "bit9/bit10";
2114 case I915_BIT_6_SWIZZLE_9_11:
2115 return "bit9/bit11";
2116 case I915_BIT_6_SWIZZLE_9_10_11:
2117 return "bit9/bit10/bit11";
2118 case I915_BIT_6_SWIZZLE_9_17:
2119 return "bit9/bit17";
2120 case I915_BIT_6_SWIZZLE_9_10_17:
2121 return "bit9/bit10/bit17";
2122 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2123 return "unknown";
ea16a3cd
DV		 2124 }
2125
2126 return "bug";
2127}
2128
2129static int i915_swizzle_info(struct seq_file *m, void *data)
2130{
9f25d007 2131 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2132 struct drm_device *dev = node->minor->dev;
2133 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2134 int ret;
2135
2136 ret = mutex_lock_interruptible(&dev->struct_mutex);
2137 if (ret)
2138 return ret;
c8c8fb33 2139 intel_runtime_pm_get(dev_priv);
ea16a3cd 2140
ea16a3cd
DV		 2141 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2142 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2143 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2144 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2145
2146 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2147 seq_printf(m, "DDC = 0x%08x\n",
2148 I915_READ(DCC));
656bfa3a
DV		 2149 seq_printf(m, "DDC2 = 0x%08x\n",
2150 I915_READ(DCC2));
ea16a3cd
DV		 2151 seq_printf(m, "C0DRB3 = 0x%04x\n",
2152 I915_READ16(C0DRB3));
2153 seq_printf(m, "C1DRB3 = 0x%04x\n",
2154 I915_READ16(C1DRB3));
9d3203e1 2155 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2156 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2157 I915_READ(MAD_DIMM_C0));
2158 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2159 I915_READ(MAD_DIMM_C1));
2160 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2161 I915_READ(MAD_DIMM_C2));
2162 seq_printf(m, "TILECTL = 0x%08x\n",
2163 I915_READ(TILECTL));
5907f5fb 2164 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2165 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2166 I915_READ(GAMTARBMODE));
2167 else
2168 seq_printf(m, "ARB_MODE = 0x%08x\n",
2169 I915_READ(ARB_MODE));
3fa7d235
DV		 2170 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2171 I915_READ(DISP_ARB_CTL));
ea16a3cd 2172 }
656bfa3a
DV		 2173
2174 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2175 seq_puts(m, "L-shaped memory detected\n");
2176
c8c8fb33 2177 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2178 mutex_unlock(&dev->struct_mutex);
2179
2180 return 0;
2181}
2182
1c60fef5
BW		 2183static int per_file_ctx(int id, void *ptr, void *data)
2184{
273497e5 2185 struct intel_context *ctx = ptr;
1c60fef5 2186 struct seq_file *m = data;
ae6c4806
DV		 2187 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2188
2189 if (!ppgtt) {
2190 seq_printf(m, " no ppgtt for context %d\n",
2191 ctx->user_handle);
2192 return 0;
2193 }
1c60fef5 2194
f83d6518
OM		 2195 if (i915_gem_context_is_default(ctx))
2196 seq_puts(m, " default context:\n");
2197 else
821d66dd 2198 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2199 ppgtt->debug_dump(ppgtt, m);
2200
2201 return 0;
2202}
2203
77df6772 2204static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2205{
3cf17fc5 2206 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2207 struct intel_engine_cs *ring;
77df6772
BW		 2208 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2209 int unused, i;
3cf17fc5 2210
77df6772
BW		 2211 if (!ppgtt)
2212 return;
2213
77df6772
BW		 2214 for_each_ring(ring, dev_priv, unused) {
2215 seq_printf(m, "%s\n", ring->name);
2216 for (i = 0; i < 4; i++) {
2217 u32 offset = 0x270 + i * 8;
2218 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2219 pdp <<= 32;
2220 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2221 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2222 }
2223 }
2224}
2225
2226static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2227{
2228 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2229 struct intel_engine_cs *ring;
1c60fef5 2230 struct drm_file *file;
77df6772 2231 int i;
3cf17fc5 2232
3cf17fc5
DV		 2233 if (INTEL_INFO(dev)->gen == 6)
2234 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2235
a2c7f6fd 2236 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2237 seq_printf(m, "%s\n", ring->name);
2238 if (INTEL_INFO(dev)->gen == 7)
2239 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2240 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2241 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2242 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2243 }
2244 if (dev_priv->mm.aliasing_ppgtt) {
2245 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2246
267f0c90 2247 seq_puts(m, "aliasing PPGTT:\n");
7324cc04 2248 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
1c60fef5 2249
87d60b63 2250 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2251 }
1c60fef5
BW		 2252
2253 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2254 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2255
1c60fef5
BW		 2256 seq_printf(m, "proc: %s\n",
2257 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2258 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2259 }
2260 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2261}
2262
2263static int i915_ppgtt_info(struct seq_file *m, void *data)
2264{
9f25d007 2265 struct drm_info_node *node = m->private;
77df6772 2266 struct drm_device *dev = node->minor->dev;
c8c8fb33 2267 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2268
2269 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2270 if (ret)
2271 return ret;
c8c8fb33 2272 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2273
2274 if (INTEL_INFO(dev)->gen >= 8)
2275 gen8_ppgtt_info(m, dev);
2276 else if (INTEL_INFO(dev)->gen >= 6)
2277 gen6_ppgtt_info(m, dev);
2278
c8c8fb33 2279 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2280 mutex_unlock(&dev->struct_mutex);
2281
2282 return 0;
2283}
2284
f5a4c67d
CW		 2285static int count_irq_waiters(struct drm_i915_private *i915)
2286{
2287 struct intel_engine_cs *ring;
2288 int count = 0;
2289 int i;
2290
2291 for_each_ring(ring, i915, i)
2292 count += ring->irq_refcount;
2293
2294 return count;
2295}
2296
1854d5ca
CW		 2297static int i915_rps_boost_info(struct seq_file *m, void *data)
2298{
2299 struct drm_info_node *node = m->private;
2300 struct drm_device *dev = node->minor->dev;
2301 struct drm_i915_private *dev_priv = dev->dev_private;
2302 struct drm_file *file;
1854d5ca 2303
f5a4c67d
CW		 2304 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2305 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2306 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2307 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2308 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2309 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2310 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2311 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2312 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2313 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2314 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2315 struct drm_i915_file_private *file_priv = file->driver_priv;
2316 struct task_struct *task;
2317
2318 rcu_read_lock();
2319 task = pid_task(file->pid, PIDTYPE_PID);
2320 seq_printf(m, "%s [%d]: %d boosts%s\n",
2321 task ? task->comm : "<unknown>",
2322 task ? task->pid : -1,
2e1b8730
CW		 2323 file_priv->rps.boosts,
2324 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2325 rcu_read_unlock();
2326 }
2e1b8730
CW		 2327 seq_printf(m, "Semaphore boosts: %d%s\n",
2328 dev_priv->rps.semaphores.boosts,
2329 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2330 seq_printf(m, "MMIO flip boosts: %d%s\n",
2331 dev_priv->rps.mmioflips.boosts,
2332 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2333 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2334 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2335
8d3afd7d 2336 return 0;
1854d5ca
CW		 2337}
2338
63573eb7
BW		 2339static int i915_llc(struct seq_file *m, void *data)
2340{
9f25d007 2341 struct drm_info_node *node = m->private;
63573eb7
BW		 2342 struct drm_device *dev = node->minor->dev;
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344
2345 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2346 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2347 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2348
2349 return 0;
2350}
2351
e91fd8c6
RV		 2352static int i915_edp_psr_status(struct seq_file *m, void *data)
2353{
2354 struct drm_info_node *node = m->private;
2355 struct drm_device *dev = node->minor->dev;
2356 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2357 u32 psrperf = 0;
a6cbdb8e
RV		 2358 u32 stat[3];
2359 enum pipe pipe;
a031d709 2360 bool enabled = false;
e91fd8c6 2361
3553a8ea
DL		 2362 if (!HAS_PSR(dev)) {
2363 seq_puts(m, "PSR not supported\n");
2364 return 0;
2365 }
2366
c8c8fb33
PZ		 2367 intel_runtime_pm_get(dev_priv);
2368
fa128fa6 2369 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2370 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2371 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2372 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2373 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2374 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2375 dev_priv->psr.busy_frontbuffer_bits);
2376 seq_printf(m, "Re-enable work scheduled: %s\n",
2377 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2378
3553a8ea
DL		 2379 if (HAS_DDI(dev))
2380 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2381 else {
2382 for_each_pipe(dev_priv, pipe) {
2383 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2384 VLV_EDP_PSR_CURR_STATE_MASK;
2385 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2386 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2387 enabled = true;
a6cbdb8e
RV		 2388 }
2389 }
2390 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2391
2392 if (!HAS_DDI(dev))
2393 for_each_pipe(dev_priv, pipe) {
2394 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2395 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2396 seq_printf(m, " pipe %c", pipe_name(pipe));
2397 }
2398 seq_puts(m, "\n");
e91fd8c6 2399
a6cbdb8e 2400 /* CHV PSR has no kind of performance counter */
3553a8ea 2401 if (HAS_DDI(dev)) {
a031d709
RV		 2402 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2403 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2404
2405 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2406 }
fa128fa6 2407 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2408
c8c8fb33 2409 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2410 return 0;
2411}
2412
d2e216d0
RV		 2413static int i915_sink_crc(struct seq_file *m, void *data)
2414{
2415 struct drm_info_node *node = m->private;
2416 struct drm_device *dev = node->minor->dev;
2417 struct intel_encoder *encoder;
2418 struct intel_connector *connector;
2419 struct intel_dp *intel_dp = NULL;
2420 int ret;
2421 u8 crc[6];
2422
2423 drm_modeset_lock_all(dev);
aca5e361 2424 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2425
2426 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2427 continue;
2428
b6ae3c7c
PZ		 2429 if (!connector->base.encoder)
2430 continue;
2431
d2e216d0
RV		 2432 encoder = to_intel_encoder(connector->base.encoder);
2433 if (encoder->type != INTEL_OUTPUT_EDP)
2434 continue;
2435
2436 intel_dp = enc_to_intel_dp(&encoder->base);
2437
2438 ret = intel_dp_sink_crc(intel_dp, crc);
2439 if (ret)
2440 goto out;
2441
2442 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2443 crc[0], crc[1], crc[2],
2444 crc[3], crc[4], crc[5]);
2445 goto out;
2446 }
2447 ret = -ENODEV;
2448out:
2449 drm_modeset_unlock_all(dev);
2450 return ret;
2451}
2452
ec013e7f
JB		 2453static int i915_energy_uJ(struct seq_file *m, void *data)
2454{
2455 struct drm_info_node *node = m->private;
2456 struct drm_device *dev = node->minor->dev;
2457 struct drm_i915_private *dev_priv = dev->dev_private;
2458 u64 power;
2459 u32 units;
2460
2461 if (INTEL_INFO(dev)->gen < 6)
2462 return -ENODEV;
2463
36623ef8
PZ		 2464 intel_runtime_pm_get(dev_priv);
2465
ec013e7f
JB		 2466 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2467 power = (power & 0x1f00) >> 8;
2468 units = 1000000 / (1 << power); /* convert to uJ */
2469 power = I915_READ(MCH_SECP_NRG_STTS);
2470 power *= units;
2471
36623ef8
PZ		 2472 intel_runtime_pm_put(dev_priv);
2473
ec013e7f 2474 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2475
2476 return 0;
2477}
2478
6455c870 2479static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2480{
9f25d007 2481 struct drm_info_node *node = m->private;
371db66a
PZ		 2482 struct drm_device *dev = node->minor->dev;
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2484
6455c870 2485 if (!HAS_RUNTIME_PM(dev)) {
371db66a
PZ		 2486 seq_puts(m, "not supported\n");
2487 return 0;
2488 }
2489
86c4ec0d 2490 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2491 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2492 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2493#ifdef CONFIG_PM
a6aaec8b
DL		 2494 seq_printf(m, "Usage count: %d\n",
2495 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2496#else
2497 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2498#endif
371db66a 2499
ec013e7f
JB		 2500 return 0;
2501}
2502
1da51581
ID		 2503static const char *power_domain_str(enum intel_display_power_domain domain)
2504{
2505 switch (domain) {
2506 case POWER_DOMAIN_PIPE_A:
2507 return "PIPE_A";
2508 case POWER_DOMAIN_PIPE_B:
2509 return "PIPE_B";
2510 case POWER_DOMAIN_PIPE_C:
2511 return "PIPE_C";
2512 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2513 return "PIPE_A_PANEL_FITTER";
2514 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2515 return "PIPE_B_PANEL_FITTER";
2516 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2517 return "PIPE_C_PANEL_FITTER";
2518 case POWER_DOMAIN_TRANSCODER_A:
2519 return "TRANSCODER_A";
2520 case POWER_DOMAIN_TRANSCODER_B:
2521 return "TRANSCODER_B";
2522 case POWER_DOMAIN_TRANSCODER_C:
2523 return "TRANSCODER_C";
2524 case POWER_DOMAIN_TRANSCODER_EDP:
2525 return "TRANSCODER_EDP";
319be8ae
ID		 2526 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2527 return "PORT_DDI_A_2_LANES";
2528 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2529 return "PORT_DDI_A_4_LANES";
2530 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2531 return "PORT_DDI_B_2_LANES";
2532 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2533 return "PORT_DDI_B_4_LANES";
2534 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2535 return "PORT_DDI_C_2_LANES";
2536 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2537 return "PORT_DDI_C_4_LANES";
2538 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2539 return "PORT_DDI_D_2_LANES";
2540 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2541 return "PORT_DDI_D_4_LANES";
2542 case POWER_DOMAIN_PORT_DSI:
2543 return "PORT_DSI";
2544 case POWER_DOMAIN_PORT_CRT:
2545 return "PORT_CRT";
2546 case POWER_DOMAIN_PORT_OTHER:
2547 return "PORT_OTHER";
1da51581
ID		 2548 case POWER_DOMAIN_VGA:
2549 return "VGA";
2550 case POWER_DOMAIN_AUDIO:
2551 return "AUDIO";
bd2bb1b9
PZ		 2552 case POWER_DOMAIN_PLLS:
2553 return "PLLS";
1407121a
S		 2554 case POWER_DOMAIN_AUX_A:
2555 return "AUX_A";
2556 case POWER_DOMAIN_AUX_B:
2557 return "AUX_B";
2558 case POWER_DOMAIN_AUX_C:
2559 return "AUX_C";
2560 case POWER_DOMAIN_AUX_D:
2561 return "AUX_D";
1da51581
ID		 2562 case POWER_DOMAIN_INIT:
2563 return "INIT";
2564 default:
5f77eeb0 2565 MISSING_CASE(domain);
1da51581
ID		 2566 return "?";
2567 }
2568}
2569
2570static int i915_power_domain_info(struct seq_file *m, void *unused)
2571{
9f25d007 2572 struct drm_info_node *node = m->private;
1da51581
ID		 2573 struct drm_device *dev = node->minor->dev;
2574 struct drm_i915_private *dev_priv = dev->dev_private;
2575 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2576 int i;
2577
2578 mutex_lock(&power_domains->lock);
2579
2580 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2581 for (i = 0; i < power_domains->power_well_count; i++) {
2582 struct i915_power_well *power_well;
2583 enum intel_display_power_domain power_domain;
2584
2585 power_well = &power_domains->power_wells[i];
2586 seq_printf(m, "%-25s %d\n", power_well->name,
2587 power_well->count);
2588
2589 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2590 power_domain++) {
2591 if (!(BIT(power_domain) & power_well->domains))
2592 continue;
2593
2594 seq_printf(m, " %-23s %d\n",
2595 power_domain_str(power_domain),
2596 power_domains->domain_use_count[power_domain]);
2597 }
2598 }
2599
2600 mutex_unlock(&power_domains->lock);
2601
2602 return 0;
2603}
2604
53f5e3ca
JB		 2605static void intel_seq_print_mode(struct seq_file *m, int tabs,
2606 struct drm_display_mode *mode)
2607{
2608 int i;
2609
2610 for (i = 0; i < tabs; i++)
2611 seq_putc(m, '\t');
2612
2613 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2614 mode->base.id, mode->name,
2615 mode->vrefresh, mode->clock,
2616 mode->hdisplay, mode->hsync_start,
2617 mode->hsync_end, mode->htotal,
2618 mode->vdisplay, mode->vsync_start,
2619 mode->vsync_end, mode->vtotal,
2620 mode->type, mode->flags);
2621}
2622
2623static void intel_encoder_info(struct seq_file *m,
2624 struct intel_crtc *intel_crtc,
2625 struct intel_encoder *intel_encoder)
2626{
9f25d007 2627 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2628 struct drm_device *dev = node->minor->dev;
2629 struct drm_crtc *crtc = &intel_crtc->base;
2630 struct intel_connector *intel_connector;
2631 struct drm_encoder *encoder;
2632
2633 encoder = &intel_encoder->base;
2634 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2635 encoder->base.id, encoder->name);
53f5e3ca
JB		 2636 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2637 struct drm_connector *connector = &intel_connector->base;
2638 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2639 connector->base.id,
c23cc417 2640 connector->name,
53f5e3ca
JB		 2641 drm_get_connector_status_name(connector->status));
2642 if (connector->status == connector_status_connected) {
2643 struct drm_display_mode *mode = &crtc->mode;
2644 seq_printf(m, ", mode:\n");
2645 intel_seq_print_mode(m, 2, mode);
2646 } else {
2647 seq_putc(m, '\n');
2648 }
2649 }
2650}
2651
2652static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2653{
9f25d007 2654 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2655 struct drm_device *dev = node->minor->dev;
2656 struct drm_crtc *crtc = &intel_crtc->base;
2657 struct intel_encoder *intel_encoder;
2658
5aa8a937
MR		 2659 if (crtc->primary->fb)
2660 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2661 crtc->primary->fb->base.id, crtc->x, crtc->y,
2662 crtc->primary->fb->width, crtc->primary->fb->height);
2663 else
2664 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2665 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2666 intel_encoder_info(m, intel_crtc, intel_encoder);
2667}
2668
2669static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2670{
2671 struct drm_display_mode *mode = panel->fixed_mode;
2672
2673 seq_printf(m, "\tfixed mode:\n");
2674 intel_seq_print_mode(m, 2, mode);
2675}
2676
2677static void intel_dp_info(struct seq_file *m,
2678 struct intel_connector *intel_connector)
2679{
2680 struct intel_encoder *intel_encoder = intel_connector->encoder;
2681 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2682
2683 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2684 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2685 "no");
2686 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2687 intel_panel_info(m, &intel_connector->panel);
2688}
2689
2690static void intel_hdmi_info(struct seq_file *m,
2691 struct intel_connector *intel_connector)
2692{
2693 struct intel_encoder *intel_encoder = intel_connector->encoder;
2694 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2695
2696 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2697 "no");
2698}
2699
2700static void intel_lvds_info(struct seq_file *m,
2701 struct intel_connector *intel_connector)
2702{
2703 intel_panel_info(m, &intel_connector->panel);
2704}
2705
2706static void intel_connector_info(struct seq_file *m,
2707 struct drm_connector *connector)
2708{
2709 struct intel_connector *intel_connector = to_intel_connector(connector);
2710 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2711 struct drm_display_mode *mode;
53f5e3ca
JB		 2712
2713 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2714 connector->base.id, connector->name,
53f5e3ca
JB		 2715 drm_get_connector_status_name(connector->status));
2716 if (connector->status == connector_status_connected) {
2717 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2718 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2719 connector->display_info.width_mm,
2720 connector->display_info.height_mm);
2721 seq_printf(m, "\tsubpixel order: %s\n",
2722 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2723 seq_printf(m, "\tCEA rev: %d\n",
2724 connector->display_info.cea_rev);
2725 }
36cd7444
DA		 2726 if (intel_encoder) {
2727 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2728 intel_encoder->type == INTEL_OUTPUT_EDP)
2729 intel_dp_info(m, intel_connector);
2730 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2731 intel_hdmi_info(m, intel_connector);
2732 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2733 intel_lvds_info(m, intel_connector);
2734 }
53f5e3ca 2735
f103fc7d
JB		 2736 seq_printf(m, "\tmodes:\n");
2737 list_for_each_entry(mode, &connector->modes, head)
2738 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2739}
2740
065f2ec2
CW		 2741static bool cursor_active(struct drm_device *dev, int pipe)
2742{
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744 u32 state;
2745
2746 if (IS_845G(dev) || IS_I865G(dev))
2747 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2748 else
5efb3e28 2749 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2750
2751 return state;
2752}
2753
2754static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2755{
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 u32 pos;
2758
5efb3e28 2759 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2760
2761 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2762 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2763 *x = -*x;
2764
2765 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2766 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2767 *y = -*y;
2768
2769 return cursor_active(dev, pipe);
2770}
2771
53f5e3ca
JB		 2772static int i915_display_info(struct seq_file *m, void *unused)
2773{
9f25d007 2774 struct drm_info_node *node = m->private;
53f5e3ca 2775 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2776 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2777 struct intel_crtc *crtc;
53f5e3ca
JB		 2778 struct drm_connector *connector;
2779
b0e5ddf3 2780 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2781 drm_modeset_lock_all(dev);
2782 seq_printf(m, "CRTC info\n");
2783 seq_printf(m, "---------\n");
d3fcc808 2784 for_each_intel_crtc(dev, crtc) {
065f2ec2 2785 bool active;
f77076c9 2786 struct intel_crtc_state *pipe_config;
065f2ec2 2787 int x, y;
53f5e3ca 2788
f77076c9
ML		 2789 pipe_config = to_intel_crtc_state(crtc->base.state);
2790
57127efa 2791 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2792 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9
ML		 2793 yesno(pipe_config->base.active),
2794 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2795 if (pipe_config->base.active) {
065f2ec2
CW		 2796 intel_crtc_info(m, crtc);
2797
a23dc658 2798 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2799 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2800 yesno(crtc->cursor_base),
3dd512fb
MR		 2801 x, y, crtc->base.cursor->state->crtc_w,
2802 crtc->base.cursor->state->crtc_h,
57127efa 2803 crtc->cursor_addr, yesno(active));
a23dc658 2804 }
cace841c
DV		 2805
2806 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2807 yesno(!crtc->cpu_fifo_underrun_disabled),
2808 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2809 }
2810
2811 seq_printf(m, "\n");
2812 seq_printf(m, "Connector info\n");
2813 seq_printf(m, "--------------\n");
2814 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2815 intel_connector_info(m, connector);
2816 }
2817 drm_modeset_unlock_all(dev);
b0e5ddf3 2818 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2819
2820 return 0;
2821}
2822
e04934cf
BW		 2823static int i915_semaphore_status(struct seq_file *m, void *unused)
2824{
2825 struct drm_info_node *node = (struct drm_info_node *) m->private;
2826 struct drm_device *dev = node->minor->dev;
2827 struct drm_i915_private *dev_priv = dev->dev_private;
2828 struct intel_engine_cs *ring;
2829 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2830 int i, j, ret;
2831
2832 if (!i915_semaphore_is_enabled(dev)) {
2833 seq_puts(m, "Semaphores are disabled\n");
2834 return 0;
2835 }
2836
2837 ret = mutex_lock_interruptible(&dev->struct_mutex);
2838 if (ret)
2839 return ret;
03872064 2840 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2841
2842 if (IS_BROADWELL(dev)) {
2843 struct page *page;
2844 uint64_t *seqno;
2845
2846 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2847
2848 seqno = (uint64_t *)kmap_atomic(page);
2849 for_each_ring(ring, dev_priv, i) {
2850 uint64_t offset;
2851
2852 seq_printf(m, "%s\n", ring->name);
2853
2854 seq_puts(m, " Last signal:");
2855 for (j = 0; j < num_rings; j++) {
2856 offset = i * I915_NUM_RINGS + j;
2857 seq_printf(m, "0x%08llx (0x%02llx) ",
2858 seqno[offset], offset * 8);
2859 }
2860 seq_putc(m, '\n');
2861
2862 seq_puts(m, " Last wait: ");
2863 for (j = 0; j < num_rings; j++) {
2864 offset = i + (j * I915_NUM_RINGS);
2865 seq_printf(m, "0x%08llx (0x%02llx) ",
2866 seqno[offset], offset * 8);
2867 }
2868 seq_putc(m, '\n');
2869
2870 }
2871 kunmap_atomic(seqno);
2872 } else {
2873 seq_puts(m, " Last signal:");
2874 for_each_ring(ring, dev_priv, i)
2875 for (j = 0; j < num_rings; j++)
2876 seq_printf(m, "0x%08x\n",
2877 I915_READ(ring->semaphore.mbox.signal[j]));
2878 seq_putc(m, '\n');
2879 }
2880
2881 seq_puts(m, "\nSync seqno:\n");
2882 for_each_ring(ring, dev_priv, i) {
2883 for (j = 0; j < num_rings; j++) {
2884 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2885 }
2886 seq_putc(m, '\n');
2887 }
2888 seq_putc(m, '\n');
2889
03872064 2890 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2891 mutex_unlock(&dev->struct_mutex);
2892 return 0;
2893}
2894
728e29d7
DV		 2895static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2896{
2897 struct drm_info_node *node = (struct drm_info_node *) m->private;
2898 struct drm_device *dev = node->minor->dev;
2899 struct drm_i915_private *dev_priv = dev->dev_private;
2900 int i;
2901
2902 drm_modeset_lock_all(dev);
2903 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2904 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2905
2906 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2907 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2908 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2909 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2910 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2911 seq_printf(m, " dpll_md: 0x%08x\n",
2912 pll->config.hw_state.dpll_md);
2913 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2914 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2915 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2916 }
2917 drm_modeset_unlock_all(dev);
2918
2919 return 0;
2920}
2921
1ed1ef9d 2922static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2923{
2924 int i;
2925 int ret;
2926 struct drm_info_node *node = (struct drm_info_node *) m->private;
2927 struct drm_device *dev = node->minor->dev;
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929
888b5995
AS		 2930 ret = mutex_lock_interruptible(&dev->struct_mutex);
2931 if (ret)
2932 return ret;
2933
2934 intel_runtime_pm_get(dev_priv);
2935
7225342a
MK		 2936 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2937 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2938 u32 addr, mask, value, read;
2939 bool ok;
888b5995 2940
7225342a
MK		 2941 addr = dev_priv->workarounds.reg[i].addr;
2942 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2943 value = dev_priv->workarounds.reg[i].value;
2944 read = I915_READ(addr);
2945 ok = (value & mask) == (read & mask);
2946 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2947 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2948 }
2949
2950 intel_runtime_pm_put(dev_priv);
2951 mutex_unlock(&dev->struct_mutex);
2952
2953 return 0;
2954}
2955
c5511e44
DL		 2956static int i915_ddb_info(struct seq_file *m, void *unused)
2957{
2958 struct drm_info_node *node = m->private;
2959 struct drm_device *dev = node->minor->dev;
2960 struct drm_i915_private *dev_priv = dev->dev_private;
2961 struct skl_ddb_allocation *ddb;
2962 struct skl_ddb_entry *entry;
2963 enum pipe pipe;
2964 int plane;
2965
2fcffe19
DL		 2966 if (INTEL_INFO(dev)->gen < 9)
2967 return 0;
2968
c5511e44
DL		 2969 drm_modeset_lock_all(dev);
2970
2971 ddb = &dev_priv->wm.skl_hw.ddb;
2972
2973 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2974
2975 for_each_pipe(dev_priv, pipe) {
2976 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2977
dd740780 2978 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 2979 entry = &ddb->plane[pipe][plane];
2980 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2981 entry->start, entry->end,
2982 skl_ddb_entry_size(entry));
2983 }
2984
2985 entry = &ddb->cursor[pipe];
2986 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2987 entry->end, skl_ddb_entry_size(entry));
2988 }
2989
2990 drm_modeset_unlock_all(dev);
2991
2992 return 0;
2993}
2994
a54746e3
VK		 2995static void drrs_status_per_crtc(struct seq_file *m,
2996 struct drm_device *dev, struct intel_crtc *intel_crtc)
2997{
2998 struct intel_encoder *intel_encoder;
2999 struct drm_i915_private *dev_priv = dev->dev_private;
3000 struct i915_drrs *drrs = &dev_priv->drrs;
3001 int vrefresh = 0;
3002
3003 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3004 /* Encoder connected on this CRTC */
3005 switch (intel_encoder->type) {
3006 case INTEL_OUTPUT_EDP:
3007 seq_puts(m, "eDP:\n");
3008 break;
3009 case INTEL_OUTPUT_DSI:
3010 seq_puts(m, "DSI:\n");
3011 break;
3012 case INTEL_OUTPUT_HDMI:
3013 seq_puts(m, "HDMI:\n");
3014 break;
3015 case INTEL_OUTPUT_DISPLAYPORT:
3016 seq_puts(m, "DP:\n");
3017 break;
3018 default:
3019 seq_printf(m, "Other encoder (id=%d).\n",
3020 intel_encoder->type);
3021 return;
3022 }
3023 }
3024
3025 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3026 seq_puts(m, "\tVBT: DRRS_type: Static");
3027 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3028 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3029 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3030 seq_puts(m, "\tVBT: DRRS_type: None");
3031 else
3032 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3033
3034 seq_puts(m, "\n\n");
3035
f77076c9 3036 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3037 struct intel_panel *panel;
3038
3039 mutex_lock(&drrs->mutex);
3040 /* DRRS Supported */
3041 seq_puts(m, "\tDRRS Supported: Yes\n");
3042
3043 /* disable_drrs() will make drrs->dp NULL */
3044 if (!drrs->dp) {
3045 seq_puts(m, "Idleness DRRS: Disabled");
3046 mutex_unlock(&drrs->mutex);
3047 return;
3048 }
3049
3050 panel = &drrs->dp->attached_connector->panel;
3051 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3052 drrs->busy_frontbuffer_bits);
3053
3054 seq_puts(m, "\n\t\t");
3055 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3056 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3057 vrefresh = panel->fixed_mode->vrefresh;
3058 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3059 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3060 vrefresh = panel->downclock_mode->vrefresh;
3061 } else {
3062 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3063 drrs->refresh_rate_type);
3064 mutex_unlock(&drrs->mutex);
3065 return;
3066 }
3067 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3068
3069 seq_puts(m, "\n\t\t");
3070 mutex_unlock(&drrs->mutex);
3071 } else {
3072 /* DRRS not supported. Print the VBT parameter*/
3073 seq_puts(m, "\tDRRS Supported : No");
3074 }
3075 seq_puts(m, "\n");
3076}
3077
3078static int i915_drrs_status(struct seq_file *m, void *unused)
3079{
3080 struct drm_info_node *node = m->private;
3081 struct drm_device *dev = node->minor->dev;
3082 struct intel_crtc *intel_crtc;
3083 int active_crtc_cnt = 0;
3084
3085 for_each_intel_crtc(dev, intel_crtc) {
3086 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3087
f77076c9 3088 if (intel_crtc->base.state->active) {
a54746e3
VK		 3089 active_crtc_cnt++;
3090 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3091
3092 drrs_status_per_crtc(m, dev, intel_crtc);
3093 }
3094
3095 drm_modeset_unlock(&intel_crtc->base.mutex);
3096 }
3097
3098 if (!active_crtc_cnt)
3099 seq_puts(m, "No active crtc found\n");
3100
3101 return 0;
3102}
3103
07144428
DL		 3104struct pipe_crc_info {
3105 const char *name;
3106 struct drm_device *dev;
3107 enum pipe pipe;
3108};
3109
11bed958
DA		 3110static int i915_dp_mst_info(struct seq_file *m, void *unused)
3111{
3112 struct drm_info_node *node = (struct drm_info_node *) m->private;
3113 struct drm_device *dev = node->minor->dev;
3114 struct drm_encoder *encoder;
3115 struct intel_encoder *intel_encoder;
3116 struct intel_digital_port *intel_dig_port;
3117 drm_modeset_lock_all(dev);
3118 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3119 intel_encoder = to_intel_encoder(encoder);
3120 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3121 continue;
3122 intel_dig_port = enc_to_dig_port(encoder);
3123 if (!intel_dig_port->dp.can_mst)
3124 continue;
3125
3126 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3127 }
3128 drm_modeset_unlock_all(dev);
3129 return 0;
3130}
3131
07144428
DL		 3132static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3133{
be5c7a90
DL		 3134 struct pipe_crc_info *info = inode->i_private;
3135 struct drm_i915_private *dev_priv = info->dev->dev_private;
3136 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3137
7eb1c496
DV		 3138 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3139 return -ENODEV;
3140
d538bbdf
DL		 3141 spin_lock_irq(&pipe_crc->lock);
3142
3143 if (pipe_crc->opened) {
3144 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3145 return -EBUSY; /* already open */
3146 }
3147
d538bbdf 3148 pipe_crc->opened = true;
07144428
DL		 3149 filep->private_data = inode->i_private;
3150
d538bbdf
DL		 3151 spin_unlock_irq(&pipe_crc->lock);
3152
07144428
DL		 3153 return 0;
3154}
3155
3156static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3157{
be5c7a90
DL		 3158 struct pipe_crc_info *info = inode->i_private;
3159 struct drm_i915_private *dev_priv = info->dev->dev_private;
3160 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3161
d538bbdf
DL		 3162 spin_lock_irq(&pipe_crc->lock);
3163 pipe_crc->opened = false;
3164 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3165
07144428
DL		 3166 return 0;
3167}
3168
3169/* (6 fields, 8 chars each, space separated (5) + '\n') */
3170#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3171/* account for \'0' */
3172#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3173
3174static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3175{
d538bbdf
DL		 3176 assert_spin_locked(&pipe_crc->lock);
3177 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3178 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3179}
3180
3181static ssize_t
3182i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3183 loff_t *pos)
3184{
3185 struct pipe_crc_info *info = filep->private_data;
3186 struct drm_device *dev = info->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3189 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3190 int n_entries;
07144428
DL		 3191 ssize_t bytes_read;
3192
3193 /*
3194 * Don't allow user space to provide buffers not big enough to hold
3195 * a line of data.
3196 */
3197 if (count < PIPE_CRC_LINE_LEN)
3198 return -EINVAL;
3199
3200 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3201 return 0;
07144428
DL		 3202
3203 /* nothing to read */
d538bbdf 3204 spin_lock_irq(&pipe_crc->lock);
07144428 3205 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3206 int ret;
3207
3208 if (filep->f_flags & O_NONBLOCK) {
3209 spin_unlock_irq(&pipe_crc->lock);
07144428 3210 return -EAGAIN;
d538bbdf 3211 }
07144428 3212
d538bbdf
DL		 3213 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3214 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3215 if (ret) {
3216 spin_unlock_irq(&pipe_crc->lock);
3217 return ret;
3218 }
8bf1e9f1
SH		 3219 }
3220
07144428 3221 /* We now have one or more entries to read */
9ad6d99f 3222 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3223
07144428 3224 bytes_read = 0;
9ad6d99f
VS		 3225 while (n_entries > 0) {
3226 struct intel_pipe_crc_entry *entry =
3227 &pipe_crc->entries[pipe_crc->tail];
07144428 3228 int ret;
8bf1e9f1 3229
9ad6d99f
VS		 3230 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3231 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3232 break;
3233
3234 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3235 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3236
07144428
DL		 3237 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3238 "%8u %8x %8x %8x %8x %8x\n",
3239 entry->frame, entry->crc[0],
3240 entry->crc[1], entry->crc[2],
3241 entry->crc[3], entry->crc[4]);
3242
9ad6d99f
VS		 3243 spin_unlock_irq(&pipe_crc->lock);
3244
3245 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3246 if (ret == PIPE_CRC_LINE_LEN)
3247 return -EFAULT;
b2c88f5b 3248
9ad6d99f
VS		 3249 user_buf += PIPE_CRC_LINE_LEN;
3250 n_entries--;
3251
3252 spin_lock_irq(&pipe_crc->lock);
3253 }
8bf1e9f1 3254
d538bbdf
DL		 3255 spin_unlock_irq(&pipe_crc->lock);
3256
07144428
DL		 3257 return bytes_read;
3258}
3259
3260static const struct file_operations i915_pipe_crc_fops = {
3261 .owner = THIS_MODULE,
3262 .open = i915_pipe_crc_open,
3263 .read = i915_pipe_crc_read,
3264 .release = i915_pipe_crc_release,
3265};
3266
3267static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3268 {
3269 .name = "i915_pipe_A_crc",
3270 .pipe = PIPE_A,
3271 },
3272 {
3273 .name = "i915_pipe_B_crc",
3274 .pipe = PIPE_B,
3275 },
3276 {
3277 .name = "i915_pipe_C_crc",
3278 .pipe = PIPE_C,
3279 },
3280};
3281
3282static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3283 enum pipe pipe)
3284{
3285 struct drm_device *dev = minor->dev;
3286 struct dentry *ent;
3287 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3288
3289 info->dev = dev;
3290 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3291 &i915_pipe_crc_fops);
f3c5fe97
WY		 3292 if (!ent)
3293 return -ENOMEM;
07144428
DL		 3294
3295 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3296}
3297
e8dfcf78 3298static const char * const pipe_crc_sources[] = {
926321d5
DV		 3299 "none",
3300 "plane1",
3301 "plane2",
3302 "pf",
5b3a856b 3303 "pipe",
3d099a05
DV		 3304 "TV",
3305 "DP-B",
3306 "DP-C",
3307 "DP-D",
46a19188 3308 "auto",
926321d5
DV		 3309};
3310
3311static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3312{
3313 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3314 return pipe_crc_sources[source];
3315}
3316
bd9db02f 3317static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3318{
3319 struct drm_device *dev = m->private;
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 int i;
3322
3323 for (i = 0; i < I915_MAX_PIPES; i++)
3324 seq_printf(m, "%c %s\n", pipe_name(i),
3325 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3326
3327 return 0;
3328}
3329
bd9db02f 3330static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3331{
3332 struct drm_device *dev = inode->i_private;
3333
bd9db02f 3334 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3335}
3336
46a19188 3337static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3338 uint32_t *val)
3339{
46a19188
DV		 3340 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3341 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3342
3343 switch (*source) {
52f843f6
DV		 3344 case INTEL_PIPE_CRC_SOURCE_PIPE:
3345 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3346 break;
3347 case INTEL_PIPE_CRC_SOURCE_NONE:
3348 *val = 0;
3349 break;
3350 default:
3351 return -EINVAL;
3352 }
3353
3354 return 0;
3355}
3356
46a19188
DV		 3357static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3358 enum intel_pipe_crc_source *source)
3359{
3360 struct intel_encoder *encoder;
3361 struct intel_crtc *crtc;
26756809 3362 struct intel_digital_port *dig_port;
46a19188
DV		 3363 int ret = 0;
3364
3365 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3366
6e9f798d 3367 drm_modeset_lock_all(dev);
b2784e15 3368 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3369 if (!encoder->base.crtc)
3370 continue;
3371
3372 crtc = to_intel_crtc(encoder->base.crtc);
3373
3374 if (crtc->pipe != pipe)
3375 continue;
3376
3377 switch (encoder->type) {
3378 case INTEL_OUTPUT_TVOUT:
3379 *source = INTEL_PIPE_CRC_SOURCE_TV;
3380 break;
3381 case INTEL_OUTPUT_DISPLAYPORT:
3382 case INTEL_OUTPUT_EDP:
26756809
DV		 3383 dig_port = enc_to_dig_port(&encoder->base);
3384 switch (dig_port->port) {
3385 case PORT_B:
3386 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3387 break;
3388 case PORT_C:
3389 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3390 break;
3391 case PORT_D:
3392 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3393 break;
3394 default:
3395 WARN(1, "nonexisting DP port %c\n",
3396 port_name(dig_port->port));
3397 break;
3398 }
46a19188 3399 break;
6847d71b
PZ		 3400 default:
3401 break;
46a19188
DV		 3402 }
3403 }
6e9f798d 3404 drm_modeset_unlock_all(dev);
46a19188
DV		 3405
3406 return ret;
3407}
3408
3409static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3410 enum pipe pipe,
3411 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3412 uint32_t *val)
3413{
8d2f24ca
DV		 3414 struct drm_i915_private *dev_priv = dev->dev_private;
3415 bool need_stable_symbols = false;
3416
46a19188
DV		 3417 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3418 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3419 if (ret)
3420 return ret;
3421 }
3422
3423 switch (*source) {
7ac0129b
DV		 3424 case INTEL_PIPE_CRC_SOURCE_PIPE:
3425 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3426 break;
3427 case INTEL_PIPE_CRC_SOURCE_DP_B:
3428 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3429 need_stable_symbols = true;
7ac0129b
DV		 3430 break;
3431 case INTEL_PIPE_CRC_SOURCE_DP_C:
3432 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3433 need_stable_symbols = true;
7ac0129b 3434 break;
2be57922
VS		 3435 case INTEL_PIPE_CRC_SOURCE_DP_D:
3436 if (!IS_CHERRYVIEW(dev))
3437 return -EINVAL;
3438 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3439 need_stable_symbols = true;
3440 break;
7ac0129b
DV		 3441 case INTEL_PIPE_CRC_SOURCE_NONE:
3442 *val = 0;
3443 break;
3444 default:
3445 return -EINVAL;
3446 }
3447
8d2f24ca
DV		 3448 /*
3449 * When the pipe CRC tap point is after the transcoders we need
3450 * to tweak symbol-level features to produce a deterministic series of
3451 * symbols for a given frame. We need to reset those features only once
3452 * a frame (instead of every nth symbol):
3453 * - DC-balance: used to ensure a better clock recovery from the data
3454 * link (SDVO)
3455 * - DisplayPort scrambling: used for EMI reduction
3456 */
3457 if (need_stable_symbols) {
3458 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3459
8d2f24ca 3460 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3461 switch (pipe) {
3462 case PIPE_A:
8d2f24ca 3463 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3464 break;
3465 case PIPE_B:
8d2f24ca 3466 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3467 break;
3468 case PIPE_C:
3469 tmp |= PIPE_C_SCRAMBLE_RESET;
3470 break;
3471 default:
3472 return -EINVAL;
3473 }
8d2f24ca
DV		 3474 I915_WRITE(PORT_DFT2_G4X, tmp);
3475 }
3476
7ac0129b
DV		 3477 return 0;
3478}
3479
4b79ebf7 3480static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3481 enum pipe pipe,
3482 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3483 uint32_t *val)
3484{
84093603
DV		 3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486 bool need_stable_symbols = false;
3487
46a19188
DV		 3488 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3489 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3490 if (ret)
3491 return ret;
3492 }
3493
3494 switch (*source) {
4b79ebf7
DV		 3495 case INTEL_PIPE_CRC_SOURCE_PIPE:
3496 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3497 break;
3498 case INTEL_PIPE_CRC_SOURCE_TV:
3499 if (!SUPPORTS_TV(dev))
3500 return -EINVAL;
3501 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3502 break;
3503 case INTEL_PIPE_CRC_SOURCE_DP_B:
3504 if (!IS_G4X(dev))
3505 return -EINVAL;
3506 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3507 need_stable_symbols = true;
4b79ebf7
DV		 3508 break;
3509 case INTEL_PIPE_CRC_SOURCE_DP_C:
3510 if (!IS_G4X(dev))
3511 return -EINVAL;
3512 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3513 need_stable_symbols = true;
4b79ebf7
DV		 3514 break;
3515 case INTEL_PIPE_CRC_SOURCE_DP_D:
3516 if (!IS_G4X(dev))
3517 return -EINVAL;
3518 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3519 need_stable_symbols = true;
4b79ebf7
DV		 3520 break;
3521 case INTEL_PIPE_CRC_SOURCE_NONE:
3522 *val = 0;
3523 break;
3524 default:
3525 return -EINVAL;
3526 }
3527
84093603
DV		 3528 /*
3529 * When the pipe CRC tap point is after the transcoders we need
3530 * to tweak symbol-level features to produce a deterministic series of
3531 * symbols for a given frame. We need to reset those features only once
3532 * a frame (instead of every nth symbol):
3533 * - DC-balance: used to ensure a better clock recovery from the data
3534 * link (SDVO)
3535 * - DisplayPort scrambling: used for EMI reduction
3536 */
3537 if (need_stable_symbols) {
3538 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3539
3540 WARN_ON(!IS_G4X(dev));
3541
3542 I915_WRITE(PORT_DFT_I9XX,
3543 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3544
3545 if (pipe == PIPE_A)
3546 tmp |= PIPE_A_SCRAMBLE_RESET;
3547 else
3548 tmp |= PIPE_B_SCRAMBLE_RESET;
3549
3550 I915_WRITE(PORT_DFT2_G4X, tmp);
3551 }
3552
4b79ebf7
DV		 3553 return 0;
3554}
3555
8d2f24ca
DV		 3556static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3557 enum pipe pipe)
3558{
3559 struct drm_i915_private *dev_priv = dev->dev_private;
3560 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3561
eb736679
VS		 3562 switch (pipe) {
3563 case PIPE_A:
8d2f24ca 3564 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3565 break;
3566 case PIPE_B:
8d2f24ca 3567 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3568 break;
3569 case PIPE_C:
3570 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3571 break;
3572 default:
3573 return;
3574 }
8d2f24ca
DV		 3575 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3576 tmp &= ~DC_BALANCE_RESET_VLV;
3577 I915_WRITE(PORT_DFT2_G4X, tmp);
3578
3579}
3580
84093603
DV		 3581static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3582 enum pipe pipe)
3583{
3584 struct drm_i915_private *dev_priv = dev->dev_private;
3585 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3586
3587 if (pipe == PIPE_A)
3588 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3589 else
3590 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3591 I915_WRITE(PORT_DFT2_G4X, tmp);
3592
3593 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3594 I915_WRITE(PORT_DFT_I9XX,
3595 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3596 }
3597}
3598
46a19188 3599static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3600 uint32_t *val)
3601{
46a19188
DV		 3602 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3603 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3604
3605 switch (*source) {
5b3a856b
DV		 3606 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3607 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3608 break;
3609 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3610 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3611 break;
5b3a856b
DV		 3612 case INTEL_PIPE_CRC_SOURCE_PIPE:
3613 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3614 break;
3d099a05 3615 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3616 *val = 0;
3617 break;
3d099a05
DV		 3618 default:
3619 return -EINVAL;
5b3a856b
DV		 3620 }
3621
3622 return 0;
3623}
3624
fabf6e51
DV		 3625static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3626{
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *crtc =
3629 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3630 struct intel_crtc_state *pipe_config;
fabf6e51
DV		 3631
3632 drm_modeset_lock_all(dev);
f77076c9
ML		 3633 pipe_config = to_intel_crtc_state(crtc->base.state);
3634
fabf6e51
DV		 3635 /*
3636 * If we use the eDP transcoder we need to make sure that we don't
3637 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3638 * relevant on hsw with pipe A when using the always-on power well
3639 * routing.
3640 */
f77076c9
ML		 3641 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3642 !pipe_config->pch_pfit.enabled) {
3643 bool active = pipe_config->base.active;
1b509259 3644
f77076c9 3645 if (active) {
1b509259 3646 intel_crtc_control(&crtc->base, false);
f77076c9
ML		 3647 pipe_config = to_intel_crtc_state(crtc->base.state);
3648 }
1b509259 3649
f77076c9 3650 pipe_config->pch_pfit.force_thru = true;
fabf6e51
DV		 3651
3652 intel_display_power_get(dev_priv,
3653 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3654
1b509259
ML		 3655 if (active)
3656 intel_crtc_control(&crtc->base, true);
fabf6e51
DV		 3657 }
3658 drm_modeset_unlock_all(dev);
3659}
3660
3661static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3662{
3663 struct drm_i915_private *dev_priv = dev->dev_private;
3664 struct intel_crtc *crtc =
3665 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3666 struct intel_crtc_state *pipe_config;
fabf6e51
DV		 3667
3668 drm_modeset_lock_all(dev);
3669 /*
3670 * If we use the eDP transcoder we need to make sure that we don't
3671 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3672 * relevant on hsw with pipe A when using the always-on power well
3673 * routing.
3674 */
f77076c9
ML		 3675 pipe_config = to_intel_crtc_state(crtc->base.state);
3676 if (pipe_config->pch_pfit.force_thru) {
3677 bool active = pipe_config->base.active;
fabf6e51 3678
f77076c9 3679 if (active) {
1b509259 3680 intel_crtc_control(&crtc->base, false);
f77076c9
ML		 3681 pipe_config = to_intel_crtc_state(crtc->base.state);
3682 }
fabf6e51 3683
f77076c9 3684 pipe_config->pch_pfit.force_thru = false;
fabf6e51
DV		 3685
3686 intel_display_power_put(dev_priv,
3687 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
1b509259
ML		 3688
3689 if (active)
3690 intel_crtc_control(&crtc->base, true);
fabf6e51
DV		 3691 }
3692 drm_modeset_unlock_all(dev);
3693}
3694
3695static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3696 enum pipe pipe,
3697 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3698 uint32_t *val)
3699{
46a19188
DV		 3700 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3701 *source = INTEL_PIPE_CRC_SOURCE_PF;
3702
3703 switch (*source) {
5b3a856b
DV		 3704 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3705 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3706 break;
3707 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3708 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3709 break;
3710 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3711 if (IS_HASWELL(dev) && pipe == PIPE_A)
3712 hsw_trans_edp_pipe_A_crc_wa(dev);
3713
5b3a856b
DV		 3714 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3715 break;
3d099a05 3716 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3717 *val = 0;
3718 break;
3d099a05
DV		 3719 default:
3720 return -EINVAL;
5b3a856b
DV		 3721 }
3722
3723 return 0;
3724}
3725
926321d5
DV		 3726static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3727 enum intel_pipe_crc_source source)
3728{
3729 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3730 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3731 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3732 pipe));
432f3342 3733 u32 val = 0; /* shut up gcc */
5b3a856b 3734 int ret;
926321d5 3735
cc3da175
DL		 3736 if (pipe_crc->source == source)
3737 return 0;
3738
ae676fcd
DL		 3739 /* forbid changing the source without going back to 'none' */
3740 if (pipe_crc->source && source)
3741 return -EINVAL;
3742
9d8b0588
DV		 3743 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3744 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3745 return -EIO;
3746 }
3747
52f843f6 3748 if (IS_GEN2(dev))
46a19188 3749 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3750 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3751 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3752 else if (IS_VALLEYVIEW(dev))
fabf6e51 3753 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3754 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3755 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3756 else
fabf6e51 3757 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3758
3759 if (ret != 0)
3760 return ret;
3761
4b584369
DL		 3762 /* none -> real source transition */
3763 if (source) {
4252fbc3
VS		 3764 struct intel_pipe_crc_entry *entries;
3765
7cd6ccff
DL		 3766 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3767 pipe_name(pipe), pipe_crc_source_name(source));
3768
3cf54b34
VS		 3769 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3770 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3771 GFP_KERNEL);
3772 if (!entries)
e5f75aca
DL		 3773 return -ENOMEM;
3774
8c740dce
PZ		 3775 /*
3776 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3777 * enabled and disabled dynamically based on package C states,
3778 * user space can't make reliable use of the CRCs, so let's just
3779 * completely disable it.
3780 */
3781 hsw_disable_ips(crtc);
3782
d538bbdf 3783 spin_lock_irq(&pipe_crc->lock);
64387b61 3784 kfree(pipe_crc->entries);
4252fbc3 3785 pipe_crc->entries = entries;
d538bbdf
DL		 3786 pipe_crc->head = 0;
3787 pipe_crc->tail = 0;
3788 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3789 }
3790
cc3da175 3791 pipe_crc->source = source;
926321d5 3792
926321d5
DV		 3793 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3794 POSTING_READ(PIPE_CRC_CTL(pipe));
3795
e5f75aca
DL		 3796 /* real source -> none transition */
3797 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3798 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3799 struct intel_crtc *crtc =
3800 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3801
7cd6ccff
DL		 3802 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3803 pipe_name(pipe));
3804
a33d7105 3805 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 3806 if (crtc->base.state->active)
a33d7105
DV		 3807 intel_wait_for_vblank(dev, pipe);
3808 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3809
d538bbdf
DL		 3810 spin_lock_irq(&pipe_crc->lock);
3811 entries = pipe_crc->entries;
e5f75aca 3812 pipe_crc->entries = NULL;
9ad6d99f
VS		 3813 pipe_crc->head = 0;
3814 pipe_crc->tail = 0;
d538bbdf
DL		 3815 spin_unlock_irq(&pipe_crc->lock);
3816
3817 kfree(entries);
84093603
DV		 3818
3819 if (IS_G4X(dev))
3820 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3821 else if (IS_VALLEYVIEW(dev))
3822 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3823 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3824 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3825
3826 hsw_enable_ips(crtc);
e5f75aca
DL		 3827 }
3828
926321d5
DV		 3829 return 0;
3830}
3831
3832/*
3833 * Parse pipe CRC command strings:
b94dec87
DL		 3834 * command: wsp* object wsp+ name wsp+ source wsp*
3835 * object: 'pipe'
3836 * name: (A | B | C)
926321d5
DV		 3837 * source: (none | plane1 | plane2 | pf)
3838 * wsp: (#0x20 | #0x9 | #0xA)+
3839 *
3840 * eg.:
b94dec87
DL		 3841 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3842 * "pipe A none" -> Stop CRC
926321d5 3843 */
bd9db02f 3844static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3845{
3846 int n_words = 0;
3847
3848 while (*buf) {
3849 char *end;
3850
3851 /* skip leading white space */
3852 buf = skip_spaces(buf);
3853 if (!*buf)
3854 break; /* end of buffer */
3855
3856 /* find end of word */
3857 for (end = buf; *end && !isspace(*end); end++)
3858 ;
3859
3860 if (n_words == max_words) {
3861 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3862 max_words);
3863 return -EINVAL; /* ran out of words[] before bytes */
3864 }
3865
3866 if (*end)
3867 *end++ = '\0';
3868 words[n_words++] = buf;
3869 buf = end;
3870 }
3871
3872 return n_words;
3873}
3874
b94dec87
DL		 3875enum intel_pipe_crc_object {
3876 PIPE_CRC_OBJECT_PIPE,
3877};
3878
e8dfcf78 3879static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3880 "pipe",
3881};
3882
3883static int
bd9db02f 3884display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3885{
3886 int i;
3887
3888 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3889 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3890 *o = i;
b94dec87
DL		 3891 return 0;
3892 }
3893
3894 return -EINVAL;
3895}
3896
bd9db02f 3897static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3898{
3899 const char name = buf[0];
3900
3901 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3902 return -EINVAL;
3903
3904 *pipe = name - 'A';
3905
3906 return 0;
3907}
3908
3909static int
bd9db02f 3910display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3911{
3912 int i;
3913
3914 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3915 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3916 *s = i;
926321d5
DV		 3917 return 0;
3918 }
3919
3920 return -EINVAL;
3921}
3922
bd9db02f 3923static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3924{
b94dec87 3925#define N_WORDS 3
926321d5 3926 int n_words;
b94dec87 3927 char *words[N_WORDS];
926321d5 3928 enum pipe pipe;
b94dec87 3929 enum intel_pipe_crc_object object;
926321d5
DV		 3930 enum intel_pipe_crc_source source;
3931
bd9db02f 3932 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3933 if (n_words != N_WORDS) {
3934 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3935 N_WORDS);
3936 return -EINVAL;
3937 }
3938
bd9db02f 3939 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3940 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3941 return -EINVAL;
3942 }
3943
bd9db02f 3944 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3945 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3946 return -EINVAL;
3947 }
3948
bd9db02f 3949 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3950 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3951 return -EINVAL;
3952 }
3953
3954 return pipe_crc_set_source(dev, pipe, source);
3955}
3956
bd9db02f
DL		 3957static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3958 size_t len, loff_t *offp)
926321d5
DV		 3959{
3960 struct seq_file *m = file->private_data;
3961 struct drm_device *dev = m->private;
3962 char *tmpbuf;
3963 int ret;
3964
3965 if (len == 0)
3966 return 0;
3967
3968 if (len > PAGE_SIZE - 1) {
3969 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3970 PAGE_SIZE);
3971 return -E2BIG;
3972 }
3973
3974 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3975 if (!tmpbuf)
3976 return -ENOMEM;
3977
3978 if (copy_from_user(tmpbuf, ubuf, len)) {
3979 ret = -EFAULT;
3980 goto out;
3981 }
3982 tmpbuf[len] = '\0';
3983
bd9db02f 3984 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3985
3986out:
3987 kfree(tmpbuf);
3988 if (ret < 0)
3989 return ret;
3990
3991 *offp += len;
3992 return len;
3993}
3994
bd9db02f 3995static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3996 .owner = THIS_MODULE,
bd9db02f 3997 .open = display_crc_ctl_open,
926321d5
DV		 3998 .read = seq_read,
3999 .llseek = seq_lseek,
4000 .release = single_release,
bd9db02f 4001 .write = display_crc_ctl_write
926321d5
DV		 4002};
4003
eb3394fa
TP		 4004static ssize_t i915_displayport_test_active_write(struct file *file,
4005 const char __user *ubuf,
4006 size_t len, loff_t *offp)
4007{
4008 char *input_buffer;
4009 int status = 0;
4010 struct seq_file *m;
4011 struct drm_device *dev;
4012 struct drm_connector *connector;
4013 struct list_head *connector_list;
4014 struct intel_dp *intel_dp;
4015 int val = 0;
4016
4017 m = file->private_data;
4018 if (!m) {
4019 status = -ENODEV;
4020 return status;
4021 }
4022 dev = m->private;
4023
4024 if (!dev) {
4025 status = -ENODEV;
4026 return status;
4027 }
4028 connector_list = &dev->mode_config.connector_list;
4029
4030 if (len == 0)
4031 return 0;
4032
4033 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4034 if (!input_buffer)
4035 return -ENOMEM;
4036
4037 if (copy_from_user(input_buffer, ubuf, len)) {
4038 status = -EFAULT;
4039 goto out;
4040 }
4041
4042 input_buffer[len] = '\0';
4043 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4044
4045 list_for_each_entry(connector, connector_list, head) {
4046
4047 if (connector->connector_type !=
4048 DRM_MODE_CONNECTOR_DisplayPort)
4049 continue;
4050
4051 if (connector->connector_type ==
4052 DRM_MODE_CONNECTOR_DisplayPort &&
4053 connector->status == connector_status_connected &&
4054 connector->encoder != NULL) {
4055 intel_dp = enc_to_intel_dp(connector->encoder);
4056 status = kstrtoint(input_buffer, 10, &val);
4057 if (status < 0)
4058 goto out;
4059 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4060 /* To prevent erroneous activation of the compliance
4061 * testing code, only accept an actual value of 1 here
4062 */
4063 if (val == 1)
4064 intel_dp->compliance_test_active = 1;
4065 else
4066 intel_dp->compliance_test_active = 0;
4067 }
4068 }
4069out:
4070 kfree(input_buffer);
4071 if (status < 0)
4072 return status;
4073
4074 *offp += len;
4075 return len;
4076}
4077
4078static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4079{
4080 struct drm_device *dev = m->private;
4081 struct drm_connector *connector;
4082 struct list_head *connector_list = &dev->mode_config.connector_list;
4083 struct intel_dp *intel_dp;
4084
4085 if (!dev)
4086 return -ENODEV;
4087
4088 list_for_each_entry(connector, connector_list, head) {
4089
4090 if (connector->connector_type !=
4091 DRM_MODE_CONNECTOR_DisplayPort)
4092 continue;
4093
4094 if (connector->status == connector_status_connected &&
4095 connector->encoder != NULL) {
4096 intel_dp = enc_to_intel_dp(connector->encoder);
4097 if (intel_dp->compliance_test_active)
4098 seq_puts(m, "1");
4099 else
4100 seq_puts(m, "0");
4101 } else
4102 seq_puts(m, "0");
4103 }
4104
4105 return 0;
4106}
4107
4108static int i915_displayport_test_active_open(struct inode *inode,
4109 struct file *file)
4110{
4111 struct drm_device *dev = inode->i_private;
4112
4113 return single_open(file, i915_displayport_test_active_show, dev);
4114}
4115
4116static const struct file_operations i915_displayport_test_active_fops = {
4117 .owner = THIS_MODULE,
4118 .open = i915_displayport_test_active_open,
4119 .read = seq_read,
4120 .llseek = seq_lseek,
4121 .release = single_release,
4122 .write = i915_displayport_test_active_write
4123};
4124
4125static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4126{
4127 struct drm_device *dev = m->private;
4128 struct drm_connector *connector;
4129 struct list_head *connector_list = &dev->mode_config.connector_list;
4130 struct intel_dp *intel_dp;
4131
4132 if (!dev)
4133 return -ENODEV;
4134
4135 list_for_each_entry(connector, connector_list, head) {
4136
4137 if (connector->connector_type !=
4138 DRM_MODE_CONNECTOR_DisplayPort)
4139 continue;
4140
4141 if (connector->status == connector_status_connected &&
4142 connector->encoder != NULL) {
4143 intel_dp = enc_to_intel_dp(connector->encoder);
4144 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4145 } else
4146 seq_puts(m, "0");
4147 }
4148
4149 return 0;
4150}
4151static int i915_displayport_test_data_open(struct inode *inode,
4152 struct file *file)
4153{
4154 struct drm_device *dev = inode->i_private;
4155
4156 return single_open(file, i915_displayport_test_data_show, dev);
4157}
4158
4159static const struct file_operations i915_displayport_test_data_fops = {
4160 .owner = THIS_MODULE,
4161 .open = i915_displayport_test_data_open,
4162 .read = seq_read,
4163 .llseek = seq_lseek,
4164 .release = single_release
4165};
4166
4167static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4168{
4169 struct drm_device *dev = m->private;
4170 struct drm_connector *connector;
4171 struct list_head *connector_list = &dev->mode_config.connector_list;
4172 struct intel_dp *intel_dp;
4173
4174 if (!dev)
4175 return -ENODEV;
4176
4177 list_for_each_entry(connector, connector_list, head) {
4178
4179 if (connector->connector_type !=
4180 DRM_MODE_CONNECTOR_DisplayPort)
4181 continue;
4182
4183 if (connector->status == connector_status_connected &&
4184 connector->encoder != NULL) {
4185 intel_dp = enc_to_intel_dp(connector->encoder);
4186 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4187 } else
4188 seq_puts(m, "0");
4189 }
4190
4191 return 0;
4192}
4193
4194static int i915_displayport_test_type_open(struct inode *inode,
4195 struct file *file)
4196{
4197 struct drm_device *dev = inode->i_private;
4198
4199 return single_open(file, i915_displayport_test_type_show, dev);
4200}
4201
4202static const struct file_operations i915_displayport_test_type_fops = {
4203 .owner = THIS_MODULE,
4204 .open = i915_displayport_test_type_open,
4205 .read = seq_read,
4206 .llseek = seq_lseek,
4207 .release = single_release
4208};
4209
97e94b22 4210static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4211{
4212 struct drm_device *dev = m->private;
546c81fd 4213 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4214 int level;
4215
4216 drm_modeset_lock_all(dev);
4217
4218 for (level = 0; level < num_levels; level++) {
4219 unsigned int latency = wm[level];
4220
97e94b22
DL		 4221 /*
4222 * - WM1+ latency values in 0.5us units
4223 * - latencies are in us on gen9
4224 */
4225 if (INTEL_INFO(dev)->gen >= 9)
4226 latency *= 10;
4227 else if (level > 0)
369a1342
VS		 4228 latency *= 5;
4229
4230 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4231 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4232 }
4233
4234 drm_modeset_unlock_all(dev);
4235}
4236
4237static int pri_wm_latency_show(struct seq_file *m, void *data)
4238{
4239 struct drm_device *dev = m->private;
97e94b22
DL		 4240 struct drm_i915_private *dev_priv = dev->dev_private;
4241 const uint16_t *latencies;
4242
4243 if (INTEL_INFO(dev)->gen >= 9)
4244 latencies = dev_priv->wm.skl_latency;
4245 else
4246 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4247
97e94b22 4248 wm_latency_show(m, latencies);
369a1342
VS		 4249
4250 return 0;
4251}
4252
4253static int spr_wm_latency_show(struct seq_file *m, void *data)
4254{
4255 struct drm_device *dev = m->private;
97e94b22
DL		 4256 struct drm_i915_private *dev_priv = dev->dev_private;
4257 const uint16_t *latencies;
4258
4259 if (INTEL_INFO(dev)->gen >= 9)
4260 latencies = dev_priv->wm.skl_latency;
4261 else
4262 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4263
97e94b22 4264 wm_latency_show(m, latencies);
369a1342
VS		 4265
4266 return 0;
4267}
4268
4269static int cur_wm_latency_show(struct seq_file *m, void *data)
4270{
4271 struct drm_device *dev = m->private;
97e94b22
DL		 4272 struct drm_i915_private *dev_priv = dev->dev_private;
4273 const uint16_t *latencies;
4274
4275 if (INTEL_INFO(dev)->gen >= 9)
4276 latencies = dev_priv->wm.skl_latency;
4277 else
4278 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4279
97e94b22 4280 wm_latency_show(m, latencies);
369a1342
VS		 4281
4282 return 0;
4283}
4284
4285static int pri_wm_latency_open(struct inode *inode, struct file *file)
4286{
4287 struct drm_device *dev = inode->i_private;
4288
9ad0257c 4289 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4290 return -ENODEV;
4291
4292 return single_open(file, pri_wm_latency_show, dev);
4293}
4294
4295static int spr_wm_latency_open(struct inode *inode, struct file *file)
4296{
4297 struct drm_device *dev = inode->i_private;
4298
9ad0257c 4299 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4300 return -ENODEV;
4301
4302 return single_open(file, spr_wm_latency_show, dev);
4303}
4304
4305static int cur_wm_latency_open(struct inode *inode, struct file *file)
4306{
4307 struct drm_device *dev = inode->i_private;
4308
9ad0257c 4309 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4310 return -ENODEV;
4311
4312 return single_open(file, cur_wm_latency_show, dev);
4313}
4314
4315static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4316 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4317{
4318 struct seq_file *m = file->private_data;
4319 struct drm_device *dev = m->private;
97e94b22 4320 uint16_t new[8] = { 0 };
546c81fd 4321 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4322 int level;
4323 int ret;
4324 char tmp[32];
4325
4326 if (len >= sizeof(tmp))
4327 return -EINVAL;
4328
4329 if (copy_from_user(tmp, ubuf, len))
4330 return -EFAULT;
4331
4332 tmp[len] = '\0';
4333
97e94b22
DL		 4334 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4335 &new[0], &new[1], &new[2], &new[3],
4336 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4337 if (ret != num_levels)
4338 return -EINVAL;
4339
4340 drm_modeset_lock_all(dev);
4341
4342 for (level = 0; level < num_levels; level++)
4343 wm[level] = new[level];
4344
4345 drm_modeset_unlock_all(dev);
4346
4347 return len;
4348}
4349
4350
4351static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4352 size_t len, loff_t *offp)
4353{
4354 struct seq_file *m = file->private_data;
4355 struct drm_device *dev = m->private;
97e94b22
DL		 4356 struct drm_i915_private *dev_priv = dev->dev_private;
4357 uint16_t *latencies;
369a1342 4358
97e94b22
DL		 4359 if (INTEL_INFO(dev)->gen >= 9)
4360 latencies = dev_priv->wm.skl_latency;
4361 else
4362 latencies = to_i915(dev)->wm.pri_latency;
4363
4364 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4365}
4366
4367static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4368 size_t len, loff_t *offp)
4369{
4370 struct seq_file *m = file->private_data;
4371 struct drm_device *dev = m->private;
97e94b22
DL		 4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373 uint16_t *latencies;
369a1342 4374
97e94b22
DL		 4375 if (INTEL_INFO(dev)->gen >= 9)
4376 latencies = dev_priv->wm.skl_latency;
4377 else
4378 latencies = to_i915(dev)->wm.spr_latency;
4379
4380 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4381}
4382
4383static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4384 size_t len, loff_t *offp)
4385{
4386 struct seq_file *m = file->private_data;
4387 struct drm_device *dev = m->private;
97e94b22
DL		 4388 struct drm_i915_private *dev_priv = dev->dev_private;
4389 uint16_t *latencies;
4390
4391 if (INTEL_INFO(dev)->gen >= 9)
4392 latencies = dev_priv->wm.skl_latency;
4393 else
4394 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4395
97e94b22 4396 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4397}
4398
4399static const struct file_operations i915_pri_wm_latency_fops = {
4400 .owner = THIS_MODULE,
4401 .open = pri_wm_latency_open,
4402 .read = seq_read,
4403 .llseek = seq_lseek,
4404 .release = single_release,
4405 .write = pri_wm_latency_write
4406};
4407
4408static const struct file_operations i915_spr_wm_latency_fops = {
4409 .owner = THIS_MODULE,
4410 .open = spr_wm_latency_open,
4411 .read = seq_read,
4412 .llseek = seq_lseek,
4413 .release = single_release,
4414 .write = spr_wm_latency_write
4415};
4416
4417static const struct file_operations i915_cur_wm_latency_fops = {
4418 .owner = THIS_MODULE,
4419 .open = cur_wm_latency_open,
4420 .read = seq_read,
4421 .llseek = seq_lseek,
4422 .release = single_release,
4423 .write = cur_wm_latency_write
4424};
4425
647416f9
KC		 4426static int
4427i915_wedged_get(void *data, u64 *val)
f3cd474b 4428{
647416f9 4429 struct drm_device *dev = data;
e277a1f8 4430 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4431
647416f9 4432 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4433
647416f9 4434 return 0;
f3cd474b
CW		 4435}
4436
647416f9
KC		 4437static int
4438i915_wedged_set(void *data, u64 val)
f3cd474b 4439{
647416f9 4440 struct drm_device *dev = data;
d46c0517
ID		 4441 struct drm_i915_private *dev_priv = dev->dev_private;
4442
b8d24a06
MK		 4443 /*
4444 * There is no safeguard against this debugfs entry colliding
4445 * with the hangcheck calling same i915_handle_error() in
4446 * parallel, causing an explosion. For now we assume that the
4447 * test harness is responsible enough not to inject gpu hangs
4448 * while it is writing to 'i915_wedged'
4449 */
4450
4451 if (i915_reset_in_progress(&dev_priv->gpu_error))
4452 return -EAGAIN;
4453
d46c0517 4454 intel_runtime_pm_get(dev_priv);
f3cd474b 4455
58174462
MK		 4456 i915_handle_error(dev, val,
4457 "Manually setting wedged to %llu", val);
d46c0517
ID		 4458
4459 intel_runtime_pm_put(dev_priv);
4460
647416f9 4461 return 0;
f3cd474b
CW		 4462}
4463
647416f9
KC		 4464DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4465 i915_wedged_get, i915_wedged_set,
3a3b4f98 4466 "%llu\n");
f3cd474b 4467
647416f9
KC		 4468static int
4469i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4470{
647416f9 4471 struct drm_device *dev = data;
e277a1f8 4472 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4473
647416f9 4474 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4475
647416f9 4476 return 0;
e5eb3d63
DV		 4477}
4478
647416f9
KC		 4479static int
4480i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4481{
647416f9 4482 struct drm_device *dev = data;
e5eb3d63 4483 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4484 int ret;
e5eb3d63 4485
647416f9 4486 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4487
22bcfc6a
DV		 4488 ret = mutex_lock_interruptible(&dev->struct_mutex);
4489 if (ret)
4490 return ret;
4491
99584db3 4492 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4493 mutex_unlock(&dev->struct_mutex);
4494
647416f9 4495 return 0;
e5eb3d63
DV		 4496}
4497
647416f9
KC		 4498DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4499 i915_ring_stop_get, i915_ring_stop_set,
4500 "0x%08llx\n");
d5442303 4501
094f9a54
CW		 4502static int
4503i915_ring_missed_irq_get(void *data, u64 *val)
4504{
4505 struct drm_device *dev = data;
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4507
4508 *val = dev_priv->gpu_error.missed_irq_rings;
4509 return 0;
4510}
4511
4512static int
4513i915_ring_missed_irq_set(void *data, u64 val)
4514{
4515 struct drm_device *dev = data;
4516 struct drm_i915_private *dev_priv = dev->dev_private;
4517 int ret;
4518
4519 /* Lock against concurrent debugfs callers */
4520 ret = mutex_lock_interruptible(&dev->struct_mutex);
4521 if (ret)
4522 return ret;
4523 dev_priv->gpu_error.missed_irq_rings = val;
4524 mutex_unlock(&dev->struct_mutex);
4525
4526 return 0;
4527}
4528
4529DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4530 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4531 "0x%08llx\n");
4532
4533static int
4534i915_ring_test_irq_get(void *data, u64 *val)
4535{
4536 struct drm_device *dev = data;
4537 struct drm_i915_private *dev_priv = dev->dev_private;
4538
4539 *val = dev_priv->gpu_error.test_irq_rings;
4540
4541 return 0;
4542}
4543
4544static int
4545i915_ring_test_irq_set(void *data, u64 val)
4546{
4547 struct drm_device *dev = data;
4548 struct drm_i915_private *dev_priv = dev->dev_private;
4549 int ret;
4550
4551 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4552
4553 /* Lock against concurrent debugfs callers */
4554 ret = mutex_lock_interruptible(&dev->struct_mutex);
4555 if (ret)
4556 return ret;
4557
4558 dev_priv->gpu_error.test_irq_rings = val;
4559 mutex_unlock(&dev->struct_mutex);
4560
4561 return 0;
4562}
4563
4564DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4565 i915_ring_test_irq_get, i915_ring_test_irq_set,
4566 "0x%08llx\n");
4567
dd624afd
CW		 4568#define DROP_UNBOUND 0x1
4569#define DROP_BOUND 0x2
4570#define DROP_RETIRE 0x4
4571#define DROP_ACTIVE 0x8
4572#define DROP_ALL (DROP_UNBOUND | \
4573 DROP_BOUND | \
4574 DROP_RETIRE | \
4575 DROP_ACTIVE)
647416f9
KC		 4576static int
4577i915_drop_caches_get(void *data, u64 *val)
dd624afd 4578{
647416f9 4579 *val = DROP_ALL;
dd624afd 4580
647416f9 4581 return 0;
dd624afd
CW		 4582}
4583
647416f9
KC		 4584static int
4585i915_drop_caches_set(void *data, u64 val)
dd624afd 4586{
647416f9 4587 struct drm_device *dev = data;
dd624afd 4588 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4589 int ret;
dd624afd 4590
2f9fe5ff 4591 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4592
4593 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4594 * on ioctls on -EAGAIN. */
4595 ret = mutex_lock_interruptible(&dev->struct_mutex);
4596 if (ret)
4597 return ret;
4598
4599 if (val & DROP_ACTIVE) {
4600 ret = i915_gpu_idle(dev);
4601 if (ret)
4602 goto unlock;
4603 }
4604
4605 if (val & (DROP_RETIRE | DROP_ACTIVE))
4606 i915_gem_retire_requests(dev);
4607
21ab4e74
CW		 4608 if (val & DROP_BOUND)
4609 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4610
21ab4e74
CW		 4611 if (val & DROP_UNBOUND)
4612 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4613
4614unlock:
4615 mutex_unlock(&dev->struct_mutex);
4616
647416f9 4617 return ret;
dd624afd
CW		 4618}
4619
647416f9
KC		 4620DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4621 i915_drop_caches_get, i915_drop_caches_set,
4622 "0x%08llx\n");
dd624afd 4623
647416f9
KC		 4624static int
4625i915_max_freq_get(void *data, u64 *val)
358733e9 4626{
647416f9 4627 struct drm_device *dev = data;
e277a1f8 4628 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4629 int ret;
004777cb 4630
daa3afb2 4631 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4632 return -ENODEV;
4633
5c9669ce
TR		 4634 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4635
4fc688ce 4636 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4637 if (ret)
4638 return ret;
358733e9 4639
7c59a9c1 4640 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4641 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4642
647416f9 4643 return 0;
358733e9
JB		 4644}
4645
647416f9
KC		 4646static int
4647i915_max_freq_set(void *data, u64 val)
358733e9 4648{
647416f9 4649 struct drm_device *dev = data;
358733e9 4650 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4651 u32 hw_max, hw_min;
647416f9 4652 int ret;
004777cb 4653
daa3afb2 4654 if (INTEL_INFO(dev)->gen < 6)
004777cb 4655 return -ENODEV;
358733e9 4656
5c9669ce
TR		 4657 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4658
647416f9 4659 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4660
4fc688ce 4661 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4662 if (ret)
4663 return ret;
4664
358733e9
JB		 4665 /*
4666 * Turbo will still be enabled, but won't go above the set value.
4667 */
bc4d91f6 4668 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4669
bc4d91f6
AG		 4670 hw_max = dev_priv->rps.max_freq;
4671 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4672
b39fb297 4673 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4674 mutex_unlock(&dev_priv->rps.hw_lock);
4675 return -EINVAL;
0a073b84
JB		 4676 }
4677
b39fb297 4678 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4679
ffe02b40 4680 intel_set_rps(dev, val);
dd0a1aa1 4681
4fc688ce 4682 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4683
647416f9 4684 return 0;
358733e9
JB		 4685}
4686
647416f9
KC		 4687DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4688 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4689 "%llu\n");
358733e9 4690
647416f9
KC		 4691static int
4692i915_min_freq_get(void *data, u64 *val)
1523c310 4693{
647416f9 4694 struct drm_device *dev = data;
e277a1f8 4695 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4696 int ret;
004777cb 4697
daa3afb2 4698 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4699 return -ENODEV;
4700
5c9669ce
TR		 4701 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4702
4fc688ce 4703 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4704 if (ret)
4705 return ret;
1523c310 4706
7c59a9c1 4707 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4708 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4709
647416f9 4710 return 0;
1523c310
JB		 4711}
4712
647416f9
KC		 4713static int
4714i915_min_freq_set(void *data, u64 val)
1523c310 4715{
647416f9 4716 struct drm_device *dev = data;
1523c310 4717 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4718 u32 hw_max, hw_min;
647416f9 4719 int ret;
004777cb 4720
daa3afb2 4721 if (INTEL_INFO(dev)->gen < 6)
004777cb 4722 return -ENODEV;
1523c310 4723
5c9669ce
TR		 4724 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4725
647416f9 4726 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4727
4fc688ce 4728 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4729 if (ret)
4730 return ret;
4731
1523c310
JB		 4732 /*
4733 * Turbo will still be enabled, but won't go below the set value.
4734 */
bc4d91f6 4735 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4736
bc4d91f6
AG		 4737 hw_max = dev_priv->rps.max_freq;
4738 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4739
b39fb297 4740 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4741 mutex_unlock(&dev_priv->rps.hw_lock);
4742 return -EINVAL;
0a073b84 4743 }
dd0a1aa1 4744
b39fb297 4745 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4746
ffe02b40 4747 intel_set_rps(dev, val);
dd0a1aa1 4748
4fc688ce 4749 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4750
647416f9 4751 return 0;
1523c310
JB		 4752}
4753
647416f9
KC		 4754DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4755 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4756 "%llu\n");
1523c310 4757
647416f9
KC		 4758static int
4759i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4760{
647416f9 4761 struct drm_device *dev = data;
e277a1f8 4762 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4763 u32 snpcr;
647416f9 4764 int ret;
07b7ddd9 4765
004777cb
DV		 4766 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4767 return -ENODEV;
4768
22bcfc6a
DV		 4769 ret = mutex_lock_interruptible(&dev->struct_mutex);
4770 if (ret)
4771 return ret;
c8c8fb33 4772 intel_runtime_pm_get(dev_priv);
22bcfc6a 4773
07b7ddd9 4774 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4775
4776 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4777 mutex_unlock(&dev_priv->dev->struct_mutex);
4778
647416f9 4779 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4780
647416f9 4781 return 0;
07b7ddd9
JB		 4782}
4783
647416f9
KC		 4784static int
4785i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4786{
647416f9 4787 struct drm_device *dev = data;
07b7ddd9 4788 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4789 u32 snpcr;
07b7ddd9 4790
004777cb
DV		 4791 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4792 return -ENODEV;
4793
647416f9 4794 if (val > 3)
07b7ddd9
JB		 4795 return -EINVAL;
4796
c8c8fb33 4797 intel_runtime_pm_get(dev_priv);
647416f9 4798 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4799
4800 /* Update the cache sharing policy here as well */
4801 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4802 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4803 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4804 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4805
c8c8fb33 4806 intel_runtime_pm_put(dev_priv);
647416f9 4807 return 0;
07b7ddd9
JB		 4808}
4809
647416f9
KC		 4810DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4811 i915_cache_sharing_get, i915_cache_sharing_set,
4812 "%llu\n");
07b7ddd9 4813
5d39525a
JM		 4814struct sseu_dev_status {
4815 unsigned int slice_total;
4816 unsigned int subslice_total;
4817 unsigned int subslice_per_slice;
4818 unsigned int eu_total;
4819 unsigned int eu_per_subslice;
4820};
4821
4822static void cherryview_sseu_device_status(struct drm_device *dev,
4823 struct sseu_dev_status *stat)
4824{
4825 struct drm_i915_private *dev_priv = dev->dev_private;
4826 const int ss_max = 2;
4827 int ss;
4828 u32 sig1[ss_max], sig2[ss_max];
4829
4830 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4831 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4832 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4833 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4834
4835 for (ss = 0; ss < ss_max; ss++) {
4836 unsigned int eu_cnt;
4837
4838 if (sig1[ss] & CHV_SS_PG_ENABLE)
4839 /* skip disabled subslice */
4840 continue;
4841
4842 stat->slice_total = 1;
4843 stat->subslice_per_slice++;
4844 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4845 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4846 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4847 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4848 stat->eu_total += eu_cnt;
4849 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4850 }
4851 stat->subslice_total = stat->subslice_per_slice;
4852}
4853
4854static void gen9_sseu_device_status(struct drm_device *dev,
4855 struct sseu_dev_status *stat)
4856{
4857 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 4858 int s_max = 3, ss_max = 4;
5d39525a
JM		 4859 int s, ss;
4860 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4861
1c046bc1
JM		 4862 /* BXT has a single slice and at most 3 subslices. */
4863 if (IS_BROXTON(dev)) {
4864 s_max = 1;
4865 ss_max = 3;
4866 }
4867
4868 for (s = 0; s < s_max; s++) {
4869 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4870 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4871 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4872 }
4873
5d39525a
JM		 4874 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4875 GEN9_PGCTL_SSA_EU19_ACK |
4876 GEN9_PGCTL_SSA_EU210_ACK |
4877 GEN9_PGCTL_SSA_EU311_ACK;
4878 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4879 GEN9_PGCTL_SSB_EU19_ACK |
4880 GEN9_PGCTL_SSB_EU210_ACK |
4881 GEN9_PGCTL_SSB_EU311_ACK;
4882
4883 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 4884 unsigned int ss_cnt = 0;
4885
5d39525a
JM		 4886 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4887 /* skip disabled slice */
4888 continue;
4889
4890 stat->slice_total++;
1c046bc1
JM		 4891
4892 if (IS_SKYLAKE(dev))
4893 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4894
5d39525a
JM		 4895 for (ss = 0; ss < ss_max; ss++) {
4896 unsigned int eu_cnt;
4897
1c046bc1
JM		 4898 if (IS_BROXTON(dev) &&
4899 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4900 /* skip disabled subslice */
4901 continue;
4902
4903 if (IS_BROXTON(dev))
4904 ss_cnt++;
4905
5d39525a
JM		 4906 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4907 eu_mask[ss%2]);
4908 stat->eu_total += eu_cnt;
4909 stat->eu_per_subslice = max(stat->eu_per_subslice,
4910 eu_cnt);
4911 }
1c046bc1
JM		 4912
4913 stat->subslice_total += ss_cnt;
4914 stat->subslice_per_slice = max(stat->subslice_per_slice,
4915 ss_cnt);
5d39525a
JM		 4916 }
4917}
4918
3873218f
JM		 4919static int i915_sseu_status(struct seq_file *m, void *unused)
4920{
4921 struct drm_info_node *node = (struct drm_info_node *) m->private;
4922 struct drm_device *dev = node->minor->dev;
5d39525a 4923 struct sseu_dev_status stat;
3873218f 4924
5575f03a 4925 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
3873218f
JM		 4926 return -ENODEV;
4927
4928 seq_puts(m, "SSEU Device Info\n");
4929 seq_printf(m, " Available Slice Total: %u\n",
4930 INTEL_INFO(dev)->slice_total);
4931 seq_printf(m, " Available Subslice Total: %u\n",
4932 INTEL_INFO(dev)->subslice_total);
4933 seq_printf(m, " Available Subslice Per Slice: %u\n",
4934 INTEL_INFO(dev)->subslice_per_slice);
4935 seq_printf(m, " Available EU Total: %u\n",
4936 INTEL_INFO(dev)->eu_total);
4937 seq_printf(m, " Available EU Per Subslice: %u\n",
4938 INTEL_INFO(dev)->eu_per_subslice);
4939 seq_printf(m, " Has Slice Power Gating: %s\n",
4940 yesno(INTEL_INFO(dev)->has_slice_pg));
4941 seq_printf(m, " Has Subslice Power Gating: %s\n",
4942 yesno(INTEL_INFO(dev)->has_subslice_pg));
4943 seq_printf(m, " Has EU Power Gating: %s\n",
4944 yesno(INTEL_INFO(dev)->has_eu_pg));
4945
7f992aba 4946 seq_puts(m, "SSEU Device Status\n");
5d39525a 4947 memset(&stat, 0, sizeof(stat));
5575f03a 4948 if (IS_CHERRYVIEW(dev)) {
5d39525a 4949 cherryview_sseu_device_status(dev, &stat);
1c046bc1 4950 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 4951 gen9_sseu_device_status(dev, &stat);
7f992aba 4952 }
5d39525a
JM		 4953 seq_printf(m, " Enabled Slice Total: %u\n",
4954 stat.slice_total);
4955 seq_printf(m, " Enabled Subslice Total: %u\n",
4956 stat.subslice_total);
4957 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
4958 stat.subslice_per_slice);
4959 seq_printf(m, " Enabled EU Total: %u\n",
4960 stat.eu_total);
4961 seq_printf(m, " Enabled EU Per Subslice: %u\n",
4962 stat.eu_per_subslice);
7f992aba 4963
3873218f
JM		 4964 return 0;
4965}
4966
6d794d42
BW		 4967static int i915_forcewake_open(struct inode *inode, struct file *file)
4968{
4969 struct drm_device *dev = inode->i_private;
4970 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4971
075edca4 4972 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4973 return 0;
4974
6daccb0b 4975 intel_runtime_pm_get(dev_priv);
59bad947 4976 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4977
4978 return 0;
4979}
4980
c43b5634 4981static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4982{
4983 struct drm_device *dev = inode->i_private;
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985
075edca4 4986 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4987 return 0;
4988
59bad947 4989 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4990 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4991
4992 return 0;
4993}
4994
4995static const struct file_operations i915_forcewake_fops = {
4996 .owner = THIS_MODULE,
4997 .open = i915_forcewake_open,
4998 .release = i915_forcewake_release,
4999};
5000
5001static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5002{
5003 struct drm_device *dev = minor->dev;
5004 struct dentry *ent;
5005
5006 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5007 S_IRUSR,
6d794d42
BW		 5008 root, dev,
5009 &i915_forcewake_fops);
f3c5fe97
WY		 5010 if (!ent)
5011 return -ENOMEM;
6d794d42 5012
8eb57294 5013 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5014}
5015
6a9c308d
DV		 5016static int i915_debugfs_create(struct dentry *root,
5017 struct drm_minor *minor,
5018 const char *name,
5019 const struct file_operations *fops)
07b7ddd9
JB		 5020{
5021 struct drm_device *dev = minor->dev;
5022 struct dentry *ent;
5023
6a9c308d 5024 ent = debugfs_create_file(name,
07b7ddd9
JB		 5025 S_IRUGO | S_IWUSR,
5026 root, dev,
6a9c308d 5027 fops);
f3c5fe97
WY		 5028 if (!ent)
5029 return -ENOMEM;
07b7ddd9 5030
6a9c308d 5031 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5032}
5033
06c5bf8c 5034static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5035 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5036 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5037 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5038 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5039 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5040 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5041 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5042 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5043 {"i915_gem_request", i915_gem_request_info, 0},
5044 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5045 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5046 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5047 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5048 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5049 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5050 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5051 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 5052 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5053 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5054 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5055 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5056 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 5057 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5058 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5059 {"i915_sr_status", i915_sr_status, 0},
44834a67 5060 {"i915_opregion", i915_opregion, 0},
37811fcc 5061 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5062 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5063 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5064 {"i915_execlists", i915_execlists, 0},
f65367b5 5065 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5066 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5067 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5068 {"i915_llc", i915_llc, 0},
e91fd8c6 5069 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5070 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5071 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5072 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5073 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 5074 {"i915_display_info", i915_display_info, 0},
e04934cf 5075 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5076 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5077 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5078 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5079 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5080 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5081 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5082 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5083};
27c202ad 5084#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5085
06c5bf8c 5086static const struct i915_debugfs_files {
34b9674c
DV		 5087 const char *name;
5088 const struct file_operations *fops;
5089} i915_debugfs_files[] = {
5090 {"i915_wedged", &i915_wedged_fops},
5091 {"i915_max_freq", &i915_max_freq_fops},
5092 {"i915_min_freq", &i915_min_freq_fops},
5093 {"i915_cache_sharing", &i915_cache_sharing_fops},
5094 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5095 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5096 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5097 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5098 {"i915_error_state", &i915_error_state_fops},
5099 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5100 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5101 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5102 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5103 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5104 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5105 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5106 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5107 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5108};
5109
07144428
DL		 5110void intel_display_crc_init(struct drm_device *dev)
5111{
5112 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5113 enum pipe pipe;
07144428 5114
055e393f 5115 for_each_pipe(dev_priv, pipe) {
b378360e 5116 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5117
d538bbdf
DL		 5118 pipe_crc->opened = false;
5119 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5120 init_waitqueue_head(&pipe_crc->wq);
5121 }
5122}
5123
27c202ad 5124int i915_debugfs_init(struct drm_minor *minor)
2017263e 5125{
34b9674c 5126 int ret, i;
f3cd474b 5127
6d794d42 5128 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5129 if (ret)
5130 return ret;
6a9c308d 5131
07144428
DL		 5132 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5133 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5134 if (ret)
5135 return ret;
5136 }
5137
34b9674c
DV		 5138 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5139 ret = i915_debugfs_create(minor->debugfs_root, minor,
5140 i915_debugfs_files[i].name,
5141 i915_debugfs_files[i].fops);
5142 if (ret)
5143 return ret;
5144 }
40633219 5145
27c202ad
BG		 5146 return drm_debugfs_create_files(i915_debugfs_list,
5147 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5148 minor->debugfs_root, minor);
5149}
5150
27c202ad 5151void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5152{
34b9674c
DV		 5153 int i;
5154
27c202ad
BG		 5155 drm_debugfs_remove_files(i915_debugfs_list,
5156 I915_DEBUGFS_ENTRIES, minor);
07144428 5157
6d794d42
BW		 5158 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5159 1, minor);
07144428 5160
e309a997 5161 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5162 struct drm_info_list *info_list =
5163 (struct drm_info_list *)&i915_pipe_crc_data[i];
5164
5165 drm_debugfs_remove_files(info_list, 1, minor);
5166 }
5167
34b9674c
DV		 5168 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5169 struct drm_info_list *info_list =
5170 (struct drm_info_list *) i915_debugfs_files[i].fops;
5171
5172 drm_debugfs_remove_files(info_list, 1, minor);
5173 }
2017263e 5174}
aa7471d2
JN		 5175
5176struct dpcd_block {
5177 /* DPCD dump start address. */
5178 unsigned int offset;
5179 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5180 unsigned int end;
5181 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5182 size_t size;
5183 /* Only valid for eDP. */
5184 bool edp;
5185};
5186
5187static const struct dpcd_block i915_dpcd_debug[] = {
5188 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5189 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5190 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5191 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5192 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5193 { .offset = DP_SET_POWER },
5194 { .offset = DP_EDP_DPCD_REV },
5195 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5196 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5197 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5198};
5199
5200static int i915_dpcd_show(struct seq_file *m, void *data)
5201{
5202 struct drm_connector *connector = m->private;
5203 struct intel_dp *intel_dp =
5204 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5205 uint8_t buf[16];
5206 ssize_t err;
5207 int i;
5208
5c1a8875
MK		 5209 if (connector->status != connector_status_connected)
5210 return -ENODEV;
5211
aa7471d2
JN		 5212 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5213 const struct dpcd_block *b = &i915_dpcd_debug[i];
5214 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5215
5216 if (b->edp &&
5217 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5218 continue;
5219
5220 /* low tech for now */
5221 if (WARN_ON(size > sizeof(buf)))
5222 continue;
5223
5224 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5225 if (err <= 0) {
5226 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5227 size, b->offset, err);
5228 continue;
5229 }
5230
5231 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5232 }
aa7471d2
JN		 5233
5234 return 0;
5235}
5236
5237static int i915_dpcd_open(struct inode *inode, struct file *file)
5238{
5239 return single_open(file, i915_dpcd_show, inode->i_private);
5240}
5241
5242static const struct file_operations i915_dpcd_fops = {
5243 .owner = THIS_MODULE,
5244 .open = i915_dpcd_open,
5245 .read = seq_read,
5246 .llseek = seq_lseek,
5247 .release = single_release,
5248};
5249
5250/**
5251 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5252 * @connector: pointer to a registered drm_connector
5253 *
5254 * Cleanup will be done by drm_connector_unregister() through a call to
5255 * drm_debugfs_connector_remove().
5256 *
5257 * Returns 0 on success, negative error codes on error.
5258 */
5259int i915_debugfs_connector_add(struct drm_connector *connector)
5260{
5261 struct dentry *root = connector->debugfs_entry;
5262
5263 /* The connector must have been registered beforehands. */
5264 if (!root)
5265 return -ENODEV;
5266
5267 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5268 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5269 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5270 &i915_dpcd_fops);
5271
5272 return 0;
5273}
Linux kernel - Deliverables
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