Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
70d39fe4 CW |
49 | static const char *yesno(int v) |
50 | { | |
51 | return v ? "yes" : "no"; | |
52 | } | |
53 | ||
497666d8 DL |
54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
55 | * allocated we need to hook into the minor for release. */ | |
56 | static int | |
57 | drm_add_fake_info_node(struct drm_minor *minor, | |
58 | struct dentry *ent, | |
59 | const void *key) | |
60 | { | |
61 | struct drm_info_node *node; | |
62 | ||
63 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
64 | if (node == NULL) { | |
65 | debugfs_remove(ent); | |
66 | return -ENOMEM; | |
67 | } | |
68 | ||
69 | node->minor = minor; | |
70 | node->dent = ent; | |
71 | node->info_ent = (void *) key; | |
72 | ||
73 | mutex_lock(&minor->debugfs_lock); | |
74 | list_add(&node->list, &minor->debugfs_list); | |
75 | mutex_unlock(&minor->debugfs_lock); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
70d39fe4 CW |
80 | static int i915_capabilities(struct seq_file *m, void *data) |
81 | { | |
82 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
83 | struct drm_device *dev = node->minor->dev; | |
84 | const struct intel_device_info *info = INTEL_INFO(dev); | |
85 | ||
86 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
89 | #define SEP_SEMICOLON ; | |
90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
91 | #undef PRINT_FLAG | |
92 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
93 | |
94 | return 0; | |
95 | } | |
2017263e | 96 | |
05394f39 | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 98 | { |
05394f39 | 99 | if (obj->user_pin_count > 0) |
a6172a80 | 100 | return "P"; |
d7f46fc4 | 101 | else if (i915_gem_obj_is_pinned(obj)) |
a6172a80 CW |
102 | return "p"; |
103 | else | |
104 | return " "; | |
105 | } | |
106 | ||
05394f39 | 107 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 108 | { |
0206e353 AJ |
109 | switch (obj->tiling_mode) { |
110 | default: | |
111 | case I915_TILING_NONE: return " "; | |
112 | case I915_TILING_X: return "X"; | |
113 | case I915_TILING_Y: return "Y"; | |
114 | } | |
a6172a80 CW |
115 | } |
116 | ||
1d693bcc BW |
117 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
118 | { | |
119 | return obj->has_global_gtt_mapping ? "g" : " "; | |
120 | } | |
121 | ||
37811fcc CW |
122 | static void |
123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
124 | { | |
1d693bcc | 125 | struct i915_vma *vma; |
d7f46fc4 BW |
126 | int pin_count = 0; |
127 | ||
fb1ae911 | 128 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
129 | &obj->base, |
130 | get_pin_flag(obj), | |
131 | get_tiling_flag(obj), | |
1d693bcc | 132 | get_global_flag(obj), |
a05a5862 | 133 | obj->base.size / 1024, |
37811fcc CW |
134 | obj->base.read_domains, |
135 | obj->base.write_domain, | |
0201f1ec CW |
136 | obj->last_read_seqno, |
137 | obj->last_write_seqno, | |
caea7476 | 138 | obj->last_fenced_seqno, |
84734a04 | 139 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
140 | obj->dirty ? " dirty" : "", |
141 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
142 | if (obj->base.name) | |
143 | seq_printf(m, " (name: %d)", obj->base.name); | |
d7f46fc4 BW |
144 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
145 | if (vma->pin_count > 0) | |
146 | pin_count++; | |
147 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
148 | if (obj->pin_display) |
149 | seq_printf(m, " (display)"); | |
37811fcc CW |
150 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
151 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
152 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
153 | if (!i915_is_ggtt(vma->vm)) | |
154 | seq_puts(m, " (pp"); | |
155 | else | |
156 | seq_puts(m, " (g"); | |
157 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
158 | vma->node.start, vma->node.size); | |
159 | } | |
c1ad11fc CW |
160 | if (obj->stolen) |
161 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
162 | if (obj->pin_mappable || obj->fault_mappable) { |
163 | char s[3], *t = s; | |
164 | if (obj->pin_mappable) | |
165 | *t++ = 'p'; | |
166 | if (obj->fault_mappable) | |
167 | *t++ = 'f'; | |
168 | *t = '\0'; | |
169 | seq_printf(m, " (%s mappable)", s); | |
170 | } | |
69dc4987 CW |
171 | if (obj->ring != NULL) |
172 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
173 | } |
174 | ||
3ccfd19d BW |
175 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
176 | { | |
177 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); | |
178 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); | |
179 | seq_putc(m, ' '); | |
180 | } | |
181 | ||
433e12f7 | 182 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
183 | { |
184 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
185 | uintptr_t list = (uintptr_t) node->info_ent->data; |
186 | struct list_head *head; | |
2017263e | 187 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
188 | struct drm_i915_private *dev_priv = dev->dev_private; |
189 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 190 | struct i915_vma *vma; |
8f2480fb CW |
191 | size_t total_obj_size, total_gtt_size; |
192 | int count, ret; | |
de227ef0 CW |
193 | |
194 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
195 | if (ret) | |
196 | return ret; | |
2017263e | 197 | |
ca191b13 | 198 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
199 | switch (list) { |
200 | case ACTIVE_LIST: | |
267f0c90 | 201 | seq_puts(m, "Active:\n"); |
5cef07e1 | 202 | head = &vm->active_list; |
433e12f7 BG |
203 | break; |
204 | case INACTIVE_LIST: | |
267f0c90 | 205 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 206 | head = &vm->inactive_list; |
433e12f7 | 207 | break; |
433e12f7 | 208 | default: |
de227ef0 CW |
209 | mutex_unlock(&dev->struct_mutex); |
210 | return -EINVAL; | |
2017263e | 211 | } |
2017263e | 212 | |
8f2480fb | 213 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
214 | list_for_each_entry(vma, head, mm_list) { |
215 | seq_printf(m, " "); | |
216 | describe_obj(m, vma->obj); | |
217 | seq_printf(m, "\n"); | |
218 | total_obj_size += vma->obj->base.size; | |
219 | total_gtt_size += vma->node.size; | |
8f2480fb | 220 | count++; |
2017263e | 221 | } |
de227ef0 | 222 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 223 | |
8f2480fb CW |
224 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
225 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
226 | return 0; |
227 | } | |
228 | ||
6d2b8885 CW |
229 | static int obj_rank_by_stolen(void *priv, |
230 | struct list_head *A, struct list_head *B) | |
231 | { | |
232 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 233 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 234 | struct drm_i915_gem_object *b = |
b25cb2f8 | 235 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
236 | |
237 | return a->stolen->start - b->stolen->start; | |
238 | } | |
239 | ||
240 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
241 | { | |
242 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
243 | struct drm_device *dev = node->minor->dev; | |
244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
245 | struct drm_i915_gem_object *obj; | |
246 | size_t total_obj_size, total_gtt_size; | |
247 | LIST_HEAD(stolen); | |
248 | int count, ret; | |
249 | ||
250 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
251 | if (ret) | |
252 | return ret; | |
253 | ||
254 | total_obj_size = total_gtt_size = count = 0; | |
255 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
256 | if (obj->stolen == NULL) | |
257 | continue; | |
258 | ||
b25cb2f8 | 259 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
260 | |
261 | total_obj_size += obj->base.size; | |
262 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
263 | count++; | |
264 | } | |
265 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
266 | if (obj->stolen == NULL) | |
267 | continue; | |
268 | ||
b25cb2f8 | 269 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
270 | |
271 | total_obj_size += obj->base.size; | |
272 | count++; | |
273 | } | |
274 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
275 | seq_puts(m, "Stolen:\n"); | |
276 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 277 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
278 | seq_puts(m, " "); |
279 | describe_obj(m, obj); | |
280 | seq_putc(m, '\n'); | |
b25cb2f8 | 281 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
282 | } |
283 | mutex_unlock(&dev->struct_mutex); | |
284 | ||
285 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
286 | count, total_obj_size, total_gtt_size); | |
287 | return 0; | |
288 | } | |
289 | ||
6299f992 CW |
290 | #define count_objects(list, member) do { \ |
291 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 292 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
293 | ++count; \ |
294 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 295 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
296 | ++mappable_count; \ |
297 | } \ | |
298 | } \ | |
0206e353 | 299 | } while (0) |
6299f992 | 300 | |
2db8e9d6 | 301 | struct file_stats { |
6313c204 | 302 | struct drm_i915_file_private *file_priv; |
2db8e9d6 | 303 | int count; |
c67a17e9 CW |
304 | size_t total, unbound; |
305 | size_t global, shared; | |
306 | size_t active, inactive; | |
2db8e9d6 CW |
307 | }; |
308 | ||
309 | static int per_file_stats(int id, void *ptr, void *data) | |
310 | { | |
311 | struct drm_i915_gem_object *obj = ptr; | |
312 | struct file_stats *stats = data; | |
6313c204 | 313 | struct i915_vma *vma; |
2db8e9d6 CW |
314 | |
315 | stats->count++; | |
316 | stats->total += obj->base.size; | |
317 | ||
c67a17e9 CW |
318 | if (obj->base.name || obj->base.dma_buf) |
319 | stats->shared += obj->base.size; | |
320 | ||
6313c204 CW |
321 | if (USES_FULL_PPGTT(obj->base.dev)) { |
322 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
323 | struct i915_hw_ppgtt *ppgtt; | |
324 | ||
325 | if (!drm_mm_node_allocated(&vma->node)) | |
326 | continue; | |
327 | ||
328 | if (i915_is_ggtt(vma->vm)) { | |
329 | stats->global += obj->base.size; | |
330 | continue; | |
331 | } | |
332 | ||
333 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
334 | if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv) | |
335 | continue; | |
336 | ||
337 | if (obj->ring) /* XXX per-vma statistic */ | |
338 | stats->active += obj->base.size; | |
339 | else | |
340 | stats->inactive += obj->base.size; | |
341 | ||
342 | return 0; | |
343 | } | |
2db8e9d6 | 344 | } else { |
6313c204 CW |
345 | if (i915_gem_obj_ggtt_bound(obj)) { |
346 | stats->global += obj->base.size; | |
347 | if (obj->ring) | |
348 | stats->active += obj->base.size; | |
349 | else | |
350 | stats->inactive += obj->base.size; | |
351 | return 0; | |
352 | } | |
2db8e9d6 CW |
353 | } |
354 | ||
6313c204 CW |
355 | if (!list_empty(&obj->global_list)) |
356 | stats->unbound += obj->base.size; | |
357 | ||
2db8e9d6 CW |
358 | return 0; |
359 | } | |
360 | ||
ca191b13 BW |
361 | #define count_vmas(list, member) do { \ |
362 | list_for_each_entry(vma, list, member) { \ | |
363 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
364 | ++count; \ | |
365 | if (vma->obj->map_and_fenceable) { \ | |
366 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
367 | ++mappable_count; \ | |
368 | } \ | |
369 | } \ | |
370 | } while (0) | |
371 | ||
372 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
373 | { |
374 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
375 | struct drm_device *dev = node->minor->dev; | |
376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
377 | u32 count, mappable_count, purgeable_count; |
378 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 379 | struct drm_i915_gem_object *obj; |
5cef07e1 | 380 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 381 | struct drm_file *file; |
ca191b13 | 382 | struct i915_vma *vma; |
73aa808f CW |
383 | int ret; |
384 | ||
385 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
386 | if (ret) | |
387 | return ret; | |
388 | ||
6299f992 CW |
389 | seq_printf(m, "%u objects, %zu bytes\n", |
390 | dev_priv->mm.object_count, | |
391 | dev_priv->mm.object_memory); | |
392 | ||
393 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 394 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
395 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
396 | count, mappable_count, size, mappable_size); | |
397 | ||
398 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 399 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
400 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
401 | count, mappable_count, size, mappable_size); | |
402 | ||
6299f992 | 403 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 404 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
405 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
406 | count, mappable_count, size, mappable_size); | |
407 | ||
b7abb714 | 408 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 409 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 410 | size += obj->base.size, ++count; |
b7abb714 CW |
411 | if (obj->madv == I915_MADV_DONTNEED) |
412 | purgeable_size += obj->base.size, ++purgeable_count; | |
413 | } | |
6c085a72 CW |
414 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
415 | ||
6299f992 | 416 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 417 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 418 | if (obj->fault_mappable) { |
f343c5f6 | 419 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
420 | ++count; |
421 | } | |
422 | if (obj->pin_mappable) { | |
f343c5f6 | 423 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
424 | ++mappable_count; |
425 | } | |
b7abb714 CW |
426 | if (obj->madv == I915_MADV_DONTNEED) { |
427 | purgeable_size += obj->base.size; | |
428 | ++purgeable_count; | |
429 | } | |
6299f992 | 430 | } |
b7abb714 CW |
431 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
432 | purgeable_count, purgeable_size); | |
6299f992 CW |
433 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
434 | mappable_count, mappable_size); | |
435 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
436 | count, size); | |
437 | ||
93d18799 | 438 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
439 | dev_priv->gtt.base.total, |
440 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 441 | |
267f0c90 | 442 | seq_putc(m, '\n'); |
2db8e9d6 CW |
443 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
444 | struct file_stats stats; | |
3ec2f427 | 445 | struct task_struct *task; |
2db8e9d6 CW |
446 | |
447 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 448 | stats.file_priv = file->driver_priv; |
2db8e9d6 | 449 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
3ec2f427 TH |
450 | /* |
451 | * Although we have a valid reference on file->pid, that does | |
452 | * not guarantee that the task_struct who called get_pid() is | |
453 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
454 | * Therefore, we need to protect this ->comm access using RCU. | |
455 | */ | |
456 | rcu_read_lock(); | |
457 | task = pid_task(file->pid, PIDTYPE_PID); | |
c67a17e9 | 458 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", |
3ec2f427 | 459 | task ? task->comm : "<unknown>", |
2db8e9d6 CW |
460 | stats.count, |
461 | stats.total, | |
462 | stats.active, | |
463 | stats.inactive, | |
6313c204 | 464 | stats.global, |
c67a17e9 | 465 | stats.shared, |
2db8e9d6 | 466 | stats.unbound); |
3ec2f427 | 467 | rcu_read_unlock(); |
2db8e9d6 CW |
468 | } |
469 | ||
73aa808f CW |
470 | mutex_unlock(&dev->struct_mutex); |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
aee56cff | 475 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
476 | { |
477 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
478 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 479 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
480 | struct drm_i915_private *dev_priv = dev->dev_private; |
481 | struct drm_i915_gem_object *obj; | |
482 | size_t total_obj_size, total_gtt_size; | |
483 | int count, ret; | |
484 | ||
485 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
486 | if (ret) | |
487 | return ret; | |
488 | ||
489 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 490 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 491 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
492 | continue; |
493 | ||
267f0c90 | 494 | seq_puts(m, " "); |
08c18323 | 495 | describe_obj(m, obj); |
267f0c90 | 496 | seq_putc(m, '\n'); |
08c18323 | 497 | total_obj_size += obj->base.size; |
f343c5f6 | 498 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
499 | count++; |
500 | } | |
501 | ||
502 | mutex_unlock(&dev->struct_mutex); | |
503 | ||
504 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
505 | count, total_obj_size, total_gtt_size); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
4e5359cd SF |
510 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
511 | { | |
512 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
513 | struct drm_device *dev = node->minor->dev; | |
514 | unsigned long flags; | |
515 | struct intel_crtc *crtc; | |
516 | ||
517 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
518 | const char pipe = pipe_name(crtc->pipe); |
519 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
520 | struct intel_unpin_work *work; |
521 | ||
522 | spin_lock_irqsave(&dev->event_lock, flags); | |
523 | work = crtc->unpin_work; | |
524 | if (work == NULL) { | |
9db4a9c7 | 525 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
526 | pipe, plane); |
527 | } else { | |
e7d841ca | 528 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 529 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
530 | pipe, plane); |
531 | } else { | |
9db4a9c7 | 532 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
533 | pipe, plane); |
534 | } | |
535 | if (work->enable_stall_check) | |
267f0c90 | 536 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 537 | else |
267f0c90 | 538 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 539 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
540 | |
541 | if (work->old_fb_obj) { | |
05394f39 CW |
542 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
543 | if (obj) | |
f343c5f6 BW |
544 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
545 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
546 | } |
547 | if (work->pending_flip_obj) { | |
05394f39 CW |
548 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
549 | if (obj) | |
f343c5f6 BW |
550 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
551 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
552 | } |
553 | } | |
554 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
555 | } | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
2017263e BG |
560 | static int i915_gem_request_info(struct seq_file *m, void *data) |
561 | { | |
562 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
563 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 564 | struct drm_i915_private *dev_priv = dev->dev_private; |
a2c7f6fd | 565 | struct intel_ring_buffer *ring; |
2017263e | 566 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 567 | int ret, count, i; |
de227ef0 CW |
568 | |
569 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
570 | if (ret) | |
571 | return ret; | |
2017263e | 572 | |
c2c347a9 | 573 | count = 0; |
a2c7f6fd CW |
574 | for_each_ring(ring, dev_priv, i) { |
575 | if (list_empty(&ring->request_list)) | |
576 | continue; | |
577 | ||
578 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 579 | list_for_each_entry(gem_request, |
a2c7f6fd | 580 | &ring->request_list, |
c2c347a9 CW |
581 | list) { |
582 | seq_printf(m, " %d @ %d\n", | |
583 | gem_request->seqno, | |
584 | (int) (jiffies - gem_request->emitted_jiffies)); | |
585 | } | |
586 | count++; | |
2017263e | 587 | } |
de227ef0 CW |
588 | mutex_unlock(&dev->struct_mutex); |
589 | ||
c2c347a9 | 590 | if (count == 0) |
267f0c90 | 591 | seq_puts(m, "No requests\n"); |
c2c347a9 | 592 | |
2017263e BG |
593 | return 0; |
594 | } | |
595 | ||
b2223497 CW |
596 | static void i915_ring_seqno_info(struct seq_file *m, |
597 | struct intel_ring_buffer *ring) | |
598 | { | |
599 | if (ring->get_seqno) { | |
43a7b924 | 600 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 601 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
602 | } |
603 | } | |
604 | ||
2017263e BG |
605 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
606 | { | |
607 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
608 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 609 | struct drm_i915_private *dev_priv = dev->dev_private; |
a2c7f6fd | 610 | struct intel_ring_buffer *ring; |
1ec14ad3 | 611 | int ret, i; |
de227ef0 CW |
612 | |
613 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
614 | if (ret) | |
615 | return ret; | |
c8c8fb33 | 616 | intel_runtime_pm_get(dev_priv); |
2017263e | 617 | |
a2c7f6fd CW |
618 | for_each_ring(ring, dev_priv, i) |
619 | i915_ring_seqno_info(m, ring); | |
de227ef0 | 620 | |
c8c8fb33 | 621 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
622 | mutex_unlock(&dev->struct_mutex); |
623 | ||
2017263e BG |
624 | return 0; |
625 | } | |
626 | ||
627 | ||
628 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
629 | { | |
630 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
631 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 632 | struct drm_i915_private *dev_priv = dev->dev_private; |
a2c7f6fd | 633 | struct intel_ring_buffer *ring; |
9db4a9c7 | 634 | int ret, i, pipe; |
de227ef0 CW |
635 | |
636 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
637 | if (ret) | |
638 | return ret; | |
c8c8fb33 | 639 | intel_runtime_pm_get(dev_priv); |
2017263e | 640 | |
a123f157 | 641 | if (INTEL_INFO(dev)->gen >= 8) { |
a123f157 BW |
642 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
643 | I915_READ(GEN8_MASTER_IRQ)); | |
644 | ||
645 | for (i = 0; i < 4; i++) { | |
646 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
647 | i, I915_READ(GEN8_GT_IMR(i))); | |
648 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
649 | i, I915_READ(GEN8_GT_IIR(i))); | |
650 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
651 | i, I915_READ(GEN8_GT_IER(i))); | |
652 | } | |
653 | ||
07d27e20 | 654 | for_each_pipe(pipe) { |
a123f157 | 655 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
656 | pipe_name(pipe), |
657 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 658 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
659 | pipe_name(pipe), |
660 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 661 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
662 | pipe_name(pipe), |
663 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
a123f157 BW |
664 | } |
665 | ||
666 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
667 | I915_READ(GEN8_DE_PORT_IMR)); | |
668 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
669 | I915_READ(GEN8_DE_PORT_IIR)); | |
670 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
671 | I915_READ(GEN8_DE_PORT_IER)); | |
672 | ||
673 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
674 | I915_READ(GEN8_DE_MISC_IMR)); | |
675 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
676 | I915_READ(GEN8_DE_MISC_IIR)); | |
677 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
678 | I915_READ(GEN8_DE_MISC_IER)); | |
679 | ||
680 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
681 | I915_READ(GEN8_PCU_IMR)); | |
682 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
683 | I915_READ(GEN8_PCU_IIR)); | |
684 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
685 | I915_READ(GEN8_PCU_IER)); | |
686 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
687 | seq_printf(m, "Display IER:\t%08x\n", |
688 | I915_READ(VLV_IER)); | |
689 | seq_printf(m, "Display IIR:\t%08x\n", | |
690 | I915_READ(VLV_IIR)); | |
691 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
692 | I915_READ(VLV_IIR_RW)); | |
693 | seq_printf(m, "Display IMR:\t%08x\n", | |
694 | I915_READ(VLV_IMR)); | |
695 | for_each_pipe(pipe) | |
696 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
697 | pipe_name(pipe), | |
698 | I915_READ(PIPESTAT(pipe))); | |
699 | ||
700 | seq_printf(m, "Master IER:\t%08x\n", | |
701 | I915_READ(VLV_MASTER_IER)); | |
702 | ||
703 | seq_printf(m, "Render IER:\t%08x\n", | |
704 | I915_READ(GTIER)); | |
705 | seq_printf(m, "Render IIR:\t%08x\n", | |
706 | I915_READ(GTIIR)); | |
707 | seq_printf(m, "Render IMR:\t%08x\n", | |
708 | I915_READ(GTIMR)); | |
709 | ||
710 | seq_printf(m, "PM IER:\t\t%08x\n", | |
711 | I915_READ(GEN6_PMIER)); | |
712 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
713 | I915_READ(GEN6_PMIIR)); | |
714 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
715 | I915_READ(GEN6_PMIMR)); | |
716 | ||
717 | seq_printf(m, "Port hotplug:\t%08x\n", | |
718 | I915_READ(PORT_HOTPLUG_EN)); | |
719 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
720 | I915_READ(VLV_DPFLIPSTAT)); | |
721 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
722 | I915_READ(DPINVGTT)); | |
723 | ||
724 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
725 | seq_printf(m, "Interrupt enable: %08x\n", |
726 | I915_READ(IER)); | |
727 | seq_printf(m, "Interrupt identity: %08x\n", | |
728 | I915_READ(IIR)); | |
729 | seq_printf(m, "Interrupt mask: %08x\n", | |
730 | I915_READ(IMR)); | |
9db4a9c7 JB |
731 | for_each_pipe(pipe) |
732 | seq_printf(m, "Pipe %c stat: %08x\n", | |
733 | pipe_name(pipe), | |
734 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
735 | } else { |
736 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
737 | I915_READ(DEIER)); | |
738 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
739 | I915_READ(DEIIR)); | |
740 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
741 | I915_READ(DEIMR)); | |
742 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
743 | I915_READ(SDEIER)); | |
744 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
745 | I915_READ(SDEIIR)); | |
746 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
747 | I915_READ(SDEIMR)); | |
748 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
749 | I915_READ(GTIER)); | |
750 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
751 | I915_READ(GTIIR)); | |
752 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
753 | I915_READ(GTIMR)); | |
754 | } | |
a2c7f6fd | 755 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 756 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
757 | seq_printf(m, |
758 | "Graphics Interrupt mask (%s): %08x\n", | |
759 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 760 | } |
a2c7f6fd | 761 | i915_ring_seqno_info(m, ring); |
9862e600 | 762 | } |
c8c8fb33 | 763 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
764 | mutex_unlock(&dev->struct_mutex); |
765 | ||
2017263e BG |
766 | return 0; |
767 | } | |
768 | ||
a6172a80 CW |
769 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
770 | { | |
771 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
772 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 773 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
774 | int i, ret; |
775 | ||
776 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
777 | if (ret) | |
778 | return ret; | |
a6172a80 CW |
779 | |
780 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
781 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
782 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 783 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 784 | |
6c085a72 CW |
785 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
786 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 787 | if (obj == NULL) |
267f0c90 | 788 | seq_puts(m, "unused"); |
c2c347a9 | 789 | else |
05394f39 | 790 | describe_obj(m, obj); |
267f0c90 | 791 | seq_putc(m, '\n'); |
a6172a80 CW |
792 | } |
793 | ||
05394f39 | 794 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
795 | return 0; |
796 | } | |
797 | ||
2017263e BG |
798 | static int i915_hws_info(struct seq_file *m, void *data) |
799 | { | |
800 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
801 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 802 | struct drm_i915_private *dev_priv = dev->dev_private; |
4066c0ae | 803 | struct intel_ring_buffer *ring; |
1a240d4d | 804 | const u32 *hws; |
4066c0ae CW |
805 | int i; |
806 | ||
1ec14ad3 | 807 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 808 | hws = ring->status_page.page_addr; |
2017263e BG |
809 | if (hws == NULL) |
810 | return 0; | |
811 | ||
812 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
813 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
814 | i * 4, | |
815 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
816 | } | |
817 | return 0; | |
818 | } | |
819 | ||
d5442303 DV |
820 | static ssize_t |
821 | i915_error_state_write(struct file *filp, | |
822 | const char __user *ubuf, | |
823 | size_t cnt, | |
824 | loff_t *ppos) | |
825 | { | |
edc3d884 | 826 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 827 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 828 | int ret; |
d5442303 DV |
829 | |
830 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
831 | ||
22bcfc6a DV |
832 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
833 | if (ret) | |
834 | return ret; | |
835 | ||
d5442303 DV |
836 | i915_destroy_error_state(dev); |
837 | mutex_unlock(&dev->struct_mutex); | |
838 | ||
839 | return cnt; | |
840 | } | |
841 | ||
842 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
843 | { | |
844 | struct drm_device *dev = inode->i_private; | |
d5442303 | 845 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
846 | |
847 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
848 | if (!error_priv) | |
849 | return -ENOMEM; | |
850 | ||
851 | error_priv->dev = dev; | |
852 | ||
95d5bfb3 | 853 | i915_error_state_get(dev, error_priv); |
d5442303 | 854 | |
edc3d884 MK |
855 | file->private_data = error_priv; |
856 | ||
857 | return 0; | |
d5442303 DV |
858 | } |
859 | ||
860 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
861 | { | |
edc3d884 | 862 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 863 | |
95d5bfb3 | 864 | i915_error_state_put(error_priv); |
d5442303 DV |
865 | kfree(error_priv); |
866 | ||
edc3d884 MK |
867 | return 0; |
868 | } | |
869 | ||
4dc955f7 MK |
870 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
871 | size_t count, loff_t *pos) | |
872 | { | |
873 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
874 | struct drm_i915_error_state_buf error_str; | |
875 | loff_t tmp_pos = 0; | |
876 | ssize_t ret_count = 0; | |
877 | int ret; | |
878 | ||
879 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
880 | if (ret) | |
881 | return ret; | |
edc3d884 | 882 | |
fc16b48b | 883 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
884 | if (ret) |
885 | goto out; | |
886 | ||
edc3d884 MK |
887 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
888 | error_str.buf, | |
889 | error_str.bytes); | |
890 | ||
891 | if (ret_count < 0) | |
892 | ret = ret_count; | |
893 | else | |
894 | *pos = error_str.start + ret_count; | |
895 | out: | |
4dc955f7 | 896 | i915_error_state_buf_release(&error_str); |
edc3d884 | 897 | return ret ?: ret_count; |
d5442303 DV |
898 | } |
899 | ||
900 | static const struct file_operations i915_error_state_fops = { | |
901 | .owner = THIS_MODULE, | |
902 | .open = i915_error_state_open, | |
edc3d884 | 903 | .read = i915_error_state_read, |
d5442303 DV |
904 | .write = i915_error_state_write, |
905 | .llseek = default_llseek, | |
906 | .release = i915_error_state_release, | |
907 | }; | |
908 | ||
647416f9 KC |
909 | static int |
910 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 911 | { |
647416f9 | 912 | struct drm_device *dev = data; |
e277a1f8 | 913 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
914 | int ret; |
915 | ||
916 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
917 | if (ret) | |
918 | return ret; | |
919 | ||
647416f9 | 920 | *val = dev_priv->next_seqno; |
40633219 MK |
921 | mutex_unlock(&dev->struct_mutex); |
922 | ||
647416f9 | 923 | return 0; |
40633219 MK |
924 | } |
925 | ||
647416f9 KC |
926 | static int |
927 | i915_next_seqno_set(void *data, u64 val) | |
928 | { | |
929 | struct drm_device *dev = data; | |
40633219 MK |
930 | int ret; |
931 | ||
40633219 MK |
932 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
933 | if (ret) | |
934 | return ret; | |
935 | ||
e94fbaa8 | 936 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
937 | mutex_unlock(&dev->struct_mutex); |
938 | ||
647416f9 | 939 | return ret; |
40633219 MK |
940 | } |
941 | ||
647416f9 KC |
942 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
943 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 944 | "0x%llx\n"); |
40633219 | 945 | |
f97108d1 JB |
946 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
947 | { | |
948 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
949 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 950 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
951 | u16 crstanddelay; |
952 | int ret; | |
953 | ||
954 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
955 | if (ret) | |
956 | return ret; | |
c8c8fb33 | 957 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
958 | |
959 | crstanddelay = I915_READ16(CRSTANDVID); | |
960 | ||
c8c8fb33 | 961 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 962 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
963 | |
964 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
adb4bd12 | 969 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 JB |
970 | { |
971 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
972 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 973 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
974 | int ret = 0; |
975 | ||
976 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 977 | |
5c9669ce TR |
978 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
979 | ||
3b8d8d91 JB |
980 | if (IS_GEN5(dev)) { |
981 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
982 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
983 | ||
984 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
985 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
986 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
987 | MEMSTAT_VID_SHIFT); | |
988 | seq_printf(m, "Current P-state: %d\n", | |
989 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 990 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
991 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
992 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
993 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
0d8f9491 | 994 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 995 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
996 | u32 rpupei, rpcurup, rpprevup; |
997 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
998 | int max_freq; |
999 | ||
1000 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
1001 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1002 | if (ret) | |
c8c8fb33 | 1003 | goto out; |
d1ebd816 | 1004 | |
c8d9a590 | 1005 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1006 | |
8e8c06cd CW |
1007 | reqf = I915_READ(GEN6_RPNSWREQ); |
1008 | reqf &= ~GEN6_TURBO_DISABLE; | |
1009 | if (IS_HASWELL(dev)) | |
1010 | reqf >>= 24; | |
1011 | else | |
1012 | reqf >>= 25; | |
1013 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
1014 | ||
0d8f9491 CW |
1015 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1016 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1017 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1018 | ||
ccab5c82 JB |
1019 | rpstat = I915_READ(GEN6_RPSTAT1); |
1020 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
1021 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
1022 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
1023 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
1024 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
1025 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
1026 | if (IS_HASWELL(dev)) |
1027 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
1028 | else | |
1029 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
1030 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 1031 | |
c8d9a590 | 1032 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1033 | mutex_unlock(&dev->struct_mutex); |
1034 | ||
0d8f9491 CW |
1035 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
1036 | I915_READ(GEN6_PMIER), | |
1037 | I915_READ(GEN6_PMIMR), | |
1038 | I915_READ(GEN6_PMISR), | |
1039 | I915_READ(GEN6_PMIIR), | |
1040 | I915_READ(GEN6_PMINTRMSK)); | |
3b8d8d91 | 1041 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 JB |
1042 | seq_printf(m, "Render p-state ratio: %d\n", |
1043 | (gt_perf_status & 0xff00) >> 8); | |
1044 | seq_printf(m, "Render p-state VID: %d\n", | |
1045 | gt_perf_status & 0xff); | |
1046 | seq_printf(m, "Render p-state limit: %d\n", | |
1047 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1048 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1049 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1050 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1051 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1052 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1053 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1054 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1055 | GEN6_CURICONT_MASK); | |
1056 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1057 | GEN6_CURBSYTAVG_MASK); | |
1058 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1059 | GEN6_CURBSYTAVG_MASK); | |
1060 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
1061 | GEN6_CURIAVG_MASK); | |
1062 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1063 | GEN6_CURBSYTAVG_MASK); | |
1064 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1065 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
1066 | |
1067 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
1068 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 1069 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1070 | |
1071 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
1072 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 1073 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1074 | |
1075 | max_freq = rp_state_cap & 0xff; | |
1076 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 1077 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
1078 | |
1079 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
b39fb297 | 1080 | dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER); |
0a073b84 JB |
1081 | } else if (IS_VALLEYVIEW(dev)) { |
1082 | u32 freq_sts, val; | |
1083 | ||
259bd5d4 | 1084 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1085 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1086 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1087 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1088 | ||
c5bd2bf6 | 1089 | val = valleyview_rps_max_freq(dev_priv); |
0a073b84 | 1090 | seq_printf(m, "max GPU freq: %d MHz\n", |
2ec3815f | 1091 | vlv_gpu_freq(dev_priv, val)); |
0a073b84 | 1092 | |
c5bd2bf6 | 1093 | val = valleyview_rps_min_freq(dev_priv); |
0a073b84 | 1094 | seq_printf(m, "min GPU freq: %d MHz\n", |
2ec3815f | 1095 | vlv_gpu_freq(dev_priv, val)); |
0a073b84 JB |
1096 | |
1097 | seq_printf(m, "current GPU freq: %d MHz\n", | |
2ec3815f | 1098 | vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
259bd5d4 | 1099 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1100 | } else { |
267f0c90 | 1101 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1102 | } |
f97108d1 | 1103 | |
c8c8fb33 PZ |
1104 | out: |
1105 | intel_runtime_pm_put(dev_priv); | |
1106 | return ret; | |
f97108d1 JB |
1107 | } |
1108 | ||
1109 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
1110 | { | |
1111 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1112 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 1113 | struct drm_i915_private *dev_priv = dev->dev_private; |
f97108d1 | 1114 | u32 delayfreq; |
616fdb5a BW |
1115 | int ret, i; |
1116 | ||
1117 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1118 | if (ret) | |
1119 | return ret; | |
c8c8fb33 | 1120 | intel_runtime_pm_get(dev_priv); |
f97108d1 JB |
1121 | |
1122 | for (i = 0; i < 16; i++) { | |
1123 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
1124 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
1125 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
1126 | } |
1127 | ||
c8c8fb33 PZ |
1128 | intel_runtime_pm_put(dev_priv); |
1129 | ||
616fdb5a BW |
1130 | mutex_unlock(&dev->struct_mutex); |
1131 | ||
f97108d1 JB |
1132 | return 0; |
1133 | } | |
1134 | ||
1135 | static inline int MAP_TO_MV(int map) | |
1136 | { | |
1137 | return 1250 - (map * 25); | |
1138 | } | |
1139 | ||
1140 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
1141 | { | |
1142 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1143 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 1144 | struct drm_i915_private *dev_priv = dev->dev_private; |
f97108d1 | 1145 | u32 inttoext; |
616fdb5a BW |
1146 | int ret, i; |
1147 | ||
1148 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1149 | if (ret) | |
1150 | return ret; | |
c8c8fb33 | 1151 | intel_runtime_pm_get(dev_priv); |
f97108d1 JB |
1152 | |
1153 | for (i = 1; i <= 32; i++) { | |
1154 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1155 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1156 | } | |
1157 | ||
c8c8fb33 | 1158 | intel_runtime_pm_put(dev_priv); |
616fdb5a BW |
1159 | mutex_unlock(&dev->struct_mutex); |
1160 | ||
f97108d1 JB |
1161 | return 0; |
1162 | } | |
1163 | ||
4d85529d | 1164 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1165 | { |
1166 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1167 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 1168 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1169 | u32 rgvmodectl, rstdbyctl; |
1170 | u16 crstandvid; | |
1171 | int ret; | |
1172 | ||
1173 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1174 | if (ret) | |
1175 | return ret; | |
c8c8fb33 | 1176 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1177 | |
1178 | rgvmodectl = I915_READ(MEMMODECTL); | |
1179 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1180 | crstandvid = I915_READ16(CRSTANDVID); | |
1181 | ||
c8c8fb33 | 1182 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1183 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
1184 | |
1185 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1186 | "yes" : "no"); | |
1187 | seq_printf(m, "Boost freq: %d\n", | |
1188 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1189 | MEMMODE_BOOST_FREQ_SHIFT); | |
1190 | seq_printf(m, "HW control enabled: %s\n", | |
1191 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1192 | seq_printf(m, "SW control enabled: %s\n", | |
1193 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1194 | seq_printf(m, "Gated voltage change: %s\n", | |
1195 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1196 | seq_printf(m, "Starting frequency: P%d\n", | |
1197 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1198 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1199 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1200 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1201 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1202 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1203 | seq_printf(m, "Render standby enabled: %s\n", | |
1204 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1205 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1206 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1207 | case RSX_STATUS_ON: | |
267f0c90 | 1208 | seq_puts(m, "on\n"); |
88271da3 JB |
1209 | break; |
1210 | case RSX_STATUS_RC1: | |
267f0c90 | 1211 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1212 | break; |
1213 | case RSX_STATUS_RC1E: | |
267f0c90 | 1214 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1215 | break; |
1216 | case RSX_STATUS_RS1: | |
267f0c90 | 1217 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1218 | break; |
1219 | case RSX_STATUS_RS2: | |
267f0c90 | 1220 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1221 | break; |
1222 | case RSX_STATUS_RS3: | |
267f0c90 | 1223 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1224 | break; |
1225 | default: | |
267f0c90 | 1226 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1227 | break; |
1228 | } | |
f97108d1 JB |
1229 | |
1230 | return 0; | |
1231 | } | |
1232 | ||
669ab5aa D |
1233 | static int vlv_drpc_info(struct seq_file *m) |
1234 | { | |
1235 | ||
1236 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1237 | struct drm_device *dev = node->minor->dev; | |
1238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1239 | u32 rpmodectl1, rcctl1; | |
1240 | unsigned fw_rendercount = 0, fw_mediacount = 0; | |
1241 | ||
d46c0517 ID |
1242 | intel_runtime_pm_get(dev_priv); |
1243 | ||
669ab5aa D |
1244 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1245 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1246 | ||
d46c0517 ID |
1247 | intel_runtime_pm_put(dev_priv); |
1248 | ||
669ab5aa D |
1249 | seq_printf(m, "Video Turbo Mode: %s\n", |
1250 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1251 | seq_printf(m, "Turbo enabled: %s\n", | |
1252 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1253 | seq_printf(m, "HW control enabled: %s\n", | |
1254 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1255 | seq_printf(m, "SW control enabled: %s\n", | |
1256 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1257 | GEN6_RP_MEDIA_SW_MODE)); | |
1258 | seq_printf(m, "RC6 Enabled: %s\n", | |
1259 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1260 | GEN6_RC_CTL_EI_MODE(1)))); | |
1261 | seq_printf(m, "Render Power Well: %s\n", | |
1262 | (I915_READ(VLV_GTLC_PW_STATUS) & | |
1263 | VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1264 | seq_printf(m, "Media Power Well: %s\n", | |
1265 | (I915_READ(VLV_GTLC_PW_STATUS) & | |
1266 | VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1267 | ||
9cc19be5 ID |
1268 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1269 | I915_READ(VLV_GT_RENDER_RC6)); | |
1270 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1271 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1272 | ||
669ab5aa D |
1273 | spin_lock_irq(&dev_priv->uncore.lock); |
1274 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1275 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1276 | spin_unlock_irq(&dev_priv->uncore.lock); | |
1277 | ||
1278 | seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount); | |
1279 | seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount); | |
1280 | ||
1281 | ||
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | ||
4d85529d BW |
1286 | static int gen6_drpc_info(struct seq_file *m) |
1287 | { | |
1288 | ||
1289 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1290 | struct drm_device *dev = node->minor->dev; | |
1291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1292 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1293 | unsigned forcewake_count; |
aee56cff | 1294 | int count = 0, ret; |
4d85529d BW |
1295 | |
1296 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1297 | if (ret) | |
1298 | return ret; | |
c8c8fb33 | 1299 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1300 | |
907b28c5 CW |
1301 | spin_lock_irq(&dev_priv->uncore.lock); |
1302 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1303 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1304 | |
1305 | if (forcewake_count) { | |
267f0c90 DL |
1306 | seq_puts(m, "RC information inaccurate because somebody " |
1307 | "holds a forcewake reference \n"); | |
4d85529d BW |
1308 | } else { |
1309 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1310 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1311 | udelay(10); | |
1312 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1313 | } | |
1314 | ||
1315 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1316 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1317 | |
1318 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1319 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1320 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1321 | mutex_lock(&dev_priv->rps.hw_lock); |
1322 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1323 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1324 | |
c8c8fb33 PZ |
1325 | intel_runtime_pm_put(dev_priv); |
1326 | ||
4d85529d BW |
1327 | seq_printf(m, "Video Turbo Mode: %s\n", |
1328 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1329 | seq_printf(m, "HW control enabled: %s\n", | |
1330 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1331 | seq_printf(m, "SW control enabled: %s\n", | |
1332 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1333 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1334 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1335 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1336 | seq_printf(m, "RC6 Enabled: %s\n", | |
1337 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1338 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1339 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1340 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1341 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1342 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1343 | switch (gt_core_status & GEN6_RCn_MASK) { |
1344 | case GEN6_RC0: | |
1345 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1346 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1347 | else |
267f0c90 | 1348 | seq_puts(m, "on\n"); |
4d85529d BW |
1349 | break; |
1350 | case GEN6_RC3: | |
267f0c90 | 1351 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1352 | break; |
1353 | case GEN6_RC6: | |
267f0c90 | 1354 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1355 | break; |
1356 | case GEN6_RC7: | |
267f0c90 | 1357 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1358 | break; |
1359 | default: | |
267f0c90 | 1360 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1361 | break; |
1362 | } | |
1363 | ||
1364 | seq_printf(m, "Core Power Down: %s\n", | |
1365 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1366 | |
1367 | /* Not exactly sure what this is */ | |
1368 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1369 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1370 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1371 | I915_READ(GEN6_GT_GFX_RC6)); | |
1372 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1373 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1374 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1375 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1376 | ||
ecd8faea BW |
1377 | seq_printf(m, "RC6 voltage: %dmV\n", |
1378 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1379 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1380 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1381 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1382 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1383 | return 0; |
1384 | } | |
1385 | ||
1386 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1387 | { | |
1388 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1389 | struct drm_device *dev = node->minor->dev; | |
1390 | ||
669ab5aa D |
1391 | if (IS_VALLEYVIEW(dev)) |
1392 | return vlv_drpc_info(m); | |
1393 | else if (IS_GEN6(dev) || IS_GEN7(dev)) | |
4d85529d BW |
1394 | return gen6_drpc_info(m); |
1395 | else | |
1396 | return ironlake_drpc_info(m); | |
1397 | } | |
1398 | ||
b5e50c3f JB |
1399 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1400 | { | |
1401 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1402 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 1403 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1404 | |
3a77c4c4 | 1405 | if (!HAS_FBC(dev)) { |
267f0c90 | 1406 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1407 | return 0; |
1408 | } | |
1409 | ||
36623ef8 PZ |
1410 | intel_runtime_pm_get(dev_priv); |
1411 | ||
ee5382ae | 1412 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1413 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1414 | } else { |
267f0c90 | 1415 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1416 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1417 | case FBC_OK: |
1418 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1419 | break; | |
1420 | case FBC_UNSUPPORTED: | |
1421 | seq_puts(m, "unsupported by this chipset"); | |
1422 | break; | |
bed4a673 | 1423 | case FBC_NO_OUTPUT: |
267f0c90 | 1424 | seq_puts(m, "no outputs"); |
bed4a673 | 1425 | break; |
b5e50c3f | 1426 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1427 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1428 | break; |
1429 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1430 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1431 | break; |
1432 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1433 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1434 | break; |
1435 | case FBC_BAD_PLANE: | |
267f0c90 | 1436 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1437 | break; |
1438 | case FBC_NOT_TILED: | |
267f0c90 | 1439 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1440 | break; |
9c928d16 | 1441 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1442 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1443 | break; |
c1a9f047 | 1444 | case FBC_MODULE_PARAM: |
267f0c90 | 1445 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1446 | break; |
8a5729a3 | 1447 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1448 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1449 | break; |
b5e50c3f | 1450 | default: |
267f0c90 | 1451 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1452 | } |
267f0c90 | 1453 | seq_putc(m, '\n'); |
b5e50c3f | 1454 | } |
36623ef8 PZ |
1455 | |
1456 | intel_runtime_pm_put(dev_priv); | |
1457 | ||
b5e50c3f JB |
1458 | return 0; |
1459 | } | |
1460 | ||
92d44621 PZ |
1461 | static int i915_ips_status(struct seq_file *m, void *unused) |
1462 | { | |
1463 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1464 | struct drm_device *dev = node->minor->dev; | |
1465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1466 | ||
f5adf94e | 1467 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1468 | seq_puts(m, "not supported\n"); |
1469 | return 0; | |
1470 | } | |
1471 | ||
36623ef8 PZ |
1472 | intel_runtime_pm_get(dev_priv); |
1473 | ||
e59150dc | 1474 | if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE) |
92d44621 PZ |
1475 | seq_puts(m, "enabled\n"); |
1476 | else | |
1477 | seq_puts(m, "disabled\n"); | |
1478 | ||
36623ef8 PZ |
1479 | intel_runtime_pm_put(dev_priv); |
1480 | ||
92d44621 PZ |
1481 | return 0; |
1482 | } | |
1483 | ||
4a9bef37 JB |
1484 | static int i915_sr_status(struct seq_file *m, void *unused) |
1485 | { | |
1486 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1487 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 1488 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1489 | bool sr_enabled = false; |
1490 | ||
36623ef8 PZ |
1491 | intel_runtime_pm_get(dev_priv); |
1492 | ||
1398261a | 1493 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1494 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1495 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1496 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1497 | else if (IS_I915GM(dev)) | |
1498 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1499 | else if (IS_PINEVIEW(dev)) | |
1500 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1501 | ||
36623ef8 PZ |
1502 | intel_runtime_pm_put(dev_priv); |
1503 | ||
5ba2aaaa CW |
1504 | seq_printf(m, "self-refresh: %s\n", |
1505 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1506 | |
1507 | return 0; | |
1508 | } | |
1509 | ||
7648fa99 JB |
1510 | static int i915_emon_status(struct seq_file *m, void *unused) |
1511 | { | |
1512 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1513 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 1514 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1515 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1516 | int ret; |
1517 | ||
582be6b4 CW |
1518 | if (!IS_GEN5(dev)) |
1519 | return -ENODEV; | |
1520 | ||
de227ef0 CW |
1521 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1522 | if (ret) | |
1523 | return ret; | |
7648fa99 JB |
1524 | |
1525 | temp = i915_mch_val(dev_priv); | |
1526 | chipset = i915_chipset_val(dev_priv); | |
1527 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1528 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1529 | |
1530 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1531 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1532 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1533 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1534 | ||
1535 | return 0; | |
1536 | } | |
1537 | ||
23b2f8bb JB |
1538 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1539 | { | |
1540 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1541 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 1542 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1543 | int ret = 0; |
23b2f8bb JB |
1544 | int gpu_freq, ia_freq; |
1545 | ||
1c70c0ce | 1546 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1547 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1548 | return 0; |
1549 | } | |
1550 | ||
5bfa0199 PZ |
1551 | intel_runtime_pm_get(dev_priv); |
1552 | ||
5c9669ce TR |
1553 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1554 | ||
4fc688ce | 1555 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1556 | if (ret) |
5bfa0199 | 1557 | goto out; |
23b2f8bb | 1558 | |
267f0c90 | 1559 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1560 | |
b39fb297 BW |
1561 | for (gpu_freq = dev_priv->rps.min_freq_softlimit; |
1562 | gpu_freq <= dev_priv->rps.max_freq_softlimit; | |
23b2f8bb | 1563 | gpu_freq++) { |
42c0526c BW |
1564 | ia_freq = gpu_freq; |
1565 | sandybridge_pcode_read(dev_priv, | |
1566 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1567 | &ia_freq); | |
3ebecd07 CW |
1568 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1569 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1570 | ((ia_freq >> 0) & 0xff) * 100, | |
1571 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1572 | } |
1573 | ||
4fc688ce | 1574 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1575 | |
5bfa0199 PZ |
1576 | out: |
1577 | intel_runtime_pm_put(dev_priv); | |
1578 | return ret; | |
23b2f8bb JB |
1579 | } |
1580 | ||
7648fa99 JB |
1581 | static int i915_gfxec(struct seq_file *m, void *unused) |
1582 | { | |
1583 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1584 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 1585 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1586 | int ret; |
1587 | ||
1588 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1589 | if (ret) | |
1590 | return ret; | |
c8c8fb33 | 1591 | intel_runtime_pm_get(dev_priv); |
7648fa99 JB |
1592 | |
1593 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
c8c8fb33 | 1594 | intel_runtime_pm_put(dev_priv); |
7648fa99 | 1595 | |
616fdb5a BW |
1596 | mutex_unlock(&dev->struct_mutex); |
1597 | ||
7648fa99 JB |
1598 | return 0; |
1599 | } | |
1600 | ||
44834a67 CW |
1601 | static int i915_opregion(struct seq_file *m, void *unused) |
1602 | { | |
1603 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1604 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 1605 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 | 1606 | struct intel_opregion *opregion = &dev_priv->opregion; |
0d38f009 | 1607 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1608 | int ret; |
1609 | ||
0d38f009 DV |
1610 | if (data == NULL) |
1611 | return -ENOMEM; | |
1612 | ||
44834a67 CW |
1613 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1614 | if (ret) | |
0d38f009 | 1615 | goto out; |
44834a67 | 1616 | |
0d38f009 DV |
1617 | if (opregion->header) { |
1618 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1619 | seq_write(m, data, OPREGION_SIZE); | |
1620 | } | |
44834a67 CW |
1621 | |
1622 | mutex_unlock(&dev->struct_mutex); | |
1623 | ||
0d38f009 DV |
1624 | out: |
1625 | kfree(data); | |
44834a67 CW |
1626 | return 0; |
1627 | } | |
1628 | ||
37811fcc CW |
1629 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1630 | { | |
1631 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1632 | struct drm_device *dev = node->minor->dev; | |
4520f53a | 1633 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1634 | struct intel_framebuffer *fb; |
37811fcc | 1635 | |
4520f53a DV |
1636 | #ifdef CONFIG_DRM_I915_FBDEV |
1637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1638 | int ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
37811fcc CW |
1639 | if (ret) |
1640 | return ret; | |
1641 | ||
1642 | ifbdev = dev_priv->fbdev; | |
1643 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1644 | ||
623f9783 | 1645 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1646 | fb->base.width, |
1647 | fb->base.height, | |
1648 | fb->base.depth, | |
623f9783 DV |
1649 | fb->base.bits_per_pixel, |
1650 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1651 | describe_obj(m, fb->obj); |
267f0c90 | 1652 | seq_putc(m, '\n'); |
4b096ac1 | 1653 | mutex_unlock(&dev->mode_config.mutex); |
4520f53a | 1654 | #endif |
37811fcc | 1655 | |
4b096ac1 | 1656 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc | 1657 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
131a56dc | 1658 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
37811fcc CW |
1659 | continue; |
1660 | ||
623f9783 | 1661 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1662 | fb->base.width, |
1663 | fb->base.height, | |
1664 | fb->base.depth, | |
623f9783 DV |
1665 | fb->base.bits_per_pixel, |
1666 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1667 | describe_obj(m, fb->obj); |
267f0c90 | 1668 | seq_putc(m, '\n'); |
37811fcc | 1669 | } |
4b096ac1 | 1670 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1671 | |
1672 | return 0; | |
1673 | } | |
1674 | ||
e76d3630 BW |
1675 | static int i915_context_status(struct seq_file *m, void *unused) |
1676 | { | |
1677 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1678 | struct drm_device *dev = node->minor->dev; | |
e277a1f8 | 1679 | struct drm_i915_private *dev_priv = dev->dev_private; |
a168c293 | 1680 | struct intel_ring_buffer *ring; |
a33afea5 | 1681 | struct i915_hw_context *ctx; |
a168c293 | 1682 | int ret, i; |
e76d3630 BW |
1683 | |
1684 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1685 | if (ret) | |
1686 | return ret; | |
1687 | ||
3e373948 | 1688 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1689 | seq_puts(m, "power context "); |
3e373948 | 1690 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1691 | seq_putc(m, '\n'); |
dc501fbc | 1692 | } |
e76d3630 | 1693 | |
3e373948 | 1694 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1695 | seq_puts(m, "render context "); |
3e373948 | 1696 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1697 | seq_putc(m, '\n'); |
dc501fbc | 1698 | } |
e76d3630 | 1699 | |
a33afea5 | 1700 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
b77f6997 CW |
1701 | if (ctx->obj == NULL) |
1702 | continue; | |
1703 | ||
a33afea5 | 1704 | seq_puts(m, "HW context "); |
3ccfd19d | 1705 | describe_ctx(m, ctx); |
a33afea5 BW |
1706 | for_each_ring(ring, dev_priv, i) |
1707 | if (ring->default_context == ctx) | |
1708 | seq_printf(m, "(default context %s) ", ring->name); | |
1709 | ||
1710 | describe_obj(m, ctx->obj); | |
1711 | seq_putc(m, '\n'); | |
a168c293 BW |
1712 | } |
1713 | ||
e76d3630 BW |
1714 | mutex_unlock(&dev->mode_config.mutex); |
1715 | ||
1716 | return 0; | |
1717 | } | |
1718 | ||
6d794d42 BW |
1719 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1720 | { | |
1721 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1722 | struct drm_device *dev = node->minor->dev; | |
1723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43709ba0 | 1724 | unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0; |
6d794d42 | 1725 | |
907b28c5 | 1726 | spin_lock_irq(&dev_priv->uncore.lock); |
43709ba0 D |
1727 | if (IS_VALLEYVIEW(dev)) { |
1728 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1729 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1730 | } else | |
1731 | forcewake_count = dev_priv->uncore.forcewake_count; | |
907b28c5 | 1732 | spin_unlock_irq(&dev_priv->uncore.lock); |
6d794d42 | 1733 | |
43709ba0 D |
1734 | if (IS_VALLEYVIEW(dev)) { |
1735 | seq_printf(m, "fw_rendercount = %u\n", fw_rendercount); | |
1736 | seq_printf(m, "fw_mediacount = %u\n", fw_mediacount); | |
1737 | } else | |
1738 | seq_printf(m, "forcewake count = %u\n", forcewake_count); | |
6d794d42 BW |
1739 | |
1740 | return 0; | |
1741 | } | |
1742 | ||
ea16a3cd DV |
1743 | static const char *swizzle_string(unsigned swizzle) |
1744 | { | |
aee56cff | 1745 | switch (swizzle) { |
ea16a3cd DV |
1746 | case I915_BIT_6_SWIZZLE_NONE: |
1747 | return "none"; | |
1748 | case I915_BIT_6_SWIZZLE_9: | |
1749 | return "bit9"; | |
1750 | case I915_BIT_6_SWIZZLE_9_10: | |
1751 | return "bit9/bit10"; | |
1752 | case I915_BIT_6_SWIZZLE_9_11: | |
1753 | return "bit9/bit11"; | |
1754 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1755 | return "bit9/bit10/bit11"; | |
1756 | case I915_BIT_6_SWIZZLE_9_17: | |
1757 | return "bit9/bit17"; | |
1758 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1759 | return "bit9/bit10/bit17"; | |
1760 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1761 | return "unknown"; |
ea16a3cd DV |
1762 | } |
1763 | ||
1764 | return "bug"; | |
1765 | } | |
1766 | ||
1767 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1768 | { | |
1769 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1770 | struct drm_device *dev = node->minor->dev; | |
1771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1772 | int ret; |
1773 | ||
1774 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1775 | if (ret) | |
1776 | return ret; | |
c8c8fb33 | 1777 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 1778 | |
ea16a3cd DV |
1779 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1780 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1781 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1782 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1783 | ||
1784 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1785 | seq_printf(m, "DDC = 0x%08x\n", | |
1786 | I915_READ(DCC)); | |
1787 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1788 | I915_READ16(C0DRB3)); | |
1789 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1790 | I915_READ16(C1DRB3)); | |
9d3203e1 | 1791 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
1792 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
1793 | I915_READ(MAD_DIMM_C0)); | |
1794 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1795 | I915_READ(MAD_DIMM_C1)); | |
1796 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1797 | I915_READ(MAD_DIMM_C2)); | |
1798 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1799 | I915_READ(TILECTL)); | |
9d3203e1 BW |
1800 | if (IS_GEN8(dev)) |
1801 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", | |
1802 | I915_READ(GAMTARBMODE)); | |
1803 | else | |
1804 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1805 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
1806 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
1807 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 1808 | } |
c8c8fb33 | 1809 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
1810 | mutex_unlock(&dev->struct_mutex); |
1811 | ||
1812 | return 0; | |
1813 | } | |
1814 | ||
1c60fef5 BW |
1815 | static int per_file_ctx(int id, void *ptr, void *data) |
1816 | { | |
1817 | struct i915_hw_context *ctx = ptr; | |
1818 | struct seq_file *m = data; | |
1819 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx); | |
1820 | ||
1821 | ppgtt->debug_dump(ppgtt, m); | |
1822 | ||
1823 | return 0; | |
1824 | } | |
1825 | ||
77df6772 | 1826 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 1827 | { |
3cf17fc5 DV |
1828 | struct drm_i915_private *dev_priv = dev->dev_private; |
1829 | struct intel_ring_buffer *ring; | |
77df6772 BW |
1830 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1831 | int unused, i; | |
3cf17fc5 | 1832 | |
77df6772 BW |
1833 | if (!ppgtt) |
1834 | return; | |
1835 | ||
1836 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); | |
5abbcca3 | 1837 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); |
77df6772 BW |
1838 | for_each_ring(ring, dev_priv, unused) { |
1839 | seq_printf(m, "%s\n", ring->name); | |
1840 | for (i = 0; i < 4; i++) { | |
1841 | u32 offset = 0x270 + i * 8; | |
1842 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); | |
1843 | pdp <<= 32; | |
1844 | pdp |= I915_READ(ring->mmio_base + offset); | |
a2a5b15c | 1845 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
1846 | } |
1847 | } | |
1848 | } | |
1849 | ||
1850 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
1851 | { | |
1852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1853 | struct intel_ring_buffer *ring; | |
1c60fef5 | 1854 | struct drm_file *file; |
77df6772 | 1855 | int i; |
3cf17fc5 | 1856 | |
3cf17fc5 DV |
1857 | if (INTEL_INFO(dev)->gen == 6) |
1858 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1859 | ||
a2c7f6fd | 1860 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1861 | seq_printf(m, "%s\n", ring->name); |
1862 | if (INTEL_INFO(dev)->gen == 7) | |
1863 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1864 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1865 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1866 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1867 | } | |
1868 | if (dev_priv->mm.aliasing_ppgtt) { | |
1869 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1870 | ||
267f0c90 | 1871 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 | 1872 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1c60fef5 | 1873 | |
87d60b63 | 1874 | ppgtt->debug_dump(ppgtt, m); |
1c60fef5 BW |
1875 | } else |
1876 | return; | |
1877 | ||
1878 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { | |
1879 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1880 | struct i915_hw_ppgtt *pvt_ppgtt; | |
1881 | ||
1882 | pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx); | |
1883 | seq_printf(m, "proc: %s\n", | |
1884 | get_pid_task(file->pid, PIDTYPE_PID)->comm); | |
1885 | seq_puts(m, " default context:\n"); | |
1886 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); | |
3cf17fc5 DV |
1887 | } |
1888 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
77df6772 BW |
1889 | } |
1890 | ||
1891 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
1892 | { | |
1893 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1894 | struct drm_device *dev = node->minor->dev; | |
c8c8fb33 | 1895 | struct drm_i915_private *dev_priv = dev->dev_private; |
77df6772 BW |
1896 | |
1897 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1898 | if (ret) | |
1899 | return ret; | |
c8c8fb33 | 1900 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
1901 | |
1902 | if (INTEL_INFO(dev)->gen >= 8) | |
1903 | gen8_ppgtt_info(m, dev); | |
1904 | else if (INTEL_INFO(dev)->gen >= 6) | |
1905 | gen6_ppgtt_info(m, dev); | |
1906 | ||
c8c8fb33 | 1907 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
1908 | mutex_unlock(&dev->struct_mutex); |
1909 | ||
1910 | return 0; | |
1911 | } | |
1912 | ||
63573eb7 BW |
1913 | static int i915_llc(struct seq_file *m, void *data) |
1914 | { | |
1915 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1916 | struct drm_device *dev = node->minor->dev; | |
1917 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1918 | ||
1919 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1920 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1921 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1922 | ||
1923 | return 0; | |
1924 | } | |
1925 | ||
e91fd8c6 RV |
1926 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1927 | { | |
1928 | struct drm_info_node *node = m->private; | |
1929 | struct drm_device *dev = node->minor->dev; | |
1930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1931 | u32 psrperf = 0; |
1932 | bool enabled = false; | |
e91fd8c6 | 1933 | |
c8c8fb33 PZ |
1934 | intel_runtime_pm_get(dev_priv); |
1935 | ||
a031d709 RV |
1936 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1937 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
e91fd8c6 | 1938 | |
a031d709 RV |
1939 | enabled = HAS_PSR(dev) && |
1940 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
1941 | seq_printf(m, "Enabled: %s\n", yesno(enabled)); | |
e91fd8c6 | 1942 | |
a031d709 RV |
1943 | if (HAS_PSR(dev)) |
1944 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1945 | EDP_PSR_PERF_CNT_MASK; | |
1946 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
e91fd8c6 | 1947 | |
c8c8fb33 | 1948 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
1949 | return 0; |
1950 | } | |
1951 | ||
d2e216d0 RV |
1952 | static int i915_sink_crc(struct seq_file *m, void *data) |
1953 | { | |
1954 | struct drm_info_node *node = m->private; | |
1955 | struct drm_device *dev = node->minor->dev; | |
1956 | struct intel_encoder *encoder; | |
1957 | struct intel_connector *connector; | |
1958 | struct intel_dp *intel_dp = NULL; | |
1959 | int ret; | |
1960 | u8 crc[6]; | |
1961 | ||
1962 | drm_modeset_lock_all(dev); | |
1963 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
1964 | base.head) { | |
1965 | ||
1966 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
1967 | continue; | |
1968 | ||
b6ae3c7c PZ |
1969 | if (!connector->base.encoder) |
1970 | continue; | |
1971 | ||
d2e216d0 RV |
1972 | encoder = to_intel_encoder(connector->base.encoder); |
1973 | if (encoder->type != INTEL_OUTPUT_EDP) | |
1974 | continue; | |
1975 | ||
1976 | intel_dp = enc_to_intel_dp(&encoder->base); | |
1977 | ||
1978 | ret = intel_dp_sink_crc(intel_dp, crc); | |
1979 | if (ret) | |
1980 | goto out; | |
1981 | ||
1982 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
1983 | crc[0], crc[1], crc[2], | |
1984 | crc[3], crc[4], crc[5]); | |
1985 | goto out; | |
1986 | } | |
1987 | ret = -ENODEV; | |
1988 | out: | |
1989 | drm_modeset_unlock_all(dev); | |
1990 | return ret; | |
1991 | } | |
1992 | ||
ec013e7f JB |
1993 | static int i915_energy_uJ(struct seq_file *m, void *data) |
1994 | { | |
1995 | struct drm_info_node *node = m->private; | |
1996 | struct drm_device *dev = node->minor->dev; | |
1997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1998 | u64 power; | |
1999 | u32 units; | |
2000 | ||
2001 | if (INTEL_INFO(dev)->gen < 6) | |
2002 | return -ENODEV; | |
2003 | ||
36623ef8 PZ |
2004 | intel_runtime_pm_get(dev_priv); |
2005 | ||
ec013e7f JB |
2006 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2007 | power = (power & 0x1f00) >> 8; | |
2008 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2009 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2010 | power *= units; | |
2011 | ||
36623ef8 PZ |
2012 | intel_runtime_pm_put(dev_priv); |
2013 | ||
ec013e7f | 2014 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2015 | |
2016 | return 0; | |
2017 | } | |
2018 | ||
2019 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
2020 | { | |
2021 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2022 | struct drm_device *dev = node->minor->dev; | |
2023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2024 | ||
85b8d5c2 | 2025 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
371db66a PZ |
2026 | seq_puts(m, "not supported\n"); |
2027 | return 0; | |
2028 | } | |
2029 | ||
86c4ec0d | 2030 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2031 | seq_printf(m, "IRQs disabled: %s\n", |
5d584b2e | 2032 | yesno(dev_priv->pm.irqs_disabled)); |
371db66a | 2033 | |
ec013e7f JB |
2034 | return 0; |
2035 | } | |
2036 | ||
1da51581 ID |
2037 | static const char *power_domain_str(enum intel_display_power_domain domain) |
2038 | { | |
2039 | switch (domain) { | |
2040 | case POWER_DOMAIN_PIPE_A: | |
2041 | return "PIPE_A"; | |
2042 | case POWER_DOMAIN_PIPE_B: | |
2043 | return "PIPE_B"; | |
2044 | case POWER_DOMAIN_PIPE_C: | |
2045 | return "PIPE_C"; | |
2046 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
2047 | return "PIPE_A_PANEL_FITTER"; | |
2048 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
2049 | return "PIPE_B_PANEL_FITTER"; | |
2050 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
2051 | return "PIPE_C_PANEL_FITTER"; | |
2052 | case POWER_DOMAIN_TRANSCODER_A: | |
2053 | return "TRANSCODER_A"; | |
2054 | case POWER_DOMAIN_TRANSCODER_B: | |
2055 | return "TRANSCODER_B"; | |
2056 | case POWER_DOMAIN_TRANSCODER_C: | |
2057 | return "TRANSCODER_C"; | |
2058 | case POWER_DOMAIN_TRANSCODER_EDP: | |
2059 | return "TRANSCODER_EDP"; | |
319be8ae ID |
2060 | case POWER_DOMAIN_PORT_DDI_A_2_LANES: |
2061 | return "PORT_DDI_A_2_LANES"; | |
2062 | case POWER_DOMAIN_PORT_DDI_A_4_LANES: | |
2063 | return "PORT_DDI_A_4_LANES"; | |
2064 | case POWER_DOMAIN_PORT_DDI_B_2_LANES: | |
2065 | return "PORT_DDI_B_2_LANES"; | |
2066 | case POWER_DOMAIN_PORT_DDI_B_4_LANES: | |
2067 | return "PORT_DDI_B_4_LANES"; | |
2068 | case POWER_DOMAIN_PORT_DDI_C_2_LANES: | |
2069 | return "PORT_DDI_C_2_LANES"; | |
2070 | case POWER_DOMAIN_PORT_DDI_C_4_LANES: | |
2071 | return "PORT_DDI_C_4_LANES"; | |
2072 | case POWER_DOMAIN_PORT_DDI_D_2_LANES: | |
2073 | return "PORT_DDI_D_2_LANES"; | |
2074 | case POWER_DOMAIN_PORT_DDI_D_4_LANES: | |
2075 | return "PORT_DDI_D_4_LANES"; | |
2076 | case POWER_DOMAIN_PORT_DSI: | |
2077 | return "PORT_DSI"; | |
2078 | case POWER_DOMAIN_PORT_CRT: | |
2079 | return "PORT_CRT"; | |
2080 | case POWER_DOMAIN_PORT_OTHER: | |
2081 | return "PORT_OTHER"; | |
1da51581 ID |
2082 | case POWER_DOMAIN_VGA: |
2083 | return "VGA"; | |
2084 | case POWER_DOMAIN_AUDIO: | |
2085 | return "AUDIO"; | |
2086 | case POWER_DOMAIN_INIT: | |
2087 | return "INIT"; | |
2088 | default: | |
2089 | WARN_ON(1); | |
2090 | return "?"; | |
2091 | } | |
2092 | } | |
2093 | ||
2094 | static int i915_power_domain_info(struct seq_file *m, void *unused) | |
2095 | { | |
2096 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2097 | struct drm_device *dev = node->minor->dev; | |
2098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2099 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2100 | int i; | |
2101 | ||
2102 | mutex_lock(&power_domains->lock); | |
2103 | ||
2104 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2105 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2106 | struct i915_power_well *power_well; | |
2107 | enum intel_display_power_domain power_domain; | |
2108 | ||
2109 | power_well = &power_domains->power_wells[i]; | |
2110 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2111 | power_well->count); | |
2112 | ||
2113 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2114 | power_domain++) { | |
2115 | if (!(BIT(power_domain) & power_well->domains)) | |
2116 | continue; | |
2117 | ||
2118 | seq_printf(m, " %-23s %d\n", | |
2119 | power_domain_str(power_domain), | |
2120 | power_domains->domain_use_count[power_domain]); | |
2121 | } | |
2122 | } | |
2123 | ||
2124 | mutex_unlock(&power_domains->lock); | |
2125 | ||
2126 | return 0; | |
2127 | } | |
2128 | ||
53f5e3ca JB |
2129 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2130 | struct drm_display_mode *mode) | |
2131 | { | |
2132 | int i; | |
2133 | ||
2134 | for (i = 0; i < tabs; i++) | |
2135 | seq_putc(m, '\t'); | |
2136 | ||
2137 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2138 | mode->base.id, mode->name, | |
2139 | mode->vrefresh, mode->clock, | |
2140 | mode->hdisplay, mode->hsync_start, | |
2141 | mode->hsync_end, mode->htotal, | |
2142 | mode->vdisplay, mode->vsync_start, | |
2143 | mode->vsync_end, mode->vtotal, | |
2144 | mode->type, mode->flags); | |
2145 | } | |
2146 | ||
2147 | static void intel_encoder_info(struct seq_file *m, | |
2148 | struct intel_crtc *intel_crtc, | |
2149 | struct intel_encoder *intel_encoder) | |
2150 | { | |
2151 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2152 | struct drm_device *dev = node->minor->dev; | |
2153 | struct drm_crtc *crtc = &intel_crtc->base; | |
2154 | struct intel_connector *intel_connector; | |
2155 | struct drm_encoder *encoder; | |
2156 | ||
2157 | encoder = &intel_encoder->base; | |
2158 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
2159 | encoder->base.id, drm_get_encoder_name(encoder)); | |
2160 | for_each_connector_on_encoder(dev, encoder, intel_connector) { | |
2161 | struct drm_connector *connector = &intel_connector->base; | |
2162 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2163 | connector->base.id, | |
2164 | drm_get_connector_name(connector), | |
2165 | drm_get_connector_status_name(connector->status)); | |
2166 | if (connector->status == connector_status_connected) { | |
2167 | struct drm_display_mode *mode = &crtc->mode; | |
2168 | seq_printf(m, ", mode:\n"); | |
2169 | intel_seq_print_mode(m, 2, mode); | |
2170 | } else { | |
2171 | seq_putc(m, '\n'); | |
2172 | } | |
2173 | } | |
2174 | } | |
2175 | ||
2176 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2177 | { | |
2178 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2179 | struct drm_device *dev = node->minor->dev; | |
2180 | struct drm_crtc *crtc = &intel_crtc->base; | |
2181 | struct intel_encoder *intel_encoder; | |
2182 | ||
2183 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", | |
f4510a27 MR |
2184 | crtc->primary->fb->base.id, crtc->x, crtc->y, |
2185 | crtc->primary->fb->width, crtc->primary->fb->height); | |
53f5e3ca JB |
2186 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2187 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2188 | } | |
2189 | ||
2190 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2191 | { | |
2192 | struct drm_display_mode *mode = panel->fixed_mode; | |
2193 | ||
2194 | seq_printf(m, "\tfixed mode:\n"); | |
2195 | intel_seq_print_mode(m, 2, mode); | |
2196 | } | |
2197 | ||
2198 | static void intel_dp_info(struct seq_file *m, | |
2199 | struct intel_connector *intel_connector) | |
2200 | { | |
2201 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2202 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2203 | ||
2204 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
2205 | seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : | |
2206 | "no"); | |
2207 | if (intel_encoder->type == INTEL_OUTPUT_EDP) | |
2208 | intel_panel_info(m, &intel_connector->panel); | |
2209 | } | |
2210 | ||
2211 | static void intel_hdmi_info(struct seq_file *m, | |
2212 | struct intel_connector *intel_connector) | |
2213 | { | |
2214 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2215 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2216 | ||
2217 | seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : | |
2218 | "no"); | |
2219 | } | |
2220 | ||
2221 | static void intel_lvds_info(struct seq_file *m, | |
2222 | struct intel_connector *intel_connector) | |
2223 | { | |
2224 | intel_panel_info(m, &intel_connector->panel); | |
2225 | } | |
2226 | ||
2227 | static void intel_connector_info(struct seq_file *m, | |
2228 | struct drm_connector *connector) | |
2229 | { | |
2230 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2231 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2232 | struct drm_display_mode *mode; |
53f5e3ca JB |
2233 | |
2234 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
2235 | connector->base.id, drm_get_connector_name(connector), | |
2236 | drm_get_connector_status_name(connector->status)); | |
2237 | if (connector->status == connector_status_connected) { | |
2238 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2239 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2240 | connector->display_info.width_mm, | |
2241 | connector->display_info.height_mm); | |
2242 | seq_printf(m, "\tsubpixel order: %s\n", | |
2243 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2244 | seq_printf(m, "\tCEA rev: %d\n", | |
2245 | connector->display_info.cea_rev); | |
2246 | } | |
2247 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2248 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2249 | intel_dp_info(m, intel_connector); | |
2250 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2251 | intel_hdmi_info(m, intel_connector); | |
2252 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2253 | intel_lvds_info(m, intel_connector); | |
2254 | ||
f103fc7d JB |
2255 | seq_printf(m, "\tmodes:\n"); |
2256 | list_for_each_entry(mode, &connector->modes, head) | |
2257 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2258 | } |
2259 | ||
065f2ec2 CW |
2260 | static bool cursor_active(struct drm_device *dev, int pipe) |
2261 | { | |
2262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2263 | u32 state; | |
2264 | ||
2265 | if (IS_845G(dev) || IS_I865G(dev)) | |
2266 | state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
2267 | else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) | |
2268 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
2269 | else | |
2270 | state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
2271 | ||
2272 | return state; | |
2273 | } | |
2274 | ||
2275 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2276 | { | |
2277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2278 | u32 pos; | |
2279 | ||
2280 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2281 | pos = I915_READ(CURPOS_IVB(pipe)); | |
2282 | else | |
2283 | pos = I915_READ(CURPOS(pipe)); | |
2284 | ||
2285 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2286 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2287 | *x = -*x; | |
2288 | ||
2289 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2290 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2291 | *y = -*y; | |
2292 | ||
2293 | return cursor_active(dev, pipe); | |
2294 | } | |
2295 | ||
53f5e3ca JB |
2296 | static int i915_display_info(struct seq_file *m, void *unused) |
2297 | { | |
2298 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2299 | struct drm_device *dev = node->minor->dev; | |
b0e5ddf3 | 2300 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 2301 | struct intel_crtc *crtc; |
53f5e3ca JB |
2302 | struct drm_connector *connector; |
2303 | ||
b0e5ddf3 | 2304 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
2305 | drm_modeset_lock_all(dev); |
2306 | seq_printf(m, "CRTC info\n"); | |
2307 | seq_printf(m, "---------\n"); | |
065f2ec2 CW |
2308 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
2309 | bool active; | |
2310 | int x, y; | |
53f5e3ca JB |
2311 | |
2312 | seq_printf(m, "CRTC %d: pipe: %c, active: %s\n", | |
065f2ec2 CW |
2313 | crtc->base.base.id, pipe_name(crtc->pipe), |
2314 | yesno(crtc->active)); | |
a23dc658 | 2315 | if (crtc->active) { |
065f2ec2 CW |
2316 | intel_crtc_info(m, crtc); |
2317 | ||
a23dc658 PZ |
2318 | active = cursor_position(dev, crtc->pipe, &x, &y); |
2319 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n", | |
2320 | yesno(crtc->cursor_visible), | |
2321 | x, y, crtc->cursor_addr, | |
2322 | yesno(active)); | |
2323 | } | |
53f5e3ca JB |
2324 | } |
2325 | ||
2326 | seq_printf(m, "\n"); | |
2327 | seq_printf(m, "Connector info\n"); | |
2328 | seq_printf(m, "--------------\n"); | |
2329 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2330 | intel_connector_info(m, connector); | |
2331 | } | |
2332 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 2333 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
2334 | |
2335 | return 0; | |
2336 | } | |
2337 | ||
07144428 DL |
2338 | struct pipe_crc_info { |
2339 | const char *name; | |
2340 | struct drm_device *dev; | |
2341 | enum pipe pipe; | |
2342 | }; | |
2343 | ||
2344 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) | |
2345 | { | |
be5c7a90 DL |
2346 | struct pipe_crc_info *info = inode->i_private; |
2347 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2348 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2349 | ||
7eb1c496 DV |
2350 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
2351 | return -ENODEV; | |
2352 | ||
d538bbdf DL |
2353 | spin_lock_irq(&pipe_crc->lock); |
2354 | ||
2355 | if (pipe_crc->opened) { | |
2356 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
2357 | return -EBUSY; /* already open */ |
2358 | } | |
2359 | ||
d538bbdf | 2360 | pipe_crc->opened = true; |
07144428 DL |
2361 | filep->private_data = inode->i_private; |
2362 | ||
d538bbdf DL |
2363 | spin_unlock_irq(&pipe_crc->lock); |
2364 | ||
07144428 DL |
2365 | return 0; |
2366 | } | |
2367 | ||
2368 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
2369 | { | |
be5c7a90 DL |
2370 | struct pipe_crc_info *info = inode->i_private; |
2371 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2372 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2373 | ||
d538bbdf DL |
2374 | spin_lock_irq(&pipe_crc->lock); |
2375 | pipe_crc->opened = false; | |
2376 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 2377 | |
07144428 DL |
2378 | return 0; |
2379 | } | |
2380 | ||
2381 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
2382 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
2383 | /* account for \'0' */ | |
2384 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
2385 | ||
2386 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 2387 | { |
d538bbdf DL |
2388 | assert_spin_locked(&pipe_crc->lock); |
2389 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
2390 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
2391 | } |
2392 | ||
2393 | static ssize_t | |
2394 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
2395 | loff_t *pos) | |
2396 | { | |
2397 | struct pipe_crc_info *info = filep->private_data; | |
2398 | struct drm_device *dev = info->dev; | |
2399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2400 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2401 | char buf[PIPE_CRC_BUFFER_LEN]; | |
2402 | int head, tail, n_entries, n; | |
2403 | ssize_t bytes_read; | |
2404 | ||
2405 | /* | |
2406 | * Don't allow user space to provide buffers not big enough to hold | |
2407 | * a line of data. | |
2408 | */ | |
2409 | if (count < PIPE_CRC_LINE_LEN) | |
2410 | return -EINVAL; | |
2411 | ||
2412 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 2413 | return 0; |
07144428 DL |
2414 | |
2415 | /* nothing to read */ | |
d538bbdf | 2416 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 2417 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
2418 | int ret; |
2419 | ||
2420 | if (filep->f_flags & O_NONBLOCK) { | |
2421 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 2422 | return -EAGAIN; |
d538bbdf | 2423 | } |
07144428 | 2424 | |
d538bbdf DL |
2425 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
2426 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
2427 | if (ret) { | |
2428 | spin_unlock_irq(&pipe_crc->lock); | |
2429 | return ret; | |
2430 | } | |
8bf1e9f1 SH |
2431 | } |
2432 | ||
07144428 | 2433 | /* We now have one or more entries to read */ |
d538bbdf DL |
2434 | head = pipe_crc->head; |
2435 | tail = pipe_crc->tail; | |
07144428 DL |
2436 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
2437 | count / PIPE_CRC_LINE_LEN); | |
d538bbdf DL |
2438 | spin_unlock_irq(&pipe_crc->lock); |
2439 | ||
07144428 DL |
2440 | bytes_read = 0; |
2441 | n = 0; | |
2442 | do { | |
b2c88f5b | 2443 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
07144428 | 2444 | int ret; |
8bf1e9f1 | 2445 | |
07144428 DL |
2446 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
2447 | "%8u %8x %8x %8x %8x %8x\n", | |
2448 | entry->frame, entry->crc[0], | |
2449 | entry->crc[1], entry->crc[2], | |
2450 | entry->crc[3], entry->crc[4]); | |
2451 | ||
2452 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, | |
2453 | buf, PIPE_CRC_LINE_LEN); | |
2454 | if (ret == PIPE_CRC_LINE_LEN) | |
2455 | return -EFAULT; | |
b2c88f5b DL |
2456 | |
2457 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
2458 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
07144428 DL |
2459 | n++; |
2460 | } while (--n_entries); | |
8bf1e9f1 | 2461 | |
d538bbdf DL |
2462 | spin_lock_irq(&pipe_crc->lock); |
2463 | pipe_crc->tail = tail; | |
2464 | spin_unlock_irq(&pipe_crc->lock); | |
2465 | ||
07144428 DL |
2466 | return bytes_read; |
2467 | } | |
2468 | ||
2469 | static const struct file_operations i915_pipe_crc_fops = { | |
2470 | .owner = THIS_MODULE, | |
2471 | .open = i915_pipe_crc_open, | |
2472 | .read = i915_pipe_crc_read, | |
2473 | .release = i915_pipe_crc_release, | |
2474 | }; | |
2475 | ||
2476 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
2477 | { | |
2478 | .name = "i915_pipe_A_crc", | |
2479 | .pipe = PIPE_A, | |
2480 | }, | |
2481 | { | |
2482 | .name = "i915_pipe_B_crc", | |
2483 | .pipe = PIPE_B, | |
2484 | }, | |
2485 | { | |
2486 | .name = "i915_pipe_C_crc", | |
2487 | .pipe = PIPE_C, | |
2488 | }, | |
2489 | }; | |
2490 | ||
2491 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
2492 | enum pipe pipe) | |
2493 | { | |
2494 | struct drm_device *dev = minor->dev; | |
2495 | struct dentry *ent; | |
2496 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
2497 | ||
2498 | info->dev = dev; | |
2499 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
2500 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
2501 | if (!ent) |
2502 | return -ENOMEM; | |
07144428 DL |
2503 | |
2504 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
2505 | } |
2506 | ||
e8dfcf78 | 2507 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
2508 | "none", |
2509 | "plane1", | |
2510 | "plane2", | |
2511 | "pf", | |
5b3a856b | 2512 | "pipe", |
3d099a05 DV |
2513 | "TV", |
2514 | "DP-B", | |
2515 | "DP-C", | |
2516 | "DP-D", | |
46a19188 | 2517 | "auto", |
926321d5 DV |
2518 | }; |
2519 | ||
2520 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
2521 | { | |
2522 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
2523 | return pipe_crc_sources[source]; | |
2524 | } | |
2525 | ||
bd9db02f | 2526 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
2527 | { |
2528 | struct drm_device *dev = m->private; | |
2529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2530 | int i; | |
2531 | ||
2532 | for (i = 0; i < I915_MAX_PIPES; i++) | |
2533 | seq_printf(m, "%c %s\n", pipe_name(i), | |
2534 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
2535 | ||
2536 | return 0; | |
2537 | } | |
2538 | ||
bd9db02f | 2539 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
2540 | { |
2541 | struct drm_device *dev = inode->i_private; | |
2542 | ||
bd9db02f | 2543 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
2544 | } |
2545 | ||
46a19188 | 2546 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
2547 | uint32_t *val) |
2548 | { | |
46a19188 DV |
2549 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2550 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2551 | ||
2552 | switch (*source) { | |
52f843f6 DV |
2553 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2554 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
2555 | break; | |
2556 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2557 | *val = 0; | |
2558 | break; | |
2559 | default: | |
2560 | return -EINVAL; | |
2561 | } | |
2562 | ||
2563 | return 0; | |
2564 | } | |
2565 | ||
46a19188 DV |
2566 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
2567 | enum intel_pipe_crc_source *source) | |
2568 | { | |
2569 | struct intel_encoder *encoder; | |
2570 | struct intel_crtc *crtc; | |
26756809 | 2571 | struct intel_digital_port *dig_port; |
46a19188 DV |
2572 | int ret = 0; |
2573 | ||
2574 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2575 | ||
2576 | mutex_lock(&dev->mode_config.mutex); | |
2577 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
2578 | base.head) { | |
2579 | if (!encoder->base.crtc) | |
2580 | continue; | |
2581 | ||
2582 | crtc = to_intel_crtc(encoder->base.crtc); | |
2583 | ||
2584 | if (crtc->pipe != pipe) | |
2585 | continue; | |
2586 | ||
2587 | switch (encoder->type) { | |
2588 | case INTEL_OUTPUT_TVOUT: | |
2589 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
2590 | break; | |
2591 | case INTEL_OUTPUT_DISPLAYPORT: | |
2592 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
2593 | dig_port = enc_to_dig_port(&encoder->base); |
2594 | switch (dig_port->port) { | |
2595 | case PORT_B: | |
2596 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
2597 | break; | |
2598 | case PORT_C: | |
2599 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
2600 | break; | |
2601 | case PORT_D: | |
2602 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
2603 | break; | |
2604 | default: | |
2605 | WARN(1, "nonexisting DP port %c\n", | |
2606 | port_name(dig_port->port)); | |
2607 | break; | |
2608 | } | |
46a19188 DV |
2609 | break; |
2610 | } | |
2611 | } | |
2612 | mutex_unlock(&dev->mode_config.mutex); | |
2613 | ||
2614 | return ret; | |
2615 | } | |
2616 | ||
2617 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
2618 | enum pipe pipe, | |
2619 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
2620 | uint32_t *val) |
2621 | { | |
8d2f24ca DV |
2622 | struct drm_i915_private *dev_priv = dev->dev_private; |
2623 | bool need_stable_symbols = false; | |
2624 | ||
46a19188 DV |
2625 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2626 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2627 | if (ret) | |
2628 | return ret; | |
2629 | } | |
2630 | ||
2631 | switch (*source) { | |
7ac0129b DV |
2632 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2633 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
2634 | break; | |
2635 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2636 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 2637 | need_stable_symbols = true; |
7ac0129b DV |
2638 | break; |
2639 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2640 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 2641 | need_stable_symbols = true; |
7ac0129b DV |
2642 | break; |
2643 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2644 | *val = 0; | |
2645 | break; | |
2646 | default: | |
2647 | return -EINVAL; | |
2648 | } | |
2649 | ||
8d2f24ca DV |
2650 | /* |
2651 | * When the pipe CRC tap point is after the transcoders we need | |
2652 | * to tweak symbol-level features to produce a deterministic series of | |
2653 | * symbols for a given frame. We need to reset those features only once | |
2654 | * a frame (instead of every nth symbol): | |
2655 | * - DC-balance: used to ensure a better clock recovery from the data | |
2656 | * link (SDVO) | |
2657 | * - DisplayPort scrambling: used for EMI reduction | |
2658 | */ | |
2659 | if (need_stable_symbols) { | |
2660 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2661 | ||
8d2f24ca DV |
2662 | tmp |= DC_BALANCE_RESET_VLV; |
2663 | if (pipe == PIPE_A) | |
2664 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2665 | else | |
2666 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2667 | ||
2668 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2669 | } | |
2670 | ||
7ac0129b DV |
2671 | return 0; |
2672 | } | |
2673 | ||
4b79ebf7 | 2674 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
2675 | enum pipe pipe, |
2676 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
2677 | uint32_t *val) |
2678 | { | |
84093603 DV |
2679 | struct drm_i915_private *dev_priv = dev->dev_private; |
2680 | bool need_stable_symbols = false; | |
2681 | ||
46a19188 DV |
2682 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2683 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2684 | if (ret) | |
2685 | return ret; | |
2686 | } | |
2687 | ||
2688 | switch (*source) { | |
4b79ebf7 DV |
2689 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2690 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
2691 | break; | |
2692 | case INTEL_PIPE_CRC_SOURCE_TV: | |
2693 | if (!SUPPORTS_TV(dev)) | |
2694 | return -EINVAL; | |
2695 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
2696 | break; | |
2697 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2698 | if (!IS_G4X(dev)) | |
2699 | return -EINVAL; | |
2700 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 2701 | need_stable_symbols = true; |
4b79ebf7 DV |
2702 | break; |
2703 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2704 | if (!IS_G4X(dev)) | |
2705 | return -EINVAL; | |
2706 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 2707 | need_stable_symbols = true; |
4b79ebf7 DV |
2708 | break; |
2709 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
2710 | if (!IS_G4X(dev)) | |
2711 | return -EINVAL; | |
2712 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 2713 | need_stable_symbols = true; |
4b79ebf7 DV |
2714 | break; |
2715 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2716 | *val = 0; | |
2717 | break; | |
2718 | default: | |
2719 | return -EINVAL; | |
2720 | } | |
2721 | ||
84093603 DV |
2722 | /* |
2723 | * When the pipe CRC tap point is after the transcoders we need | |
2724 | * to tweak symbol-level features to produce a deterministic series of | |
2725 | * symbols for a given frame. We need to reset those features only once | |
2726 | * a frame (instead of every nth symbol): | |
2727 | * - DC-balance: used to ensure a better clock recovery from the data | |
2728 | * link (SDVO) | |
2729 | * - DisplayPort scrambling: used for EMI reduction | |
2730 | */ | |
2731 | if (need_stable_symbols) { | |
2732 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2733 | ||
2734 | WARN_ON(!IS_G4X(dev)); | |
2735 | ||
2736 | I915_WRITE(PORT_DFT_I9XX, | |
2737 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
2738 | ||
2739 | if (pipe == PIPE_A) | |
2740 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2741 | else | |
2742 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2743 | ||
2744 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2745 | } | |
2746 | ||
4b79ebf7 DV |
2747 | return 0; |
2748 | } | |
2749 | ||
8d2f24ca DV |
2750 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
2751 | enum pipe pipe) | |
2752 | { | |
2753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2754 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2755 | ||
2756 | if (pipe == PIPE_A) | |
2757 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2758 | else | |
2759 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2760 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) | |
2761 | tmp &= ~DC_BALANCE_RESET_VLV; | |
2762 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2763 | ||
2764 | } | |
2765 | ||
84093603 DV |
2766 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
2767 | enum pipe pipe) | |
2768 | { | |
2769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2770 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2771 | ||
2772 | if (pipe == PIPE_A) | |
2773 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2774 | else | |
2775 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2776 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2777 | ||
2778 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
2779 | I915_WRITE(PORT_DFT_I9XX, | |
2780 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
2781 | } | |
2782 | } | |
2783 | ||
46a19188 | 2784 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2785 | uint32_t *val) |
2786 | { | |
46a19188 DV |
2787 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2788 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2789 | ||
2790 | switch (*source) { | |
5b3a856b DV |
2791 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2792 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
2793 | break; | |
2794 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2795 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
2796 | break; | |
5b3a856b DV |
2797 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2798 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
2799 | break; | |
3d099a05 | 2800 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2801 | *val = 0; |
2802 | break; | |
3d099a05 DV |
2803 | default: |
2804 | return -EINVAL; | |
5b3a856b DV |
2805 | } |
2806 | ||
2807 | return 0; | |
2808 | } | |
2809 | ||
46a19188 | 2810 | static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2811 | uint32_t *val) |
2812 | { | |
46a19188 DV |
2813 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2814 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
2815 | ||
2816 | switch (*source) { | |
5b3a856b DV |
2817 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2818 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
2819 | break; | |
2820 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2821 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
2822 | break; | |
2823 | case INTEL_PIPE_CRC_SOURCE_PF: | |
2824 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; | |
2825 | break; | |
3d099a05 | 2826 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2827 | *val = 0; |
2828 | break; | |
3d099a05 DV |
2829 | default: |
2830 | return -EINVAL; | |
5b3a856b DV |
2831 | } |
2832 | ||
2833 | return 0; | |
2834 | } | |
2835 | ||
926321d5 DV |
2836 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
2837 | enum intel_pipe_crc_source source) | |
2838 | { | |
2839 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 2840 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
432f3342 | 2841 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 2842 | int ret; |
926321d5 | 2843 | |
cc3da175 DL |
2844 | if (pipe_crc->source == source) |
2845 | return 0; | |
2846 | ||
ae676fcd DL |
2847 | /* forbid changing the source without going back to 'none' */ |
2848 | if (pipe_crc->source && source) | |
2849 | return -EINVAL; | |
2850 | ||
52f843f6 | 2851 | if (IS_GEN2(dev)) |
46a19188 | 2852 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 2853 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 2854 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
7ac0129b | 2855 | else if (IS_VALLEYVIEW(dev)) |
46a19188 | 2856 | ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val); |
4b79ebf7 | 2857 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 2858 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 2859 | else |
46a19188 | 2860 | ret = ivb_pipe_crc_ctl_reg(&source, &val); |
5b3a856b DV |
2861 | |
2862 | if (ret != 0) | |
2863 | return ret; | |
2864 | ||
4b584369 DL |
2865 | /* none -> real source transition */ |
2866 | if (source) { | |
7cd6ccff DL |
2867 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
2868 | pipe_name(pipe), pipe_crc_source_name(source)); | |
2869 | ||
e5f75aca DL |
2870 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
2871 | INTEL_PIPE_CRC_ENTRIES_NR, | |
2872 | GFP_KERNEL); | |
2873 | if (!pipe_crc->entries) | |
2874 | return -ENOMEM; | |
2875 | ||
d538bbdf DL |
2876 | spin_lock_irq(&pipe_crc->lock); |
2877 | pipe_crc->head = 0; | |
2878 | pipe_crc->tail = 0; | |
2879 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
2880 | } |
2881 | ||
cc3da175 | 2882 | pipe_crc->source = source; |
926321d5 | 2883 | |
926321d5 DV |
2884 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
2885 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
2886 | ||
e5f75aca DL |
2887 | /* real source -> none transition */ |
2888 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf DL |
2889 | struct intel_pipe_crc_entry *entries; |
2890 | ||
7cd6ccff DL |
2891 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
2892 | pipe_name(pipe)); | |
2893 | ||
bcf17ab2 DV |
2894 | intel_wait_for_vblank(dev, pipe); |
2895 | ||
d538bbdf DL |
2896 | spin_lock_irq(&pipe_crc->lock); |
2897 | entries = pipe_crc->entries; | |
e5f75aca | 2898 | pipe_crc->entries = NULL; |
d538bbdf DL |
2899 | spin_unlock_irq(&pipe_crc->lock); |
2900 | ||
2901 | kfree(entries); | |
84093603 DV |
2902 | |
2903 | if (IS_G4X(dev)) | |
2904 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
8d2f24ca DV |
2905 | else if (IS_VALLEYVIEW(dev)) |
2906 | vlv_undo_pipe_scramble_reset(dev, pipe); | |
e5f75aca DL |
2907 | } |
2908 | ||
926321d5 DV |
2909 | return 0; |
2910 | } | |
2911 | ||
2912 | /* | |
2913 | * Parse pipe CRC command strings: | |
b94dec87 DL |
2914 | * command: wsp* object wsp+ name wsp+ source wsp* |
2915 | * object: 'pipe' | |
2916 | * name: (A | B | C) | |
926321d5 DV |
2917 | * source: (none | plane1 | plane2 | pf) |
2918 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
2919 | * | |
2920 | * eg.: | |
b94dec87 DL |
2921 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
2922 | * "pipe A none" -> Stop CRC | |
926321d5 | 2923 | */ |
bd9db02f | 2924 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
2925 | { |
2926 | int n_words = 0; | |
2927 | ||
2928 | while (*buf) { | |
2929 | char *end; | |
2930 | ||
2931 | /* skip leading white space */ | |
2932 | buf = skip_spaces(buf); | |
2933 | if (!*buf) | |
2934 | break; /* end of buffer */ | |
2935 | ||
2936 | /* find end of word */ | |
2937 | for (end = buf; *end && !isspace(*end); end++) | |
2938 | ; | |
2939 | ||
2940 | if (n_words == max_words) { | |
2941 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
2942 | max_words); | |
2943 | return -EINVAL; /* ran out of words[] before bytes */ | |
2944 | } | |
2945 | ||
2946 | if (*end) | |
2947 | *end++ = '\0'; | |
2948 | words[n_words++] = buf; | |
2949 | buf = end; | |
2950 | } | |
2951 | ||
2952 | return n_words; | |
2953 | } | |
2954 | ||
b94dec87 DL |
2955 | enum intel_pipe_crc_object { |
2956 | PIPE_CRC_OBJECT_PIPE, | |
2957 | }; | |
2958 | ||
e8dfcf78 | 2959 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
2960 | "pipe", |
2961 | }; | |
2962 | ||
2963 | static int | |
bd9db02f | 2964 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
2965 | { |
2966 | int i; | |
2967 | ||
2968 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
2969 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 2970 | *o = i; |
b94dec87 DL |
2971 | return 0; |
2972 | } | |
2973 | ||
2974 | return -EINVAL; | |
2975 | } | |
2976 | ||
bd9db02f | 2977 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
2978 | { |
2979 | const char name = buf[0]; | |
2980 | ||
2981 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
2982 | return -EINVAL; | |
2983 | ||
2984 | *pipe = name - 'A'; | |
2985 | ||
2986 | return 0; | |
2987 | } | |
2988 | ||
2989 | static int | |
bd9db02f | 2990 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
2991 | { |
2992 | int i; | |
2993 | ||
2994 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
2995 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 2996 | *s = i; |
926321d5 DV |
2997 | return 0; |
2998 | } | |
2999 | ||
3000 | return -EINVAL; | |
3001 | } | |
3002 | ||
bd9db02f | 3003 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 3004 | { |
b94dec87 | 3005 | #define N_WORDS 3 |
926321d5 | 3006 | int n_words; |
b94dec87 | 3007 | char *words[N_WORDS]; |
926321d5 | 3008 | enum pipe pipe; |
b94dec87 | 3009 | enum intel_pipe_crc_object object; |
926321d5 DV |
3010 | enum intel_pipe_crc_source source; |
3011 | ||
bd9db02f | 3012 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
3013 | if (n_words != N_WORDS) { |
3014 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
3015 | N_WORDS); | |
3016 | return -EINVAL; | |
3017 | } | |
3018 | ||
bd9db02f | 3019 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 3020 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
3021 | return -EINVAL; |
3022 | } | |
3023 | ||
bd9db02f | 3024 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 3025 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
3026 | return -EINVAL; |
3027 | } | |
3028 | ||
bd9db02f | 3029 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 3030 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
3031 | return -EINVAL; |
3032 | } | |
3033 | ||
3034 | return pipe_crc_set_source(dev, pipe, source); | |
3035 | } | |
3036 | ||
bd9db02f DL |
3037 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
3038 | size_t len, loff_t *offp) | |
926321d5 DV |
3039 | { |
3040 | struct seq_file *m = file->private_data; | |
3041 | struct drm_device *dev = m->private; | |
3042 | char *tmpbuf; | |
3043 | int ret; | |
3044 | ||
3045 | if (len == 0) | |
3046 | return 0; | |
3047 | ||
3048 | if (len > PAGE_SIZE - 1) { | |
3049 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
3050 | PAGE_SIZE); | |
3051 | return -E2BIG; | |
3052 | } | |
3053 | ||
3054 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
3055 | if (!tmpbuf) | |
3056 | return -ENOMEM; | |
3057 | ||
3058 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
3059 | ret = -EFAULT; | |
3060 | goto out; | |
3061 | } | |
3062 | tmpbuf[len] = '\0'; | |
3063 | ||
bd9db02f | 3064 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
3065 | |
3066 | out: | |
3067 | kfree(tmpbuf); | |
3068 | if (ret < 0) | |
3069 | return ret; | |
3070 | ||
3071 | *offp += len; | |
3072 | return len; | |
3073 | } | |
3074 | ||
bd9db02f | 3075 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 3076 | .owner = THIS_MODULE, |
bd9db02f | 3077 | .open = display_crc_ctl_open, |
926321d5 DV |
3078 | .read = seq_read, |
3079 | .llseek = seq_lseek, | |
3080 | .release = single_release, | |
bd9db02f | 3081 | .write = display_crc_ctl_write |
926321d5 DV |
3082 | }; |
3083 | ||
369a1342 VS |
3084 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[5]) |
3085 | { | |
3086 | struct drm_device *dev = m->private; | |
3087 | int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4; | |
3088 | int level; | |
3089 | ||
3090 | drm_modeset_lock_all(dev); | |
3091 | ||
3092 | for (level = 0; level < num_levels; level++) { | |
3093 | unsigned int latency = wm[level]; | |
3094 | ||
3095 | /* WM1+ latency values in 0.5us units */ | |
3096 | if (level > 0) | |
3097 | latency *= 5; | |
3098 | ||
3099 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
3100 | level, wm[level], | |
3101 | latency / 10, latency % 10); | |
3102 | } | |
3103 | ||
3104 | drm_modeset_unlock_all(dev); | |
3105 | } | |
3106 | ||
3107 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3108 | { | |
3109 | struct drm_device *dev = m->private; | |
3110 | ||
3111 | wm_latency_show(m, to_i915(dev)->wm.pri_latency); | |
3112 | ||
3113 | return 0; | |
3114 | } | |
3115 | ||
3116 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3117 | { | |
3118 | struct drm_device *dev = m->private; | |
3119 | ||
3120 | wm_latency_show(m, to_i915(dev)->wm.spr_latency); | |
3121 | ||
3122 | return 0; | |
3123 | } | |
3124 | ||
3125 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3126 | { | |
3127 | struct drm_device *dev = m->private; | |
3128 | ||
3129 | wm_latency_show(m, to_i915(dev)->wm.cur_latency); | |
3130 | ||
3131 | return 0; | |
3132 | } | |
3133 | ||
3134 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3135 | { | |
3136 | struct drm_device *dev = inode->i_private; | |
3137 | ||
3138 | if (!HAS_PCH_SPLIT(dev)) | |
3139 | return -ENODEV; | |
3140 | ||
3141 | return single_open(file, pri_wm_latency_show, dev); | |
3142 | } | |
3143 | ||
3144 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3145 | { | |
3146 | struct drm_device *dev = inode->i_private; | |
3147 | ||
3148 | if (!HAS_PCH_SPLIT(dev)) | |
3149 | return -ENODEV; | |
3150 | ||
3151 | return single_open(file, spr_wm_latency_show, dev); | |
3152 | } | |
3153 | ||
3154 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3155 | { | |
3156 | struct drm_device *dev = inode->i_private; | |
3157 | ||
3158 | if (!HAS_PCH_SPLIT(dev)) | |
3159 | return -ENODEV; | |
3160 | ||
3161 | return single_open(file, cur_wm_latency_show, dev); | |
3162 | } | |
3163 | ||
3164 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
3165 | size_t len, loff_t *offp, uint16_t wm[5]) | |
3166 | { | |
3167 | struct seq_file *m = file->private_data; | |
3168 | struct drm_device *dev = m->private; | |
3169 | uint16_t new[5] = { 0 }; | |
3170 | int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4; | |
3171 | int level; | |
3172 | int ret; | |
3173 | char tmp[32]; | |
3174 | ||
3175 | if (len >= sizeof(tmp)) | |
3176 | return -EINVAL; | |
3177 | ||
3178 | if (copy_from_user(tmp, ubuf, len)) | |
3179 | return -EFAULT; | |
3180 | ||
3181 | tmp[len] = '\0'; | |
3182 | ||
3183 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]); | |
3184 | if (ret != num_levels) | |
3185 | return -EINVAL; | |
3186 | ||
3187 | drm_modeset_lock_all(dev); | |
3188 | ||
3189 | for (level = 0; level < num_levels; level++) | |
3190 | wm[level] = new[level]; | |
3191 | ||
3192 | drm_modeset_unlock_all(dev); | |
3193 | ||
3194 | return len; | |
3195 | } | |
3196 | ||
3197 | ||
3198 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
3199 | size_t len, loff_t *offp) | |
3200 | { | |
3201 | struct seq_file *m = file->private_data; | |
3202 | struct drm_device *dev = m->private; | |
3203 | ||
3204 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency); | |
3205 | } | |
3206 | ||
3207 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
3208 | size_t len, loff_t *offp) | |
3209 | { | |
3210 | struct seq_file *m = file->private_data; | |
3211 | struct drm_device *dev = m->private; | |
3212 | ||
3213 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency); | |
3214 | } | |
3215 | ||
3216 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
3217 | size_t len, loff_t *offp) | |
3218 | { | |
3219 | struct seq_file *m = file->private_data; | |
3220 | struct drm_device *dev = m->private; | |
3221 | ||
3222 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency); | |
3223 | } | |
3224 | ||
3225 | static const struct file_operations i915_pri_wm_latency_fops = { | |
3226 | .owner = THIS_MODULE, | |
3227 | .open = pri_wm_latency_open, | |
3228 | .read = seq_read, | |
3229 | .llseek = seq_lseek, | |
3230 | .release = single_release, | |
3231 | .write = pri_wm_latency_write | |
3232 | }; | |
3233 | ||
3234 | static const struct file_operations i915_spr_wm_latency_fops = { | |
3235 | .owner = THIS_MODULE, | |
3236 | .open = spr_wm_latency_open, | |
3237 | .read = seq_read, | |
3238 | .llseek = seq_lseek, | |
3239 | .release = single_release, | |
3240 | .write = spr_wm_latency_write | |
3241 | }; | |
3242 | ||
3243 | static const struct file_operations i915_cur_wm_latency_fops = { | |
3244 | .owner = THIS_MODULE, | |
3245 | .open = cur_wm_latency_open, | |
3246 | .read = seq_read, | |
3247 | .llseek = seq_lseek, | |
3248 | .release = single_release, | |
3249 | .write = cur_wm_latency_write | |
3250 | }; | |
3251 | ||
647416f9 KC |
3252 | static int |
3253 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 3254 | { |
647416f9 | 3255 | struct drm_device *dev = data; |
e277a1f8 | 3256 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 3257 | |
647416f9 | 3258 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 3259 | |
647416f9 | 3260 | return 0; |
f3cd474b CW |
3261 | } |
3262 | ||
647416f9 KC |
3263 | static int |
3264 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 3265 | { |
647416f9 | 3266 | struct drm_device *dev = data; |
d46c0517 ID |
3267 | struct drm_i915_private *dev_priv = dev->dev_private; |
3268 | ||
3269 | intel_runtime_pm_get(dev_priv); | |
f3cd474b | 3270 | |
58174462 MK |
3271 | i915_handle_error(dev, val, |
3272 | "Manually setting wedged to %llu", val); | |
d46c0517 ID |
3273 | |
3274 | intel_runtime_pm_put(dev_priv); | |
3275 | ||
647416f9 | 3276 | return 0; |
f3cd474b CW |
3277 | } |
3278 | ||
647416f9 KC |
3279 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
3280 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 3281 | "%llu\n"); |
f3cd474b | 3282 | |
647416f9 KC |
3283 | static int |
3284 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 3285 | { |
647416f9 | 3286 | struct drm_device *dev = data; |
e277a1f8 | 3287 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 3288 | |
647416f9 | 3289 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 3290 | |
647416f9 | 3291 | return 0; |
e5eb3d63 DV |
3292 | } |
3293 | ||
647416f9 KC |
3294 | static int |
3295 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 3296 | { |
647416f9 | 3297 | struct drm_device *dev = data; |
e5eb3d63 | 3298 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3299 | int ret; |
e5eb3d63 | 3300 | |
647416f9 | 3301 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 3302 | |
22bcfc6a DV |
3303 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3304 | if (ret) | |
3305 | return ret; | |
3306 | ||
99584db3 | 3307 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
3308 | mutex_unlock(&dev->struct_mutex); |
3309 | ||
647416f9 | 3310 | return 0; |
e5eb3d63 DV |
3311 | } |
3312 | ||
647416f9 KC |
3313 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
3314 | i915_ring_stop_get, i915_ring_stop_set, | |
3315 | "0x%08llx\n"); | |
d5442303 | 3316 | |
094f9a54 CW |
3317 | static int |
3318 | i915_ring_missed_irq_get(void *data, u64 *val) | |
3319 | { | |
3320 | struct drm_device *dev = data; | |
3321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3322 | ||
3323 | *val = dev_priv->gpu_error.missed_irq_rings; | |
3324 | return 0; | |
3325 | } | |
3326 | ||
3327 | static int | |
3328 | i915_ring_missed_irq_set(void *data, u64 val) | |
3329 | { | |
3330 | struct drm_device *dev = data; | |
3331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3332 | int ret; | |
3333 | ||
3334 | /* Lock against concurrent debugfs callers */ | |
3335 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3336 | if (ret) | |
3337 | return ret; | |
3338 | dev_priv->gpu_error.missed_irq_rings = val; | |
3339 | mutex_unlock(&dev->struct_mutex); | |
3340 | ||
3341 | return 0; | |
3342 | } | |
3343 | ||
3344 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
3345 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
3346 | "0x%08llx\n"); | |
3347 | ||
3348 | static int | |
3349 | i915_ring_test_irq_get(void *data, u64 *val) | |
3350 | { | |
3351 | struct drm_device *dev = data; | |
3352 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3353 | ||
3354 | *val = dev_priv->gpu_error.test_irq_rings; | |
3355 | ||
3356 | return 0; | |
3357 | } | |
3358 | ||
3359 | static int | |
3360 | i915_ring_test_irq_set(void *data, u64 val) | |
3361 | { | |
3362 | struct drm_device *dev = data; | |
3363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3364 | int ret; | |
3365 | ||
3366 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
3367 | ||
3368 | /* Lock against concurrent debugfs callers */ | |
3369 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3370 | if (ret) | |
3371 | return ret; | |
3372 | ||
3373 | dev_priv->gpu_error.test_irq_rings = val; | |
3374 | mutex_unlock(&dev->struct_mutex); | |
3375 | ||
3376 | return 0; | |
3377 | } | |
3378 | ||
3379 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
3380 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
3381 | "0x%08llx\n"); | |
3382 | ||
dd624afd CW |
3383 | #define DROP_UNBOUND 0x1 |
3384 | #define DROP_BOUND 0x2 | |
3385 | #define DROP_RETIRE 0x4 | |
3386 | #define DROP_ACTIVE 0x8 | |
3387 | #define DROP_ALL (DROP_UNBOUND | \ | |
3388 | DROP_BOUND | \ | |
3389 | DROP_RETIRE | \ | |
3390 | DROP_ACTIVE) | |
647416f9 KC |
3391 | static int |
3392 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 3393 | { |
647416f9 | 3394 | *val = DROP_ALL; |
dd624afd | 3395 | |
647416f9 | 3396 | return 0; |
dd624afd CW |
3397 | } |
3398 | ||
647416f9 KC |
3399 | static int |
3400 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 3401 | { |
647416f9 | 3402 | struct drm_device *dev = data; |
dd624afd CW |
3403 | struct drm_i915_private *dev_priv = dev->dev_private; |
3404 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
3405 | struct i915_address_space *vm; |
3406 | struct i915_vma *vma, *x; | |
647416f9 | 3407 | int ret; |
dd624afd | 3408 | |
2f9fe5ff | 3409 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
3410 | |
3411 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
3412 | * on ioctls on -EAGAIN. */ | |
3413 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3414 | if (ret) | |
3415 | return ret; | |
3416 | ||
3417 | if (val & DROP_ACTIVE) { | |
3418 | ret = i915_gpu_idle(dev); | |
3419 | if (ret) | |
3420 | goto unlock; | |
3421 | } | |
3422 | ||
3423 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
3424 | i915_gem_retire_requests(dev); | |
3425 | ||
3426 | if (val & DROP_BOUND) { | |
ca191b13 BW |
3427 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3428 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
3429 | mm_list) { | |
d7f46fc4 | 3430 | if (vma->pin_count) |
ca191b13 BW |
3431 | continue; |
3432 | ||
3433 | ret = i915_vma_unbind(vma); | |
3434 | if (ret) | |
3435 | goto unlock; | |
3436 | } | |
31a46c9c | 3437 | } |
dd624afd CW |
3438 | } |
3439 | ||
3440 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
3441 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
3442 | global_list) | |
dd624afd CW |
3443 | if (obj->pages_pin_count == 0) { |
3444 | ret = i915_gem_object_put_pages(obj); | |
3445 | if (ret) | |
3446 | goto unlock; | |
3447 | } | |
3448 | } | |
3449 | ||
3450 | unlock: | |
3451 | mutex_unlock(&dev->struct_mutex); | |
3452 | ||
647416f9 | 3453 | return ret; |
dd624afd CW |
3454 | } |
3455 | ||
647416f9 KC |
3456 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
3457 | i915_drop_caches_get, i915_drop_caches_set, | |
3458 | "0x%08llx\n"); | |
dd624afd | 3459 | |
647416f9 KC |
3460 | static int |
3461 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 3462 | { |
647416f9 | 3463 | struct drm_device *dev = data; |
e277a1f8 | 3464 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3465 | int ret; |
004777cb DV |
3466 | |
3467 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
3468 | return -ENODEV; | |
3469 | ||
5c9669ce TR |
3470 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3471 | ||
4fc688ce | 3472 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3473 | if (ret) |
3474 | return ret; | |
358733e9 | 3475 | |
0a073b84 | 3476 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 3477 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
0a073b84 | 3478 | else |
b39fb297 | 3479 | *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
4fc688ce | 3480 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 3481 | |
647416f9 | 3482 | return 0; |
358733e9 JB |
3483 | } |
3484 | ||
647416f9 KC |
3485 | static int |
3486 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 3487 | { |
647416f9 | 3488 | struct drm_device *dev = data; |
358733e9 | 3489 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 3490 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 3491 | int ret; |
004777cb DV |
3492 | |
3493 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
3494 | return -ENODEV; | |
358733e9 | 3495 | |
5c9669ce TR |
3496 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3497 | ||
647416f9 | 3498 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 3499 | |
4fc688ce | 3500 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3501 | if (ret) |
3502 | return ret; | |
3503 | ||
358733e9 JB |
3504 | /* |
3505 | * Turbo will still be enabled, but won't go above the set value. | |
3506 | */ | |
0a073b84 | 3507 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 3508 | val = vlv_freq_opcode(dev_priv, val); |
dd0a1aa1 JM |
3509 | |
3510 | hw_max = valleyview_rps_max_freq(dev_priv); | |
3511 | hw_min = valleyview_rps_min_freq(dev_priv); | |
0a073b84 JB |
3512 | } else { |
3513 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
dd0a1aa1 JM |
3514 | |
3515 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
b39fb297 | 3516 | hw_max = dev_priv->rps.max_freq; |
dd0a1aa1 JM |
3517 | hw_min = (rp_state_cap >> 16) & 0xff; |
3518 | } | |
3519 | ||
b39fb297 | 3520 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
3521 | mutex_unlock(&dev_priv->rps.hw_lock); |
3522 | return -EINVAL; | |
0a073b84 JB |
3523 | } |
3524 | ||
b39fb297 | 3525 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 JM |
3526 | |
3527 | if (IS_VALLEYVIEW(dev)) | |
3528 | valleyview_set_rps(dev, val); | |
3529 | else | |
3530 | gen6_set_rps(dev, val); | |
3531 | ||
4fc688ce | 3532 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 3533 | |
647416f9 | 3534 | return 0; |
358733e9 JB |
3535 | } |
3536 | ||
647416f9 KC |
3537 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
3538 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 3539 | "%llu\n"); |
358733e9 | 3540 | |
647416f9 KC |
3541 | static int |
3542 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 3543 | { |
647416f9 | 3544 | struct drm_device *dev = data; |
e277a1f8 | 3545 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3546 | int ret; |
004777cb DV |
3547 | |
3548 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
3549 | return -ENODEV; | |
3550 | ||
5c9669ce TR |
3551 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3552 | ||
4fc688ce | 3553 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3554 | if (ret) |
3555 | return ret; | |
1523c310 | 3556 | |
0a073b84 | 3557 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 3558 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
0a073b84 | 3559 | else |
b39fb297 | 3560 | *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
4fc688ce | 3561 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3562 | |
647416f9 | 3563 | return 0; |
1523c310 JB |
3564 | } |
3565 | ||
647416f9 KC |
3566 | static int |
3567 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 3568 | { |
647416f9 | 3569 | struct drm_device *dev = data; |
1523c310 | 3570 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 3571 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 3572 | int ret; |
004777cb DV |
3573 | |
3574 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
3575 | return -ENODEV; | |
1523c310 | 3576 | |
5c9669ce TR |
3577 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3578 | ||
647416f9 | 3579 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 3580 | |
4fc688ce | 3581 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3582 | if (ret) |
3583 | return ret; | |
3584 | ||
1523c310 JB |
3585 | /* |
3586 | * Turbo will still be enabled, but won't go below the set value. | |
3587 | */ | |
0a073b84 | 3588 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 3589 | val = vlv_freq_opcode(dev_priv, val); |
dd0a1aa1 JM |
3590 | |
3591 | hw_max = valleyview_rps_max_freq(dev_priv); | |
3592 | hw_min = valleyview_rps_min_freq(dev_priv); | |
0a073b84 JB |
3593 | } else { |
3594 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
dd0a1aa1 JM |
3595 | |
3596 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
b39fb297 | 3597 | hw_max = dev_priv->rps.max_freq; |
dd0a1aa1 JM |
3598 | hw_min = (rp_state_cap >> 16) & 0xff; |
3599 | } | |
3600 | ||
b39fb297 | 3601 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
3602 | mutex_unlock(&dev_priv->rps.hw_lock); |
3603 | return -EINVAL; | |
0a073b84 | 3604 | } |
dd0a1aa1 | 3605 | |
b39fb297 | 3606 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 JM |
3607 | |
3608 | if (IS_VALLEYVIEW(dev)) | |
3609 | valleyview_set_rps(dev, val); | |
3610 | else | |
3611 | gen6_set_rps(dev, val); | |
3612 | ||
4fc688ce | 3613 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3614 | |
647416f9 | 3615 | return 0; |
1523c310 JB |
3616 | } |
3617 | ||
647416f9 KC |
3618 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
3619 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 3620 | "%llu\n"); |
1523c310 | 3621 | |
647416f9 KC |
3622 | static int |
3623 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 3624 | { |
647416f9 | 3625 | struct drm_device *dev = data; |
e277a1f8 | 3626 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 3627 | u32 snpcr; |
647416f9 | 3628 | int ret; |
07b7ddd9 | 3629 | |
004777cb DV |
3630 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3631 | return -ENODEV; | |
3632 | ||
22bcfc6a DV |
3633 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3634 | if (ret) | |
3635 | return ret; | |
c8c8fb33 | 3636 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 3637 | |
07b7ddd9 | 3638 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
3639 | |
3640 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
3641 | mutex_unlock(&dev_priv->dev->struct_mutex); |
3642 | ||
647416f9 | 3643 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 3644 | |
647416f9 | 3645 | return 0; |
07b7ddd9 JB |
3646 | } |
3647 | ||
647416f9 KC |
3648 | static int |
3649 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 3650 | { |
647416f9 | 3651 | struct drm_device *dev = data; |
07b7ddd9 | 3652 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 3653 | u32 snpcr; |
07b7ddd9 | 3654 | |
004777cb DV |
3655 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3656 | return -ENODEV; | |
3657 | ||
647416f9 | 3658 | if (val > 3) |
07b7ddd9 JB |
3659 | return -EINVAL; |
3660 | ||
c8c8fb33 | 3661 | intel_runtime_pm_get(dev_priv); |
647416f9 | 3662 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
3663 | |
3664 | /* Update the cache sharing policy here as well */ | |
3665 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
3666 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
3667 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
3668 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3669 | ||
c8c8fb33 | 3670 | intel_runtime_pm_put(dev_priv); |
647416f9 | 3671 | return 0; |
07b7ddd9 JB |
3672 | } |
3673 | ||
647416f9 KC |
3674 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
3675 | i915_cache_sharing_get, i915_cache_sharing_set, | |
3676 | "%llu\n"); | |
07b7ddd9 | 3677 | |
6d794d42 BW |
3678 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
3679 | { | |
3680 | struct drm_device *dev = inode->i_private; | |
3681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 3682 | |
075edca4 | 3683 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3684 | return 0; |
3685 | ||
c8d9a590 | 3686 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3687 | |
3688 | return 0; | |
3689 | } | |
3690 | ||
c43b5634 | 3691 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
3692 | { |
3693 | struct drm_device *dev = inode->i_private; | |
3694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3695 | ||
075edca4 | 3696 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3697 | return 0; |
3698 | ||
c8d9a590 | 3699 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3700 | |
3701 | return 0; | |
3702 | } | |
3703 | ||
3704 | static const struct file_operations i915_forcewake_fops = { | |
3705 | .owner = THIS_MODULE, | |
3706 | .open = i915_forcewake_open, | |
3707 | .release = i915_forcewake_release, | |
3708 | }; | |
3709 | ||
3710 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
3711 | { | |
3712 | struct drm_device *dev = minor->dev; | |
3713 | struct dentry *ent; | |
3714 | ||
3715 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 3716 | S_IRUSR, |
6d794d42 BW |
3717 | root, dev, |
3718 | &i915_forcewake_fops); | |
f3c5fe97 WY |
3719 | if (!ent) |
3720 | return -ENOMEM; | |
6d794d42 | 3721 | |
8eb57294 | 3722 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
3723 | } |
3724 | ||
6a9c308d DV |
3725 | static int i915_debugfs_create(struct dentry *root, |
3726 | struct drm_minor *minor, | |
3727 | const char *name, | |
3728 | const struct file_operations *fops) | |
07b7ddd9 JB |
3729 | { |
3730 | struct drm_device *dev = minor->dev; | |
3731 | struct dentry *ent; | |
3732 | ||
6a9c308d | 3733 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
3734 | S_IRUGO | S_IWUSR, |
3735 | root, dev, | |
6a9c308d | 3736 | fops); |
f3c5fe97 WY |
3737 | if (!ent) |
3738 | return -ENOMEM; | |
07b7ddd9 | 3739 | |
6a9c308d | 3740 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
3741 | } |
3742 | ||
06c5bf8c | 3743 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 3744 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 3745 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 3746 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 3747 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 3748 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 3749 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 3750 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 3751 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
3752 | {"i915_gem_request", i915_gem_request_info, 0}, |
3753 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 3754 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 3755 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
3756 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
3757 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
3758 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 3759 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 | 3760 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
adb4bd12 | 3761 | {"i915_frequency_info", i915_frequency_info, 0}, |
f97108d1 JB |
3762 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, |
3763 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
3764 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 3765 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 3766 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 3767 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 3768 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 3769 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 3770 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 3771 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 3772 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 3773 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 3774 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 3775 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 3776 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 3777 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 3778 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 3779 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 3780 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 3781 | {"i915_pc8_status", i915_pc8_status, 0}, |
1da51581 | 3782 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
53f5e3ca | 3783 | {"i915_display_info", i915_display_info, 0}, |
2017263e | 3784 | }; |
27c202ad | 3785 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 3786 | |
06c5bf8c | 3787 | static const struct i915_debugfs_files { |
34b9674c DV |
3788 | const char *name; |
3789 | const struct file_operations *fops; | |
3790 | } i915_debugfs_files[] = { | |
3791 | {"i915_wedged", &i915_wedged_fops}, | |
3792 | {"i915_max_freq", &i915_max_freq_fops}, | |
3793 | {"i915_min_freq", &i915_min_freq_fops}, | |
3794 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
3795 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
3796 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
3797 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
3798 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
3799 | {"i915_error_state", &i915_error_state_fops}, | |
3800 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 3801 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
3802 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
3803 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
3804 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
34b9674c DV |
3805 | }; |
3806 | ||
07144428 DL |
3807 | void intel_display_crc_init(struct drm_device *dev) |
3808 | { | |
3809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 3810 | enum pipe pipe; |
07144428 | 3811 | |
b378360e DV |
3812 | for_each_pipe(pipe) { |
3813 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
07144428 | 3814 | |
d538bbdf DL |
3815 | pipe_crc->opened = false; |
3816 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
3817 | init_waitqueue_head(&pipe_crc->wq); |
3818 | } | |
3819 | } | |
3820 | ||
27c202ad | 3821 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 3822 | { |
34b9674c | 3823 | int ret, i; |
f3cd474b | 3824 | |
6d794d42 | 3825 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
3826 | if (ret) |
3827 | return ret; | |
6a9c308d | 3828 | |
07144428 DL |
3829 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
3830 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
3831 | if (ret) | |
3832 | return ret; | |
3833 | } | |
3834 | ||
34b9674c DV |
3835 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3836 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
3837 | i915_debugfs_files[i].name, | |
3838 | i915_debugfs_files[i].fops); | |
3839 | if (ret) | |
3840 | return ret; | |
3841 | } | |
40633219 | 3842 | |
27c202ad BG |
3843 | return drm_debugfs_create_files(i915_debugfs_list, |
3844 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
3845 | minor->debugfs_root, minor); |
3846 | } | |
3847 | ||
27c202ad | 3848 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 3849 | { |
34b9674c DV |
3850 | int i; |
3851 | ||
27c202ad BG |
3852 | drm_debugfs_remove_files(i915_debugfs_list, |
3853 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 3854 | |
6d794d42 BW |
3855 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
3856 | 1, minor); | |
07144428 | 3857 | |
e309a997 | 3858 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
3859 | struct drm_info_list *info_list = |
3860 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
3861 | ||
3862 | drm_debugfs_remove_files(info_list, 1, minor); | |
3863 | } | |
3864 | ||
34b9674c DV |
3865 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3866 | struct drm_info_list *info_list = | |
3867 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
3868 | ||
3869 | drm_debugfs_remove_files(info_list, 1, minor); | |
3870 | } | |
2017263e | 3871 | } |