projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm: revamp locking around fb creation/destruction
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
f3cd474b 30#include <linux/debugfs.h>
5a0e3ad6 31#include <linux/slab.h>
2d1a8a48 32#include <linux/export.h>
760285e7 33#include <drm/drmP.h>
4e5359cd 34#include "intel_drv.h"
e5c65260 35#include "intel_ringbuffer.h"
760285e7 36#include <drm/i915_drm.h>
2017263e
BG		 37#include "i915_drv.h"
38
39#define DRM_I915_RING_DEBUG 1
40
41
42#if defined(CONFIG_DEBUG_FS)
43
f13d3f73 44enum {
69dc4987 45 ACTIVE_LIST,
f13d3f73 46 INACTIVE_LIST,
d21d5975 47 PINNED_LIST,
f13d3f73 48};
2017263e 49
70d39fe4
CW		 50static const char *yesno(int v)
51{
52 return v ? "yes" : "no";
53}
54
55static int i915_capabilities(struct seq_file *m, void *data)
56{
57 struct drm_info_node *node = (struct drm_info_node *) m->private;
58 struct drm_device *dev = node->minor->dev;
59 const struct intel_device_info *info = INTEL_INFO(dev);
60
61 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 62 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
c96ea64e
DV		 63#define DEV_INFO_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
64#define DEV_INFO_SEP ;
65 DEV_INFO_FLAGS;
66#undef DEV_INFO_FLAG
67#undef DEV_INFO_SEP
70d39fe4
CW		 68
69 return 0;
70}
2017263e 71
05394f39 72static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 73{
05394f39 74 if (obj->user_pin_count > 0)
a6172a80 75 return "P";
05394f39 76 else if (obj->pin_count > 0)
a6172a80
CW		 77 return "p";
78 else
79 return " ";
80}
81
05394f39 82static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 83{
0206e353
AJ		 84 switch (obj->tiling_mode) {
85 default:
86 case I915_TILING_NONE: return " ";
87 case I915_TILING_X: return "X";
88 case I915_TILING_Y: return "Y";
89 }
a6172a80
CW		 90}
91
93dfb40c 92static const char *cache_level_str(int type)
08c18323
CW		 93{
94 switch (type) {
93dfb40c
CW		 95 case I915_CACHE_NONE: return " uncached";
96 case I915_CACHE_LLC: return " snooped (LLC)";
97 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
08c18323
CW		 98 default: return "";
99 }
100}
101
37811fcc
CW		 102static void
103describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
104{
0201f1ec 105 seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d %d%s%s%s",
37811fcc
CW		 106 &obj->base,
107 get_pin_flag(obj),
108 get_tiling_flag(obj),
a05a5862 109 obj->base.size / 1024,
37811fcc
CW		 110 obj->base.read_domains,
111 obj->base.write_domain,
0201f1ec
CW		 112 obj->last_read_seqno,
113 obj->last_write_seqno,
caea7476 114 obj->last_fenced_seqno,
93dfb40c 115 cache_level_str(obj->cache_level),
37811fcc
CW		 116 obj->dirty ? " dirty" : "",
117 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
118 if (obj->base.name)
119 seq_printf(m, " (name: %d)", obj->base.name);
c110a6d7
CW		 120 if (obj->pin_count)
121 seq_printf(m, " (pinned x %d)", obj->pin_count);
37811fcc
CW		 122 if (obj->fence_reg != I915_FENCE_REG_NONE)
123 seq_printf(m, " (fence: %d)", obj->fence_reg);
124 if (obj->gtt_space != NULL)
a00b10c3
CW		 125 seq_printf(m, " (gtt offset: %08x, size: %08x)",
126 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
6299f992
CW		 127 if (obj->pin_mappable || obj->fault_mappable) {
128 char s[3], *t = s;
129 if (obj->pin_mappable)
130 *t++ = 'p';
131 if (obj->fault_mappable)
132 *t++ = 'f';
133 *t = '\0';
134 seq_printf(m, " (%s mappable)", s);
135 }
69dc4987
CW		 136 if (obj->ring != NULL)
137 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 138}
139
433e12f7 140static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 141{
142 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 143 uintptr_t list = (uintptr_t) node->info_ent->data;
144 struct list_head *head;
2017263e
BG		 145 struct drm_device *dev = node->minor->dev;
146 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 147 struct drm_i915_gem_object *obj;
8f2480fb
CW		 148 size_t total_obj_size, total_gtt_size;
149 int count, ret;
de227ef0
CW		 150
151 ret = mutex_lock_interruptible(&dev->struct_mutex);
152 if (ret)
153 return ret;
2017263e 154
433e12f7
BG		 155 switch (list) {
156 case ACTIVE_LIST:
157 seq_printf(m, "Active:\n");
69dc4987 158 head = &dev_priv->mm.active_list;
433e12f7
BG		 159 break;
160 case INACTIVE_LIST:
a17458fc 161 seq_printf(m, "Inactive:\n");
433e12f7
BG		 162 head = &dev_priv->mm.inactive_list;
163 break;
433e12f7 164 default:
de227ef0
CW		 165 mutex_unlock(&dev->struct_mutex);
166 return -EINVAL;
2017263e 167 }
2017263e 168
8f2480fb 169 total_obj_size = total_gtt_size = count = 0;
05394f39 170 list_for_each_entry(obj, head, mm_list) {
37811fcc 171 seq_printf(m, " ");
05394f39 172 describe_obj(m, obj);
f4ceda89 173 seq_printf(m, "\n");
05394f39
CW		 174 total_obj_size += obj->base.size;
175 total_gtt_size += obj->gtt_space->size;
8f2480fb 176 count++;
2017263e 177 }
de227ef0 178 mutex_unlock(&dev->struct_mutex);
5e118f41 179
8f2480fb
CW		 180 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
181 count, total_obj_size, total_gtt_size);
2017263e
BG		 182 return 0;
183}
184
6299f992
CW		 185#define count_objects(list, member) do { \
186 list_for_each_entry(obj, list, member) { \
187 size += obj->gtt_space->size; \
188 ++count; \
189 if (obj->map_and_fenceable) { \
190 mappable_size += obj->gtt_space->size; \
191 ++mappable_count; \
192 } \
193 } \
0206e353 194} while (0)
6299f992 195
73aa808f
CW		 196static int i915_gem_object_info(struct seq_file *m, void* data)
197{
198 struct drm_info_node *node = (struct drm_info_node *) m->private;
199 struct drm_device *dev = node->minor->dev;
200 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 201 u32 count, mappable_count, purgeable_count;
202 size_t size, mappable_size, purgeable_size;
6299f992 203 struct drm_i915_gem_object *obj;
73aa808f
CW		 204 int ret;
205
206 ret = mutex_lock_interruptible(&dev->struct_mutex);
207 if (ret)
208 return ret;
209
6299f992
CW		 210 seq_printf(m, "%u objects, %zu bytes\n",
211 dev_priv->mm.object_count,
212 dev_priv->mm.object_memory);
213
214 size = count = mappable_size = mappable_count = 0;
6c085a72 215 count_objects(&dev_priv->mm.bound_list, gtt_list);
6299f992
CW		 216 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
217 count, mappable_count, size, mappable_size);
218
219 size = count = mappable_size = mappable_count = 0;
220 count_objects(&dev_priv->mm.active_list, mm_list);
6299f992
CW		 221 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
222 count, mappable_count, size, mappable_size);
223
6299f992
CW		 224 size = count = mappable_size = mappable_count = 0;
225 count_objects(&dev_priv->mm.inactive_list, mm_list);
226 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
227 count, mappable_count, size, mappable_size);
228
b7abb714
CW		 229 size = count = purgeable_size = purgeable_count = 0;
230 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) {
6c085a72 231 size += obj->base.size, ++count;
b7abb714
CW		 232 if (obj->madv == I915_MADV_DONTNEED)
233 purgeable_size += obj->base.size, ++purgeable_count;
234 }
6c085a72
CW		 235 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
236
6299f992 237 size = count = mappable_size = mappable_count = 0;
6c085a72 238 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
6299f992
CW		 239 if (obj->fault_mappable) {
240 size += obj->gtt_space->size;
241 ++count;
242 }
243 if (obj->pin_mappable) {
244 mappable_size += obj->gtt_space->size;
245 ++mappable_count;
246 }
b7abb714
CW		 247 if (obj->madv == I915_MADV_DONTNEED) {
248 purgeable_size += obj->base.size;
249 ++purgeable_count;
250 }
6299f992 251 }
b7abb714
CW		 252 seq_printf(m, "%u purgeable objects, %zu bytes\n",
253 purgeable_count, purgeable_size);
6299f992
CW		 254 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
255 mappable_count, mappable_size);
256 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
257 count, size);
258
259 seq_printf(m, "%zu [%zu] gtt total\n",
260 dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
73aa808f
CW		 261
262 mutex_unlock(&dev->struct_mutex);
263
264 return 0;
265}
266
08c18323
CW		 267static int i915_gem_gtt_info(struct seq_file *m, void* data)
268{
269 struct drm_info_node *node = (struct drm_info_node *) m->private;
270 struct drm_device *dev = node->minor->dev;
1b50247a 271 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 272 struct drm_i915_private *dev_priv = dev->dev_private;
273 struct drm_i915_gem_object *obj;
274 size_t total_obj_size, total_gtt_size;
275 int count, ret;
276
277 ret = mutex_lock_interruptible(&dev->struct_mutex);
278 if (ret)
279 return ret;
280
281 total_obj_size = total_gtt_size = count = 0;
6c085a72 282 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1b50247a
CW		 283 if (list == PINNED_LIST && obj->pin_count == 0)
284 continue;
285
08c18323
CW		 286 seq_printf(m, " ");
287 describe_obj(m, obj);
288 seq_printf(m, "\n");
289 total_obj_size += obj->base.size;
290 total_gtt_size += obj->gtt_space->size;
291 count++;
292 }
293
294 mutex_unlock(&dev->struct_mutex);
295
296 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
297 count, total_obj_size, total_gtt_size);
298
299 return 0;
300}
301
4e5359cd
SF		 302static int i915_gem_pageflip_info(struct seq_file *m, void *data)
303{
304 struct drm_info_node *node = (struct drm_info_node *) m->private;
305 struct drm_device *dev = node->minor->dev;
306 unsigned long flags;
307 struct intel_crtc *crtc;
308
309 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 310 const char pipe = pipe_name(crtc->pipe);
311 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 312 struct intel_unpin_work *work;
313
314 spin_lock_irqsave(&dev->event_lock, flags);
315 work = crtc->unpin_work;
316 if (work == NULL) {
9db4a9c7 317 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 318 pipe, plane);
319 } else {
e7d841ca 320 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 321 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 322 pipe, plane);
323 } else {
9db4a9c7 324 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 325 pipe, plane);
326 }
327 if (work->enable_stall_check)
328 seq_printf(m, "Stall check enabled, ");
329 else
330 seq_printf(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 331 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 332
333 if (work->old_fb_obj) {
05394f39
CW		 334 struct drm_i915_gem_object *obj = work->old_fb_obj;
335 if (obj)
336 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF		 337 }
338 if (work->pending_flip_obj) {
05394f39
CW		 339 struct drm_i915_gem_object *obj = work->pending_flip_obj;
340 if (obj)
341 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
4e5359cd
SF		 342 }
343 }
344 spin_unlock_irqrestore(&dev->event_lock, flags);
345 }
346
347 return 0;
348}
349
2017263e
BG		 350static int i915_gem_request_info(struct seq_file *m, void *data)
351{
352 struct drm_info_node *node = (struct drm_info_node *) m->private;
353 struct drm_device *dev = node->minor->dev;
354 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 355 struct intel_ring_buffer *ring;
2017263e 356 struct drm_i915_gem_request *gem_request;
a2c7f6fd 357 int ret, count, i;
de227ef0
CW		 358
359 ret = mutex_lock_interruptible(&dev->struct_mutex);
360 if (ret)
361 return ret;
2017263e 362
c2c347a9 363 count = 0;
a2c7f6fd
CW		 364 for_each_ring(ring, dev_priv, i) {
365 if (list_empty(&ring->request_list))
366 continue;
367
368 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 369 list_for_each_entry(gem_request,
a2c7f6fd 370 &ring->request_list,
c2c347a9
CW		 371 list) {
372 seq_printf(m, " %d @ %d\n",
373 gem_request->seqno,
374 (int) (jiffies - gem_request->emitted_jiffies));
375 }
376 count++;
2017263e 377 }
de227ef0
CW		 378 mutex_unlock(&dev->struct_mutex);
379
c2c347a9
CW		 380 if (count == 0)
381 seq_printf(m, "No requests\n");
382
2017263e
BG		 383 return 0;
384}
385
b2223497
CW		 386static void i915_ring_seqno_info(struct seq_file *m,
387 struct intel_ring_buffer *ring)
388{
389 if (ring->get_seqno) {
390 seq_printf(m, "Current sequence (%s): %d\n",
b2eadbc8 391 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 392 }
393}
394
2017263e
BG		 395static int i915_gem_seqno_info(struct seq_file *m, void *data)
396{
397 struct drm_info_node *node = (struct drm_info_node *) m->private;
398 struct drm_device *dev = node->minor->dev;
399 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 400 struct intel_ring_buffer *ring;
1ec14ad3 401 int ret, i;
de227ef0
CW		 402
403 ret = mutex_lock_interruptible(&dev->struct_mutex);
404 if (ret)
405 return ret;
2017263e 406
a2c7f6fd
CW		 407 for_each_ring(ring, dev_priv, i)
408 i915_ring_seqno_info(m, ring);
de227ef0
CW		 409
410 mutex_unlock(&dev->struct_mutex);
411
2017263e
BG		 412 return 0;
413}
414
415
416static int i915_interrupt_info(struct seq_file *m, void *data)
417{
418 struct drm_info_node *node = (struct drm_info_node *) m->private;
419 struct drm_device *dev = node->minor->dev;
420 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 421 struct intel_ring_buffer *ring;
9db4a9c7 422 int ret, i, pipe;
de227ef0
CW		 423
424 ret = mutex_lock_interruptible(&dev->struct_mutex);
425 if (ret)
426 return ret;
2017263e 427
7e231dbe
JB		 428 if (IS_VALLEYVIEW(dev)) {
429 seq_printf(m, "Display IER:\t%08x\n",
430 I915_READ(VLV_IER));
431 seq_printf(m, "Display IIR:\t%08x\n",
432 I915_READ(VLV_IIR));
433 seq_printf(m, "Display IIR_RW:\t%08x\n",
434 I915_READ(VLV_IIR_RW));
435 seq_printf(m, "Display IMR:\t%08x\n",
436 I915_READ(VLV_IMR));
437 for_each_pipe(pipe)
438 seq_printf(m, "Pipe %c stat:\t%08x\n",
439 pipe_name(pipe),
440 I915_READ(PIPESTAT(pipe)));
441
442 seq_printf(m, "Master IER:\t%08x\n",
443 I915_READ(VLV_MASTER_IER));
444
445 seq_printf(m, "Render IER:\t%08x\n",
446 I915_READ(GTIER));
447 seq_printf(m, "Render IIR:\t%08x\n",
448 I915_READ(GTIIR));
449 seq_printf(m, "Render IMR:\t%08x\n",
450 I915_READ(GTIMR));
451
452 seq_printf(m, "PM IER:\t\t%08x\n",
453 I915_READ(GEN6_PMIER));
454 seq_printf(m, "PM IIR:\t\t%08x\n",
455 I915_READ(GEN6_PMIIR));
456 seq_printf(m, "PM IMR:\t\t%08x\n",
457 I915_READ(GEN6_PMIMR));
458
459 seq_printf(m, "Port hotplug:\t%08x\n",
460 I915_READ(PORT_HOTPLUG_EN));
461 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
462 I915_READ(VLV_DPFLIPSTAT));
463 seq_printf(m, "DPINVGTT:\t%08x\n",
464 I915_READ(DPINVGTT));
465
466 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 467 seq_printf(m, "Interrupt enable: %08x\n",
468 I915_READ(IER));
469 seq_printf(m, "Interrupt identity: %08x\n",
470 I915_READ(IIR));
471 seq_printf(m, "Interrupt mask: %08x\n",
472 I915_READ(IMR));
9db4a9c7
JB		 473 for_each_pipe(pipe)
474 seq_printf(m, "Pipe %c stat: %08x\n",
475 pipe_name(pipe),
476 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 477 } else {
478 seq_printf(m, "North Display Interrupt enable: %08x\n",
479 I915_READ(DEIER));
480 seq_printf(m, "North Display Interrupt identity: %08x\n",
481 I915_READ(DEIIR));
482 seq_printf(m, "North Display Interrupt mask: %08x\n",
483 I915_READ(DEIMR));
484 seq_printf(m, "South Display Interrupt enable: %08x\n",
485 I915_READ(SDEIER));
486 seq_printf(m, "South Display Interrupt identity: %08x\n",
487 I915_READ(SDEIIR));
488 seq_printf(m, "South Display Interrupt mask: %08x\n",
489 I915_READ(SDEIMR));
490 seq_printf(m, "Graphics Interrupt enable: %08x\n",
491 I915_READ(GTIER));
492 seq_printf(m, "Graphics Interrupt identity: %08x\n",
493 I915_READ(GTIIR));
494 seq_printf(m, "Graphics Interrupt mask: %08x\n",
495 I915_READ(GTIMR));
496 }
2017263e
BG		 497 seq_printf(m, "Interrupts received: %d\n",
498 atomic_read(&dev_priv->irq_received));
a2c7f6fd 499 for_each_ring(ring, dev_priv, i) {
da64c6fc 500 if (IS_GEN6(dev) || IS_GEN7(dev)) {
a2c7f6fd
CW		 501 seq_printf(m,
502 "Graphics Interrupt mask (%s): %08x\n",
503 ring->name, I915_READ_IMR(ring));
9862e600 504 }
a2c7f6fd 505 i915_ring_seqno_info(m, ring);
9862e600 506 }
de227ef0
CW		 507 mutex_unlock(&dev->struct_mutex);
508
2017263e
BG		 509 return 0;
510}
511
a6172a80
CW		 512static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
513{
514 struct drm_info_node *node = (struct drm_info_node *) m->private;
515 struct drm_device *dev = node->minor->dev;
516 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 517 int i, ret;
518
519 ret = mutex_lock_interruptible(&dev->struct_mutex);
520 if (ret)
521 return ret;
a6172a80
CW		 522
523 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
524 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
525 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 526 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 527
6c085a72
CW		 528 seq_printf(m, "Fence %d, pin count = %d, object = ",
529 i, dev_priv->fence_regs[i].pin_count);
c2c347a9
CW		 530 if (obj == NULL)
531 seq_printf(m, "unused");
532 else
05394f39 533 describe_obj(m, obj);
c2c347a9 534 seq_printf(m, "\n");
a6172a80
CW		 535 }
536
05394f39 537 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 538 return 0;
539}
540
2017263e
BG		 541static int i915_hws_info(struct seq_file *m, void *data)
542{
543 struct drm_info_node *node = (struct drm_info_node *) m->private;
544 struct drm_device *dev = node->minor->dev;
545 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 546 struct intel_ring_buffer *ring;
311bd68e 547 const volatile u32 __iomem *hws;
4066c0ae
CW		 548 int i;
549
1ec14ad3 550 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
311bd68e 551 hws = (volatile u32 __iomem *)ring->status_page.page_addr;
2017263e
BG		 552 if (hws == NULL)
553 return 0;
554
555 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
556 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
557 i * 4,
558 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
559 }
560 return 0;
561}
562
e5c65260
CW		 563static const char *ring_str(int ring)
564{
565 switch (ring) {
96154f2f
DV		 566 case RCS: return "render";
567 case VCS: return "bsd";
568 case BCS: return "blt";
e5c65260
CW		 569 default: return "";
570 }
571}
572
9df30794
CW		 573static const char *pin_flag(int pinned)
574{
575 if (pinned > 0)
576 return " P";
577 else if (pinned < 0)
578 return " p";
579 else
580 return "";
581}
582
583static const char *tiling_flag(int tiling)
584{
585 switch (tiling) {
586 default:
587 case I915_TILING_NONE: return "";
588 case I915_TILING_X: return " X";
589 case I915_TILING_Y: return " Y";
590 }
591}
592
593static const char *dirty_flag(int dirty)
594{
595 return dirty ? " dirty" : "";
596}
597
598static const char *purgeable_flag(int purgeable)
599{
600 return purgeable ? " purgeable" : "";
601}
602
c724e8a9
CW		 603static void print_error_buffers(struct seq_file *m,
604 const char *name,
605 struct drm_i915_error_buffer *err,
606 int count)
607{
608 seq_printf(m, "%s [%d]:\n", name, count);
609
610 while (count--) {
0201f1ec 611 seq_printf(m, " %08x %8u %04x %04x %x %x%s%s%s%s%s%s%s",
c724e8a9
CW		 612 err->gtt_offset,
613 err->size,
614 err->read_domains,
615 err->write_domain,
0201f1ec 616 err->rseqno, err->wseqno,
c724e8a9
CW		 617 pin_flag(err->pinned),
618 tiling_flag(err->tiling),
619 dirty_flag(err->dirty),
620 purgeable_flag(err->purgeable),
96154f2f 621 err->ring != -1 ? " " : "",
a779e5ab 622 ring_str(err->ring),
93dfb40c 623 cache_level_str(err->cache_level));
c724e8a9
CW		 624
625 if (err->name)
626 seq_printf(m, " (name: %d)", err->name);
627 if (err->fence_reg != I915_FENCE_REG_NONE)
628 seq_printf(m, " (fence: %d)", err->fence_reg);
629
630 seq_printf(m, "\n");
631 err++;
632 }
633}
634
d27b1e0e
DV		 635static void i915_ring_error_state(struct seq_file *m,
636 struct drm_device *dev,
637 struct drm_i915_error_state *error,
638 unsigned ring)
639{
ec34a01d 640 BUG_ON(ring >= I915_NUM_RINGS); /* shut up confused gcc */
d27b1e0e 641 seq_printf(m, "%s command stream:\n", ring_str(ring));
c1cd90ed
DV		 642 seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
643 seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
d27b1e0e
DV		 644 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
645 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
646 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
647 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
050ee91f 648 if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
c1cd90ed 649 seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
050ee91f 650
c1cd90ed
DV		 651 if (INTEL_INFO(dev)->gen >= 4)
652 seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
653 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
9d2f41fa 654 seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
33f3f518 655 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 656 seq_printf(m, " RC PSMI: 0x%08x\n", error->rc_psmi[ring]);
33f3f518 657 seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
df2b23d9
CW		 658 seq_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
659 error->semaphore_mboxes[ring][0],
660 error->semaphore_seqno[ring][0]);
661 seq_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
662 error->semaphore_mboxes[ring][1],
663 error->semaphore_seqno[ring][1]);
33f3f518 664 }
d27b1e0e 665 seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
9574b3fe 666 seq_printf(m, " waiting: %s\n", yesno(error->waiting[ring]));
7e3b8737
DV		 667 seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
668 seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
d27b1e0e
DV		 669}
670
d5442303
DV		 671struct i915_error_state_file_priv {
672 struct drm_device *dev;
673 struct drm_i915_error_state *error;
674};
675
63eeaf38
JB		 676static int i915_error_state(struct seq_file *m, void *unused)
677{
d5442303
DV		 678 struct i915_error_state_file_priv *error_priv = m->private;
679 struct drm_device *dev = error_priv->dev;
63eeaf38 680 drm_i915_private_t *dev_priv = dev->dev_private;
d5442303 681 struct drm_i915_error_state *error = error_priv->error;
b4519513 682 struct intel_ring_buffer *ring;
52d39a21 683 int i, j, page, offset, elt;
63eeaf38 684
742cbee8 685 if (!error) {
63eeaf38 686 seq_printf(m, "no error state collected\n");
742cbee8 687 return 0;
63eeaf38
JB		 688 }
689
8a905236
JB		 690 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
691 error->time.tv_usec);
9df30794 692 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
1d8f38f4 693 seq_printf(m, "EIR: 0x%08x\n", error->eir);
be998e2e 694 seq_printf(m, "IER: 0x%08x\n", error->ier);
1d8f38f4 695 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
b9a3906b 696 seq_printf(m, "CCID: 0x%08x\n", error->ccid);
9df30794 697
bf3301ab 698 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 699 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
700
050ee91f
BW		 701 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
702 seq_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]);
703
33f3f518 704 if (INTEL_INFO(dev)->gen >= 6) {
d27b1e0e 705 seq_printf(m, "ERROR: 0x%08x\n", error->error);
33f3f518
DV		 706 seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
707 }
d27b1e0e 708
71e172e8
BW		 709 if (INTEL_INFO(dev)->gen == 7)
710 seq_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
711
b4519513
CW		 712 for_each_ring(ring, dev_priv, i)
713 i915_ring_error_state(m, dev, error, i);
d27b1e0e 714
c724e8a9
CW		 715 if (error->active_bo)
716 print_error_buffers(m, "Active",
717 error->active_bo,
718 error->active_bo_count);
719
720 if (error->pinned_bo)
721 print_error_buffers(m, "Pinned",
722 error->pinned_bo,
723 error->pinned_bo_count);
9df30794 724
52d39a21
CW		 725 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
726 struct drm_i915_error_object *obj;
9df30794 727
52d39a21 728 if ((obj = error->ring[i].batchbuffer)) {
bcfb2e28
CW		 729 seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
730 dev_priv->ring[i].name,
731 obj->gtt_offset);
9df30794
CW		 732 offset = 0;
733 for (page = 0; page < obj->page_count; page++) {
734 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
735 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
736 offset += 4;
737 }
738 }
739 }
9df30794 740
52d39a21
CW		 741 if (error->ring[i].num_requests) {
742 seq_printf(m, "%s --- %d requests\n",
743 dev_priv->ring[i].name,
744 error->ring[i].num_requests);
745 for (j = 0; j < error->ring[i].num_requests; j++) {
ee4f42b1 746 seq_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
52d39a21 747 error->ring[i].requests[j].seqno,
ee4f42b1
CW		 748 error->ring[i].requests[j].jiffies,
749 error->ring[i].requests[j].tail);
52d39a21
CW		 750 }
751 }
752
753 if ((obj = error->ring[i].ringbuffer)) {
e2f973d5
CW		 754 seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
755 dev_priv->ring[i].name,
756 obj->gtt_offset);
757 offset = 0;
758 for (page = 0; page < obj->page_count; page++) {
759 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
760 seq_printf(m, "%08x : %08x\n",
761 offset,
762 obj->pages[page][elt]);
763 offset += 4;
764 }
9df30794
CW		 765 }
766 }
767 }
63eeaf38 768
6ef3d427
CW		 769 if (error->overlay)
770 intel_overlay_print_error_state(m, error->overlay);
771
c4a1d9e4
CW		 772 if (error->display)
773 intel_display_print_error_state(m, dev, error->display);
774
63eeaf38
JB		 775 return 0;
776}
6911a9b8 777
d5442303
DV		 778static ssize_t
779i915_error_state_write(struct file *filp,
780 const char __user *ubuf,
781 size_t cnt,
782 loff_t *ppos)
783{
784 struct seq_file *m = filp->private_data;
785 struct i915_error_state_file_priv *error_priv = m->private;
786 struct drm_device *dev = error_priv->dev;
22bcfc6a 787 int ret;
d5442303
DV		 788
789 DRM_DEBUG_DRIVER("Resetting error state\n");
790
22bcfc6a
DV		 791 ret = mutex_lock_interruptible(&dev->struct_mutex);
792 if (ret)
793 return ret;
794
d5442303
DV		 795 i915_destroy_error_state(dev);
796 mutex_unlock(&dev->struct_mutex);
797
798 return cnt;
799}
800
801static int i915_error_state_open(struct inode *inode, struct file *file)
802{
803 struct drm_device *dev = inode->i_private;
804 drm_i915_private_t *dev_priv = dev->dev_private;
805 struct i915_error_state_file_priv *error_priv;
806 unsigned long flags;
807
808 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
809 if (!error_priv)
810 return -ENOMEM;
811
812 error_priv->dev = dev;
813
814 spin_lock_irqsave(&dev_priv->error_lock, flags);
815 error_priv->error = dev_priv->first_error;
816 if (error_priv->error)
817 kref_get(&error_priv->error->ref);
818 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
819
820 return single_open(file, i915_error_state, error_priv);
821}
822
823static int i915_error_state_release(struct inode *inode, struct file *file)
824{
825 struct seq_file *m = file->private_data;
826 struct i915_error_state_file_priv *error_priv = m->private;
827
828 if (error_priv->error)
829 kref_put(&error_priv->error->ref, i915_error_state_free);
830 kfree(error_priv);
831
832 return single_release(inode, file);
833}
834
835static const struct file_operations i915_error_state_fops = {
836 .owner = THIS_MODULE,
837 .open = i915_error_state_open,
838 .read = seq_read,
839 .write = i915_error_state_write,
840 .llseek = default_llseek,
841 .release = i915_error_state_release,
842};
843
f97108d1
JB		 844static int i915_rstdby_delays(struct seq_file *m, void *unused)
845{
846 struct drm_info_node *node = (struct drm_info_node *) m->private;
847 struct drm_device *dev = node->minor->dev;
848 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 849 u16 crstanddelay;
850 int ret;
851
852 ret = mutex_lock_interruptible(&dev->struct_mutex);
853 if (ret)
854 return ret;
855
856 crstanddelay = I915_READ16(CRSTANDVID);
857
858 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 859
860 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
861
862 return 0;
863}
864
865static int i915_cur_delayinfo(struct seq_file *m, void *unused)
866{
867 struct drm_info_node *node = (struct drm_info_node *) m->private;
868 struct drm_device *dev = node->minor->dev;
869 drm_i915_private_t *dev_priv = dev->dev_private;
d1ebd816 870 int ret;
3b8d8d91
JB		 871
872 if (IS_GEN5(dev)) {
873 u16 rgvswctl = I915_READ16(MEMSWCTL);
874 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
875
876 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
877 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
878 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
879 MEMSTAT_VID_SHIFT);
880 seq_printf(m, "Current P-state: %d\n",
881 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1c70c0ce 882 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91
JB		 883 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
884 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
885 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
ccab5c82
JB		 886 u32 rpstat;
887 u32 rpupei, rpcurup, rpprevup;
888 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 889 int max_freq;
890
891 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 892 ret = mutex_lock_interruptible(&dev->struct_mutex);
893 if (ret)
894 return ret;
895
fcca7926 896 gen6_gt_force_wake_get(dev_priv);
3b8d8d91 897
ccab5c82
JB		 898 rpstat = I915_READ(GEN6_RPSTAT1);
899 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
900 rpcurup = I915_READ(GEN6_RP_CUR_UP);
901 rpprevup = I915_READ(GEN6_RP_PREV_UP);
902 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
903 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
904 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
905
d1ebd816
BW		 906 gen6_gt_force_wake_put(dev_priv);
907 mutex_unlock(&dev->struct_mutex);
908
3b8d8d91 909 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 910 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 911 seq_printf(m, "Render p-state ratio: %d\n",
912 (gt_perf_status & 0xff00) >> 8);
913 seq_printf(m, "Render p-state VID: %d\n",
914 gt_perf_status & 0xff);
915 seq_printf(m, "Render p-state limit: %d\n",
916 rp_state_limits & 0xff);
ccab5c82 917 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
c8735b0c 918 GEN6_CAGF_SHIFT) * GT_FREQUENCY_MULTIPLIER);
ccab5c82
JB		 919 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
920 GEN6_CURICONT_MASK);
921 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
922 GEN6_CURBSYTAVG_MASK);
923 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
924 GEN6_CURBSYTAVG_MASK);
925 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
926 GEN6_CURIAVG_MASK);
927 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
928 GEN6_CURBSYTAVG_MASK);
929 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
930 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 931
932 max_freq = (rp_state_cap & 0xff0000) >> 16;
933 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 934 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 935
936 max_freq = (rp_state_cap & 0xff00) >> 8;
937 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 938 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 939
940 max_freq = rp_state_cap & 0xff;
941 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 942 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 943 } else {
944 seq_printf(m, "no P-state info available\n");
945 }
f97108d1
JB		 946
947 return 0;
948}
949
950static int i915_delayfreq_table(struct seq_file *m, void *unused)
951{
952 struct drm_info_node *node = (struct drm_info_node *) m->private;
953 struct drm_device *dev = node->minor->dev;
954 drm_i915_private_t *dev_priv = dev->dev_private;
955 u32 delayfreq;
616fdb5a
BW		 956 int ret, i;
957
958 ret = mutex_lock_interruptible(&dev->struct_mutex);
959 if (ret)
960 return ret;
f97108d1
JB		 961
962 for (i = 0; i < 16; i++) {
963 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 964 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
965 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 966 }
967
616fdb5a
BW		 968 mutex_unlock(&dev->struct_mutex);
969
f97108d1
JB		 970 return 0;
971}
972
973static inline int MAP_TO_MV(int map)
974{
975 return 1250 - (map * 25);
976}
977
978static int i915_inttoext_table(struct seq_file *m, void *unused)
979{
980 struct drm_info_node *node = (struct drm_info_node *) m->private;
981 struct drm_device *dev = node->minor->dev;
982 drm_i915_private_t *dev_priv = dev->dev_private;
983 u32 inttoext;
616fdb5a
BW		 984 int ret, i;
985
986 ret = mutex_lock_interruptible(&dev->struct_mutex);
987 if (ret)
988 return ret;
f97108d1
JB		 989
990 for (i = 1; i <= 32; i++) {
991 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
992 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
993 }
994
616fdb5a
BW		 995 mutex_unlock(&dev->struct_mutex);
996
f97108d1
JB		 997 return 0;
998}
999
4d85529d 1000static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1001{
1002 struct drm_info_node *node = (struct drm_info_node *) m->private;
1003 struct drm_device *dev = node->minor->dev;
1004 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1005 u32 rgvmodectl, rstdbyctl;
1006 u16 crstandvid;
1007 int ret;
1008
1009 ret = mutex_lock_interruptible(&dev->struct_mutex);
1010 if (ret)
1011 return ret;
1012
1013 rgvmodectl = I915_READ(MEMMODECTL);
1014 rstdbyctl = I915_READ(RSTDBYCTL);
1015 crstandvid = I915_READ16(CRSTANDVID);
1016
1017 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1018
1019 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1020 "yes" : "no");
1021 seq_printf(m, "Boost freq: %d\n",
1022 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1023 MEMMODE_BOOST_FREQ_SHIFT);
1024 seq_printf(m, "HW control enabled: %s\n",
1025 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1026 seq_printf(m, "SW control enabled: %s\n",
1027 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1028 seq_printf(m, "Gated voltage change: %s\n",
1029 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1030 seq_printf(m, "Starting frequency: P%d\n",
1031 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1032 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1033 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1034 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1035 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1036 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1037 seq_printf(m, "Render standby enabled: %s\n",
1038 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
88271da3
JB		 1039 seq_printf(m, "Current RS state: ");
1040 switch (rstdbyctl & RSX_STATUS_MASK) {
1041 case RSX_STATUS_ON:
1042 seq_printf(m, "on\n");
1043 break;
1044 case RSX_STATUS_RC1:
1045 seq_printf(m, "RC1\n");
1046 break;
1047 case RSX_STATUS_RC1E:
1048 seq_printf(m, "RC1E\n");
1049 break;
1050 case RSX_STATUS_RS1:
1051 seq_printf(m, "RS1\n");
1052 break;
1053 case RSX_STATUS_RS2:
1054 seq_printf(m, "RS2 (RC6)\n");
1055 break;
1056 case RSX_STATUS_RS3:
1057 seq_printf(m, "RC3 (RC6+)\n");
1058 break;
1059 default:
1060 seq_printf(m, "unknown\n");
1061 break;
1062 }
f97108d1
JB		 1063
1064 return 0;
1065}
1066
4d85529d
BW		 1067static int gen6_drpc_info(struct seq_file *m)
1068{
1069
1070 struct drm_info_node *node = (struct drm_info_node *) m->private;
1071 struct drm_device *dev = node->minor->dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1073 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1074 unsigned forcewake_count;
4d85529d
BW		 1075 int count=0, ret;
1076
1077
1078 ret = mutex_lock_interruptible(&dev->struct_mutex);
1079 if (ret)
1080 return ret;
1081
93b525dc
DV		 1082 spin_lock_irq(&dev_priv->gt_lock);
1083 forcewake_count = dev_priv->forcewake_count;
1084 spin_unlock_irq(&dev_priv->gt_lock);
1085
1086 if (forcewake_count) {
1087 seq_printf(m, "RC information inaccurate because somebody "
1088 "holds a forcewake reference \n");
4d85529d
BW		 1089 } else {
1090 /* NB: we cannot use forcewake, else we read the wrong values */
1091 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1092 udelay(10);
1093 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1094 }
1095
1096 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1097 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1098
1099 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1100 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1101 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1102 mutex_lock(&dev_priv->rps.hw_lock);
1103 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1104 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d
BW		 1105
1106 seq_printf(m, "Video Turbo Mode: %s\n",
1107 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1108 seq_printf(m, "HW control enabled: %s\n",
1109 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1110 seq_printf(m, "SW control enabled: %s\n",
1111 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1112 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1113 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1114 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1115 seq_printf(m, "RC6 Enabled: %s\n",
1116 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1117 seq_printf(m, "Deep RC6 Enabled: %s\n",
1118 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1119 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1120 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1121 seq_printf(m, "Current RC state: ");
1122 switch (gt_core_status & GEN6_RCn_MASK) {
1123 case GEN6_RC0:
1124 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1125 seq_printf(m, "Core Power Down\n");
1126 else
1127 seq_printf(m, "on\n");
1128 break;
1129 case GEN6_RC3:
1130 seq_printf(m, "RC3\n");
1131 break;
1132 case GEN6_RC6:
1133 seq_printf(m, "RC6\n");
1134 break;
1135 case GEN6_RC7:
1136 seq_printf(m, "RC7\n");
1137 break;
1138 default:
1139 seq_printf(m, "Unknown\n");
1140 break;
1141 }
1142
1143 seq_printf(m, "Core Power Down: %s\n",
1144 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1145
1146 /* Not exactly sure what this is */
1147 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1148 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1149 seq_printf(m, "RC6 residency since boot: %u\n",
1150 I915_READ(GEN6_GT_GFX_RC6));
1151 seq_printf(m, "RC6+ residency since boot: %u\n",
1152 I915_READ(GEN6_GT_GFX_RC6p));
1153 seq_printf(m, "RC6++ residency since boot: %u\n",
1154 I915_READ(GEN6_GT_GFX_RC6pp));
1155
ecd8faea
BW		 1156 seq_printf(m, "RC6 voltage: %dmV\n",
1157 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1158 seq_printf(m, "RC6+ voltage: %dmV\n",
1159 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1160 seq_printf(m, "RC6++ voltage: %dmV\n",
1161 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1162 return 0;
1163}
1164
1165static int i915_drpc_info(struct seq_file *m, void *unused)
1166{
1167 struct drm_info_node *node = (struct drm_info_node *) m->private;
1168 struct drm_device *dev = node->minor->dev;
1169
1170 if (IS_GEN6(dev) || IS_GEN7(dev))
1171 return gen6_drpc_info(m);
1172 else
1173 return ironlake_drpc_info(m);
1174}
1175
b5e50c3f
JB		 1176static int i915_fbc_status(struct seq_file *m, void *unused)
1177{
1178 struct drm_info_node *node = (struct drm_info_node *) m->private;
1179 struct drm_device *dev = node->minor->dev;
b5e50c3f 1180 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1181
ee5382ae 1182 if (!I915_HAS_FBC(dev)) {
b5e50c3f
JB		 1183 seq_printf(m, "FBC unsupported on this chipset\n");
1184 return 0;
1185 }
1186
ee5382ae 1187 if (intel_fbc_enabled(dev)) {
b5e50c3f
JB		 1188 seq_printf(m, "FBC enabled\n");
1189 } else {
1190 seq_printf(m, "FBC disabled: ");
1191 switch (dev_priv->no_fbc_reason) {
bed4a673
CW		 1192 case FBC_NO_OUTPUT:
1193 seq_printf(m, "no outputs");
1194 break;
b5e50c3f
JB		 1195 case FBC_STOLEN_TOO_SMALL:
1196 seq_printf(m, "not enough stolen memory");
1197 break;
1198 case FBC_UNSUPPORTED_MODE:
1199 seq_printf(m, "mode not supported");
1200 break;
1201 case FBC_MODE_TOO_LARGE:
1202 seq_printf(m, "mode too large");
1203 break;
1204 case FBC_BAD_PLANE:
1205 seq_printf(m, "FBC unsupported on plane");
1206 break;
1207 case FBC_NOT_TILED:
1208 seq_printf(m, "scanout buffer not tiled");
1209 break;
9c928d16
JB		 1210 case FBC_MULTIPLE_PIPES:
1211 seq_printf(m, "multiple pipes are enabled");
1212 break;
c1a9f047
JB		 1213 case FBC_MODULE_PARAM:
1214 seq_printf(m, "disabled per module param (default off)");
1215 break;
b5e50c3f
JB		 1216 default:
1217 seq_printf(m, "unknown reason");
1218 }
1219 seq_printf(m, "\n");
1220 }
1221 return 0;
1222}
1223
4a9bef37
JB		 1224static int i915_sr_status(struct seq_file *m, void *unused)
1225{
1226 struct drm_info_node *node = (struct drm_info_node *) m->private;
1227 struct drm_device *dev = node->minor->dev;
1228 drm_i915_private_t *dev_priv = dev->dev_private;
1229 bool sr_enabled = false;
1230
1398261a 1231 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1232 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1233 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1234 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1235 else if (IS_I915GM(dev))
1236 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1237 else if (IS_PINEVIEW(dev))
1238 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1239
5ba2aaaa
CW		 1240 seq_printf(m, "self-refresh: %s\n",
1241 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1242
1243 return 0;
1244}
1245
7648fa99
JB		 1246static int i915_emon_status(struct seq_file *m, void *unused)
1247{
1248 struct drm_info_node *node = (struct drm_info_node *) m->private;
1249 struct drm_device *dev = node->minor->dev;
1250 drm_i915_private_t *dev_priv = dev->dev_private;
1251 unsigned long temp, chipset, gfx;
de227ef0
CW		 1252 int ret;
1253
582be6b4
CW		 1254 if (!IS_GEN5(dev))
1255 return -ENODEV;
1256
de227ef0
CW		 1257 ret = mutex_lock_interruptible(&dev->struct_mutex);
1258 if (ret)
1259 return ret;
7648fa99
JB		 1260
1261 temp = i915_mch_val(dev_priv);
1262 chipset = i915_chipset_val(dev_priv);
1263 gfx = i915_gfx_val(dev_priv);
de227ef0 1264 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1265
1266 seq_printf(m, "GMCH temp: %ld\n", temp);
1267 seq_printf(m, "Chipset power: %ld\n", chipset);
1268 seq_printf(m, "GFX power: %ld\n", gfx);
1269 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1270
1271 return 0;
1272}
1273
23b2f8bb
JB		 1274static int i915_ring_freq_table(struct seq_file *m, void *unused)
1275{
1276 struct drm_info_node *node = (struct drm_info_node *) m->private;
1277 struct drm_device *dev = node->minor->dev;
1278 drm_i915_private_t *dev_priv = dev->dev_private;
1279 int ret;
1280 int gpu_freq, ia_freq;
1281
1c70c0ce 1282 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
23b2f8bb
JB		 1283 seq_printf(m, "unsupported on this chipset\n");
1284 return 0;
1285 }
1286
4fc688ce 1287 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1288 if (ret)
1289 return ret;
1290
1291 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1292
c6a828d3
DV		 1293 for (gpu_freq = dev_priv->rps.min_delay;
1294 gpu_freq <= dev_priv->rps.max_delay;
23b2f8bb 1295 gpu_freq++) {
42c0526c
BW		 1296 ia_freq = gpu_freq;
1297 sandybridge_pcode_read(dev_priv,
1298 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1299 &ia_freq);
c8735b0c 1300 seq_printf(m, "%d\t\t%d\n", gpu_freq * GT_FREQUENCY_MULTIPLIER, ia_freq * 100);
23b2f8bb
JB		 1301 }
1302
4fc688ce 1303 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb
JB		 1304
1305 return 0;
1306}
1307
7648fa99
JB		 1308static int i915_gfxec(struct seq_file *m, void *unused)
1309{
1310 struct drm_info_node *node = (struct drm_info_node *) m->private;
1311 struct drm_device *dev = node->minor->dev;
1312 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1313 int ret;
1314
1315 ret = mutex_lock_interruptible(&dev->struct_mutex);
1316 if (ret)
1317 return ret;
7648fa99
JB		 1318
1319 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1320
616fdb5a
BW		 1321 mutex_unlock(&dev->struct_mutex);
1322
7648fa99
JB		 1323 return 0;
1324}
1325
44834a67
CW		 1326static int i915_opregion(struct seq_file *m, void *unused)
1327{
1328 struct drm_info_node *node = (struct drm_info_node *) m->private;
1329 struct drm_device *dev = node->minor->dev;
1330 drm_i915_private_t *dev_priv = dev->dev_private;
1331 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1332 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1333 int ret;
1334
0d38f009
DV		 1335 if (data == NULL)
1336 return -ENOMEM;
1337
44834a67
CW		 1338 ret = mutex_lock_interruptible(&dev->struct_mutex);
1339 if (ret)
0d38f009 1340 goto out;
44834a67 1341
0d38f009
DV		 1342 if (opregion->header) {
1343 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1344 seq_write(m, data, OPREGION_SIZE);
1345 }
44834a67
CW		 1346
1347 mutex_unlock(&dev->struct_mutex);
1348
0d38f009
DV		 1349out:
1350 kfree(data);
44834a67
CW		 1351 return 0;
1352}
1353
37811fcc
CW		 1354static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1355{
1356 struct drm_info_node *node = (struct drm_info_node *) m->private;
1357 struct drm_device *dev = node->minor->dev;
1358 drm_i915_private_t *dev_priv = dev->dev_private;
1359 struct intel_fbdev *ifbdev;
1360 struct intel_framebuffer *fb;
1361 int ret;
1362
1363 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1364 if (ret)
1365 return ret;
1366
1367 ifbdev = dev_priv->fbdev;
1368 fb = to_intel_framebuffer(ifbdev->helper.fb);
1369
1370 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1371 fb->base.width,
1372 fb->base.height,
1373 fb->base.depth,
1374 fb->base.bits_per_pixel);
05394f39 1375 describe_obj(m, fb->obj);
37811fcc 1376 seq_printf(m, "\n");
4b096ac1 1377 mutex_unlock(&dev->mode_config.mutex);
37811fcc 1378
4b096ac1 1379 mutex_lock(&dev->mode_config.fb_lock);
37811fcc
CW		 1380 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1381 if (&fb->base == ifbdev->helper.fb)
1382 continue;
1383
1384 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1385 fb->base.width,
1386 fb->base.height,
1387 fb->base.depth,
1388 fb->base.bits_per_pixel);
05394f39 1389 describe_obj(m, fb->obj);
37811fcc
CW		 1390 seq_printf(m, "\n");
1391 }
4b096ac1 1392 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1393
1394 return 0;
1395}
1396
e76d3630
BW		 1397static int i915_context_status(struct seq_file *m, void *unused)
1398{
1399 struct drm_info_node *node = (struct drm_info_node *) m->private;
1400 struct drm_device *dev = node->minor->dev;
1401 drm_i915_private_t *dev_priv = dev->dev_private;
1402 int ret;
1403
1404 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1405 if (ret)
1406 return ret;
1407
3e373948 1408 if (dev_priv->ips.pwrctx) {
dc501fbc 1409 seq_printf(m, "power context ");
3e373948 1410 describe_obj(m, dev_priv->ips.pwrctx);
dc501fbc
BW		 1411 seq_printf(m, "\n");
1412 }
e76d3630 1413
3e373948 1414 if (dev_priv->ips.renderctx) {
dc501fbc 1415 seq_printf(m, "render context ");
3e373948 1416 describe_obj(m, dev_priv->ips.renderctx);
dc501fbc
BW		 1417 seq_printf(m, "\n");
1418 }
e76d3630
BW		 1419
1420 mutex_unlock(&dev->mode_config.mutex);
1421
1422 return 0;
1423}
1424
6d794d42
BW		 1425static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1426{
1427 struct drm_info_node *node = (struct drm_info_node *) m->private;
1428 struct drm_device *dev = node->minor->dev;
1429 struct drm_i915_private *dev_priv = dev->dev_private;
9f1f46a4 1430 unsigned forcewake_count;
6d794d42 1431
9f1f46a4
DV		 1432 spin_lock_irq(&dev_priv->gt_lock);
1433 forcewake_count = dev_priv->forcewake_count;
1434 spin_unlock_irq(&dev_priv->gt_lock);
6d794d42 1435
9f1f46a4 1436 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1437
1438 return 0;
1439}
1440
ea16a3cd
DV		 1441static const char *swizzle_string(unsigned swizzle)
1442{
1443 switch(swizzle) {
1444 case I915_BIT_6_SWIZZLE_NONE:
1445 return "none";
1446 case I915_BIT_6_SWIZZLE_9:
1447 return "bit9";
1448 case I915_BIT_6_SWIZZLE_9_10:
1449 return "bit9/bit10";
1450 case I915_BIT_6_SWIZZLE_9_11:
1451 return "bit9/bit11";
1452 case I915_BIT_6_SWIZZLE_9_10_11:
1453 return "bit9/bit10/bit11";
1454 case I915_BIT_6_SWIZZLE_9_17:
1455 return "bit9/bit17";
1456 case I915_BIT_6_SWIZZLE_9_10_17:
1457 return "bit9/bit10/bit17";
1458 case I915_BIT_6_SWIZZLE_UNKNOWN:
1459 return "unkown";
1460 }
1461
1462 return "bug";
1463}
1464
1465static int i915_swizzle_info(struct seq_file *m, void *data)
1466{
1467 struct drm_info_node *node = (struct drm_info_node *) m->private;
1468 struct drm_device *dev = node->minor->dev;
1469 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1470 int ret;
1471
1472 ret = mutex_lock_interruptible(&dev->struct_mutex);
1473 if (ret)
1474 return ret;
ea16a3cd 1475
ea16a3cd
DV		 1476 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1477 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1478 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1479 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1480
1481 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1482 seq_printf(m, "DDC = 0x%08x\n",
1483 I915_READ(DCC));
1484 seq_printf(m, "C0DRB3 = 0x%04x\n",
1485 I915_READ16(C0DRB3));
1486 seq_printf(m, "C1DRB3 = 0x%04x\n",
1487 I915_READ16(C1DRB3));
3fa7d235
DV		 1488 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1489 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1490 I915_READ(MAD_DIMM_C0));
1491 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1492 I915_READ(MAD_DIMM_C1));
1493 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1494 I915_READ(MAD_DIMM_C2));
1495 seq_printf(m, "TILECTL = 0x%08x\n",
1496 I915_READ(TILECTL));
1497 seq_printf(m, "ARB_MODE = 0x%08x\n",
1498 I915_READ(ARB_MODE));
1499 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1500 I915_READ(DISP_ARB_CTL));
ea16a3cd
DV		 1501 }
1502 mutex_unlock(&dev->struct_mutex);
1503
1504 return 0;
1505}
1506
3cf17fc5
DV		 1507static int i915_ppgtt_info(struct seq_file *m, void *data)
1508{
1509 struct drm_info_node *node = (struct drm_info_node *) m->private;
1510 struct drm_device *dev = node->minor->dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 struct intel_ring_buffer *ring;
1513 int i, ret;
1514
1515
1516 ret = mutex_lock_interruptible(&dev->struct_mutex);
1517 if (ret)
1518 return ret;
1519 if (INTEL_INFO(dev)->gen == 6)
1520 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1521
a2c7f6fd 1522 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1523 seq_printf(m, "%s\n", ring->name);
1524 if (INTEL_INFO(dev)->gen == 7)
1525 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1526 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1527 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1528 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1529 }
1530 if (dev_priv->mm.aliasing_ppgtt) {
1531 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1532
1533 seq_printf(m, "aliasing PPGTT:\n");
1534 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1535 }
1536 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1537 mutex_unlock(&dev->struct_mutex);
1538
1539 return 0;
1540}
1541
57f350b6
JB		 1542static int i915_dpio_info(struct seq_file *m, void *data)
1543{
1544 struct drm_info_node *node = (struct drm_info_node *) m->private;
1545 struct drm_device *dev = node->minor->dev;
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547 int ret;
1548
1549
1550 if (!IS_VALLEYVIEW(dev)) {
1551 seq_printf(m, "unsupported\n");
1552 return 0;
1553 }
1554
1555 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1556 if (ret)
1557 return ret;
1558
1559 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1560
1561 seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
1562 intel_dpio_read(dev_priv, _DPIO_DIV_A));
1563 seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
1564 intel_dpio_read(dev_priv, _DPIO_DIV_B));
1565
1566 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1567 intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
1568 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1569 intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
1570
1571 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1572 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1573 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1574 intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1575
1576 seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
1577 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
1578 seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
1579 intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
1580
1581 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1582 intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1583
1584 mutex_unlock(&dev->mode_config.mutex);
1585
1586 return 0;
1587}
1588
f3cd474b
CW		 1589static ssize_t
1590i915_wedged_read(struct file *filp,
1591 char __user *ubuf,
1592 size_t max,
1593 loff_t *ppos)
1594{
1595 struct drm_device *dev = filp->private_data;
1596 drm_i915_private_t *dev_priv = dev->dev_private;
1597 char buf[80];
1598 int len;
1599
0206e353 1600 len = snprintf(buf, sizeof(buf),
f3cd474b
CW		 1601 "wedged : %d\n",
1602 atomic_read(&dev_priv->mm.wedged));
1603
0206e353
AJ		 1604 if (len > sizeof(buf))
1605 len = sizeof(buf);
f4433a8d 1606
f3cd474b
CW		 1607 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1608}
1609
1610static ssize_t
1611i915_wedged_write(struct file *filp,
1612 const char __user *ubuf,
1613 size_t cnt,
1614 loff_t *ppos)
1615{
1616 struct drm_device *dev = filp->private_data;
f3cd474b
CW		 1617 char buf[20];
1618 int val = 1;
1619
1620 if (cnt > 0) {
0206e353 1621 if (cnt > sizeof(buf) - 1)
f3cd474b
CW		 1622 return -EINVAL;
1623
1624 if (copy_from_user(buf, ubuf, cnt))
1625 return -EFAULT;
1626 buf[cnt] = 0;
1627
1628 val = simple_strtoul(buf, NULL, 0);
1629 }
1630
1631 DRM_INFO("Manually setting wedged to %d\n", val);
527f9e90 1632 i915_handle_error(dev, val);
f3cd474b
CW		 1633
1634 return cnt;
1635}
1636
1637static const struct file_operations i915_wedged_fops = {
1638 .owner = THIS_MODULE,
234e3405 1639 .open = simple_open,
f3cd474b
CW		 1640 .read = i915_wedged_read,
1641 .write = i915_wedged_write,
6038f373 1642 .llseek = default_llseek,
f3cd474b
CW		 1643};
1644
e5eb3d63
DV		 1645static ssize_t
1646i915_ring_stop_read(struct file *filp,
1647 char __user *ubuf,
1648 size_t max,
1649 loff_t *ppos)
1650{
1651 struct drm_device *dev = filp->private_data;
1652 drm_i915_private_t *dev_priv = dev->dev_private;
1653 char buf[20];
1654 int len;
1655
1656 len = snprintf(buf, sizeof(buf),
1657 "0x%08x\n", dev_priv->stop_rings);
1658
1659 if (len > sizeof(buf))
1660 len = sizeof(buf);
1661
1662 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1663}
1664
1665static ssize_t
1666i915_ring_stop_write(struct file *filp,
1667 const char __user *ubuf,
1668 size_t cnt,
1669 loff_t *ppos)
1670{
1671 struct drm_device *dev = filp->private_data;
1672 struct drm_i915_private *dev_priv = dev->dev_private;
1673 char buf[20];
22bcfc6a 1674 int val = 0, ret;
e5eb3d63
DV		 1675
1676 if (cnt > 0) {
1677 if (cnt > sizeof(buf) - 1)
1678 return -EINVAL;
1679
1680 if (copy_from_user(buf, ubuf, cnt))
1681 return -EFAULT;
1682 buf[cnt] = 0;
1683
1684 val = simple_strtoul(buf, NULL, 0);
1685 }
1686
1687 DRM_DEBUG_DRIVER("Stopping rings 0x%08x\n", val);
1688
22bcfc6a
DV		 1689 ret = mutex_lock_interruptible(&dev->struct_mutex);
1690 if (ret)
1691 return ret;
1692
e5eb3d63
DV		 1693 dev_priv->stop_rings = val;
1694 mutex_unlock(&dev->struct_mutex);
1695
1696 return cnt;
1697}
1698
1699static const struct file_operations i915_ring_stop_fops = {
1700 .owner = THIS_MODULE,
1701 .open = simple_open,
1702 .read = i915_ring_stop_read,
1703 .write = i915_ring_stop_write,
1704 .llseek = default_llseek,
1705};
d5442303 1706
358733e9
JB		 1707static ssize_t
1708i915_max_freq_read(struct file *filp,
1709 char __user *ubuf,
1710 size_t max,
1711 loff_t *ppos)
1712{
1713 struct drm_device *dev = filp->private_data;
1714 drm_i915_private_t *dev_priv = dev->dev_private;
1715 char buf[80];
004777cb
DV		 1716 int len, ret;
1717
1718 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1719 return -ENODEV;
1720
4fc688ce 1721 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 1722 if (ret)
1723 return ret;
358733e9 1724
0206e353 1725 len = snprintf(buf, sizeof(buf),
c8735b0c 1726 "max freq: %d\n", dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER);
4fc688ce 1727 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 1728
0206e353
AJ		 1729 if (len > sizeof(buf))
1730 len = sizeof(buf);
358733e9
JB		 1731
1732 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1733}
1734
1735static ssize_t
1736i915_max_freq_write(struct file *filp,
1737 const char __user *ubuf,
1738 size_t cnt,
1739 loff_t *ppos)
1740{
1741 struct drm_device *dev = filp->private_data;
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 char buf[20];
004777cb
DV		 1744 int val = 1, ret;
1745
1746 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1747 return -ENODEV;
358733e9
JB		 1748
1749 if (cnt > 0) {
0206e353 1750 if (cnt > sizeof(buf) - 1)
358733e9
JB		 1751 return -EINVAL;
1752
1753 if (copy_from_user(buf, ubuf, cnt))
1754 return -EFAULT;
1755 buf[cnt] = 0;
1756
1757 val = simple_strtoul(buf, NULL, 0);
1758 }
1759
1760 DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
1761
4fc688ce 1762 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 1763 if (ret)
1764 return ret;
1765
358733e9
JB		 1766 /*
1767 * Turbo will still be enabled, but won't go above the set value.
1768 */
c8735b0c 1769 dev_priv->rps.max_delay = val / GT_FREQUENCY_MULTIPLIER;
358733e9 1770
c8735b0c 1771 gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
4fc688ce 1772 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9
JB		 1773
1774 return cnt;
1775}
1776
1777static const struct file_operations i915_max_freq_fops = {
1778 .owner = THIS_MODULE,
234e3405 1779 .open = simple_open,
358733e9
JB		 1780 .read = i915_max_freq_read,
1781 .write = i915_max_freq_write,
1782 .llseek = default_llseek,
1783};
1784
1523c310
JB		 1785static ssize_t
1786i915_min_freq_read(struct file *filp, char __user *ubuf, size_t max,
1787 loff_t *ppos)
1788{
1789 struct drm_device *dev = filp->private_data;
1790 drm_i915_private_t *dev_priv = dev->dev_private;
1791 char buf[80];
004777cb
DV		 1792 int len, ret;
1793
1794 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1795 return -ENODEV;
1796
4fc688ce 1797 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 1798 if (ret)
1799 return ret;
1523c310
JB		 1800
1801 len = snprintf(buf, sizeof(buf),
c8735b0c 1802 "min freq: %d\n", dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER);
4fc688ce 1803 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310
JB		 1804
1805 if (len > sizeof(buf))
1806 len = sizeof(buf);
1807
1808 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1809}
1810
1811static ssize_t
1812i915_min_freq_write(struct file *filp, const char __user *ubuf, size_t cnt,
1813 loff_t *ppos)
1814{
1815 struct drm_device *dev = filp->private_data;
1816 struct drm_i915_private *dev_priv = dev->dev_private;
1817 char buf[20];
004777cb
DV		 1818 int val = 1, ret;
1819
1820 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1821 return -ENODEV;
1523c310
JB		 1822
1823 if (cnt > 0) {
1824 if (cnt > sizeof(buf) - 1)
1825 return -EINVAL;
1826
1827 if (copy_from_user(buf, ubuf, cnt))
1828 return -EFAULT;
1829 buf[cnt] = 0;
1830
1831 val = simple_strtoul(buf, NULL, 0);
1832 }
1833
1834 DRM_DEBUG_DRIVER("Manually setting min freq to %d\n", val);
1835
4fc688ce 1836 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 1837 if (ret)
1838 return ret;
1839
1523c310
JB		 1840 /*
1841 * Turbo will still be enabled, but won't go below the set value.
1842 */
c8735b0c 1843 dev_priv->rps.min_delay = val / GT_FREQUENCY_MULTIPLIER;
1523c310 1844
c8735b0c 1845 gen6_set_rps(dev, val / GT_FREQUENCY_MULTIPLIER);
4fc688ce 1846 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310
JB		 1847
1848 return cnt;
1849}
1850
1851static const struct file_operations i915_min_freq_fops = {
1852 .owner = THIS_MODULE,
1853 .open = simple_open,
1854 .read = i915_min_freq_read,
1855 .write = i915_min_freq_write,
1856 .llseek = default_llseek,
1857};
1858
07b7ddd9
JB		 1859static ssize_t
1860i915_cache_sharing_read(struct file *filp,
1861 char __user *ubuf,
1862 size_t max,
1863 loff_t *ppos)
1864{
1865 struct drm_device *dev = filp->private_data;
1866 drm_i915_private_t *dev_priv = dev->dev_private;
1867 char buf[80];
1868 u32 snpcr;
22bcfc6a 1869 int len, ret;
07b7ddd9 1870
004777cb
DV		 1871 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1872 return -ENODEV;
1873
22bcfc6a
DV		 1874 ret = mutex_lock_interruptible(&dev->struct_mutex);
1875 if (ret)
1876 return ret;
1877
07b7ddd9
JB		 1878 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1879 mutex_unlock(&dev_priv->dev->struct_mutex);
1880
0206e353 1881 len = snprintf(buf, sizeof(buf),
07b7ddd9
JB		 1882 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
1883 GEN6_MBC_SNPCR_SHIFT);
1884
0206e353
AJ		 1885 if (len > sizeof(buf))
1886 len = sizeof(buf);
07b7ddd9
JB		 1887
1888 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1889}
1890
1891static ssize_t
1892i915_cache_sharing_write(struct file *filp,
1893 const char __user *ubuf,
1894 size_t cnt,
1895 loff_t *ppos)
1896{
1897 struct drm_device *dev = filp->private_data;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 char buf[20];
1900 u32 snpcr;
1901 int val = 1;
1902
004777cb
DV		 1903 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
1904 return -ENODEV;
1905
07b7ddd9 1906 if (cnt > 0) {
0206e353 1907 if (cnt > sizeof(buf) - 1)
07b7ddd9
JB		 1908 return -EINVAL;
1909
1910 if (copy_from_user(buf, ubuf, cnt))
1911 return -EFAULT;
1912 buf[cnt] = 0;
1913
1914 val = simple_strtoul(buf, NULL, 0);
1915 }
1916
1917 if (val < 0 || val > 3)
1918 return -EINVAL;
1919
1920 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
1921
1922 /* Update the cache sharing policy here as well */
1923 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1924 snpcr &= ~GEN6_MBC_SNPCR_MASK;
1925 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
1926 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1927
1928 return cnt;
1929}
1930
1931static const struct file_operations i915_cache_sharing_fops = {
1932 .owner = THIS_MODULE,
234e3405 1933 .open = simple_open,
07b7ddd9
JB		 1934 .read = i915_cache_sharing_read,
1935 .write = i915_cache_sharing_write,
1936 .llseek = default_llseek,
1937};
1938
f3cd474b
CW		 1939/* As the drm_debugfs_init() routines are called before dev->dev_private is
1940 * allocated we need to hook into the minor for release. */
1941static int
1942drm_add_fake_info_node(struct drm_minor *minor,
1943 struct dentry *ent,
1944 const void *key)
1945{
1946 struct drm_info_node *node;
1947
1948 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
1949 if (node == NULL) {
1950 debugfs_remove(ent);
1951 return -ENOMEM;
1952 }
1953
1954 node->minor = minor;
1955 node->dent = ent;
1956 node->info_ent = (void *) key;
b3e067c0
MS		 1957
1958 mutex_lock(&minor->debugfs_lock);
1959 list_add(&node->list, &minor->debugfs_list);
1960 mutex_unlock(&minor->debugfs_lock);
f3cd474b
CW		 1961
1962 return 0;
1963}
1964
6d794d42
BW		 1965static int i915_forcewake_open(struct inode *inode, struct file *file)
1966{
1967 struct drm_device *dev = inode->i_private;
1968 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 1969
075edca4 1970 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 1971 return 0;
1972
6d794d42 1973 gen6_gt_force_wake_get(dev_priv);
6d794d42
BW		 1974
1975 return 0;
1976}
1977
c43b5634 1978static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 1979{
1980 struct drm_device *dev = inode->i_private;
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982
075edca4 1983 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 1984 return 0;
1985
6d794d42 1986 gen6_gt_force_wake_put(dev_priv);
6d794d42
BW		 1987
1988 return 0;
1989}
1990
1991static const struct file_operations i915_forcewake_fops = {
1992 .owner = THIS_MODULE,
1993 .open = i915_forcewake_open,
1994 .release = i915_forcewake_release,
1995};
1996
1997static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
1998{
1999 struct drm_device *dev = minor->dev;
2000 struct dentry *ent;
2001
2002 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 2003 S_IRUSR,
6d794d42
BW		 2004 root, dev,
2005 &i915_forcewake_fops);
2006 if (IS_ERR(ent))
2007 return PTR_ERR(ent);
2008
8eb57294 2009 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 2010}
2011
6a9c308d
DV		 2012static int i915_debugfs_create(struct dentry *root,
2013 struct drm_minor *minor,
2014 const char *name,
2015 const struct file_operations *fops)
07b7ddd9
JB		 2016{
2017 struct drm_device *dev = minor->dev;
2018 struct dentry *ent;
2019
6a9c308d 2020 ent = debugfs_create_file(name,
07b7ddd9
JB		 2021 S_IRUGO | S_IWUSR,
2022 root, dev,
6a9c308d 2023 fops);
07b7ddd9
JB		 2024 if (IS_ERR(ent))
2025 return PTR_ERR(ent);
2026
6a9c308d 2027 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 2028}
2029
27c202ad 2030static struct drm_info_list i915_debugfs_list[] = {
311bd68e 2031 {"i915_capabilities", i915_capabilities, 0},
73aa808f 2032 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 2033 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 2034 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 2035 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 2036 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4e5359cd 2037 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 2038 {"i915_gem_request", i915_gem_request_info, 0},
2039 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 2040 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 2041 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 2042 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
2043 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
2044 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
f97108d1
JB		 2045 {"i915_rstdby_delays", i915_rstdby_delays, 0},
2046 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
2047 {"i915_delayfreq_table", i915_delayfreq_table, 0},
2048 {"i915_inttoext_table", i915_inttoext_table, 0},
2049 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 2050 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 2051 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 2052 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 2053 {"i915_fbc_status", i915_fbc_status, 0},
4a9bef37 2054 {"i915_sr_status", i915_sr_status, 0},
44834a67 2055 {"i915_opregion", i915_opregion, 0},
37811fcc 2056 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 2057 {"i915_context_status", i915_context_status, 0},
6d794d42 2058 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 2059 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 2060 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 2061 {"i915_dpio", i915_dpio_info, 0},
2017263e 2062};
27c202ad 2063#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 2064
27c202ad 2065int i915_debugfs_init(struct drm_minor *minor)
2017263e 2066{
f3cd474b
CW		 2067 int ret;
2068
6a9c308d
DV		 2069 ret = i915_debugfs_create(minor->debugfs_root, minor,
2070 "i915_wedged",
2071 &i915_wedged_fops);
f3cd474b
CW		 2072 if (ret)
2073 return ret;
2074
6d794d42 2075 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 2076 if (ret)
2077 return ret;
6a9c308d
DV		 2078
2079 ret = i915_debugfs_create(minor->debugfs_root, minor,
2080 "i915_max_freq",
2081 &i915_max_freq_fops);
07b7ddd9
JB		 2082 if (ret)
2083 return ret;
6a9c308d 2084
1523c310
JB		 2085 ret = i915_debugfs_create(minor->debugfs_root, minor,
2086 "i915_min_freq",
2087 &i915_min_freq_fops);
2088 if (ret)
2089 return ret;
2090
6a9c308d
DV		 2091 ret = i915_debugfs_create(minor->debugfs_root, minor,
2092 "i915_cache_sharing",
2093 &i915_cache_sharing_fops);
6d794d42
BW		 2094 if (ret)
2095 return ret;
004777cb 2096
e5eb3d63
DV		 2097 ret = i915_debugfs_create(minor->debugfs_root, minor,
2098 "i915_ring_stop",
2099 &i915_ring_stop_fops);
2100 if (ret)
2101 return ret;
6d794d42 2102
d5442303
DV		 2103 ret = i915_debugfs_create(minor->debugfs_root, minor,
2104 "i915_error_state",
2105 &i915_error_state_fops);
2106 if (ret)
2107 return ret;
2108
27c202ad
BG		 2109 return drm_debugfs_create_files(i915_debugfs_list,
2110 I915_DEBUGFS_ENTRIES,
2017263e
BG		 2111 minor->debugfs_root, minor);
2112}
2113
27c202ad 2114void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 2115{
27c202ad
BG		 2116 drm_debugfs_remove_files(i915_debugfs_list,
2117 I915_DEBUGFS_ENTRIES, minor);
6d794d42
BW		 2118 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
2119 1, minor);
33db679b
KH		 2120 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
2121 1, minor);
358733e9
JB		 2122 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
2123 1, minor);
1523c310
JB		 2124 drm_debugfs_remove_files((struct drm_info_list *) &i915_min_freq_fops,
2125 1, minor);
07b7ddd9
JB		 2126 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
2127 1, minor);
e5eb3d63
DV		 2128 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
2129 1, minor);
6bd459df
DV		 2130 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
2131 1, minor);
2017263e
BG		 2132}
2133
2134#endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
This page took 0.348825 seconds and 5 git commands to generate.