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drm/i915/bdw: WaProgramL3SqcReg1Default
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
4feb7659 99 if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
20e28fba 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
37811fcc
CW		 127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
1d693bcc 130 get_global_flag(obj),
a05a5862 131 obj->base.size / 1024,
37811fcc
CW		 132 obj->base.read_domains,
133 obj->base.write_domain,
97b2a6a1
JH		 134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 142 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 143 if (vma->pin_count > 0)
144 pin_count++;
ba0635ff
DC		 145 }
146 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 147 if (obj->pin_display)
148 seq_printf(m, " (display)");
37811fcc
CW		 149 if (obj->fence_reg != I915_FENCE_REG_NONE)
150 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 151 list_for_each_entry(vma, &obj->vma_list, vma_link) {
152 if (!i915_is_ggtt(vma->vm))
153 seq_puts(m, " (pp");
154 else
155 seq_puts(m, " (g");
440fd528 156 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
fe14d5f4
TU		 157 vma->node.start, vma->node.size,
158 vma->ggtt_view.type);
1d693bcc 159 }
c1ad11fc 160 if (obj->stolen)
440fd528 161 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
41c52415
JH		 171 if (obj->last_read_req != NULL)
172 seq_printf(m, " (%s)",
173 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 174 if (obj->frontbuffer_bits)
175 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 176}
177
273497e5 178static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 179{
ea0c76f8 180 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 181 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
182 seq_putc(m, ' ');
183}
184
433e12f7 185static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 186{
9f25d007 187 struct drm_info_node *node = m->private;
433e12f7
BG		 188 uintptr_t list = (uintptr_t) node->info_ent->data;
189 struct list_head *head;
2017263e 190 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 193 struct i915_vma *vma;
8f2480fb
CW		 194 size_t total_obj_size, total_gtt_size;
195 int count, ret;
de227ef0
CW		 196
197 ret = mutex_lock_interruptible(&dev->struct_mutex);
198 if (ret)
199 return ret;
2017263e 200
ca191b13 201 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 202 switch (list) {
203 case ACTIVE_LIST:
267f0c90 204 seq_puts(m, "Active:\n");
5cef07e1 205 head = &vm->active_list;
433e12f7
BG		 206 break;
207 case INACTIVE_LIST:
267f0c90 208 seq_puts(m, "Inactive:\n");
5cef07e1 209 head = &vm->inactive_list;
433e12f7 210 break;
433e12f7 211 default:
de227ef0
CW		 212 mutex_unlock(&dev->struct_mutex);
213 return -EINVAL;
2017263e 214 }
2017263e 215
8f2480fb 216 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 217 list_for_each_entry(vma, head, mm_list) {
218 seq_printf(m, " ");
219 describe_obj(m, vma->obj);
220 seq_printf(m, "\n");
221 total_obj_size += vma->obj->base.size;
222 total_gtt_size += vma->node.size;
8f2480fb 223 count++;
2017263e 224 }
de227ef0 225 mutex_unlock(&dev->struct_mutex);
5e118f41 226
8f2480fb
CW		 227 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
228 count, total_obj_size, total_gtt_size);
2017263e
BG		 229 return 0;
230}
231
6d2b8885
CW		 232static int obj_rank_by_stolen(void *priv,
233 struct list_head *A, struct list_head *B)
234{
235 struct drm_i915_gem_object *a =
b25cb2f8 236 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 237 struct drm_i915_gem_object *b =
b25cb2f8 238 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 239
240 return a->stolen->start - b->stolen->start;
241}
242
243static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
244{
9f25d007 245 struct drm_info_node *node = m->private;
6d2b8885
CW		 246 struct drm_device *dev = node->minor->dev;
247 struct drm_i915_private *dev_priv = dev->dev_private;
248 struct drm_i915_gem_object *obj;
249 size_t total_obj_size, total_gtt_size;
250 LIST_HEAD(stolen);
251 int count, ret;
252
253 ret = mutex_lock_interruptible(&dev->struct_mutex);
254 if (ret)
255 return ret;
256
257 total_obj_size = total_gtt_size = count = 0;
258 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
259 if (obj->stolen == NULL)
260 continue;
261
b25cb2f8 262 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 263
264 total_obj_size += obj->base.size;
265 total_gtt_size += i915_gem_obj_ggtt_size(obj);
266 count++;
267 }
268 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
269 if (obj->stolen == NULL)
270 continue;
271
b25cb2f8 272 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 273
274 total_obj_size += obj->base.size;
275 count++;
276 }
277 list_sort(NULL, &stolen, obj_rank_by_stolen);
278 seq_puts(m, "Stolen:\n");
279 while (!list_empty(&stolen)) {
b25cb2f8 280 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 281 seq_puts(m, " ");
282 describe_obj(m, obj);
283 seq_putc(m, '\n');
b25cb2f8 284 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 285 }
286 mutex_unlock(&dev->struct_mutex);
287
288 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
289 count, total_obj_size, total_gtt_size);
290 return 0;
291}
292
6299f992
CW		 293#define count_objects(list, member) do { \
294 list_for_each_entry(obj, list, member) { \
f343c5f6 295 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 296 ++count; \
297 if (obj->map_and_fenceable) { \
f343c5f6 298 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 299 ++mappable_count; \
300 } \
301 } \
0206e353 302} while (0)
6299f992 303
2db8e9d6 304struct file_stats {
6313c204 305 struct drm_i915_file_private *file_priv;
2db8e9d6 306 int count;
c67a17e9
CW		 307 size_t total, unbound;
308 size_t global, shared;
309 size_t active, inactive;
2db8e9d6
CW		 310};
311
312static int per_file_stats(int id, void *ptr, void *data)
313{
314 struct drm_i915_gem_object *obj = ptr;
315 struct file_stats *stats = data;
6313c204 316 struct i915_vma *vma;
2db8e9d6
CW		 317
318 stats->count++;
319 stats->total += obj->base.size;
320
c67a17e9
CW		 321 if (obj->base.name || obj->base.dma_buf)
322 stats->shared += obj->base.size;
323
6313c204
CW		 324 if (USES_FULL_PPGTT(obj->base.dev)) {
325 list_for_each_entry(vma, &obj->vma_list, vma_link) {
326 struct i915_hw_ppgtt *ppgtt;
327
328 if (!drm_mm_node_allocated(&vma->node))
329 continue;
330
331 if (i915_is_ggtt(vma->vm)) {
332 stats->global += obj->base.size;
333 continue;
334 }
335
336 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 337 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 338 continue;
339
41c52415 340 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 341 stats->active += obj->base.size;
342 else
343 stats->inactive += obj->base.size;
344
345 return 0;
346 }
2db8e9d6 347 } else {
6313c204
CW		 348 if (i915_gem_obj_ggtt_bound(obj)) {
349 stats->global += obj->base.size;
41c52415 350 if (obj->active)
6313c204
CW		 351 stats->active += obj->base.size;
352 else
353 stats->inactive += obj->base.size;
354 return 0;
355 }
2db8e9d6
CW		 356 }
357
6313c204
CW		 358 if (!list_empty(&obj->global_list))
359 stats->unbound += obj->base.size;
360
2db8e9d6
CW		 361 return 0;
362}
363
493018dc
BV		 364#define print_file_stats(m, name, stats) \
365 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
366 name, \
367 stats.count, \
368 stats.total, \
369 stats.active, \
370 stats.inactive, \
371 stats.global, \
372 stats.shared, \
373 stats.unbound)
374
375static void print_batch_pool_stats(struct seq_file *m,
376 struct drm_i915_private *dev_priv)
377{
378 struct drm_i915_gem_object *obj;
379 struct file_stats stats;
380
381 memset(&stats, 0, sizeof(stats));
382
383 list_for_each_entry(obj,
384 &dev_priv->mm.batch_pool.cache_list,
385 batch_pool_list)
386 per_file_stats(0, obj, &stats);
387
388 print_file_stats(m, "batch pool", stats);
389}
390
ca191b13
BW		 391#define count_vmas(list, member) do { \
392 list_for_each_entry(vma, list, member) { \
393 size += i915_gem_obj_ggtt_size(vma->obj); \
394 ++count; \
395 if (vma->obj->map_and_fenceable) { \
396 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
397 ++mappable_count; \
398 } \
399 } \
400} while (0)
401
402static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 403{
9f25d007 404 struct drm_info_node *node = m->private;
73aa808f
CW		 405 struct drm_device *dev = node->minor->dev;
406 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 407 u32 count, mappable_count, purgeable_count;
408 size_t size, mappable_size, purgeable_size;
6299f992 409 struct drm_i915_gem_object *obj;
5cef07e1 410 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 411 struct drm_file *file;
ca191b13 412 struct i915_vma *vma;
73aa808f
CW		 413 int ret;
414
415 ret = mutex_lock_interruptible(&dev->struct_mutex);
416 if (ret)
417 return ret;
418
6299f992
CW		 419 seq_printf(m, "%u objects, %zu bytes\n",
420 dev_priv->mm.object_count,
421 dev_priv->mm.object_memory);
422
423 size = count = mappable_size = mappable_count = 0;
35c20a60 424 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 425 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
426 count, mappable_count, size, mappable_size);
427
428 size = count = mappable_size = mappable_count = 0;
ca191b13 429 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 430 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
431 count, mappable_count, size, mappable_size);
432
6299f992 433 size = count = mappable_size = mappable_count = 0;
ca191b13 434 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 435 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
436 count, mappable_count, size, mappable_size);
437
b7abb714 438 size = count = purgeable_size = purgeable_count = 0;
35c20a60 439 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 440 size += obj->base.size, ++count;
b7abb714
CW		 441 if (obj->madv == I915_MADV_DONTNEED)
442 purgeable_size += obj->base.size, ++purgeable_count;
443 }
6c085a72
CW		 444 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
445
6299f992 446 size = count = mappable_size = mappable_count = 0;
35c20a60 447 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 448 if (obj->fault_mappable) {
f343c5f6 449 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 450 ++count;
451 }
452 if (obj->pin_mappable) {
f343c5f6 453 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 454 ++mappable_count;
455 }
b7abb714
CW		 456 if (obj->madv == I915_MADV_DONTNEED) {
457 purgeable_size += obj->base.size;
458 ++purgeable_count;
459 }
6299f992 460 }
b7abb714
CW		 461 seq_printf(m, "%u purgeable objects, %zu bytes\n",
462 purgeable_count, purgeable_size);
6299f992
CW		 463 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
464 mappable_count, mappable_size);
465 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
466 count, size);
467
93d18799 468 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 469 dev_priv->gtt.base.total,
470 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 471
493018dc
BV		 472 seq_putc(m, '\n');
473 print_batch_pool_stats(m, dev_priv);
474
267f0c90 475 seq_putc(m, '\n');
2db8e9d6
CW		 476 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
477 struct file_stats stats;
3ec2f427 478 struct task_struct *task;
2db8e9d6
CW		 479
480 memset(&stats, 0, sizeof(stats));
6313c204 481 stats.file_priv = file->driver_priv;
5b5ffff0 482 spin_lock(&file->table_lock);
2db8e9d6 483 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 484 spin_unlock(&file->table_lock);
3ec2f427
TH		 485 /*
486 * Although we have a valid reference on file->pid, that does
487 * not guarantee that the task_struct who called get_pid() is
488 * still alive (e.g. get_pid(current) => fork() => exit()).
489 * Therefore, we need to protect this ->comm access using RCU.
490 */
491 rcu_read_lock();
492 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 493 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 494 rcu_read_unlock();
2db8e9d6
CW		 495 }
496
73aa808f
CW		 497 mutex_unlock(&dev->struct_mutex);
498
499 return 0;
500}
501
aee56cff 502static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 503{
9f25d007 504 struct drm_info_node *node = m->private;
08c18323 505 struct drm_device *dev = node->minor->dev;
1b50247a 506 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 507 struct drm_i915_private *dev_priv = dev->dev_private;
508 struct drm_i915_gem_object *obj;
509 size_t total_obj_size, total_gtt_size;
510 int count, ret;
511
512 ret = mutex_lock_interruptible(&dev->struct_mutex);
513 if (ret)
514 return ret;
515
516 total_obj_size = total_gtt_size = count = 0;
35c20a60 517 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 518 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 519 continue;
520
267f0c90 521 seq_puts(m, " ");
08c18323 522 describe_obj(m, obj);
267f0c90 523 seq_putc(m, '\n');
08c18323 524 total_obj_size += obj->base.size;
f343c5f6 525 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 526 count++;
527 }
528
529 mutex_unlock(&dev->struct_mutex);
530
531 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
532 count, total_obj_size, total_gtt_size);
533
534 return 0;
535}
536
4e5359cd
SF		 537static int i915_gem_pageflip_info(struct seq_file *m, void *data)
538{
9f25d007 539 struct drm_info_node *node = m->private;
4e5359cd 540 struct drm_device *dev = node->minor->dev;
d6bbafa1 541 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 542 struct intel_crtc *crtc;
8a270ebf
DV		 543 int ret;
544
545 ret = mutex_lock_interruptible(&dev->struct_mutex);
546 if (ret)
547 return ret;
4e5359cd 548
d3fcc808 549 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 550 const char pipe = pipe_name(crtc->pipe);
551 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 552 struct intel_unpin_work *work;
553
5e2d7afc 554 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 555 work = crtc->unpin_work;
556 if (work == NULL) {
9db4a9c7 557 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 558 pipe, plane);
559 } else {
d6bbafa1
CW		 560 u32 addr;
561
e7d841ca 562 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 563 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 564 pipe, plane);
565 } else {
9db4a9c7 566 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 567 pipe, plane);
568 }
3a8a946e
DV		 569 if (work->flip_queued_req) {
570 struct intel_engine_cs *ring =
571 i915_gem_request_get_ring(work->flip_queued_req);
572
20e28fba 573 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 574 ring->name,
f06cc1b9 575 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 576 dev_priv->next_seqno,
3a8a946e 577 ring->get_seqno(ring, true),
1b5a433a 578 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 579 } else
580 seq_printf(m, "Flip not associated with any ring\n");
581 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
582 work->flip_queued_vblank,
583 work->flip_ready_vblank,
1e3feefd 584 drm_crtc_vblank_count(&crtc->base));
4e5359cd 585 if (work->enable_stall_check)
267f0c90 586 seq_puts(m, "Stall check enabled, ");
4e5359cd 587 else
267f0c90 588 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 589 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 590
d6bbafa1
CW		 591 if (INTEL_INFO(dev)->gen >= 4)
592 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
593 else
594 addr = I915_READ(DSPADDR(crtc->plane));
595 seq_printf(m, "Current scanout address 0x%08x\n", addr);
596
4e5359cd 597 if (work->pending_flip_obj) {
d6bbafa1
CW		 598 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
599 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 600 }
601 }
5e2d7afc 602 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 603 }
604
8a270ebf
DV		 605 mutex_unlock(&dev->struct_mutex);
606
4e5359cd
SF		 607 return 0;
608}
609
493018dc
BV		 610static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
611{
612 struct drm_info_node *node = m->private;
613 struct drm_device *dev = node->minor->dev;
614 struct drm_i915_private *dev_priv = dev->dev_private;
615 struct drm_i915_gem_object *obj;
616 int count = 0;
617 int ret;
618
619 ret = mutex_lock_interruptible(&dev->struct_mutex);
620 if (ret)
621 return ret;
622
623 seq_puts(m, "cache:\n");
624 list_for_each_entry(obj,
625 &dev_priv->mm.batch_pool.cache_list,
626 batch_pool_list) {
627 seq_puts(m, " ");
628 describe_obj(m, obj);
629 seq_putc(m, '\n');
630 count++;
631 }
632
633 seq_printf(m, "total: %d\n", count);
634
635 mutex_unlock(&dev->struct_mutex);
636
637 return 0;
638}
639
2017263e
BG		 640static int i915_gem_request_info(struct seq_file *m, void *data)
641{
9f25d007 642 struct drm_info_node *node = m->private;
2017263e 643 struct drm_device *dev = node->minor->dev;
e277a1f8 644 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 645 struct intel_engine_cs *ring;
2d1070b2
CW		 646 struct drm_i915_gem_request *rq;
647 int ret, any, i;
de227ef0
CW		 648
649 ret = mutex_lock_interruptible(&dev->struct_mutex);
650 if (ret)
651 return ret;
2017263e 652
2d1070b2 653 any = 0;
a2c7f6fd 654 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 655 int count;
656
657 count = 0;
658 list_for_each_entry(rq, &ring->request_list, list)
659 count++;
660 if (count == 0)
a2c7f6fd
CW		 661 continue;
662
2d1070b2
CW		 663 seq_printf(m, "%s requests: %d\n", ring->name, count);
664 list_for_each_entry(rq, &ring->request_list, list) {
665 struct task_struct *task;
666
667 rcu_read_lock();
668 task = NULL;
669 if (rq->pid)
670 task = pid_task(rq->pid, PIDTYPE_PID);
671 seq_printf(m, " %x @ %d: %s [%d]\n",
672 rq->seqno,
673 (int) (jiffies - rq->emitted_jiffies),
674 task ? task->comm : "<unknown>",
675 task ? task->pid : -1);
676 rcu_read_unlock();
c2c347a9 677 }
2d1070b2
CW		 678
679 any++;
2017263e 680 }
de227ef0
CW		 681 mutex_unlock(&dev->struct_mutex);
682
2d1070b2 683 if (any == 0)
267f0c90 684 seq_puts(m, "No requests\n");
c2c347a9 685
2017263e
BG		 686 return 0;
687}
688
b2223497 689static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 690 struct intel_engine_cs *ring)
b2223497
CW		 691{
692 if (ring->get_seqno) {
20e28fba 693 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 694 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 695 }
696}
697
2017263e
BG		 698static int i915_gem_seqno_info(struct seq_file *m, void *data)
699{
9f25d007 700 struct drm_info_node *node = m->private;
2017263e 701 struct drm_device *dev = node->minor->dev;
e277a1f8 702 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 703 struct intel_engine_cs *ring;
1ec14ad3 704 int ret, i;
de227ef0
CW		 705
706 ret = mutex_lock_interruptible(&dev->struct_mutex);
707 if (ret)
708 return ret;
c8c8fb33 709 intel_runtime_pm_get(dev_priv);
2017263e 710
a2c7f6fd
CW		 711 for_each_ring(ring, dev_priv, i)
712 i915_ring_seqno_info(m, ring);
de227ef0 713
c8c8fb33 714 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 715 mutex_unlock(&dev->struct_mutex);
716
2017263e
BG		 717 return 0;
718}
719
720
721static int i915_interrupt_info(struct seq_file *m, void *data)
722{
9f25d007 723 struct drm_info_node *node = m->private;
2017263e 724 struct drm_device *dev = node->minor->dev;
e277a1f8 725 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 726 struct intel_engine_cs *ring;
9db4a9c7 727 int ret, i, pipe;
de227ef0
CW		 728
729 ret = mutex_lock_interruptible(&dev->struct_mutex);
730 if (ret)
731 return ret;
c8c8fb33 732 intel_runtime_pm_get(dev_priv);
2017263e 733
74e1ca8c 734 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 735 seq_printf(m, "Master Interrupt Control:\t%08x\n",
736 I915_READ(GEN8_MASTER_IRQ));
737
738 seq_printf(m, "Display IER:\t%08x\n",
739 I915_READ(VLV_IER));
740 seq_printf(m, "Display IIR:\t%08x\n",
741 I915_READ(VLV_IIR));
742 seq_printf(m, "Display IIR_RW:\t%08x\n",
743 I915_READ(VLV_IIR_RW));
744 seq_printf(m, "Display IMR:\t%08x\n",
745 I915_READ(VLV_IMR));
055e393f 746 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 747 seq_printf(m, "Pipe %c stat:\t%08x\n",
748 pipe_name(pipe),
749 I915_READ(PIPESTAT(pipe)));
750
751 seq_printf(m, "Port hotplug:\t%08x\n",
752 I915_READ(PORT_HOTPLUG_EN));
753 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
754 I915_READ(VLV_DPFLIPSTAT));
755 seq_printf(m, "DPINVGTT:\t%08x\n",
756 I915_READ(DPINVGTT));
757
758 for (i = 0; i < 4; i++) {
759 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
760 i, I915_READ(GEN8_GT_IMR(i)));
761 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
762 i, I915_READ(GEN8_GT_IIR(i)));
763 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
764 i, I915_READ(GEN8_GT_IER(i)));
765 }
766
767 seq_printf(m, "PCU interrupt mask:\t%08x\n",
768 I915_READ(GEN8_PCU_IMR));
769 seq_printf(m, "PCU interrupt identity:\t%08x\n",
770 I915_READ(GEN8_PCU_IIR));
771 seq_printf(m, "PCU interrupt enable:\t%08x\n",
772 I915_READ(GEN8_PCU_IER));
773 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 774 seq_printf(m, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ));
776
777 for (i = 0; i < 4; i++) {
778 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
779 i, I915_READ(GEN8_GT_IMR(i)));
780 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
781 i, I915_READ(GEN8_GT_IIR(i)));
782 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
783 i, I915_READ(GEN8_GT_IER(i)));
784 }
785
055e393f 786 for_each_pipe(dev_priv, pipe) {
f458ebbc 787 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 788 POWER_DOMAIN_PIPE(pipe))) {
789 seq_printf(m, "Pipe %c power disabled\n",
790 pipe_name(pipe));
791 continue;
792 }
a123f157 793 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 794 pipe_name(pipe),
795 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 796 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 797 pipe_name(pipe),
798 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 799 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 800 pipe_name(pipe),
801 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 802 }
803
804 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
805 I915_READ(GEN8_DE_PORT_IMR));
806 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
807 I915_READ(GEN8_DE_PORT_IIR));
808 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
809 I915_READ(GEN8_DE_PORT_IER));
810
811 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
812 I915_READ(GEN8_DE_MISC_IMR));
813 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
814 I915_READ(GEN8_DE_MISC_IIR));
815 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
816 I915_READ(GEN8_DE_MISC_IER));
817
818 seq_printf(m, "PCU interrupt mask:\t%08x\n",
819 I915_READ(GEN8_PCU_IMR));
820 seq_printf(m, "PCU interrupt identity:\t%08x\n",
821 I915_READ(GEN8_PCU_IIR));
822 seq_printf(m, "PCU interrupt enable:\t%08x\n",
823 I915_READ(GEN8_PCU_IER));
824 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 825 seq_printf(m, "Display IER:\t%08x\n",
826 I915_READ(VLV_IER));
827 seq_printf(m, "Display IIR:\t%08x\n",
828 I915_READ(VLV_IIR));
829 seq_printf(m, "Display IIR_RW:\t%08x\n",
830 I915_READ(VLV_IIR_RW));
831 seq_printf(m, "Display IMR:\t%08x\n",
832 I915_READ(VLV_IMR));
055e393f 833 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 834 seq_printf(m, "Pipe %c stat:\t%08x\n",
835 pipe_name(pipe),
836 I915_READ(PIPESTAT(pipe)));
837
838 seq_printf(m, "Master IER:\t%08x\n",
839 I915_READ(VLV_MASTER_IER));
840
841 seq_printf(m, "Render IER:\t%08x\n",
842 I915_READ(GTIER));
843 seq_printf(m, "Render IIR:\t%08x\n",
844 I915_READ(GTIIR));
845 seq_printf(m, "Render IMR:\t%08x\n",
846 I915_READ(GTIMR));
847
848 seq_printf(m, "PM IER:\t\t%08x\n",
849 I915_READ(GEN6_PMIER));
850 seq_printf(m, "PM IIR:\t\t%08x\n",
851 I915_READ(GEN6_PMIIR));
852 seq_printf(m, "PM IMR:\t\t%08x\n",
853 I915_READ(GEN6_PMIMR));
854
855 seq_printf(m, "Port hotplug:\t%08x\n",
856 I915_READ(PORT_HOTPLUG_EN));
857 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
858 I915_READ(VLV_DPFLIPSTAT));
859 seq_printf(m, "DPINVGTT:\t%08x\n",
860 I915_READ(DPINVGTT));
861
862 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 863 seq_printf(m, "Interrupt enable: %08x\n",
864 I915_READ(IER));
865 seq_printf(m, "Interrupt identity: %08x\n",
866 I915_READ(IIR));
867 seq_printf(m, "Interrupt mask: %08x\n",
868 I915_READ(IMR));
055e393f 869 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 870 seq_printf(m, "Pipe %c stat: %08x\n",
871 pipe_name(pipe),
872 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 873 } else {
874 seq_printf(m, "North Display Interrupt enable: %08x\n",
875 I915_READ(DEIER));
876 seq_printf(m, "North Display Interrupt identity: %08x\n",
877 I915_READ(DEIIR));
878 seq_printf(m, "North Display Interrupt mask: %08x\n",
879 I915_READ(DEIMR));
880 seq_printf(m, "South Display Interrupt enable: %08x\n",
881 I915_READ(SDEIER));
882 seq_printf(m, "South Display Interrupt identity: %08x\n",
883 I915_READ(SDEIIR));
884 seq_printf(m, "South Display Interrupt mask: %08x\n",
885 I915_READ(SDEIMR));
886 seq_printf(m, "Graphics Interrupt enable: %08x\n",
887 I915_READ(GTIER));
888 seq_printf(m, "Graphics Interrupt identity: %08x\n",
889 I915_READ(GTIIR));
890 seq_printf(m, "Graphics Interrupt mask: %08x\n",
891 I915_READ(GTIMR));
892 }
a2c7f6fd 893 for_each_ring(ring, dev_priv, i) {
a123f157 894 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 895 seq_printf(m,
896 "Graphics Interrupt mask (%s): %08x\n",
897 ring->name, I915_READ_IMR(ring));
9862e600 898 }
a2c7f6fd 899 i915_ring_seqno_info(m, ring);
9862e600 900 }
c8c8fb33 901 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 902 mutex_unlock(&dev->struct_mutex);
903
2017263e
BG		 904 return 0;
905}
906
a6172a80
CW		 907static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
908{
9f25d007 909 struct drm_info_node *node = m->private;
a6172a80 910 struct drm_device *dev = node->minor->dev;
e277a1f8 911 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 912 int i, ret;
913
914 ret = mutex_lock_interruptible(&dev->struct_mutex);
915 if (ret)
916 return ret;
a6172a80
CW		 917
918 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
919 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
920 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 921 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 922
6c085a72
CW		 923 seq_printf(m, "Fence %d, pin count = %d, object = ",
924 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 925 if (obj == NULL)
267f0c90 926 seq_puts(m, "unused");
c2c347a9 927 else
05394f39 928 describe_obj(m, obj);
267f0c90 929 seq_putc(m, '\n');
a6172a80
CW		 930 }
931
05394f39 932 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 933 return 0;
934}
935
2017263e
BG		 936static int i915_hws_info(struct seq_file *m, void *data)
937{
9f25d007 938 struct drm_info_node *node = m->private;
2017263e 939 struct drm_device *dev = node->minor->dev;
e277a1f8 940 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 941 struct intel_engine_cs *ring;
1a240d4d 942 const u32 *hws;
4066c0ae
CW		 943 int i;
944
1ec14ad3 945 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 946 hws = ring->status_page.page_addr;
2017263e
BG		 947 if (hws == NULL)
948 return 0;
949
950 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
951 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
952 i * 4,
953 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
954 }
955 return 0;
956}
957
d5442303
DV		 958static ssize_t
959i915_error_state_write(struct file *filp,
960 const char __user *ubuf,
961 size_t cnt,
962 loff_t *ppos)
963{
edc3d884 964 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 965 struct drm_device *dev = error_priv->dev;
22bcfc6a 966 int ret;
d5442303
DV		 967
968 DRM_DEBUG_DRIVER("Resetting error state\n");
969
22bcfc6a
DV		 970 ret = mutex_lock_interruptible(&dev->struct_mutex);
971 if (ret)
972 return ret;
973
d5442303
DV		 974 i915_destroy_error_state(dev);
975 mutex_unlock(&dev->struct_mutex);
976
977 return cnt;
978}
979
980static int i915_error_state_open(struct inode *inode, struct file *file)
981{
982 struct drm_device *dev = inode->i_private;
d5442303 983 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 984
985 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
986 if (!error_priv)
987 return -ENOMEM;
988
989 error_priv->dev = dev;
990
95d5bfb3 991 i915_error_state_get(dev, error_priv);
d5442303 992
edc3d884
MK		 993 file->private_data = error_priv;
994
995 return 0;
d5442303
DV		 996}
997
998static int i915_error_state_release(struct inode *inode, struct file *file)
999{
edc3d884 1000 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1001
95d5bfb3 1002 i915_error_state_put(error_priv);
d5442303
DV		 1003 kfree(error_priv);
1004
edc3d884
MK		 1005 return 0;
1006}
1007
4dc955f7
MK		 1008static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1009 size_t count, loff_t *pos)
1010{
1011 struct i915_error_state_file_priv *error_priv = file->private_data;
1012 struct drm_i915_error_state_buf error_str;
1013 loff_t tmp_pos = 0;
1014 ssize_t ret_count = 0;
1015 int ret;
1016
0a4cd7c8 1017 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1018 if (ret)
1019 return ret;
edc3d884 1020
fc16b48b 1021 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1022 if (ret)
1023 goto out;
1024
edc3d884
MK		 1025 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1026 error_str.buf,
1027 error_str.bytes);
1028
1029 if (ret_count < 0)
1030 ret = ret_count;
1031 else
1032 *pos = error_str.start + ret_count;
1033out:
4dc955f7 1034 i915_error_state_buf_release(&error_str);
edc3d884 1035 return ret ?: ret_count;
d5442303
DV		 1036}
1037
1038static const struct file_operations i915_error_state_fops = {
1039 .owner = THIS_MODULE,
1040 .open = i915_error_state_open,
edc3d884 1041 .read = i915_error_state_read,
d5442303
DV		 1042 .write = i915_error_state_write,
1043 .llseek = default_llseek,
1044 .release = i915_error_state_release,
1045};
1046
647416f9
KC		 1047static int
1048i915_next_seqno_get(void *data, u64 *val)
40633219 1049{
647416f9 1050 struct drm_device *dev = data;
e277a1f8 1051 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1052 int ret;
1053
1054 ret = mutex_lock_interruptible(&dev->struct_mutex);
1055 if (ret)
1056 return ret;
1057
647416f9 1058 *val = dev_priv->next_seqno;
40633219
MK		 1059 mutex_unlock(&dev->struct_mutex);
1060
647416f9 1061 return 0;
40633219
MK		 1062}
1063
647416f9
KC		 1064static int
1065i915_next_seqno_set(void *data, u64 val)
1066{
1067 struct drm_device *dev = data;
40633219
MK		 1068 int ret;
1069
40633219
MK		 1070 ret = mutex_lock_interruptible(&dev->struct_mutex);
1071 if (ret)
1072 return ret;
1073
e94fbaa8 1074 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1075 mutex_unlock(&dev->struct_mutex);
1076
647416f9 1077 return ret;
40633219
MK		 1078}
1079
647416f9
KC		 1080DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1081 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1082 "0x%llx\n");
40633219 1083
adb4bd12 1084static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1085{
9f25d007 1086 struct drm_info_node *node = m->private;
f97108d1 1087 struct drm_device *dev = node->minor->dev;
e277a1f8 1088 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1089 int ret = 0;
1090
1091 intel_runtime_pm_get(dev_priv);
3b8d8d91 1092
5c9669ce
TR		 1093 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1094
3b8d8d91
JB		 1095 if (IS_GEN5(dev)) {
1096 u16 rgvswctl = I915_READ16(MEMSWCTL);
1097 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1098
1099 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1100 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1101 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1102 MEMSTAT_VID_SHIFT);
1103 seq_printf(m, "Current P-state: %d\n",
1104 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2 1105 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
60260a5b 1106 IS_BROADWELL(dev) || IS_GEN9(dev)) {
3b8d8d91
JB		 1107 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1108 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1109 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1110 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1111 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1112 u32 rpupei, rpcurup, rpprevup;
1113 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1114 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1115 int max_freq;
1116
1117 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1118 ret = mutex_lock_interruptible(&dev->struct_mutex);
1119 if (ret)
c8c8fb33 1120 goto out;
d1ebd816 1121
59bad947 1122 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1123
8e8c06cd 1124 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1125 if (IS_GEN9(dev))
1126 reqf >>= 23;
1127 else {
1128 reqf &= ~GEN6_TURBO_DISABLE;
1129 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1130 reqf >>= 24;
1131 else
1132 reqf >>= 25;
1133 }
7c59a9c1 1134 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1135
0d8f9491
CW		 1136 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1137 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1138 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1139
ccab5c82
JB		 1140 rpstat = I915_READ(GEN6_RPSTAT1);
1141 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1142 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1143 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1144 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1145 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1146 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1147 if (IS_GEN9(dev))
1148 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1149 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1150 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1151 else
1152 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1153 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1154
59bad947 1155 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1156 mutex_unlock(&dev->struct_mutex);
1157
9dd3c605
PZ		 1158 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1159 pm_ier = I915_READ(GEN6_PMIER);
1160 pm_imr = I915_READ(GEN6_PMIMR);
1161 pm_isr = I915_READ(GEN6_PMISR);
1162 pm_iir = I915_READ(GEN6_PMIIR);
1163 pm_mask = I915_READ(GEN6_PMINTRMSK);
1164 } else {
1165 pm_ier = I915_READ(GEN8_GT_IER(2));
1166 pm_imr = I915_READ(GEN8_GT_IMR(2));
1167 pm_isr = I915_READ(GEN8_GT_ISR(2));
1168 pm_iir = I915_READ(GEN8_GT_IIR(2));
1169 pm_mask = I915_READ(GEN6_PMINTRMSK);
1170 }
0d8f9491 1171 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1172 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1173 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1174 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1175 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1176 seq_printf(m, "Render p-state VID: %d\n",
1177 gt_perf_status & 0xff);
1178 seq_printf(m, "Render p-state limit: %d\n",
1179 rp_state_limits & 0xff);
0d8f9491
CW		 1180 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1181 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1182 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1183 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1184 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1185 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1186 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1187 GEN6_CURICONT_MASK);
1188 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1189 GEN6_CURBSYTAVG_MASK);
1190 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1191 GEN6_CURBSYTAVG_MASK);
1192 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1193 GEN6_CURIAVG_MASK);
1194 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1195 GEN6_CURBSYTAVG_MASK);
1196 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1197 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1198
1199 max_freq = (rp_state_cap & 0xff0000) >> 16;
60260a5b 1200 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1201 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1202 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1203
1204 max_freq = (rp_state_cap & 0xff00) >> 8;
60260a5b 1205 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1206 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1207 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1208
1209 max_freq = rp_state_cap & 0xff;
60260a5b 1210 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1211 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1212 intel_gpu_freq(dev_priv, max_freq));
31c77388
BW		 1213
1214 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1215 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff
CW		 1216
1217 seq_printf(m, "Idle freq: %d MHz\n",
1218 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
0a073b84 1219 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1220 u32 freq_sts;
0a073b84 1221
259bd5d4 1222 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1223 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1224 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1225 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1226
0a073b84 1227 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1228 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1229
0a073b84 1230 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1231 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1232
aed242ff
CW		 1233 seq_printf(m, "idle GPU freq: %d MHz\n",
1234 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1235
7c59a9c1
VS		 1236 seq_printf(m,
1237 "efficient (RPe) frequency: %d MHz\n",
1238 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1239
1240 seq_printf(m, "current GPU freq: %d MHz\n",
7c59a9c1 1241 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1242 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1243 } else {
267f0c90 1244 seq_puts(m, "no P-state info available\n");
3b8d8d91 1245 }
f97108d1 1246
c8c8fb33
PZ		 1247out:
1248 intel_runtime_pm_put(dev_priv);
1249 return ret;
f97108d1
JB		 1250}
1251
f654449a
CW		 1252static int i915_hangcheck_info(struct seq_file *m, void *unused)
1253{
1254 struct drm_info_node *node = m->private;
ebbc7546
MK		 1255 struct drm_device *dev = node->minor->dev;
1256 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1257 struct intel_engine_cs *ring;
ebbc7546
MK		 1258 u64 acthd[I915_NUM_RINGS];
1259 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1260 int i;
1261
1262 if (!i915.enable_hangcheck) {
1263 seq_printf(m, "Hangcheck disabled\n");
1264 return 0;
1265 }
1266
ebbc7546
MK		 1267 intel_runtime_pm_get(dev_priv);
1268
1269 for_each_ring(ring, dev_priv, i) {
1270 seqno[i] = ring->get_seqno(ring, false);
1271 acthd[i] = intel_ring_get_active_head(ring);
1272 }
1273
1274 intel_runtime_pm_put(dev_priv);
1275
f654449a
CW		 1276 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1277 seq_printf(m, "Hangcheck active, fires in %dms\n",
1278 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1279 jiffies));
1280 } else
1281 seq_printf(m, "Hangcheck inactive\n");
1282
1283 for_each_ring(ring, dev_priv, i) {
1284 seq_printf(m, "%s:\n", ring->name);
1285 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1286 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1287 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1288 (long long)ring->hangcheck.acthd,
ebbc7546 1289 (long long)acthd[i]);
f654449a
CW		 1290 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1291 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1292 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1293 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1294 }
1295
1296 return 0;
1297}
1298
4d85529d 1299static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1300{
9f25d007 1301 struct drm_info_node *node = m->private;
f97108d1 1302 struct drm_device *dev = node->minor->dev;
e277a1f8 1303 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1304 u32 rgvmodectl, rstdbyctl;
1305 u16 crstandvid;
1306 int ret;
1307
1308 ret = mutex_lock_interruptible(&dev->struct_mutex);
1309 if (ret)
1310 return ret;
c8c8fb33 1311 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1312
1313 rgvmodectl = I915_READ(MEMMODECTL);
1314 rstdbyctl = I915_READ(RSTDBYCTL);
1315 crstandvid = I915_READ16(CRSTANDVID);
1316
c8c8fb33 1317 intel_runtime_pm_put(dev_priv);
616fdb5a 1318 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1319
1320 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1321 "yes" : "no");
1322 seq_printf(m, "Boost freq: %d\n",
1323 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1324 MEMMODE_BOOST_FREQ_SHIFT);
1325 seq_printf(m, "HW control enabled: %s\n",
1326 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1327 seq_printf(m, "SW control enabled: %s\n",
1328 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1329 seq_printf(m, "Gated voltage change: %s\n",
1330 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1331 seq_printf(m, "Starting frequency: P%d\n",
1332 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1333 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1334 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1335 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1336 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1337 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1338 seq_printf(m, "Render standby enabled: %s\n",
1339 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1340 seq_puts(m, "Current RS state: ");
88271da3
JB		 1341 switch (rstdbyctl & RSX_STATUS_MASK) {
1342 case RSX_STATUS_ON:
267f0c90 1343 seq_puts(m, "on\n");
88271da3
JB		 1344 break;
1345 case RSX_STATUS_RC1:
267f0c90 1346 seq_puts(m, "RC1\n");
88271da3
JB		 1347 break;
1348 case RSX_STATUS_RC1E:
267f0c90 1349 seq_puts(m, "RC1E\n");
88271da3
JB		 1350 break;
1351 case RSX_STATUS_RS1:
267f0c90 1352 seq_puts(m, "RS1\n");
88271da3
JB		 1353 break;
1354 case RSX_STATUS_RS2:
267f0c90 1355 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1356 break;
1357 case RSX_STATUS_RS3:
267f0c90 1358 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1359 break;
1360 default:
267f0c90 1361 seq_puts(m, "unknown\n");
88271da3
JB		 1362 break;
1363 }
f97108d1
JB		 1364
1365 return 0;
1366}
1367
f65367b5 1368static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1369{
b2cff0db
CW		 1370 struct drm_info_node *node = m->private;
1371 struct drm_device *dev = node->minor->dev;
1372 struct drm_i915_private *dev_priv = dev->dev_private;
1373 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1374 int i;
1375
1376 spin_lock_irq(&dev_priv->uncore.lock);
1377 for_each_fw_domain(fw_domain, dev_priv, i) {
1378 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1379 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1380 fw_domain->wake_count);
1381 }
1382 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1383
b2cff0db
CW		 1384 return 0;
1385}
1386
1387static int vlv_drpc_info(struct seq_file *m)
1388{
9f25d007 1389 struct drm_info_node *node = m->private;
669ab5aa
D		 1390 struct drm_device *dev = node->minor->dev;
1391 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1392 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1393
d46c0517
ID		 1394 intel_runtime_pm_get(dev_priv);
1395
6b312cd3 1396 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1397 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1398 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1399
d46c0517
ID		 1400 intel_runtime_pm_put(dev_priv);
1401
669ab5aa
D		 1402 seq_printf(m, "Video Turbo Mode: %s\n",
1403 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1404 seq_printf(m, "Turbo enabled: %s\n",
1405 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1406 seq_printf(m, "HW control enabled: %s\n",
1407 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1408 seq_printf(m, "SW control enabled: %s\n",
1409 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1410 GEN6_RP_MEDIA_SW_MODE));
1411 seq_printf(m, "RC6 Enabled: %s\n",
1412 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1413 GEN6_RC_CTL_EI_MODE(1))));
1414 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1415 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1416 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1417 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1418
9cc19be5
ID		 1419 seq_printf(m, "Render RC6 residency since boot: %u\n",
1420 I915_READ(VLV_GT_RENDER_RC6));
1421 seq_printf(m, "Media RC6 residency since boot: %u\n",
1422 I915_READ(VLV_GT_MEDIA_RC6));
1423
f65367b5 1424 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1425}
1426
4d85529d
BW		 1427static int gen6_drpc_info(struct seq_file *m)
1428{
9f25d007 1429 struct drm_info_node *node = m->private;
4d85529d
BW		 1430 struct drm_device *dev = node->minor->dev;
1431 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1432 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1433 unsigned forcewake_count;
aee56cff 1434 int count = 0, ret;
4d85529d
BW		 1435
1436 ret = mutex_lock_interruptible(&dev->struct_mutex);
1437 if (ret)
1438 return ret;
c8c8fb33 1439 intel_runtime_pm_get(dev_priv);
4d85529d 1440
907b28c5 1441 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1442 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1443 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1444
1445 if (forcewake_count) {
267f0c90
DL		 1446 seq_puts(m, "RC information inaccurate because somebody "
1447 "holds a forcewake reference \n");
4d85529d
BW		 1448 } else {
1449 /* NB: we cannot use forcewake, else we read the wrong values */
1450 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1451 udelay(10);
1452 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1453 }
1454
1455 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1456 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1457
1458 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1459 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1460 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1461 mutex_lock(&dev_priv->rps.hw_lock);
1462 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1463 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1464
c8c8fb33
PZ		 1465 intel_runtime_pm_put(dev_priv);
1466
4d85529d
BW		 1467 seq_printf(m, "Video Turbo Mode: %s\n",
1468 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1469 seq_printf(m, "HW control enabled: %s\n",
1470 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1471 seq_printf(m, "SW control enabled: %s\n",
1472 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1473 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1474 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1475 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1476 seq_printf(m, "RC6 Enabled: %s\n",
1477 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1478 seq_printf(m, "Deep RC6 Enabled: %s\n",
1479 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1480 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1481 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1482 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1483 switch (gt_core_status & GEN6_RCn_MASK) {
1484 case GEN6_RC0:
1485 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1486 seq_puts(m, "Core Power Down\n");
4d85529d 1487 else
267f0c90 1488 seq_puts(m, "on\n");
4d85529d
BW		 1489 break;
1490 case GEN6_RC3:
267f0c90 1491 seq_puts(m, "RC3\n");
4d85529d
BW		 1492 break;
1493 case GEN6_RC6:
267f0c90 1494 seq_puts(m, "RC6\n");
4d85529d
BW		 1495 break;
1496 case GEN6_RC7:
267f0c90 1497 seq_puts(m, "RC7\n");
4d85529d
BW		 1498 break;
1499 default:
267f0c90 1500 seq_puts(m, "Unknown\n");
4d85529d
BW		 1501 break;
1502 }
1503
1504 seq_printf(m, "Core Power Down: %s\n",
1505 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1506
1507 /* Not exactly sure what this is */
1508 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1509 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1510 seq_printf(m, "RC6 residency since boot: %u\n",
1511 I915_READ(GEN6_GT_GFX_RC6));
1512 seq_printf(m, "RC6+ residency since boot: %u\n",
1513 I915_READ(GEN6_GT_GFX_RC6p));
1514 seq_printf(m, "RC6++ residency since boot: %u\n",
1515 I915_READ(GEN6_GT_GFX_RC6pp));
1516
ecd8faea
BW		 1517 seq_printf(m, "RC6 voltage: %dmV\n",
1518 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1519 seq_printf(m, "RC6+ voltage: %dmV\n",
1520 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1521 seq_printf(m, "RC6++ voltage: %dmV\n",
1522 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1523 return 0;
1524}
1525
1526static int i915_drpc_info(struct seq_file *m, void *unused)
1527{
9f25d007 1528 struct drm_info_node *node = m->private;
4d85529d
BW		 1529 struct drm_device *dev = node->minor->dev;
1530
669ab5aa
D		 1531 if (IS_VALLEYVIEW(dev))
1532 return vlv_drpc_info(m);
ac66cf4b 1533 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1534 return gen6_drpc_info(m);
1535 else
1536 return ironlake_drpc_info(m);
1537}
1538
b5e50c3f
JB		 1539static int i915_fbc_status(struct seq_file *m, void *unused)
1540{
9f25d007 1541 struct drm_info_node *node = m->private;
b5e50c3f 1542 struct drm_device *dev = node->minor->dev;
e277a1f8 1543 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1544
3a77c4c4 1545 if (!HAS_FBC(dev)) {
267f0c90 1546 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1547 return 0;
1548 }
1549
36623ef8
PZ		 1550 intel_runtime_pm_get(dev_priv);
1551
ee5382ae 1552 if (intel_fbc_enabled(dev)) {
267f0c90 1553 seq_puts(m, "FBC enabled\n");
b5e50c3f 1554 } else {
267f0c90 1555 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1556 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1557 case FBC_OK:
1558 seq_puts(m, "FBC actived, but currently disabled in hardware");
1559 break;
1560 case FBC_UNSUPPORTED:
1561 seq_puts(m, "unsupported by this chipset");
1562 break;
bed4a673 1563 case FBC_NO_OUTPUT:
267f0c90 1564 seq_puts(m, "no outputs");
bed4a673 1565 break;
b5e50c3f 1566 case FBC_STOLEN_TOO_SMALL:
267f0c90 1567 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1568 break;
1569 case FBC_UNSUPPORTED_MODE:
267f0c90 1570 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1571 break;
1572 case FBC_MODE_TOO_LARGE:
267f0c90 1573 seq_puts(m, "mode too large");
b5e50c3f
JB		 1574 break;
1575 case FBC_BAD_PLANE:
267f0c90 1576 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1577 break;
1578 case FBC_NOT_TILED:
267f0c90 1579 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1580 break;
9c928d16 1581 case FBC_MULTIPLE_PIPES:
267f0c90 1582 seq_puts(m, "multiple pipes are enabled");
9c928d16 1583 break;
c1a9f047 1584 case FBC_MODULE_PARAM:
267f0c90 1585 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1586 break;
8a5729a3 1587 case FBC_CHIP_DEFAULT:
267f0c90 1588 seq_puts(m, "disabled per chip default");
8a5729a3 1589 break;
b5e50c3f 1590 default:
267f0c90 1591 seq_puts(m, "unknown reason");
b5e50c3f 1592 }
267f0c90 1593 seq_putc(m, '\n');
b5e50c3f 1594 }
36623ef8
PZ		 1595
1596 intel_runtime_pm_put(dev_priv);
1597
b5e50c3f
JB		 1598 return 0;
1599}
1600
da46f936
RV		 1601static int i915_fbc_fc_get(void *data, u64 *val)
1602{
1603 struct drm_device *dev = data;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605
1606 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1607 return -ENODEV;
1608
1609 drm_modeset_lock_all(dev);
1610 *val = dev_priv->fbc.false_color;
1611 drm_modeset_unlock_all(dev);
1612
1613 return 0;
1614}
1615
1616static int i915_fbc_fc_set(void *data, u64 val)
1617{
1618 struct drm_device *dev = data;
1619 struct drm_i915_private *dev_priv = dev->dev_private;
1620 u32 reg;
1621
1622 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1623 return -ENODEV;
1624
1625 drm_modeset_lock_all(dev);
1626
1627 reg = I915_READ(ILK_DPFC_CONTROL);
1628 dev_priv->fbc.false_color = val;
1629
1630 I915_WRITE(ILK_DPFC_CONTROL, val ?
1631 (reg | FBC_CTL_FALSE_COLOR) :
1632 (reg & ~FBC_CTL_FALSE_COLOR));
1633
1634 drm_modeset_unlock_all(dev);
1635 return 0;
1636}
1637
1638DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1639 i915_fbc_fc_get, i915_fbc_fc_set,
1640 "%llu\n");
1641
92d44621
PZ		 1642static int i915_ips_status(struct seq_file *m, void *unused)
1643{
9f25d007 1644 struct drm_info_node *node = m->private;
92d44621
PZ		 1645 struct drm_device *dev = node->minor->dev;
1646 struct drm_i915_private *dev_priv = dev->dev_private;
1647
f5adf94e 1648 if (!HAS_IPS(dev)) {
92d44621
PZ		 1649 seq_puts(m, "not supported\n");
1650 return 0;
1651 }
1652
36623ef8
PZ		 1653 intel_runtime_pm_get(dev_priv);
1654
0eaa53f0
RV		 1655 seq_printf(m, "Enabled by kernel parameter: %s\n",
1656 yesno(i915.enable_ips));
1657
1658 if (INTEL_INFO(dev)->gen >= 8) {
1659 seq_puts(m, "Currently: unknown\n");
1660 } else {
1661 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1662 seq_puts(m, "Currently: enabled\n");
1663 else
1664 seq_puts(m, "Currently: disabled\n");
1665 }
92d44621 1666
36623ef8
PZ		 1667 intel_runtime_pm_put(dev_priv);
1668
92d44621
PZ		 1669 return 0;
1670}
1671
4a9bef37
JB		 1672static int i915_sr_status(struct seq_file *m, void *unused)
1673{
9f25d007 1674 struct drm_info_node *node = m->private;
4a9bef37 1675 struct drm_device *dev = node->minor->dev;
e277a1f8 1676 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1677 bool sr_enabled = false;
1678
36623ef8
PZ		 1679 intel_runtime_pm_get(dev_priv);
1680
1398261a 1681 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1682 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1683 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1684 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1685 else if (IS_I915GM(dev))
1686 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1687 else if (IS_PINEVIEW(dev))
1688 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1689
36623ef8
PZ		 1690 intel_runtime_pm_put(dev_priv);
1691
5ba2aaaa
CW		 1692 seq_printf(m, "self-refresh: %s\n",
1693 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1694
1695 return 0;
1696}
1697
7648fa99
JB		 1698static int i915_emon_status(struct seq_file *m, void *unused)
1699{
9f25d007 1700 struct drm_info_node *node = m->private;
7648fa99 1701 struct drm_device *dev = node->minor->dev;
e277a1f8 1702 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1703 unsigned long temp, chipset, gfx;
de227ef0
CW		 1704 int ret;
1705
582be6b4
CW		 1706 if (!IS_GEN5(dev))
1707 return -ENODEV;
1708
de227ef0
CW		 1709 ret = mutex_lock_interruptible(&dev->struct_mutex);
1710 if (ret)
1711 return ret;
7648fa99
JB		 1712
1713 temp = i915_mch_val(dev_priv);
1714 chipset = i915_chipset_val(dev_priv);
1715 gfx = i915_gfx_val(dev_priv);
de227ef0 1716 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1717
1718 seq_printf(m, "GMCH temp: %ld\n", temp);
1719 seq_printf(m, "Chipset power: %ld\n", chipset);
1720 seq_printf(m, "GFX power: %ld\n", gfx);
1721 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1722
1723 return 0;
1724}
1725
23b2f8bb
JB		 1726static int i915_ring_freq_table(struct seq_file *m, void *unused)
1727{
9f25d007 1728 struct drm_info_node *node = m->private;
23b2f8bb 1729 struct drm_device *dev = node->minor->dev;
e277a1f8 1730 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1731 int ret = 0;
23b2f8bb
JB		 1732 int gpu_freq, ia_freq;
1733
1c70c0ce 1734 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1735 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1736 return 0;
1737 }
1738
5bfa0199
PZ		 1739 intel_runtime_pm_get(dev_priv);
1740
5c9669ce
TR		 1741 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1742
4fc688ce 1743 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1744 if (ret)
5bfa0199 1745 goto out;
23b2f8bb 1746
267f0c90 1747 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1748
b39fb297
BW		 1749 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1750 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1751 gpu_freq++) {
42c0526c
BW		 1752 ia_freq = gpu_freq;
1753 sandybridge_pcode_read(dev_priv,
1754 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1755 &ia_freq);
3ebecd07 1756 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
7c59a9c1 1757 intel_gpu_freq(dev_priv, gpu_freq),
3ebecd07
CW		 1758 ((ia_freq >> 0) & 0xff) * 100,
1759 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1760 }
1761
4fc688ce 1762 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1763
5bfa0199
PZ		 1764out:
1765 intel_runtime_pm_put(dev_priv);
1766 return ret;
23b2f8bb
JB		 1767}
1768
44834a67
CW		 1769static int i915_opregion(struct seq_file *m, void *unused)
1770{
9f25d007 1771 struct drm_info_node *node = m->private;
44834a67 1772 struct drm_device *dev = node->minor->dev;
e277a1f8 1773 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1774 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1775 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1776 int ret;
1777
0d38f009
DV		 1778 if (data == NULL)
1779 return -ENOMEM;
1780
44834a67
CW		 1781 ret = mutex_lock_interruptible(&dev->struct_mutex);
1782 if (ret)
0d38f009 1783 goto out;
44834a67 1784
0d38f009
DV		 1785 if (opregion->header) {
1786 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1787 seq_write(m, data, OPREGION_SIZE);
1788 }
44834a67
CW		 1789
1790 mutex_unlock(&dev->struct_mutex);
1791
0d38f009
DV		 1792out:
1793 kfree(data);
44834a67
CW		 1794 return 0;
1795}
1796
37811fcc
CW		 1797static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1798{
9f25d007 1799 struct drm_info_node *node = m->private;
37811fcc 1800 struct drm_device *dev = node->minor->dev;
4520f53a 1801 struct intel_fbdev *ifbdev = NULL;
37811fcc 1802 struct intel_framebuffer *fb;
37811fcc 1803
4520f53a
DV		 1804#ifdef CONFIG_DRM_I915_FBDEV
1805 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1806
1807 ifbdev = dev_priv->fbdev;
1808 fb = to_intel_framebuffer(ifbdev->helper.fb);
1809
c1ca506d 1810 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1811 fb->base.width,
1812 fb->base.height,
1813 fb->base.depth,
623f9783 1814 fb->base.bits_per_pixel,
c1ca506d 1815 fb->base.modifier[0],
623f9783 1816 atomic_read(&fb->base.refcount.refcount));
05394f39 1817 describe_obj(m, fb->obj);
267f0c90 1818 seq_putc(m, '\n');
4520f53a 1819#endif
37811fcc 1820
4b096ac1 1821 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1822 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1823 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1824 continue;
1825
c1ca506d 1826 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1827 fb->base.width,
1828 fb->base.height,
1829 fb->base.depth,
623f9783 1830 fb->base.bits_per_pixel,
c1ca506d 1831 fb->base.modifier[0],
623f9783 1832 atomic_read(&fb->base.refcount.refcount));
05394f39 1833 describe_obj(m, fb->obj);
267f0c90 1834 seq_putc(m, '\n');
37811fcc 1835 }
4b096ac1 1836 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1837
1838 return 0;
1839}
1840
c9fe99bd
OM		 1841static void describe_ctx_ringbuf(struct seq_file *m,
1842 struct intel_ringbuffer *ringbuf)
1843{
1844 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1845 ringbuf->space, ringbuf->head, ringbuf->tail,
1846 ringbuf->last_retired_head);
1847}
1848
e76d3630
BW		 1849static int i915_context_status(struct seq_file *m, void *unused)
1850{
9f25d007 1851 struct drm_info_node *node = m->private;
e76d3630 1852 struct drm_device *dev = node->minor->dev;
e277a1f8 1853 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1854 struct intel_engine_cs *ring;
273497e5 1855 struct intel_context *ctx;
a168c293 1856 int ret, i;
e76d3630 1857
f3d28878 1858 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1859 if (ret)
1860 return ret;
1861
a33afea5 1862 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1863 if (!i915.enable_execlists &&
1864 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1865 continue;
1866
a33afea5 1867 seq_puts(m, "HW context ");
3ccfd19d 1868 describe_ctx(m, ctx);
c9fe99bd 1869 for_each_ring(ring, dev_priv, i) {
a33afea5 1870 if (ring->default_context == ctx)
c9fe99bd
OM		 1871 seq_printf(m, "(default context %s) ",
1872 ring->name);
1873 }
1874
1875 if (i915.enable_execlists) {
1876 seq_putc(m, '\n');
1877 for_each_ring(ring, dev_priv, i) {
1878 struct drm_i915_gem_object *ctx_obj =
1879 ctx->engine[i].state;
1880 struct intel_ringbuffer *ringbuf =
1881 ctx->engine[i].ringbuf;
1882
1883 seq_printf(m, "%s: ", ring->name);
1884 if (ctx_obj)
1885 describe_obj(m, ctx_obj);
1886 if (ringbuf)
1887 describe_ctx_ringbuf(m, ringbuf);
1888 seq_putc(m, '\n');
1889 }
1890 } else {
1891 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1892 }
a33afea5 1893
a33afea5 1894 seq_putc(m, '\n');
a168c293
BW		 1895 }
1896
f3d28878 1897 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1898
1899 return 0;
1900}
1901
064ca1d2
TD		 1902static void i915_dump_lrc_obj(struct seq_file *m,
1903 struct intel_engine_cs *ring,
1904 struct drm_i915_gem_object *ctx_obj)
1905{
1906 struct page *page;
1907 uint32_t *reg_state;
1908 int j;
1909 unsigned long ggtt_offset = 0;
1910
1911 if (ctx_obj == NULL) {
1912 seq_printf(m, "Context on %s with no gem object\n",
1913 ring->name);
1914 return;
1915 }
1916
1917 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1918 intel_execlists_ctx_id(ctx_obj));
1919
1920 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1921 seq_puts(m, "\tNot bound in GGTT\n");
1922 else
1923 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1924
1925 if (i915_gem_object_get_pages(ctx_obj)) {
1926 seq_puts(m, "\tFailed to get pages for context object\n");
1927 return;
1928 }
1929
1930 page = i915_gem_object_get_page(ctx_obj, 1);
1931 if (!WARN_ON(page == NULL)) {
1932 reg_state = kmap_atomic(page);
1933
1934 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1935 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1936 ggtt_offset + 4096 + (j * 4),
1937 reg_state[j], reg_state[j + 1],
1938 reg_state[j + 2], reg_state[j + 3]);
1939 }
1940 kunmap_atomic(reg_state);
1941 }
1942
1943 seq_putc(m, '\n');
1944}
1945
c0ab1ae9
BW		 1946static int i915_dump_lrc(struct seq_file *m, void *unused)
1947{
1948 struct drm_info_node *node = (struct drm_info_node *) m->private;
1949 struct drm_device *dev = node->minor->dev;
1950 struct drm_i915_private *dev_priv = dev->dev_private;
1951 struct intel_engine_cs *ring;
1952 struct intel_context *ctx;
1953 int ret, i;
1954
1955 if (!i915.enable_execlists) {
1956 seq_printf(m, "Logical Ring Contexts are disabled\n");
1957 return 0;
1958 }
1959
1960 ret = mutex_lock_interruptible(&dev->struct_mutex);
1961 if (ret)
1962 return ret;
1963
1964 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1965 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 1966 if (ring->default_context != ctx)
1967 i915_dump_lrc_obj(m, ring,
1968 ctx->engine[i].state);
c0ab1ae9
BW		 1969 }
1970 }
1971
1972 mutex_unlock(&dev->struct_mutex);
1973
1974 return 0;
1975}
1976
4ba70e44
OM		 1977static int i915_execlists(struct seq_file *m, void *data)
1978{
1979 struct drm_info_node *node = (struct drm_info_node *)m->private;
1980 struct drm_device *dev = node->minor->dev;
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 struct intel_engine_cs *ring;
1983 u32 status_pointer;
1984 u8 read_pointer;
1985 u8 write_pointer;
1986 u32 status;
1987 u32 ctx_id;
1988 struct list_head *cursor;
1989 int ring_id, i;
1990 int ret;
1991
1992 if (!i915.enable_execlists) {
1993 seq_puts(m, "Logical Ring Contexts are disabled\n");
1994 return 0;
1995 }
1996
1997 ret = mutex_lock_interruptible(&dev->struct_mutex);
1998 if (ret)
1999 return ret;
2000
fc0412ec
MT		 2001 intel_runtime_pm_get(dev_priv);
2002
4ba70e44 2003 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2004 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2005 int count = 0;
2006 unsigned long flags;
2007
2008 seq_printf(m, "%s\n", ring->name);
2009
2010 status = I915_READ(RING_EXECLIST_STATUS(ring));
2011 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2012 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2013 status, ctx_id);
2014
2015 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2016 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2017
2018 read_pointer = ring->next_context_status_buffer;
2019 write_pointer = status_pointer & 0x07;
2020 if (read_pointer > write_pointer)
2021 write_pointer += 6;
2022 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2023 read_pointer, write_pointer);
2024
2025 for (i = 0; i < 6; i++) {
2026 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2027 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2028
2029 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2030 i, status, ctx_id);
2031 }
2032
2033 spin_lock_irqsave(&ring->execlist_lock, flags);
2034 list_for_each(cursor, &ring->execlist_queue)
2035 count++;
2036 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2037 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2038 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2039
2040 seq_printf(m, "\t%d requests in queue\n", count);
2041 if (head_req) {
2042 struct drm_i915_gem_object *ctx_obj;
2043
6d3d8274 2044 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2045 seq_printf(m, "\tHead request id: %u\n",
2046 intel_execlists_ctx_id(ctx_obj));
2047 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2048 head_req->tail);
4ba70e44
OM		 2049 }
2050
2051 seq_putc(m, '\n');
2052 }
2053
fc0412ec 2054 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2055 mutex_unlock(&dev->struct_mutex);
2056
2057 return 0;
2058}
2059
ea16a3cd
DV		 2060static const char *swizzle_string(unsigned swizzle)
2061{
aee56cff 2062 switch (swizzle) {
ea16a3cd
DV		 2063 case I915_BIT_6_SWIZZLE_NONE:
2064 return "none";
2065 case I915_BIT_6_SWIZZLE_9:
2066 return "bit9";
2067 case I915_BIT_6_SWIZZLE_9_10:
2068 return "bit9/bit10";
2069 case I915_BIT_6_SWIZZLE_9_11:
2070 return "bit9/bit11";
2071 case I915_BIT_6_SWIZZLE_9_10_11:
2072 return "bit9/bit10/bit11";
2073 case I915_BIT_6_SWIZZLE_9_17:
2074 return "bit9/bit17";
2075 case I915_BIT_6_SWIZZLE_9_10_17:
2076 return "bit9/bit10/bit17";
2077 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2078 return "unknown";
ea16a3cd
DV		 2079 }
2080
2081 return "bug";
2082}
2083
2084static int i915_swizzle_info(struct seq_file *m, void *data)
2085{
9f25d007 2086 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2087 struct drm_device *dev = node->minor->dev;
2088 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2089 int ret;
2090
2091 ret = mutex_lock_interruptible(&dev->struct_mutex);
2092 if (ret)
2093 return ret;
c8c8fb33 2094 intel_runtime_pm_get(dev_priv);
ea16a3cd 2095
ea16a3cd
DV		 2096 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2097 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2098 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2099 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2100
2101 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2102 seq_printf(m, "DDC = 0x%08x\n",
2103 I915_READ(DCC));
656bfa3a
DV		 2104 seq_printf(m, "DDC2 = 0x%08x\n",
2105 I915_READ(DCC2));
ea16a3cd
DV		 2106 seq_printf(m, "C0DRB3 = 0x%04x\n",
2107 I915_READ16(C0DRB3));
2108 seq_printf(m, "C1DRB3 = 0x%04x\n",
2109 I915_READ16(C1DRB3));
9d3203e1 2110 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2111 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2112 I915_READ(MAD_DIMM_C0));
2113 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2114 I915_READ(MAD_DIMM_C1));
2115 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2116 I915_READ(MAD_DIMM_C2));
2117 seq_printf(m, "TILECTL = 0x%08x\n",
2118 I915_READ(TILECTL));
5907f5fb 2119 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2120 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2121 I915_READ(GAMTARBMODE));
2122 else
2123 seq_printf(m, "ARB_MODE = 0x%08x\n",
2124 I915_READ(ARB_MODE));
3fa7d235
DV		 2125 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2126 I915_READ(DISP_ARB_CTL));
ea16a3cd 2127 }
656bfa3a
DV		 2128
2129 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2130 seq_puts(m, "L-shaped memory detected\n");
2131
c8c8fb33 2132 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2133 mutex_unlock(&dev->struct_mutex);
2134
2135 return 0;
2136}
2137
1c60fef5
BW		 2138static int per_file_ctx(int id, void *ptr, void *data)
2139{
273497e5 2140 struct intel_context *ctx = ptr;
1c60fef5 2141 struct seq_file *m = data;
ae6c4806
DV		 2142 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2143
2144 if (!ppgtt) {
2145 seq_printf(m, " no ppgtt for context %d\n",
2146 ctx->user_handle);
2147 return 0;
2148 }
1c60fef5 2149
f83d6518
OM		 2150 if (i915_gem_context_is_default(ctx))
2151 seq_puts(m, " default context:\n");
2152 else
821d66dd 2153 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2154 ppgtt->debug_dump(ppgtt, m);
2155
2156 return 0;
2157}
2158
77df6772 2159static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2160{
3cf17fc5 2161 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2162 struct intel_engine_cs *ring;
77df6772
BW		 2163 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2164 int unused, i;
3cf17fc5 2165
77df6772
BW		 2166 if (!ppgtt)
2167 return;
2168
2169 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2170 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2171 for_each_ring(ring, dev_priv, unused) {
2172 seq_printf(m, "%s\n", ring->name);
2173 for (i = 0; i < 4; i++) {
2174 u32 offset = 0x270 + i * 8;
2175 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2176 pdp <<= 32;
2177 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2178 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2179 }
2180 }
2181}
2182
2183static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2184{
2185 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2186 struct intel_engine_cs *ring;
1c60fef5 2187 struct drm_file *file;
77df6772 2188 int i;
3cf17fc5 2189
3cf17fc5
DV		 2190 if (INTEL_INFO(dev)->gen == 6)
2191 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2192
a2c7f6fd 2193 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2194 seq_printf(m, "%s\n", ring->name);
2195 if (INTEL_INFO(dev)->gen == 7)
2196 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2197 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2198 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2199 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2200 }
2201 if (dev_priv->mm.aliasing_ppgtt) {
2202 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2203
267f0c90 2204 seq_puts(m, "aliasing PPGTT:\n");
7324cc04 2205 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
1c60fef5 2206
87d60b63 2207 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2208 }
1c60fef5
BW		 2209
2210 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2211 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2212
1c60fef5
BW		 2213 seq_printf(m, "proc: %s\n",
2214 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2215 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2216 }
2217 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2218}
2219
2220static int i915_ppgtt_info(struct seq_file *m, void *data)
2221{
9f25d007 2222 struct drm_info_node *node = m->private;
77df6772 2223 struct drm_device *dev = node->minor->dev;
c8c8fb33 2224 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2225
2226 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2227 if (ret)
2228 return ret;
c8c8fb33 2229 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2230
2231 if (INTEL_INFO(dev)->gen >= 8)
2232 gen8_ppgtt_info(m, dev);
2233 else if (INTEL_INFO(dev)->gen >= 6)
2234 gen6_ppgtt_info(m, dev);
2235
c8c8fb33 2236 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2237 mutex_unlock(&dev->struct_mutex);
2238
2239 return 0;
2240}
2241
63573eb7
BW		 2242static int i915_llc(struct seq_file *m, void *data)
2243{
9f25d007 2244 struct drm_info_node *node = m->private;
63573eb7
BW		 2245 struct drm_device *dev = node->minor->dev;
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2249 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2250 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2251
2252 return 0;
2253}
2254
e91fd8c6
RV		 2255static int i915_edp_psr_status(struct seq_file *m, void *data)
2256{
2257 struct drm_info_node *node = m->private;
2258 struct drm_device *dev = node->minor->dev;
2259 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2260 u32 psrperf = 0;
a6cbdb8e
RV		 2261 u32 stat[3];
2262 enum pipe pipe;
a031d709 2263 bool enabled = false;
e91fd8c6 2264
3553a8ea
DL		 2265 if (!HAS_PSR(dev)) {
2266 seq_puts(m, "PSR not supported\n");
2267 return 0;
2268 }
2269
c8c8fb33
PZ		 2270 intel_runtime_pm_get(dev_priv);
2271
fa128fa6 2272 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2273 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2274 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2275 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2276 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2277 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2278 dev_priv->psr.busy_frontbuffer_bits);
2279 seq_printf(m, "Re-enable work scheduled: %s\n",
2280 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2281
3553a8ea
DL		 2282 if (HAS_DDI(dev))
2283 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2284 else {
2285 for_each_pipe(dev_priv, pipe) {
2286 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2287 VLV_EDP_PSR_CURR_STATE_MASK;
2288 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2289 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2290 enabled = true;
a6cbdb8e
RV		 2291 }
2292 }
2293 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2294
2295 if (!HAS_DDI(dev))
2296 for_each_pipe(dev_priv, pipe) {
2297 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2298 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2299 seq_printf(m, " pipe %c", pipe_name(pipe));
2300 }
2301 seq_puts(m, "\n");
e91fd8c6 2302
fb495814
RV		 2303 seq_printf(m, "Link standby: %s\n",
2304 yesno((bool)dev_priv->psr.link_standby));
2305
a6cbdb8e 2306 /* CHV PSR has no kind of performance counter */
3553a8ea 2307 if (HAS_DDI(dev)) {
a031d709
RV		 2308 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2309 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2310
2311 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2312 }
fa128fa6 2313 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2314
c8c8fb33 2315 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2316 return 0;
2317}
2318
d2e216d0
RV		 2319static int i915_sink_crc(struct seq_file *m, void *data)
2320{
2321 struct drm_info_node *node = m->private;
2322 struct drm_device *dev = node->minor->dev;
2323 struct intel_encoder *encoder;
2324 struct intel_connector *connector;
2325 struct intel_dp *intel_dp = NULL;
2326 int ret;
2327 u8 crc[6];
2328
2329 drm_modeset_lock_all(dev);
aca5e361 2330 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2331
2332 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2333 continue;
2334
b6ae3c7c
PZ		 2335 if (!connector->base.encoder)
2336 continue;
2337
d2e216d0
RV		 2338 encoder = to_intel_encoder(connector->base.encoder);
2339 if (encoder->type != INTEL_OUTPUT_EDP)
2340 continue;
2341
2342 intel_dp = enc_to_intel_dp(&encoder->base);
2343
2344 ret = intel_dp_sink_crc(intel_dp, crc);
2345 if (ret)
2346 goto out;
2347
2348 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2349 crc[0], crc[1], crc[2],
2350 crc[3], crc[4], crc[5]);
2351 goto out;
2352 }
2353 ret = -ENODEV;
2354out:
2355 drm_modeset_unlock_all(dev);
2356 return ret;
2357}
2358
ec013e7f
JB		 2359static int i915_energy_uJ(struct seq_file *m, void *data)
2360{
2361 struct drm_info_node *node = m->private;
2362 struct drm_device *dev = node->minor->dev;
2363 struct drm_i915_private *dev_priv = dev->dev_private;
2364 u64 power;
2365 u32 units;
2366
2367 if (INTEL_INFO(dev)->gen < 6)
2368 return -ENODEV;
2369
36623ef8
PZ		 2370 intel_runtime_pm_get(dev_priv);
2371
ec013e7f
JB		 2372 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2373 power = (power & 0x1f00) >> 8;
2374 units = 1000000 / (1 << power); /* convert to uJ */
2375 power = I915_READ(MCH_SECP_NRG_STTS);
2376 power *= units;
2377
36623ef8
PZ		 2378 intel_runtime_pm_put(dev_priv);
2379
ec013e7f 2380 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2381
2382 return 0;
2383}
2384
2385static int i915_pc8_status(struct seq_file *m, void *unused)
2386{
9f25d007 2387 struct drm_info_node *node = m->private;
371db66a
PZ		 2388 struct drm_device *dev = node->minor->dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390
85b8d5c2 2391 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2392 seq_puts(m, "not supported\n");
2393 return 0;
2394 }
2395
86c4ec0d 2396 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2397 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2398 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2399
ec013e7f
JB		 2400 return 0;
2401}
2402
1da51581
ID		 2403static const char *power_domain_str(enum intel_display_power_domain domain)
2404{
2405 switch (domain) {
2406 case POWER_DOMAIN_PIPE_A:
2407 return "PIPE_A";
2408 case POWER_DOMAIN_PIPE_B:
2409 return "PIPE_B";
2410 case POWER_DOMAIN_PIPE_C:
2411 return "PIPE_C";
2412 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2413 return "PIPE_A_PANEL_FITTER";
2414 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2415 return "PIPE_B_PANEL_FITTER";
2416 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2417 return "PIPE_C_PANEL_FITTER";
2418 case POWER_DOMAIN_TRANSCODER_A:
2419 return "TRANSCODER_A";
2420 case POWER_DOMAIN_TRANSCODER_B:
2421 return "TRANSCODER_B";
2422 case POWER_DOMAIN_TRANSCODER_C:
2423 return "TRANSCODER_C";
2424 case POWER_DOMAIN_TRANSCODER_EDP:
2425 return "TRANSCODER_EDP";
319be8ae
ID		 2426 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2427 return "PORT_DDI_A_2_LANES";
2428 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2429 return "PORT_DDI_A_4_LANES";
2430 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2431 return "PORT_DDI_B_2_LANES";
2432 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2433 return "PORT_DDI_B_4_LANES";
2434 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2435 return "PORT_DDI_C_2_LANES";
2436 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2437 return "PORT_DDI_C_4_LANES";
2438 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2439 return "PORT_DDI_D_2_LANES";
2440 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2441 return "PORT_DDI_D_4_LANES";
2442 case POWER_DOMAIN_PORT_DSI:
2443 return "PORT_DSI";
2444 case POWER_DOMAIN_PORT_CRT:
2445 return "PORT_CRT";
2446 case POWER_DOMAIN_PORT_OTHER:
2447 return "PORT_OTHER";
1da51581
ID		 2448 case POWER_DOMAIN_VGA:
2449 return "VGA";
2450 case POWER_DOMAIN_AUDIO:
2451 return "AUDIO";
bd2bb1b9
PZ		 2452 case POWER_DOMAIN_PLLS:
2453 return "PLLS";
1407121a
S		 2454 case POWER_DOMAIN_AUX_A:
2455 return "AUX_A";
2456 case POWER_DOMAIN_AUX_B:
2457 return "AUX_B";
2458 case POWER_DOMAIN_AUX_C:
2459 return "AUX_C";
2460 case POWER_DOMAIN_AUX_D:
2461 return "AUX_D";
1da51581
ID		 2462 case POWER_DOMAIN_INIT:
2463 return "INIT";
2464 default:
5f77eeb0 2465 MISSING_CASE(domain);
1da51581
ID		 2466 return "?";
2467 }
2468}
2469
2470static int i915_power_domain_info(struct seq_file *m, void *unused)
2471{
9f25d007 2472 struct drm_info_node *node = m->private;
1da51581
ID		 2473 struct drm_device *dev = node->minor->dev;
2474 struct drm_i915_private *dev_priv = dev->dev_private;
2475 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2476 int i;
2477
2478 mutex_lock(&power_domains->lock);
2479
2480 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2481 for (i = 0; i < power_domains->power_well_count; i++) {
2482 struct i915_power_well *power_well;
2483 enum intel_display_power_domain power_domain;
2484
2485 power_well = &power_domains->power_wells[i];
2486 seq_printf(m, "%-25s %d\n", power_well->name,
2487 power_well->count);
2488
2489 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2490 power_domain++) {
2491 if (!(BIT(power_domain) & power_well->domains))
2492 continue;
2493
2494 seq_printf(m, " %-23s %d\n",
2495 power_domain_str(power_domain),
2496 power_domains->domain_use_count[power_domain]);
2497 }
2498 }
2499
2500 mutex_unlock(&power_domains->lock);
2501
2502 return 0;
2503}
2504
53f5e3ca
JB		 2505static void intel_seq_print_mode(struct seq_file *m, int tabs,
2506 struct drm_display_mode *mode)
2507{
2508 int i;
2509
2510 for (i = 0; i < tabs; i++)
2511 seq_putc(m, '\t');
2512
2513 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2514 mode->base.id, mode->name,
2515 mode->vrefresh, mode->clock,
2516 mode->hdisplay, mode->hsync_start,
2517 mode->hsync_end, mode->htotal,
2518 mode->vdisplay, mode->vsync_start,
2519 mode->vsync_end, mode->vtotal,
2520 mode->type, mode->flags);
2521}
2522
2523static void intel_encoder_info(struct seq_file *m,
2524 struct intel_crtc *intel_crtc,
2525 struct intel_encoder *intel_encoder)
2526{
9f25d007 2527 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2528 struct drm_device *dev = node->minor->dev;
2529 struct drm_crtc *crtc = &intel_crtc->base;
2530 struct intel_connector *intel_connector;
2531 struct drm_encoder *encoder;
2532
2533 encoder = &intel_encoder->base;
2534 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2535 encoder->base.id, encoder->name);
53f5e3ca
JB		 2536 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2537 struct drm_connector *connector = &intel_connector->base;
2538 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2539 connector->base.id,
c23cc417 2540 connector->name,
53f5e3ca
JB		 2541 drm_get_connector_status_name(connector->status));
2542 if (connector->status == connector_status_connected) {
2543 struct drm_display_mode *mode = &crtc->mode;
2544 seq_printf(m, ", mode:\n");
2545 intel_seq_print_mode(m, 2, mode);
2546 } else {
2547 seq_putc(m, '\n');
2548 }
2549 }
2550}
2551
2552static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2553{
9f25d007 2554 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2555 struct drm_device *dev = node->minor->dev;
2556 struct drm_crtc *crtc = &intel_crtc->base;
2557 struct intel_encoder *intel_encoder;
2558
5aa8a937
MR		 2559 if (crtc->primary->fb)
2560 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2561 crtc->primary->fb->base.id, crtc->x, crtc->y,
2562 crtc->primary->fb->width, crtc->primary->fb->height);
2563 else
2564 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2565 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2566 intel_encoder_info(m, intel_crtc, intel_encoder);
2567}
2568
2569static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2570{
2571 struct drm_display_mode *mode = panel->fixed_mode;
2572
2573 seq_printf(m, "\tfixed mode:\n");
2574 intel_seq_print_mode(m, 2, mode);
2575}
2576
2577static void intel_dp_info(struct seq_file *m,
2578 struct intel_connector *intel_connector)
2579{
2580 struct intel_encoder *intel_encoder = intel_connector->encoder;
2581 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2582
2583 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2584 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2585 "no");
2586 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2587 intel_panel_info(m, &intel_connector->panel);
2588}
2589
2590static void intel_hdmi_info(struct seq_file *m,
2591 struct intel_connector *intel_connector)
2592{
2593 struct intel_encoder *intel_encoder = intel_connector->encoder;
2594 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2595
2596 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2597 "no");
2598}
2599
2600static void intel_lvds_info(struct seq_file *m,
2601 struct intel_connector *intel_connector)
2602{
2603 intel_panel_info(m, &intel_connector->panel);
2604}
2605
2606static void intel_connector_info(struct seq_file *m,
2607 struct drm_connector *connector)
2608{
2609 struct intel_connector *intel_connector = to_intel_connector(connector);
2610 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2611 struct drm_display_mode *mode;
53f5e3ca
JB		 2612
2613 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2614 connector->base.id, connector->name,
53f5e3ca
JB		 2615 drm_get_connector_status_name(connector->status));
2616 if (connector->status == connector_status_connected) {
2617 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2618 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2619 connector->display_info.width_mm,
2620 connector->display_info.height_mm);
2621 seq_printf(m, "\tsubpixel order: %s\n",
2622 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2623 seq_printf(m, "\tCEA rev: %d\n",
2624 connector->display_info.cea_rev);
2625 }
36cd7444
DA		 2626 if (intel_encoder) {
2627 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2628 intel_encoder->type == INTEL_OUTPUT_EDP)
2629 intel_dp_info(m, intel_connector);
2630 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2631 intel_hdmi_info(m, intel_connector);
2632 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2633 intel_lvds_info(m, intel_connector);
2634 }
53f5e3ca 2635
f103fc7d
JB		 2636 seq_printf(m, "\tmodes:\n");
2637 list_for_each_entry(mode, &connector->modes, head)
2638 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2639}
2640
065f2ec2
CW		 2641static bool cursor_active(struct drm_device *dev, int pipe)
2642{
2643 struct drm_i915_private *dev_priv = dev->dev_private;
2644 u32 state;
2645
2646 if (IS_845G(dev) || IS_I865G(dev))
2647 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2648 else
5efb3e28 2649 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2650
2651 return state;
2652}
2653
2654static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2655{
2656 struct drm_i915_private *dev_priv = dev->dev_private;
2657 u32 pos;
2658
5efb3e28 2659 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2660
2661 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2662 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2663 *x = -*x;
2664
2665 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2666 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2667 *y = -*y;
2668
2669 return cursor_active(dev, pipe);
2670}
2671
53f5e3ca
JB		 2672static int i915_display_info(struct seq_file *m, void *unused)
2673{
9f25d007 2674 struct drm_info_node *node = m->private;
53f5e3ca 2675 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2676 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2677 struct intel_crtc *crtc;
53f5e3ca
JB		 2678 struct drm_connector *connector;
2679
b0e5ddf3 2680 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2681 drm_modeset_lock_all(dev);
2682 seq_printf(m, "CRTC info\n");
2683 seq_printf(m, "---------\n");
d3fcc808 2684 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2685 bool active;
2686 int x, y;
53f5e3ca 2687
57127efa 2688 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2689 crtc->base.base.id, pipe_name(crtc->pipe),
6e3c9717
ACO		 2690 yesno(crtc->active), crtc->config->pipe_src_w,
2691 crtc->config->pipe_src_h);
a23dc658 2692 if (crtc->active) {
065f2ec2
CW		 2693 intel_crtc_info(m, crtc);
2694
a23dc658 2695 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2696 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2697 yesno(crtc->cursor_base),
3dd512fb
MR		 2698 x, y, crtc->base.cursor->state->crtc_w,
2699 crtc->base.cursor->state->crtc_h,
57127efa 2700 crtc->cursor_addr, yesno(active));
a23dc658 2701 }
cace841c
DV		 2702
2703 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2704 yesno(!crtc->cpu_fifo_underrun_disabled),
2705 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2706 }
2707
2708 seq_printf(m, "\n");
2709 seq_printf(m, "Connector info\n");
2710 seq_printf(m, "--------------\n");
2711 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2712 intel_connector_info(m, connector);
2713 }
2714 drm_modeset_unlock_all(dev);
b0e5ddf3 2715 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2716
2717 return 0;
2718}
2719
e04934cf
BW		 2720static int i915_semaphore_status(struct seq_file *m, void *unused)
2721{
2722 struct drm_info_node *node = (struct drm_info_node *) m->private;
2723 struct drm_device *dev = node->minor->dev;
2724 struct drm_i915_private *dev_priv = dev->dev_private;
2725 struct intel_engine_cs *ring;
2726 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2727 int i, j, ret;
2728
2729 if (!i915_semaphore_is_enabled(dev)) {
2730 seq_puts(m, "Semaphores are disabled\n");
2731 return 0;
2732 }
2733
2734 ret = mutex_lock_interruptible(&dev->struct_mutex);
2735 if (ret)
2736 return ret;
03872064 2737 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2738
2739 if (IS_BROADWELL(dev)) {
2740 struct page *page;
2741 uint64_t *seqno;
2742
2743 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2744
2745 seqno = (uint64_t *)kmap_atomic(page);
2746 for_each_ring(ring, dev_priv, i) {
2747 uint64_t offset;
2748
2749 seq_printf(m, "%s\n", ring->name);
2750
2751 seq_puts(m, " Last signal:");
2752 for (j = 0; j < num_rings; j++) {
2753 offset = i * I915_NUM_RINGS + j;
2754 seq_printf(m, "0x%08llx (0x%02llx) ",
2755 seqno[offset], offset * 8);
2756 }
2757 seq_putc(m, '\n');
2758
2759 seq_puts(m, " Last wait: ");
2760 for (j = 0; j < num_rings; j++) {
2761 offset = i + (j * I915_NUM_RINGS);
2762 seq_printf(m, "0x%08llx (0x%02llx) ",
2763 seqno[offset], offset * 8);
2764 }
2765 seq_putc(m, '\n');
2766
2767 }
2768 kunmap_atomic(seqno);
2769 } else {
2770 seq_puts(m, " Last signal:");
2771 for_each_ring(ring, dev_priv, i)
2772 for (j = 0; j < num_rings; j++)
2773 seq_printf(m, "0x%08x\n",
2774 I915_READ(ring->semaphore.mbox.signal[j]));
2775 seq_putc(m, '\n');
2776 }
2777
2778 seq_puts(m, "\nSync seqno:\n");
2779 for_each_ring(ring, dev_priv, i) {
2780 for (j = 0; j < num_rings; j++) {
2781 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2782 }
2783 seq_putc(m, '\n');
2784 }
2785 seq_putc(m, '\n');
2786
03872064 2787 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2788 mutex_unlock(&dev->struct_mutex);
2789 return 0;
2790}
2791
728e29d7
DV		 2792static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2793{
2794 struct drm_info_node *node = (struct drm_info_node *) m->private;
2795 struct drm_device *dev = node->minor->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 int i;
2798
2799 drm_modeset_lock_all(dev);
2800 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2801 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2802
2803 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2804 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2805 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2806 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2807 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2808 seq_printf(m, " dpll_md: 0x%08x\n",
2809 pll->config.hw_state.dpll_md);
2810 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2811 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2812 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2813 }
2814 drm_modeset_unlock_all(dev);
2815
2816 return 0;
2817}
2818
1ed1ef9d 2819static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2820{
2821 int i;
2822 int ret;
2823 struct drm_info_node *node = (struct drm_info_node *) m->private;
2824 struct drm_device *dev = node->minor->dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826
888b5995
AS		 2827 ret = mutex_lock_interruptible(&dev->struct_mutex);
2828 if (ret)
2829 return ret;
2830
2831 intel_runtime_pm_get(dev_priv);
2832
7225342a
MK		 2833 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2834 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2835 u32 addr, mask, value, read;
2836 bool ok;
888b5995 2837
7225342a
MK		 2838 addr = dev_priv->workarounds.reg[i].addr;
2839 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2840 value = dev_priv->workarounds.reg[i].value;
2841 read = I915_READ(addr);
2842 ok = (value & mask) == (read & mask);
2843 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2844 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2845 }
2846
2847 intel_runtime_pm_put(dev_priv);
2848 mutex_unlock(&dev->struct_mutex);
2849
2850 return 0;
2851}
2852
c5511e44
DL		 2853static int i915_ddb_info(struct seq_file *m, void *unused)
2854{
2855 struct drm_info_node *node = m->private;
2856 struct drm_device *dev = node->minor->dev;
2857 struct drm_i915_private *dev_priv = dev->dev_private;
2858 struct skl_ddb_allocation *ddb;
2859 struct skl_ddb_entry *entry;
2860 enum pipe pipe;
2861 int plane;
2862
2fcffe19
DL		 2863 if (INTEL_INFO(dev)->gen < 9)
2864 return 0;
2865
c5511e44
DL		 2866 drm_modeset_lock_all(dev);
2867
2868 ddb = &dev_priv->wm.skl_hw.ddb;
2869
2870 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2871
2872 for_each_pipe(dev_priv, pipe) {
2873 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2874
dd740780 2875 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 2876 entry = &ddb->plane[pipe][plane];
2877 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2878 entry->start, entry->end,
2879 skl_ddb_entry_size(entry));
2880 }
2881
2882 entry = &ddb->cursor[pipe];
2883 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2884 entry->end, skl_ddb_entry_size(entry));
2885 }
2886
2887 drm_modeset_unlock_all(dev);
2888
2889 return 0;
2890}
2891
a54746e3
VK		 2892static void drrs_status_per_crtc(struct seq_file *m,
2893 struct drm_device *dev, struct intel_crtc *intel_crtc)
2894{
2895 struct intel_encoder *intel_encoder;
2896 struct drm_i915_private *dev_priv = dev->dev_private;
2897 struct i915_drrs *drrs = &dev_priv->drrs;
2898 int vrefresh = 0;
2899
2900 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
2901 /* Encoder connected on this CRTC */
2902 switch (intel_encoder->type) {
2903 case INTEL_OUTPUT_EDP:
2904 seq_puts(m, "eDP:\n");
2905 break;
2906 case INTEL_OUTPUT_DSI:
2907 seq_puts(m, "DSI:\n");
2908 break;
2909 case INTEL_OUTPUT_HDMI:
2910 seq_puts(m, "HDMI:\n");
2911 break;
2912 case INTEL_OUTPUT_DISPLAYPORT:
2913 seq_puts(m, "DP:\n");
2914 break;
2915 default:
2916 seq_printf(m, "Other encoder (id=%d).\n",
2917 intel_encoder->type);
2918 return;
2919 }
2920 }
2921
2922 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
2923 seq_puts(m, "\tVBT: DRRS_type: Static");
2924 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
2925 seq_puts(m, "\tVBT: DRRS_type: Seamless");
2926 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
2927 seq_puts(m, "\tVBT: DRRS_type: None");
2928 else
2929 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
2930
2931 seq_puts(m, "\n\n");
2932
2933 if (intel_crtc->config->has_drrs) {
2934 struct intel_panel *panel;
2935
2936 mutex_lock(&drrs->mutex);
2937 /* DRRS Supported */
2938 seq_puts(m, "\tDRRS Supported: Yes\n");
2939
2940 /* disable_drrs() will make drrs->dp NULL */
2941 if (!drrs->dp) {
2942 seq_puts(m, "Idleness DRRS: Disabled");
2943 mutex_unlock(&drrs->mutex);
2944 return;
2945 }
2946
2947 panel = &drrs->dp->attached_connector->panel;
2948 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
2949 drrs->busy_frontbuffer_bits);
2950
2951 seq_puts(m, "\n\t\t");
2952 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
2953 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
2954 vrefresh = panel->fixed_mode->vrefresh;
2955 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
2956 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
2957 vrefresh = panel->downclock_mode->vrefresh;
2958 } else {
2959 seq_printf(m, "DRRS_State: Unknown(%d)\n",
2960 drrs->refresh_rate_type);
2961 mutex_unlock(&drrs->mutex);
2962 return;
2963 }
2964 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
2965
2966 seq_puts(m, "\n\t\t");
2967 mutex_unlock(&drrs->mutex);
2968 } else {
2969 /* DRRS not supported. Print the VBT parameter*/
2970 seq_puts(m, "\tDRRS Supported : No");
2971 }
2972 seq_puts(m, "\n");
2973}
2974
2975static int i915_drrs_status(struct seq_file *m, void *unused)
2976{
2977 struct drm_info_node *node = m->private;
2978 struct drm_device *dev = node->minor->dev;
2979 struct intel_crtc *intel_crtc;
2980 int active_crtc_cnt = 0;
2981
2982 for_each_intel_crtc(dev, intel_crtc) {
2983 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
2984
2985 if (intel_crtc->active) {
2986 active_crtc_cnt++;
2987 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
2988
2989 drrs_status_per_crtc(m, dev, intel_crtc);
2990 }
2991
2992 drm_modeset_unlock(&intel_crtc->base.mutex);
2993 }
2994
2995 if (!active_crtc_cnt)
2996 seq_puts(m, "No active crtc found\n");
2997
2998 return 0;
2999}
3000
07144428
DL		 3001struct pipe_crc_info {
3002 const char *name;
3003 struct drm_device *dev;
3004 enum pipe pipe;
3005};
3006
11bed958
DA		 3007static int i915_dp_mst_info(struct seq_file *m, void *unused)
3008{
3009 struct drm_info_node *node = (struct drm_info_node *) m->private;
3010 struct drm_device *dev = node->minor->dev;
3011 struct drm_encoder *encoder;
3012 struct intel_encoder *intel_encoder;
3013 struct intel_digital_port *intel_dig_port;
3014 drm_modeset_lock_all(dev);
3015 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3016 intel_encoder = to_intel_encoder(encoder);
3017 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3018 continue;
3019 intel_dig_port = enc_to_dig_port(encoder);
3020 if (!intel_dig_port->dp.can_mst)
3021 continue;
3022
3023 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3024 }
3025 drm_modeset_unlock_all(dev);
3026 return 0;
3027}
3028
07144428
DL		 3029static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3030{
be5c7a90
DL		 3031 struct pipe_crc_info *info = inode->i_private;
3032 struct drm_i915_private *dev_priv = info->dev->dev_private;
3033 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3034
7eb1c496
DV		 3035 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3036 return -ENODEV;
3037
d538bbdf
DL		 3038 spin_lock_irq(&pipe_crc->lock);
3039
3040 if (pipe_crc->opened) {
3041 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3042 return -EBUSY; /* already open */
3043 }
3044
d538bbdf 3045 pipe_crc->opened = true;
07144428
DL		 3046 filep->private_data = inode->i_private;
3047
d538bbdf
DL		 3048 spin_unlock_irq(&pipe_crc->lock);
3049
07144428
DL		 3050 return 0;
3051}
3052
3053static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3054{
be5c7a90
DL		 3055 struct pipe_crc_info *info = inode->i_private;
3056 struct drm_i915_private *dev_priv = info->dev->dev_private;
3057 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3058
d538bbdf
DL		 3059 spin_lock_irq(&pipe_crc->lock);
3060 pipe_crc->opened = false;
3061 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3062
07144428
DL		 3063 return 0;
3064}
3065
3066/* (6 fields, 8 chars each, space separated (5) + '\n') */
3067#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3068/* account for \'0' */
3069#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3070
3071static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3072{
d538bbdf
DL		 3073 assert_spin_locked(&pipe_crc->lock);
3074 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3075 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3076}
3077
3078static ssize_t
3079i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3080 loff_t *pos)
3081{
3082 struct pipe_crc_info *info = filep->private_data;
3083 struct drm_device *dev = info->dev;
3084 struct drm_i915_private *dev_priv = dev->dev_private;
3085 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3086 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3087 int n_entries;
07144428
DL		 3088 ssize_t bytes_read;
3089
3090 /*
3091 * Don't allow user space to provide buffers not big enough to hold
3092 * a line of data.
3093 */
3094 if (count < PIPE_CRC_LINE_LEN)
3095 return -EINVAL;
3096
3097 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3098 return 0;
07144428
DL		 3099
3100 /* nothing to read */
d538bbdf 3101 spin_lock_irq(&pipe_crc->lock);
07144428 3102 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3103 int ret;
3104
3105 if (filep->f_flags & O_NONBLOCK) {
3106 spin_unlock_irq(&pipe_crc->lock);
07144428 3107 return -EAGAIN;
d538bbdf 3108 }
07144428 3109
d538bbdf
DL		 3110 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3111 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3112 if (ret) {
3113 spin_unlock_irq(&pipe_crc->lock);
3114 return ret;
3115 }
8bf1e9f1
SH		 3116 }
3117
07144428 3118 /* We now have one or more entries to read */
9ad6d99f 3119 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3120
07144428 3121 bytes_read = 0;
9ad6d99f
VS		 3122 while (n_entries > 0) {
3123 struct intel_pipe_crc_entry *entry =
3124 &pipe_crc->entries[pipe_crc->tail];
07144428 3125 int ret;
8bf1e9f1 3126
9ad6d99f
VS		 3127 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3128 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3129 break;
3130
3131 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3132 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3133
07144428
DL		 3134 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3135 "%8u %8x %8x %8x %8x %8x\n",
3136 entry->frame, entry->crc[0],
3137 entry->crc[1], entry->crc[2],
3138 entry->crc[3], entry->crc[4]);
3139
9ad6d99f
VS		 3140 spin_unlock_irq(&pipe_crc->lock);
3141
3142 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3143 if (ret == PIPE_CRC_LINE_LEN)
3144 return -EFAULT;
b2c88f5b 3145
9ad6d99f
VS		 3146 user_buf += PIPE_CRC_LINE_LEN;
3147 n_entries--;
3148
3149 spin_lock_irq(&pipe_crc->lock);
3150 }
8bf1e9f1 3151
d538bbdf
DL		 3152 spin_unlock_irq(&pipe_crc->lock);
3153
07144428
DL		 3154 return bytes_read;
3155}
3156
3157static const struct file_operations i915_pipe_crc_fops = {
3158 .owner = THIS_MODULE,
3159 .open = i915_pipe_crc_open,
3160 .read = i915_pipe_crc_read,
3161 .release = i915_pipe_crc_release,
3162};
3163
3164static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3165 {
3166 .name = "i915_pipe_A_crc",
3167 .pipe = PIPE_A,
3168 },
3169 {
3170 .name = "i915_pipe_B_crc",
3171 .pipe = PIPE_B,
3172 },
3173 {
3174 .name = "i915_pipe_C_crc",
3175 .pipe = PIPE_C,
3176 },
3177};
3178
3179static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3180 enum pipe pipe)
3181{
3182 struct drm_device *dev = minor->dev;
3183 struct dentry *ent;
3184 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3185
3186 info->dev = dev;
3187 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3188 &i915_pipe_crc_fops);
f3c5fe97
WY		 3189 if (!ent)
3190 return -ENOMEM;
07144428
DL		 3191
3192 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3193}
3194
e8dfcf78 3195static const char * const pipe_crc_sources[] = {
926321d5
DV		 3196 "none",
3197 "plane1",
3198 "plane2",
3199 "pf",
5b3a856b 3200 "pipe",
3d099a05
DV		 3201 "TV",
3202 "DP-B",
3203 "DP-C",
3204 "DP-D",
46a19188 3205 "auto",
926321d5
DV		 3206};
3207
3208static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3209{
3210 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3211 return pipe_crc_sources[source];
3212}
3213
bd9db02f 3214static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3215{
3216 struct drm_device *dev = m->private;
3217 struct drm_i915_private *dev_priv = dev->dev_private;
3218 int i;
3219
3220 for (i = 0; i < I915_MAX_PIPES; i++)
3221 seq_printf(m, "%c %s\n", pipe_name(i),
3222 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3223
3224 return 0;
3225}
3226
bd9db02f 3227static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3228{
3229 struct drm_device *dev = inode->i_private;
3230
bd9db02f 3231 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3232}
3233
46a19188 3234static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3235 uint32_t *val)
3236{
46a19188
DV		 3237 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3238 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3239
3240 switch (*source) {
52f843f6
DV		 3241 case INTEL_PIPE_CRC_SOURCE_PIPE:
3242 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3243 break;
3244 case INTEL_PIPE_CRC_SOURCE_NONE:
3245 *val = 0;
3246 break;
3247 default:
3248 return -EINVAL;
3249 }
3250
3251 return 0;
3252}
3253
46a19188
DV		 3254static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3255 enum intel_pipe_crc_source *source)
3256{
3257 struct intel_encoder *encoder;
3258 struct intel_crtc *crtc;
26756809 3259 struct intel_digital_port *dig_port;
46a19188
DV		 3260 int ret = 0;
3261
3262 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3263
6e9f798d 3264 drm_modeset_lock_all(dev);
b2784e15 3265 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3266 if (!encoder->base.crtc)
3267 continue;
3268
3269 crtc = to_intel_crtc(encoder->base.crtc);
3270
3271 if (crtc->pipe != pipe)
3272 continue;
3273
3274 switch (encoder->type) {
3275 case INTEL_OUTPUT_TVOUT:
3276 *source = INTEL_PIPE_CRC_SOURCE_TV;
3277 break;
3278 case INTEL_OUTPUT_DISPLAYPORT:
3279 case INTEL_OUTPUT_EDP:
26756809
DV		 3280 dig_port = enc_to_dig_port(&encoder->base);
3281 switch (dig_port->port) {
3282 case PORT_B:
3283 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3284 break;
3285 case PORT_C:
3286 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3287 break;
3288 case PORT_D:
3289 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3290 break;
3291 default:
3292 WARN(1, "nonexisting DP port %c\n",
3293 port_name(dig_port->port));
3294 break;
3295 }
46a19188 3296 break;
6847d71b
PZ		 3297 default:
3298 break;
46a19188
DV		 3299 }
3300 }
6e9f798d 3301 drm_modeset_unlock_all(dev);
46a19188
DV		 3302
3303 return ret;
3304}
3305
3306static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3307 enum pipe pipe,
3308 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3309 uint32_t *val)
3310{
8d2f24ca
DV		 3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312 bool need_stable_symbols = false;
3313
46a19188
DV		 3314 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3315 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3316 if (ret)
3317 return ret;
3318 }
3319
3320 switch (*source) {
7ac0129b
DV		 3321 case INTEL_PIPE_CRC_SOURCE_PIPE:
3322 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3323 break;
3324 case INTEL_PIPE_CRC_SOURCE_DP_B:
3325 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3326 need_stable_symbols = true;
7ac0129b
DV		 3327 break;
3328 case INTEL_PIPE_CRC_SOURCE_DP_C:
3329 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3330 need_stable_symbols = true;
7ac0129b 3331 break;
2be57922
VS		 3332 case INTEL_PIPE_CRC_SOURCE_DP_D:
3333 if (!IS_CHERRYVIEW(dev))
3334 return -EINVAL;
3335 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3336 need_stable_symbols = true;
3337 break;
7ac0129b
DV		 3338 case INTEL_PIPE_CRC_SOURCE_NONE:
3339 *val = 0;
3340 break;
3341 default:
3342 return -EINVAL;
3343 }
3344
8d2f24ca
DV		 3345 /*
3346 * When the pipe CRC tap point is after the transcoders we need
3347 * to tweak symbol-level features to produce a deterministic series of
3348 * symbols for a given frame. We need to reset those features only once
3349 * a frame (instead of every nth symbol):
3350 * - DC-balance: used to ensure a better clock recovery from the data
3351 * link (SDVO)
3352 * - DisplayPort scrambling: used for EMI reduction
3353 */
3354 if (need_stable_symbols) {
3355 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3356
8d2f24ca 3357 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3358 switch (pipe) {
3359 case PIPE_A:
8d2f24ca 3360 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3361 break;
3362 case PIPE_B:
8d2f24ca 3363 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3364 break;
3365 case PIPE_C:
3366 tmp |= PIPE_C_SCRAMBLE_RESET;
3367 break;
3368 default:
3369 return -EINVAL;
3370 }
8d2f24ca
DV		 3371 I915_WRITE(PORT_DFT2_G4X, tmp);
3372 }
3373
7ac0129b
DV		 3374 return 0;
3375}
3376
4b79ebf7 3377static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3378 enum pipe pipe,
3379 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3380 uint32_t *val)
3381{
84093603
DV		 3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383 bool need_stable_symbols = false;
3384
46a19188
DV		 3385 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3386 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3387 if (ret)
3388 return ret;
3389 }
3390
3391 switch (*source) {
4b79ebf7
DV		 3392 case INTEL_PIPE_CRC_SOURCE_PIPE:
3393 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3394 break;
3395 case INTEL_PIPE_CRC_SOURCE_TV:
3396 if (!SUPPORTS_TV(dev))
3397 return -EINVAL;
3398 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3399 break;
3400 case INTEL_PIPE_CRC_SOURCE_DP_B:
3401 if (!IS_G4X(dev))
3402 return -EINVAL;
3403 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3404 need_stable_symbols = true;
4b79ebf7
DV		 3405 break;
3406 case INTEL_PIPE_CRC_SOURCE_DP_C:
3407 if (!IS_G4X(dev))
3408 return -EINVAL;
3409 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3410 need_stable_symbols = true;
4b79ebf7
DV		 3411 break;
3412 case INTEL_PIPE_CRC_SOURCE_DP_D:
3413 if (!IS_G4X(dev))
3414 return -EINVAL;
3415 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3416 need_stable_symbols = true;
4b79ebf7
DV		 3417 break;
3418 case INTEL_PIPE_CRC_SOURCE_NONE:
3419 *val = 0;
3420 break;
3421 default:
3422 return -EINVAL;
3423 }
3424
84093603
DV		 3425 /*
3426 * When the pipe CRC tap point is after the transcoders we need
3427 * to tweak symbol-level features to produce a deterministic series of
3428 * symbols for a given frame. We need to reset those features only once
3429 * a frame (instead of every nth symbol):
3430 * - DC-balance: used to ensure a better clock recovery from the data
3431 * link (SDVO)
3432 * - DisplayPort scrambling: used for EMI reduction
3433 */
3434 if (need_stable_symbols) {
3435 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3436
3437 WARN_ON(!IS_G4X(dev));
3438
3439 I915_WRITE(PORT_DFT_I9XX,
3440 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3441
3442 if (pipe == PIPE_A)
3443 tmp |= PIPE_A_SCRAMBLE_RESET;
3444 else
3445 tmp |= PIPE_B_SCRAMBLE_RESET;
3446
3447 I915_WRITE(PORT_DFT2_G4X, tmp);
3448 }
3449
4b79ebf7
DV		 3450 return 0;
3451}
3452
8d2f24ca
DV		 3453static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3454 enum pipe pipe)
3455{
3456 struct drm_i915_private *dev_priv = dev->dev_private;
3457 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3458
eb736679
VS		 3459 switch (pipe) {
3460 case PIPE_A:
8d2f24ca 3461 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3462 break;
3463 case PIPE_B:
8d2f24ca 3464 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3465 break;
3466 case PIPE_C:
3467 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3468 break;
3469 default:
3470 return;
3471 }
8d2f24ca
DV		 3472 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3473 tmp &= ~DC_BALANCE_RESET_VLV;
3474 I915_WRITE(PORT_DFT2_G4X, tmp);
3475
3476}
3477
84093603
DV		 3478static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3479 enum pipe pipe)
3480{
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3483
3484 if (pipe == PIPE_A)
3485 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3486 else
3487 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3488 I915_WRITE(PORT_DFT2_G4X, tmp);
3489
3490 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3491 I915_WRITE(PORT_DFT_I9XX,
3492 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3493 }
3494}
3495
46a19188 3496static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3497 uint32_t *val)
3498{
46a19188
DV		 3499 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3500 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3501
3502 switch (*source) {
5b3a856b
DV		 3503 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3504 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3505 break;
3506 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3507 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3508 break;
5b3a856b
DV		 3509 case INTEL_PIPE_CRC_SOURCE_PIPE:
3510 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3511 break;
3d099a05 3512 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3513 *val = 0;
3514 break;
3d099a05
DV		 3515 default:
3516 return -EINVAL;
5b3a856b
DV		 3517 }
3518
3519 return 0;
3520}
3521
fabf6e51
DV		 3522static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3523{
3524 struct drm_i915_private *dev_priv = dev->dev_private;
3525 struct intel_crtc *crtc =
3526 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3527
3528 drm_modeset_lock_all(dev);
3529 /*
3530 * If we use the eDP transcoder we need to make sure that we don't
3531 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3532 * relevant on hsw with pipe A when using the always-on power well
3533 * routing.
3534 */
6e3c9717
ACO		 3535 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3536 !crtc->config->pch_pfit.enabled) {
3537 crtc->config->pch_pfit.force_thru = true;
fabf6e51
DV		 3538
3539 intel_display_power_get(dev_priv,
3540 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3541
3542 dev_priv->display.crtc_disable(&crtc->base);
3543 dev_priv->display.crtc_enable(&crtc->base);
3544 }
3545 drm_modeset_unlock_all(dev);
3546}
3547
3548static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3549{
3550 struct drm_i915_private *dev_priv = dev->dev_private;
3551 struct intel_crtc *crtc =
3552 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3553
3554 drm_modeset_lock_all(dev);
3555 /*
3556 * If we use the eDP transcoder we need to make sure that we don't
3557 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3558 * relevant on hsw with pipe A when using the always-on power well
3559 * routing.
3560 */
6e3c9717
ACO		 3561 if (crtc->config->pch_pfit.force_thru) {
3562 crtc->config->pch_pfit.force_thru = false;
fabf6e51
DV		 3563
3564 dev_priv->display.crtc_disable(&crtc->base);
3565 dev_priv->display.crtc_enable(&crtc->base);
3566
3567 intel_display_power_put(dev_priv,
3568 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3569 }
3570 drm_modeset_unlock_all(dev);
3571}
3572
3573static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3574 enum pipe pipe,
3575 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3576 uint32_t *val)
3577{
46a19188
DV		 3578 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3579 *source = INTEL_PIPE_CRC_SOURCE_PF;
3580
3581 switch (*source) {
5b3a856b
DV		 3582 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3583 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3584 break;
3585 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3586 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3587 break;
3588 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3589 if (IS_HASWELL(dev) && pipe == PIPE_A)
3590 hsw_trans_edp_pipe_A_crc_wa(dev);
3591
5b3a856b
DV		 3592 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3593 break;
3d099a05 3594 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3595 *val = 0;
3596 break;
3d099a05
DV		 3597 default:
3598 return -EINVAL;
5b3a856b
DV		 3599 }
3600
3601 return 0;
3602}
3603
926321d5
DV		 3604static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3605 enum intel_pipe_crc_source source)
3606{
3607 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3608 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3609 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3610 pipe));
432f3342 3611 u32 val = 0; /* shut up gcc */
5b3a856b 3612 int ret;
926321d5 3613
cc3da175
DL		 3614 if (pipe_crc->source == source)
3615 return 0;
3616
ae676fcd
DL		 3617 /* forbid changing the source without going back to 'none' */
3618 if (pipe_crc->source && source)
3619 return -EINVAL;
3620
9d8b0588
DV		 3621 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3622 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3623 return -EIO;
3624 }
3625
52f843f6 3626 if (IS_GEN2(dev))
46a19188 3627 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3628 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3629 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3630 else if (IS_VALLEYVIEW(dev))
fabf6e51 3631 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3632 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3633 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3634 else
fabf6e51 3635 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3636
3637 if (ret != 0)
3638 return ret;
3639
4b584369
DL		 3640 /* none -> real source transition */
3641 if (source) {
4252fbc3
VS		 3642 struct intel_pipe_crc_entry *entries;
3643
7cd6ccff
DL		 3644 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3645 pipe_name(pipe), pipe_crc_source_name(source));
3646
3cf54b34
VS		 3647 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3648 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3649 GFP_KERNEL);
3650 if (!entries)
e5f75aca
DL		 3651 return -ENOMEM;
3652
8c740dce
PZ		 3653 /*
3654 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3655 * enabled and disabled dynamically based on package C states,
3656 * user space can't make reliable use of the CRCs, so let's just
3657 * completely disable it.
3658 */
3659 hsw_disable_ips(crtc);
3660
d538bbdf 3661 spin_lock_irq(&pipe_crc->lock);
64387b61 3662 kfree(pipe_crc->entries);
4252fbc3 3663 pipe_crc->entries = entries;
d538bbdf
DL		 3664 pipe_crc->head = 0;
3665 pipe_crc->tail = 0;
3666 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3667 }
3668
cc3da175 3669 pipe_crc->source = source;
926321d5 3670
926321d5
DV		 3671 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3672 POSTING_READ(PIPE_CRC_CTL(pipe));
3673
e5f75aca
DL		 3674 /* real source -> none transition */
3675 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3676 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3677 struct intel_crtc *crtc =
3678 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3679
7cd6ccff
DL		 3680 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3681 pipe_name(pipe));
3682
a33d7105
DV		 3683 drm_modeset_lock(&crtc->base.mutex, NULL);
3684 if (crtc->active)
3685 intel_wait_for_vblank(dev, pipe);
3686 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3687
d538bbdf
DL		 3688 spin_lock_irq(&pipe_crc->lock);
3689 entries = pipe_crc->entries;
e5f75aca 3690 pipe_crc->entries = NULL;
9ad6d99f
VS		 3691 pipe_crc->head = 0;
3692 pipe_crc->tail = 0;
d538bbdf
DL		 3693 spin_unlock_irq(&pipe_crc->lock);
3694
3695 kfree(entries);
84093603
DV		 3696
3697 if (IS_G4X(dev))
3698 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3699 else if (IS_VALLEYVIEW(dev))
3700 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3701 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3702 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3703
3704 hsw_enable_ips(crtc);
e5f75aca
DL		 3705 }
3706
926321d5
DV		 3707 return 0;
3708}
3709
3710/*
3711 * Parse pipe CRC command strings:
b94dec87
DL		 3712 * command: wsp* object wsp+ name wsp+ source wsp*
3713 * object: 'pipe'
3714 * name: (A | B | C)
926321d5
DV		 3715 * source: (none | plane1 | plane2 | pf)
3716 * wsp: (#0x20 | #0x9 | #0xA)+
3717 *
3718 * eg.:
b94dec87
DL		 3719 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3720 * "pipe A none" -> Stop CRC
926321d5 3721 */
bd9db02f 3722static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3723{
3724 int n_words = 0;
3725
3726 while (*buf) {
3727 char *end;
3728
3729 /* skip leading white space */
3730 buf = skip_spaces(buf);
3731 if (!*buf)
3732 break; /* end of buffer */
3733
3734 /* find end of word */
3735 for (end = buf; *end && !isspace(*end); end++)
3736 ;
3737
3738 if (n_words == max_words) {
3739 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3740 max_words);
3741 return -EINVAL; /* ran out of words[] before bytes */
3742 }
3743
3744 if (*end)
3745 *end++ = '\0';
3746 words[n_words++] = buf;
3747 buf = end;
3748 }
3749
3750 return n_words;
3751}
3752
b94dec87
DL		 3753enum intel_pipe_crc_object {
3754 PIPE_CRC_OBJECT_PIPE,
3755};
3756
e8dfcf78 3757static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3758 "pipe",
3759};
3760
3761static int
bd9db02f 3762display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3763{
3764 int i;
3765
3766 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3767 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3768 *o = i;
b94dec87
DL		 3769 return 0;
3770 }
3771
3772 return -EINVAL;
3773}
3774
bd9db02f 3775static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3776{
3777 const char name = buf[0];
3778
3779 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3780 return -EINVAL;
3781
3782 *pipe = name - 'A';
3783
3784 return 0;
3785}
3786
3787static int
bd9db02f 3788display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3789{
3790 int i;
3791
3792 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3793 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3794 *s = i;
926321d5
DV		 3795 return 0;
3796 }
3797
3798 return -EINVAL;
3799}
3800
bd9db02f 3801static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3802{
b94dec87 3803#define N_WORDS 3
926321d5 3804 int n_words;
b94dec87 3805 char *words[N_WORDS];
926321d5 3806 enum pipe pipe;
b94dec87 3807 enum intel_pipe_crc_object object;
926321d5
DV		 3808 enum intel_pipe_crc_source source;
3809
bd9db02f 3810 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3811 if (n_words != N_WORDS) {
3812 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3813 N_WORDS);
3814 return -EINVAL;
3815 }
3816
bd9db02f 3817 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3818 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3819 return -EINVAL;
3820 }
3821
bd9db02f 3822 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3823 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3824 return -EINVAL;
3825 }
3826
bd9db02f 3827 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3828 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3829 return -EINVAL;
3830 }
3831
3832 return pipe_crc_set_source(dev, pipe, source);
3833}
3834
bd9db02f
DL		 3835static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3836 size_t len, loff_t *offp)
926321d5
DV		 3837{
3838 struct seq_file *m = file->private_data;
3839 struct drm_device *dev = m->private;
3840 char *tmpbuf;
3841 int ret;
3842
3843 if (len == 0)
3844 return 0;
3845
3846 if (len > PAGE_SIZE - 1) {
3847 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3848 PAGE_SIZE);
3849 return -E2BIG;
3850 }
3851
3852 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3853 if (!tmpbuf)
3854 return -ENOMEM;
3855
3856 if (copy_from_user(tmpbuf, ubuf, len)) {
3857 ret = -EFAULT;
3858 goto out;
3859 }
3860 tmpbuf[len] = '\0';
3861
bd9db02f 3862 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3863
3864out:
3865 kfree(tmpbuf);
3866 if (ret < 0)
3867 return ret;
3868
3869 *offp += len;
3870 return len;
3871}
3872
bd9db02f 3873static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3874 .owner = THIS_MODULE,
bd9db02f 3875 .open = display_crc_ctl_open,
926321d5
DV		 3876 .read = seq_read,
3877 .llseek = seq_lseek,
3878 .release = single_release,
bd9db02f 3879 .write = display_crc_ctl_write
926321d5
DV		 3880};
3881
97e94b22 3882static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3883{
3884 struct drm_device *dev = m->private;
546c81fd 3885 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3886 int level;
3887
3888 drm_modeset_lock_all(dev);
3889
3890 for (level = 0; level < num_levels; level++) {
3891 unsigned int latency = wm[level];
3892
97e94b22
DL		 3893 /*
3894 * - WM1+ latency values in 0.5us units
3895 * - latencies are in us on gen9
3896 */
3897 if (INTEL_INFO(dev)->gen >= 9)
3898 latency *= 10;
3899 else if (level > 0)
369a1342
VS		 3900 latency *= 5;
3901
3902 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3903 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3904 }
3905
3906 drm_modeset_unlock_all(dev);
3907}
3908
3909static int pri_wm_latency_show(struct seq_file *m, void *data)
3910{
3911 struct drm_device *dev = m->private;
97e94b22
DL		 3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913 const uint16_t *latencies;
3914
3915 if (INTEL_INFO(dev)->gen >= 9)
3916 latencies = dev_priv->wm.skl_latency;
3917 else
3918 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3919
97e94b22 3920 wm_latency_show(m, latencies);
369a1342
VS		 3921
3922 return 0;
3923}
3924
3925static int spr_wm_latency_show(struct seq_file *m, void *data)
3926{
3927 struct drm_device *dev = m->private;
97e94b22
DL		 3928 struct drm_i915_private *dev_priv = dev->dev_private;
3929 const uint16_t *latencies;
3930
3931 if (INTEL_INFO(dev)->gen >= 9)
3932 latencies = dev_priv->wm.skl_latency;
3933 else
3934 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3935
97e94b22 3936 wm_latency_show(m, latencies);
369a1342
VS		 3937
3938 return 0;
3939}
3940
3941static int cur_wm_latency_show(struct seq_file *m, void *data)
3942{
3943 struct drm_device *dev = m->private;
97e94b22
DL		 3944 struct drm_i915_private *dev_priv = dev->dev_private;
3945 const uint16_t *latencies;
3946
3947 if (INTEL_INFO(dev)->gen >= 9)
3948 latencies = dev_priv->wm.skl_latency;
3949 else
3950 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3951
97e94b22 3952 wm_latency_show(m, latencies);
369a1342
VS		 3953
3954 return 0;
3955}
3956
3957static int pri_wm_latency_open(struct inode *inode, struct file *file)
3958{
3959 struct drm_device *dev = inode->i_private;
3960
9ad0257c 3961 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3962 return -ENODEV;
3963
3964 return single_open(file, pri_wm_latency_show, dev);
3965}
3966
3967static int spr_wm_latency_open(struct inode *inode, struct file *file)
3968{
3969 struct drm_device *dev = inode->i_private;
3970
9ad0257c 3971 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3972 return -ENODEV;
3973
3974 return single_open(file, spr_wm_latency_show, dev);
3975}
3976
3977static int cur_wm_latency_open(struct inode *inode, struct file *file)
3978{
3979 struct drm_device *dev = inode->i_private;
3980
9ad0257c 3981 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3982 return -ENODEV;
3983
3984 return single_open(file, cur_wm_latency_show, dev);
3985}
3986
3987static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 3988 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 3989{
3990 struct seq_file *m = file->private_data;
3991 struct drm_device *dev = m->private;
97e94b22 3992 uint16_t new[8] = { 0 };
546c81fd 3993 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3994 int level;
3995 int ret;
3996 char tmp[32];
3997
3998 if (len >= sizeof(tmp))
3999 return -EINVAL;
4000
4001 if (copy_from_user(tmp, ubuf, len))
4002 return -EFAULT;
4003
4004 tmp[len] = '\0';
4005
97e94b22
DL		 4006 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4007 &new[0], &new[1], &new[2], &new[3],
4008 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4009 if (ret != num_levels)
4010 return -EINVAL;
4011
4012 drm_modeset_lock_all(dev);
4013
4014 for (level = 0; level < num_levels; level++)
4015 wm[level] = new[level];
4016
4017 drm_modeset_unlock_all(dev);
4018
4019 return len;
4020}
4021
4022
4023static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4024 size_t len, loff_t *offp)
4025{
4026 struct seq_file *m = file->private_data;
4027 struct drm_device *dev = m->private;
97e94b22
DL		 4028 struct drm_i915_private *dev_priv = dev->dev_private;
4029 uint16_t *latencies;
369a1342 4030
97e94b22
DL		 4031 if (INTEL_INFO(dev)->gen >= 9)
4032 latencies = dev_priv->wm.skl_latency;
4033 else
4034 latencies = to_i915(dev)->wm.pri_latency;
4035
4036 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4037}
4038
4039static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4040 size_t len, loff_t *offp)
4041{
4042 struct seq_file *m = file->private_data;
4043 struct drm_device *dev = m->private;
97e94b22
DL		 4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 uint16_t *latencies;
369a1342 4046
97e94b22
DL		 4047 if (INTEL_INFO(dev)->gen >= 9)
4048 latencies = dev_priv->wm.skl_latency;
4049 else
4050 latencies = to_i915(dev)->wm.spr_latency;
4051
4052 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4053}
4054
4055static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4056 size_t len, loff_t *offp)
4057{
4058 struct seq_file *m = file->private_data;
4059 struct drm_device *dev = m->private;
97e94b22
DL		 4060 struct drm_i915_private *dev_priv = dev->dev_private;
4061 uint16_t *latencies;
4062
4063 if (INTEL_INFO(dev)->gen >= 9)
4064 latencies = dev_priv->wm.skl_latency;
4065 else
4066 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4067
97e94b22 4068 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4069}
4070
4071static const struct file_operations i915_pri_wm_latency_fops = {
4072 .owner = THIS_MODULE,
4073 .open = pri_wm_latency_open,
4074 .read = seq_read,
4075 .llseek = seq_lseek,
4076 .release = single_release,
4077 .write = pri_wm_latency_write
4078};
4079
4080static const struct file_operations i915_spr_wm_latency_fops = {
4081 .owner = THIS_MODULE,
4082 .open = spr_wm_latency_open,
4083 .read = seq_read,
4084 .llseek = seq_lseek,
4085 .release = single_release,
4086 .write = spr_wm_latency_write
4087};
4088
4089static const struct file_operations i915_cur_wm_latency_fops = {
4090 .owner = THIS_MODULE,
4091 .open = cur_wm_latency_open,
4092 .read = seq_read,
4093 .llseek = seq_lseek,
4094 .release = single_release,
4095 .write = cur_wm_latency_write
4096};
4097
647416f9
KC		 4098static int
4099i915_wedged_get(void *data, u64 *val)
f3cd474b 4100{
647416f9 4101 struct drm_device *dev = data;
e277a1f8 4102 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4103
647416f9 4104 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4105
647416f9 4106 return 0;
f3cd474b
CW		 4107}
4108
647416f9
KC		 4109static int
4110i915_wedged_set(void *data, u64 val)
f3cd474b 4111{
647416f9 4112 struct drm_device *dev = data;
d46c0517
ID		 4113 struct drm_i915_private *dev_priv = dev->dev_private;
4114
b8d24a06
MK		 4115 /*
4116 * There is no safeguard against this debugfs entry colliding
4117 * with the hangcheck calling same i915_handle_error() in
4118 * parallel, causing an explosion. For now we assume that the
4119 * test harness is responsible enough not to inject gpu hangs
4120 * while it is writing to 'i915_wedged'
4121 */
4122
4123 if (i915_reset_in_progress(&dev_priv->gpu_error))
4124 return -EAGAIN;
4125
d46c0517 4126 intel_runtime_pm_get(dev_priv);
f3cd474b 4127
58174462
MK		 4128 i915_handle_error(dev, val,
4129 "Manually setting wedged to %llu", val);
d46c0517
ID		 4130
4131 intel_runtime_pm_put(dev_priv);
4132
647416f9 4133 return 0;
f3cd474b
CW		 4134}
4135
647416f9
KC		 4136DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4137 i915_wedged_get, i915_wedged_set,
3a3b4f98 4138 "%llu\n");
f3cd474b 4139
647416f9
KC		 4140static int
4141i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4142{
647416f9 4143 struct drm_device *dev = data;
e277a1f8 4144 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4145
647416f9 4146 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4147
647416f9 4148 return 0;
e5eb3d63
DV		 4149}
4150
647416f9
KC		 4151static int
4152i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4153{
647416f9 4154 struct drm_device *dev = data;
e5eb3d63 4155 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4156 int ret;
e5eb3d63 4157
647416f9 4158 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4159
22bcfc6a
DV		 4160 ret = mutex_lock_interruptible(&dev->struct_mutex);
4161 if (ret)
4162 return ret;
4163
99584db3 4164 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4165 mutex_unlock(&dev->struct_mutex);
4166
647416f9 4167 return 0;
e5eb3d63
DV		 4168}
4169
647416f9
KC		 4170DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4171 i915_ring_stop_get, i915_ring_stop_set,
4172 "0x%08llx\n");
d5442303 4173
094f9a54
CW		 4174static int
4175i915_ring_missed_irq_get(void *data, u64 *val)
4176{
4177 struct drm_device *dev = data;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179
4180 *val = dev_priv->gpu_error.missed_irq_rings;
4181 return 0;
4182}
4183
4184static int
4185i915_ring_missed_irq_set(void *data, u64 val)
4186{
4187 struct drm_device *dev = data;
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 int ret;
4190
4191 /* Lock against concurrent debugfs callers */
4192 ret = mutex_lock_interruptible(&dev->struct_mutex);
4193 if (ret)
4194 return ret;
4195 dev_priv->gpu_error.missed_irq_rings = val;
4196 mutex_unlock(&dev->struct_mutex);
4197
4198 return 0;
4199}
4200
4201DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4202 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4203 "0x%08llx\n");
4204
4205static int
4206i915_ring_test_irq_get(void *data, u64 *val)
4207{
4208 struct drm_device *dev = data;
4209 struct drm_i915_private *dev_priv = dev->dev_private;
4210
4211 *val = dev_priv->gpu_error.test_irq_rings;
4212
4213 return 0;
4214}
4215
4216static int
4217i915_ring_test_irq_set(void *data, u64 val)
4218{
4219 struct drm_device *dev = data;
4220 struct drm_i915_private *dev_priv = dev->dev_private;
4221 int ret;
4222
4223 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4224
4225 /* Lock against concurrent debugfs callers */
4226 ret = mutex_lock_interruptible(&dev->struct_mutex);
4227 if (ret)
4228 return ret;
4229
4230 dev_priv->gpu_error.test_irq_rings = val;
4231 mutex_unlock(&dev->struct_mutex);
4232
4233 return 0;
4234}
4235
4236DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4237 i915_ring_test_irq_get, i915_ring_test_irq_set,
4238 "0x%08llx\n");
4239
dd624afd
CW		 4240#define DROP_UNBOUND 0x1
4241#define DROP_BOUND 0x2
4242#define DROP_RETIRE 0x4
4243#define DROP_ACTIVE 0x8
4244#define DROP_ALL (DROP_UNBOUND | \
4245 DROP_BOUND | \
4246 DROP_RETIRE | \
4247 DROP_ACTIVE)
647416f9
KC		 4248static int
4249i915_drop_caches_get(void *data, u64 *val)
dd624afd 4250{
647416f9 4251 *val = DROP_ALL;
dd624afd 4252
647416f9 4253 return 0;
dd624afd
CW		 4254}
4255
647416f9
KC		 4256static int
4257i915_drop_caches_set(void *data, u64 val)
dd624afd 4258{
647416f9 4259 struct drm_device *dev = data;
dd624afd 4260 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4261 int ret;
dd624afd 4262
2f9fe5ff 4263 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4264
4265 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4266 * on ioctls on -EAGAIN. */
4267 ret = mutex_lock_interruptible(&dev->struct_mutex);
4268 if (ret)
4269 return ret;
4270
4271 if (val & DROP_ACTIVE) {
4272 ret = i915_gpu_idle(dev);
4273 if (ret)
4274 goto unlock;
4275 }
4276
4277 if (val & (DROP_RETIRE | DROP_ACTIVE))
4278 i915_gem_retire_requests(dev);
4279
21ab4e74
CW		 4280 if (val & DROP_BOUND)
4281 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4282
21ab4e74
CW		 4283 if (val & DROP_UNBOUND)
4284 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4285
4286unlock:
4287 mutex_unlock(&dev->struct_mutex);
4288
647416f9 4289 return ret;
dd624afd
CW		 4290}
4291
647416f9
KC		 4292DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4293 i915_drop_caches_get, i915_drop_caches_set,
4294 "0x%08llx\n");
dd624afd 4295
647416f9
KC		 4296static int
4297i915_max_freq_get(void *data, u64 *val)
358733e9 4298{
647416f9 4299 struct drm_device *dev = data;
e277a1f8 4300 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4301 int ret;
004777cb 4302
daa3afb2 4303 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4304 return -ENODEV;
4305
5c9669ce
TR		 4306 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4307
4fc688ce 4308 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4309 if (ret)
4310 return ret;
358733e9 4311
7c59a9c1 4312 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4313 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4314
647416f9 4315 return 0;
358733e9
JB		 4316}
4317
647416f9
KC		 4318static int
4319i915_max_freq_set(void *data, u64 val)
358733e9 4320{
647416f9 4321 struct drm_device *dev = data;
358733e9 4322 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4323 u32 hw_max, hw_min;
647416f9 4324 int ret;
004777cb 4325
daa3afb2 4326 if (INTEL_INFO(dev)->gen < 6)
004777cb 4327 return -ENODEV;
358733e9 4328
5c9669ce
TR		 4329 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4330
647416f9 4331 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4332
4fc688ce 4333 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4334 if (ret)
4335 return ret;
4336
358733e9
JB		 4337 /*
4338 * Turbo will still be enabled, but won't go above the set value.
4339 */
bc4d91f6 4340 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4341
bc4d91f6
AG		 4342 hw_max = dev_priv->rps.max_freq;
4343 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4344
b39fb297 4345 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4346 mutex_unlock(&dev_priv->rps.hw_lock);
4347 return -EINVAL;
0a073b84
JB		 4348 }
4349
b39fb297 4350 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4351
ffe02b40 4352 intel_set_rps(dev, val);
dd0a1aa1 4353
4fc688ce 4354 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4355
647416f9 4356 return 0;
358733e9
JB		 4357}
4358
647416f9
KC		 4359DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4360 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4361 "%llu\n");
358733e9 4362
647416f9
KC		 4363static int
4364i915_min_freq_get(void *data, u64 *val)
1523c310 4365{
647416f9 4366 struct drm_device *dev = data;
e277a1f8 4367 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4368 int ret;
004777cb 4369
daa3afb2 4370 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4371 return -ENODEV;
4372
5c9669ce
TR		 4373 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4374
4fc688ce 4375 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4376 if (ret)
4377 return ret;
1523c310 4378
7c59a9c1 4379 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4380 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4381
647416f9 4382 return 0;
1523c310
JB		 4383}
4384
647416f9
KC		 4385static int
4386i915_min_freq_set(void *data, u64 val)
1523c310 4387{
647416f9 4388 struct drm_device *dev = data;
1523c310 4389 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4390 u32 hw_max, hw_min;
647416f9 4391 int ret;
004777cb 4392
daa3afb2 4393 if (INTEL_INFO(dev)->gen < 6)
004777cb 4394 return -ENODEV;
1523c310 4395
5c9669ce
TR		 4396 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4397
647416f9 4398 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4399
4fc688ce 4400 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4401 if (ret)
4402 return ret;
4403
1523c310
JB		 4404 /*
4405 * Turbo will still be enabled, but won't go below the set value.
4406 */
bc4d91f6 4407 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4408
bc4d91f6
AG		 4409 hw_max = dev_priv->rps.max_freq;
4410 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4411
b39fb297 4412 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4413 mutex_unlock(&dev_priv->rps.hw_lock);
4414 return -EINVAL;
0a073b84 4415 }
dd0a1aa1 4416
b39fb297 4417 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4418
ffe02b40 4419 intel_set_rps(dev, val);
dd0a1aa1 4420
4fc688ce 4421 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4422
647416f9 4423 return 0;
1523c310
JB		 4424}
4425
647416f9
KC		 4426DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4427 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4428 "%llu\n");
1523c310 4429
647416f9
KC		 4430static int
4431i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4432{
647416f9 4433 struct drm_device *dev = data;
e277a1f8 4434 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4435 u32 snpcr;
647416f9 4436 int ret;
07b7ddd9 4437
004777cb
DV		 4438 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4439 return -ENODEV;
4440
22bcfc6a
DV		 4441 ret = mutex_lock_interruptible(&dev->struct_mutex);
4442 if (ret)
4443 return ret;
c8c8fb33 4444 intel_runtime_pm_get(dev_priv);
22bcfc6a 4445
07b7ddd9 4446 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4447
4448 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4449 mutex_unlock(&dev_priv->dev->struct_mutex);
4450
647416f9 4451 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4452
647416f9 4453 return 0;
07b7ddd9
JB		 4454}
4455
647416f9
KC		 4456static int
4457i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4458{
647416f9 4459 struct drm_device *dev = data;
07b7ddd9 4460 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4461 u32 snpcr;
07b7ddd9 4462
004777cb
DV		 4463 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4464 return -ENODEV;
4465
647416f9 4466 if (val > 3)
07b7ddd9
JB		 4467 return -EINVAL;
4468
c8c8fb33 4469 intel_runtime_pm_get(dev_priv);
647416f9 4470 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4471
4472 /* Update the cache sharing policy here as well */
4473 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4474 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4475 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4476 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4477
c8c8fb33 4478 intel_runtime_pm_put(dev_priv);
647416f9 4479 return 0;
07b7ddd9
JB		 4480}
4481
647416f9
KC		 4482DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4483 i915_cache_sharing_get, i915_cache_sharing_set,
4484 "%llu\n");
07b7ddd9 4485
3873218f
JM		 4486static int i915_sseu_status(struct seq_file *m, void *unused)
4487{
4488 struct drm_info_node *node = (struct drm_info_node *) m->private;
4489 struct drm_device *dev = node->minor->dev;
7f992aba
JM		 4490 struct drm_i915_private *dev_priv = dev->dev_private;
4491 unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
3873218f 4492
5575f03a 4493 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
3873218f
JM		 4494 return -ENODEV;
4495
4496 seq_puts(m, "SSEU Device Info\n");
4497 seq_printf(m, " Available Slice Total: %u\n",
4498 INTEL_INFO(dev)->slice_total);
4499 seq_printf(m, " Available Subslice Total: %u\n",
4500 INTEL_INFO(dev)->subslice_total);
4501 seq_printf(m, " Available Subslice Per Slice: %u\n",
4502 INTEL_INFO(dev)->subslice_per_slice);
4503 seq_printf(m, " Available EU Total: %u\n",
4504 INTEL_INFO(dev)->eu_total);
4505 seq_printf(m, " Available EU Per Subslice: %u\n",
4506 INTEL_INFO(dev)->eu_per_subslice);
4507 seq_printf(m, " Has Slice Power Gating: %s\n",
4508 yesno(INTEL_INFO(dev)->has_slice_pg));
4509 seq_printf(m, " Has Subslice Power Gating: %s\n",
4510 yesno(INTEL_INFO(dev)->has_subslice_pg));
4511 seq_printf(m, " Has EU Power Gating: %s\n",
4512 yesno(INTEL_INFO(dev)->has_eu_pg));
4513
7f992aba 4514 seq_puts(m, "SSEU Device Status\n");
5575f03a
JM		 4515 if (IS_CHERRYVIEW(dev)) {
4516 const int ss_max = 2;
4517 int ss;
4518 u32 sig1[ss_max], sig2[ss_max];
4519
4520 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4521 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4522 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4523 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4524
4525 for (ss = 0; ss < ss_max; ss++) {
4526 unsigned int eu_cnt;
4527
4528 if (sig1[ss] & CHV_SS_PG_ENABLE)
4529 /* skip disabled subslice */
4530 continue;
4531
4532 s_tot = 1;
4533 ss_per++;
4534 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4535 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4536 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4537 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4538 eu_tot += eu_cnt;
4539 eu_per = max(eu_per, eu_cnt);
4540 }
4541 ss_tot = ss_per;
4542 } else if (IS_SKYLAKE(dev)) {
7f992aba
JM		 4543 const int s_max = 3, ss_max = 4;
4544 int s, ss;
4545 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4546
4547 s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
4548 s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
4549 s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
4550 eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
4551 eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
4552 eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
4553 eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
4554 eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
4555 eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
4556 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4557 GEN9_PGCTL_SSA_EU19_ACK |
4558 GEN9_PGCTL_SSA_EU210_ACK |
4559 GEN9_PGCTL_SSA_EU311_ACK;
4560 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4561 GEN9_PGCTL_SSB_EU19_ACK |
4562 GEN9_PGCTL_SSB_EU210_ACK |
4563 GEN9_PGCTL_SSB_EU311_ACK;
4564
4565 for (s = 0; s < s_max; s++) {
4566 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4567 /* skip disabled slice */
4568 continue;
4569
4570 s_tot++;
4571 ss_per = INTEL_INFO(dev)->subslice_per_slice;
4572 ss_tot += ss_per;
4573 for (ss = 0; ss < ss_max; ss++) {
4574 unsigned int eu_cnt;
4575
4576 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4577 eu_mask[ss%2]);
4578 eu_tot += eu_cnt;
4579 eu_per = max(eu_per, eu_cnt);
4580 }
4581 }
4582 }
4583 seq_printf(m, " Enabled Slice Total: %u\n", s_tot);
4584 seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot);
4585 seq_printf(m, " Enabled Subslice Per Slice: %u\n", ss_per);
4586 seq_printf(m, " Enabled EU Total: %u\n", eu_tot);
4587 seq_printf(m, " Enabled EU Per Subslice: %u\n", eu_per);
4588
3873218f
JM		 4589 return 0;
4590}
4591
6d794d42
BW		 4592static int i915_forcewake_open(struct inode *inode, struct file *file)
4593{
4594 struct drm_device *dev = inode->i_private;
4595 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4596
075edca4 4597 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4598 return 0;
4599
6daccb0b 4600 intel_runtime_pm_get(dev_priv);
59bad947 4601 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4602
4603 return 0;
4604}
4605
c43b5634 4606static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4607{
4608 struct drm_device *dev = inode->i_private;
4609 struct drm_i915_private *dev_priv = dev->dev_private;
4610
075edca4 4611 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4612 return 0;
4613
59bad947 4614 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4615 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4616
4617 return 0;
4618}
4619
4620static const struct file_operations i915_forcewake_fops = {
4621 .owner = THIS_MODULE,
4622 .open = i915_forcewake_open,
4623 .release = i915_forcewake_release,
4624};
4625
4626static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4627{
4628 struct drm_device *dev = minor->dev;
4629 struct dentry *ent;
4630
4631 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4632 S_IRUSR,
6d794d42
BW		 4633 root, dev,
4634 &i915_forcewake_fops);
f3c5fe97
WY		 4635 if (!ent)
4636 return -ENOMEM;
6d794d42 4637
8eb57294 4638 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4639}
4640
6a9c308d
DV		 4641static int i915_debugfs_create(struct dentry *root,
4642 struct drm_minor *minor,
4643 const char *name,
4644 const struct file_operations *fops)
07b7ddd9
JB		 4645{
4646 struct drm_device *dev = minor->dev;
4647 struct dentry *ent;
4648
6a9c308d 4649 ent = debugfs_create_file(name,
07b7ddd9
JB		 4650 S_IRUGO | S_IWUSR,
4651 root, dev,
6a9c308d 4652 fops);
f3c5fe97
WY		 4653 if (!ent)
4654 return -ENOMEM;
07b7ddd9 4655
6a9c308d 4656 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4657}
4658
06c5bf8c 4659static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4660 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4661 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4662 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4663 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4664 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4665 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4666 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4667 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4668 {"i915_gem_request", i915_gem_request_info, 0},
4669 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4670 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4671 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4672 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4673 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4674 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4675 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 4676 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 4677 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 4678 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 4679 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4680 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4681 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4682 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4683 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4684 {"i915_sr_status", i915_sr_status, 0},
44834a67 4685 {"i915_opregion", i915_opregion, 0},
37811fcc 4686 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4687 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4688 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4689 {"i915_execlists", i915_execlists, 0},
f65367b5 4690 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 4691 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4692 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4693 {"i915_llc", i915_llc, 0},
e91fd8c6 4694 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4695 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4696 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4697 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4698 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4699 {"i915_display_info", i915_display_info, 0},
e04934cf 4700 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4701 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4702 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4703 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4704 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 4705 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 4706 {"i915_drrs_status", i915_drrs_status, 0},
2017263e 4707};
27c202ad 4708#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4709
06c5bf8c 4710static const struct i915_debugfs_files {
34b9674c
DV		 4711 const char *name;
4712 const struct file_operations *fops;
4713} i915_debugfs_files[] = {
4714 {"i915_wedged", &i915_wedged_fops},
4715 {"i915_max_freq", &i915_max_freq_fops},
4716 {"i915_min_freq", &i915_min_freq_fops},
4717 {"i915_cache_sharing", &i915_cache_sharing_fops},
4718 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4719 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4720 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4721 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4722 {"i915_error_state", &i915_error_state_fops},
4723 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4724 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4725 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4726 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4727 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4728 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4729};
4730
07144428
DL		 4731void intel_display_crc_init(struct drm_device *dev)
4732{
4733 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4734 enum pipe pipe;
07144428 4735
055e393f 4736 for_each_pipe(dev_priv, pipe) {
b378360e 4737 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4738
d538bbdf
DL		 4739 pipe_crc->opened = false;
4740 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4741 init_waitqueue_head(&pipe_crc->wq);
4742 }
4743}
4744
27c202ad 4745int i915_debugfs_init(struct drm_minor *minor)
2017263e 4746{
34b9674c 4747 int ret, i;
f3cd474b 4748
6d794d42 4749 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4750 if (ret)
4751 return ret;
6a9c308d 4752
07144428
DL		 4753 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4754 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4755 if (ret)
4756 return ret;
4757 }
4758
34b9674c
DV		 4759 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4760 ret = i915_debugfs_create(minor->debugfs_root, minor,
4761 i915_debugfs_files[i].name,
4762 i915_debugfs_files[i].fops);
4763 if (ret)
4764 return ret;
4765 }
40633219 4766
27c202ad
BG		 4767 return drm_debugfs_create_files(i915_debugfs_list,
4768 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4769 minor->debugfs_root, minor);
4770}
4771
27c202ad 4772void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4773{
34b9674c
DV		 4774 int i;
4775
27c202ad
BG		 4776 drm_debugfs_remove_files(i915_debugfs_list,
4777 I915_DEBUGFS_ENTRIES, minor);
07144428 4778
6d794d42
BW		 4779 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4780 1, minor);
07144428 4781
e309a997 4782 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4783 struct drm_info_list *info_list =
4784 (struct drm_info_list *)&i915_pipe_crc_data[i];
4785
4786 drm_debugfs_remove_files(info_list, 1, minor);
4787 }
4788
34b9674c
DV		 4789 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4790 struct drm_info_list *info_list =
4791 (struct drm_info_list *) i915_debugfs_files[i].fops;
4792
4793 drm_debugfs_remove_files(info_list, 1, minor);
4794 }
2017263e 4795}
Linux kernel - Deliverables
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