Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
497666d8 DL |
43 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
44 | * allocated we need to hook into the minor for release. */ | |
45 | static int | |
46 | drm_add_fake_info_node(struct drm_minor *minor, | |
47 | struct dentry *ent, | |
48 | const void *key) | |
49 | { | |
50 | struct drm_info_node *node; | |
51 | ||
52 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
53 | if (node == NULL) { | |
54 | debugfs_remove(ent); | |
55 | return -ENOMEM; | |
56 | } | |
57 | ||
58 | node->minor = minor; | |
59 | node->dent = ent; | |
60 | node->info_ent = (void *) key; | |
61 | ||
62 | mutex_lock(&minor->debugfs_lock); | |
63 | list_add(&node->list, &minor->debugfs_list); | |
64 | mutex_unlock(&minor->debugfs_lock); | |
65 | ||
66 | return 0; | |
67 | } | |
68 | ||
70d39fe4 CW |
69 | static int i915_capabilities(struct seq_file *m, void *data) |
70 | { | |
9f25d007 | 71 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
72 | struct drm_device *dev = node->minor->dev; |
73 | const struct intel_device_info *info = INTEL_INFO(dev); | |
74 | ||
75 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 76 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
77 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
78 | #define SEP_SEMICOLON ; | |
79 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
80 | #undef PRINT_FLAG | |
81 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
82 | |
83 | return 0; | |
84 | } | |
2017263e | 85 | |
a7363de7 | 86 | static char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 87 | { |
573adb39 | 88 | return i915_gem_object_is_active(obj) ? '*' : ' '; |
a6172a80 CW |
89 | } |
90 | ||
a7363de7 | 91 | static char get_pin_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
92 | { |
93 | return obj->pin_display ? 'p' : ' '; | |
94 | } | |
95 | ||
a7363de7 | 96 | static char get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 97 | { |
3e510a8e | 98 | switch (i915_gem_object_get_tiling(obj)) { |
0206e353 | 99 | default: |
be12a86b TU |
100 | case I915_TILING_NONE: return ' '; |
101 | case I915_TILING_X: return 'X'; | |
102 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 103 | } |
a6172a80 CW |
104 | } |
105 | ||
a7363de7 | 106 | static char get_global_flag(struct drm_i915_gem_object *obj) |
be12a86b TU |
107 | { |
108 | return i915_gem_obj_to_ggtt(obj) ? 'g' : ' '; | |
109 | } | |
110 | ||
a7363de7 | 111 | static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) |
1d693bcc | 112 | { |
be12a86b | 113 | return obj->mapping ? 'M' : ' '; |
1d693bcc BW |
114 | } |
115 | ||
ca1543be TU |
116 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
117 | { | |
118 | u64 size = 0; | |
119 | struct i915_vma *vma; | |
120 | ||
1c7f4bca | 121 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3272db53 | 122 | if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
123 | size += vma->node.size; |
124 | } | |
125 | ||
126 | return size; | |
127 | } | |
128 | ||
37811fcc CW |
129 | static void |
130 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
131 | { | |
b4716185 | 132 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 133 | struct intel_engine_cs *engine; |
1d693bcc | 134 | struct i915_vma *vma; |
faf5bf0a | 135 | unsigned int frontbuffer_bits; |
d7f46fc4 | 136 | int pin_count = 0; |
c3232b18 | 137 | enum intel_engine_id id; |
d7f46fc4 | 138 | |
188c1ab7 CW |
139 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
140 | ||
be12a86b | 141 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ", |
37811fcc | 142 | &obj->base, |
be12a86b | 143 | get_active_flag(obj), |
37811fcc CW |
144 | get_pin_flag(obj), |
145 | get_tiling_flag(obj), | |
1d693bcc | 146 | get_global_flag(obj), |
be12a86b | 147 | get_pin_mapped_flag(obj), |
a05a5862 | 148 | obj->base.size / 1024, |
37811fcc | 149 | obj->base.read_domains, |
b4716185 | 150 | obj->base.write_domain); |
c3232b18 | 151 | for_each_engine_id(engine, dev_priv, id) |
b4716185 | 152 | seq_printf(m, "%x ", |
d72d908b CW |
153 | i915_gem_active_get_seqno(&obj->last_read[id], |
154 | &obj->base.dev->struct_mutex)); | |
b4716185 | 155 | seq_printf(m, "] %x %x%s%s%s", |
d72d908b CW |
156 | i915_gem_active_get_seqno(&obj->last_write, |
157 | &obj->base.dev->struct_mutex), | |
158 | i915_gem_active_get_seqno(&obj->last_fence, | |
159 | &obj->base.dev->struct_mutex), | |
0a4cd7c8 | 160 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
37811fcc CW |
161 | obj->dirty ? " dirty" : "", |
162 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
163 | if (obj->base.name) | |
164 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 165 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
20dfbde4 | 166 | if (i915_vma_is_pinned(vma)) |
d7f46fc4 | 167 | pin_count++; |
ba0635ff DC |
168 | } |
169 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
170 | if (obj->pin_display) |
171 | seq_printf(m, " (display)"); | |
37811fcc CW |
172 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
173 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1c7f4bca | 174 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
15717de2 CW |
175 | if (!drm_mm_node_allocated(&vma->node)) |
176 | continue; | |
177 | ||
8d2fdc3f | 178 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
3272db53 | 179 | i915_vma_is_ggtt(vma) ? "g" : "pp", |
8d2fdc3f | 180 | vma->node.start, vma->node.size); |
3272db53 | 181 | if (i915_vma_is_ggtt(vma)) |
596c5923 CW |
182 | seq_printf(m, ", type: %u", vma->ggtt_view.type); |
183 | seq_puts(m, ")"); | |
1d693bcc | 184 | } |
c1ad11fc | 185 | if (obj->stolen) |
440fd528 | 186 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
30154650 | 187 | if (obj->pin_display || obj->fault_mappable) { |
6299f992 | 188 | char s[3], *t = s; |
30154650 | 189 | if (obj->pin_display) |
6299f992 CW |
190 | *t++ = 'p'; |
191 | if (obj->fault_mappable) | |
192 | *t++ = 'f'; | |
193 | *t = '\0'; | |
194 | seq_printf(m, " (%s mappable)", s); | |
195 | } | |
27c01aae | 196 | |
d72d908b CW |
197 | engine = i915_gem_active_get_engine(&obj->last_write, |
198 | &obj->base.dev->struct_mutex); | |
27c01aae CW |
199 | if (engine) |
200 | seq_printf(m, " (%s)", engine->name); | |
201 | ||
faf5bf0a CW |
202 | frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); |
203 | if (frontbuffer_bits) | |
204 | seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); | |
37811fcc CW |
205 | } |
206 | ||
6d2b8885 CW |
207 | static int obj_rank_by_stolen(void *priv, |
208 | struct list_head *A, struct list_head *B) | |
209 | { | |
210 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 211 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 212 | struct drm_i915_gem_object *b = |
b25cb2f8 | 213 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 214 | |
2d05fa16 RV |
215 | if (a->stolen->start < b->stolen->start) |
216 | return -1; | |
217 | if (a->stolen->start > b->stolen->start) | |
218 | return 1; | |
219 | return 0; | |
6d2b8885 CW |
220 | } |
221 | ||
222 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
223 | { | |
9f25d007 | 224 | struct drm_info_node *node = m->private; |
6d2b8885 | 225 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 226 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d2b8885 | 227 | struct drm_i915_gem_object *obj; |
c44ef60e | 228 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
229 | LIST_HEAD(stolen); |
230 | int count, ret; | |
231 | ||
232 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
233 | if (ret) | |
234 | return ret; | |
235 | ||
236 | total_obj_size = total_gtt_size = count = 0; | |
237 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
238 | if (obj->stolen == NULL) | |
239 | continue; | |
240 | ||
b25cb2f8 | 241 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
242 | |
243 | total_obj_size += obj->base.size; | |
ca1543be | 244 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
245 | count++; |
246 | } | |
247 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
248 | if (obj->stolen == NULL) | |
249 | continue; | |
250 | ||
b25cb2f8 | 251 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
252 | |
253 | total_obj_size += obj->base.size; | |
254 | count++; | |
255 | } | |
256 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
257 | seq_puts(m, "Stolen:\n"); | |
258 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 259 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
260 | seq_puts(m, " "); |
261 | describe_obj(m, obj); | |
262 | seq_putc(m, '\n'); | |
b25cb2f8 | 263 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
264 | } |
265 | mutex_unlock(&dev->struct_mutex); | |
266 | ||
c44ef60e | 267 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
268 | count, total_obj_size, total_gtt_size); |
269 | return 0; | |
270 | } | |
271 | ||
2db8e9d6 | 272 | struct file_stats { |
6313c204 | 273 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
274 | unsigned long count; |
275 | u64 total, unbound; | |
276 | u64 global, shared; | |
277 | u64 active, inactive; | |
2db8e9d6 CW |
278 | }; |
279 | ||
280 | static int per_file_stats(int id, void *ptr, void *data) | |
281 | { | |
282 | struct drm_i915_gem_object *obj = ptr; | |
283 | struct file_stats *stats = data; | |
6313c204 | 284 | struct i915_vma *vma; |
2db8e9d6 CW |
285 | |
286 | stats->count++; | |
287 | stats->total += obj->base.size; | |
15717de2 CW |
288 | if (!obj->bind_count) |
289 | stats->unbound += obj->base.size; | |
c67a17e9 CW |
290 | if (obj->base.name || obj->base.dma_buf) |
291 | stats->shared += obj->base.size; | |
292 | ||
894eeecc CW |
293 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
294 | if (!drm_mm_node_allocated(&vma->node)) | |
295 | continue; | |
6313c204 | 296 | |
3272db53 | 297 | if (i915_vma_is_ggtt(vma)) { |
894eeecc CW |
298 | stats->global += vma->node.size; |
299 | } else { | |
300 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); | |
6313c204 | 301 | |
2bfa996e | 302 | if (ppgtt->base.file != stats->file_priv) |
6313c204 | 303 | continue; |
6313c204 | 304 | } |
894eeecc | 305 | |
b0decaf7 | 306 | if (i915_vma_is_active(vma)) |
894eeecc CW |
307 | stats->active += vma->node.size; |
308 | else | |
309 | stats->inactive += vma->node.size; | |
2db8e9d6 CW |
310 | } |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
b0da1b79 CW |
315 | #define print_file_stats(m, name, stats) do { \ |
316 | if (stats.count) \ | |
c44ef60e | 317 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
318 | name, \ |
319 | stats.count, \ | |
320 | stats.total, \ | |
321 | stats.active, \ | |
322 | stats.inactive, \ | |
323 | stats.global, \ | |
324 | stats.shared, \ | |
325 | stats.unbound); \ | |
326 | } while (0) | |
493018dc BV |
327 | |
328 | static void print_batch_pool_stats(struct seq_file *m, | |
329 | struct drm_i915_private *dev_priv) | |
330 | { | |
331 | struct drm_i915_gem_object *obj; | |
332 | struct file_stats stats; | |
e2f80391 | 333 | struct intel_engine_cs *engine; |
b4ac5afc | 334 | int j; |
493018dc BV |
335 | |
336 | memset(&stats, 0, sizeof(stats)); | |
337 | ||
b4ac5afc | 338 | for_each_engine(engine, dev_priv) { |
e2f80391 | 339 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 340 | list_for_each_entry(obj, |
e2f80391 | 341 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
342 | batch_pool_link) |
343 | per_file_stats(0, obj, &stats); | |
344 | } | |
06fbca71 | 345 | } |
493018dc | 346 | |
b0da1b79 | 347 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
348 | } |
349 | ||
15da9565 CW |
350 | static int per_file_ctx_stats(int id, void *ptr, void *data) |
351 | { | |
352 | struct i915_gem_context *ctx = ptr; | |
353 | int n; | |
354 | ||
355 | for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { | |
356 | if (ctx->engine[n].state) | |
bf3783e5 | 357 | per_file_stats(0, ctx->engine[n].state->obj, data); |
dca33ecc | 358 | if (ctx->engine[n].ring) |
57e88531 | 359 | per_file_stats(0, ctx->engine[n].ring->vma->obj, data); |
15da9565 CW |
360 | } |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
365 | static void print_context_stats(struct seq_file *m, | |
366 | struct drm_i915_private *dev_priv) | |
367 | { | |
368 | struct file_stats stats; | |
369 | struct drm_file *file; | |
370 | ||
371 | memset(&stats, 0, sizeof(stats)); | |
372 | ||
91c8a326 | 373 | mutex_lock(&dev_priv->drm.struct_mutex); |
15da9565 CW |
374 | if (dev_priv->kernel_context) |
375 | per_file_ctx_stats(0, dev_priv->kernel_context, &stats); | |
376 | ||
91c8a326 | 377 | list_for_each_entry(file, &dev_priv->drm.filelist, lhead) { |
15da9565 CW |
378 | struct drm_i915_file_private *fpriv = file->driver_priv; |
379 | idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); | |
380 | } | |
91c8a326 | 381 | mutex_unlock(&dev_priv->drm.struct_mutex); |
15da9565 CW |
382 | |
383 | print_file_stats(m, "[k]contexts", stats); | |
384 | } | |
385 | ||
ca191b13 | 386 | static int i915_gem_object_info(struct seq_file *m, void* data) |
73aa808f | 387 | { |
9f25d007 | 388 | struct drm_info_node *node = m->private; |
73aa808f | 389 | struct drm_device *dev = node->minor->dev; |
72e96d64 JL |
390 | struct drm_i915_private *dev_priv = to_i915(dev); |
391 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
2bd160a1 CW |
392 | u32 count, mapped_count, purgeable_count, dpy_count; |
393 | u64 size, mapped_size, purgeable_size, dpy_size; | |
6299f992 | 394 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 395 | struct drm_file *file; |
73aa808f CW |
396 | int ret; |
397 | ||
398 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
399 | if (ret) | |
400 | return ret; | |
401 | ||
6299f992 CW |
402 | seq_printf(m, "%u objects, %zu bytes\n", |
403 | dev_priv->mm.object_count, | |
404 | dev_priv->mm.object_memory); | |
405 | ||
b7abb714 | 406 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 407 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
2bd160a1 CW |
408 | size += obj->base.size; |
409 | ++count; | |
410 | ||
411 | if (obj->madv == I915_MADV_DONTNEED) { | |
412 | purgeable_size += obj->base.size; | |
413 | ++purgeable_count; | |
414 | } | |
415 | ||
be19b10d | 416 | if (obj->mapping) { |
2bd160a1 CW |
417 | mapped_count++; |
418 | mapped_size += obj->base.size; | |
be19b10d | 419 | } |
b7abb714 | 420 | } |
c44ef60e | 421 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 422 | |
2bd160a1 | 423 | size = count = dpy_size = dpy_count = 0; |
35c20a60 | 424 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2bd160a1 CW |
425 | size += obj->base.size; |
426 | ++count; | |
427 | ||
30154650 | 428 | if (obj->pin_display) { |
2bd160a1 CW |
429 | dpy_size += obj->base.size; |
430 | ++dpy_count; | |
6299f992 | 431 | } |
2bd160a1 | 432 | |
b7abb714 CW |
433 | if (obj->madv == I915_MADV_DONTNEED) { |
434 | purgeable_size += obj->base.size; | |
435 | ++purgeable_count; | |
436 | } | |
2bd160a1 | 437 | |
be19b10d | 438 | if (obj->mapping) { |
2bd160a1 CW |
439 | mapped_count++; |
440 | mapped_size += obj->base.size; | |
be19b10d | 441 | } |
6299f992 | 442 | } |
2bd160a1 CW |
443 | seq_printf(m, "%u bound objects, %llu bytes\n", |
444 | count, size); | |
c44ef60e | 445 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 446 | purgeable_count, purgeable_size); |
2bd160a1 CW |
447 | seq_printf(m, "%u mapped objects, %llu bytes\n", |
448 | mapped_count, mapped_size); | |
449 | seq_printf(m, "%u display objects (pinned), %llu bytes\n", | |
450 | dpy_count, dpy_size); | |
6299f992 | 451 | |
c44ef60e | 452 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 453 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 454 | |
493018dc BV |
455 | seq_putc(m, '\n'); |
456 | print_batch_pool_stats(m, dev_priv); | |
1d2ac403 DV |
457 | mutex_unlock(&dev->struct_mutex); |
458 | ||
459 | mutex_lock(&dev->filelist_mutex); | |
15da9565 | 460 | print_context_stats(m, dev_priv); |
2db8e9d6 CW |
461 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
462 | struct file_stats stats; | |
3ec2f427 | 463 | struct task_struct *task; |
2db8e9d6 CW |
464 | |
465 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 466 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 467 | spin_lock(&file->table_lock); |
2db8e9d6 | 468 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 469 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
470 | /* |
471 | * Although we have a valid reference on file->pid, that does | |
472 | * not guarantee that the task_struct who called get_pid() is | |
473 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
474 | * Therefore, we need to protect this ->comm access using RCU. | |
475 | */ | |
476 | rcu_read_lock(); | |
477 | task = pid_task(file->pid, PIDTYPE_PID); | |
493018dc | 478 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 479 | rcu_read_unlock(); |
2db8e9d6 | 480 | } |
1d2ac403 | 481 | mutex_unlock(&dev->filelist_mutex); |
73aa808f CW |
482 | |
483 | return 0; | |
484 | } | |
485 | ||
aee56cff | 486 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 487 | { |
9f25d007 | 488 | struct drm_info_node *node = m->private; |
08c18323 | 489 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 490 | struct drm_i915_private *dev_priv = to_i915(dev); |
6da84829 | 491 | bool show_pin_display_only = !!data; |
08c18323 | 492 | struct drm_i915_gem_object *obj; |
c44ef60e | 493 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
494 | int count, ret; |
495 | ||
496 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
497 | if (ret) | |
498 | return ret; | |
499 | ||
500 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 501 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6da84829 | 502 | if (show_pin_display_only && !obj->pin_display) |
1b50247a CW |
503 | continue; |
504 | ||
267f0c90 | 505 | seq_puts(m, " "); |
08c18323 | 506 | describe_obj(m, obj); |
267f0c90 | 507 | seq_putc(m, '\n'); |
08c18323 | 508 | total_obj_size += obj->base.size; |
ca1543be | 509 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
510 | count++; |
511 | } | |
512 | ||
513 | mutex_unlock(&dev->struct_mutex); | |
514 | ||
c44ef60e | 515 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
516 | count, total_obj_size, total_gtt_size); |
517 | ||
518 | return 0; | |
519 | } | |
520 | ||
4e5359cd SF |
521 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
522 | { | |
9f25d007 | 523 | struct drm_info_node *node = m->private; |
4e5359cd | 524 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 525 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e5359cd | 526 | struct intel_crtc *crtc; |
8a270ebf DV |
527 | int ret; |
528 | ||
529 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
530 | if (ret) | |
531 | return ret; | |
4e5359cd | 532 | |
d3fcc808 | 533 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
534 | const char pipe = pipe_name(crtc->pipe); |
535 | const char plane = plane_name(crtc->plane); | |
51cbaf01 | 536 | struct intel_flip_work *work; |
4e5359cd | 537 | |
5e2d7afc | 538 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
539 | work = crtc->flip_work; |
540 | if (work == NULL) { | |
9db4a9c7 | 541 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
542 | pipe, plane); |
543 | } else { | |
5a21b665 DV |
544 | u32 pending; |
545 | u32 addr; | |
546 | ||
547 | pending = atomic_read(&work->pending); | |
548 | if (pending) { | |
549 | seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", | |
550 | pipe, plane); | |
551 | } else { | |
552 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", | |
553 | pipe, plane); | |
554 | } | |
555 | if (work->flip_queued_req) { | |
556 | struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req); | |
557 | ||
558 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", | |
559 | engine->name, | |
560 | i915_gem_request_get_seqno(work->flip_queued_req), | |
561 | dev_priv->next_seqno, | |
1b7744e7 | 562 | intel_engine_get_seqno(engine), |
f69a02c9 | 563 | i915_gem_request_completed(work->flip_queued_req)); |
5a21b665 DV |
564 | } else |
565 | seq_printf(m, "Flip not associated with any ring\n"); | |
566 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
567 | work->flip_queued_vblank, | |
568 | work->flip_ready_vblank, | |
569 | intel_crtc_get_vblank_counter(crtc)); | |
570 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); | |
571 | ||
572 | if (INTEL_INFO(dev)->gen >= 4) | |
573 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); | |
574 | else | |
575 | addr = I915_READ(DSPADDR(crtc->plane)); | |
576 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
577 | ||
578 | if (work->pending_flip_obj) { | |
579 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); | |
580 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
581 | } |
582 | } | |
5e2d7afc | 583 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
584 | } |
585 | ||
8a270ebf DV |
586 | mutex_unlock(&dev->struct_mutex); |
587 | ||
4e5359cd SF |
588 | return 0; |
589 | } | |
590 | ||
493018dc BV |
591 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
592 | { | |
593 | struct drm_info_node *node = m->private; | |
594 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 595 | struct drm_i915_private *dev_priv = to_i915(dev); |
493018dc | 596 | struct drm_i915_gem_object *obj; |
e2f80391 | 597 | struct intel_engine_cs *engine; |
8d9d5744 | 598 | int total = 0; |
b4ac5afc | 599 | int ret, j; |
493018dc BV |
600 | |
601 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
602 | if (ret) | |
603 | return ret; | |
604 | ||
b4ac5afc | 605 | for_each_engine(engine, dev_priv) { |
e2f80391 | 606 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
607 | int count; |
608 | ||
609 | count = 0; | |
610 | list_for_each_entry(obj, | |
e2f80391 | 611 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
612 | batch_pool_link) |
613 | count++; | |
614 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 615 | engine->name, j, count); |
8d9d5744 CW |
616 | |
617 | list_for_each_entry(obj, | |
e2f80391 | 618 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
619 | batch_pool_link) { |
620 | seq_puts(m, " "); | |
621 | describe_obj(m, obj); | |
622 | seq_putc(m, '\n'); | |
623 | } | |
624 | ||
625 | total += count; | |
06fbca71 | 626 | } |
493018dc BV |
627 | } |
628 | ||
8d9d5744 | 629 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
630 | |
631 | mutex_unlock(&dev->struct_mutex); | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
2017263e BG |
636 | static int i915_gem_request_info(struct seq_file *m, void *data) |
637 | { | |
9f25d007 | 638 | struct drm_info_node *node = m->private; |
2017263e | 639 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 640 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 641 | struct intel_engine_cs *engine; |
eed29a5b | 642 | struct drm_i915_gem_request *req; |
b4ac5afc | 643 | int ret, any; |
de227ef0 CW |
644 | |
645 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
646 | if (ret) | |
647 | return ret; | |
2017263e | 648 | |
2d1070b2 | 649 | any = 0; |
b4ac5afc | 650 | for_each_engine(engine, dev_priv) { |
2d1070b2 CW |
651 | int count; |
652 | ||
653 | count = 0; | |
efdf7c06 | 654 | list_for_each_entry(req, &engine->request_list, link) |
2d1070b2 CW |
655 | count++; |
656 | if (count == 0) | |
a2c7f6fd CW |
657 | continue; |
658 | ||
e2f80391 | 659 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
efdf7c06 | 660 | list_for_each_entry(req, &engine->request_list, link) { |
2d1070b2 CW |
661 | struct task_struct *task; |
662 | ||
663 | rcu_read_lock(); | |
664 | task = NULL; | |
eed29a5b DV |
665 | if (req->pid) |
666 | task = pid_task(req->pid, PIDTYPE_PID); | |
2d1070b2 | 667 | seq_printf(m, " %x @ %d: %s [%d]\n", |
04769652 | 668 | req->fence.seqno, |
eed29a5b | 669 | (int) (jiffies - req->emitted_jiffies), |
2d1070b2 CW |
670 | task ? task->comm : "<unknown>", |
671 | task ? task->pid : -1); | |
672 | rcu_read_unlock(); | |
c2c347a9 | 673 | } |
2d1070b2 CW |
674 | |
675 | any++; | |
2017263e | 676 | } |
de227ef0 CW |
677 | mutex_unlock(&dev->struct_mutex); |
678 | ||
2d1070b2 | 679 | if (any == 0) |
267f0c90 | 680 | seq_puts(m, "No requests\n"); |
c2c347a9 | 681 | |
2017263e BG |
682 | return 0; |
683 | } | |
684 | ||
b2223497 | 685 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 686 | struct intel_engine_cs *engine) |
b2223497 | 687 | { |
688e6c72 CW |
688 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
689 | struct rb_node *rb; | |
690 | ||
12471ba8 | 691 | seq_printf(m, "Current sequence (%s): %x\n", |
1b7744e7 | 692 | engine->name, intel_engine_get_seqno(engine)); |
688e6c72 CW |
693 | |
694 | spin_lock(&b->lock); | |
695 | for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { | |
696 | struct intel_wait *w = container_of(rb, typeof(*w), node); | |
697 | ||
698 | seq_printf(m, "Waiting (%s): %s [%d] on %x\n", | |
699 | engine->name, w->tsk->comm, w->tsk->pid, w->seqno); | |
700 | } | |
701 | spin_unlock(&b->lock); | |
b2223497 CW |
702 | } |
703 | ||
2017263e BG |
704 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
705 | { | |
9f25d007 | 706 | struct drm_info_node *node = m->private; |
2017263e | 707 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 708 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 709 | struct intel_engine_cs *engine; |
b4ac5afc | 710 | int ret; |
de227ef0 CW |
711 | |
712 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
713 | if (ret) | |
714 | return ret; | |
c8c8fb33 | 715 | intel_runtime_pm_get(dev_priv); |
2017263e | 716 | |
b4ac5afc | 717 | for_each_engine(engine, dev_priv) |
e2f80391 | 718 | i915_ring_seqno_info(m, engine); |
de227ef0 | 719 | |
c8c8fb33 | 720 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
721 | mutex_unlock(&dev->struct_mutex); |
722 | ||
2017263e BG |
723 | return 0; |
724 | } | |
725 | ||
726 | ||
727 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
728 | { | |
9f25d007 | 729 | struct drm_info_node *node = m->private; |
2017263e | 730 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 731 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 732 | struct intel_engine_cs *engine; |
9db4a9c7 | 733 | int ret, i, pipe; |
de227ef0 CW |
734 | |
735 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
736 | if (ret) | |
737 | return ret; | |
c8c8fb33 | 738 | intel_runtime_pm_get(dev_priv); |
2017263e | 739 | |
74e1ca8c | 740 | if (IS_CHERRYVIEW(dev)) { |
74e1ca8c VS |
741 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
742 | I915_READ(GEN8_MASTER_IRQ)); | |
743 | ||
744 | seq_printf(m, "Display IER:\t%08x\n", | |
745 | I915_READ(VLV_IER)); | |
746 | seq_printf(m, "Display IIR:\t%08x\n", | |
747 | I915_READ(VLV_IIR)); | |
748 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
749 | I915_READ(VLV_IIR_RW)); | |
750 | seq_printf(m, "Display IMR:\t%08x\n", | |
751 | I915_READ(VLV_IMR)); | |
055e393f | 752 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
753 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
754 | pipe_name(pipe), | |
755 | I915_READ(PIPESTAT(pipe))); | |
756 | ||
757 | seq_printf(m, "Port hotplug:\t%08x\n", | |
758 | I915_READ(PORT_HOTPLUG_EN)); | |
759 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
760 | I915_READ(VLV_DPFLIPSTAT)); | |
761 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
762 | I915_READ(DPINVGTT)); | |
763 | ||
764 | for (i = 0; i < 4; i++) { | |
765 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
766 | i, I915_READ(GEN8_GT_IMR(i))); | |
767 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
768 | i, I915_READ(GEN8_GT_IIR(i))); | |
769 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
770 | i, I915_READ(GEN8_GT_IER(i))); | |
771 | } | |
772 | ||
773 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
774 | I915_READ(GEN8_PCU_IMR)); | |
775 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
776 | I915_READ(GEN8_PCU_IIR)); | |
777 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
778 | I915_READ(GEN8_PCU_IER)); | |
779 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
780 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
781 | I915_READ(GEN8_MASTER_IRQ)); | |
782 | ||
783 | for (i = 0; i < 4; i++) { | |
784 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
785 | i, I915_READ(GEN8_GT_IMR(i))); | |
786 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
787 | i, I915_READ(GEN8_GT_IIR(i))); | |
788 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
789 | i, I915_READ(GEN8_GT_IER(i))); | |
790 | } | |
791 | ||
055e393f | 792 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
793 | enum intel_display_power_domain power_domain; |
794 | ||
795 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
796 | if (!intel_display_power_get_if_enabled(dev_priv, | |
797 | power_domain)) { | |
22c59960 PZ |
798 | seq_printf(m, "Pipe %c power disabled\n", |
799 | pipe_name(pipe)); | |
800 | continue; | |
801 | } | |
a123f157 | 802 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
803 | pipe_name(pipe), |
804 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 805 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
806 | pipe_name(pipe), |
807 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 808 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
809 | pipe_name(pipe), |
810 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
811 | |
812 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
813 | } |
814 | ||
815 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
816 | I915_READ(GEN8_DE_PORT_IMR)); | |
817 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
818 | I915_READ(GEN8_DE_PORT_IIR)); | |
819 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
820 | I915_READ(GEN8_DE_PORT_IER)); | |
821 | ||
822 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
823 | I915_READ(GEN8_DE_MISC_IMR)); | |
824 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
825 | I915_READ(GEN8_DE_MISC_IIR)); | |
826 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
827 | I915_READ(GEN8_DE_MISC_IER)); | |
828 | ||
829 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
830 | I915_READ(GEN8_PCU_IMR)); | |
831 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
832 | I915_READ(GEN8_PCU_IIR)); | |
833 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
834 | I915_READ(GEN8_PCU_IER)); | |
835 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
836 | seq_printf(m, "Display IER:\t%08x\n", |
837 | I915_READ(VLV_IER)); | |
838 | seq_printf(m, "Display IIR:\t%08x\n", | |
839 | I915_READ(VLV_IIR)); | |
840 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
841 | I915_READ(VLV_IIR_RW)); | |
842 | seq_printf(m, "Display IMR:\t%08x\n", | |
843 | I915_READ(VLV_IMR)); | |
055e393f | 844 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
845 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
846 | pipe_name(pipe), | |
847 | I915_READ(PIPESTAT(pipe))); | |
848 | ||
849 | seq_printf(m, "Master IER:\t%08x\n", | |
850 | I915_READ(VLV_MASTER_IER)); | |
851 | ||
852 | seq_printf(m, "Render IER:\t%08x\n", | |
853 | I915_READ(GTIER)); | |
854 | seq_printf(m, "Render IIR:\t%08x\n", | |
855 | I915_READ(GTIIR)); | |
856 | seq_printf(m, "Render IMR:\t%08x\n", | |
857 | I915_READ(GTIMR)); | |
858 | ||
859 | seq_printf(m, "PM IER:\t\t%08x\n", | |
860 | I915_READ(GEN6_PMIER)); | |
861 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
862 | I915_READ(GEN6_PMIIR)); | |
863 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
864 | I915_READ(GEN6_PMIMR)); | |
865 | ||
866 | seq_printf(m, "Port hotplug:\t%08x\n", | |
867 | I915_READ(PORT_HOTPLUG_EN)); | |
868 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
869 | I915_READ(VLV_DPFLIPSTAT)); | |
870 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
871 | I915_READ(DPINVGTT)); | |
872 | ||
873 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
874 | seq_printf(m, "Interrupt enable: %08x\n", |
875 | I915_READ(IER)); | |
876 | seq_printf(m, "Interrupt identity: %08x\n", | |
877 | I915_READ(IIR)); | |
878 | seq_printf(m, "Interrupt mask: %08x\n", | |
879 | I915_READ(IMR)); | |
055e393f | 880 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
881 | seq_printf(m, "Pipe %c stat: %08x\n", |
882 | pipe_name(pipe), | |
883 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
884 | } else { |
885 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
886 | I915_READ(DEIER)); | |
887 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
888 | I915_READ(DEIIR)); | |
889 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
890 | I915_READ(DEIMR)); | |
891 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
892 | I915_READ(SDEIER)); | |
893 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
894 | I915_READ(SDEIIR)); | |
895 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
896 | I915_READ(SDEIMR)); | |
897 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
898 | I915_READ(GTIER)); | |
899 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
900 | I915_READ(GTIIR)); | |
901 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
902 | I915_READ(GTIMR)); | |
903 | } | |
b4ac5afc | 904 | for_each_engine(engine, dev_priv) { |
a123f157 | 905 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
906 | seq_printf(m, |
907 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 908 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 909 | } |
e2f80391 | 910 | i915_ring_seqno_info(m, engine); |
9862e600 | 911 | } |
c8c8fb33 | 912 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
913 | mutex_unlock(&dev->struct_mutex); |
914 | ||
2017263e BG |
915 | return 0; |
916 | } | |
917 | ||
a6172a80 CW |
918 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
919 | { | |
9f25d007 | 920 | struct drm_info_node *node = m->private; |
a6172a80 | 921 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 922 | struct drm_i915_private *dev_priv = to_i915(dev); |
de227ef0 CW |
923 | int i, ret; |
924 | ||
925 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
926 | if (ret) | |
927 | return ret; | |
a6172a80 | 928 | |
a6172a80 CW |
929 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
930 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 931 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 932 | |
6c085a72 CW |
933 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
934 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 935 | if (obj == NULL) |
267f0c90 | 936 | seq_puts(m, "unused"); |
c2c347a9 | 937 | else |
05394f39 | 938 | describe_obj(m, obj); |
267f0c90 | 939 | seq_putc(m, '\n'); |
a6172a80 CW |
940 | } |
941 | ||
05394f39 | 942 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
943 | return 0; |
944 | } | |
945 | ||
2017263e BG |
946 | static int i915_hws_info(struct seq_file *m, void *data) |
947 | { | |
9f25d007 | 948 | struct drm_info_node *node = m->private; |
2017263e | 949 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 950 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 951 | struct intel_engine_cs *engine; |
1a240d4d | 952 | const u32 *hws; |
4066c0ae CW |
953 | int i; |
954 | ||
4a570db5 | 955 | engine = &dev_priv->engine[(uintptr_t)node->info_ent->data]; |
e2f80391 | 956 | hws = engine->status_page.page_addr; |
2017263e BG |
957 | if (hws == NULL) |
958 | return 0; | |
959 | ||
960 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
961 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
962 | i * 4, | |
963 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
964 | } | |
965 | return 0; | |
966 | } | |
967 | ||
d5442303 DV |
968 | static ssize_t |
969 | i915_error_state_write(struct file *filp, | |
970 | const char __user *ubuf, | |
971 | size_t cnt, | |
972 | loff_t *ppos) | |
973 | { | |
edc3d884 | 974 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 975 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 976 | int ret; |
d5442303 DV |
977 | |
978 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
979 | ||
22bcfc6a DV |
980 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
981 | if (ret) | |
982 | return ret; | |
983 | ||
d5442303 DV |
984 | i915_destroy_error_state(dev); |
985 | mutex_unlock(&dev->struct_mutex); | |
986 | ||
987 | return cnt; | |
988 | } | |
989 | ||
990 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
991 | { | |
992 | struct drm_device *dev = inode->i_private; | |
d5442303 | 993 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
994 | |
995 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
996 | if (!error_priv) | |
997 | return -ENOMEM; | |
998 | ||
999 | error_priv->dev = dev; | |
1000 | ||
95d5bfb3 | 1001 | i915_error_state_get(dev, error_priv); |
d5442303 | 1002 | |
edc3d884 MK |
1003 | file->private_data = error_priv; |
1004 | ||
1005 | return 0; | |
d5442303 DV |
1006 | } |
1007 | ||
1008 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
1009 | { | |
edc3d884 | 1010 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 1011 | |
95d5bfb3 | 1012 | i915_error_state_put(error_priv); |
d5442303 DV |
1013 | kfree(error_priv); |
1014 | ||
edc3d884 MK |
1015 | return 0; |
1016 | } | |
1017 | ||
4dc955f7 MK |
1018 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1019 | size_t count, loff_t *pos) | |
1020 | { | |
1021 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1022 | struct drm_i915_error_state_buf error_str; | |
1023 | loff_t tmp_pos = 0; | |
1024 | ssize_t ret_count = 0; | |
1025 | int ret; | |
1026 | ||
0a4cd7c8 | 1027 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
4dc955f7 MK |
1028 | if (ret) |
1029 | return ret; | |
edc3d884 | 1030 | |
fc16b48b | 1031 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1032 | if (ret) |
1033 | goto out; | |
1034 | ||
edc3d884 MK |
1035 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1036 | error_str.buf, | |
1037 | error_str.bytes); | |
1038 | ||
1039 | if (ret_count < 0) | |
1040 | ret = ret_count; | |
1041 | else | |
1042 | *pos = error_str.start + ret_count; | |
1043 | out: | |
4dc955f7 | 1044 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1045 | return ret ?: ret_count; |
d5442303 DV |
1046 | } |
1047 | ||
1048 | static const struct file_operations i915_error_state_fops = { | |
1049 | .owner = THIS_MODULE, | |
1050 | .open = i915_error_state_open, | |
edc3d884 | 1051 | .read = i915_error_state_read, |
d5442303 DV |
1052 | .write = i915_error_state_write, |
1053 | .llseek = default_llseek, | |
1054 | .release = i915_error_state_release, | |
1055 | }; | |
1056 | ||
647416f9 KC |
1057 | static int |
1058 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1059 | { |
647416f9 | 1060 | struct drm_device *dev = data; |
fac5e23e | 1061 | struct drm_i915_private *dev_priv = to_i915(dev); |
40633219 MK |
1062 | int ret; |
1063 | ||
1064 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1065 | if (ret) | |
1066 | return ret; | |
1067 | ||
647416f9 | 1068 | *val = dev_priv->next_seqno; |
40633219 MK |
1069 | mutex_unlock(&dev->struct_mutex); |
1070 | ||
647416f9 | 1071 | return 0; |
40633219 MK |
1072 | } |
1073 | ||
647416f9 KC |
1074 | static int |
1075 | i915_next_seqno_set(void *data, u64 val) | |
1076 | { | |
1077 | struct drm_device *dev = data; | |
40633219 MK |
1078 | int ret; |
1079 | ||
40633219 MK |
1080 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1081 | if (ret) | |
1082 | return ret; | |
1083 | ||
e94fbaa8 | 1084 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1085 | mutex_unlock(&dev->struct_mutex); |
1086 | ||
647416f9 | 1087 | return ret; |
40633219 MK |
1088 | } |
1089 | ||
647416f9 KC |
1090 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1091 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1092 | "0x%llx\n"); |
40633219 | 1093 | |
adb4bd12 | 1094 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1095 | { |
9f25d007 | 1096 | struct drm_info_node *node = m->private; |
f97108d1 | 1097 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1098 | struct drm_i915_private *dev_priv = to_i915(dev); |
c8c8fb33 PZ |
1099 | int ret = 0; |
1100 | ||
1101 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 JB |
1102 | |
1103 | if (IS_GEN5(dev)) { | |
1104 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1105 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1106 | ||
1107 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1108 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1109 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1110 | MEMSTAT_VID_SHIFT); | |
1111 | seq_printf(m, "Current P-state: %d\n", | |
1112 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
666a4537 WB |
1113 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
1114 | u32 freq_sts; | |
1115 | ||
1116 | mutex_lock(&dev_priv->rps.hw_lock); | |
1117 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1118 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1119 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1120 | ||
1121 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1122 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1123 | ||
1124 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1125 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1126 | ||
1127 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1128 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1129 | ||
1130 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1131 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1132 | ||
1133 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1134 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1135 | ||
1136 | seq_printf(m, | |
1137 | "efficient (RPe) frequency: %d MHz\n", | |
1138 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1139 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1140 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
35040562 BP |
1141 | u32 rp_state_limits; |
1142 | u32 gt_perf_status; | |
1143 | u32 rp_state_cap; | |
0d8f9491 | 1144 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1145 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1146 | u32 rpupei, rpcurup, rpprevup; |
1147 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1148 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1149 | int max_freq; |
1150 | ||
35040562 BP |
1151 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
1152 | if (IS_BROXTON(dev)) { | |
1153 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); | |
1154 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1155 | } else { | |
1156 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1157 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1158 | } | |
1159 | ||
3b8d8d91 | 1160 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1161 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1162 | if (ret) | |
c8c8fb33 | 1163 | goto out; |
d1ebd816 | 1164 | |
59bad947 | 1165 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1166 | |
8e8c06cd | 1167 | reqf = I915_READ(GEN6_RPNSWREQ); |
60260a5b AG |
1168 | if (IS_GEN9(dev)) |
1169 | reqf >>= 23; | |
1170 | else { | |
1171 | reqf &= ~GEN6_TURBO_DISABLE; | |
1172 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
1173 | reqf >>= 24; | |
1174 | else | |
1175 | reqf >>= 25; | |
1176 | } | |
7c59a9c1 | 1177 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1178 | |
0d8f9491 CW |
1179 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1180 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1181 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1182 | ||
ccab5c82 | 1183 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1184 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1185 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1186 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1187 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1188 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1189 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
60260a5b AG |
1190 | if (IS_GEN9(dev)) |
1191 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
1192 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
f82855d3 BW |
1193 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1194 | else | |
1195 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1196 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1197 | |
59bad947 | 1198 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1199 | mutex_unlock(&dev->struct_mutex); |
1200 | ||
9dd3c605 PZ |
1201 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1202 | pm_ier = I915_READ(GEN6_PMIER); | |
1203 | pm_imr = I915_READ(GEN6_PMIMR); | |
1204 | pm_isr = I915_READ(GEN6_PMISR); | |
1205 | pm_iir = I915_READ(GEN6_PMIIR); | |
1206 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1207 | } else { | |
1208 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1209 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1210 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1211 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1212 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1213 | } | |
0d8f9491 | 1214 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1215 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
1800ad25 | 1216 | seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); |
3b8d8d91 | 1217 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1218 | seq_printf(m, "Render p-state ratio: %d\n", |
60260a5b | 1219 | (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1220 | seq_printf(m, "Render p-state VID: %d\n", |
1221 | gt_perf_status & 0xff); | |
1222 | seq_printf(m, "Render p-state limit: %d\n", | |
1223 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1224 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1225 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1226 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1227 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1228 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1229 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1230 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1231 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1232 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1233 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1234 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1235 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1236 | seq_printf(m, "Up threshold: %d%%\n", |
1237 | dev_priv->rps.up_threshold); | |
1238 | ||
d6cda9c7 AG |
1239 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1240 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1241 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1242 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1243 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1244 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1245 | seq_printf(m, "Down threshold: %d%%\n", |
1246 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1247 | |
35040562 BP |
1248 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : |
1249 | rp_state_cap >> 16) & 0xff; | |
ef11bdb3 RV |
1250 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1251 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1252 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1253 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1254 | |
1255 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
ef11bdb3 RV |
1256 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1257 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1258 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1259 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1260 | |
35040562 BP |
1261 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : |
1262 | rp_state_cap >> 0) & 0xff; | |
ef11bdb3 RV |
1263 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1264 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1265 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1266 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1267 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1268 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1269 | |
d86ed34a CW |
1270 | seq_printf(m, "Current freq: %d MHz\n", |
1271 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1272 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1273 | seq_printf(m, "Idle freq: %d MHz\n", |
1274 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1275 | seq_printf(m, "Min freq: %d MHz\n", |
1276 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
29ecd78d CW |
1277 | seq_printf(m, "Boost freq: %d MHz\n", |
1278 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
d86ed34a CW |
1279 | seq_printf(m, "Max freq: %d MHz\n", |
1280 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1281 | seq_printf(m, | |
1282 | "efficient (RPe) frequency: %d MHz\n", | |
1283 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1284 | } else { |
267f0c90 | 1285 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1286 | } |
f97108d1 | 1287 | |
1170f28c MK |
1288 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1289 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1290 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1291 | ||
c8c8fb33 PZ |
1292 | out: |
1293 | intel_runtime_pm_put(dev_priv); | |
1294 | return ret; | |
f97108d1 JB |
1295 | } |
1296 | ||
f654449a CW |
1297 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1298 | { | |
1299 | struct drm_info_node *node = m->private; | |
ebbc7546 | 1300 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1301 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 1302 | struct intel_engine_cs *engine; |
666796da TU |
1303 | u64 acthd[I915_NUM_ENGINES]; |
1304 | u32 seqno[I915_NUM_ENGINES]; | |
61642ff0 | 1305 | u32 instdone[I915_NUM_INSTDONE_REG]; |
c3232b18 DG |
1306 | enum intel_engine_id id; |
1307 | int j; | |
f654449a CW |
1308 | |
1309 | if (!i915.enable_hangcheck) { | |
1310 | seq_printf(m, "Hangcheck disabled\n"); | |
1311 | return 0; | |
1312 | } | |
1313 | ||
ebbc7546 MK |
1314 | intel_runtime_pm_get(dev_priv); |
1315 | ||
c3232b18 | 1316 | for_each_engine_id(engine, dev_priv, id) { |
7e37f889 | 1317 | acthd[id] = intel_engine_get_active_head(engine); |
1b7744e7 | 1318 | seqno[id] = intel_engine_get_seqno(engine); |
ebbc7546 MK |
1319 | } |
1320 | ||
c033666a | 1321 | i915_get_extra_instdone(dev_priv, instdone); |
61642ff0 | 1322 | |
ebbc7546 MK |
1323 | intel_runtime_pm_put(dev_priv); |
1324 | ||
f654449a CW |
1325 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1326 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1327 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1328 | jiffies)); | |
1329 | } else | |
1330 | seq_printf(m, "Hangcheck inactive\n"); | |
1331 | ||
c3232b18 | 1332 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 1333 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d CW |
1334 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
1335 | engine->hangcheck.seqno, | |
1336 | seqno[id], | |
1337 | engine->last_submitted_seqno); | |
83348ba8 CW |
1338 | seq_printf(m, "\twaiters? %s, fake irq active? %s\n", |
1339 | yesno(intel_engine_has_waiter(engine)), | |
1340 | yesno(test_bit(engine->id, | |
1341 | &dev_priv->gpu_error.missed_irq_rings))); | |
f654449a | 1342 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1343 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1344 | (long long)acthd[id]); |
e2f80391 TU |
1345 | seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); |
1346 | seq_printf(m, "\taction = %d\n", engine->hangcheck.action); | |
61642ff0 | 1347 | |
e2f80391 | 1348 | if (engine->id == RCS) { |
61642ff0 MK |
1349 | seq_puts(m, "\tinstdone read ="); |
1350 | ||
1351 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1352 | seq_printf(m, " 0x%08x", instdone[j]); | |
1353 | ||
1354 | seq_puts(m, "\n\tinstdone accu ="); | |
1355 | ||
1356 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1357 | seq_printf(m, " 0x%08x", | |
e2f80391 | 1358 | engine->hangcheck.instdone[j]); |
61642ff0 MK |
1359 | |
1360 | seq_puts(m, "\n"); | |
1361 | } | |
f654449a CW |
1362 | } |
1363 | ||
1364 | return 0; | |
1365 | } | |
1366 | ||
4d85529d | 1367 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1368 | { |
9f25d007 | 1369 | struct drm_info_node *node = m->private; |
f97108d1 | 1370 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1371 | struct drm_i915_private *dev_priv = to_i915(dev); |
616fdb5a BW |
1372 | u32 rgvmodectl, rstdbyctl; |
1373 | u16 crstandvid; | |
1374 | int ret; | |
1375 | ||
1376 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1377 | if (ret) | |
1378 | return ret; | |
c8c8fb33 | 1379 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1380 | |
1381 | rgvmodectl = I915_READ(MEMMODECTL); | |
1382 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1383 | crstandvid = I915_READ16(CRSTANDVID); | |
1384 | ||
c8c8fb33 | 1385 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1386 | mutex_unlock(&dev->struct_mutex); |
f97108d1 | 1387 | |
742f491d | 1388 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1389 | seq_printf(m, "Boost freq: %d\n", |
1390 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1391 | MEMMODE_BOOST_FREQ_SHIFT); | |
1392 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1393 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1394 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1395 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1396 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1397 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1398 | seq_printf(m, "Starting frequency: P%d\n", |
1399 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1400 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1401 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1402 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1403 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1404 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1405 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1406 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1407 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1408 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1409 | case RSX_STATUS_ON: | |
267f0c90 | 1410 | seq_puts(m, "on\n"); |
88271da3 JB |
1411 | break; |
1412 | case RSX_STATUS_RC1: | |
267f0c90 | 1413 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1414 | break; |
1415 | case RSX_STATUS_RC1E: | |
267f0c90 | 1416 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1417 | break; |
1418 | case RSX_STATUS_RS1: | |
267f0c90 | 1419 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1420 | break; |
1421 | case RSX_STATUS_RS2: | |
267f0c90 | 1422 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1423 | break; |
1424 | case RSX_STATUS_RS3: | |
267f0c90 | 1425 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1426 | break; |
1427 | default: | |
267f0c90 | 1428 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1429 | break; |
1430 | } | |
f97108d1 JB |
1431 | |
1432 | return 0; | |
1433 | } | |
1434 | ||
f65367b5 | 1435 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1436 | { |
b2cff0db CW |
1437 | struct drm_info_node *node = m->private; |
1438 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 1439 | struct drm_i915_private *dev_priv = to_i915(dev); |
b2cff0db | 1440 | struct intel_uncore_forcewake_domain *fw_domain; |
b2cff0db CW |
1441 | |
1442 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1443 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1444 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1445 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1446 | fw_domain->wake_count); |
1447 | } | |
1448 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1449 | |
b2cff0db CW |
1450 | return 0; |
1451 | } | |
1452 | ||
1453 | static int vlv_drpc_info(struct seq_file *m) | |
1454 | { | |
9f25d007 | 1455 | struct drm_info_node *node = m->private; |
669ab5aa | 1456 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1457 | struct drm_i915_private *dev_priv = to_i915(dev); |
6b312cd3 | 1458 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1459 | |
d46c0517 ID |
1460 | intel_runtime_pm_get(dev_priv); |
1461 | ||
6b312cd3 | 1462 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1463 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1464 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1465 | ||
d46c0517 ID |
1466 | intel_runtime_pm_put(dev_priv); |
1467 | ||
669ab5aa D |
1468 | seq_printf(m, "Video Turbo Mode: %s\n", |
1469 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1470 | seq_printf(m, "Turbo enabled: %s\n", | |
1471 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1472 | seq_printf(m, "HW control enabled: %s\n", | |
1473 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1474 | seq_printf(m, "SW control enabled: %s\n", | |
1475 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1476 | GEN6_RP_MEDIA_SW_MODE)); | |
1477 | seq_printf(m, "RC6 Enabled: %s\n", | |
1478 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1479 | GEN6_RC_CTL_EI_MODE(1)))); | |
1480 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1481 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1482 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1483 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1484 | |
9cc19be5 ID |
1485 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1486 | I915_READ(VLV_GT_RENDER_RC6)); | |
1487 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1488 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1489 | ||
f65367b5 | 1490 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1491 | } |
1492 | ||
4d85529d BW |
1493 | static int gen6_drpc_info(struct seq_file *m) |
1494 | { | |
9f25d007 | 1495 | struct drm_info_node *node = m->private; |
4d85529d | 1496 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1497 | struct drm_i915_private *dev_priv = to_i915(dev); |
ecd8faea | 1498 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
f2dd7578 | 1499 | u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; |
93b525dc | 1500 | unsigned forcewake_count; |
aee56cff | 1501 | int count = 0, ret; |
4d85529d BW |
1502 | |
1503 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1504 | if (ret) | |
1505 | return ret; | |
c8c8fb33 | 1506 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1507 | |
907b28c5 | 1508 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1509 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1510 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1511 | |
1512 | if (forcewake_count) { | |
267f0c90 DL |
1513 | seq_puts(m, "RC information inaccurate because somebody " |
1514 | "holds a forcewake reference \n"); | |
4d85529d BW |
1515 | } else { |
1516 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1517 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1518 | udelay(10); | |
1519 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1520 | } | |
1521 | ||
75aa3f63 | 1522 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1523 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1524 | |
1525 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1526 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
f2dd7578 AG |
1527 | if (INTEL_INFO(dev)->gen >= 9) { |
1528 | gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); | |
1529 | gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); | |
1530 | } | |
4d85529d | 1531 | mutex_unlock(&dev->struct_mutex); |
44cbd338 BW |
1532 | mutex_lock(&dev_priv->rps.hw_lock); |
1533 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1534 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1535 | |
c8c8fb33 PZ |
1536 | intel_runtime_pm_put(dev_priv); |
1537 | ||
4d85529d BW |
1538 | seq_printf(m, "Video Turbo Mode: %s\n", |
1539 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1540 | seq_printf(m, "HW control enabled: %s\n", | |
1541 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1542 | seq_printf(m, "SW control enabled: %s\n", | |
1543 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1544 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1545 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1546 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1547 | seq_printf(m, "RC6 Enabled: %s\n", | |
1548 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
f2dd7578 AG |
1549 | if (INTEL_INFO(dev)->gen >= 9) { |
1550 | seq_printf(m, "Render Well Gating Enabled: %s\n", | |
1551 | yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); | |
1552 | seq_printf(m, "Media Well Gating Enabled: %s\n", | |
1553 | yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); | |
1554 | } | |
4d85529d BW |
1555 | seq_printf(m, "Deep RC6 Enabled: %s\n", |
1556 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1557 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1558 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1559 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1560 | switch (gt_core_status & GEN6_RCn_MASK) { |
1561 | case GEN6_RC0: | |
1562 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1563 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1564 | else |
267f0c90 | 1565 | seq_puts(m, "on\n"); |
4d85529d BW |
1566 | break; |
1567 | case GEN6_RC3: | |
267f0c90 | 1568 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1569 | break; |
1570 | case GEN6_RC6: | |
267f0c90 | 1571 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1572 | break; |
1573 | case GEN6_RC7: | |
267f0c90 | 1574 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1575 | break; |
1576 | default: | |
267f0c90 | 1577 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1578 | break; |
1579 | } | |
1580 | ||
1581 | seq_printf(m, "Core Power Down: %s\n", | |
1582 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
f2dd7578 AG |
1583 | if (INTEL_INFO(dev)->gen >= 9) { |
1584 | seq_printf(m, "Render Power Well: %s\n", | |
1585 | (gen9_powergate_status & | |
1586 | GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1587 | seq_printf(m, "Media Power Well: %s\n", | |
1588 | (gen9_powergate_status & | |
1589 | GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1590 | } | |
cce66a28 BW |
1591 | |
1592 | /* Not exactly sure what this is */ | |
1593 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1594 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1595 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1596 | I915_READ(GEN6_GT_GFX_RC6)); | |
1597 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1598 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1599 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1600 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1601 | ||
ecd8faea BW |
1602 | seq_printf(m, "RC6 voltage: %dmV\n", |
1603 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1604 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1605 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1606 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1607 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
f2dd7578 | 1608 | return i915_forcewake_domains(m, NULL); |
4d85529d BW |
1609 | } |
1610 | ||
1611 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1612 | { | |
9f25d007 | 1613 | struct drm_info_node *node = m->private; |
4d85529d BW |
1614 | struct drm_device *dev = node->minor->dev; |
1615 | ||
666a4537 | 1616 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
669ab5aa | 1617 | return vlv_drpc_info(m); |
ac66cf4b | 1618 | else if (INTEL_INFO(dev)->gen >= 6) |
4d85529d BW |
1619 | return gen6_drpc_info(m); |
1620 | else | |
1621 | return ironlake_drpc_info(m); | |
1622 | } | |
1623 | ||
9a851789 DV |
1624 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1625 | { | |
1626 | struct drm_info_node *node = m->private; | |
1627 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 1628 | struct drm_i915_private *dev_priv = to_i915(dev); |
9a851789 DV |
1629 | |
1630 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1631 | dev_priv->fb_tracking.busy_bits); | |
1632 | ||
1633 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1634 | dev_priv->fb_tracking.flip_bits); | |
1635 | ||
1636 | return 0; | |
1637 | } | |
1638 | ||
b5e50c3f JB |
1639 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1640 | { | |
9f25d007 | 1641 | struct drm_info_node *node = m->private; |
b5e50c3f | 1642 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1643 | struct drm_i915_private *dev_priv = to_i915(dev); |
b5e50c3f | 1644 | |
3a77c4c4 | 1645 | if (!HAS_FBC(dev)) { |
267f0c90 | 1646 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1647 | return 0; |
1648 | } | |
1649 | ||
36623ef8 | 1650 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1651 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1652 | |
0e631adc | 1653 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1654 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1655 | else |
1656 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1657 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1658 | |
31b9df10 PZ |
1659 | if (INTEL_INFO(dev_priv)->gen >= 7) |
1660 | seq_printf(m, "Compressing: %s\n", | |
1661 | yesno(I915_READ(FBC_STATUS2) & | |
1662 | FBC_COMPRESSION_MASK)); | |
1663 | ||
25ad93fd | 1664 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1665 | intel_runtime_pm_put(dev_priv); |
1666 | ||
b5e50c3f JB |
1667 | return 0; |
1668 | } | |
1669 | ||
da46f936 RV |
1670 | static int i915_fbc_fc_get(void *data, u64 *val) |
1671 | { | |
1672 | struct drm_device *dev = data; | |
fac5e23e | 1673 | struct drm_i915_private *dev_priv = to_i915(dev); |
da46f936 RV |
1674 | |
1675 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1676 | return -ENODEV; | |
1677 | ||
da46f936 | 1678 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1679 | |
1680 | return 0; | |
1681 | } | |
1682 | ||
1683 | static int i915_fbc_fc_set(void *data, u64 val) | |
1684 | { | |
1685 | struct drm_device *dev = data; | |
fac5e23e | 1686 | struct drm_i915_private *dev_priv = to_i915(dev); |
da46f936 RV |
1687 | u32 reg; |
1688 | ||
1689 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1690 | return -ENODEV; | |
1691 | ||
25ad93fd | 1692 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1693 | |
1694 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1695 | dev_priv->fbc.false_color = val; | |
1696 | ||
1697 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1698 | (reg | FBC_CTL_FALSE_COLOR) : | |
1699 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1700 | ||
25ad93fd | 1701 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1702 | return 0; |
1703 | } | |
1704 | ||
1705 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1706 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1707 | "%llu\n"); | |
1708 | ||
92d44621 PZ |
1709 | static int i915_ips_status(struct seq_file *m, void *unused) |
1710 | { | |
9f25d007 | 1711 | struct drm_info_node *node = m->private; |
92d44621 | 1712 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1713 | struct drm_i915_private *dev_priv = to_i915(dev); |
92d44621 | 1714 | |
f5adf94e | 1715 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1716 | seq_puts(m, "not supported\n"); |
1717 | return 0; | |
1718 | } | |
1719 | ||
36623ef8 PZ |
1720 | intel_runtime_pm_get(dev_priv); |
1721 | ||
0eaa53f0 RV |
1722 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1723 | yesno(i915.enable_ips)); | |
1724 | ||
1725 | if (INTEL_INFO(dev)->gen >= 8) { | |
1726 | seq_puts(m, "Currently: unknown\n"); | |
1727 | } else { | |
1728 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1729 | seq_puts(m, "Currently: enabled\n"); | |
1730 | else | |
1731 | seq_puts(m, "Currently: disabled\n"); | |
1732 | } | |
92d44621 | 1733 | |
36623ef8 PZ |
1734 | intel_runtime_pm_put(dev_priv); |
1735 | ||
92d44621 PZ |
1736 | return 0; |
1737 | } | |
1738 | ||
4a9bef37 JB |
1739 | static int i915_sr_status(struct seq_file *m, void *unused) |
1740 | { | |
9f25d007 | 1741 | struct drm_info_node *node = m->private; |
4a9bef37 | 1742 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1743 | struct drm_i915_private *dev_priv = to_i915(dev); |
4a9bef37 JB |
1744 | bool sr_enabled = false; |
1745 | ||
36623ef8 PZ |
1746 | intel_runtime_pm_get(dev_priv); |
1747 | ||
1398261a | 1748 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1749 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
77b64555 ACO |
1750 | else if (IS_CRESTLINE(dev) || IS_G4X(dev) || |
1751 | IS_I945G(dev) || IS_I945GM(dev)) | |
4a9bef37 JB |
1752 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1753 | else if (IS_I915GM(dev)) | |
1754 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1755 | else if (IS_PINEVIEW(dev)) | |
1756 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
666a4537 | 1757 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
77b64555 | 1758 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1759 | |
36623ef8 PZ |
1760 | intel_runtime_pm_put(dev_priv); |
1761 | ||
5ba2aaaa CW |
1762 | seq_printf(m, "self-refresh: %s\n", |
1763 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1764 | |
1765 | return 0; | |
1766 | } | |
1767 | ||
7648fa99 JB |
1768 | static int i915_emon_status(struct seq_file *m, void *unused) |
1769 | { | |
9f25d007 | 1770 | struct drm_info_node *node = m->private; |
7648fa99 | 1771 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1772 | struct drm_i915_private *dev_priv = to_i915(dev); |
7648fa99 | 1773 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1774 | int ret; |
1775 | ||
582be6b4 CW |
1776 | if (!IS_GEN5(dev)) |
1777 | return -ENODEV; | |
1778 | ||
de227ef0 CW |
1779 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1780 | if (ret) | |
1781 | return ret; | |
7648fa99 JB |
1782 | |
1783 | temp = i915_mch_val(dev_priv); | |
1784 | chipset = i915_chipset_val(dev_priv); | |
1785 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1786 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1787 | |
1788 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1789 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1790 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1791 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1792 | ||
1793 | return 0; | |
1794 | } | |
1795 | ||
23b2f8bb JB |
1796 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1797 | { | |
9f25d007 | 1798 | struct drm_info_node *node = m->private; |
23b2f8bb | 1799 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1800 | struct drm_i915_private *dev_priv = to_i915(dev); |
5bfa0199 | 1801 | int ret = 0; |
23b2f8bb | 1802 | int gpu_freq, ia_freq; |
f936ec34 | 1803 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1804 | |
97d3308a | 1805 | if (!HAS_CORE_RING_FREQ(dev)) { |
267f0c90 | 1806 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1807 | return 0; |
1808 | } | |
1809 | ||
5bfa0199 PZ |
1810 | intel_runtime_pm_get(dev_priv); |
1811 | ||
4fc688ce | 1812 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1813 | if (ret) |
5bfa0199 | 1814 | goto out; |
23b2f8bb | 1815 | |
ef11bdb3 | 1816 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
f936ec34 AG |
1817 | /* Convert GT frequency to 50 HZ units */ |
1818 | min_gpu_freq = | |
1819 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1820 | max_gpu_freq = | |
1821 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1822 | } else { | |
1823 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1824 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1825 | } | |
1826 | ||
267f0c90 | 1827 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1828 | |
f936ec34 | 1829 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1830 | ia_freq = gpu_freq; |
1831 | sandybridge_pcode_read(dev_priv, | |
1832 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1833 | &ia_freq); | |
3ebecd07 | 1834 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1835 | intel_gpu_freq(dev_priv, (gpu_freq * |
ef11bdb3 RV |
1836 | (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1837 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1838 | ((ia_freq >> 0) & 0xff) * 100, |
1839 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1840 | } |
1841 | ||
4fc688ce | 1842 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1843 | |
5bfa0199 PZ |
1844 | out: |
1845 | intel_runtime_pm_put(dev_priv); | |
1846 | return ret; | |
23b2f8bb JB |
1847 | } |
1848 | ||
44834a67 CW |
1849 | static int i915_opregion(struct seq_file *m, void *unused) |
1850 | { | |
9f25d007 | 1851 | struct drm_info_node *node = m->private; |
44834a67 | 1852 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1853 | struct drm_i915_private *dev_priv = to_i915(dev); |
44834a67 CW |
1854 | struct intel_opregion *opregion = &dev_priv->opregion; |
1855 | int ret; | |
1856 | ||
1857 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1858 | if (ret) | |
0d38f009 | 1859 | goto out; |
44834a67 | 1860 | |
2455a8e4 JN |
1861 | if (opregion->header) |
1862 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1863 | |
1864 | mutex_unlock(&dev->struct_mutex); | |
1865 | ||
0d38f009 | 1866 | out: |
44834a67 CW |
1867 | return 0; |
1868 | } | |
1869 | ||
ada8f955 JN |
1870 | static int i915_vbt(struct seq_file *m, void *unused) |
1871 | { | |
1872 | struct drm_info_node *node = m->private; | |
1873 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 1874 | struct drm_i915_private *dev_priv = to_i915(dev); |
ada8f955 JN |
1875 | struct intel_opregion *opregion = &dev_priv->opregion; |
1876 | ||
1877 | if (opregion->vbt) | |
1878 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1879 | ||
1880 | return 0; | |
1881 | } | |
1882 | ||
37811fcc CW |
1883 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1884 | { | |
9f25d007 | 1885 | struct drm_info_node *node = m->private; |
37811fcc | 1886 | struct drm_device *dev = node->minor->dev; |
b13b8402 | 1887 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1888 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1889 | int ret; |
1890 | ||
1891 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1892 | if (ret) | |
1893 | return ret; | |
37811fcc | 1894 | |
0695726e | 1895 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
25bcce94 CW |
1896 | if (to_i915(dev)->fbdev) { |
1897 | fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb); | |
1898 | ||
1899 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1900 | fbdev_fb->base.width, | |
1901 | fbdev_fb->base.height, | |
1902 | fbdev_fb->base.depth, | |
1903 | fbdev_fb->base.bits_per_pixel, | |
1904 | fbdev_fb->base.modifier[0], | |
1905 | drm_framebuffer_read_refcount(&fbdev_fb->base)); | |
1906 | describe_obj(m, fbdev_fb->obj); | |
1907 | seq_putc(m, '\n'); | |
1908 | } | |
4520f53a | 1909 | #endif |
37811fcc | 1910 | |
4b096ac1 | 1911 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1912 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1913 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1914 | if (fb == fbdev_fb) | |
37811fcc CW |
1915 | continue; |
1916 | ||
c1ca506d | 1917 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1918 | fb->base.width, |
1919 | fb->base.height, | |
1920 | fb->base.depth, | |
623f9783 | 1921 | fb->base.bits_per_pixel, |
c1ca506d | 1922 | fb->base.modifier[0], |
747a598f | 1923 | drm_framebuffer_read_refcount(&fb->base)); |
05394f39 | 1924 | describe_obj(m, fb->obj); |
267f0c90 | 1925 | seq_putc(m, '\n'); |
37811fcc | 1926 | } |
4b096ac1 | 1927 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1928 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1929 | |
1930 | return 0; | |
1931 | } | |
1932 | ||
7e37f889 | 1933 | static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) |
c9fe99bd OM |
1934 | { |
1935 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
7e37f889 CW |
1936 | ring->space, ring->head, ring->tail, |
1937 | ring->last_retired_head); | |
c9fe99bd OM |
1938 | } |
1939 | ||
e76d3630 BW |
1940 | static int i915_context_status(struct seq_file *m, void *unused) |
1941 | { | |
9f25d007 | 1942 | struct drm_info_node *node = m->private; |
e76d3630 | 1943 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 1944 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 1945 | struct intel_engine_cs *engine; |
e2efd130 | 1946 | struct i915_gem_context *ctx; |
c3232b18 | 1947 | int ret; |
e76d3630 | 1948 | |
f3d28878 | 1949 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1950 | if (ret) |
1951 | return ret; | |
1952 | ||
a33afea5 | 1953 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
5d1808ec | 1954 | seq_printf(m, "HW context %u ", ctx->hw_id); |
d28b99ab CW |
1955 | if (IS_ERR(ctx->file_priv)) { |
1956 | seq_puts(m, "(deleted) "); | |
1957 | } else if (ctx->file_priv) { | |
1958 | struct pid *pid = ctx->file_priv->file->pid; | |
1959 | struct task_struct *task; | |
1960 | ||
1961 | task = get_pid_task(pid, PIDTYPE_PID); | |
1962 | if (task) { | |
1963 | seq_printf(m, "(%s [%d]) ", | |
1964 | task->comm, task->pid); | |
1965 | put_task_struct(task); | |
1966 | } | |
1967 | } else { | |
1968 | seq_puts(m, "(kernel) "); | |
1969 | } | |
1970 | ||
bca44d80 CW |
1971 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
1972 | seq_putc(m, '\n'); | |
c9fe99bd | 1973 | |
bca44d80 CW |
1974 | for_each_engine(engine, dev_priv) { |
1975 | struct intel_context *ce = &ctx->engine[engine->id]; | |
1976 | ||
1977 | seq_printf(m, "%s: ", engine->name); | |
1978 | seq_putc(m, ce->initialised ? 'I' : 'i'); | |
1979 | if (ce->state) | |
bf3783e5 | 1980 | describe_obj(m, ce->state->obj); |
dca33ecc | 1981 | if (ce->ring) |
7e37f889 | 1982 | describe_ctx_ring(m, ce->ring); |
c9fe99bd | 1983 | seq_putc(m, '\n'); |
c9fe99bd | 1984 | } |
a33afea5 | 1985 | |
a33afea5 | 1986 | seq_putc(m, '\n'); |
a168c293 BW |
1987 | } |
1988 | ||
f3d28878 | 1989 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1990 | |
1991 | return 0; | |
1992 | } | |
1993 | ||
064ca1d2 | 1994 | static void i915_dump_lrc_obj(struct seq_file *m, |
e2efd130 | 1995 | struct i915_gem_context *ctx, |
0bc40be8 | 1996 | struct intel_engine_cs *engine) |
064ca1d2 | 1997 | { |
bf3783e5 | 1998 | struct i915_vma *vma = ctx->engine[engine->id].state; |
064ca1d2 | 1999 | struct page *page; |
064ca1d2 | 2000 | int j; |
064ca1d2 | 2001 | |
7069b144 CW |
2002 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
2003 | ||
bf3783e5 CW |
2004 | if (!vma) { |
2005 | seq_puts(m, "\tFake context\n"); | |
064ca1d2 TD |
2006 | return; |
2007 | } | |
2008 | ||
bf3783e5 CW |
2009 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
2010 | seq_printf(m, "\tBound in GGTT at 0x%08x\n", | |
2011 | lower_32_bits(vma->node.start)); | |
064ca1d2 | 2012 | |
bf3783e5 CW |
2013 | if (i915_gem_object_get_pages(vma->obj)) { |
2014 | seq_puts(m, "\tFailed to get pages for context object\n\n"); | |
064ca1d2 TD |
2015 | return; |
2016 | } | |
2017 | ||
bf3783e5 CW |
2018 | page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); |
2019 | if (page) { | |
2020 | u32 *reg_state = kmap_atomic(page); | |
064ca1d2 TD |
2021 | |
2022 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
bf3783e5 CW |
2023 | seq_printf(m, |
2024 | "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2025 | j * 4, | |
064ca1d2 TD |
2026 | reg_state[j], reg_state[j + 1], |
2027 | reg_state[j + 2], reg_state[j + 3]); | |
2028 | } | |
2029 | kunmap_atomic(reg_state); | |
2030 | } | |
2031 | ||
2032 | seq_putc(m, '\n'); | |
2033 | } | |
2034 | ||
c0ab1ae9 BW |
2035 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2036 | { | |
2037 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2038 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2039 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2040 | struct intel_engine_cs *engine; |
e2efd130 | 2041 | struct i915_gem_context *ctx; |
b4ac5afc | 2042 | int ret; |
c0ab1ae9 BW |
2043 | |
2044 | if (!i915.enable_execlists) { | |
2045 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2046 | return 0; | |
2047 | } | |
2048 | ||
2049 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2050 | if (ret) | |
2051 | return ret; | |
2052 | ||
e28e404c | 2053 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
24f1d3cc CW |
2054 | for_each_engine(engine, dev_priv) |
2055 | i915_dump_lrc_obj(m, ctx, engine); | |
c0ab1ae9 BW |
2056 | |
2057 | mutex_unlock(&dev->struct_mutex); | |
2058 | ||
2059 | return 0; | |
2060 | } | |
2061 | ||
4ba70e44 OM |
2062 | static int i915_execlists(struct seq_file *m, void *data) |
2063 | { | |
2064 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
2065 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2066 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2067 | struct intel_engine_cs *engine; |
4ba70e44 OM |
2068 | u32 status_pointer; |
2069 | u8 read_pointer; | |
2070 | u8 write_pointer; | |
2071 | u32 status; | |
2072 | u32 ctx_id; | |
2073 | struct list_head *cursor; | |
b4ac5afc | 2074 | int i, ret; |
4ba70e44 OM |
2075 | |
2076 | if (!i915.enable_execlists) { | |
2077 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
2078 | return 0; | |
2079 | } | |
2080 | ||
2081 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2082 | if (ret) | |
2083 | return ret; | |
2084 | ||
fc0412ec MT |
2085 | intel_runtime_pm_get(dev_priv); |
2086 | ||
b4ac5afc | 2087 | for_each_engine(engine, dev_priv) { |
6d3d8274 | 2088 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 | 2089 | int count = 0; |
4ba70e44 | 2090 | |
e2f80391 | 2091 | seq_printf(m, "%s\n", engine->name); |
4ba70e44 | 2092 | |
e2f80391 TU |
2093 | status = I915_READ(RING_EXECLIST_STATUS_LO(engine)); |
2094 | ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine)); | |
4ba70e44 OM |
2095 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
2096 | status, ctx_id); | |
2097 | ||
e2f80391 | 2098 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); |
4ba70e44 OM |
2099 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
2100 | ||
e2f80391 | 2101 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 2102 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
4ba70e44 | 2103 | if (read_pointer > write_pointer) |
5590a5f0 | 2104 | write_pointer += GEN8_CSB_ENTRIES; |
4ba70e44 OM |
2105 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
2106 | read_pointer, write_pointer); | |
2107 | ||
5590a5f0 | 2108 | for (i = 0; i < GEN8_CSB_ENTRIES; i++) { |
e2f80391 TU |
2109 | status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i)); |
2110 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i)); | |
4ba70e44 OM |
2111 | |
2112 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
2113 | i, status, ctx_id); | |
2114 | } | |
2115 | ||
27af5eea | 2116 | spin_lock_bh(&engine->execlist_lock); |
e2f80391 | 2117 | list_for_each(cursor, &engine->execlist_queue) |
4ba70e44 | 2118 | count++; |
e2f80391 TU |
2119 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
2120 | struct drm_i915_gem_request, | |
2121 | execlist_link); | |
27af5eea | 2122 | spin_unlock_bh(&engine->execlist_lock); |
4ba70e44 OM |
2123 | |
2124 | seq_printf(m, "\t%d requests in queue\n", count); | |
2125 | if (head_req) { | |
7069b144 CW |
2126 | seq_printf(m, "\tHead request context: %u\n", |
2127 | head_req->ctx->hw_id); | |
4ba70e44 | 2128 | seq_printf(m, "\tHead request tail: %u\n", |
6d3d8274 | 2129 | head_req->tail); |
4ba70e44 OM |
2130 | } |
2131 | ||
2132 | seq_putc(m, '\n'); | |
2133 | } | |
2134 | ||
fc0412ec | 2135 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2136 | mutex_unlock(&dev->struct_mutex); |
2137 | ||
2138 | return 0; | |
2139 | } | |
2140 | ||
ea16a3cd DV |
2141 | static const char *swizzle_string(unsigned swizzle) |
2142 | { | |
aee56cff | 2143 | switch (swizzle) { |
ea16a3cd DV |
2144 | case I915_BIT_6_SWIZZLE_NONE: |
2145 | return "none"; | |
2146 | case I915_BIT_6_SWIZZLE_9: | |
2147 | return "bit9"; | |
2148 | case I915_BIT_6_SWIZZLE_9_10: | |
2149 | return "bit9/bit10"; | |
2150 | case I915_BIT_6_SWIZZLE_9_11: | |
2151 | return "bit9/bit11"; | |
2152 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2153 | return "bit9/bit10/bit11"; | |
2154 | case I915_BIT_6_SWIZZLE_9_17: | |
2155 | return "bit9/bit17"; | |
2156 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2157 | return "bit9/bit10/bit17"; | |
2158 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2159 | return "unknown"; |
ea16a3cd DV |
2160 | } |
2161 | ||
2162 | return "bug"; | |
2163 | } | |
2164 | ||
2165 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2166 | { | |
9f25d007 | 2167 | struct drm_info_node *node = m->private; |
ea16a3cd | 2168 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 2169 | struct drm_i915_private *dev_priv = to_i915(dev); |
22bcfc6a DV |
2170 | int ret; |
2171 | ||
2172 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2173 | if (ret) | |
2174 | return ret; | |
c8c8fb33 | 2175 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2176 | |
ea16a3cd DV |
2177 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2178 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2179 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2180 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2181 | ||
2182 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
2183 | seq_printf(m, "DDC = 0x%08x\n", | |
2184 | I915_READ(DCC)); | |
656bfa3a DV |
2185 | seq_printf(m, "DDC2 = 0x%08x\n", |
2186 | I915_READ(DCC2)); | |
ea16a3cd DV |
2187 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2188 | I915_READ16(C0DRB3)); | |
2189 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2190 | I915_READ16(C1DRB3)); | |
9d3203e1 | 2191 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
2192 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2193 | I915_READ(MAD_DIMM_C0)); | |
2194 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2195 | I915_READ(MAD_DIMM_C1)); | |
2196 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2197 | I915_READ(MAD_DIMM_C2)); | |
2198 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2199 | I915_READ(TILECTL)); | |
5907f5fb | 2200 | if (INTEL_INFO(dev)->gen >= 8) |
9d3203e1 BW |
2201 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2202 | I915_READ(GAMTARBMODE)); | |
2203 | else | |
2204 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2205 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2206 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2207 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2208 | } |
656bfa3a DV |
2209 | |
2210 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2211 | seq_puts(m, "L-shaped memory detected\n"); | |
2212 | ||
c8c8fb33 | 2213 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2214 | mutex_unlock(&dev->struct_mutex); |
2215 | ||
2216 | return 0; | |
2217 | } | |
2218 | ||
1c60fef5 BW |
2219 | static int per_file_ctx(int id, void *ptr, void *data) |
2220 | { | |
e2efd130 | 2221 | struct i915_gem_context *ctx = ptr; |
1c60fef5 | 2222 | struct seq_file *m = data; |
ae6c4806 DV |
2223 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2224 | ||
2225 | if (!ppgtt) { | |
2226 | seq_printf(m, " no ppgtt for context %d\n", | |
2227 | ctx->user_handle); | |
2228 | return 0; | |
2229 | } | |
1c60fef5 | 2230 | |
f83d6518 OM |
2231 | if (i915_gem_context_is_default(ctx)) |
2232 | seq_puts(m, " default context:\n"); | |
2233 | else | |
821d66dd | 2234 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2235 | ppgtt->debug_dump(ppgtt, m); |
2236 | ||
2237 | return 0; | |
2238 | } | |
2239 | ||
77df6772 | 2240 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 2241 | { |
fac5e23e | 2242 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2243 | struct intel_engine_cs *engine; |
77df6772 | 2244 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
b4ac5afc | 2245 | int i; |
3cf17fc5 | 2246 | |
77df6772 BW |
2247 | if (!ppgtt) |
2248 | return; | |
2249 | ||
b4ac5afc | 2250 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2251 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2252 | for (i = 0; i < 4; i++) { |
e2f80391 | 2253 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2254 | pdp <<= 32; |
e2f80391 | 2255 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2256 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2257 | } |
2258 | } | |
2259 | } | |
2260 | ||
2261 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
2262 | { | |
fac5e23e | 2263 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2264 | struct intel_engine_cs *engine; |
3cf17fc5 | 2265 | |
7e22dbbb | 2266 | if (IS_GEN6(dev_priv)) |
3cf17fc5 DV |
2267 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); |
2268 | ||
b4ac5afc | 2269 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2270 | seq_printf(m, "%s\n", engine->name); |
7e22dbbb | 2271 | if (IS_GEN7(dev_priv)) |
e2f80391 TU |
2272 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2273 | I915_READ(RING_MODE_GEN7(engine))); | |
2274 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2275 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2276 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2277 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2278 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2279 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2280 | } |
2281 | if (dev_priv->mm.aliasing_ppgtt) { | |
2282 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2283 | ||
267f0c90 | 2284 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2285 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2286 | |
87d60b63 | 2287 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2288 | } |
1c60fef5 | 2289 | |
3cf17fc5 | 2290 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2291 | } |
2292 | ||
2293 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2294 | { | |
9f25d007 | 2295 | struct drm_info_node *node = m->private; |
77df6772 | 2296 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 2297 | struct drm_i915_private *dev_priv = to_i915(dev); |
ea91e401 | 2298 | struct drm_file *file; |
77df6772 BW |
2299 | |
2300 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2301 | if (ret) | |
2302 | return ret; | |
c8c8fb33 | 2303 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
2304 | |
2305 | if (INTEL_INFO(dev)->gen >= 8) | |
2306 | gen8_ppgtt_info(m, dev); | |
2307 | else if (INTEL_INFO(dev)->gen >= 6) | |
2308 | gen6_ppgtt_info(m, dev); | |
2309 | ||
1d2ac403 | 2310 | mutex_lock(&dev->filelist_mutex); |
ea91e401 MT |
2311 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2312 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2313 | struct task_struct *task; |
ea91e401 | 2314 | |
7cb5dff8 | 2315 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2316 | if (!task) { |
2317 | ret = -ESRCH; | |
b0212486 | 2318 | goto out_unlock; |
06812760 | 2319 | } |
7cb5dff8 GT |
2320 | seq_printf(m, "\nproc: %s\n", task->comm); |
2321 | put_task_struct(task); | |
ea91e401 MT |
2322 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2323 | (void *)(unsigned long)m); | |
2324 | } | |
b0212486 | 2325 | out_unlock: |
1d2ac403 | 2326 | mutex_unlock(&dev->filelist_mutex); |
ea91e401 | 2327 | |
c8c8fb33 | 2328 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
2329 | mutex_unlock(&dev->struct_mutex); |
2330 | ||
06812760 | 2331 | return ret; |
3cf17fc5 DV |
2332 | } |
2333 | ||
f5a4c67d CW |
2334 | static int count_irq_waiters(struct drm_i915_private *i915) |
2335 | { | |
e2f80391 | 2336 | struct intel_engine_cs *engine; |
f5a4c67d | 2337 | int count = 0; |
f5a4c67d | 2338 | |
b4ac5afc | 2339 | for_each_engine(engine, i915) |
688e6c72 | 2340 | count += intel_engine_has_waiter(engine); |
f5a4c67d CW |
2341 | |
2342 | return count; | |
2343 | } | |
2344 | ||
7466c291 CW |
2345 | static const char *rps_power_to_str(unsigned int power) |
2346 | { | |
2347 | static const char * const strings[] = { | |
2348 | [LOW_POWER] = "low power", | |
2349 | [BETWEEN] = "mixed", | |
2350 | [HIGH_POWER] = "high power", | |
2351 | }; | |
2352 | ||
2353 | if (power >= ARRAY_SIZE(strings) || !strings[power]) | |
2354 | return "unknown"; | |
2355 | ||
2356 | return strings[power]; | |
2357 | } | |
2358 | ||
1854d5ca CW |
2359 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2360 | { | |
2361 | struct drm_info_node *node = m->private; | |
2362 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2363 | struct drm_i915_private *dev_priv = to_i915(dev); |
1854d5ca | 2364 | struct drm_file *file; |
1854d5ca | 2365 | |
f5a4c67d | 2366 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
67d97da3 CW |
2367 | seq_printf(m, "GPU busy? %s [%x]\n", |
2368 | yesno(dev_priv->gt.awake), dev_priv->gt.active_engines); | |
f5a4c67d | 2369 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); |
7466c291 CW |
2370 | seq_printf(m, "Frequency requested %d\n", |
2371 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
2372 | seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
f5a4c67d CW |
2373 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2374 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2375 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2376 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
7466c291 CW |
2377 | seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", |
2378 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), | |
2379 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
2380 | intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); | |
1d2ac403 DV |
2381 | |
2382 | mutex_lock(&dev->filelist_mutex); | |
8d3afd7d | 2383 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2384 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2385 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2386 | struct task_struct *task; | |
2387 | ||
2388 | rcu_read_lock(); | |
2389 | task = pid_task(file->pid, PIDTYPE_PID); | |
2390 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2391 | task ? task->comm : "<unknown>", | |
2392 | task ? task->pid : -1, | |
2e1b8730 CW |
2393 | file_priv->rps.boosts, |
2394 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2395 | rcu_read_unlock(); |
2396 | } | |
197be2ae | 2397 | seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2398 | spin_unlock(&dev_priv->rps.client_lock); |
1d2ac403 | 2399 | mutex_unlock(&dev->filelist_mutex); |
1854d5ca | 2400 | |
7466c291 CW |
2401 | if (INTEL_GEN(dev_priv) >= 6 && |
2402 | dev_priv->rps.enabled && | |
2403 | dev_priv->gt.active_engines) { | |
2404 | u32 rpup, rpupei; | |
2405 | u32 rpdown, rpdownei; | |
2406 | ||
2407 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
2408 | rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; | |
2409 | rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; | |
2410 | rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; | |
2411 | rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; | |
2412 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2413 | ||
2414 | seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", | |
2415 | rps_power_to_str(dev_priv->rps.power)); | |
2416 | seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", | |
2417 | 100 * rpup / rpupei, | |
2418 | dev_priv->rps.up_threshold); | |
2419 | seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", | |
2420 | 100 * rpdown / rpdownei, | |
2421 | dev_priv->rps.down_threshold); | |
2422 | } else { | |
2423 | seq_puts(m, "\nRPS Autotuning inactive\n"); | |
2424 | } | |
2425 | ||
8d3afd7d | 2426 | return 0; |
1854d5ca CW |
2427 | } |
2428 | ||
63573eb7 BW |
2429 | static int i915_llc(struct seq_file *m, void *data) |
2430 | { | |
9f25d007 | 2431 | struct drm_info_node *node = m->private; |
63573eb7 | 2432 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 2433 | struct drm_i915_private *dev_priv = to_i915(dev); |
3accaf7e | 2434 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2435 | |
63573eb7 | 2436 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
3accaf7e MK |
2437 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2438 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2439 | |
2440 | return 0; | |
2441 | } | |
2442 | ||
fdf5d357 AD |
2443 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2444 | { | |
2445 | struct drm_info_node *node = m->private; | |
fac5e23e | 2446 | struct drm_i915_private *dev_priv = to_i915(node->minor->dev); |
fdf5d357 AD |
2447 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
2448 | u32 tmp, i; | |
2449 | ||
2d1fe073 | 2450 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2451 | return 0; |
2452 | ||
2453 | seq_printf(m, "GuC firmware status:\n"); | |
2454 | seq_printf(m, "\tpath: %s\n", | |
2455 | guc_fw->guc_fw_path); | |
2456 | seq_printf(m, "\tfetch: %s\n", | |
2457 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2458 | seq_printf(m, "\tload: %s\n", | |
2459 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2460 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2461 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2462 | seq_printf(m, "\tversion found: %d.%d\n", | |
2463 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2464 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2465 | guc_fw->header_offset, guc_fw->header_size); | |
2466 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2467 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2468 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2469 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2470 | |
2471 | tmp = I915_READ(GUC_STATUS); | |
2472 | ||
2473 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2474 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2475 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2476 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2477 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2478 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2479 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2480 | seq_puts(m, "\nScratch registers:\n"); | |
2481 | for (i = 0; i < 16; i++) | |
2482 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2483 | ||
2484 | return 0; | |
2485 | } | |
2486 | ||
8b417c26 DG |
2487 | static void i915_guc_client_info(struct seq_file *m, |
2488 | struct drm_i915_private *dev_priv, | |
2489 | struct i915_guc_client *client) | |
2490 | { | |
e2f80391 | 2491 | struct intel_engine_cs *engine; |
c18468c4 | 2492 | enum intel_engine_id id; |
8b417c26 | 2493 | uint64_t tot = 0; |
8b417c26 DG |
2494 | |
2495 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2496 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2497 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
2498 | client->doorbell_id, client->doorbell_offset, client->cookie); | |
2499 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", | |
2500 | client->wq_size, client->wq_offset, client->wq_tail); | |
2501 | ||
551aaecd | 2502 | seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); |
8b417c26 DG |
2503 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); |
2504 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2505 | ||
c18468c4 DG |
2506 | for_each_engine_id(engine, dev_priv, id) { |
2507 | u64 submissions = client->submissions[id]; | |
2508 | tot += submissions; | |
8b417c26 | 2509 | seq_printf(m, "\tSubmissions: %llu %s\n", |
c18468c4 | 2510 | submissions, engine->name); |
8b417c26 DG |
2511 | } |
2512 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2513 | } | |
2514 | ||
2515 | static int i915_guc_info(struct seq_file *m, void *data) | |
2516 | { | |
2517 | struct drm_info_node *node = m->private; | |
2518 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2519 | struct drm_i915_private *dev_priv = to_i915(dev); |
8b417c26 | 2520 | struct intel_guc guc; |
0a0b457f | 2521 | struct i915_guc_client client = {}; |
e2f80391 | 2522 | struct intel_engine_cs *engine; |
c18468c4 | 2523 | enum intel_engine_id id; |
8b417c26 DG |
2524 | u64 total = 0; |
2525 | ||
2d1fe073 | 2526 | if (!HAS_GUC_SCHED(dev_priv)) |
8b417c26 DG |
2527 | return 0; |
2528 | ||
5a843307 AD |
2529 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
2530 | return 0; | |
2531 | ||
8b417c26 | 2532 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
8b417c26 | 2533 | guc = dev_priv->guc; |
5a843307 | 2534 | if (guc.execbuf_client) |
8b417c26 | 2535 | client = *guc.execbuf_client; |
5a843307 AD |
2536 | |
2537 | mutex_unlock(&dev->struct_mutex); | |
8b417c26 | 2538 | |
9636f6db DG |
2539 | seq_printf(m, "Doorbell map:\n"); |
2540 | seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap); | |
2541 | seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline); | |
2542 | ||
8b417c26 DG |
2543 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); |
2544 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); | |
2545 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); | |
2546 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); | |
2547 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); | |
2548 | ||
2549 | seq_printf(m, "\nGuC submissions:\n"); | |
c18468c4 DG |
2550 | for_each_engine_id(engine, dev_priv, id) { |
2551 | u64 submissions = guc.submissions[id]; | |
2552 | total += submissions; | |
397097b0 | 2553 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
c18468c4 | 2554 | engine->name, submissions, guc.last_seqno[id]); |
8b417c26 DG |
2555 | } |
2556 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2557 | ||
2558 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); | |
2559 | i915_guc_client_info(m, dev_priv, &client); | |
2560 | ||
2561 | /* Add more as required ... */ | |
2562 | ||
2563 | return 0; | |
2564 | } | |
2565 | ||
4c7e77fc AD |
2566 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2567 | { | |
2568 | struct drm_info_node *node = m->private; | |
2569 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2570 | struct drm_i915_private *dev_priv = to_i915(dev); |
8b797af1 | 2571 | struct drm_i915_gem_object *obj; |
4c7e77fc AD |
2572 | int i = 0, pg; |
2573 | ||
8b797af1 | 2574 | if (!dev_priv->guc.log_vma) |
4c7e77fc AD |
2575 | return 0; |
2576 | ||
8b797af1 CW |
2577 | obj = dev_priv->guc.log_vma->obj; |
2578 | for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { | |
2579 | u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); | |
4c7e77fc AD |
2580 | |
2581 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2582 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2583 | *(log + i), *(log + i + 1), | |
2584 | *(log + i + 2), *(log + i + 3)); | |
2585 | ||
2586 | kunmap_atomic(log); | |
2587 | } | |
2588 | ||
2589 | seq_putc(m, '\n'); | |
2590 | ||
2591 | return 0; | |
2592 | } | |
2593 | ||
e91fd8c6 RV |
2594 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2595 | { | |
2596 | struct drm_info_node *node = m->private; | |
2597 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2598 | struct drm_i915_private *dev_priv = to_i915(dev); |
a031d709 | 2599 | u32 psrperf = 0; |
a6cbdb8e RV |
2600 | u32 stat[3]; |
2601 | enum pipe pipe; | |
a031d709 | 2602 | bool enabled = false; |
e91fd8c6 | 2603 | |
3553a8ea DL |
2604 | if (!HAS_PSR(dev)) { |
2605 | seq_puts(m, "PSR not supported\n"); | |
2606 | return 0; | |
2607 | } | |
2608 | ||
c8c8fb33 PZ |
2609 | intel_runtime_pm_get(dev_priv); |
2610 | ||
fa128fa6 | 2611 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2612 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2613 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2614 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2615 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2616 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2617 | dev_priv->psr.busy_frontbuffer_bits); | |
2618 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2619 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2620 | |
3553a8ea | 2621 | if (HAS_DDI(dev)) |
443a389f | 2622 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
3553a8ea DL |
2623 | else { |
2624 | for_each_pipe(dev_priv, pipe) { | |
2625 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2626 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2627 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2628 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2629 | enabled = true; | |
a6cbdb8e RV |
2630 | } |
2631 | } | |
60e5ffe3 RV |
2632 | |
2633 | seq_printf(m, "Main link in standby mode: %s\n", | |
2634 | yesno(dev_priv->psr.link_standby)); | |
2635 | ||
a6cbdb8e RV |
2636 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2637 | ||
2638 | if (!HAS_DDI(dev)) | |
2639 | for_each_pipe(dev_priv, pipe) { | |
2640 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2641 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2642 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2643 | } | |
2644 | seq_puts(m, "\n"); | |
e91fd8c6 | 2645 | |
05eec3c2 RV |
2646 | /* |
2647 | * VLV/CHV PSR has no kind of performance counter | |
2648 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2649 | */ | |
2650 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
443a389f | 2651 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2652 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2653 | |
2654 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2655 | } | |
fa128fa6 | 2656 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2657 | |
c8c8fb33 | 2658 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2659 | return 0; |
2660 | } | |
2661 | ||
d2e216d0 RV |
2662 | static int i915_sink_crc(struct seq_file *m, void *data) |
2663 | { | |
2664 | struct drm_info_node *node = m->private; | |
2665 | struct drm_device *dev = node->minor->dev; | |
d2e216d0 RV |
2666 | struct intel_connector *connector; |
2667 | struct intel_dp *intel_dp = NULL; | |
2668 | int ret; | |
2669 | u8 crc[6]; | |
2670 | ||
2671 | drm_modeset_lock_all(dev); | |
aca5e361 | 2672 | for_each_intel_connector(dev, connector) { |
26c17cf6 | 2673 | struct drm_crtc *crtc; |
d2e216d0 | 2674 | |
26c17cf6 | 2675 | if (!connector->base.state->best_encoder) |
d2e216d0 RV |
2676 | continue; |
2677 | ||
26c17cf6 ML |
2678 | crtc = connector->base.state->crtc; |
2679 | if (!crtc->state->active) | |
b6ae3c7c PZ |
2680 | continue; |
2681 | ||
26c17cf6 | 2682 | if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) |
d2e216d0 RV |
2683 | continue; |
2684 | ||
26c17cf6 | 2685 | intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); |
d2e216d0 RV |
2686 | |
2687 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2688 | if (ret) | |
2689 | goto out; | |
2690 | ||
2691 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2692 | crc[0], crc[1], crc[2], | |
2693 | crc[3], crc[4], crc[5]); | |
2694 | goto out; | |
2695 | } | |
2696 | ret = -ENODEV; | |
2697 | out: | |
2698 | drm_modeset_unlock_all(dev); | |
2699 | return ret; | |
2700 | } | |
2701 | ||
ec013e7f JB |
2702 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2703 | { | |
2704 | struct drm_info_node *node = m->private; | |
2705 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2706 | struct drm_i915_private *dev_priv = to_i915(dev); |
ec013e7f JB |
2707 | u64 power; |
2708 | u32 units; | |
2709 | ||
2710 | if (INTEL_INFO(dev)->gen < 6) | |
2711 | return -ENODEV; | |
2712 | ||
36623ef8 PZ |
2713 | intel_runtime_pm_get(dev_priv); |
2714 | ||
ec013e7f JB |
2715 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2716 | power = (power & 0x1f00) >> 8; | |
2717 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2718 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2719 | power *= units; | |
2720 | ||
36623ef8 PZ |
2721 | intel_runtime_pm_put(dev_priv); |
2722 | ||
ec013e7f | 2723 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2724 | |
2725 | return 0; | |
2726 | } | |
2727 | ||
6455c870 | 2728 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2729 | { |
9f25d007 | 2730 | struct drm_info_node *node = m->private; |
371db66a | 2731 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 2732 | struct drm_i915_private *dev_priv = to_i915(dev); |
371db66a | 2733 | |
a156e64d CW |
2734 | if (!HAS_RUNTIME_PM(dev_priv)) |
2735 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2736 | |
67d97da3 | 2737 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); |
371db66a | 2738 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2739 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2740 | #ifdef CONFIG_PM |
a6aaec8b DL |
2741 | seq_printf(m, "Usage count: %d\n", |
2742 | atomic_read(&dev->dev->power.usage_count)); | |
0d804184 CW |
2743 | #else |
2744 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2745 | #endif | |
a156e64d | 2746 | seq_printf(m, "PCI device power state: %s [%d]\n", |
91c8a326 CW |
2747 | pci_power_name(dev_priv->drm.pdev->current_state), |
2748 | dev_priv->drm.pdev->current_state); | |
371db66a | 2749 | |
ec013e7f JB |
2750 | return 0; |
2751 | } | |
2752 | ||
1da51581 ID |
2753 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2754 | { | |
9f25d007 | 2755 | struct drm_info_node *node = m->private; |
1da51581 | 2756 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 2757 | struct drm_i915_private *dev_priv = to_i915(dev); |
1da51581 ID |
2758 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
2759 | int i; | |
2760 | ||
2761 | mutex_lock(&power_domains->lock); | |
2762 | ||
2763 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2764 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2765 | struct i915_power_well *power_well; | |
2766 | enum intel_display_power_domain power_domain; | |
2767 | ||
2768 | power_well = &power_domains->power_wells[i]; | |
2769 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2770 | power_well->count); | |
2771 | ||
2772 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2773 | power_domain++) { | |
2774 | if (!(BIT(power_domain) & power_well->domains)) | |
2775 | continue; | |
2776 | ||
2777 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2778 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2779 | power_domains->domain_use_count[power_domain]); |
2780 | } | |
2781 | } | |
2782 | ||
2783 | mutex_unlock(&power_domains->lock); | |
2784 | ||
2785 | return 0; | |
2786 | } | |
2787 | ||
b7cec66d DL |
2788 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2789 | { | |
2790 | struct drm_info_node *node = m->private; | |
2791 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 2792 | struct drm_i915_private *dev_priv = to_i915(dev); |
b7cec66d DL |
2793 | struct intel_csr *csr; |
2794 | ||
2795 | if (!HAS_CSR(dev)) { | |
2796 | seq_puts(m, "not supported\n"); | |
2797 | return 0; | |
2798 | } | |
2799 | ||
2800 | csr = &dev_priv->csr; | |
2801 | ||
6fb403de MK |
2802 | intel_runtime_pm_get(dev_priv); |
2803 | ||
b7cec66d DL |
2804 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2805 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2806 | ||
2807 | if (!csr->dmc_payload) | |
6fb403de | 2808 | goto out; |
b7cec66d DL |
2809 | |
2810 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2811 | CSR_VERSION_MINOR(csr->version)); | |
2812 | ||
8337206d DL |
2813 | if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { |
2814 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2815 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2816 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2817 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
16e11b99 MK |
2818 | } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) { |
2819 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2820 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2821 | } |
2822 | ||
6fb403de MK |
2823 | out: |
2824 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2825 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2826 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2827 | ||
8337206d DL |
2828 | intel_runtime_pm_put(dev_priv); |
2829 | ||
b7cec66d DL |
2830 | return 0; |
2831 | } | |
2832 | ||
53f5e3ca JB |
2833 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2834 | struct drm_display_mode *mode) | |
2835 | { | |
2836 | int i; | |
2837 | ||
2838 | for (i = 0; i < tabs; i++) | |
2839 | seq_putc(m, '\t'); | |
2840 | ||
2841 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2842 | mode->base.id, mode->name, | |
2843 | mode->vrefresh, mode->clock, | |
2844 | mode->hdisplay, mode->hsync_start, | |
2845 | mode->hsync_end, mode->htotal, | |
2846 | mode->vdisplay, mode->vsync_start, | |
2847 | mode->vsync_end, mode->vtotal, | |
2848 | mode->type, mode->flags); | |
2849 | } | |
2850 | ||
2851 | static void intel_encoder_info(struct seq_file *m, | |
2852 | struct intel_crtc *intel_crtc, | |
2853 | struct intel_encoder *intel_encoder) | |
2854 | { | |
9f25d007 | 2855 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2856 | struct drm_device *dev = node->minor->dev; |
2857 | struct drm_crtc *crtc = &intel_crtc->base; | |
2858 | struct intel_connector *intel_connector; | |
2859 | struct drm_encoder *encoder; | |
2860 | ||
2861 | encoder = &intel_encoder->base; | |
2862 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2863 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2864 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2865 | struct drm_connector *connector = &intel_connector->base; | |
2866 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2867 | connector->base.id, | |
c23cc417 | 2868 | connector->name, |
53f5e3ca JB |
2869 | drm_get_connector_status_name(connector->status)); |
2870 | if (connector->status == connector_status_connected) { | |
2871 | struct drm_display_mode *mode = &crtc->mode; | |
2872 | seq_printf(m, ", mode:\n"); | |
2873 | intel_seq_print_mode(m, 2, mode); | |
2874 | } else { | |
2875 | seq_putc(m, '\n'); | |
2876 | } | |
2877 | } | |
2878 | } | |
2879 | ||
2880 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2881 | { | |
9f25d007 | 2882 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2883 | struct drm_device *dev = node->minor->dev; |
2884 | struct drm_crtc *crtc = &intel_crtc->base; | |
2885 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2886 | struct drm_plane_state *plane_state = crtc->primary->state; |
2887 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2888 | |
23a48d53 | 2889 | if (fb) |
5aa8a937 | 2890 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2891 | fb->base.id, plane_state->src_x >> 16, |
2892 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2893 | else |
2894 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2895 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2896 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2897 | } | |
2898 | ||
2899 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2900 | { | |
2901 | struct drm_display_mode *mode = panel->fixed_mode; | |
2902 | ||
2903 | seq_printf(m, "\tfixed mode:\n"); | |
2904 | intel_seq_print_mode(m, 2, mode); | |
2905 | } | |
2906 | ||
2907 | static void intel_dp_info(struct seq_file *m, | |
2908 | struct intel_connector *intel_connector) | |
2909 | { | |
2910 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2911 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2912 | ||
2913 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2914 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
b6dabe3b | 2915 | if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) |
53f5e3ca JB |
2916 | intel_panel_info(m, &intel_connector->panel); |
2917 | } | |
2918 | ||
2919 | static void intel_hdmi_info(struct seq_file *m, | |
2920 | struct intel_connector *intel_connector) | |
2921 | { | |
2922 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2923 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2924 | ||
742f491d | 2925 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2926 | } |
2927 | ||
2928 | static void intel_lvds_info(struct seq_file *m, | |
2929 | struct intel_connector *intel_connector) | |
2930 | { | |
2931 | intel_panel_info(m, &intel_connector->panel); | |
2932 | } | |
2933 | ||
2934 | static void intel_connector_info(struct seq_file *m, | |
2935 | struct drm_connector *connector) | |
2936 | { | |
2937 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2938 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2939 | struct drm_display_mode *mode; |
53f5e3ca JB |
2940 | |
2941 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2942 | connector->base.id, connector->name, |
53f5e3ca JB |
2943 | drm_get_connector_status_name(connector->status)); |
2944 | if (connector->status == connector_status_connected) { | |
2945 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2946 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2947 | connector->display_info.width_mm, | |
2948 | connector->display_info.height_mm); | |
2949 | seq_printf(m, "\tsubpixel order: %s\n", | |
2950 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2951 | seq_printf(m, "\tCEA rev: %d\n", | |
2952 | connector->display_info.cea_rev); | |
2953 | } | |
ee648a74 ML |
2954 | |
2955 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
2956 | return; | |
2957 | ||
2958 | switch (connector->connector_type) { | |
2959 | case DRM_MODE_CONNECTOR_DisplayPort: | |
2960 | case DRM_MODE_CONNECTOR_eDP: | |
2961 | intel_dp_info(m, intel_connector); | |
2962 | break; | |
2963 | case DRM_MODE_CONNECTOR_LVDS: | |
2964 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
36cd7444 | 2965 | intel_lvds_info(m, intel_connector); |
ee648a74 ML |
2966 | break; |
2967 | case DRM_MODE_CONNECTOR_HDMIA: | |
2968 | if (intel_encoder->type == INTEL_OUTPUT_HDMI || | |
2969 | intel_encoder->type == INTEL_OUTPUT_UNKNOWN) | |
2970 | intel_hdmi_info(m, intel_connector); | |
2971 | break; | |
2972 | default: | |
2973 | break; | |
36cd7444 | 2974 | } |
53f5e3ca | 2975 | |
f103fc7d JB |
2976 | seq_printf(m, "\tmodes:\n"); |
2977 | list_for_each_entry(mode, &connector->modes, head) | |
2978 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2979 | } |
2980 | ||
065f2ec2 CW |
2981 | static bool cursor_active(struct drm_device *dev, int pipe) |
2982 | { | |
fac5e23e | 2983 | struct drm_i915_private *dev_priv = to_i915(dev); |
065f2ec2 CW |
2984 | u32 state; |
2985 | ||
2986 | if (IS_845G(dev) || IS_I865G(dev)) | |
0b87c24e | 2987 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 2988 | else |
5efb3e28 | 2989 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2990 | |
2991 | return state; | |
2992 | } | |
2993 | ||
2994 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2995 | { | |
fac5e23e | 2996 | struct drm_i915_private *dev_priv = to_i915(dev); |
065f2ec2 CW |
2997 | u32 pos; |
2998 | ||
5efb3e28 | 2999 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
3000 | |
3001 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
3002 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
3003 | *x = -*x; | |
3004 | ||
3005 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
3006 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
3007 | *y = -*y; | |
3008 | ||
3009 | return cursor_active(dev, pipe); | |
3010 | } | |
3011 | ||
3abc4e09 RF |
3012 | static const char *plane_type(enum drm_plane_type type) |
3013 | { | |
3014 | switch (type) { | |
3015 | case DRM_PLANE_TYPE_OVERLAY: | |
3016 | return "OVL"; | |
3017 | case DRM_PLANE_TYPE_PRIMARY: | |
3018 | return "PRI"; | |
3019 | case DRM_PLANE_TYPE_CURSOR: | |
3020 | return "CUR"; | |
3021 | /* | |
3022 | * Deliberately omitting default: to generate compiler warnings | |
3023 | * when a new drm_plane_type gets added. | |
3024 | */ | |
3025 | } | |
3026 | ||
3027 | return "unknown"; | |
3028 | } | |
3029 | ||
3030 | static const char *plane_rotation(unsigned int rotation) | |
3031 | { | |
3032 | static char buf[48]; | |
3033 | /* | |
3034 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3035 | * will print them all to visualize if the values are misused | |
3036 | */ | |
3037 | snprintf(buf, sizeof(buf), | |
3038 | "%s%s%s%s%s%s(0x%08x)", | |
31ad61e4 JL |
3039 | (rotation & DRM_ROTATE_0) ? "0 " : "", |
3040 | (rotation & DRM_ROTATE_90) ? "90 " : "", | |
3041 | (rotation & DRM_ROTATE_180) ? "180 " : "", | |
3042 | (rotation & DRM_ROTATE_270) ? "270 " : "", | |
3043 | (rotation & DRM_REFLECT_X) ? "FLIPX " : "", | |
3044 | (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", | |
3abc4e09 RF |
3045 | rotation); |
3046 | ||
3047 | return buf; | |
3048 | } | |
3049 | ||
3050 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3051 | { | |
3052 | struct drm_info_node *node = m->private; | |
3053 | struct drm_device *dev = node->minor->dev; | |
3054 | struct intel_plane *intel_plane; | |
3055 | ||
3056 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3057 | struct drm_plane_state *state; | |
3058 | struct drm_plane *plane = &intel_plane->base; | |
3059 | ||
3060 | if (!plane->state) { | |
3061 | seq_puts(m, "plane->state is NULL!\n"); | |
3062 | continue; | |
3063 | } | |
3064 | ||
3065 | state = plane->state; | |
3066 | ||
3067 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", | |
3068 | plane->base.id, | |
3069 | plane_type(intel_plane->base.type), | |
3070 | state->crtc_x, state->crtc_y, | |
3071 | state->crtc_w, state->crtc_h, | |
3072 | (state->src_x >> 16), | |
3073 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3074 | (state->src_y >> 16), | |
3075 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3076 | (state->src_w >> 16), | |
3077 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3078 | (state->src_h >> 16), | |
3079 | ((state->src_h & 0xffff) * 15625) >> 10, | |
3080 | state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A", | |
3081 | plane_rotation(state->rotation)); | |
3082 | } | |
3083 | } | |
3084 | ||
3085 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3086 | { | |
3087 | struct intel_crtc_state *pipe_config; | |
3088 | int num_scalers = intel_crtc->num_scalers; | |
3089 | int i; | |
3090 | ||
3091 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3092 | ||
3093 | /* Not all platformas have a scaler */ | |
3094 | if (num_scalers) { | |
3095 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3096 | num_scalers, | |
3097 | pipe_config->scaler_state.scaler_users, | |
3098 | pipe_config->scaler_state.scaler_id); | |
3099 | ||
3100 | for (i = 0; i < SKL_NUM_SCALERS; i++) { | |
3101 | struct intel_scaler *sc = | |
3102 | &pipe_config->scaler_state.scalers[i]; | |
3103 | ||
3104 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3105 | i, yesno(sc->in_use), sc->mode); | |
3106 | } | |
3107 | seq_puts(m, "\n"); | |
3108 | } else { | |
3109 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3110 | } | |
3111 | } | |
3112 | ||
53f5e3ca JB |
3113 | static int i915_display_info(struct seq_file *m, void *unused) |
3114 | { | |
9f25d007 | 3115 | struct drm_info_node *node = m->private; |
53f5e3ca | 3116 | struct drm_device *dev = node->minor->dev; |
fac5e23e | 3117 | struct drm_i915_private *dev_priv = to_i915(dev); |
065f2ec2 | 3118 | struct intel_crtc *crtc; |
53f5e3ca JB |
3119 | struct drm_connector *connector; |
3120 | ||
b0e5ddf3 | 3121 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3122 | drm_modeset_lock_all(dev); |
3123 | seq_printf(m, "CRTC info\n"); | |
3124 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3125 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3126 | bool active; |
f77076c9 | 3127 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3128 | int x, y; |
53f5e3ca | 3129 | |
f77076c9 ML |
3130 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3131 | ||
3abc4e09 | 3132 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3133 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3134 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3135 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3136 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3137 | ||
f77076c9 | 3138 | if (pipe_config->base.active) { |
065f2ec2 CW |
3139 | intel_crtc_info(m, crtc); |
3140 | ||
a23dc658 | 3141 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 3142 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3143 | yesno(crtc->cursor_base), |
3dd512fb MR |
3144 | x, y, crtc->base.cursor->state->crtc_w, |
3145 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3146 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3147 | intel_scaler_info(m, crtc); |
3148 | intel_plane_info(m, crtc); | |
a23dc658 | 3149 | } |
cace841c DV |
3150 | |
3151 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3152 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3153 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3154 | } |
3155 | ||
3156 | seq_printf(m, "\n"); | |
3157 | seq_printf(m, "Connector info\n"); | |
3158 | seq_printf(m, "--------------\n"); | |
3159 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3160 | intel_connector_info(m, connector); | |
3161 | } | |
3162 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3163 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3164 | |
3165 | return 0; | |
3166 | } | |
3167 | ||
e04934cf BW |
3168 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3169 | { | |
3170 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3171 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 3172 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 3173 | struct intel_engine_cs *engine; |
c1bb1145 | 3174 | int num_rings = INTEL_INFO(dev)->num_rings; |
c3232b18 DG |
3175 | enum intel_engine_id id; |
3176 | int j, ret; | |
e04934cf | 3177 | |
39df9190 | 3178 | if (!i915.semaphores) { |
e04934cf BW |
3179 | seq_puts(m, "Semaphores are disabled\n"); |
3180 | return 0; | |
3181 | } | |
3182 | ||
3183 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3184 | if (ret) | |
3185 | return ret; | |
03872064 | 3186 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
3187 | |
3188 | if (IS_BROADWELL(dev)) { | |
3189 | struct page *page; | |
3190 | uint64_t *seqno; | |
3191 | ||
3192 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
3193 | ||
3194 | seqno = (uint64_t *)kmap_atomic(page); | |
c3232b18 | 3195 | for_each_engine_id(engine, dev_priv, id) { |
e04934cf BW |
3196 | uint64_t offset; |
3197 | ||
e2f80391 | 3198 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3199 | |
3200 | seq_puts(m, " Last signal:"); | |
3201 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3202 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3203 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3204 | seqno[offset], offset * 8); | |
3205 | } | |
3206 | seq_putc(m, '\n'); | |
3207 | ||
3208 | seq_puts(m, " Last wait: "); | |
3209 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3210 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3211 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3212 | seqno[offset], offset * 8); | |
3213 | } | |
3214 | seq_putc(m, '\n'); | |
3215 | ||
3216 | } | |
3217 | kunmap_atomic(seqno); | |
3218 | } else { | |
3219 | seq_puts(m, " Last signal:"); | |
b4ac5afc | 3220 | for_each_engine(engine, dev_priv) |
e04934cf BW |
3221 | for (j = 0; j < num_rings; j++) |
3222 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3223 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3224 | seq_putc(m, '\n'); |
3225 | } | |
3226 | ||
3227 | seq_puts(m, "\nSync seqno:\n"); | |
b4ac5afc DG |
3228 | for_each_engine(engine, dev_priv) { |
3229 | for (j = 0; j < num_rings; j++) | |
e2f80391 TU |
3230 | seq_printf(m, " 0x%08x ", |
3231 | engine->semaphore.sync_seqno[j]); | |
e04934cf BW |
3232 | seq_putc(m, '\n'); |
3233 | } | |
3234 | seq_putc(m, '\n'); | |
3235 | ||
03872064 | 3236 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3237 | mutex_unlock(&dev->struct_mutex); |
3238 | return 0; | |
3239 | } | |
3240 | ||
728e29d7 DV |
3241 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3242 | { | |
3243 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3244 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 3245 | struct drm_i915_private *dev_priv = to_i915(dev); |
728e29d7 DV |
3246 | int i; |
3247 | ||
3248 | drm_modeset_lock_all(dev); | |
3249 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3250 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3251 | ||
3252 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd ML |
3253 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
3254 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); | |
728e29d7 | 3255 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3256 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3257 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3258 | pll->config.hw_state.dpll_md); | |
3259 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3260 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3261 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3262 | } |
3263 | drm_modeset_unlock_all(dev); | |
3264 | ||
3265 | return 0; | |
3266 | } | |
3267 | ||
1ed1ef9d | 3268 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3269 | { |
3270 | int i; | |
3271 | int ret; | |
e2f80391 | 3272 | struct intel_engine_cs *engine; |
888b5995 AS |
3273 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
3274 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 3275 | struct drm_i915_private *dev_priv = to_i915(dev); |
33136b06 | 3276 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3277 | enum intel_engine_id id; |
888b5995 | 3278 | |
888b5995 AS |
3279 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3280 | if (ret) | |
3281 | return ret; | |
3282 | ||
3283 | intel_runtime_pm_get(dev_priv); | |
3284 | ||
33136b06 | 3285 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
c3232b18 | 3286 | for_each_engine_id(engine, dev_priv, id) |
33136b06 | 3287 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3288 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3289 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3290 | i915_reg_t addr; |
3291 | u32 mask, value, read; | |
2fa60f6d | 3292 | bool ok; |
888b5995 | 3293 | |
33136b06 AS |
3294 | addr = workarounds->reg[i].addr; |
3295 | mask = workarounds->reg[i].mask; | |
3296 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3297 | read = I915_READ(addr); |
3298 | ok = (value & mask) == (read & mask); | |
3299 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3300 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3301 | } |
3302 | ||
3303 | intel_runtime_pm_put(dev_priv); | |
3304 | mutex_unlock(&dev->struct_mutex); | |
3305 | ||
3306 | return 0; | |
3307 | } | |
3308 | ||
c5511e44 DL |
3309 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3310 | { | |
3311 | struct drm_info_node *node = m->private; | |
3312 | struct drm_device *dev = node->minor->dev; | |
fac5e23e | 3313 | struct drm_i915_private *dev_priv = to_i915(dev); |
c5511e44 DL |
3314 | struct skl_ddb_allocation *ddb; |
3315 | struct skl_ddb_entry *entry; | |
3316 | enum pipe pipe; | |
3317 | int plane; | |
3318 | ||
2fcffe19 DL |
3319 | if (INTEL_INFO(dev)->gen < 9) |
3320 | return 0; | |
3321 | ||
c5511e44 DL |
3322 | drm_modeset_lock_all(dev); |
3323 | ||
3324 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3325 | ||
3326 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3327 | ||
3328 | for_each_pipe(dev_priv, pipe) { | |
3329 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3330 | ||
dd740780 | 3331 | for_each_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3332 | entry = &ddb->plane[pipe][plane]; |
3333 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3334 | entry->start, entry->end, | |
3335 | skl_ddb_entry_size(entry)); | |
3336 | } | |
3337 | ||
4969d33e | 3338 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3339 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3340 | entry->end, skl_ddb_entry_size(entry)); | |
3341 | } | |
3342 | ||
3343 | drm_modeset_unlock_all(dev); | |
3344 | ||
3345 | return 0; | |
3346 | } | |
3347 | ||
a54746e3 VK |
3348 | static void drrs_status_per_crtc(struct seq_file *m, |
3349 | struct drm_device *dev, struct intel_crtc *intel_crtc) | |
3350 | { | |
fac5e23e | 3351 | struct drm_i915_private *dev_priv = to_i915(dev); |
a54746e3 VK |
3352 | struct i915_drrs *drrs = &dev_priv->drrs; |
3353 | int vrefresh = 0; | |
26875fe5 | 3354 | struct drm_connector *connector; |
a54746e3 | 3355 | |
26875fe5 ML |
3356 | drm_for_each_connector(connector, dev) { |
3357 | if (connector->state->crtc != &intel_crtc->base) | |
3358 | continue; | |
3359 | ||
3360 | seq_printf(m, "%s:\n", connector->name); | |
a54746e3 VK |
3361 | } |
3362 | ||
3363 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3364 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3365 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3366 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3367 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3368 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3369 | else | |
3370 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3371 | ||
3372 | seq_puts(m, "\n\n"); | |
3373 | ||
f77076c9 | 3374 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3375 | struct intel_panel *panel; |
3376 | ||
3377 | mutex_lock(&drrs->mutex); | |
3378 | /* DRRS Supported */ | |
3379 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3380 | ||
3381 | /* disable_drrs() will make drrs->dp NULL */ | |
3382 | if (!drrs->dp) { | |
3383 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3384 | mutex_unlock(&drrs->mutex); | |
3385 | return; | |
3386 | } | |
3387 | ||
3388 | panel = &drrs->dp->attached_connector->panel; | |
3389 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3390 | drrs->busy_frontbuffer_bits); | |
3391 | ||
3392 | seq_puts(m, "\n\t\t"); | |
3393 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3394 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3395 | vrefresh = panel->fixed_mode->vrefresh; | |
3396 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3397 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3398 | vrefresh = panel->downclock_mode->vrefresh; | |
3399 | } else { | |
3400 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3401 | drrs->refresh_rate_type); | |
3402 | mutex_unlock(&drrs->mutex); | |
3403 | return; | |
3404 | } | |
3405 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3406 | ||
3407 | seq_puts(m, "\n\t\t"); | |
3408 | mutex_unlock(&drrs->mutex); | |
3409 | } else { | |
3410 | /* DRRS not supported. Print the VBT parameter*/ | |
3411 | seq_puts(m, "\tDRRS Supported : No"); | |
3412 | } | |
3413 | seq_puts(m, "\n"); | |
3414 | } | |
3415 | ||
3416 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3417 | { | |
3418 | struct drm_info_node *node = m->private; | |
3419 | struct drm_device *dev = node->minor->dev; | |
3420 | struct intel_crtc *intel_crtc; | |
3421 | int active_crtc_cnt = 0; | |
3422 | ||
26875fe5 | 3423 | drm_modeset_lock_all(dev); |
a54746e3 | 3424 | for_each_intel_crtc(dev, intel_crtc) { |
f77076c9 | 3425 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3426 | active_crtc_cnt++; |
3427 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3428 | ||
3429 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3430 | } | |
a54746e3 | 3431 | } |
26875fe5 | 3432 | drm_modeset_unlock_all(dev); |
a54746e3 VK |
3433 | |
3434 | if (!active_crtc_cnt) | |
3435 | seq_puts(m, "No active crtc found\n"); | |
3436 | ||
3437 | return 0; | |
3438 | } | |
3439 | ||
07144428 DL |
3440 | struct pipe_crc_info { |
3441 | const char *name; | |
3442 | struct drm_device *dev; | |
3443 | enum pipe pipe; | |
3444 | }; | |
3445 | ||
11bed958 DA |
3446 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3447 | { | |
3448 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3449 | struct drm_device *dev = node->minor->dev; | |
11bed958 DA |
3450 | struct intel_encoder *intel_encoder; |
3451 | struct intel_digital_port *intel_dig_port; | |
b6dabe3b ML |
3452 | struct drm_connector *connector; |
3453 | ||
11bed958 | 3454 | drm_modeset_lock_all(dev); |
b6dabe3b ML |
3455 | drm_for_each_connector(connector, dev) { |
3456 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
11bed958 | 3457 | continue; |
b6dabe3b ML |
3458 | |
3459 | intel_encoder = intel_attached_encoder(connector); | |
3460 | if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) | |
3461 | continue; | |
3462 | ||
3463 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
11bed958 DA |
3464 | if (!intel_dig_port->dp.can_mst) |
3465 | continue; | |
b6dabe3b | 3466 | |
40ae80cc JB |
3467 | seq_printf(m, "MST Source Port %c\n", |
3468 | port_name(intel_dig_port->port)); | |
11bed958 DA |
3469 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); |
3470 | } | |
3471 | drm_modeset_unlock_all(dev); | |
3472 | return 0; | |
3473 | } | |
3474 | ||
07144428 DL |
3475 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3476 | { | |
be5c7a90 | 3477 | struct pipe_crc_info *info = inode->i_private; |
fac5e23e | 3478 | struct drm_i915_private *dev_priv = to_i915(info->dev); |
be5c7a90 DL |
3479 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3480 | ||
7eb1c496 DV |
3481 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
3482 | return -ENODEV; | |
3483 | ||
d538bbdf DL |
3484 | spin_lock_irq(&pipe_crc->lock); |
3485 | ||
3486 | if (pipe_crc->opened) { | |
3487 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3488 | return -EBUSY; /* already open */ |
3489 | } | |
3490 | ||
d538bbdf | 3491 | pipe_crc->opened = true; |
07144428 DL |
3492 | filep->private_data = inode->i_private; |
3493 | ||
d538bbdf DL |
3494 | spin_unlock_irq(&pipe_crc->lock); |
3495 | ||
07144428 DL |
3496 | return 0; |
3497 | } | |
3498 | ||
3499 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3500 | { | |
be5c7a90 | 3501 | struct pipe_crc_info *info = inode->i_private; |
fac5e23e | 3502 | struct drm_i915_private *dev_priv = to_i915(info->dev); |
be5c7a90 DL |
3503 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3504 | ||
d538bbdf DL |
3505 | spin_lock_irq(&pipe_crc->lock); |
3506 | pipe_crc->opened = false; | |
3507 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3508 | |
07144428 DL |
3509 | return 0; |
3510 | } | |
3511 | ||
3512 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3513 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3514 | /* account for \'0' */ | |
3515 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3516 | ||
3517 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3518 | { |
d538bbdf DL |
3519 | assert_spin_locked(&pipe_crc->lock); |
3520 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3521 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3522 | } |
3523 | ||
3524 | static ssize_t | |
3525 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3526 | loff_t *pos) | |
3527 | { | |
3528 | struct pipe_crc_info *info = filep->private_data; | |
3529 | struct drm_device *dev = info->dev; | |
fac5e23e | 3530 | struct drm_i915_private *dev_priv = to_i915(dev); |
07144428 DL |
3531 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; |
3532 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3533 | int n_entries; |
07144428 DL |
3534 | ssize_t bytes_read; |
3535 | ||
3536 | /* | |
3537 | * Don't allow user space to provide buffers not big enough to hold | |
3538 | * a line of data. | |
3539 | */ | |
3540 | if (count < PIPE_CRC_LINE_LEN) | |
3541 | return -EINVAL; | |
3542 | ||
3543 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3544 | return 0; |
07144428 DL |
3545 | |
3546 | /* nothing to read */ | |
d538bbdf | 3547 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3548 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3549 | int ret; |
3550 | ||
3551 | if (filep->f_flags & O_NONBLOCK) { | |
3552 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3553 | return -EAGAIN; |
d538bbdf | 3554 | } |
07144428 | 3555 | |
d538bbdf DL |
3556 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3557 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3558 | if (ret) { | |
3559 | spin_unlock_irq(&pipe_crc->lock); | |
3560 | return ret; | |
3561 | } | |
8bf1e9f1 SH |
3562 | } |
3563 | ||
07144428 | 3564 | /* We now have one or more entries to read */ |
9ad6d99f | 3565 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3566 | |
07144428 | 3567 | bytes_read = 0; |
9ad6d99f VS |
3568 | while (n_entries > 0) { |
3569 | struct intel_pipe_crc_entry *entry = | |
3570 | &pipe_crc->entries[pipe_crc->tail]; | |
8bf1e9f1 | 3571 | |
9ad6d99f VS |
3572 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3573 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3574 | break; | |
3575 | ||
3576 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3577 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3578 | ||
07144428 DL |
3579 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3580 | "%8u %8x %8x %8x %8x %8x\n", | |
3581 | entry->frame, entry->crc[0], | |
3582 | entry->crc[1], entry->crc[2], | |
3583 | entry->crc[3], entry->crc[4]); | |
3584 | ||
9ad6d99f VS |
3585 | spin_unlock_irq(&pipe_crc->lock); |
3586 | ||
4e9121e6 | 3587 | if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN)) |
07144428 | 3588 | return -EFAULT; |
b2c88f5b | 3589 | |
9ad6d99f VS |
3590 | user_buf += PIPE_CRC_LINE_LEN; |
3591 | n_entries--; | |
3592 | ||
3593 | spin_lock_irq(&pipe_crc->lock); | |
3594 | } | |
8bf1e9f1 | 3595 | |
d538bbdf DL |
3596 | spin_unlock_irq(&pipe_crc->lock); |
3597 | ||
07144428 DL |
3598 | return bytes_read; |
3599 | } | |
3600 | ||
3601 | static const struct file_operations i915_pipe_crc_fops = { | |
3602 | .owner = THIS_MODULE, | |
3603 | .open = i915_pipe_crc_open, | |
3604 | .read = i915_pipe_crc_read, | |
3605 | .release = i915_pipe_crc_release, | |
3606 | }; | |
3607 | ||
3608 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3609 | { | |
3610 | .name = "i915_pipe_A_crc", | |
3611 | .pipe = PIPE_A, | |
3612 | }, | |
3613 | { | |
3614 | .name = "i915_pipe_B_crc", | |
3615 | .pipe = PIPE_B, | |
3616 | }, | |
3617 | { | |
3618 | .name = "i915_pipe_C_crc", | |
3619 | .pipe = PIPE_C, | |
3620 | }, | |
3621 | }; | |
3622 | ||
3623 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3624 | enum pipe pipe) | |
3625 | { | |
3626 | struct drm_device *dev = minor->dev; | |
3627 | struct dentry *ent; | |
3628 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3629 | ||
3630 | info->dev = dev; | |
3631 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
3632 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3633 | if (!ent) |
3634 | return -ENOMEM; | |
07144428 DL |
3635 | |
3636 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3637 | } |
3638 | ||
e8dfcf78 | 3639 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3640 | "none", |
3641 | "plane1", | |
3642 | "plane2", | |
3643 | "pf", | |
5b3a856b | 3644 | "pipe", |
3d099a05 DV |
3645 | "TV", |
3646 | "DP-B", | |
3647 | "DP-C", | |
3648 | "DP-D", | |
46a19188 | 3649 | "auto", |
926321d5 DV |
3650 | }; |
3651 | ||
3652 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3653 | { | |
3654 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3655 | return pipe_crc_sources[source]; | |
3656 | } | |
3657 | ||
bd9db02f | 3658 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
3659 | { |
3660 | struct drm_device *dev = m->private; | |
fac5e23e | 3661 | struct drm_i915_private *dev_priv = to_i915(dev); |
926321d5 DV |
3662 | int i; |
3663 | ||
3664 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3665 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3666 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3667 | ||
3668 | return 0; | |
3669 | } | |
3670 | ||
bd9db02f | 3671 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
3672 | { |
3673 | struct drm_device *dev = inode->i_private; | |
3674 | ||
bd9db02f | 3675 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
3676 | } |
3677 | ||
46a19188 | 3678 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3679 | uint32_t *val) |
3680 | { | |
46a19188 DV |
3681 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3682 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3683 | ||
3684 | switch (*source) { | |
52f843f6 DV |
3685 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3686 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3687 | break; | |
3688 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3689 | *val = 0; | |
3690 | break; | |
3691 | default: | |
3692 | return -EINVAL; | |
3693 | } | |
3694 | ||
3695 | return 0; | |
3696 | } | |
3697 | ||
46a19188 DV |
3698 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
3699 | enum intel_pipe_crc_source *source) | |
3700 | { | |
3701 | struct intel_encoder *encoder; | |
3702 | struct intel_crtc *crtc; | |
26756809 | 3703 | struct intel_digital_port *dig_port; |
46a19188 DV |
3704 | int ret = 0; |
3705 | ||
3706 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3707 | ||
6e9f798d | 3708 | drm_modeset_lock_all(dev); |
b2784e15 | 3709 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3710 | if (!encoder->base.crtc) |
3711 | continue; | |
3712 | ||
3713 | crtc = to_intel_crtc(encoder->base.crtc); | |
3714 | ||
3715 | if (crtc->pipe != pipe) | |
3716 | continue; | |
3717 | ||
3718 | switch (encoder->type) { | |
3719 | case INTEL_OUTPUT_TVOUT: | |
3720 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3721 | break; | |
cca0502b | 3722 | case INTEL_OUTPUT_DP: |
46a19188 | 3723 | case INTEL_OUTPUT_EDP: |
26756809 DV |
3724 | dig_port = enc_to_dig_port(&encoder->base); |
3725 | switch (dig_port->port) { | |
3726 | case PORT_B: | |
3727 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3728 | break; | |
3729 | case PORT_C: | |
3730 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3731 | break; | |
3732 | case PORT_D: | |
3733 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3734 | break; | |
3735 | default: | |
3736 | WARN(1, "nonexisting DP port %c\n", | |
3737 | port_name(dig_port->port)); | |
3738 | break; | |
3739 | } | |
46a19188 | 3740 | break; |
6847d71b PZ |
3741 | default: |
3742 | break; | |
46a19188 DV |
3743 | } |
3744 | } | |
6e9f798d | 3745 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3746 | |
3747 | return ret; | |
3748 | } | |
3749 | ||
3750 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
3751 | enum pipe pipe, | |
3752 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3753 | uint32_t *val) |
3754 | { | |
fac5e23e | 3755 | struct drm_i915_private *dev_priv = to_i915(dev); |
8d2f24ca DV |
3756 | bool need_stable_symbols = false; |
3757 | ||
46a19188 DV |
3758 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3759 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3760 | if (ret) | |
3761 | return ret; | |
3762 | } | |
3763 | ||
3764 | switch (*source) { | |
7ac0129b DV |
3765 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3766 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3767 | break; | |
3768 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3769 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3770 | need_stable_symbols = true; |
7ac0129b DV |
3771 | break; |
3772 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3773 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3774 | need_stable_symbols = true; |
7ac0129b | 3775 | break; |
2be57922 VS |
3776 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
3777 | if (!IS_CHERRYVIEW(dev)) | |
3778 | return -EINVAL; | |
3779 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3780 | need_stable_symbols = true; | |
3781 | break; | |
7ac0129b DV |
3782 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3783 | *val = 0; | |
3784 | break; | |
3785 | default: | |
3786 | return -EINVAL; | |
3787 | } | |
3788 | ||
8d2f24ca DV |
3789 | /* |
3790 | * When the pipe CRC tap point is after the transcoders we need | |
3791 | * to tweak symbol-level features to produce a deterministic series of | |
3792 | * symbols for a given frame. We need to reset those features only once | |
3793 | * a frame (instead of every nth symbol): | |
3794 | * - DC-balance: used to ensure a better clock recovery from the data | |
3795 | * link (SDVO) | |
3796 | * - DisplayPort scrambling: used for EMI reduction | |
3797 | */ | |
3798 | if (need_stable_symbols) { | |
3799 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3800 | ||
8d2f24ca | 3801 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3802 | switch (pipe) { |
3803 | case PIPE_A: | |
8d2f24ca | 3804 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3805 | break; |
3806 | case PIPE_B: | |
8d2f24ca | 3807 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3808 | break; |
3809 | case PIPE_C: | |
3810 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3811 | break; | |
3812 | default: | |
3813 | return -EINVAL; | |
3814 | } | |
8d2f24ca DV |
3815 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3816 | } | |
3817 | ||
7ac0129b DV |
3818 | return 0; |
3819 | } | |
3820 | ||
4b79ebf7 | 3821 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
3822 | enum pipe pipe, |
3823 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3824 | uint32_t *val) |
3825 | { | |
fac5e23e | 3826 | struct drm_i915_private *dev_priv = to_i915(dev); |
84093603 DV |
3827 | bool need_stable_symbols = false; |
3828 | ||
46a19188 DV |
3829 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3830 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3831 | if (ret) | |
3832 | return ret; | |
3833 | } | |
3834 | ||
3835 | switch (*source) { | |
4b79ebf7 DV |
3836 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3837 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3838 | break; | |
3839 | case INTEL_PIPE_CRC_SOURCE_TV: | |
3840 | if (!SUPPORTS_TV(dev)) | |
3841 | return -EINVAL; | |
3842 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3843 | break; | |
3844 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3845 | if (!IS_G4X(dev)) | |
3846 | return -EINVAL; | |
3847 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3848 | need_stable_symbols = true; |
4b79ebf7 DV |
3849 | break; |
3850 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3851 | if (!IS_G4X(dev)) | |
3852 | return -EINVAL; | |
3853 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3854 | need_stable_symbols = true; |
4b79ebf7 DV |
3855 | break; |
3856 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
3857 | if (!IS_G4X(dev)) | |
3858 | return -EINVAL; | |
3859 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3860 | need_stable_symbols = true; |
4b79ebf7 DV |
3861 | break; |
3862 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3863 | *val = 0; | |
3864 | break; | |
3865 | default: | |
3866 | return -EINVAL; | |
3867 | } | |
3868 | ||
84093603 DV |
3869 | /* |
3870 | * When the pipe CRC tap point is after the transcoders we need | |
3871 | * to tweak symbol-level features to produce a deterministic series of | |
3872 | * symbols for a given frame. We need to reset those features only once | |
3873 | * a frame (instead of every nth symbol): | |
3874 | * - DC-balance: used to ensure a better clock recovery from the data | |
3875 | * link (SDVO) | |
3876 | * - DisplayPort scrambling: used for EMI reduction | |
3877 | */ | |
3878 | if (need_stable_symbols) { | |
3879 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3880 | ||
3881 | WARN_ON(!IS_G4X(dev)); | |
3882 | ||
3883 | I915_WRITE(PORT_DFT_I9XX, | |
3884 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3885 | ||
3886 | if (pipe == PIPE_A) | |
3887 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3888 | else | |
3889 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3890 | ||
3891 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3892 | } | |
3893 | ||
4b79ebf7 DV |
3894 | return 0; |
3895 | } | |
3896 | ||
8d2f24ca DV |
3897 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
3898 | enum pipe pipe) | |
3899 | { | |
fac5e23e | 3900 | struct drm_i915_private *dev_priv = to_i915(dev); |
8d2f24ca DV |
3901 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
3902 | ||
eb736679 VS |
3903 | switch (pipe) { |
3904 | case PIPE_A: | |
8d2f24ca | 3905 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3906 | break; |
3907 | case PIPE_B: | |
8d2f24ca | 3908 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3909 | break; |
3910 | case PIPE_C: | |
3911 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3912 | break; | |
3913 | default: | |
3914 | return; | |
3915 | } | |
8d2f24ca DV |
3916 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3917 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3918 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3919 | ||
3920 | } | |
3921 | ||
84093603 DV |
3922 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
3923 | enum pipe pipe) | |
3924 | { | |
fac5e23e | 3925 | struct drm_i915_private *dev_priv = to_i915(dev); |
84093603 DV |
3926 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); |
3927 | ||
3928 | if (pipe == PIPE_A) | |
3929 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3930 | else | |
3931 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3932 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3933 | ||
3934 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3935 | I915_WRITE(PORT_DFT_I9XX, | |
3936 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3937 | } | |
3938 | } | |
3939 | ||
46a19188 | 3940 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3941 | uint32_t *val) |
3942 | { | |
46a19188 DV |
3943 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3944 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3945 | ||
3946 | switch (*source) { | |
5b3a856b DV |
3947 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3948 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
3949 | break; | |
3950 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3951 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
3952 | break; | |
5b3a856b DV |
3953 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3954 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
3955 | break; | |
3d099a05 | 3956 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3957 | *val = 0; |
3958 | break; | |
3d099a05 DV |
3959 | default: |
3960 | return -EINVAL; | |
5b3a856b DV |
3961 | } |
3962 | ||
3963 | return 0; | |
3964 | } | |
3965 | ||
c4e2d043 | 3966 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable) |
fabf6e51 | 3967 | { |
fac5e23e | 3968 | struct drm_i915_private *dev_priv = to_i915(dev); |
fabf6e51 DV |
3969 | struct intel_crtc *crtc = |
3970 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 3971 | struct intel_crtc_state *pipe_config; |
c4e2d043 ML |
3972 | struct drm_atomic_state *state; |
3973 | int ret = 0; | |
fabf6e51 DV |
3974 | |
3975 | drm_modeset_lock_all(dev); | |
c4e2d043 ML |
3976 | state = drm_atomic_state_alloc(dev); |
3977 | if (!state) { | |
3978 | ret = -ENOMEM; | |
3979 | goto out; | |
fabf6e51 | 3980 | } |
fabf6e51 | 3981 | |
c4e2d043 ML |
3982 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
3983 | pipe_config = intel_atomic_get_crtc_state(state, crtc); | |
3984 | if (IS_ERR(pipe_config)) { | |
3985 | ret = PTR_ERR(pipe_config); | |
3986 | goto out; | |
3987 | } | |
fabf6e51 | 3988 | |
c4e2d043 ML |
3989 | pipe_config->pch_pfit.force_thru = enable; |
3990 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
3991 | pipe_config->pch_pfit.enabled != enable) | |
3992 | pipe_config->base.connectors_changed = true; | |
1b509259 | 3993 | |
c4e2d043 ML |
3994 | ret = drm_atomic_commit(state); |
3995 | out: | |
fabf6e51 | 3996 | drm_modeset_unlock_all(dev); |
c4e2d043 ML |
3997 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
3998 | if (ret) | |
3999 | drm_atomic_state_free(state); | |
fabf6e51 DV |
4000 | } |
4001 | ||
4002 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
4003 | enum pipe pipe, | |
4004 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
4005 | uint32_t *val) |
4006 | { | |
46a19188 DV |
4007 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
4008 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
4009 | ||
4010 | switch (*source) { | |
5b3a856b DV |
4011 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
4012 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
4013 | break; | |
4014 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
4015 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
4016 | break; | |
4017 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 | 4018 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4019 | hsw_trans_edp_pipe_A_crc_wa(dev, true); |
fabf6e51 | 4020 | |
5b3a856b DV |
4021 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
4022 | break; | |
3d099a05 | 4023 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
4024 | *val = 0; |
4025 | break; | |
3d099a05 DV |
4026 | default: |
4027 | return -EINVAL; | |
5b3a856b DV |
4028 | } |
4029 | ||
4030 | return 0; | |
4031 | } | |
4032 | ||
926321d5 DV |
4033 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
4034 | enum intel_pipe_crc_source source) | |
4035 | { | |
fac5e23e | 4036 | struct drm_i915_private *dev_priv = to_i915(dev); |
cc3da175 | 4037 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
8c740dce PZ |
4038 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
4039 | pipe)); | |
e129649b | 4040 | enum intel_display_power_domain power_domain; |
432f3342 | 4041 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 4042 | int ret; |
926321d5 | 4043 | |
cc3da175 DL |
4044 | if (pipe_crc->source == source) |
4045 | return 0; | |
4046 | ||
ae676fcd DL |
4047 | /* forbid changing the source without going back to 'none' */ |
4048 | if (pipe_crc->source && source) | |
4049 | return -EINVAL; | |
4050 | ||
e129649b ID |
4051 | power_domain = POWER_DOMAIN_PIPE(pipe); |
4052 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9d8b0588 DV |
4053 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
4054 | return -EIO; | |
4055 | } | |
4056 | ||
52f843f6 | 4057 | if (IS_GEN2(dev)) |
46a19188 | 4058 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 4059 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 4060 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
666a4537 | 4061 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
fabf6e51 | 4062 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 4063 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 4064 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 4065 | else |
fabf6e51 | 4066 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
4067 | |
4068 | if (ret != 0) | |
e129649b | 4069 | goto out; |
5b3a856b | 4070 | |
4b584369 DL |
4071 | /* none -> real source transition */ |
4072 | if (source) { | |
4252fbc3 VS |
4073 | struct intel_pipe_crc_entry *entries; |
4074 | ||
7cd6ccff DL |
4075 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
4076 | pipe_name(pipe), pipe_crc_source_name(source)); | |
4077 | ||
3cf54b34 VS |
4078 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
4079 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 | 4080 | GFP_KERNEL); |
e129649b ID |
4081 | if (!entries) { |
4082 | ret = -ENOMEM; | |
4083 | goto out; | |
4084 | } | |
e5f75aca | 4085 | |
8c740dce PZ |
4086 | /* |
4087 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
4088 | * enabled and disabled dynamically based on package C states, | |
4089 | * user space can't make reliable use of the CRCs, so let's just | |
4090 | * completely disable it. | |
4091 | */ | |
4092 | hsw_disable_ips(crtc); | |
4093 | ||
d538bbdf | 4094 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 4095 | kfree(pipe_crc->entries); |
4252fbc3 | 4096 | pipe_crc->entries = entries; |
d538bbdf DL |
4097 | pipe_crc->head = 0; |
4098 | pipe_crc->tail = 0; | |
4099 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
4100 | } |
4101 | ||
cc3da175 | 4102 | pipe_crc->source = source; |
926321d5 | 4103 | |
926321d5 DV |
4104 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
4105 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
4106 | ||
e5f75aca DL |
4107 | /* real source -> none transition */ |
4108 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 4109 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
4110 | struct intel_crtc *crtc = |
4111 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 4112 | |
7cd6ccff DL |
4113 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
4114 | pipe_name(pipe)); | |
4115 | ||
a33d7105 | 4116 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 4117 | if (crtc->base.state->active) |
a33d7105 DV |
4118 | intel_wait_for_vblank(dev, pipe); |
4119 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 4120 | |
d538bbdf DL |
4121 | spin_lock_irq(&pipe_crc->lock); |
4122 | entries = pipe_crc->entries; | |
e5f75aca | 4123 | pipe_crc->entries = NULL; |
9ad6d99f VS |
4124 | pipe_crc->head = 0; |
4125 | pipe_crc->tail = 0; | |
d538bbdf DL |
4126 | spin_unlock_irq(&pipe_crc->lock); |
4127 | ||
4128 | kfree(entries); | |
84093603 DV |
4129 | |
4130 | if (IS_G4X(dev)) | |
4131 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
666a4537 | 4132 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
8d2f24ca | 4133 | vlv_undo_pipe_scramble_reset(dev, pipe); |
fabf6e51 | 4134 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4135 | hsw_trans_edp_pipe_A_crc_wa(dev, false); |
8c740dce PZ |
4136 | |
4137 | hsw_enable_ips(crtc); | |
e5f75aca DL |
4138 | } |
4139 | ||
e129649b ID |
4140 | ret = 0; |
4141 | ||
4142 | out: | |
4143 | intel_display_power_put(dev_priv, power_domain); | |
4144 | ||
4145 | return ret; | |
926321d5 DV |
4146 | } |
4147 | ||
4148 | /* | |
4149 | * Parse pipe CRC command strings: | |
b94dec87 DL |
4150 | * command: wsp* object wsp+ name wsp+ source wsp* |
4151 | * object: 'pipe' | |
4152 | * name: (A | B | C) | |
926321d5 DV |
4153 | * source: (none | plane1 | plane2 | pf) |
4154 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
4155 | * | |
4156 | * eg.: | |
b94dec87 DL |
4157 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
4158 | * "pipe A none" -> Stop CRC | |
926321d5 | 4159 | */ |
bd9db02f | 4160 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
4161 | { |
4162 | int n_words = 0; | |
4163 | ||
4164 | while (*buf) { | |
4165 | char *end; | |
4166 | ||
4167 | /* skip leading white space */ | |
4168 | buf = skip_spaces(buf); | |
4169 | if (!*buf) | |
4170 | break; /* end of buffer */ | |
4171 | ||
4172 | /* find end of word */ | |
4173 | for (end = buf; *end && !isspace(*end); end++) | |
4174 | ; | |
4175 | ||
4176 | if (n_words == max_words) { | |
4177 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
4178 | max_words); | |
4179 | return -EINVAL; /* ran out of words[] before bytes */ | |
4180 | } | |
4181 | ||
4182 | if (*end) | |
4183 | *end++ = '\0'; | |
4184 | words[n_words++] = buf; | |
4185 | buf = end; | |
4186 | } | |
4187 | ||
4188 | return n_words; | |
4189 | } | |
4190 | ||
b94dec87 DL |
4191 | enum intel_pipe_crc_object { |
4192 | PIPE_CRC_OBJECT_PIPE, | |
4193 | }; | |
4194 | ||
e8dfcf78 | 4195 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
4196 | "pipe", |
4197 | }; | |
4198 | ||
4199 | static int | |
bd9db02f | 4200 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
4201 | { |
4202 | int i; | |
4203 | ||
4204 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
4205 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 4206 | *o = i; |
b94dec87 DL |
4207 | return 0; |
4208 | } | |
4209 | ||
4210 | return -EINVAL; | |
4211 | } | |
4212 | ||
bd9db02f | 4213 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
4214 | { |
4215 | const char name = buf[0]; | |
4216 | ||
4217 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
4218 | return -EINVAL; | |
4219 | ||
4220 | *pipe = name - 'A'; | |
4221 | ||
4222 | return 0; | |
4223 | } | |
4224 | ||
4225 | static int | |
bd9db02f | 4226 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
4227 | { |
4228 | int i; | |
4229 | ||
4230 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
4231 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 4232 | *s = i; |
926321d5 DV |
4233 | return 0; |
4234 | } | |
4235 | ||
4236 | return -EINVAL; | |
4237 | } | |
4238 | ||
bd9db02f | 4239 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 4240 | { |
b94dec87 | 4241 | #define N_WORDS 3 |
926321d5 | 4242 | int n_words; |
b94dec87 | 4243 | char *words[N_WORDS]; |
926321d5 | 4244 | enum pipe pipe; |
b94dec87 | 4245 | enum intel_pipe_crc_object object; |
926321d5 DV |
4246 | enum intel_pipe_crc_source source; |
4247 | ||
bd9db02f | 4248 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
4249 | if (n_words != N_WORDS) { |
4250 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
4251 | N_WORDS); | |
4252 | return -EINVAL; | |
4253 | } | |
4254 | ||
bd9db02f | 4255 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 4256 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
4257 | return -EINVAL; |
4258 | } | |
4259 | ||
bd9db02f | 4260 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 4261 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
4262 | return -EINVAL; |
4263 | } | |
4264 | ||
bd9db02f | 4265 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 4266 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
4267 | return -EINVAL; |
4268 | } | |
4269 | ||
4270 | return pipe_crc_set_source(dev, pipe, source); | |
4271 | } | |
4272 | ||
bd9db02f DL |
4273 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
4274 | size_t len, loff_t *offp) | |
926321d5 DV |
4275 | { |
4276 | struct seq_file *m = file->private_data; | |
4277 | struct drm_device *dev = m->private; | |
4278 | char *tmpbuf; | |
4279 | int ret; | |
4280 | ||
4281 | if (len == 0) | |
4282 | return 0; | |
4283 | ||
4284 | if (len > PAGE_SIZE - 1) { | |
4285 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
4286 | PAGE_SIZE); | |
4287 | return -E2BIG; | |
4288 | } | |
4289 | ||
4290 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
4291 | if (!tmpbuf) | |
4292 | return -ENOMEM; | |
4293 | ||
4294 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
4295 | ret = -EFAULT; | |
4296 | goto out; | |
4297 | } | |
4298 | tmpbuf[len] = '\0'; | |
4299 | ||
bd9db02f | 4300 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
4301 | |
4302 | out: | |
4303 | kfree(tmpbuf); | |
4304 | if (ret < 0) | |
4305 | return ret; | |
4306 | ||
4307 | *offp += len; | |
4308 | return len; | |
4309 | } | |
4310 | ||
bd9db02f | 4311 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4312 | .owner = THIS_MODULE, |
bd9db02f | 4313 | .open = display_crc_ctl_open, |
926321d5 DV |
4314 | .read = seq_read, |
4315 | .llseek = seq_lseek, | |
4316 | .release = single_release, | |
bd9db02f | 4317 | .write = display_crc_ctl_write |
926321d5 DV |
4318 | }; |
4319 | ||
eb3394fa TP |
4320 | static ssize_t i915_displayport_test_active_write(struct file *file, |
4321 | const char __user *ubuf, | |
4322 | size_t len, loff_t *offp) | |
4323 | { | |
4324 | char *input_buffer; | |
4325 | int status = 0; | |
eb3394fa TP |
4326 | struct drm_device *dev; |
4327 | struct drm_connector *connector; | |
4328 | struct list_head *connector_list; | |
4329 | struct intel_dp *intel_dp; | |
4330 | int val = 0; | |
4331 | ||
9aaffa34 | 4332 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 4333 | |
eb3394fa TP |
4334 | connector_list = &dev->mode_config.connector_list; |
4335 | ||
4336 | if (len == 0) | |
4337 | return 0; | |
4338 | ||
4339 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4340 | if (!input_buffer) | |
4341 | return -ENOMEM; | |
4342 | ||
4343 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4344 | status = -EFAULT; | |
4345 | goto out; | |
4346 | } | |
4347 | ||
4348 | input_buffer[len] = '\0'; | |
4349 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4350 | ||
4351 | list_for_each_entry(connector, connector_list, head) { | |
4352 | ||
4353 | if (connector->connector_type != | |
4354 | DRM_MODE_CONNECTOR_DisplayPort) | |
4355 | continue; | |
4356 | ||
b8bb08ec | 4357 | if (connector->status == connector_status_connected && |
eb3394fa TP |
4358 | connector->encoder != NULL) { |
4359 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4360 | status = kstrtoint(input_buffer, 10, &val); | |
4361 | if (status < 0) | |
4362 | goto out; | |
4363 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4364 | /* To prevent erroneous activation of the compliance | |
4365 | * testing code, only accept an actual value of 1 here | |
4366 | */ | |
4367 | if (val == 1) | |
4368 | intel_dp->compliance_test_active = 1; | |
4369 | else | |
4370 | intel_dp->compliance_test_active = 0; | |
4371 | } | |
4372 | } | |
4373 | out: | |
4374 | kfree(input_buffer); | |
4375 | if (status < 0) | |
4376 | return status; | |
4377 | ||
4378 | *offp += len; | |
4379 | return len; | |
4380 | } | |
4381 | ||
4382 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4383 | { | |
4384 | struct drm_device *dev = m->private; | |
4385 | struct drm_connector *connector; | |
4386 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4387 | struct intel_dp *intel_dp; | |
4388 | ||
eb3394fa TP |
4389 | list_for_each_entry(connector, connector_list, head) { |
4390 | ||
4391 | if (connector->connector_type != | |
4392 | DRM_MODE_CONNECTOR_DisplayPort) | |
4393 | continue; | |
4394 | ||
4395 | if (connector->status == connector_status_connected && | |
4396 | connector->encoder != NULL) { | |
4397 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4398 | if (intel_dp->compliance_test_active) | |
4399 | seq_puts(m, "1"); | |
4400 | else | |
4401 | seq_puts(m, "0"); | |
4402 | } else | |
4403 | seq_puts(m, "0"); | |
4404 | } | |
4405 | ||
4406 | return 0; | |
4407 | } | |
4408 | ||
4409 | static int i915_displayport_test_active_open(struct inode *inode, | |
4410 | struct file *file) | |
4411 | { | |
4412 | struct drm_device *dev = inode->i_private; | |
4413 | ||
4414 | return single_open(file, i915_displayport_test_active_show, dev); | |
4415 | } | |
4416 | ||
4417 | static const struct file_operations i915_displayport_test_active_fops = { | |
4418 | .owner = THIS_MODULE, | |
4419 | .open = i915_displayport_test_active_open, | |
4420 | .read = seq_read, | |
4421 | .llseek = seq_lseek, | |
4422 | .release = single_release, | |
4423 | .write = i915_displayport_test_active_write | |
4424 | }; | |
4425 | ||
4426 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4427 | { | |
4428 | struct drm_device *dev = m->private; | |
4429 | struct drm_connector *connector; | |
4430 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4431 | struct intel_dp *intel_dp; | |
4432 | ||
eb3394fa TP |
4433 | list_for_each_entry(connector, connector_list, head) { |
4434 | ||
4435 | if (connector->connector_type != | |
4436 | DRM_MODE_CONNECTOR_DisplayPort) | |
4437 | continue; | |
4438 | ||
4439 | if (connector->status == connector_status_connected && | |
4440 | connector->encoder != NULL) { | |
4441 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4442 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4443 | } else | |
4444 | seq_puts(m, "0"); | |
4445 | } | |
4446 | ||
4447 | return 0; | |
4448 | } | |
4449 | static int i915_displayport_test_data_open(struct inode *inode, | |
4450 | struct file *file) | |
4451 | { | |
4452 | struct drm_device *dev = inode->i_private; | |
4453 | ||
4454 | return single_open(file, i915_displayport_test_data_show, dev); | |
4455 | } | |
4456 | ||
4457 | static const struct file_operations i915_displayport_test_data_fops = { | |
4458 | .owner = THIS_MODULE, | |
4459 | .open = i915_displayport_test_data_open, | |
4460 | .read = seq_read, | |
4461 | .llseek = seq_lseek, | |
4462 | .release = single_release | |
4463 | }; | |
4464 | ||
4465 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4466 | { | |
4467 | struct drm_device *dev = m->private; | |
4468 | struct drm_connector *connector; | |
4469 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4470 | struct intel_dp *intel_dp; | |
4471 | ||
eb3394fa TP |
4472 | list_for_each_entry(connector, connector_list, head) { |
4473 | ||
4474 | if (connector->connector_type != | |
4475 | DRM_MODE_CONNECTOR_DisplayPort) | |
4476 | continue; | |
4477 | ||
4478 | if (connector->status == connector_status_connected && | |
4479 | connector->encoder != NULL) { | |
4480 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4481 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4482 | } else | |
4483 | seq_puts(m, "0"); | |
4484 | } | |
4485 | ||
4486 | return 0; | |
4487 | } | |
4488 | ||
4489 | static int i915_displayport_test_type_open(struct inode *inode, | |
4490 | struct file *file) | |
4491 | { | |
4492 | struct drm_device *dev = inode->i_private; | |
4493 | ||
4494 | return single_open(file, i915_displayport_test_type_show, dev); | |
4495 | } | |
4496 | ||
4497 | static const struct file_operations i915_displayport_test_type_fops = { | |
4498 | .owner = THIS_MODULE, | |
4499 | .open = i915_displayport_test_type_open, | |
4500 | .read = seq_read, | |
4501 | .llseek = seq_lseek, | |
4502 | .release = single_release | |
4503 | }; | |
4504 | ||
97e94b22 | 4505 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 VS |
4506 | { |
4507 | struct drm_device *dev = m->private; | |
369a1342 | 4508 | int level; |
de38b95c VS |
4509 | int num_levels; |
4510 | ||
4511 | if (IS_CHERRYVIEW(dev)) | |
4512 | num_levels = 3; | |
4513 | else if (IS_VALLEYVIEW(dev)) | |
4514 | num_levels = 1; | |
4515 | else | |
4516 | num_levels = ilk_wm_max_level(dev) + 1; | |
369a1342 VS |
4517 | |
4518 | drm_modeset_lock_all(dev); | |
4519 | ||
4520 | for (level = 0; level < num_levels; level++) { | |
4521 | unsigned int latency = wm[level]; | |
4522 | ||
97e94b22 DL |
4523 | /* |
4524 | * - WM1+ latency values in 0.5us units | |
de38b95c | 4525 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 4526 | */ |
666a4537 WB |
4527 | if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) || |
4528 | IS_CHERRYVIEW(dev)) | |
97e94b22 DL |
4529 | latency *= 10; |
4530 | else if (level > 0) | |
369a1342 VS |
4531 | latency *= 5; |
4532 | ||
4533 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4534 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4535 | } |
4536 | ||
4537 | drm_modeset_unlock_all(dev); | |
4538 | } | |
4539 | ||
4540 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4541 | { | |
4542 | struct drm_device *dev = m->private; | |
fac5e23e | 4543 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 DL |
4544 | const uint16_t *latencies; |
4545 | ||
4546 | if (INTEL_INFO(dev)->gen >= 9) | |
4547 | latencies = dev_priv->wm.skl_latency; | |
4548 | else | |
4549 | latencies = to_i915(dev)->wm.pri_latency; | |
369a1342 | 4550 | |
97e94b22 | 4551 | wm_latency_show(m, latencies); |
369a1342 VS |
4552 | |
4553 | return 0; | |
4554 | } | |
4555 | ||
4556 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4557 | { | |
4558 | struct drm_device *dev = m->private; | |
fac5e23e | 4559 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 DL |
4560 | const uint16_t *latencies; |
4561 | ||
4562 | if (INTEL_INFO(dev)->gen >= 9) | |
4563 | latencies = dev_priv->wm.skl_latency; | |
4564 | else | |
4565 | latencies = to_i915(dev)->wm.spr_latency; | |
369a1342 | 4566 | |
97e94b22 | 4567 | wm_latency_show(m, latencies); |
369a1342 VS |
4568 | |
4569 | return 0; | |
4570 | } | |
4571 | ||
4572 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4573 | { | |
4574 | struct drm_device *dev = m->private; | |
fac5e23e | 4575 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 DL |
4576 | const uint16_t *latencies; |
4577 | ||
4578 | if (INTEL_INFO(dev)->gen >= 9) | |
4579 | latencies = dev_priv->wm.skl_latency; | |
4580 | else | |
4581 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4582 | |
97e94b22 | 4583 | wm_latency_show(m, latencies); |
369a1342 VS |
4584 | |
4585 | return 0; | |
4586 | } | |
4587 | ||
4588 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4589 | { | |
4590 | struct drm_device *dev = inode->i_private; | |
4591 | ||
de38b95c | 4592 | if (INTEL_INFO(dev)->gen < 5) |
369a1342 VS |
4593 | return -ENODEV; |
4594 | ||
4595 | return single_open(file, pri_wm_latency_show, dev); | |
4596 | } | |
4597 | ||
4598 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4599 | { | |
4600 | struct drm_device *dev = inode->i_private; | |
4601 | ||
9ad0257c | 4602 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4603 | return -ENODEV; |
4604 | ||
4605 | return single_open(file, spr_wm_latency_show, dev); | |
4606 | } | |
4607 | ||
4608 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4609 | { | |
4610 | struct drm_device *dev = inode->i_private; | |
4611 | ||
9ad0257c | 4612 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4613 | return -ENODEV; |
4614 | ||
4615 | return single_open(file, cur_wm_latency_show, dev); | |
4616 | } | |
4617 | ||
4618 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4619 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4620 | { |
4621 | struct seq_file *m = file->private_data; | |
4622 | struct drm_device *dev = m->private; | |
97e94b22 | 4623 | uint16_t new[8] = { 0 }; |
de38b95c | 4624 | int num_levels; |
369a1342 VS |
4625 | int level; |
4626 | int ret; | |
4627 | char tmp[32]; | |
4628 | ||
de38b95c VS |
4629 | if (IS_CHERRYVIEW(dev)) |
4630 | num_levels = 3; | |
4631 | else if (IS_VALLEYVIEW(dev)) | |
4632 | num_levels = 1; | |
4633 | else | |
4634 | num_levels = ilk_wm_max_level(dev) + 1; | |
4635 | ||
369a1342 VS |
4636 | if (len >= sizeof(tmp)) |
4637 | return -EINVAL; | |
4638 | ||
4639 | if (copy_from_user(tmp, ubuf, len)) | |
4640 | return -EFAULT; | |
4641 | ||
4642 | tmp[len] = '\0'; | |
4643 | ||
97e94b22 DL |
4644 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4645 | &new[0], &new[1], &new[2], &new[3], | |
4646 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4647 | if (ret != num_levels) |
4648 | return -EINVAL; | |
4649 | ||
4650 | drm_modeset_lock_all(dev); | |
4651 | ||
4652 | for (level = 0; level < num_levels; level++) | |
4653 | wm[level] = new[level]; | |
4654 | ||
4655 | drm_modeset_unlock_all(dev); | |
4656 | ||
4657 | return len; | |
4658 | } | |
4659 | ||
4660 | ||
4661 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4662 | size_t len, loff_t *offp) | |
4663 | { | |
4664 | struct seq_file *m = file->private_data; | |
4665 | struct drm_device *dev = m->private; | |
fac5e23e | 4666 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 | 4667 | uint16_t *latencies; |
369a1342 | 4668 | |
97e94b22 DL |
4669 | if (INTEL_INFO(dev)->gen >= 9) |
4670 | latencies = dev_priv->wm.skl_latency; | |
4671 | else | |
4672 | latencies = to_i915(dev)->wm.pri_latency; | |
4673 | ||
4674 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4675 | } |
4676 | ||
4677 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4678 | size_t len, loff_t *offp) | |
4679 | { | |
4680 | struct seq_file *m = file->private_data; | |
4681 | struct drm_device *dev = m->private; | |
fac5e23e | 4682 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 | 4683 | uint16_t *latencies; |
369a1342 | 4684 | |
97e94b22 DL |
4685 | if (INTEL_INFO(dev)->gen >= 9) |
4686 | latencies = dev_priv->wm.skl_latency; | |
4687 | else | |
4688 | latencies = to_i915(dev)->wm.spr_latency; | |
4689 | ||
4690 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4691 | } |
4692 | ||
4693 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4694 | size_t len, loff_t *offp) | |
4695 | { | |
4696 | struct seq_file *m = file->private_data; | |
4697 | struct drm_device *dev = m->private; | |
fac5e23e | 4698 | struct drm_i915_private *dev_priv = to_i915(dev); |
97e94b22 DL |
4699 | uint16_t *latencies; |
4700 | ||
4701 | if (INTEL_INFO(dev)->gen >= 9) | |
4702 | latencies = dev_priv->wm.skl_latency; | |
4703 | else | |
4704 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4705 | |
97e94b22 | 4706 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4707 | } |
4708 | ||
4709 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4710 | .owner = THIS_MODULE, | |
4711 | .open = pri_wm_latency_open, | |
4712 | .read = seq_read, | |
4713 | .llseek = seq_lseek, | |
4714 | .release = single_release, | |
4715 | .write = pri_wm_latency_write | |
4716 | }; | |
4717 | ||
4718 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4719 | .owner = THIS_MODULE, | |
4720 | .open = spr_wm_latency_open, | |
4721 | .read = seq_read, | |
4722 | .llseek = seq_lseek, | |
4723 | .release = single_release, | |
4724 | .write = spr_wm_latency_write | |
4725 | }; | |
4726 | ||
4727 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4728 | .owner = THIS_MODULE, | |
4729 | .open = cur_wm_latency_open, | |
4730 | .read = seq_read, | |
4731 | .llseek = seq_lseek, | |
4732 | .release = single_release, | |
4733 | .write = cur_wm_latency_write | |
4734 | }; | |
4735 | ||
647416f9 KC |
4736 | static int |
4737 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4738 | { |
647416f9 | 4739 | struct drm_device *dev = data; |
fac5e23e | 4740 | struct drm_i915_private *dev_priv = to_i915(dev); |
f3cd474b | 4741 | |
d98c52cf | 4742 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4743 | |
647416f9 | 4744 | return 0; |
f3cd474b CW |
4745 | } |
4746 | ||
647416f9 KC |
4747 | static int |
4748 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4749 | { |
647416f9 | 4750 | struct drm_device *dev = data; |
fac5e23e | 4751 | struct drm_i915_private *dev_priv = to_i915(dev); |
d46c0517 | 4752 | |
b8d24a06 MK |
4753 | /* |
4754 | * There is no safeguard against this debugfs entry colliding | |
4755 | * with the hangcheck calling same i915_handle_error() in | |
4756 | * parallel, causing an explosion. For now we assume that the | |
4757 | * test harness is responsible enough not to inject gpu hangs | |
4758 | * while it is writing to 'i915_wedged' | |
4759 | */ | |
4760 | ||
d98c52cf | 4761 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4762 | return -EAGAIN; |
4763 | ||
d46c0517 | 4764 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 4765 | |
c033666a | 4766 | i915_handle_error(dev_priv, val, |
58174462 | 4767 | "Manually setting wedged to %llu", val); |
d46c0517 ID |
4768 | |
4769 | intel_runtime_pm_put(dev_priv); | |
4770 | ||
647416f9 | 4771 | return 0; |
f3cd474b CW |
4772 | } |
4773 | ||
647416f9 KC |
4774 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4775 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4776 | "%llu\n"); |
f3cd474b | 4777 | |
094f9a54 CW |
4778 | static int |
4779 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4780 | { | |
4781 | struct drm_device *dev = data; | |
fac5e23e | 4782 | struct drm_i915_private *dev_priv = to_i915(dev); |
094f9a54 CW |
4783 | |
4784 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4785 | return 0; | |
4786 | } | |
4787 | ||
4788 | static int | |
4789 | i915_ring_missed_irq_set(void *data, u64 val) | |
4790 | { | |
4791 | struct drm_device *dev = data; | |
fac5e23e | 4792 | struct drm_i915_private *dev_priv = to_i915(dev); |
094f9a54 CW |
4793 | int ret; |
4794 | ||
4795 | /* Lock against concurrent debugfs callers */ | |
4796 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4797 | if (ret) | |
4798 | return ret; | |
4799 | dev_priv->gpu_error.missed_irq_rings = val; | |
4800 | mutex_unlock(&dev->struct_mutex); | |
4801 | ||
4802 | return 0; | |
4803 | } | |
4804 | ||
4805 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4806 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4807 | "0x%08llx\n"); | |
4808 | ||
4809 | static int | |
4810 | i915_ring_test_irq_get(void *data, u64 *val) | |
4811 | { | |
4812 | struct drm_device *dev = data; | |
fac5e23e | 4813 | struct drm_i915_private *dev_priv = to_i915(dev); |
094f9a54 CW |
4814 | |
4815 | *val = dev_priv->gpu_error.test_irq_rings; | |
4816 | ||
4817 | return 0; | |
4818 | } | |
4819 | ||
4820 | static int | |
4821 | i915_ring_test_irq_set(void *data, u64 val) | |
4822 | { | |
4823 | struct drm_device *dev = data; | |
fac5e23e | 4824 | struct drm_i915_private *dev_priv = to_i915(dev); |
094f9a54 | 4825 | |
3a122c27 | 4826 | val &= INTEL_INFO(dev_priv)->ring_mask; |
094f9a54 | 4827 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); |
094f9a54 | 4828 | dev_priv->gpu_error.test_irq_rings = val; |
094f9a54 CW |
4829 | |
4830 | return 0; | |
4831 | } | |
4832 | ||
4833 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4834 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4835 | "0x%08llx\n"); | |
4836 | ||
dd624afd CW |
4837 | #define DROP_UNBOUND 0x1 |
4838 | #define DROP_BOUND 0x2 | |
4839 | #define DROP_RETIRE 0x4 | |
4840 | #define DROP_ACTIVE 0x8 | |
4841 | #define DROP_ALL (DROP_UNBOUND | \ | |
4842 | DROP_BOUND | \ | |
4843 | DROP_RETIRE | \ | |
4844 | DROP_ACTIVE) | |
647416f9 KC |
4845 | static int |
4846 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4847 | { |
647416f9 | 4848 | *val = DROP_ALL; |
dd624afd | 4849 | |
647416f9 | 4850 | return 0; |
dd624afd CW |
4851 | } |
4852 | ||
647416f9 KC |
4853 | static int |
4854 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4855 | { |
647416f9 | 4856 | struct drm_device *dev = data; |
fac5e23e | 4857 | struct drm_i915_private *dev_priv = to_i915(dev); |
647416f9 | 4858 | int ret; |
dd624afd | 4859 | |
2f9fe5ff | 4860 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4861 | |
4862 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4863 | * on ioctls on -EAGAIN. */ | |
4864 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4865 | if (ret) | |
4866 | return ret; | |
4867 | ||
4868 | if (val & DROP_ACTIVE) { | |
dcff85c8 | 4869 | ret = i915_gem_wait_for_idle(dev_priv, true); |
dd624afd CW |
4870 | if (ret) |
4871 | goto unlock; | |
4872 | } | |
4873 | ||
4874 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
c033666a | 4875 | i915_gem_retire_requests(dev_priv); |
dd624afd | 4876 | |
21ab4e74 CW |
4877 | if (val & DROP_BOUND) |
4878 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4879 | |
21ab4e74 CW |
4880 | if (val & DROP_UNBOUND) |
4881 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4882 | |
4883 | unlock: | |
4884 | mutex_unlock(&dev->struct_mutex); | |
4885 | ||
647416f9 | 4886 | return ret; |
dd624afd CW |
4887 | } |
4888 | ||
647416f9 KC |
4889 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4890 | i915_drop_caches_get, i915_drop_caches_set, | |
4891 | "0x%08llx\n"); | |
dd624afd | 4892 | |
647416f9 KC |
4893 | static int |
4894 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4895 | { |
647416f9 | 4896 | struct drm_device *dev = data; |
fac5e23e | 4897 | struct drm_i915_private *dev_priv = to_i915(dev); |
004777cb | 4898 | |
daa3afb2 | 4899 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4900 | return -ENODEV; |
4901 | ||
7c59a9c1 | 4902 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
647416f9 | 4903 | return 0; |
358733e9 JB |
4904 | } |
4905 | ||
647416f9 KC |
4906 | static int |
4907 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4908 | { |
647416f9 | 4909 | struct drm_device *dev = data; |
fac5e23e | 4910 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc4d91f6 | 4911 | u32 hw_max, hw_min; |
647416f9 | 4912 | int ret; |
004777cb | 4913 | |
daa3afb2 | 4914 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4915 | return -ENODEV; |
358733e9 | 4916 | |
647416f9 | 4917 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4918 | |
4fc688ce | 4919 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4920 | if (ret) |
4921 | return ret; | |
4922 | ||
358733e9 JB |
4923 | /* |
4924 | * Turbo will still be enabled, but won't go above the set value. | |
4925 | */ | |
bc4d91f6 | 4926 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4927 | |
bc4d91f6 AG |
4928 | hw_max = dev_priv->rps.max_freq; |
4929 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4930 | |
b39fb297 | 4931 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4932 | mutex_unlock(&dev_priv->rps.hw_lock); |
4933 | return -EINVAL; | |
0a073b84 JB |
4934 | } |
4935 | ||
b39fb297 | 4936 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4937 | |
dc97997a | 4938 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 4939 | |
4fc688ce | 4940 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4941 | |
647416f9 | 4942 | return 0; |
358733e9 JB |
4943 | } |
4944 | ||
647416f9 KC |
4945 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4946 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4947 | "%llu\n"); |
358733e9 | 4948 | |
647416f9 KC |
4949 | static int |
4950 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4951 | { |
647416f9 | 4952 | struct drm_device *dev = data; |
fac5e23e | 4953 | struct drm_i915_private *dev_priv = to_i915(dev); |
004777cb | 4954 | |
62e1baa1 | 4955 | if (INTEL_GEN(dev_priv) < 6) |
004777cb DV |
4956 | return -ENODEV; |
4957 | ||
7c59a9c1 | 4958 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
647416f9 | 4959 | return 0; |
1523c310 JB |
4960 | } |
4961 | ||
647416f9 KC |
4962 | static int |
4963 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4964 | { |
647416f9 | 4965 | struct drm_device *dev = data; |
fac5e23e | 4966 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc4d91f6 | 4967 | u32 hw_max, hw_min; |
647416f9 | 4968 | int ret; |
004777cb | 4969 | |
62e1baa1 | 4970 | if (INTEL_GEN(dev_priv) < 6) |
004777cb | 4971 | return -ENODEV; |
1523c310 | 4972 | |
647416f9 | 4973 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4974 | |
4fc688ce | 4975 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4976 | if (ret) |
4977 | return ret; | |
4978 | ||
1523c310 JB |
4979 | /* |
4980 | * Turbo will still be enabled, but won't go below the set value. | |
4981 | */ | |
bc4d91f6 | 4982 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4983 | |
bc4d91f6 AG |
4984 | hw_max = dev_priv->rps.max_freq; |
4985 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4986 | |
b39fb297 | 4987 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
4988 | mutex_unlock(&dev_priv->rps.hw_lock); |
4989 | return -EINVAL; | |
0a073b84 | 4990 | } |
dd0a1aa1 | 4991 | |
b39fb297 | 4992 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4993 | |
dc97997a | 4994 | intel_set_rps(dev_priv, val); |
dd0a1aa1 | 4995 | |
4fc688ce | 4996 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4997 | |
647416f9 | 4998 | return 0; |
1523c310 JB |
4999 | } |
5000 | ||
647416f9 KC |
5001 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
5002 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 5003 | "%llu\n"); |
1523c310 | 5004 | |
647416f9 KC |
5005 | static int |
5006 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 5007 | { |
647416f9 | 5008 | struct drm_device *dev = data; |
fac5e23e | 5009 | struct drm_i915_private *dev_priv = to_i915(dev); |
07b7ddd9 | 5010 | u32 snpcr; |
647416f9 | 5011 | int ret; |
07b7ddd9 | 5012 | |
004777cb DV |
5013 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5014 | return -ENODEV; | |
5015 | ||
22bcfc6a DV |
5016 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
5017 | if (ret) | |
5018 | return ret; | |
c8c8fb33 | 5019 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 5020 | |
07b7ddd9 | 5021 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
5022 | |
5023 | intel_runtime_pm_put(dev_priv); | |
91c8a326 | 5024 | mutex_unlock(&dev_priv->drm.struct_mutex); |
07b7ddd9 | 5025 | |
647416f9 | 5026 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 5027 | |
647416f9 | 5028 | return 0; |
07b7ddd9 JB |
5029 | } |
5030 | ||
647416f9 KC |
5031 | static int |
5032 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 5033 | { |
647416f9 | 5034 | struct drm_device *dev = data; |
fac5e23e | 5035 | struct drm_i915_private *dev_priv = to_i915(dev); |
07b7ddd9 | 5036 | u32 snpcr; |
07b7ddd9 | 5037 | |
004777cb DV |
5038 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5039 | return -ENODEV; | |
5040 | ||
647416f9 | 5041 | if (val > 3) |
07b7ddd9 JB |
5042 | return -EINVAL; |
5043 | ||
c8c8fb33 | 5044 | intel_runtime_pm_get(dev_priv); |
647416f9 | 5045 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
5046 | |
5047 | /* Update the cache sharing policy here as well */ | |
5048 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
5049 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5050 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
5051 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
5052 | ||
c8c8fb33 | 5053 | intel_runtime_pm_put(dev_priv); |
647416f9 | 5054 | return 0; |
07b7ddd9 JB |
5055 | } |
5056 | ||
647416f9 KC |
5057 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
5058 | i915_cache_sharing_get, i915_cache_sharing_set, | |
5059 | "%llu\n"); | |
07b7ddd9 | 5060 | |
5d39525a JM |
5061 | struct sseu_dev_status { |
5062 | unsigned int slice_total; | |
5063 | unsigned int subslice_total; | |
5064 | unsigned int subslice_per_slice; | |
5065 | unsigned int eu_total; | |
5066 | unsigned int eu_per_subslice; | |
5067 | }; | |
5068 | ||
5069 | static void cherryview_sseu_device_status(struct drm_device *dev, | |
5070 | struct sseu_dev_status *stat) | |
5071 | { | |
fac5e23e | 5072 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a0b457f | 5073 | int ss_max = 2; |
5d39525a JM |
5074 | int ss; |
5075 | u32 sig1[ss_max], sig2[ss_max]; | |
5076 | ||
5077 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
5078 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
5079 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
5080 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
5081 | ||
5082 | for (ss = 0; ss < ss_max; ss++) { | |
5083 | unsigned int eu_cnt; | |
5084 | ||
5085 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
5086 | /* skip disabled subslice */ | |
5087 | continue; | |
5088 | ||
5089 | stat->slice_total = 1; | |
5090 | stat->subslice_per_slice++; | |
5091 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + | |
5092 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
5093 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
5094 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
5095 | stat->eu_total += eu_cnt; | |
5096 | stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); | |
5097 | } | |
5098 | stat->subslice_total = stat->subslice_per_slice; | |
5099 | } | |
5100 | ||
5101 | static void gen9_sseu_device_status(struct drm_device *dev, | |
5102 | struct sseu_dev_status *stat) | |
5103 | { | |
fac5e23e | 5104 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c046bc1 | 5105 | int s_max = 3, ss_max = 4; |
5d39525a JM |
5106 | int s, ss; |
5107 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
5108 | ||
1c046bc1 JM |
5109 | /* BXT has a single slice and at most 3 subslices. */ |
5110 | if (IS_BROXTON(dev)) { | |
5111 | s_max = 1; | |
5112 | ss_max = 3; | |
5113 | } | |
5114 | ||
5115 | for (s = 0; s < s_max; s++) { | |
5116 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
5117 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
5118 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
5119 | } | |
5120 | ||
5d39525a JM |
5121 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
5122 | GEN9_PGCTL_SSA_EU19_ACK | | |
5123 | GEN9_PGCTL_SSA_EU210_ACK | | |
5124 | GEN9_PGCTL_SSA_EU311_ACK; | |
5125 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
5126 | GEN9_PGCTL_SSB_EU19_ACK | | |
5127 | GEN9_PGCTL_SSB_EU210_ACK | | |
5128 | GEN9_PGCTL_SSB_EU311_ACK; | |
5129 | ||
5130 | for (s = 0; s < s_max; s++) { | |
1c046bc1 JM |
5131 | unsigned int ss_cnt = 0; |
5132 | ||
5d39525a JM |
5133 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) |
5134 | /* skip disabled slice */ | |
5135 | continue; | |
5136 | ||
5137 | stat->slice_total++; | |
1c046bc1 | 5138 | |
ef11bdb3 | 5139 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1c046bc1 JM |
5140 | ss_cnt = INTEL_INFO(dev)->subslice_per_slice; |
5141 | ||
5d39525a JM |
5142 | for (ss = 0; ss < ss_max; ss++) { |
5143 | unsigned int eu_cnt; | |
5144 | ||
1c046bc1 JM |
5145 | if (IS_BROXTON(dev) && |
5146 | !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
5147 | /* skip disabled subslice */ | |
5148 | continue; | |
5149 | ||
5150 | if (IS_BROXTON(dev)) | |
5151 | ss_cnt++; | |
5152 | ||
5d39525a JM |
5153 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
5154 | eu_mask[ss%2]); | |
5155 | stat->eu_total += eu_cnt; | |
5156 | stat->eu_per_subslice = max(stat->eu_per_subslice, | |
5157 | eu_cnt); | |
5158 | } | |
1c046bc1 JM |
5159 | |
5160 | stat->subslice_total += ss_cnt; | |
5161 | stat->subslice_per_slice = max(stat->subslice_per_slice, | |
5162 | ss_cnt); | |
5d39525a JM |
5163 | } |
5164 | } | |
5165 | ||
91bedd34 ŁD |
5166 | static void broadwell_sseu_device_status(struct drm_device *dev, |
5167 | struct sseu_dev_status *stat) | |
5168 | { | |
fac5e23e | 5169 | struct drm_i915_private *dev_priv = to_i915(dev); |
91bedd34 ŁD |
5170 | int s; |
5171 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); | |
5172 | ||
5173 | stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); | |
5174 | ||
5175 | if (stat->slice_total) { | |
5176 | stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; | |
5177 | stat->subslice_total = stat->slice_total * | |
5178 | stat->subslice_per_slice; | |
5179 | stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice; | |
5180 | stat->eu_total = stat->eu_per_subslice * stat->subslice_total; | |
5181 | ||
5182 | /* subtract fused off EU(s) from enabled slice(s) */ | |
5183 | for (s = 0; s < stat->slice_total; s++) { | |
5184 | u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s]; | |
5185 | ||
5186 | stat->eu_total -= hweight8(subslice_7eu); | |
5187 | } | |
5188 | } | |
5189 | } | |
5190 | ||
3873218f JM |
5191 | static int i915_sseu_status(struct seq_file *m, void *unused) |
5192 | { | |
5193 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
238010ed DW |
5194 | struct drm_i915_private *dev_priv = to_i915(node->minor->dev); |
5195 | struct drm_device *dev = &dev_priv->drm; | |
5d39525a | 5196 | struct sseu_dev_status stat; |
3873218f | 5197 | |
91bedd34 | 5198 | if (INTEL_INFO(dev)->gen < 8) |
3873218f JM |
5199 | return -ENODEV; |
5200 | ||
5201 | seq_puts(m, "SSEU Device Info\n"); | |
5202 | seq_printf(m, " Available Slice Total: %u\n", | |
5203 | INTEL_INFO(dev)->slice_total); | |
5204 | seq_printf(m, " Available Subslice Total: %u\n", | |
5205 | INTEL_INFO(dev)->subslice_total); | |
5206 | seq_printf(m, " Available Subslice Per Slice: %u\n", | |
5207 | INTEL_INFO(dev)->subslice_per_slice); | |
5208 | seq_printf(m, " Available EU Total: %u\n", | |
5209 | INTEL_INFO(dev)->eu_total); | |
5210 | seq_printf(m, " Available EU Per Subslice: %u\n", | |
5211 | INTEL_INFO(dev)->eu_per_subslice); | |
33e141ed | 5212 | seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev))); |
5213 | if (HAS_POOLED_EU(dev)) | |
5214 | seq_printf(m, " Min EU in pool: %u\n", | |
5215 | INTEL_INFO(dev)->min_eu_in_pool); | |
3873218f JM |
5216 | seq_printf(m, " Has Slice Power Gating: %s\n", |
5217 | yesno(INTEL_INFO(dev)->has_slice_pg)); | |
5218 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
5219 | yesno(INTEL_INFO(dev)->has_subslice_pg)); | |
5220 | seq_printf(m, " Has EU Power Gating: %s\n", | |
5221 | yesno(INTEL_INFO(dev)->has_eu_pg)); | |
5222 | ||
7f992aba | 5223 | seq_puts(m, "SSEU Device Status\n"); |
5d39525a | 5224 | memset(&stat, 0, sizeof(stat)); |
238010ed DW |
5225 | |
5226 | intel_runtime_pm_get(dev_priv); | |
5227 | ||
5575f03a | 5228 | if (IS_CHERRYVIEW(dev)) { |
5d39525a | 5229 | cherryview_sseu_device_status(dev, &stat); |
91bedd34 ŁD |
5230 | } else if (IS_BROADWELL(dev)) { |
5231 | broadwell_sseu_device_status(dev, &stat); | |
1c046bc1 | 5232 | } else if (INTEL_INFO(dev)->gen >= 9) { |
5d39525a | 5233 | gen9_sseu_device_status(dev, &stat); |
7f992aba | 5234 | } |
238010ed DW |
5235 | |
5236 | intel_runtime_pm_put(dev_priv); | |
5237 | ||
5d39525a JM |
5238 | seq_printf(m, " Enabled Slice Total: %u\n", |
5239 | stat.slice_total); | |
5240 | seq_printf(m, " Enabled Subslice Total: %u\n", | |
5241 | stat.subslice_total); | |
5242 | seq_printf(m, " Enabled Subslice Per Slice: %u\n", | |
5243 | stat.subslice_per_slice); | |
5244 | seq_printf(m, " Enabled EU Total: %u\n", | |
5245 | stat.eu_total); | |
5246 | seq_printf(m, " Enabled EU Per Subslice: %u\n", | |
5247 | stat.eu_per_subslice); | |
7f992aba | 5248 | |
3873218f JM |
5249 | return 0; |
5250 | } | |
5251 | ||
6d794d42 BW |
5252 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
5253 | { | |
5254 | struct drm_device *dev = inode->i_private; | |
fac5e23e | 5255 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d794d42 | 5256 | |
075edca4 | 5257 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5258 | return 0; |
5259 | ||
6daccb0b | 5260 | intel_runtime_pm_get(dev_priv); |
59bad947 | 5261 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
5262 | |
5263 | return 0; | |
5264 | } | |
5265 | ||
c43b5634 | 5266 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
5267 | { |
5268 | struct drm_device *dev = inode->i_private; | |
fac5e23e | 5269 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d794d42 | 5270 | |
075edca4 | 5271 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5272 | return 0; |
5273 | ||
59bad947 | 5274 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 5275 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
5276 | |
5277 | return 0; | |
5278 | } | |
5279 | ||
5280 | static const struct file_operations i915_forcewake_fops = { | |
5281 | .owner = THIS_MODULE, | |
5282 | .open = i915_forcewake_open, | |
5283 | .release = i915_forcewake_release, | |
5284 | }; | |
5285 | ||
5286 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5287 | { | |
5288 | struct drm_device *dev = minor->dev; | |
5289 | struct dentry *ent; | |
5290 | ||
5291 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5292 | S_IRUSR, |
6d794d42 BW |
5293 | root, dev, |
5294 | &i915_forcewake_fops); | |
f3c5fe97 WY |
5295 | if (!ent) |
5296 | return -ENOMEM; | |
6d794d42 | 5297 | |
8eb57294 | 5298 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5299 | } |
5300 | ||
6a9c308d DV |
5301 | static int i915_debugfs_create(struct dentry *root, |
5302 | struct drm_minor *minor, | |
5303 | const char *name, | |
5304 | const struct file_operations *fops) | |
07b7ddd9 JB |
5305 | { |
5306 | struct drm_device *dev = minor->dev; | |
5307 | struct dentry *ent; | |
5308 | ||
6a9c308d | 5309 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
5310 | S_IRUGO | S_IWUSR, |
5311 | root, dev, | |
6a9c308d | 5312 | fops); |
f3c5fe97 WY |
5313 | if (!ent) |
5314 | return -ENOMEM; | |
07b7ddd9 | 5315 | |
6a9c308d | 5316 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5317 | } |
5318 | ||
06c5bf8c | 5319 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5320 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5321 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5322 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
6da84829 | 5323 | {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, |
6d2b8885 | 5324 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5325 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5326 | {"i915_gem_request", i915_gem_request_info, 0}, |
5327 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5328 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5329 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5330 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5331 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5332 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5333 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5334 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 5335 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 5336 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 5337 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 5338 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5339 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5340 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5341 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5342 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 5343 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 5344 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5345 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5346 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5347 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 5348 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 5349 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5350 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5351 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 5352 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 5353 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5354 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5355 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5356 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5357 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5358 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5359 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5360 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5361 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 5362 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 5363 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 5364 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5365 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5366 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5367 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5368 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5369 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5370 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5371 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5372 | }; |
27c202ad | 5373 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5374 | |
06c5bf8c | 5375 | static const struct i915_debugfs_files { |
34b9674c DV |
5376 | const char *name; |
5377 | const struct file_operations *fops; | |
5378 | } i915_debugfs_files[] = { | |
5379 | {"i915_wedged", &i915_wedged_fops}, | |
5380 | {"i915_max_freq", &i915_max_freq_fops}, | |
5381 | {"i915_min_freq", &i915_min_freq_fops}, | |
5382 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
094f9a54 CW |
5383 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5384 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
5385 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
5386 | {"i915_error_state", &i915_error_state_fops}, | |
5387 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 5388 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5389 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5390 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5391 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5392 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5393 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5394 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
5395 | {"i915_dp_test_active", &i915_displayport_test_active_fops} | |
34b9674c DV |
5396 | }; |
5397 | ||
07144428 DL |
5398 | void intel_display_crc_init(struct drm_device *dev) |
5399 | { | |
fac5e23e | 5400 | struct drm_i915_private *dev_priv = to_i915(dev); |
b378360e | 5401 | enum pipe pipe; |
07144428 | 5402 | |
055e393f | 5403 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5404 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5405 | |
d538bbdf DL |
5406 | pipe_crc->opened = false; |
5407 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5408 | init_waitqueue_head(&pipe_crc->wq); |
5409 | } | |
5410 | } | |
5411 | ||
1dac891c | 5412 | int i915_debugfs_register(struct drm_i915_private *dev_priv) |
2017263e | 5413 | { |
91c8a326 | 5414 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c | 5415 | int ret, i; |
f3cd474b | 5416 | |
6d794d42 | 5417 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5418 | if (ret) |
5419 | return ret; | |
6a9c308d | 5420 | |
07144428 DL |
5421 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5422 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5423 | if (ret) | |
5424 | return ret; | |
5425 | } | |
5426 | ||
34b9674c DV |
5427 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5428 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5429 | i915_debugfs_files[i].name, | |
5430 | i915_debugfs_files[i].fops); | |
5431 | if (ret) | |
5432 | return ret; | |
5433 | } | |
40633219 | 5434 | |
27c202ad BG |
5435 | return drm_debugfs_create_files(i915_debugfs_list, |
5436 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5437 | minor->debugfs_root, minor); |
5438 | } | |
5439 | ||
1dac891c | 5440 | void i915_debugfs_unregister(struct drm_i915_private *dev_priv) |
2017263e | 5441 | { |
91c8a326 | 5442 | struct drm_minor *minor = dev_priv->drm.primary; |
34b9674c DV |
5443 | int i; |
5444 | ||
27c202ad BG |
5445 | drm_debugfs_remove_files(i915_debugfs_list, |
5446 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5447 | |
6d794d42 BW |
5448 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
5449 | 1, minor); | |
07144428 | 5450 | |
e309a997 | 5451 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5452 | struct drm_info_list *info_list = |
5453 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5454 | ||
5455 | drm_debugfs_remove_files(info_list, 1, minor); | |
5456 | } | |
5457 | ||
34b9674c DV |
5458 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5459 | struct drm_info_list *info_list = | |
5460 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
5461 | ||
5462 | drm_debugfs_remove_files(info_list, 1, minor); | |
5463 | } | |
2017263e | 5464 | } |
aa7471d2 JN |
5465 | |
5466 | struct dpcd_block { | |
5467 | /* DPCD dump start address. */ | |
5468 | unsigned int offset; | |
5469 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5470 | unsigned int end; | |
5471 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5472 | size_t size; | |
5473 | /* Only valid for eDP. */ | |
5474 | bool edp; | |
5475 | }; | |
5476 | ||
5477 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5478 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5479 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5480 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5481 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5482 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5483 | { .offset = DP_SET_POWER }, | |
5484 | { .offset = DP_EDP_DPCD_REV }, | |
5485 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5486 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5487 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5488 | }; | |
5489 | ||
5490 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5491 | { | |
5492 | struct drm_connector *connector = m->private; | |
5493 | struct intel_dp *intel_dp = | |
5494 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5495 | uint8_t buf[16]; | |
5496 | ssize_t err; | |
5497 | int i; | |
5498 | ||
5c1a8875 MK |
5499 | if (connector->status != connector_status_connected) |
5500 | return -ENODEV; | |
5501 | ||
aa7471d2 JN |
5502 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5503 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5504 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5505 | ||
5506 | if (b->edp && | |
5507 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5508 | continue; | |
5509 | ||
5510 | /* low tech for now */ | |
5511 | if (WARN_ON(size > sizeof(buf))) | |
5512 | continue; | |
5513 | ||
5514 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5515 | if (err <= 0) { | |
5516 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5517 | size, b->offset, err); | |
5518 | continue; | |
5519 | } | |
5520 | ||
5521 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5522 | } |
aa7471d2 JN |
5523 | |
5524 | return 0; | |
5525 | } | |
5526 | ||
5527 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5528 | { | |
5529 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5530 | } | |
5531 | ||
5532 | static const struct file_operations i915_dpcd_fops = { | |
5533 | .owner = THIS_MODULE, | |
5534 | .open = i915_dpcd_open, | |
5535 | .read = seq_read, | |
5536 | .llseek = seq_lseek, | |
5537 | .release = single_release, | |
5538 | }; | |
5539 | ||
5540 | /** | |
5541 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5542 | * @connector: pointer to a registered drm_connector | |
5543 | * | |
5544 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5545 | * drm_debugfs_connector_remove(). | |
5546 | * | |
5547 | * Returns 0 on success, negative error codes on error. | |
5548 | */ | |
5549 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5550 | { | |
5551 | struct dentry *root = connector->debugfs_entry; | |
5552 | ||
5553 | /* The connector must have been registered beforehands. */ | |
5554 | if (!root) | |
5555 | return -ENODEV; | |
5556 | ||
5557 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5558 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5559 | debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, | |
5560 | &i915_dpcd_fops); | |
5561 | ||
5562 | return 0; | |
5563 | } |