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drm/i915: Per-process stats work better when evaluated per-process
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
82 struct drm_info_node *node = (struct drm_info_node *) m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
d7f46fc4 101 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
d7f46fc4
BW		 126 int pin_count = 0;
127
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
84734a04 139 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
c1ad11fc
CW		 160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
69dc4987
CW		 171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
37811fcc
CW		 173}
174
3ccfd19d
BW		 175static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
176{
177 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
178 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
179 seq_putc(m, ' ');
180}
181
433e12f7 182static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e
BG		 183{
184 struct drm_info_node *node = (struct drm_info_node *) m->private;
433e12f7
BG		 185 uintptr_t list = (uintptr_t) node->info_ent->data;
186 struct list_head *head;
2017263e 187 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 188 struct drm_i915_private *dev_priv = dev->dev_private;
189 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 190 struct i915_vma *vma;
8f2480fb
CW		 191 size_t total_obj_size, total_gtt_size;
192 int count, ret;
de227ef0
CW		 193
194 ret = mutex_lock_interruptible(&dev->struct_mutex);
195 if (ret)
196 return ret;
2017263e 197
ca191b13 198 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 199 switch (list) {
200 case ACTIVE_LIST:
267f0c90 201 seq_puts(m, "Active:\n");
5cef07e1 202 head = &vm->active_list;
433e12f7
BG		 203 break;
204 case INACTIVE_LIST:
267f0c90 205 seq_puts(m, "Inactive:\n");
5cef07e1 206 head = &vm->inactive_list;
433e12f7 207 break;
433e12f7 208 default:
de227ef0
CW		 209 mutex_unlock(&dev->struct_mutex);
210 return -EINVAL;
2017263e 211 }
2017263e 212
8f2480fb 213 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 214 list_for_each_entry(vma, head, mm_list) {
215 seq_printf(m, " ");
216 describe_obj(m, vma->obj);
217 seq_printf(m, "\n");
218 total_obj_size += vma->obj->base.size;
219 total_gtt_size += vma->node.size;
8f2480fb 220 count++;
2017263e 221 }
de227ef0 222 mutex_unlock(&dev->struct_mutex);
5e118f41 223
8f2480fb
CW		 224 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count, total_obj_size, total_gtt_size);
2017263e
BG		 226 return 0;
227}
228
6d2b8885
CW		 229static int obj_rank_by_stolen(void *priv,
230 struct list_head *A, struct list_head *B)
231{
232 struct drm_i915_gem_object *a =
b25cb2f8 233 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 234 struct drm_i915_gem_object *b =
b25cb2f8 235 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 236
237 return a->stolen->start - b->stolen->start;
238}
239
240static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
241{
242 struct drm_info_node *node = (struct drm_info_node *) m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 struct drm_i915_gem_object *obj;
246 size_t total_obj_size, total_gtt_size;
247 LIST_HEAD(stolen);
248 int count, ret;
249
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
251 if (ret)
252 return ret;
253
254 total_obj_size = total_gtt_size = count = 0;
255 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
256 if (obj->stolen == NULL)
257 continue;
258
b25cb2f8 259 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 260
261 total_obj_size += obj->base.size;
262 total_gtt_size += i915_gem_obj_ggtt_size(obj);
263 count++;
264 }
265 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
266 if (obj->stolen == NULL)
267 continue;
268
b25cb2f8 269 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 270
271 total_obj_size += obj->base.size;
272 count++;
273 }
274 list_sort(NULL, &stolen, obj_rank_by_stolen);
275 seq_puts(m, "Stolen:\n");
276 while (!list_empty(&stolen)) {
b25cb2f8 277 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 278 seq_puts(m, " ");
279 describe_obj(m, obj);
280 seq_putc(m, '\n');
b25cb2f8 281 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 282 }
283 mutex_unlock(&dev->struct_mutex);
284
285 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count, total_obj_size, total_gtt_size);
287 return 0;
288}
289
6299f992
CW		 290#define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
f343c5f6 292 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 293 ++count; \
294 if (obj->map_and_fenceable) { \
f343c5f6 295 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 296 ++mappable_count; \
297 } \
298 } \
0206e353 299} while (0)
6299f992 300
2db8e9d6 301struct file_stats {
6313c204 302 struct drm_i915_file_private *file_priv;
2db8e9d6 303 int count;
6313c204 304 size_t total, global, active, inactive, unbound;
2db8e9d6
CW		 305};
306
307static int per_file_stats(int id, void *ptr, void *data)
308{
309 struct drm_i915_gem_object *obj = ptr;
310 struct file_stats *stats = data;
6313c204 311 struct i915_vma *vma;
2db8e9d6
CW		 312
313 stats->count++;
314 stats->total += obj->base.size;
315
6313c204
CW		 316 if (USES_FULL_PPGTT(obj->base.dev)) {
317 list_for_each_entry(vma, &obj->vma_list, vma_link) {
318 struct i915_hw_ppgtt *ppgtt;
319
320 if (!drm_mm_node_allocated(&vma->node))
321 continue;
322
323 if (i915_is_ggtt(vma->vm)) {
324 stats->global += obj->base.size;
325 continue;
326 }
327
328 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
329 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
330 continue;
331
332 if (obj->ring) /* XXX per-vma statistic */
333 stats->active += obj->base.size;
334 else
335 stats->inactive += obj->base.size;
336
337 return 0;
338 }
2db8e9d6 339 } else {
6313c204
CW		 340 if (i915_gem_obj_ggtt_bound(obj)) {
341 stats->global += obj->base.size;
342 if (obj->ring)
343 stats->active += obj->base.size;
344 else
345 stats->inactive += obj->base.size;
346 return 0;
347 }
2db8e9d6
CW		 348 }
349
6313c204
CW		 350 if (!list_empty(&obj->global_list))
351 stats->unbound += obj->base.size;
352
2db8e9d6
CW		 353 return 0;
354}
355
ca191b13
BW		 356#define count_vmas(list, member) do { \
357 list_for_each_entry(vma, list, member) { \
358 size += i915_gem_obj_ggtt_size(vma->obj); \
359 ++count; \
360 if (vma->obj->map_and_fenceable) { \
361 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
362 ++mappable_count; \
363 } \
364 } \
365} while (0)
366
367static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f
CW		 368{
369 struct drm_info_node *node = (struct drm_info_node *) m->private;
370 struct drm_device *dev = node->minor->dev;
371 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 372 u32 count, mappable_count, purgeable_count;
373 size_t size, mappable_size, purgeable_size;
6299f992 374 struct drm_i915_gem_object *obj;
5cef07e1 375 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 376 struct drm_file *file;
ca191b13 377 struct i915_vma *vma;
73aa808f
CW		 378 int ret;
379
380 ret = mutex_lock_interruptible(&dev->struct_mutex);
381 if (ret)
382 return ret;
383
6299f992
CW		 384 seq_printf(m, "%u objects, %zu bytes\n",
385 dev_priv->mm.object_count,
386 dev_priv->mm.object_memory);
387
388 size = count = mappable_size = mappable_count = 0;
35c20a60 389 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 390 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
391 count, mappable_count, size, mappable_size);
392
393 size = count = mappable_size = mappable_count = 0;
ca191b13 394 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 395 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
396 count, mappable_count, size, mappable_size);
397
6299f992 398 size = count = mappable_size = mappable_count = 0;
ca191b13 399 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 400 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
401 count, mappable_count, size, mappable_size);
402
b7abb714 403 size = count = purgeable_size = purgeable_count = 0;
35c20a60 404 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 405 size += obj->base.size, ++count;
b7abb714
CW		 406 if (obj->madv == I915_MADV_DONTNEED)
407 purgeable_size += obj->base.size, ++purgeable_count;
408 }
6c085a72
CW		 409 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
410
6299f992 411 size = count = mappable_size = mappable_count = 0;
35c20a60 412 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 413 if (obj->fault_mappable) {
f343c5f6 414 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 415 ++count;
416 }
417 if (obj->pin_mappable) {
f343c5f6 418 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 419 ++mappable_count;
420 }
b7abb714
CW		 421 if (obj->madv == I915_MADV_DONTNEED) {
422 purgeable_size += obj->base.size;
423 ++purgeable_count;
424 }
6299f992 425 }
b7abb714
CW		 426 seq_printf(m, "%u purgeable objects, %zu bytes\n",
427 purgeable_count, purgeable_size);
6299f992
CW		 428 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
429 mappable_count, mappable_size);
430 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
431 count, size);
432
93d18799 433 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 434 dev_priv->gtt.base.total,
435 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 436
267f0c90 437 seq_putc(m, '\n');
2db8e9d6
CW		 438 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
439 struct file_stats stats;
3ec2f427 440 struct task_struct *task;
2db8e9d6
CW		 441
442 memset(&stats, 0, sizeof(stats));
6313c204 443 stats.file_priv = file->driver_priv;
2db8e9d6 444 idr_for_each(&file->object_idr, per_file_stats, &stats);
3ec2f427
TH		 445 /*
446 * Although we have a valid reference on file->pid, that does
447 * not guarantee that the task_struct who called get_pid() is
448 * still alive (e.g. get_pid(current) => fork() => exit()).
449 * Therefore, we need to protect this ->comm access using RCU.
450 */
451 rcu_read_lock();
452 task = pid_task(file->pid, PIDTYPE_PID);
6313c204 453 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu unbound)\n",
3ec2f427 454 task ? task->comm : "<unknown>",
2db8e9d6
CW		 455 stats.count,
456 stats.total,
457 stats.active,
458 stats.inactive,
6313c204 459 stats.global,
2db8e9d6 460 stats.unbound);
3ec2f427 461 rcu_read_unlock();
2db8e9d6
CW		 462 }
463
73aa808f
CW		 464 mutex_unlock(&dev->struct_mutex);
465
466 return 0;
467}
468
aee56cff 469static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323
CW		 470{
471 struct drm_info_node *node = (struct drm_info_node *) m->private;
472 struct drm_device *dev = node->minor->dev;
1b50247a 473 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 474 struct drm_i915_private *dev_priv = dev->dev_private;
475 struct drm_i915_gem_object *obj;
476 size_t total_obj_size, total_gtt_size;
477 int count, ret;
478
479 ret = mutex_lock_interruptible(&dev->struct_mutex);
480 if (ret)
481 return ret;
482
483 total_obj_size = total_gtt_size = count = 0;
35c20a60 484 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 485 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 486 continue;
487
267f0c90 488 seq_puts(m, " ");
08c18323 489 describe_obj(m, obj);
267f0c90 490 seq_putc(m, '\n');
08c18323 491 total_obj_size += obj->base.size;
f343c5f6 492 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 493 count++;
494 }
495
496 mutex_unlock(&dev->struct_mutex);
497
498 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
499 count, total_obj_size, total_gtt_size);
500
501 return 0;
502}
503
4e5359cd
SF		 504static int i915_gem_pageflip_info(struct seq_file *m, void *data)
505{
506 struct drm_info_node *node = (struct drm_info_node *) m->private;
507 struct drm_device *dev = node->minor->dev;
508 unsigned long flags;
509 struct intel_crtc *crtc;
510
511 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9db4a9c7
JB		 512 const char pipe = pipe_name(crtc->pipe);
513 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 514 struct intel_unpin_work *work;
515
516 spin_lock_irqsave(&dev->event_lock, flags);
517 work = crtc->unpin_work;
518 if (work == NULL) {
9db4a9c7 519 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 520 pipe, plane);
521 } else {
e7d841ca 522 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 523 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 524 pipe, plane);
525 } else {
9db4a9c7 526 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 527 pipe, plane);
528 }
529 if (work->enable_stall_check)
267f0c90 530 seq_puts(m, "Stall check enabled, ");
4e5359cd 531 else
267f0c90 532 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 533 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 534
535 if (work->old_fb_obj) {
05394f39
CW		 536 struct drm_i915_gem_object *obj = work->old_fb_obj;
537 if (obj)
f343c5f6
BW		 538 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
539 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 540 }
541 if (work->pending_flip_obj) {
05394f39
CW		 542 struct drm_i915_gem_object *obj = work->pending_flip_obj;
543 if (obj)
f343c5f6
BW		 544 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
545 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 546 }
547 }
548 spin_unlock_irqrestore(&dev->event_lock, flags);
549 }
550
551 return 0;
552}
553
2017263e
BG		 554static int i915_gem_request_info(struct seq_file *m, void *data)
555{
556 struct drm_info_node *node = (struct drm_info_node *) m->private;
557 struct drm_device *dev = node->minor->dev;
558 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 559 struct intel_ring_buffer *ring;
2017263e 560 struct drm_i915_gem_request *gem_request;
a2c7f6fd 561 int ret, count, i;
de227ef0
CW		 562
563 ret = mutex_lock_interruptible(&dev->struct_mutex);
564 if (ret)
565 return ret;
2017263e 566
c2c347a9 567 count = 0;
a2c7f6fd
CW		 568 for_each_ring(ring, dev_priv, i) {
569 if (list_empty(&ring->request_list))
570 continue;
571
572 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 573 list_for_each_entry(gem_request,
a2c7f6fd 574 &ring->request_list,
c2c347a9
CW		 575 list) {
576 seq_printf(m, " %d @ %d\n",
577 gem_request->seqno,
578 (int) (jiffies - gem_request->emitted_jiffies));
579 }
580 count++;
2017263e 581 }
de227ef0
CW		 582 mutex_unlock(&dev->struct_mutex);
583
c2c347a9 584 if (count == 0)
267f0c90 585 seq_puts(m, "No requests\n");
c2c347a9 586
2017263e
BG		 587 return 0;
588}
589
b2223497
CW		 590static void i915_ring_seqno_info(struct seq_file *m,
591 struct intel_ring_buffer *ring)
592{
593 if (ring->get_seqno) {
43a7b924 594 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 595 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 596 }
597}
598
2017263e
BG		 599static int i915_gem_seqno_info(struct seq_file *m, void *data)
600{
601 struct drm_info_node *node = (struct drm_info_node *) m->private;
602 struct drm_device *dev = node->minor->dev;
603 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 604 struct intel_ring_buffer *ring;
1ec14ad3 605 int ret, i;
de227ef0
CW		 606
607 ret = mutex_lock_interruptible(&dev->struct_mutex);
608 if (ret)
609 return ret;
c8c8fb33 610 intel_runtime_pm_get(dev_priv);
2017263e 611
a2c7f6fd
CW		 612 for_each_ring(ring, dev_priv, i)
613 i915_ring_seqno_info(m, ring);
de227ef0 614
c8c8fb33 615 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 616 mutex_unlock(&dev->struct_mutex);
617
2017263e
BG		 618 return 0;
619}
620
621
622static int i915_interrupt_info(struct seq_file *m, void *data)
623{
624 struct drm_info_node *node = (struct drm_info_node *) m->private;
625 struct drm_device *dev = node->minor->dev;
626 drm_i915_private_t *dev_priv = dev->dev_private;
a2c7f6fd 627 struct intel_ring_buffer *ring;
9db4a9c7 628 int ret, i, pipe;
de227ef0
CW		 629
630 ret = mutex_lock_interruptible(&dev->struct_mutex);
631 if (ret)
632 return ret;
c8c8fb33 633 intel_runtime_pm_get(dev_priv);
2017263e 634
a123f157 635 if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 636 seq_printf(m, "Master Interrupt Control:\t%08x\n",
637 I915_READ(GEN8_MASTER_IRQ));
638
639 for (i = 0; i < 4; i++) {
640 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
641 i, I915_READ(GEN8_GT_IMR(i)));
642 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
643 i, I915_READ(GEN8_GT_IIR(i)));
644 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
645 i, I915_READ(GEN8_GT_IER(i)));
646 }
647
07d27e20 648 for_each_pipe(pipe) {
a123f157 649 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 650 pipe_name(pipe),
651 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 652 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 653 pipe_name(pipe),
654 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 655 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 656 pipe_name(pipe),
657 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 658 }
659
660 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
661 I915_READ(GEN8_DE_PORT_IMR));
662 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
663 I915_READ(GEN8_DE_PORT_IIR));
664 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
665 I915_READ(GEN8_DE_PORT_IER));
666
667 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
668 I915_READ(GEN8_DE_MISC_IMR));
669 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
670 I915_READ(GEN8_DE_MISC_IIR));
671 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
672 I915_READ(GEN8_DE_MISC_IER));
673
674 seq_printf(m, "PCU interrupt mask:\t%08x\n",
675 I915_READ(GEN8_PCU_IMR));
676 seq_printf(m, "PCU interrupt identity:\t%08x\n",
677 I915_READ(GEN8_PCU_IIR));
678 seq_printf(m, "PCU interrupt enable:\t%08x\n",
679 I915_READ(GEN8_PCU_IER));
680 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 681 seq_printf(m, "Display IER:\t%08x\n",
682 I915_READ(VLV_IER));
683 seq_printf(m, "Display IIR:\t%08x\n",
684 I915_READ(VLV_IIR));
685 seq_printf(m, "Display IIR_RW:\t%08x\n",
686 I915_READ(VLV_IIR_RW));
687 seq_printf(m, "Display IMR:\t%08x\n",
688 I915_READ(VLV_IMR));
689 for_each_pipe(pipe)
690 seq_printf(m, "Pipe %c stat:\t%08x\n",
691 pipe_name(pipe),
692 I915_READ(PIPESTAT(pipe)));
693
694 seq_printf(m, "Master IER:\t%08x\n",
695 I915_READ(VLV_MASTER_IER));
696
697 seq_printf(m, "Render IER:\t%08x\n",
698 I915_READ(GTIER));
699 seq_printf(m, "Render IIR:\t%08x\n",
700 I915_READ(GTIIR));
701 seq_printf(m, "Render IMR:\t%08x\n",
702 I915_READ(GTIMR));
703
704 seq_printf(m, "PM IER:\t\t%08x\n",
705 I915_READ(GEN6_PMIER));
706 seq_printf(m, "PM IIR:\t\t%08x\n",
707 I915_READ(GEN6_PMIIR));
708 seq_printf(m, "PM IMR:\t\t%08x\n",
709 I915_READ(GEN6_PMIMR));
710
711 seq_printf(m, "Port hotplug:\t%08x\n",
712 I915_READ(PORT_HOTPLUG_EN));
713 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
714 I915_READ(VLV_DPFLIPSTAT));
715 seq_printf(m, "DPINVGTT:\t%08x\n",
716 I915_READ(DPINVGTT));
717
718 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 719 seq_printf(m, "Interrupt enable: %08x\n",
720 I915_READ(IER));
721 seq_printf(m, "Interrupt identity: %08x\n",
722 I915_READ(IIR));
723 seq_printf(m, "Interrupt mask: %08x\n",
724 I915_READ(IMR));
9db4a9c7
JB		 725 for_each_pipe(pipe)
726 seq_printf(m, "Pipe %c stat: %08x\n",
727 pipe_name(pipe),
728 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 729 } else {
730 seq_printf(m, "North Display Interrupt enable: %08x\n",
731 I915_READ(DEIER));
732 seq_printf(m, "North Display Interrupt identity: %08x\n",
733 I915_READ(DEIIR));
734 seq_printf(m, "North Display Interrupt mask: %08x\n",
735 I915_READ(DEIMR));
736 seq_printf(m, "South Display Interrupt enable: %08x\n",
737 I915_READ(SDEIER));
738 seq_printf(m, "South Display Interrupt identity: %08x\n",
739 I915_READ(SDEIIR));
740 seq_printf(m, "South Display Interrupt mask: %08x\n",
741 I915_READ(SDEIMR));
742 seq_printf(m, "Graphics Interrupt enable: %08x\n",
743 I915_READ(GTIER));
744 seq_printf(m, "Graphics Interrupt identity: %08x\n",
745 I915_READ(GTIIR));
746 seq_printf(m, "Graphics Interrupt mask: %08x\n",
747 I915_READ(GTIMR));
748 }
a2c7f6fd 749 for_each_ring(ring, dev_priv, i) {
a123f157 750 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 751 seq_printf(m,
752 "Graphics Interrupt mask (%s): %08x\n",
753 ring->name, I915_READ_IMR(ring));
9862e600 754 }
a2c7f6fd 755 i915_ring_seqno_info(m, ring);
9862e600 756 }
c8c8fb33 757 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 758 mutex_unlock(&dev->struct_mutex);
759
2017263e
BG		 760 return 0;
761}
762
a6172a80
CW		 763static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
764{
765 struct drm_info_node *node = (struct drm_info_node *) m->private;
766 struct drm_device *dev = node->minor->dev;
767 drm_i915_private_t *dev_priv = dev->dev_private;
de227ef0
CW		 768 int i, ret;
769
770 ret = mutex_lock_interruptible(&dev->struct_mutex);
771 if (ret)
772 return ret;
a6172a80
CW		 773
774 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
775 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
776 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 777 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 778
6c085a72
CW		 779 seq_printf(m, "Fence %d, pin count = %d, object = ",
780 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 781 if (obj == NULL)
267f0c90 782 seq_puts(m, "unused");
c2c347a9 783 else
05394f39 784 describe_obj(m, obj);
267f0c90 785 seq_putc(m, '\n');
a6172a80
CW		 786 }
787
05394f39 788 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 789 return 0;
790}
791
2017263e
BG		 792static int i915_hws_info(struct seq_file *m, void *data)
793{
794 struct drm_info_node *node = (struct drm_info_node *) m->private;
795 struct drm_device *dev = node->minor->dev;
796 drm_i915_private_t *dev_priv = dev->dev_private;
4066c0ae 797 struct intel_ring_buffer *ring;
1a240d4d 798 const u32 *hws;
4066c0ae
CW		 799 int i;
800
1ec14ad3 801 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 802 hws = ring->status_page.page_addr;
2017263e
BG		 803 if (hws == NULL)
804 return 0;
805
806 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
807 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
808 i * 4,
809 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
810 }
811 return 0;
812}
813
d5442303
DV		 814static ssize_t
815i915_error_state_write(struct file *filp,
816 const char __user *ubuf,
817 size_t cnt,
818 loff_t *ppos)
819{
edc3d884 820 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 821 struct drm_device *dev = error_priv->dev;
22bcfc6a 822 int ret;
d5442303
DV		 823
824 DRM_DEBUG_DRIVER("Resetting error state\n");
825
22bcfc6a
DV		 826 ret = mutex_lock_interruptible(&dev->struct_mutex);
827 if (ret)
828 return ret;
829
d5442303
DV		 830 i915_destroy_error_state(dev);
831 mutex_unlock(&dev->struct_mutex);
832
833 return cnt;
834}
835
836static int i915_error_state_open(struct inode *inode, struct file *file)
837{
838 struct drm_device *dev = inode->i_private;
d5442303 839 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 840
841 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
842 if (!error_priv)
843 return -ENOMEM;
844
845 error_priv->dev = dev;
846
95d5bfb3 847 i915_error_state_get(dev, error_priv);
d5442303 848
edc3d884
MK		 849 file->private_data = error_priv;
850
851 return 0;
d5442303
DV		 852}
853
854static int i915_error_state_release(struct inode *inode, struct file *file)
855{
edc3d884 856 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 857
95d5bfb3 858 i915_error_state_put(error_priv);
d5442303
DV		 859 kfree(error_priv);
860
edc3d884
MK		 861 return 0;
862}
863
4dc955f7
MK		 864static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
865 size_t count, loff_t *pos)
866{
867 struct i915_error_state_file_priv *error_priv = file->private_data;
868 struct drm_i915_error_state_buf error_str;
869 loff_t tmp_pos = 0;
870 ssize_t ret_count = 0;
871 int ret;
872
873 ret = i915_error_state_buf_init(&error_str, count, *pos);
874 if (ret)
875 return ret;
edc3d884 876
fc16b48b 877 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 878 if (ret)
879 goto out;
880
edc3d884
MK		 881 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
882 error_str.buf,
883 error_str.bytes);
884
885 if (ret_count < 0)
886 ret = ret_count;
887 else
888 *pos = error_str.start + ret_count;
889out:
4dc955f7 890 i915_error_state_buf_release(&error_str);
edc3d884 891 return ret ?: ret_count;
d5442303
DV		 892}
893
894static const struct file_operations i915_error_state_fops = {
895 .owner = THIS_MODULE,
896 .open = i915_error_state_open,
edc3d884 897 .read = i915_error_state_read,
d5442303
DV		 898 .write = i915_error_state_write,
899 .llseek = default_llseek,
900 .release = i915_error_state_release,
901};
902
647416f9
KC		 903static int
904i915_next_seqno_get(void *data, u64 *val)
40633219 905{
647416f9 906 struct drm_device *dev = data;
40633219 907 drm_i915_private_t *dev_priv = dev->dev_private;
40633219
MK		 908 int ret;
909
910 ret = mutex_lock_interruptible(&dev->struct_mutex);
911 if (ret)
912 return ret;
913
647416f9 914 *val = dev_priv->next_seqno;
40633219
MK		 915 mutex_unlock(&dev->struct_mutex);
916
647416f9 917 return 0;
40633219
MK		 918}
919
647416f9
KC		 920static int
921i915_next_seqno_set(void *data, u64 val)
922{
923 struct drm_device *dev = data;
40633219
MK		 924 int ret;
925
40633219
MK		 926 ret = mutex_lock_interruptible(&dev->struct_mutex);
927 if (ret)
928 return ret;
929
e94fbaa8 930 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 931 mutex_unlock(&dev->struct_mutex);
932
647416f9 933 return ret;
40633219
MK		 934}
935
647416f9
KC		 936DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
937 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 938 "0x%llx\n");
40633219 939
f97108d1
JB		 940static int i915_rstdby_delays(struct seq_file *m, void *unused)
941{
942 struct drm_info_node *node = (struct drm_info_node *) m->private;
943 struct drm_device *dev = node->minor->dev;
944 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 945 u16 crstanddelay;
946 int ret;
947
948 ret = mutex_lock_interruptible(&dev->struct_mutex);
949 if (ret)
950 return ret;
c8c8fb33 951 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 952
953 crstanddelay = I915_READ16(CRSTANDVID);
954
c8c8fb33 955 intel_runtime_pm_put(dev_priv);
616fdb5a 956 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 957
958 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
959
960 return 0;
961}
962
963static int i915_cur_delayinfo(struct seq_file *m, void *unused)
964{
965 struct drm_info_node *node = (struct drm_info_node *) m->private;
966 struct drm_device *dev = node->minor->dev;
967 drm_i915_private_t *dev_priv = dev->dev_private;
c8c8fb33
PZ		 968 int ret = 0;
969
970 intel_runtime_pm_get(dev_priv);
3b8d8d91 971
5c9669ce
TR		 972 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
973
3b8d8d91
JB		 974 if (IS_GEN5(dev)) {
975 u16 rgvswctl = I915_READ16(MEMSWCTL);
976 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
977
978 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
979 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
980 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
981 MEMSTAT_VID_SHIFT);
982 seq_printf(m, "Current P-state: %d\n",
983 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
0a073b84 984 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3b8d8d91
JB		 985 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
986 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
987 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8e8c06cd 988 u32 rpstat, cagf, reqf;
ccab5c82
JB		 989 u32 rpupei, rpcurup, rpprevup;
990 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 991 int max_freq;
992
993 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 994 ret = mutex_lock_interruptible(&dev->struct_mutex);
995 if (ret)
c8c8fb33 996 goto out;
d1ebd816 997
c8d9a590 998 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 999
8e8c06cd
CW		 1000 reqf = I915_READ(GEN6_RPNSWREQ);
1001 reqf &= ~GEN6_TURBO_DISABLE;
1002 if (IS_HASWELL(dev))
1003 reqf >>= 24;
1004 else
1005 reqf >>= 25;
1006 reqf *= GT_FREQUENCY_MULTIPLIER;
1007
ccab5c82
JB		 1008 rpstat = I915_READ(GEN6_RPSTAT1);
1009 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1010 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1011 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1012 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1013 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1014 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
f82855d3
BW		 1015 if (IS_HASWELL(dev))
1016 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1017 else
1018 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1019 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1020
c8d9a590 1021 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1022 mutex_unlock(&dev->struct_mutex);
1023
3b8d8d91 1024 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
ccab5c82 1025 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
3b8d8d91
JB		 1026 seq_printf(m, "Render p-state ratio: %d\n",
1027 (gt_perf_status & 0xff00) >> 8);
1028 seq_printf(m, "Render p-state VID: %d\n",
1029 gt_perf_status & 0xff);
1030 seq_printf(m, "Render p-state limit: %d\n",
1031 rp_state_limits & 0xff);
8e8c06cd 1032 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1033 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1034 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1035 GEN6_CURICONT_MASK);
1036 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1037 GEN6_CURBSYTAVG_MASK);
1038 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1039 GEN6_CURBSYTAVG_MASK);
1040 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1041 GEN6_CURIAVG_MASK);
1042 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1043 GEN6_CURBSYTAVG_MASK);
1044 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1045 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1046
1047 max_freq = (rp_state_cap & 0xff0000) >> 16;
1048 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1049 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1050
1051 max_freq = (rp_state_cap & 0xff00) >> 8;
1052 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1053 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1054
1055 max_freq = rp_state_cap & 0xff;
1056 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1057 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1058
1059 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1060 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 1061 } else if (IS_VALLEYVIEW(dev)) {
1062 u32 freq_sts, val;
1063
259bd5d4 1064 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1065 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1066 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1067 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1068
c5bd2bf6 1069 val = valleyview_rps_max_freq(dev_priv);
0a073b84 1070 seq_printf(m, "max GPU freq: %d MHz\n",
2ec3815f 1071 vlv_gpu_freq(dev_priv, val));
0a073b84 1072
c5bd2bf6 1073 val = valleyview_rps_min_freq(dev_priv);
0a073b84 1074 seq_printf(m, "min GPU freq: %d MHz\n",
2ec3815f 1075 vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 1076
1077 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1078 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1079 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1080 } else {
267f0c90 1081 seq_puts(m, "no P-state info available\n");
3b8d8d91 1082 }
f97108d1 1083
c8c8fb33
PZ		 1084out:
1085 intel_runtime_pm_put(dev_priv);
1086 return ret;
f97108d1
JB		 1087}
1088
1089static int i915_delayfreq_table(struct seq_file *m, void *unused)
1090{
1091 struct drm_info_node *node = (struct drm_info_node *) m->private;
1092 struct drm_device *dev = node->minor->dev;
1093 drm_i915_private_t *dev_priv = dev->dev_private;
1094 u32 delayfreq;
616fdb5a
BW		 1095 int ret, i;
1096
1097 ret = mutex_lock_interruptible(&dev->struct_mutex);
1098 if (ret)
1099 return ret;
c8c8fb33 1100 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1101
1102 for (i = 0; i < 16; i++) {
1103 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
7648fa99
JB		 1104 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1105 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
f97108d1
JB		 1106 }
1107
c8c8fb33
PZ		 1108 intel_runtime_pm_put(dev_priv);
1109
616fdb5a
BW		 1110 mutex_unlock(&dev->struct_mutex);
1111
f97108d1
JB		 1112 return 0;
1113}
1114
1115static inline int MAP_TO_MV(int map)
1116{
1117 return 1250 - (map * 25);
1118}
1119
1120static int i915_inttoext_table(struct seq_file *m, void *unused)
1121{
1122 struct drm_info_node *node = (struct drm_info_node *) m->private;
1123 struct drm_device *dev = node->minor->dev;
1124 drm_i915_private_t *dev_priv = dev->dev_private;
1125 u32 inttoext;
616fdb5a
BW		 1126 int ret, i;
1127
1128 ret = mutex_lock_interruptible(&dev->struct_mutex);
1129 if (ret)
1130 return ret;
c8c8fb33 1131 intel_runtime_pm_get(dev_priv);
f97108d1
JB		 1132
1133 for (i = 1; i <= 32; i++) {
1134 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1135 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1136 }
1137
c8c8fb33 1138 intel_runtime_pm_put(dev_priv);
616fdb5a
BW		 1139 mutex_unlock(&dev->struct_mutex);
1140
f97108d1
JB		 1141 return 0;
1142}
1143
4d85529d 1144static int ironlake_drpc_info(struct seq_file *m)
f97108d1
JB		 1145{
1146 struct drm_info_node *node = (struct drm_info_node *) m->private;
1147 struct drm_device *dev = node->minor->dev;
1148 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1149 u32 rgvmodectl, rstdbyctl;
1150 u16 crstandvid;
1151 int ret;
1152
1153 ret = mutex_lock_interruptible(&dev->struct_mutex);
1154 if (ret)
1155 return ret;
c8c8fb33 1156 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1157
1158 rgvmodectl = I915_READ(MEMMODECTL);
1159 rstdbyctl = I915_READ(RSTDBYCTL);
1160 crstandvid = I915_READ16(CRSTANDVID);
1161
c8c8fb33 1162 intel_runtime_pm_put(dev_priv);
616fdb5a 1163 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1164
1165 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1166 "yes" : "no");
1167 seq_printf(m, "Boost freq: %d\n",
1168 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1169 MEMMODE_BOOST_FREQ_SHIFT);
1170 seq_printf(m, "HW control enabled: %s\n",
1171 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1172 seq_printf(m, "SW control enabled: %s\n",
1173 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1174 seq_printf(m, "Gated voltage change: %s\n",
1175 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1176 seq_printf(m, "Starting frequency: P%d\n",
1177 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1178 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1179 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1180 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1181 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1182 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1183 seq_printf(m, "Render standby enabled: %s\n",
1184 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1185 seq_puts(m, "Current RS state: ");
88271da3
JB		 1186 switch (rstdbyctl & RSX_STATUS_MASK) {
1187 case RSX_STATUS_ON:
267f0c90 1188 seq_puts(m, "on\n");
88271da3
JB		 1189 break;
1190 case RSX_STATUS_RC1:
267f0c90 1191 seq_puts(m, "RC1\n");
88271da3
JB		 1192 break;
1193 case RSX_STATUS_RC1E:
267f0c90 1194 seq_puts(m, "RC1E\n");
88271da3
JB		 1195 break;
1196 case RSX_STATUS_RS1:
267f0c90 1197 seq_puts(m, "RS1\n");
88271da3
JB		 1198 break;
1199 case RSX_STATUS_RS2:
267f0c90 1200 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1201 break;
1202 case RSX_STATUS_RS3:
267f0c90 1203 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1204 break;
1205 default:
267f0c90 1206 seq_puts(m, "unknown\n");
88271da3
JB		 1207 break;
1208 }
f97108d1
JB		 1209
1210 return 0;
1211}
1212
669ab5aa
D		 1213static int vlv_drpc_info(struct seq_file *m)
1214{
1215
1216 struct drm_info_node *node = (struct drm_info_node *) m->private;
1217 struct drm_device *dev = node->minor->dev;
1218 struct drm_i915_private *dev_priv = dev->dev_private;
1219 u32 rpmodectl1, rcctl1;
1220 unsigned fw_rendercount = 0, fw_mediacount = 0;
1221
1222 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1223 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1224
1225 seq_printf(m, "Video Turbo Mode: %s\n",
1226 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1227 seq_printf(m, "Turbo enabled: %s\n",
1228 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1229 seq_printf(m, "HW control enabled: %s\n",
1230 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1231 seq_printf(m, "SW control enabled: %s\n",
1232 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1233 GEN6_RP_MEDIA_SW_MODE));
1234 seq_printf(m, "RC6 Enabled: %s\n",
1235 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1236 GEN6_RC_CTL_EI_MODE(1))));
1237 seq_printf(m, "Render Power Well: %s\n",
1238 (I915_READ(VLV_GTLC_PW_STATUS) &
1239 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1240 seq_printf(m, "Media Power Well: %s\n",
1241 (I915_READ(VLV_GTLC_PW_STATUS) &
1242 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1243
1244 spin_lock_irq(&dev_priv->uncore.lock);
1245 fw_rendercount = dev_priv->uncore.fw_rendercount;
1246 fw_mediacount = dev_priv->uncore.fw_mediacount;
1247 spin_unlock_irq(&dev_priv->uncore.lock);
1248
1249 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1250 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1251
1252
1253 return 0;
1254}
1255
1256
4d85529d
BW		 1257static int gen6_drpc_info(struct seq_file *m)
1258{
1259
1260 struct drm_info_node *node = (struct drm_info_node *) m->private;
1261 struct drm_device *dev = node->minor->dev;
1262 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1263 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1264 unsigned forcewake_count;
aee56cff 1265 int count = 0, ret;
4d85529d
BW		 1266
1267 ret = mutex_lock_interruptible(&dev->struct_mutex);
1268 if (ret)
1269 return ret;
c8c8fb33 1270 intel_runtime_pm_get(dev_priv);
4d85529d 1271
907b28c5
CW		 1272 spin_lock_irq(&dev_priv->uncore.lock);
1273 forcewake_count = dev_priv->uncore.forcewake_count;
1274 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1275
1276 if (forcewake_count) {
267f0c90
DL		 1277 seq_puts(m, "RC information inaccurate because somebody "
1278 "holds a forcewake reference \n");
4d85529d
BW		 1279 } else {
1280 /* NB: we cannot use forcewake, else we read the wrong values */
1281 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1282 udelay(10);
1283 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1284 }
1285
1286 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1287 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1288
1289 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1290 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1291 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1292 mutex_lock(&dev_priv->rps.hw_lock);
1293 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1294 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1295
c8c8fb33
PZ		 1296 intel_runtime_pm_put(dev_priv);
1297
4d85529d
BW		 1298 seq_printf(m, "Video Turbo Mode: %s\n",
1299 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1300 seq_printf(m, "HW control enabled: %s\n",
1301 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1302 seq_printf(m, "SW control enabled: %s\n",
1303 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1304 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1305 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1306 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1307 seq_printf(m, "RC6 Enabled: %s\n",
1308 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1309 seq_printf(m, "Deep RC6 Enabled: %s\n",
1310 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1311 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1312 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1313 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1314 switch (gt_core_status & GEN6_RCn_MASK) {
1315 case GEN6_RC0:
1316 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1317 seq_puts(m, "Core Power Down\n");
4d85529d 1318 else
267f0c90 1319 seq_puts(m, "on\n");
4d85529d
BW		 1320 break;
1321 case GEN6_RC3:
267f0c90 1322 seq_puts(m, "RC3\n");
4d85529d
BW		 1323 break;
1324 case GEN6_RC6:
267f0c90 1325 seq_puts(m, "RC6\n");
4d85529d
BW		 1326 break;
1327 case GEN6_RC7:
267f0c90 1328 seq_puts(m, "RC7\n");
4d85529d
BW		 1329 break;
1330 default:
267f0c90 1331 seq_puts(m, "Unknown\n");
4d85529d
BW		 1332 break;
1333 }
1334
1335 seq_printf(m, "Core Power Down: %s\n",
1336 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1337
1338 /* Not exactly sure what this is */
1339 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1340 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1341 seq_printf(m, "RC6 residency since boot: %u\n",
1342 I915_READ(GEN6_GT_GFX_RC6));
1343 seq_printf(m, "RC6+ residency since boot: %u\n",
1344 I915_READ(GEN6_GT_GFX_RC6p));
1345 seq_printf(m, "RC6++ residency since boot: %u\n",
1346 I915_READ(GEN6_GT_GFX_RC6pp));
1347
ecd8faea
BW		 1348 seq_printf(m, "RC6 voltage: %dmV\n",
1349 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1350 seq_printf(m, "RC6+ voltage: %dmV\n",
1351 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1352 seq_printf(m, "RC6++ voltage: %dmV\n",
1353 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1354 return 0;
1355}
1356
1357static int i915_drpc_info(struct seq_file *m, void *unused)
1358{
1359 struct drm_info_node *node = (struct drm_info_node *) m->private;
1360 struct drm_device *dev = node->minor->dev;
1361
669ab5aa
D		 1362 if (IS_VALLEYVIEW(dev))
1363 return vlv_drpc_info(m);
1364 else if (IS_GEN6(dev) || IS_GEN7(dev))
4d85529d
BW		 1365 return gen6_drpc_info(m);
1366 else
1367 return ironlake_drpc_info(m);
1368}
1369
b5e50c3f
JB		 1370static int i915_fbc_status(struct seq_file *m, void *unused)
1371{
1372 struct drm_info_node *node = (struct drm_info_node *) m->private;
1373 struct drm_device *dev = node->minor->dev;
b5e50c3f 1374 drm_i915_private_t *dev_priv = dev->dev_private;
b5e50c3f 1375
3a77c4c4 1376 if (!HAS_FBC(dev)) {
267f0c90 1377 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1378 return 0;
1379 }
1380
36623ef8
PZ		 1381 intel_runtime_pm_get(dev_priv);
1382
ee5382ae 1383 if (intel_fbc_enabled(dev)) {
267f0c90 1384 seq_puts(m, "FBC enabled\n");
b5e50c3f 1385 } else {
267f0c90 1386 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1387 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1388 case FBC_OK:
1389 seq_puts(m, "FBC actived, but currently disabled in hardware");
1390 break;
1391 case FBC_UNSUPPORTED:
1392 seq_puts(m, "unsupported by this chipset");
1393 break;
bed4a673 1394 case FBC_NO_OUTPUT:
267f0c90 1395 seq_puts(m, "no outputs");
bed4a673 1396 break;
b5e50c3f 1397 case FBC_STOLEN_TOO_SMALL:
267f0c90 1398 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1399 break;
1400 case FBC_UNSUPPORTED_MODE:
267f0c90 1401 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1402 break;
1403 case FBC_MODE_TOO_LARGE:
267f0c90 1404 seq_puts(m, "mode too large");
b5e50c3f
JB		 1405 break;
1406 case FBC_BAD_PLANE:
267f0c90 1407 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1408 break;
1409 case FBC_NOT_TILED:
267f0c90 1410 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1411 break;
9c928d16 1412 case FBC_MULTIPLE_PIPES:
267f0c90 1413 seq_puts(m, "multiple pipes are enabled");
9c928d16 1414 break;
c1a9f047 1415 case FBC_MODULE_PARAM:
267f0c90 1416 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1417 break;
8a5729a3 1418 case FBC_CHIP_DEFAULT:
267f0c90 1419 seq_puts(m, "disabled per chip default");
8a5729a3 1420 break;
b5e50c3f 1421 default:
267f0c90 1422 seq_puts(m, "unknown reason");
b5e50c3f 1423 }
267f0c90 1424 seq_putc(m, '\n');
b5e50c3f 1425 }
36623ef8
PZ		 1426
1427 intel_runtime_pm_put(dev_priv);
1428
b5e50c3f
JB		 1429 return 0;
1430}
1431
92d44621
PZ		 1432static int i915_ips_status(struct seq_file *m, void *unused)
1433{
1434 struct drm_info_node *node = (struct drm_info_node *) m->private;
1435 struct drm_device *dev = node->minor->dev;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437
f5adf94e 1438 if (!HAS_IPS(dev)) {
92d44621
PZ		 1439 seq_puts(m, "not supported\n");
1440 return 0;
1441 }
1442
36623ef8
PZ		 1443 intel_runtime_pm_get(dev_priv);
1444
e59150dc 1445 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
92d44621
PZ		 1446 seq_puts(m, "enabled\n");
1447 else
1448 seq_puts(m, "disabled\n");
1449
36623ef8
PZ		 1450 intel_runtime_pm_put(dev_priv);
1451
92d44621
PZ		 1452 return 0;
1453}
1454
4a9bef37
JB		 1455static int i915_sr_status(struct seq_file *m, void *unused)
1456{
1457 struct drm_info_node *node = (struct drm_info_node *) m->private;
1458 struct drm_device *dev = node->minor->dev;
1459 drm_i915_private_t *dev_priv = dev->dev_private;
1460 bool sr_enabled = false;
1461
36623ef8
PZ		 1462 intel_runtime_pm_get(dev_priv);
1463
1398261a 1464 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1465 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1466 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1467 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1468 else if (IS_I915GM(dev))
1469 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1470 else if (IS_PINEVIEW(dev))
1471 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1472
36623ef8
PZ		 1473 intel_runtime_pm_put(dev_priv);
1474
5ba2aaaa
CW		 1475 seq_printf(m, "self-refresh: %s\n",
1476 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1477
1478 return 0;
1479}
1480
7648fa99
JB		 1481static int i915_emon_status(struct seq_file *m, void *unused)
1482{
1483 struct drm_info_node *node = (struct drm_info_node *) m->private;
1484 struct drm_device *dev = node->minor->dev;
1485 drm_i915_private_t *dev_priv = dev->dev_private;
1486 unsigned long temp, chipset, gfx;
de227ef0
CW		 1487 int ret;
1488
582be6b4
CW		 1489 if (!IS_GEN5(dev))
1490 return -ENODEV;
1491
de227ef0
CW		 1492 ret = mutex_lock_interruptible(&dev->struct_mutex);
1493 if (ret)
1494 return ret;
7648fa99
JB		 1495
1496 temp = i915_mch_val(dev_priv);
1497 chipset = i915_chipset_val(dev_priv);
1498 gfx = i915_gfx_val(dev_priv);
de227ef0 1499 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1500
1501 seq_printf(m, "GMCH temp: %ld\n", temp);
1502 seq_printf(m, "Chipset power: %ld\n", chipset);
1503 seq_printf(m, "GFX power: %ld\n", gfx);
1504 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1505
1506 return 0;
1507}
1508
23b2f8bb
JB		 1509static int i915_ring_freq_table(struct seq_file *m, void *unused)
1510{
1511 struct drm_info_node *node = (struct drm_info_node *) m->private;
1512 struct drm_device *dev = node->minor->dev;
1513 drm_i915_private_t *dev_priv = dev->dev_private;
5bfa0199 1514 int ret = 0;
23b2f8bb
JB		 1515 int gpu_freq, ia_freq;
1516
1c70c0ce 1517 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1518 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1519 return 0;
1520 }
1521
5bfa0199
PZ		 1522 intel_runtime_pm_get(dev_priv);
1523
5c9669ce
TR		 1524 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1525
4fc688ce 1526 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1527 if (ret)
5bfa0199 1528 goto out;
23b2f8bb 1529
267f0c90 1530 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1531
b39fb297
BW		 1532 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1533 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1534 gpu_freq++) {
42c0526c
BW		 1535 ia_freq = gpu_freq;
1536 sandybridge_pcode_read(dev_priv,
1537 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1538 &ia_freq);
3ebecd07
CW		 1539 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1540 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1541 ((ia_freq >> 0) & 0xff) * 100,
1542 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1543 }
1544
4fc688ce 1545 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1546
5bfa0199
PZ		 1547out:
1548 intel_runtime_pm_put(dev_priv);
1549 return ret;
23b2f8bb
JB		 1550}
1551
7648fa99
JB		 1552static int i915_gfxec(struct seq_file *m, void *unused)
1553{
1554 struct drm_info_node *node = (struct drm_info_node *) m->private;
1555 struct drm_device *dev = node->minor->dev;
1556 drm_i915_private_t *dev_priv = dev->dev_private;
616fdb5a
BW		 1557 int ret;
1558
1559 ret = mutex_lock_interruptible(&dev->struct_mutex);
1560 if (ret)
1561 return ret;
c8c8fb33 1562 intel_runtime_pm_get(dev_priv);
7648fa99
JB		 1563
1564 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
c8c8fb33 1565 intel_runtime_pm_put(dev_priv);
7648fa99 1566
616fdb5a
BW		 1567 mutex_unlock(&dev->struct_mutex);
1568
7648fa99
JB		 1569 return 0;
1570}
1571
44834a67
CW		 1572static int i915_opregion(struct seq_file *m, void *unused)
1573{
1574 struct drm_info_node *node = (struct drm_info_node *) m->private;
1575 struct drm_device *dev = node->minor->dev;
1576 drm_i915_private_t *dev_priv = dev->dev_private;
1577 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1578 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1579 int ret;
1580
0d38f009
DV		 1581 if (data == NULL)
1582 return -ENOMEM;
1583
44834a67
CW		 1584 ret = mutex_lock_interruptible(&dev->struct_mutex);
1585 if (ret)
0d38f009 1586 goto out;
44834a67 1587
0d38f009
DV		 1588 if (opregion->header) {
1589 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1590 seq_write(m, data, OPREGION_SIZE);
1591 }
44834a67
CW		 1592
1593 mutex_unlock(&dev->struct_mutex);
1594
0d38f009
DV		 1595out:
1596 kfree(data);
44834a67
CW		 1597 return 0;
1598}
1599
37811fcc
CW		 1600static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1601{
1602 struct drm_info_node *node = (struct drm_info_node *) m->private;
1603 struct drm_device *dev = node->minor->dev;
4520f53a 1604 struct intel_fbdev *ifbdev = NULL;
37811fcc 1605 struct intel_framebuffer *fb;
37811fcc 1606
4520f53a
DV		 1607#ifdef CONFIG_DRM_I915_FBDEV
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
37811fcc
CW		 1610 if (ret)
1611 return ret;
1612
1613 ifbdev = dev_priv->fbdev;
1614 fb = to_intel_framebuffer(ifbdev->helper.fb);
1615
623f9783 1616 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1617 fb->base.width,
1618 fb->base.height,
1619 fb->base.depth,
623f9783
DV		 1620 fb->base.bits_per_pixel,
1621 atomic_read(&fb->base.refcount.refcount));
05394f39 1622 describe_obj(m, fb->obj);
267f0c90 1623 seq_putc(m, '\n');
4b096ac1 1624 mutex_unlock(&dev->mode_config.mutex);
4520f53a 1625#endif
37811fcc 1626
4b096ac1 1627 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1628 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1629 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1630 continue;
1631
623f9783 1632 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1633 fb->base.width,
1634 fb->base.height,
1635 fb->base.depth,
623f9783
DV		 1636 fb->base.bits_per_pixel,
1637 atomic_read(&fb->base.refcount.refcount));
05394f39 1638 describe_obj(m, fb->obj);
267f0c90 1639 seq_putc(m, '\n');
37811fcc 1640 }
4b096ac1 1641 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1642
1643 return 0;
1644}
1645
e76d3630
BW		 1646static int i915_context_status(struct seq_file *m, void *unused)
1647{
1648 struct drm_info_node *node = (struct drm_info_node *) m->private;
1649 struct drm_device *dev = node->minor->dev;
1650 drm_i915_private_t *dev_priv = dev->dev_private;
a168c293 1651 struct intel_ring_buffer *ring;
a33afea5 1652 struct i915_hw_context *ctx;
a168c293 1653 int ret, i;
e76d3630
BW		 1654
1655 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1656 if (ret)
1657 return ret;
1658
3e373948 1659 if (dev_priv->ips.pwrctx) {
267f0c90 1660 seq_puts(m, "power context ");
3e373948 1661 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1662 seq_putc(m, '\n');
dc501fbc 1663 }
e76d3630 1664
3e373948 1665 if (dev_priv->ips.renderctx) {
267f0c90 1666 seq_puts(m, "render context ");
3e373948 1667 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1668 seq_putc(m, '\n');
dc501fbc 1669 }
e76d3630 1670
a33afea5
BW		 1671 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1672 seq_puts(m, "HW context ");
3ccfd19d 1673 describe_ctx(m, ctx);
a33afea5
BW		 1674 for_each_ring(ring, dev_priv, i)
1675 if (ring->default_context == ctx)
1676 seq_printf(m, "(default context %s) ", ring->name);
1677
1678 describe_obj(m, ctx->obj);
1679 seq_putc(m, '\n');
a168c293
BW		 1680 }
1681
e76d3630
BW		 1682 mutex_unlock(&dev->mode_config.mutex);
1683
1684 return 0;
1685}
1686
6d794d42
BW		 1687static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1688{
1689 struct drm_info_node *node = (struct drm_info_node *) m->private;
1690 struct drm_device *dev = node->minor->dev;
1691 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1692 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1693
907b28c5 1694 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1695 if (IS_VALLEYVIEW(dev)) {
1696 fw_rendercount = dev_priv->uncore.fw_rendercount;
1697 fw_mediacount = dev_priv->uncore.fw_mediacount;
1698 } else
1699 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1700 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1701
43709ba0
D		 1702 if (IS_VALLEYVIEW(dev)) {
1703 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1704 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1705 } else
1706 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1707
1708 return 0;
1709}
1710
ea16a3cd
DV		 1711static const char *swizzle_string(unsigned swizzle)
1712{
aee56cff 1713 switch (swizzle) {
ea16a3cd
DV		 1714 case I915_BIT_6_SWIZZLE_NONE:
1715 return "none";
1716 case I915_BIT_6_SWIZZLE_9:
1717 return "bit9";
1718 case I915_BIT_6_SWIZZLE_9_10:
1719 return "bit9/bit10";
1720 case I915_BIT_6_SWIZZLE_9_11:
1721 return "bit9/bit11";
1722 case I915_BIT_6_SWIZZLE_9_10_11:
1723 return "bit9/bit10/bit11";
1724 case I915_BIT_6_SWIZZLE_9_17:
1725 return "bit9/bit17";
1726 case I915_BIT_6_SWIZZLE_9_10_17:
1727 return "bit9/bit10/bit17";
1728 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1729 return "unknown";
ea16a3cd
DV		 1730 }
1731
1732 return "bug";
1733}
1734
1735static int i915_swizzle_info(struct seq_file *m, void *data)
1736{
1737 struct drm_info_node *node = (struct drm_info_node *) m->private;
1738 struct drm_device *dev = node->minor->dev;
1739 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1740 int ret;
1741
1742 ret = mutex_lock_interruptible(&dev->struct_mutex);
1743 if (ret)
1744 return ret;
c8c8fb33 1745 intel_runtime_pm_get(dev_priv);
ea16a3cd 1746
ea16a3cd
DV		 1747 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1748 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1749 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1750 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1751
1752 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1753 seq_printf(m, "DDC = 0x%08x\n",
1754 I915_READ(DCC));
1755 seq_printf(m, "C0DRB3 = 0x%04x\n",
1756 I915_READ16(C0DRB3));
1757 seq_printf(m, "C1DRB3 = 0x%04x\n",
1758 I915_READ16(C1DRB3));
9d3203e1 1759 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1760 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1761 I915_READ(MAD_DIMM_C0));
1762 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1763 I915_READ(MAD_DIMM_C1));
1764 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1765 I915_READ(MAD_DIMM_C2));
1766 seq_printf(m, "TILECTL = 0x%08x\n",
1767 I915_READ(TILECTL));
9d3203e1
BW		 1768 if (IS_GEN8(dev))
1769 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1770 I915_READ(GAMTARBMODE));
1771 else
1772 seq_printf(m, "ARB_MODE = 0x%08x\n",
1773 I915_READ(ARB_MODE));
3fa7d235
DV		 1774 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1775 I915_READ(DISP_ARB_CTL));
ea16a3cd 1776 }
c8c8fb33 1777 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 1778 mutex_unlock(&dev->struct_mutex);
1779
1780 return 0;
1781}
1782
1c60fef5
BW		 1783static int per_file_ctx(int id, void *ptr, void *data)
1784{
1785 struct i915_hw_context *ctx = ptr;
1786 struct seq_file *m = data;
1787 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1788
1789 ppgtt->debug_dump(ppgtt, m);
1790
1791 return 0;
1792}
1793
77df6772 1794static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 1795{
3cf17fc5
DV		 1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797 struct intel_ring_buffer *ring;
77df6772
BW		 1798 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1799 int unused, i;
3cf17fc5 1800
77df6772
BW		 1801 if (!ppgtt)
1802 return;
1803
1804 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 1805 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 1806 for_each_ring(ring, dev_priv, unused) {
1807 seq_printf(m, "%s\n", ring->name);
1808 for (i = 0; i < 4; i++) {
1809 u32 offset = 0x270 + i * 8;
1810 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1811 pdp <<= 32;
1812 pdp |= I915_READ(ring->mmio_base + offset);
1813 for (i = 0; i < 4; i++)
1814 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1815 }
1816 }
1817}
1818
1819static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1820{
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 struct intel_ring_buffer *ring;
1c60fef5 1823 struct drm_file *file;
77df6772 1824 int i;
3cf17fc5 1825
3cf17fc5
DV		 1826 if (INTEL_INFO(dev)->gen == 6)
1827 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1828
a2c7f6fd 1829 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1830 seq_printf(m, "%s\n", ring->name);
1831 if (INTEL_INFO(dev)->gen == 7)
1832 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1833 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1834 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1835 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1836 }
1837 if (dev_priv->mm.aliasing_ppgtt) {
1838 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1839
267f0c90 1840 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 1841 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 1842
87d60b63 1843 ppgtt->debug_dump(ppgtt, m);
1c60fef5
BW		 1844 } else
1845 return;
1846
1847 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1848 struct drm_i915_file_private *file_priv = file->driver_priv;
1849 struct i915_hw_ppgtt *pvt_ppgtt;
1850
1851 pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx);
1852 seq_printf(m, "proc: %s\n",
1853 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1854 seq_puts(m, " default context:\n");
1855 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 1856 }
1857 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 1858}
1859
1860static int i915_ppgtt_info(struct seq_file *m, void *data)
1861{
1862 struct drm_info_node *node = (struct drm_info_node *) m->private;
1863 struct drm_device *dev = node->minor->dev;
c8c8fb33 1864 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 1865
1866 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1867 if (ret)
1868 return ret;
c8c8fb33 1869 intel_runtime_pm_get(dev_priv);
77df6772
BW		 1870
1871 if (INTEL_INFO(dev)->gen >= 8)
1872 gen8_ppgtt_info(m, dev);
1873 else if (INTEL_INFO(dev)->gen >= 6)
1874 gen6_ppgtt_info(m, dev);
1875
c8c8fb33 1876 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 1877 mutex_unlock(&dev->struct_mutex);
1878
1879 return 0;
1880}
1881
57f350b6
JB		 1882static int i915_dpio_info(struct seq_file *m, void *data)
1883{
1884 struct drm_info_node *node = (struct drm_info_node *) m->private;
1885 struct drm_device *dev = node->minor->dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 int ret;
1888
1889
1890 if (!IS_VALLEYVIEW(dev)) {
267f0c90 1891 seq_puts(m, "unsupported\n");
57f350b6
JB		 1892 return 0;
1893 }
1894
09153000 1895 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
57f350b6
JB		 1896 if (ret)
1897 return ret;
1898
1899 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1900
ab3c759a
CML		 1901 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1902 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1903 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1904 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1905
1906 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1907 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1908 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1909 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1910
1911 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1912 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1913 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1914 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1915
1916 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1917 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1918 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1919 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
57f350b6
JB		 1920
1921 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
ab3c759a 1922 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
57f350b6 1923
09153000 1924 mutex_unlock(&dev_priv->dpio_lock);
57f350b6
JB		 1925
1926 return 0;
1927}
1928
63573eb7
BW		 1929static int i915_llc(struct seq_file *m, void *data)
1930{
1931 struct drm_info_node *node = (struct drm_info_node *) m->private;
1932 struct drm_device *dev = node->minor->dev;
1933 struct drm_i915_private *dev_priv = dev->dev_private;
1934
1935 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1936 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1937 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1938
1939 return 0;
1940}
1941
e91fd8c6
RV		 1942static int i915_edp_psr_status(struct seq_file *m, void *data)
1943{
1944 struct drm_info_node *node = m->private;
1945 struct drm_device *dev = node->minor->dev;
1946 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1947 u32 psrperf = 0;
1948 bool enabled = false;
e91fd8c6 1949
c8c8fb33
PZ		 1950 intel_runtime_pm_get(dev_priv);
1951
a031d709
RV		 1952 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1953 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
e91fd8c6 1954
a031d709
RV		 1955 enabled = HAS_PSR(dev) &&
1956 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1957 seq_printf(m, "Enabled: %s\n", yesno(enabled));
e91fd8c6 1958
a031d709
RV		 1959 if (HAS_PSR(dev))
1960 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1961 EDP_PSR_PERF_CNT_MASK;
1962 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6 1963
c8c8fb33 1964 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 1965 return 0;
1966}
1967
d2e216d0
RV		 1968static int i915_sink_crc(struct seq_file *m, void *data)
1969{
1970 struct drm_info_node *node = m->private;
1971 struct drm_device *dev = node->minor->dev;
1972 struct intel_encoder *encoder;
1973 struct intel_connector *connector;
1974 struct intel_dp *intel_dp = NULL;
1975 int ret;
1976 u8 crc[6];
1977
1978 drm_modeset_lock_all(dev);
1979 list_for_each_entry(connector, &dev->mode_config.connector_list,
1980 base.head) {
1981
1982 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1983 continue;
1984
b6ae3c7c
PZ		 1985 if (!connector->base.encoder)
1986 continue;
1987
d2e216d0
RV		 1988 encoder = to_intel_encoder(connector->base.encoder);
1989 if (encoder->type != INTEL_OUTPUT_EDP)
1990 continue;
1991
1992 intel_dp = enc_to_intel_dp(&encoder->base);
1993
1994 ret = intel_dp_sink_crc(intel_dp, crc);
1995 if (ret)
1996 goto out;
1997
1998 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1999 crc[0], crc[1], crc[2],
2000 crc[3], crc[4], crc[5]);
2001 goto out;
2002 }
2003 ret = -ENODEV;
2004out:
2005 drm_modeset_unlock_all(dev);
2006 return ret;
2007}
2008
ec013e7f
JB		 2009static int i915_energy_uJ(struct seq_file *m, void *data)
2010{
2011 struct drm_info_node *node = m->private;
2012 struct drm_device *dev = node->minor->dev;
2013 struct drm_i915_private *dev_priv = dev->dev_private;
2014 u64 power;
2015 u32 units;
2016
2017 if (INTEL_INFO(dev)->gen < 6)
2018 return -ENODEV;
2019
36623ef8
PZ		 2020 intel_runtime_pm_get(dev_priv);
2021
ec013e7f
JB		 2022 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2023 power = (power & 0x1f00) >> 8;
2024 units = 1000000 / (1 << power); /* convert to uJ */
2025 power = I915_READ(MCH_SECP_NRG_STTS);
2026 power *= units;
2027
36623ef8
PZ		 2028 intel_runtime_pm_put(dev_priv);
2029
ec013e7f 2030 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2031
2032 return 0;
2033}
2034
2035static int i915_pc8_status(struct seq_file *m, void *unused)
2036{
2037 struct drm_info_node *node = (struct drm_info_node *) m->private;
2038 struct drm_device *dev = node->minor->dev;
2039 struct drm_i915_private *dev_priv = dev->dev_private;
2040
2041 if (!IS_HASWELL(dev)) {
2042 seq_puts(m, "not supported\n");
2043 return 0;
2044 }
2045
86c4ec0d 2046 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2047 seq_printf(m, "IRQs disabled: %s\n",
5d584b2e 2048 yesno(dev_priv->pm.irqs_disabled));
371db66a 2049
ec013e7f
JB		 2050 return 0;
2051}
2052
1da51581
ID		 2053static const char *power_domain_str(enum intel_display_power_domain domain)
2054{
2055 switch (domain) {
2056 case POWER_DOMAIN_PIPE_A:
2057 return "PIPE_A";
2058 case POWER_DOMAIN_PIPE_B:
2059 return "PIPE_B";
2060 case POWER_DOMAIN_PIPE_C:
2061 return "PIPE_C";
2062 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2063 return "PIPE_A_PANEL_FITTER";
2064 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2065 return "PIPE_B_PANEL_FITTER";
2066 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2067 return "PIPE_C_PANEL_FITTER";
2068 case POWER_DOMAIN_TRANSCODER_A:
2069 return "TRANSCODER_A";
2070 case POWER_DOMAIN_TRANSCODER_B:
2071 return "TRANSCODER_B";
2072 case POWER_DOMAIN_TRANSCODER_C:
2073 return "TRANSCODER_C";
2074 case POWER_DOMAIN_TRANSCODER_EDP:
2075 return "TRANSCODER_EDP";
319be8ae
ID		 2076 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2077 return "PORT_DDI_A_2_LANES";
2078 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2079 return "PORT_DDI_A_4_LANES";
2080 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2081 return "PORT_DDI_B_2_LANES";
2082 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2083 return "PORT_DDI_B_4_LANES";
2084 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2085 return "PORT_DDI_C_2_LANES";
2086 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2087 return "PORT_DDI_C_4_LANES";
2088 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2089 return "PORT_DDI_D_2_LANES";
2090 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2091 return "PORT_DDI_D_4_LANES";
2092 case POWER_DOMAIN_PORT_DSI:
2093 return "PORT_DSI";
2094 case POWER_DOMAIN_PORT_CRT:
2095 return "PORT_CRT";
2096 case POWER_DOMAIN_PORT_OTHER:
2097 return "PORT_OTHER";
1da51581
ID		 2098 case POWER_DOMAIN_VGA:
2099 return "VGA";
2100 case POWER_DOMAIN_AUDIO:
2101 return "AUDIO";
2102 case POWER_DOMAIN_INIT:
2103 return "INIT";
2104 default:
2105 WARN_ON(1);
2106 return "?";
2107 }
2108}
2109
2110static int i915_power_domain_info(struct seq_file *m, void *unused)
2111{
2112 struct drm_info_node *node = (struct drm_info_node *) m->private;
2113 struct drm_device *dev = node->minor->dev;
2114 struct drm_i915_private *dev_priv = dev->dev_private;
2115 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2116 int i;
2117
2118 mutex_lock(&power_domains->lock);
2119
2120 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2121 for (i = 0; i < power_domains->power_well_count; i++) {
2122 struct i915_power_well *power_well;
2123 enum intel_display_power_domain power_domain;
2124
2125 power_well = &power_domains->power_wells[i];
2126 seq_printf(m, "%-25s %d\n", power_well->name,
2127 power_well->count);
2128
2129 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2130 power_domain++) {
2131 if (!(BIT(power_domain) & power_well->domains))
2132 continue;
2133
2134 seq_printf(m, " %-23s %d\n",
2135 power_domain_str(power_domain),
2136 power_domains->domain_use_count[power_domain]);
2137 }
2138 }
2139
2140 mutex_unlock(&power_domains->lock);
2141
2142 return 0;
2143}
2144
53f5e3ca
JB		 2145static void intel_seq_print_mode(struct seq_file *m, int tabs,
2146 struct drm_display_mode *mode)
2147{
2148 int i;
2149
2150 for (i = 0; i < tabs; i++)
2151 seq_putc(m, '\t');
2152
2153 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2154 mode->base.id, mode->name,
2155 mode->vrefresh, mode->clock,
2156 mode->hdisplay, mode->hsync_start,
2157 mode->hsync_end, mode->htotal,
2158 mode->vdisplay, mode->vsync_start,
2159 mode->vsync_end, mode->vtotal,
2160 mode->type, mode->flags);
2161}
2162
2163static void intel_encoder_info(struct seq_file *m,
2164 struct intel_crtc *intel_crtc,
2165 struct intel_encoder *intel_encoder)
2166{
2167 struct drm_info_node *node = (struct drm_info_node *) m->private;
2168 struct drm_device *dev = node->minor->dev;
2169 struct drm_crtc *crtc = &intel_crtc->base;
2170 struct intel_connector *intel_connector;
2171 struct drm_encoder *encoder;
2172
2173 encoder = &intel_encoder->base;
2174 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2175 encoder->base.id, drm_get_encoder_name(encoder));
2176 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2177 struct drm_connector *connector = &intel_connector->base;
2178 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2179 connector->base.id,
2180 drm_get_connector_name(connector),
2181 drm_get_connector_status_name(connector->status));
2182 if (connector->status == connector_status_connected) {
2183 struct drm_display_mode *mode = &crtc->mode;
2184 seq_printf(m, ", mode:\n");
2185 intel_seq_print_mode(m, 2, mode);
2186 } else {
2187 seq_putc(m, '\n');
2188 }
2189 }
2190}
2191
2192static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2193{
2194 struct drm_info_node *node = (struct drm_info_node *) m->private;
2195 struct drm_device *dev = node->minor->dev;
2196 struct drm_crtc *crtc = &intel_crtc->base;
2197 struct intel_encoder *intel_encoder;
2198
2199 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2200 crtc->fb->base.id, crtc->x, crtc->y,
2201 crtc->fb->width, crtc->fb->height);
2202 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2203 intel_encoder_info(m, intel_crtc, intel_encoder);
2204}
2205
2206static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2207{
2208 struct drm_display_mode *mode = panel->fixed_mode;
2209
2210 seq_printf(m, "\tfixed mode:\n");
2211 intel_seq_print_mode(m, 2, mode);
2212}
2213
2214static void intel_dp_info(struct seq_file *m,
2215 struct intel_connector *intel_connector)
2216{
2217 struct intel_encoder *intel_encoder = intel_connector->encoder;
2218 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2219
2220 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2221 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2222 "no");
2223 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2224 intel_panel_info(m, &intel_connector->panel);
2225}
2226
2227static void intel_hdmi_info(struct seq_file *m,
2228 struct intel_connector *intel_connector)
2229{
2230 struct intel_encoder *intel_encoder = intel_connector->encoder;
2231 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2232
2233 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2234 "no");
2235}
2236
2237static void intel_lvds_info(struct seq_file *m,
2238 struct intel_connector *intel_connector)
2239{
2240 intel_panel_info(m, &intel_connector->panel);
2241}
2242
2243static void intel_connector_info(struct seq_file *m,
2244 struct drm_connector *connector)
2245{
2246 struct intel_connector *intel_connector = to_intel_connector(connector);
2247 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2248 struct drm_display_mode *mode;
53f5e3ca
JB		 2249
2250 seq_printf(m, "connector %d: type %s, status: %s\n",
2251 connector->base.id, drm_get_connector_name(connector),
2252 drm_get_connector_status_name(connector->status));
2253 if (connector->status == connector_status_connected) {
2254 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2255 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2256 connector->display_info.width_mm,
2257 connector->display_info.height_mm);
2258 seq_printf(m, "\tsubpixel order: %s\n",
2259 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2260 seq_printf(m, "\tCEA rev: %d\n",
2261 connector->display_info.cea_rev);
2262 }
2263 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2264 intel_encoder->type == INTEL_OUTPUT_EDP)
2265 intel_dp_info(m, intel_connector);
2266 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2267 intel_hdmi_info(m, intel_connector);
2268 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2269 intel_lvds_info(m, intel_connector);
2270
f103fc7d
JB		 2271 seq_printf(m, "\tmodes:\n");
2272 list_for_each_entry(mode, &connector->modes, head)
2273 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2274}
2275
065f2ec2
CW		 2276static bool cursor_active(struct drm_device *dev, int pipe)
2277{
2278 struct drm_i915_private *dev_priv = dev->dev_private;
2279 u32 state;
2280
2281 if (IS_845G(dev) || IS_I865G(dev))
2282 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2283 else if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev))
2284 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2285 else
2286 state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
2287
2288 return state;
2289}
2290
2291static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2292{
2293 struct drm_i915_private *dev_priv = dev->dev_private;
2294 u32 pos;
2295
2296 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
2297 pos = I915_READ(CURPOS_IVB(pipe));
2298 else
2299 pos = I915_READ(CURPOS(pipe));
2300
2301 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2302 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2303 *x = -*x;
2304
2305 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2306 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2307 *y = -*y;
2308
2309 return cursor_active(dev, pipe);
2310}
2311
53f5e3ca
JB		 2312static int i915_display_info(struct seq_file *m, void *unused)
2313{
2314 struct drm_info_node *node = (struct drm_info_node *) m->private;
2315 struct drm_device *dev = node->minor->dev;
065f2ec2 2316 struct intel_crtc *crtc;
53f5e3ca
JB		 2317 struct drm_connector *connector;
2318
2319 drm_modeset_lock_all(dev);
2320 seq_printf(m, "CRTC info\n");
2321 seq_printf(m, "---------\n");
065f2ec2
CW		 2322 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2323 bool active;
2324 int x, y;
53f5e3ca
JB		 2325
2326 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
065f2ec2
CW		 2327 crtc->base.base.id, pipe_name(crtc->pipe),
2328 yesno(crtc->active));
2329 if (crtc->active)
2330 intel_crtc_info(m, crtc);
2331
2332 active = cursor_position(dev, crtc->pipe, &x, &y);
2333 seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",
2334 yesno(crtc->cursor_visible),
2335 x, y, crtc->cursor_addr,
2336 yesno(active));
53f5e3ca
JB		 2337 }
2338
2339 seq_printf(m, "\n");
2340 seq_printf(m, "Connector info\n");
2341 seq_printf(m, "--------------\n");
2342 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2343 intel_connector_info(m, connector);
2344 }
2345 drm_modeset_unlock_all(dev);
2346
2347 return 0;
2348}
2349
07144428
DL		 2350struct pipe_crc_info {
2351 const char *name;
2352 struct drm_device *dev;
2353 enum pipe pipe;
2354};
2355
2356static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2357{
be5c7a90
DL		 2358 struct pipe_crc_info *info = inode->i_private;
2359 struct drm_i915_private *dev_priv = info->dev->dev_private;
2360 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2361
7eb1c496
DV		 2362 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2363 return -ENODEV;
2364
d538bbdf
DL		 2365 spin_lock_irq(&pipe_crc->lock);
2366
2367 if (pipe_crc->opened) {
2368 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2369 return -EBUSY; /* already open */
2370 }
2371
d538bbdf 2372 pipe_crc->opened = true;
07144428
DL		 2373 filep->private_data = inode->i_private;
2374
d538bbdf
DL		 2375 spin_unlock_irq(&pipe_crc->lock);
2376
07144428
DL		 2377 return 0;
2378}
2379
2380static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2381{
be5c7a90
DL		 2382 struct pipe_crc_info *info = inode->i_private;
2383 struct drm_i915_private *dev_priv = info->dev->dev_private;
2384 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2385
d538bbdf
DL		 2386 spin_lock_irq(&pipe_crc->lock);
2387 pipe_crc->opened = false;
2388 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2389
07144428
DL		 2390 return 0;
2391}
2392
2393/* (6 fields, 8 chars each, space separated (5) + '\n') */
2394#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2395/* account for \'0' */
2396#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2397
2398static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2399{
d538bbdf
DL		 2400 assert_spin_locked(&pipe_crc->lock);
2401 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2402 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2403}
2404
2405static ssize_t
2406i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2407 loff_t *pos)
2408{
2409 struct pipe_crc_info *info = filep->private_data;
2410 struct drm_device *dev = info->dev;
2411 struct drm_i915_private *dev_priv = dev->dev_private;
2412 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2413 char buf[PIPE_CRC_BUFFER_LEN];
2414 int head, tail, n_entries, n;
2415 ssize_t bytes_read;
2416
2417 /*
2418 * Don't allow user space to provide buffers not big enough to hold
2419 * a line of data.
2420 */
2421 if (count < PIPE_CRC_LINE_LEN)
2422 return -EINVAL;
2423
2424 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2425 return 0;
07144428
DL		 2426
2427 /* nothing to read */
d538bbdf 2428 spin_lock_irq(&pipe_crc->lock);
07144428 2429 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2430 int ret;
2431
2432 if (filep->f_flags & O_NONBLOCK) {
2433 spin_unlock_irq(&pipe_crc->lock);
07144428 2434 return -EAGAIN;
d538bbdf 2435 }
07144428 2436
d538bbdf
DL		 2437 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2438 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2439 if (ret) {
2440 spin_unlock_irq(&pipe_crc->lock);
2441 return ret;
2442 }
8bf1e9f1
SH		 2443 }
2444
07144428 2445 /* We now have one or more entries to read */
d538bbdf
DL		 2446 head = pipe_crc->head;
2447 tail = pipe_crc->tail;
07144428
DL		 2448 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2449 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2450 spin_unlock_irq(&pipe_crc->lock);
2451
07144428
DL		 2452 bytes_read = 0;
2453 n = 0;
2454 do {
b2c88f5b 2455 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2456 int ret;
8bf1e9f1 2457
07144428
DL		 2458 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2459 "%8u %8x %8x %8x %8x %8x\n",
2460 entry->frame, entry->crc[0],
2461 entry->crc[1], entry->crc[2],
2462 entry->crc[3], entry->crc[4]);
2463
2464 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2465 buf, PIPE_CRC_LINE_LEN);
2466 if (ret == PIPE_CRC_LINE_LEN)
2467 return -EFAULT;
b2c88f5b
DL		 2468
2469 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2470 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2471 n++;
2472 } while (--n_entries);
8bf1e9f1 2473
d538bbdf
DL		 2474 spin_lock_irq(&pipe_crc->lock);
2475 pipe_crc->tail = tail;
2476 spin_unlock_irq(&pipe_crc->lock);
2477
07144428
DL		 2478 return bytes_read;
2479}
2480
2481static const struct file_operations i915_pipe_crc_fops = {
2482 .owner = THIS_MODULE,
2483 .open = i915_pipe_crc_open,
2484 .read = i915_pipe_crc_read,
2485 .release = i915_pipe_crc_release,
2486};
2487
2488static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2489 {
2490 .name = "i915_pipe_A_crc",
2491 .pipe = PIPE_A,
2492 },
2493 {
2494 .name = "i915_pipe_B_crc",
2495 .pipe = PIPE_B,
2496 },
2497 {
2498 .name = "i915_pipe_C_crc",
2499 .pipe = PIPE_C,
2500 },
2501};
2502
2503static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2504 enum pipe pipe)
2505{
2506 struct drm_device *dev = minor->dev;
2507 struct dentry *ent;
2508 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2509
2510 info->dev = dev;
2511 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2512 &i915_pipe_crc_fops);
f3c5fe97
WY		 2513 if (!ent)
2514 return -ENOMEM;
07144428
DL		 2515
2516 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2517}
2518
e8dfcf78 2519static const char * const pipe_crc_sources[] = {
926321d5
DV		 2520 "none",
2521 "plane1",
2522 "plane2",
2523 "pf",
5b3a856b 2524 "pipe",
3d099a05
DV		 2525 "TV",
2526 "DP-B",
2527 "DP-C",
2528 "DP-D",
46a19188 2529 "auto",
926321d5
DV		 2530};
2531
2532static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2533{
2534 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2535 return pipe_crc_sources[source];
2536}
2537
bd9db02f 2538static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2539{
2540 struct drm_device *dev = m->private;
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542 int i;
2543
2544 for (i = 0; i < I915_MAX_PIPES; i++)
2545 seq_printf(m, "%c %s\n", pipe_name(i),
2546 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2547
2548 return 0;
2549}
2550
bd9db02f 2551static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2552{
2553 struct drm_device *dev = inode->i_private;
2554
bd9db02f 2555 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2556}
2557
46a19188 2558static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2559 uint32_t *val)
2560{
46a19188
DV		 2561 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2562 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2563
2564 switch (*source) {
52f843f6
DV		 2565 case INTEL_PIPE_CRC_SOURCE_PIPE:
2566 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2567 break;
2568 case INTEL_PIPE_CRC_SOURCE_NONE:
2569 *val = 0;
2570 break;
2571 default:
2572 return -EINVAL;
2573 }
2574
2575 return 0;
2576}
2577
46a19188
DV		 2578static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2579 enum intel_pipe_crc_source *source)
2580{
2581 struct intel_encoder *encoder;
2582 struct intel_crtc *crtc;
26756809 2583 struct intel_digital_port *dig_port;
46a19188
DV		 2584 int ret = 0;
2585
2586 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2587
2588 mutex_lock(&dev->mode_config.mutex);
2589 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2590 base.head) {
2591 if (!encoder->base.crtc)
2592 continue;
2593
2594 crtc = to_intel_crtc(encoder->base.crtc);
2595
2596 if (crtc->pipe != pipe)
2597 continue;
2598
2599 switch (encoder->type) {
2600 case INTEL_OUTPUT_TVOUT:
2601 *source = INTEL_PIPE_CRC_SOURCE_TV;
2602 break;
2603 case INTEL_OUTPUT_DISPLAYPORT:
2604 case INTEL_OUTPUT_EDP:
26756809
DV		 2605 dig_port = enc_to_dig_port(&encoder->base);
2606 switch (dig_port->port) {
2607 case PORT_B:
2608 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2609 break;
2610 case PORT_C:
2611 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2612 break;
2613 case PORT_D:
2614 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2615 break;
2616 default:
2617 WARN(1, "nonexisting DP port %c\n",
2618 port_name(dig_port->port));
2619 break;
2620 }
46a19188
DV		 2621 break;
2622 }
2623 }
2624 mutex_unlock(&dev->mode_config.mutex);
2625
2626 return ret;
2627}
2628
2629static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2630 enum pipe pipe,
2631 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2632 uint32_t *val)
2633{
8d2f24ca
DV		 2634 struct drm_i915_private *dev_priv = dev->dev_private;
2635 bool need_stable_symbols = false;
2636
46a19188
DV		 2637 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2638 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2639 if (ret)
2640 return ret;
2641 }
2642
2643 switch (*source) {
7ac0129b
DV		 2644 case INTEL_PIPE_CRC_SOURCE_PIPE:
2645 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2646 break;
2647 case INTEL_PIPE_CRC_SOURCE_DP_B:
2648 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2649 need_stable_symbols = true;
7ac0129b
DV		 2650 break;
2651 case INTEL_PIPE_CRC_SOURCE_DP_C:
2652 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2653 need_stable_symbols = true;
7ac0129b
DV		 2654 break;
2655 case INTEL_PIPE_CRC_SOURCE_NONE:
2656 *val = 0;
2657 break;
2658 default:
2659 return -EINVAL;
2660 }
2661
8d2f24ca
DV		 2662 /*
2663 * When the pipe CRC tap point is after the transcoders we need
2664 * to tweak symbol-level features to produce a deterministic series of
2665 * symbols for a given frame. We need to reset those features only once
2666 * a frame (instead of every nth symbol):
2667 * - DC-balance: used to ensure a better clock recovery from the data
2668 * link (SDVO)
2669 * - DisplayPort scrambling: used for EMI reduction
2670 */
2671 if (need_stable_symbols) {
2672 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2673
8d2f24ca
DV		 2674 tmp |= DC_BALANCE_RESET_VLV;
2675 if (pipe == PIPE_A)
2676 tmp |= PIPE_A_SCRAMBLE_RESET;
2677 else
2678 tmp |= PIPE_B_SCRAMBLE_RESET;
2679
2680 I915_WRITE(PORT_DFT2_G4X, tmp);
2681 }
2682
7ac0129b
DV		 2683 return 0;
2684}
2685
4b79ebf7 2686static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2687 enum pipe pipe,
2688 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2689 uint32_t *val)
2690{
84093603
DV		 2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 bool need_stable_symbols = false;
2693
46a19188
DV		 2694 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2695 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2696 if (ret)
2697 return ret;
2698 }
2699
2700 switch (*source) {
4b79ebf7
DV		 2701 case INTEL_PIPE_CRC_SOURCE_PIPE:
2702 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2703 break;
2704 case INTEL_PIPE_CRC_SOURCE_TV:
2705 if (!SUPPORTS_TV(dev))
2706 return -EINVAL;
2707 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2708 break;
2709 case INTEL_PIPE_CRC_SOURCE_DP_B:
2710 if (!IS_G4X(dev))
2711 return -EINVAL;
2712 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2713 need_stable_symbols = true;
4b79ebf7
DV		 2714 break;
2715 case INTEL_PIPE_CRC_SOURCE_DP_C:
2716 if (!IS_G4X(dev))
2717 return -EINVAL;
2718 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2719 need_stable_symbols = true;
4b79ebf7
DV		 2720 break;
2721 case INTEL_PIPE_CRC_SOURCE_DP_D:
2722 if (!IS_G4X(dev))
2723 return -EINVAL;
2724 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2725 need_stable_symbols = true;
4b79ebf7
DV		 2726 break;
2727 case INTEL_PIPE_CRC_SOURCE_NONE:
2728 *val = 0;
2729 break;
2730 default:
2731 return -EINVAL;
2732 }
2733
84093603
DV		 2734 /*
2735 * When the pipe CRC tap point is after the transcoders we need
2736 * to tweak symbol-level features to produce a deterministic series of
2737 * symbols for a given frame. We need to reset those features only once
2738 * a frame (instead of every nth symbol):
2739 * - DC-balance: used to ensure a better clock recovery from the data
2740 * link (SDVO)
2741 * - DisplayPort scrambling: used for EMI reduction
2742 */
2743 if (need_stable_symbols) {
2744 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2745
2746 WARN_ON(!IS_G4X(dev));
2747
2748 I915_WRITE(PORT_DFT_I9XX,
2749 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2750
2751 if (pipe == PIPE_A)
2752 tmp |= PIPE_A_SCRAMBLE_RESET;
2753 else
2754 tmp |= PIPE_B_SCRAMBLE_RESET;
2755
2756 I915_WRITE(PORT_DFT2_G4X, tmp);
2757 }
2758
4b79ebf7
DV		 2759 return 0;
2760}
2761
8d2f24ca
DV		 2762static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2763 enum pipe pipe)
2764{
2765 struct drm_i915_private *dev_priv = dev->dev_private;
2766 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2767
2768 if (pipe == PIPE_A)
2769 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2770 else
2771 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2772 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2773 tmp &= ~DC_BALANCE_RESET_VLV;
2774 I915_WRITE(PORT_DFT2_G4X, tmp);
2775
2776}
2777
84093603
DV		 2778static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2779 enum pipe pipe)
2780{
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2783
2784 if (pipe == PIPE_A)
2785 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2786 else
2787 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2788 I915_WRITE(PORT_DFT2_G4X, tmp);
2789
2790 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2791 I915_WRITE(PORT_DFT_I9XX,
2792 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2793 }
2794}
2795
46a19188 2796static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2797 uint32_t *val)
2798{
46a19188
DV		 2799 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2800 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2801
2802 switch (*source) {
5b3a856b
DV		 2803 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2804 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2805 break;
2806 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2807 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2808 break;
5b3a856b
DV		 2809 case INTEL_PIPE_CRC_SOURCE_PIPE:
2810 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2811 break;
3d099a05 2812 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2813 *val = 0;
2814 break;
3d099a05
DV		 2815 default:
2816 return -EINVAL;
5b3a856b
DV		 2817 }
2818
2819 return 0;
2820}
2821
46a19188 2822static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2823 uint32_t *val)
2824{
46a19188
DV		 2825 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2826 *source = INTEL_PIPE_CRC_SOURCE_PF;
2827
2828 switch (*source) {
5b3a856b
DV		 2829 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2830 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2831 break;
2832 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2833 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2834 break;
2835 case INTEL_PIPE_CRC_SOURCE_PF:
2836 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2837 break;
3d099a05 2838 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2839 *val = 0;
2840 break;
3d099a05
DV		 2841 default:
2842 return -EINVAL;
5b3a856b
DV		 2843 }
2844
2845 return 0;
2846}
2847
926321d5
DV		 2848static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2849 enum intel_pipe_crc_source source)
2850{
2851 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2852 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 2853 u32 val = 0; /* shut up gcc */
5b3a856b 2854 int ret;
926321d5 2855
cc3da175
DL		 2856 if (pipe_crc->source == source)
2857 return 0;
2858
ae676fcd
DL		 2859 /* forbid changing the source without going back to 'none' */
2860 if (pipe_crc->source && source)
2861 return -EINVAL;
2862
52f843f6 2863 if (IS_GEN2(dev))
46a19188 2864 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2865 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2866 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2867 else if (IS_VALLEYVIEW(dev))
46a19188 2868 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
4b79ebf7 2869 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2870 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2871 else
46a19188 2872 ret = ivb_pipe_crc_ctl_reg(&source, &val);
5b3a856b
DV		 2873
2874 if (ret != 0)
2875 return ret;
2876
4b584369
DL		 2877 /* none -> real source transition */
2878 if (source) {
7cd6ccff
DL		 2879 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2880 pipe_name(pipe), pipe_crc_source_name(source));
2881
e5f75aca
DL		 2882 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2883 INTEL_PIPE_CRC_ENTRIES_NR,
2884 GFP_KERNEL);
2885 if (!pipe_crc->entries)
2886 return -ENOMEM;
2887
d538bbdf
DL		 2888 spin_lock_irq(&pipe_crc->lock);
2889 pipe_crc->head = 0;
2890 pipe_crc->tail = 0;
2891 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 2892 }
2893
cc3da175 2894 pipe_crc->source = source;
926321d5 2895
926321d5
DV		 2896 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2897 POSTING_READ(PIPE_CRC_CTL(pipe));
2898
e5f75aca
DL		 2899 /* real source -> none transition */
2900 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf
DL		 2901 struct intel_pipe_crc_entry *entries;
2902
7cd6ccff
DL		 2903 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2904 pipe_name(pipe));
2905
bcf17ab2
DV		 2906 intel_wait_for_vblank(dev, pipe);
2907
d538bbdf
DL		 2908 spin_lock_irq(&pipe_crc->lock);
2909 entries = pipe_crc->entries;
e5f75aca 2910 pipe_crc->entries = NULL;
d538bbdf
DL		 2911 spin_unlock_irq(&pipe_crc->lock);
2912
2913 kfree(entries);
84093603
DV		 2914
2915 if (IS_G4X(dev))
2916 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 2917 else if (IS_VALLEYVIEW(dev))
2918 vlv_undo_pipe_scramble_reset(dev, pipe);
e5f75aca
DL		 2919 }
2920
926321d5
DV		 2921 return 0;
2922}
2923
2924/*
2925 * Parse pipe CRC command strings:
b94dec87
DL		 2926 * command: wsp* object wsp+ name wsp+ source wsp*
2927 * object: 'pipe'
2928 * name: (A | B | C)
926321d5
DV		 2929 * source: (none | plane1 | plane2 | pf)
2930 * wsp: (#0x20 | #0x9 | #0xA)+
2931 *
2932 * eg.:
b94dec87
DL		 2933 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2934 * "pipe A none" -> Stop CRC
926321d5 2935 */
bd9db02f 2936static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 2937{
2938 int n_words = 0;
2939
2940 while (*buf) {
2941 char *end;
2942
2943 /* skip leading white space */
2944 buf = skip_spaces(buf);
2945 if (!*buf)
2946 break; /* end of buffer */
2947
2948 /* find end of word */
2949 for (end = buf; *end && !isspace(*end); end++)
2950 ;
2951
2952 if (n_words == max_words) {
2953 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2954 max_words);
2955 return -EINVAL; /* ran out of words[] before bytes */
2956 }
2957
2958 if (*end)
2959 *end++ = '\0';
2960 words[n_words++] = buf;
2961 buf = end;
2962 }
2963
2964 return n_words;
2965}
2966
b94dec87
DL		 2967enum intel_pipe_crc_object {
2968 PIPE_CRC_OBJECT_PIPE,
2969};
2970
e8dfcf78 2971static const char * const pipe_crc_objects[] = {
b94dec87
DL		 2972 "pipe",
2973};
2974
2975static int
bd9db02f 2976display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 2977{
2978 int i;
2979
2980 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2981 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 2982 *o = i;
b94dec87
DL		 2983 return 0;
2984 }
2985
2986 return -EINVAL;
2987}
2988
bd9db02f 2989static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 2990{
2991 const char name = buf[0];
2992
2993 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2994 return -EINVAL;
2995
2996 *pipe = name - 'A';
2997
2998 return 0;
2999}
3000
3001static int
bd9db02f 3002display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3003{
3004 int i;
3005
3006 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3007 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3008 *s = i;
926321d5
DV		 3009 return 0;
3010 }
3011
3012 return -EINVAL;
3013}
3014
bd9db02f 3015static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3016{
b94dec87 3017#define N_WORDS 3
926321d5 3018 int n_words;
b94dec87 3019 char *words[N_WORDS];
926321d5 3020 enum pipe pipe;
b94dec87 3021 enum intel_pipe_crc_object object;
926321d5
DV		 3022 enum intel_pipe_crc_source source;
3023
bd9db02f 3024 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3025 if (n_words != N_WORDS) {
3026 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3027 N_WORDS);
3028 return -EINVAL;
3029 }
3030
bd9db02f 3031 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3032 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3033 return -EINVAL;
3034 }
3035
bd9db02f 3036 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3037 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3038 return -EINVAL;
3039 }
3040
bd9db02f 3041 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3042 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3043 return -EINVAL;
3044 }
3045
3046 return pipe_crc_set_source(dev, pipe, source);
3047}
3048
bd9db02f
DL		 3049static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3050 size_t len, loff_t *offp)
926321d5
DV		 3051{
3052 struct seq_file *m = file->private_data;
3053 struct drm_device *dev = m->private;
3054 char *tmpbuf;
3055 int ret;
3056
3057 if (len == 0)
3058 return 0;
3059
3060 if (len > PAGE_SIZE - 1) {
3061 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3062 PAGE_SIZE);
3063 return -E2BIG;
3064 }
3065
3066 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3067 if (!tmpbuf)
3068 return -ENOMEM;
3069
3070 if (copy_from_user(tmpbuf, ubuf, len)) {
3071 ret = -EFAULT;
3072 goto out;
3073 }
3074 tmpbuf[len] = '\0';
3075
bd9db02f 3076 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3077
3078out:
3079 kfree(tmpbuf);
3080 if (ret < 0)
3081 return ret;
3082
3083 *offp += len;
3084 return len;
3085}
3086
bd9db02f 3087static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3088 .owner = THIS_MODULE,
bd9db02f 3089 .open = display_crc_ctl_open,
926321d5
DV		 3090 .read = seq_read,
3091 .llseek = seq_lseek,
3092 .release = single_release,
bd9db02f 3093 .write = display_crc_ctl_write
926321d5
DV		 3094};
3095
369a1342
VS		 3096static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3097{
3098 struct drm_device *dev = m->private;
3099 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3100 int level;
3101
3102 drm_modeset_lock_all(dev);
3103
3104 for (level = 0; level < num_levels; level++) {
3105 unsigned int latency = wm[level];
3106
3107 /* WM1+ latency values in 0.5us units */
3108 if (level > 0)
3109 latency *= 5;
3110
3111 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3112 level, wm[level],
3113 latency / 10, latency % 10);
3114 }
3115
3116 drm_modeset_unlock_all(dev);
3117}
3118
3119static int pri_wm_latency_show(struct seq_file *m, void *data)
3120{
3121 struct drm_device *dev = m->private;
3122
3123 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3124
3125 return 0;
3126}
3127
3128static int spr_wm_latency_show(struct seq_file *m, void *data)
3129{
3130 struct drm_device *dev = m->private;
3131
3132 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3133
3134 return 0;
3135}
3136
3137static int cur_wm_latency_show(struct seq_file *m, void *data)
3138{
3139 struct drm_device *dev = m->private;
3140
3141 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3142
3143 return 0;
3144}
3145
3146static int pri_wm_latency_open(struct inode *inode, struct file *file)
3147{
3148 struct drm_device *dev = inode->i_private;
3149
3150 if (!HAS_PCH_SPLIT(dev))
3151 return -ENODEV;
3152
3153 return single_open(file, pri_wm_latency_show, dev);
3154}
3155
3156static int spr_wm_latency_open(struct inode *inode, struct file *file)
3157{
3158 struct drm_device *dev = inode->i_private;
3159
3160 if (!HAS_PCH_SPLIT(dev))
3161 return -ENODEV;
3162
3163 return single_open(file, spr_wm_latency_show, dev);
3164}
3165
3166static int cur_wm_latency_open(struct inode *inode, struct file *file)
3167{
3168 struct drm_device *dev = inode->i_private;
3169
3170 if (!HAS_PCH_SPLIT(dev))
3171 return -ENODEV;
3172
3173 return single_open(file, cur_wm_latency_show, dev);
3174}
3175
3176static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3177 size_t len, loff_t *offp, uint16_t wm[5])
3178{
3179 struct seq_file *m = file->private_data;
3180 struct drm_device *dev = m->private;
3181 uint16_t new[5] = { 0 };
3182 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3183 int level;
3184 int ret;
3185 char tmp[32];
3186
3187 if (len >= sizeof(tmp))
3188 return -EINVAL;
3189
3190 if (copy_from_user(tmp, ubuf, len))
3191 return -EFAULT;
3192
3193 tmp[len] = '\0';
3194
3195 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3196 if (ret != num_levels)
3197 return -EINVAL;
3198
3199 drm_modeset_lock_all(dev);
3200
3201 for (level = 0; level < num_levels; level++)
3202 wm[level] = new[level];
3203
3204 drm_modeset_unlock_all(dev);
3205
3206 return len;
3207}
3208
3209
3210static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3211 size_t len, loff_t *offp)
3212{
3213 struct seq_file *m = file->private_data;
3214 struct drm_device *dev = m->private;
3215
3216 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3217}
3218
3219static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3220 size_t len, loff_t *offp)
3221{
3222 struct seq_file *m = file->private_data;
3223 struct drm_device *dev = m->private;
3224
3225 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3226}
3227
3228static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3229 size_t len, loff_t *offp)
3230{
3231 struct seq_file *m = file->private_data;
3232 struct drm_device *dev = m->private;
3233
3234 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3235}
3236
3237static const struct file_operations i915_pri_wm_latency_fops = {
3238 .owner = THIS_MODULE,
3239 .open = pri_wm_latency_open,
3240 .read = seq_read,
3241 .llseek = seq_lseek,
3242 .release = single_release,
3243 .write = pri_wm_latency_write
3244};
3245
3246static const struct file_operations i915_spr_wm_latency_fops = {
3247 .owner = THIS_MODULE,
3248 .open = spr_wm_latency_open,
3249 .read = seq_read,
3250 .llseek = seq_lseek,
3251 .release = single_release,
3252 .write = spr_wm_latency_write
3253};
3254
3255static const struct file_operations i915_cur_wm_latency_fops = {
3256 .owner = THIS_MODULE,
3257 .open = cur_wm_latency_open,
3258 .read = seq_read,
3259 .llseek = seq_lseek,
3260 .release = single_release,
3261 .write = cur_wm_latency_write
3262};
3263
647416f9
KC		 3264static int
3265i915_wedged_get(void *data, u64 *val)
f3cd474b 3266{
647416f9 3267 struct drm_device *dev = data;
f3cd474b 3268 drm_i915_private_t *dev_priv = dev->dev_private;
f3cd474b 3269
647416f9 3270 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3271
647416f9 3272 return 0;
f3cd474b
CW		 3273}
3274
647416f9
KC		 3275static int
3276i915_wedged_set(void *data, u64 val)
f3cd474b 3277{
647416f9 3278 struct drm_device *dev = data;
f3cd474b 3279
58174462
MK		 3280 i915_handle_error(dev, val,
3281 "Manually setting wedged to %llu", val);
647416f9 3282 return 0;
f3cd474b
CW		 3283}
3284
647416f9
KC		 3285DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3286 i915_wedged_get, i915_wedged_set,
3a3b4f98 3287 "%llu\n");
f3cd474b 3288
647416f9
KC		 3289static int
3290i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3291{
647416f9 3292 struct drm_device *dev = data;
e5eb3d63 3293 drm_i915_private_t *dev_priv = dev->dev_private;
e5eb3d63 3294
647416f9 3295 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3296
647416f9 3297 return 0;
e5eb3d63
DV		 3298}
3299
647416f9
KC		 3300static int
3301i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3302{
647416f9 3303 struct drm_device *dev = data;
e5eb3d63 3304 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3305 int ret;
e5eb3d63 3306
647416f9 3307 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3308
22bcfc6a
DV		 3309 ret = mutex_lock_interruptible(&dev->struct_mutex);
3310 if (ret)
3311 return ret;
3312
99584db3 3313 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3314 mutex_unlock(&dev->struct_mutex);
3315
647416f9 3316 return 0;
e5eb3d63
DV		 3317}
3318
647416f9
KC		 3319DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3320 i915_ring_stop_get, i915_ring_stop_set,
3321 "0x%08llx\n");
d5442303 3322
094f9a54
CW		 3323static int
3324i915_ring_missed_irq_get(void *data, u64 *val)
3325{
3326 struct drm_device *dev = data;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328
3329 *val = dev_priv->gpu_error.missed_irq_rings;
3330 return 0;
3331}
3332
3333static int
3334i915_ring_missed_irq_set(void *data, u64 val)
3335{
3336 struct drm_device *dev = data;
3337 struct drm_i915_private *dev_priv = dev->dev_private;
3338 int ret;
3339
3340 /* Lock against concurrent debugfs callers */
3341 ret = mutex_lock_interruptible(&dev->struct_mutex);
3342 if (ret)
3343 return ret;
3344 dev_priv->gpu_error.missed_irq_rings = val;
3345 mutex_unlock(&dev->struct_mutex);
3346
3347 return 0;
3348}
3349
3350DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3351 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3352 "0x%08llx\n");
3353
3354static int
3355i915_ring_test_irq_get(void *data, u64 *val)
3356{
3357 struct drm_device *dev = data;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359
3360 *val = dev_priv->gpu_error.test_irq_rings;
3361
3362 return 0;
3363}
3364
3365static int
3366i915_ring_test_irq_set(void *data, u64 val)
3367{
3368 struct drm_device *dev = data;
3369 struct drm_i915_private *dev_priv = dev->dev_private;
3370 int ret;
3371
3372 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3373
3374 /* Lock against concurrent debugfs callers */
3375 ret = mutex_lock_interruptible(&dev->struct_mutex);
3376 if (ret)
3377 return ret;
3378
3379 dev_priv->gpu_error.test_irq_rings = val;
3380 mutex_unlock(&dev->struct_mutex);
3381
3382 return 0;
3383}
3384
3385DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3386 i915_ring_test_irq_get, i915_ring_test_irq_set,
3387 "0x%08llx\n");
3388
dd624afd
CW		 3389#define DROP_UNBOUND 0x1
3390#define DROP_BOUND 0x2
3391#define DROP_RETIRE 0x4
3392#define DROP_ACTIVE 0x8
3393#define DROP_ALL (DROP_UNBOUND | \
3394 DROP_BOUND | \
3395 DROP_RETIRE | \
3396 DROP_ACTIVE)
647416f9
KC		 3397static int
3398i915_drop_caches_get(void *data, u64 *val)
dd624afd 3399{
647416f9 3400 *val = DROP_ALL;
dd624afd 3401
647416f9 3402 return 0;
dd624afd
CW		 3403}
3404
647416f9
KC		 3405static int
3406i915_drop_caches_set(void *data, u64 val)
dd624afd 3407{
647416f9 3408 struct drm_device *dev = data;
dd624afd
CW		 3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 3411 struct i915_address_space *vm;
3412 struct i915_vma *vma, *x;
647416f9 3413 int ret;
dd624afd 3414
2f9fe5ff 3415 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 3416
3417 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3418 * on ioctls on -EAGAIN. */
3419 ret = mutex_lock_interruptible(&dev->struct_mutex);
3420 if (ret)
3421 return ret;
3422
3423 if (val & DROP_ACTIVE) {
3424 ret = i915_gpu_idle(dev);
3425 if (ret)
3426 goto unlock;
3427 }
3428
3429 if (val & (DROP_RETIRE | DROP_ACTIVE))
3430 i915_gem_retire_requests(dev);
3431
3432 if (val & DROP_BOUND) {
ca191b13
BW		 3433 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3434 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3435 mm_list) {
d7f46fc4 3436 if (vma->pin_count)
ca191b13
BW		 3437 continue;
3438
3439 ret = i915_vma_unbind(vma);
3440 if (ret)
3441 goto unlock;
3442 }
31a46c9c 3443 }
dd624afd
CW		 3444 }
3445
3446 if (val & DROP_UNBOUND) {
35c20a60
BW		 3447 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3448 global_list)
dd624afd
CW		 3449 if (obj->pages_pin_count == 0) {
3450 ret = i915_gem_object_put_pages(obj);
3451 if (ret)
3452 goto unlock;
3453 }
3454 }
3455
3456unlock:
3457 mutex_unlock(&dev->struct_mutex);
3458
647416f9 3459 return ret;
dd624afd
CW		 3460}
3461
647416f9
KC		 3462DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3463 i915_drop_caches_get, i915_drop_caches_set,
3464 "0x%08llx\n");
dd624afd 3465
647416f9
KC		 3466static int
3467i915_max_freq_get(void *data, u64 *val)
358733e9 3468{
647416f9 3469 struct drm_device *dev = data;
358733e9 3470 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 3471 int ret;
004777cb
DV		 3472
3473 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3474 return -ENODEV;
3475
5c9669ce
TR		 3476 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3477
4fc688ce 3478 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3479 if (ret)
3480 return ret;
358733e9 3481
0a073b84 3482 if (IS_VALLEYVIEW(dev))
b39fb297 3483 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 3484 else
b39fb297 3485 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3486 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3487
647416f9 3488 return 0;
358733e9
JB		 3489}
3490
647416f9
KC		 3491static int
3492i915_max_freq_set(void *data, u64 val)
358733e9 3493{
647416f9 3494 struct drm_device *dev = data;
358733e9 3495 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3496 u32 rp_state_cap, hw_max, hw_min;
647416f9 3497 int ret;
004777cb
DV		 3498
3499 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3500 return -ENODEV;
358733e9 3501
5c9669ce
TR		 3502 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3503
647416f9 3504 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 3505
4fc688ce 3506 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3507 if (ret)
3508 return ret;
3509
358733e9
JB		 3510 /*
3511 * Turbo will still be enabled, but won't go above the set value.
3512 */
0a073b84 3513 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3514 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3515
3516 hw_max = valleyview_rps_max_freq(dev_priv);
3517 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3518 } else {
3519 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3520
3521 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3522 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3523 hw_min = (rp_state_cap >> 16) & 0xff;
3524 }
3525
b39fb297 3526 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 3527 mutex_unlock(&dev_priv->rps.hw_lock);
3528 return -EINVAL;
0a073b84
JB		 3529 }
3530
b39fb297 3531 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 3532
3533 if (IS_VALLEYVIEW(dev))
3534 valleyview_set_rps(dev, val);
3535 else
3536 gen6_set_rps(dev, val);
3537
4fc688ce 3538 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3539
647416f9 3540 return 0;
358733e9
JB		 3541}
3542
647416f9
KC		 3543DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3544 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 3545 "%llu\n");
358733e9 3546
647416f9
KC		 3547static int
3548i915_min_freq_get(void *data, u64 *val)
1523c310 3549{
647416f9 3550 struct drm_device *dev = data;
1523c310 3551 drm_i915_private_t *dev_priv = dev->dev_private;
647416f9 3552 int ret;
004777cb
DV		 3553
3554 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3555 return -ENODEV;
3556
5c9669ce
TR		 3557 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3558
4fc688ce 3559 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3560 if (ret)
3561 return ret;
1523c310 3562
0a073b84 3563 if (IS_VALLEYVIEW(dev))
b39fb297 3564 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 3565 else
b39fb297 3566 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3567 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3568
647416f9 3569 return 0;
1523c310
JB		 3570}
3571
647416f9
KC		 3572static int
3573i915_min_freq_set(void *data, u64 val)
1523c310 3574{
647416f9 3575 struct drm_device *dev = data;
1523c310 3576 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3577 u32 rp_state_cap, hw_max, hw_min;
647416f9 3578 int ret;
004777cb
DV		 3579
3580 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3581 return -ENODEV;
1523c310 3582
5c9669ce
TR		 3583 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3584
647416f9 3585 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 3586
4fc688ce 3587 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3588 if (ret)
3589 return ret;
3590
1523c310
JB		 3591 /*
3592 * Turbo will still be enabled, but won't go below the set value.
3593 */
0a073b84 3594 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3595 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3596
3597 hw_max = valleyview_rps_max_freq(dev_priv);
3598 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3599 } else {
3600 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3601
3602 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3603 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3604 hw_min = (rp_state_cap >> 16) & 0xff;
3605 }
3606
b39fb297 3607 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 3608 mutex_unlock(&dev_priv->rps.hw_lock);
3609 return -EINVAL;
0a073b84 3610 }
dd0a1aa1 3611
b39fb297 3612 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 3613
3614 if (IS_VALLEYVIEW(dev))
3615 valleyview_set_rps(dev, val);
3616 else
3617 gen6_set_rps(dev, val);
3618
4fc688ce 3619 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3620
647416f9 3621 return 0;
1523c310
JB		 3622}
3623
647416f9
KC		 3624DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3625 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 3626 "%llu\n");
1523c310 3627
647416f9
KC		 3628static int
3629i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 3630{
647416f9 3631 struct drm_device *dev = data;
07b7ddd9 3632 drm_i915_private_t *dev_priv = dev->dev_private;
07b7ddd9 3633 u32 snpcr;
647416f9 3634 int ret;
07b7ddd9 3635
004777cb
DV		 3636 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3637 return -ENODEV;
3638
22bcfc6a
DV		 3639 ret = mutex_lock_interruptible(&dev->struct_mutex);
3640 if (ret)
3641 return ret;
c8c8fb33 3642 intel_runtime_pm_get(dev_priv);
22bcfc6a 3643
07b7ddd9 3644 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 3645
3646 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 3647 mutex_unlock(&dev_priv->dev->struct_mutex);
3648
647416f9 3649 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 3650
647416f9 3651 return 0;
07b7ddd9
JB		 3652}
3653
647416f9
KC		 3654static int
3655i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 3656{
647416f9 3657 struct drm_device *dev = data;
07b7ddd9 3658 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3659 u32 snpcr;
07b7ddd9 3660
004777cb
DV		 3661 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3662 return -ENODEV;
3663
647416f9 3664 if (val > 3)
07b7ddd9
JB		 3665 return -EINVAL;
3666
c8c8fb33 3667 intel_runtime_pm_get(dev_priv);
647416f9 3668 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 3669
3670 /* Update the cache sharing policy here as well */
3671 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3672 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3673 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3674 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3675
c8c8fb33 3676 intel_runtime_pm_put(dev_priv);
647416f9 3677 return 0;
07b7ddd9
JB		 3678}
3679
647416f9
KC		 3680DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3681 i915_cache_sharing_get, i915_cache_sharing_set,
3682 "%llu\n");
07b7ddd9 3683
6d794d42
BW		 3684static int i915_forcewake_open(struct inode *inode, struct file *file)
3685{
3686 struct drm_device *dev = inode->i_private;
3687 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 3688
075edca4 3689 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3690 return 0;
3691
c8c8fb33 3692 intel_runtime_pm_get(dev_priv);
c8d9a590 3693 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3694
3695 return 0;
3696}
3697
c43b5634 3698static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 3699{
3700 struct drm_device *dev = inode->i_private;
3701 struct drm_i915_private *dev_priv = dev->dev_private;
3702
075edca4 3703 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3704 return 0;
3705
c8d9a590 3706 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
c8c8fb33 3707 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 3708
3709 return 0;
3710}
3711
3712static const struct file_operations i915_forcewake_fops = {
3713 .owner = THIS_MODULE,
3714 .open = i915_forcewake_open,
3715 .release = i915_forcewake_release,
3716};
3717
3718static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3719{
3720 struct drm_device *dev = minor->dev;
3721 struct dentry *ent;
3722
3723 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 3724 S_IRUSR,
6d794d42
BW		 3725 root, dev,
3726 &i915_forcewake_fops);
f3c5fe97
WY		 3727 if (!ent)
3728 return -ENOMEM;
6d794d42 3729
8eb57294 3730 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 3731}
3732
6a9c308d
DV		 3733static int i915_debugfs_create(struct dentry *root,
3734 struct drm_minor *minor,
3735 const char *name,
3736 const struct file_operations *fops)
07b7ddd9
JB		 3737{
3738 struct drm_device *dev = minor->dev;
3739 struct dentry *ent;
3740
6a9c308d 3741 ent = debugfs_create_file(name,
07b7ddd9
JB		 3742 S_IRUGO | S_IWUSR,
3743 root, dev,
6a9c308d 3744 fops);
f3c5fe97
WY		 3745 if (!ent)
3746 return -ENOMEM;
07b7ddd9 3747
6a9c308d 3748 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 3749}
3750
06c5bf8c 3751static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 3752 {"i915_capabilities", i915_capabilities, 0},
73aa808f 3753 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 3754 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 3755 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 3756 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 3757 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 3758 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 3759 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 3760 {"i915_gem_request", i915_gem_request_info, 0},
3761 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 3762 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 3763 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 3764 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3765 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3766 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 3767 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
f97108d1
JB		 3768 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3769 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3770 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3771 {"i915_inttoext_table", i915_inttoext_table, 0},
3772 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 3773 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 3774 {"i915_ring_freq_table", i915_ring_freq_table, 0},
7648fa99 3775 {"i915_gfxec", i915_gfxec, 0},
b5e50c3f 3776 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 3777 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 3778 {"i915_sr_status", i915_sr_status, 0},
44834a67 3779 {"i915_opregion", i915_opregion, 0},
37811fcc 3780 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 3781 {"i915_context_status", i915_context_status, 0},
6d794d42 3782 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 3783 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 3784 {"i915_ppgtt_info", i915_ppgtt_info, 0},
57f350b6 3785 {"i915_dpio", i915_dpio_info, 0},
63573eb7 3786 {"i915_llc", i915_llc, 0},
e91fd8c6 3787 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 3788 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 3789 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 3790 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 3791 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 3792 {"i915_display_info", i915_display_info, 0},
2017263e 3793};
27c202ad 3794#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 3795
06c5bf8c 3796static const struct i915_debugfs_files {
34b9674c
DV		 3797 const char *name;
3798 const struct file_operations *fops;
3799} i915_debugfs_files[] = {
3800 {"i915_wedged", &i915_wedged_fops},
3801 {"i915_max_freq", &i915_max_freq_fops},
3802 {"i915_min_freq", &i915_min_freq_fops},
3803 {"i915_cache_sharing", &i915_cache_sharing_fops},
3804 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3805 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3806 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3807 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3808 {"i915_error_state", &i915_error_state_fops},
3809 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3810 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 3811 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3812 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3813 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
34b9674c
DV		 3814};
3815
07144428
DL		 3816void intel_display_crc_init(struct drm_device *dev)
3817{
3818 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 3819 enum pipe pipe;
07144428 3820
b378360e
DV		 3821 for_each_pipe(pipe) {
3822 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 3823
d538bbdf
DL		 3824 pipe_crc->opened = false;
3825 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3826 init_waitqueue_head(&pipe_crc->wq);
3827 }
3828}
3829
27c202ad 3830int i915_debugfs_init(struct drm_minor *minor)
2017263e 3831{
34b9674c 3832 int ret, i;
f3cd474b 3833
6d794d42 3834 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3835 if (ret)
3836 return ret;
6a9c308d 3837
07144428
DL		 3838 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3839 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3840 if (ret)
3841 return ret;
3842 }
3843
34b9674c
DV		 3844 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3845 ret = i915_debugfs_create(minor->debugfs_root, minor,
3846 i915_debugfs_files[i].name,
3847 i915_debugfs_files[i].fops);
3848 if (ret)
3849 return ret;
3850 }
40633219 3851
27c202ad
BG		 3852 return drm_debugfs_create_files(i915_debugfs_list,
3853 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3854 minor->debugfs_root, minor);
3855}
3856
27c202ad 3857void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3858{
34b9674c
DV		 3859 int i;
3860
27c202ad
BG		 3861 drm_debugfs_remove_files(i915_debugfs_list,
3862 I915_DEBUGFS_ENTRIES, minor);
07144428 3863
6d794d42
BW		 3864 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3865 1, minor);
07144428 3866
e309a997 3867 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3868 struct drm_info_list *info_list =
3869 (struct drm_info_list *)&i915_pipe_crc_data[i];
3870
3871 drm_debugfs_remove_files(info_list, 1, minor);
3872 }
3873
34b9674c
DV		 3874 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3875 struct drm_info_list *info_list =
3876 (struct drm_info_list *) i915_debugfs_files[i].fops;
3877
3878 drm_debugfs_remove_files(info_list, 1, minor);
3879 }
2017263e 3880}
Linux kernel - Deliverables
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