Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
2017263e BG |
43 | #if defined(CONFIG_DEBUG_FS) |
44 | ||
f13d3f73 | 45 | enum { |
69dc4987 | 46 | ACTIVE_LIST, |
f13d3f73 | 47 | INACTIVE_LIST, |
d21d5975 | 48 | PINNED_LIST, |
f13d3f73 | 49 | }; |
2017263e | 50 | |
70d39fe4 CW |
51 | static const char *yesno(int v) |
52 | { | |
53 | return v ? "yes" : "no"; | |
54 | } | |
55 | ||
497666d8 DL |
56 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
57 | * allocated we need to hook into the minor for release. */ | |
58 | static int | |
59 | drm_add_fake_info_node(struct drm_minor *minor, | |
60 | struct dentry *ent, | |
61 | const void *key) | |
62 | { | |
63 | struct drm_info_node *node; | |
64 | ||
65 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
66 | if (node == NULL) { | |
67 | debugfs_remove(ent); | |
68 | return -ENOMEM; | |
69 | } | |
70 | ||
71 | node->minor = minor; | |
72 | node->dent = ent; | |
73 | node->info_ent = (void *) key; | |
74 | ||
75 | mutex_lock(&minor->debugfs_lock); | |
76 | list_add(&node->list, &minor->debugfs_list); | |
77 | mutex_unlock(&minor->debugfs_lock); | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
70d39fe4 CW |
82 | static int i915_capabilities(struct seq_file *m, void *data) |
83 | { | |
84 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
85 | struct drm_device *dev = node->minor->dev; | |
86 | const struct intel_device_info *info = INTEL_INFO(dev); | |
87 | ||
88 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 89 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
90 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
91 | #define SEP_SEMICOLON ; | |
92 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
93 | #undef PRINT_FLAG | |
94 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
95 | |
96 | return 0; | |
97 | } | |
2017263e | 98 | |
05394f39 | 99 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 100 | { |
05394f39 | 101 | if (obj->user_pin_count > 0) |
a6172a80 | 102 | return "P"; |
05394f39 | 103 | else if (obj->pin_count > 0) |
a6172a80 CW |
104 | return "p"; |
105 | else | |
106 | return " "; | |
107 | } | |
108 | ||
05394f39 | 109 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 110 | { |
0206e353 AJ |
111 | switch (obj->tiling_mode) { |
112 | default: | |
113 | case I915_TILING_NONE: return " "; | |
114 | case I915_TILING_X: return "X"; | |
115 | case I915_TILING_Y: return "Y"; | |
116 | } | |
a6172a80 CW |
117 | } |
118 | ||
1d693bcc BW |
119 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
120 | { | |
121 | return obj->has_global_gtt_mapping ? "g" : " "; | |
122 | } | |
123 | ||
37811fcc CW |
124 | static void |
125 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
126 | { | |
1d693bcc | 127 | struct i915_vma *vma; |
fb1ae911 | 128 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
129 | &obj->base, |
130 | get_pin_flag(obj), | |
131 | get_tiling_flag(obj), | |
1d693bcc | 132 | get_global_flag(obj), |
a05a5862 | 133 | obj->base.size / 1024, |
37811fcc CW |
134 | obj->base.read_domains, |
135 | obj->base.write_domain, | |
0201f1ec CW |
136 | obj->last_read_seqno, |
137 | obj->last_write_seqno, | |
caea7476 | 138 | obj->last_fenced_seqno, |
84734a04 | 139 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
140 | obj->dirty ? " dirty" : "", |
141 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
142 | if (obj->base.name) | |
143 | seq_printf(m, " (name: %d)", obj->base.name); | |
c110a6d7 CW |
144 | if (obj->pin_count) |
145 | seq_printf(m, " (pinned x %d)", obj->pin_count); | |
cc98b413 CW |
146 | if (obj->pin_display) |
147 | seq_printf(m, " (display)"); | |
37811fcc CW |
148 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
149 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
150 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
151 | if (!i915_is_ggtt(vma->vm)) | |
152 | seq_puts(m, " (pp"); | |
153 | else | |
154 | seq_puts(m, " (g"); | |
155 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
156 | vma->node.start, vma->node.size); | |
157 | } | |
c1ad11fc CW |
158 | if (obj->stolen) |
159 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
160 | if (obj->pin_mappable || obj->fault_mappable) { |
161 | char s[3], *t = s; | |
162 | if (obj->pin_mappable) | |
163 | *t++ = 'p'; | |
164 | if (obj->fault_mappable) | |
165 | *t++ = 'f'; | |
166 | *t = '\0'; | |
167 | seq_printf(m, " (%s mappable)", s); | |
168 | } | |
69dc4987 CW |
169 | if (obj->ring != NULL) |
170 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
171 | } |
172 | ||
3ccfd19d BW |
173 | static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx) |
174 | { | |
175 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); | |
176 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); | |
177 | seq_putc(m, ' '); | |
178 | } | |
179 | ||
433e12f7 | 180 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e BG |
181 | { |
182 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
433e12f7 BG |
183 | uintptr_t list = (uintptr_t) node->info_ent->data; |
184 | struct list_head *head; | |
2017263e | 185 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
186 | struct drm_i915_private *dev_priv = dev->dev_private; |
187 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 188 | struct i915_vma *vma; |
8f2480fb CW |
189 | size_t total_obj_size, total_gtt_size; |
190 | int count, ret; | |
de227ef0 CW |
191 | |
192 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
193 | if (ret) | |
194 | return ret; | |
2017263e | 195 | |
ca191b13 | 196 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
197 | switch (list) { |
198 | case ACTIVE_LIST: | |
267f0c90 | 199 | seq_puts(m, "Active:\n"); |
5cef07e1 | 200 | head = &vm->active_list; |
433e12f7 BG |
201 | break; |
202 | case INACTIVE_LIST: | |
267f0c90 | 203 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 204 | head = &vm->inactive_list; |
433e12f7 | 205 | break; |
433e12f7 | 206 | default: |
de227ef0 CW |
207 | mutex_unlock(&dev->struct_mutex); |
208 | return -EINVAL; | |
2017263e | 209 | } |
2017263e | 210 | |
8f2480fb | 211 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
212 | list_for_each_entry(vma, head, mm_list) { |
213 | seq_printf(m, " "); | |
214 | describe_obj(m, vma->obj); | |
215 | seq_printf(m, "\n"); | |
216 | total_obj_size += vma->obj->base.size; | |
217 | total_gtt_size += vma->node.size; | |
8f2480fb | 218 | count++; |
2017263e | 219 | } |
de227ef0 | 220 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 221 | |
8f2480fb CW |
222 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
223 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
224 | return 0; |
225 | } | |
226 | ||
6d2b8885 CW |
227 | static int obj_rank_by_stolen(void *priv, |
228 | struct list_head *A, struct list_head *B) | |
229 | { | |
230 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 231 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 232 | struct drm_i915_gem_object *b = |
b25cb2f8 | 233 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
234 | |
235 | return a->stolen->start - b->stolen->start; | |
236 | } | |
237 | ||
238 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
239 | { | |
240 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
241 | struct drm_device *dev = node->minor->dev; | |
242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
243 | struct drm_i915_gem_object *obj; | |
244 | size_t total_obj_size, total_gtt_size; | |
245 | LIST_HEAD(stolen); | |
246 | int count, ret; | |
247 | ||
248 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
249 | if (ret) | |
250 | return ret; | |
251 | ||
252 | total_obj_size = total_gtt_size = count = 0; | |
253 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
254 | if (obj->stolen == NULL) | |
255 | continue; | |
256 | ||
b25cb2f8 | 257 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
258 | |
259 | total_obj_size += obj->base.size; | |
260 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
261 | count++; | |
262 | } | |
263 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
264 | if (obj->stolen == NULL) | |
265 | continue; | |
266 | ||
b25cb2f8 | 267 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
268 | |
269 | total_obj_size += obj->base.size; | |
270 | count++; | |
271 | } | |
272 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
273 | seq_puts(m, "Stolen:\n"); | |
274 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 275 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
276 | seq_puts(m, " "); |
277 | describe_obj(m, obj); | |
278 | seq_putc(m, '\n'); | |
b25cb2f8 | 279 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
280 | } |
281 | mutex_unlock(&dev->struct_mutex); | |
282 | ||
283 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
284 | count, total_obj_size, total_gtt_size); | |
285 | return 0; | |
286 | } | |
287 | ||
6299f992 CW |
288 | #define count_objects(list, member) do { \ |
289 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 290 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
291 | ++count; \ |
292 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 293 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
294 | ++mappable_count; \ |
295 | } \ | |
296 | } \ | |
0206e353 | 297 | } while (0) |
6299f992 | 298 | |
2db8e9d6 CW |
299 | struct file_stats { |
300 | int count; | |
301 | size_t total, active, inactive, unbound; | |
302 | }; | |
303 | ||
304 | static int per_file_stats(int id, void *ptr, void *data) | |
305 | { | |
306 | struct drm_i915_gem_object *obj = ptr; | |
307 | struct file_stats *stats = data; | |
308 | ||
309 | stats->count++; | |
310 | stats->total += obj->base.size; | |
311 | ||
f343c5f6 | 312 | if (i915_gem_obj_ggtt_bound(obj)) { |
2db8e9d6 CW |
313 | if (!list_empty(&obj->ring_list)) |
314 | stats->active += obj->base.size; | |
315 | else | |
316 | stats->inactive += obj->base.size; | |
317 | } else { | |
318 | if (!list_empty(&obj->global_list)) | |
319 | stats->unbound += obj->base.size; | |
320 | } | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
ca191b13 BW |
325 | #define count_vmas(list, member) do { \ |
326 | list_for_each_entry(vma, list, member) { \ | |
327 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
328 | ++count; \ | |
329 | if (vma->obj->map_and_fenceable) { \ | |
330 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
331 | ++mappable_count; \ | |
332 | } \ | |
333 | } \ | |
334 | } while (0) | |
335 | ||
336 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f CW |
337 | { |
338 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
339 | struct drm_device *dev = node->minor->dev; | |
340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
341 | u32 count, mappable_count, purgeable_count; |
342 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 343 | struct drm_i915_gem_object *obj; |
5cef07e1 | 344 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 345 | struct drm_file *file; |
ca191b13 | 346 | struct i915_vma *vma; |
73aa808f CW |
347 | int ret; |
348 | ||
349 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
350 | if (ret) | |
351 | return ret; | |
352 | ||
6299f992 CW |
353 | seq_printf(m, "%u objects, %zu bytes\n", |
354 | dev_priv->mm.object_count, | |
355 | dev_priv->mm.object_memory); | |
356 | ||
357 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 358 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
359 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
360 | count, mappable_count, size, mappable_size); | |
361 | ||
362 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 363 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
364 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
365 | count, mappable_count, size, mappable_size); | |
366 | ||
6299f992 | 367 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 368 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
369 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
370 | count, mappable_count, size, mappable_size); | |
371 | ||
b7abb714 | 372 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 373 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 374 | size += obj->base.size, ++count; |
b7abb714 CW |
375 | if (obj->madv == I915_MADV_DONTNEED) |
376 | purgeable_size += obj->base.size, ++purgeable_count; | |
377 | } | |
6c085a72 CW |
378 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
379 | ||
6299f992 | 380 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 381 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 382 | if (obj->fault_mappable) { |
f343c5f6 | 383 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
384 | ++count; |
385 | } | |
386 | if (obj->pin_mappable) { | |
f343c5f6 | 387 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
388 | ++mappable_count; |
389 | } | |
b7abb714 CW |
390 | if (obj->madv == I915_MADV_DONTNEED) { |
391 | purgeable_size += obj->base.size; | |
392 | ++purgeable_count; | |
393 | } | |
6299f992 | 394 | } |
b7abb714 CW |
395 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
396 | purgeable_count, purgeable_size); | |
6299f992 CW |
397 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
398 | mappable_count, mappable_size); | |
399 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
400 | count, size); | |
401 | ||
93d18799 | 402 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
403 | dev_priv->gtt.base.total, |
404 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 405 | |
267f0c90 | 406 | seq_putc(m, '\n'); |
2db8e9d6 CW |
407 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
408 | struct file_stats stats; | |
409 | ||
410 | memset(&stats, 0, sizeof(stats)); | |
411 | idr_for_each(&file->object_idr, per_file_stats, &stats); | |
412 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n", | |
413 | get_pid_task(file->pid, PIDTYPE_PID)->comm, | |
414 | stats.count, | |
415 | stats.total, | |
416 | stats.active, | |
417 | stats.inactive, | |
418 | stats.unbound); | |
419 | } | |
420 | ||
73aa808f CW |
421 | mutex_unlock(&dev->struct_mutex); |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
aee56cff | 426 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 CW |
427 | { |
428 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
429 | struct drm_device *dev = node->minor->dev; | |
1b50247a | 430 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
431 | struct drm_i915_private *dev_priv = dev->dev_private; |
432 | struct drm_i915_gem_object *obj; | |
433 | size_t total_obj_size, total_gtt_size; | |
434 | int count, ret; | |
435 | ||
436 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
437 | if (ret) | |
438 | return ret; | |
439 | ||
440 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 441 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
1b50247a CW |
442 | if (list == PINNED_LIST && obj->pin_count == 0) |
443 | continue; | |
444 | ||
267f0c90 | 445 | seq_puts(m, " "); |
08c18323 | 446 | describe_obj(m, obj); |
267f0c90 | 447 | seq_putc(m, '\n'); |
08c18323 | 448 | total_obj_size += obj->base.size; |
f343c5f6 | 449 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
450 | count++; |
451 | } | |
452 | ||
453 | mutex_unlock(&dev->struct_mutex); | |
454 | ||
455 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
456 | count, total_obj_size, total_gtt_size); | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
4e5359cd SF |
461 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
462 | { | |
463 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
464 | struct drm_device *dev = node->minor->dev; | |
465 | unsigned long flags; | |
466 | struct intel_crtc *crtc; | |
467 | ||
468 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9db4a9c7 JB |
469 | const char pipe = pipe_name(crtc->pipe); |
470 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
471 | struct intel_unpin_work *work; |
472 | ||
473 | spin_lock_irqsave(&dev->event_lock, flags); | |
474 | work = crtc->unpin_work; | |
475 | if (work == NULL) { | |
9db4a9c7 | 476 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
477 | pipe, plane); |
478 | } else { | |
e7d841ca | 479 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 480 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
481 | pipe, plane); |
482 | } else { | |
9db4a9c7 | 483 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
484 | pipe, plane); |
485 | } | |
486 | if (work->enable_stall_check) | |
267f0c90 | 487 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 488 | else |
267f0c90 | 489 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 490 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
491 | |
492 | if (work->old_fb_obj) { | |
05394f39 CW |
493 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
494 | if (obj) | |
f343c5f6 BW |
495 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
496 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
497 | } |
498 | if (work->pending_flip_obj) { | |
05394f39 CW |
499 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
500 | if (obj) | |
f343c5f6 BW |
501 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
502 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
503 | } |
504 | } | |
505 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
506 | } | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
2017263e BG |
511 | static int i915_gem_request_info(struct seq_file *m, void *data) |
512 | { | |
513 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
514 | struct drm_device *dev = node->minor->dev; | |
515 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 516 | struct intel_ring_buffer *ring; |
2017263e | 517 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 518 | int ret, count, i; |
de227ef0 CW |
519 | |
520 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
521 | if (ret) | |
522 | return ret; | |
2017263e | 523 | |
c2c347a9 | 524 | count = 0; |
a2c7f6fd CW |
525 | for_each_ring(ring, dev_priv, i) { |
526 | if (list_empty(&ring->request_list)) | |
527 | continue; | |
528 | ||
529 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 530 | list_for_each_entry(gem_request, |
a2c7f6fd | 531 | &ring->request_list, |
c2c347a9 CW |
532 | list) { |
533 | seq_printf(m, " %d @ %d\n", | |
534 | gem_request->seqno, | |
535 | (int) (jiffies - gem_request->emitted_jiffies)); | |
536 | } | |
537 | count++; | |
2017263e | 538 | } |
de227ef0 CW |
539 | mutex_unlock(&dev->struct_mutex); |
540 | ||
c2c347a9 | 541 | if (count == 0) |
267f0c90 | 542 | seq_puts(m, "No requests\n"); |
c2c347a9 | 543 | |
2017263e BG |
544 | return 0; |
545 | } | |
546 | ||
b2223497 CW |
547 | static void i915_ring_seqno_info(struct seq_file *m, |
548 | struct intel_ring_buffer *ring) | |
549 | { | |
550 | if (ring->get_seqno) { | |
43a7b924 | 551 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 552 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
553 | } |
554 | } | |
555 | ||
2017263e BG |
556 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
557 | { | |
558 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
559 | struct drm_device *dev = node->minor->dev; | |
560 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 561 | struct intel_ring_buffer *ring; |
1ec14ad3 | 562 | int ret, i; |
de227ef0 CW |
563 | |
564 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
565 | if (ret) | |
566 | return ret; | |
2017263e | 567 | |
a2c7f6fd CW |
568 | for_each_ring(ring, dev_priv, i) |
569 | i915_ring_seqno_info(m, ring); | |
de227ef0 CW |
570 | |
571 | mutex_unlock(&dev->struct_mutex); | |
572 | ||
2017263e BG |
573 | return 0; |
574 | } | |
575 | ||
576 | ||
577 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
578 | { | |
579 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
580 | struct drm_device *dev = node->minor->dev; | |
581 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a2c7f6fd | 582 | struct intel_ring_buffer *ring; |
9db4a9c7 | 583 | int ret, i, pipe; |
de227ef0 CW |
584 | |
585 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
586 | if (ret) | |
587 | return ret; | |
2017263e | 588 | |
a123f157 BW |
589 | if (INTEL_INFO(dev)->gen >= 8) { |
590 | int i; | |
591 | seq_printf(m, "Master Interrupt Control:\t%08x\n", | |
592 | I915_READ(GEN8_MASTER_IRQ)); | |
593 | ||
594 | for (i = 0; i < 4; i++) { | |
595 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
596 | i, I915_READ(GEN8_GT_IMR(i))); | |
597 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
598 | i, I915_READ(GEN8_GT_IIR(i))); | |
599 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
600 | i, I915_READ(GEN8_GT_IER(i))); | |
601 | } | |
602 | ||
603 | for_each_pipe(i) { | |
604 | seq_printf(m, "Pipe %c IMR:\t%08x\n", | |
605 | pipe_name(i), | |
606 | I915_READ(GEN8_DE_PIPE_IMR(i))); | |
607 | seq_printf(m, "Pipe %c IIR:\t%08x\n", | |
608 | pipe_name(i), | |
609 | I915_READ(GEN8_DE_PIPE_IIR(i))); | |
610 | seq_printf(m, "Pipe %c IER:\t%08x\n", | |
611 | pipe_name(i), | |
612 | I915_READ(GEN8_DE_PIPE_IER(i))); | |
613 | } | |
614 | ||
615 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
616 | I915_READ(GEN8_DE_PORT_IMR)); | |
617 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
618 | I915_READ(GEN8_DE_PORT_IIR)); | |
619 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
620 | I915_READ(GEN8_DE_PORT_IER)); | |
621 | ||
622 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
623 | I915_READ(GEN8_DE_MISC_IMR)); | |
624 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
625 | I915_READ(GEN8_DE_MISC_IIR)); | |
626 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
627 | I915_READ(GEN8_DE_MISC_IER)); | |
628 | ||
629 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
630 | I915_READ(GEN8_PCU_IMR)); | |
631 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
632 | I915_READ(GEN8_PCU_IIR)); | |
633 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
634 | I915_READ(GEN8_PCU_IER)); | |
635 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
636 | seq_printf(m, "Display IER:\t%08x\n", |
637 | I915_READ(VLV_IER)); | |
638 | seq_printf(m, "Display IIR:\t%08x\n", | |
639 | I915_READ(VLV_IIR)); | |
640 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
641 | I915_READ(VLV_IIR_RW)); | |
642 | seq_printf(m, "Display IMR:\t%08x\n", | |
643 | I915_READ(VLV_IMR)); | |
644 | for_each_pipe(pipe) | |
645 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
646 | pipe_name(pipe), | |
647 | I915_READ(PIPESTAT(pipe))); | |
648 | ||
649 | seq_printf(m, "Master IER:\t%08x\n", | |
650 | I915_READ(VLV_MASTER_IER)); | |
651 | ||
652 | seq_printf(m, "Render IER:\t%08x\n", | |
653 | I915_READ(GTIER)); | |
654 | seq_printf(m, "Render IIR:\t%08x\n", | |
655 | I915_READ(GTIIR)); | |
656 | seq_printf(m, "Render IMR:\t%08x\n", | |
657 | I915_READ(GTIMR)); | |
658 | ||
659 | seq_printf(m, "PM IER:\t\t%08x\n", | |
660 | I915_READ(GEN6_PMIER)); | |
661 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
662 | I915_READ(GEN6_PMIIR)); | |
663 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
664 | I915_READ(GEN6_PMIMR)); | |
665 | ||
666 | seq_printf(m, "Port hotplug:\t%08x\n", | |
667 | I915_READ(PORT_HOTPLUG_EN)); | |
668 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
669 | I915_READ(VLV_DPFLIPSTAT)); | |
670 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
671 | I915_READ(DPINVGTT)); | |
672 | ||
673 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
674 | seq_printf(m, "Interrupt enable: %08x\n", |
675 | I915_READ(IER)); | |
676 | seq_printf(m, "Interrupt identity: %08x\n", | |
677 | I915_READ(IIR)); | |
678 | seq_printf(m, "Interrupt mask: %08x\n", | |
679 | I915_READ(IMR)); | |
9db4a9c7 JB |
680 | for_each_pipe(pipe) |
681 | seq_printf(m, "Pipe %c stat: %08x\n", | |
682 | pipe_name(pipe), | |
683 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
684 | } else { |
685 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
686 | I915_READ(DEIER)); | |
687 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
688 | I915_READ(DEIIR)); | |
689 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
690 | I915_READ(DEIMR)); | |
691 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
692 | I915_READ(SDEIER)); | |
693 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
694 | I915_READ(SDEIIR)); | |
695 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
696 | I915_READ(SDEIMR)); | |
697 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
698 | I915_READ(GTIER)); | |
699 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
700 | I915_READ(GTIIR)); | |
701 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
702 | I915_READ(GTIMR)); | |
703 | } | |
2017263e BG |
704 | seq_printf(m, "Interrupts received: %d\n", |
705 | atomic_read(&dev_priv->irq_received)); | |
a2c7f6fd | 706 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 707 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
708 | seq_printf(m, |
709 | "Graphics Interrupt mask (%s): %08x\n", | |
710 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 711 | } |
a2c7f6fd | 712 | i915_ring_seqno_info(m, ring); |
9862e600 | 713 | } |
de227ef0 CW |
714 | mutex_unlock(&dev->struct_mutex); |
715 | ||
2017263e BG |
716 | return 0; |
717 | } | |
718 | ||
a6172a80 CW |
719 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
720 | { | |
721 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
722 | struct drm_device *dev = node->minor->dev; | |
723 | drm_i915_private_t *dev_priv = dev->dev_private; | |
de227ef0 CW |
724 | int i, ret; |
725 | ||
726 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
727 | if (ret) | |
728 | return ret; | |
a6172a80 CW |
729 | |
730 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
731 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
732 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 733 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 734 | |
6c085a72 CW |
735 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
736 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 737 | if (obj == NULL) |
267f0c90 | 738 | seq_puts(m, "unused"); |
c2c347a9 | 739 | else |
05394f39 | 740 | describe_obj(m, obj); |
267f0c90 | 741 | seq_putc(m, '\n'); |
a6172a80 CW |
742 | } |
743 | ||
05394f39 | 744 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
745 | return 0; |
746 | } | |
747 | ||
2017263e BG |
748 | static int i915_hws_info(struct seq_file *m, void *data) |
749 | { | |
750 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
751 | struct drm_device *dev = node->minor->dev; | |
752 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066c0ae | 753 | struct intel_ring_buffer *ring; |
1a240d4d | 754 | const u32 *hws; |
4066c0ae CW |
755 | int i; |
756 | ||
1ec14ad3 | 757 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 758 | hws = ring->status_page.page_addr; |
2017263e BG |
759 | if (hws == NULL) |
760 | return 0; | |
761 | ||
762 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
763 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
764 | i * 4, | |
765 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
766 | } | |
767 | return 0; | |
768 | } | |
769 | ||
d5442303 DV |
770 | static ssize_t |
771 | i915_error_state_write(struct file *filp, | |
772 | const char __user *ubuf, | |
773 | size_t cnt, | |
774 | loff_t *ppos) | |
775 | { | |
edc3d884 | 776 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 777 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 778 | int ret; |
d5442303 DV |
779 | |
780 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
781 | ||
22bcfc6a DV |
782 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
783 | if (ret) | |
784 | return ret; | |
785 | ||
d5442303 DV |
786 | i915_destroy_error_state(dev); |
787 | mutex_unlock(&dev->struct_mutex); | |
788 | ||
789 | return cnt; | |
790 | } | |
791 | ||
792 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
793 | { | |
794 | struct drm_device *dev = inode->i_private; | |
d5442303 | 795 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
796 | |
797 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
798 | if (!error_priv) | |
799 | return -ENOMEM; | |
800 | ||
801 | error_priv->dev = dev; | |
802 | ||
95d5bfb3 | 803 | i915_error_state_get(dev, error_priv); |
d5442303 | 804 | |
edc3d884 MK |
805 | file->private_data = error_priv; |
806 | ||
807 | return 0; | |
d5442303 DV |
808 | } |
809 | ||
810 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
811 | { | |
edc3d884 | 812 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 813 | |
95d5bfb3 | 814 | i915_error_state_put(error_priv); |
d5442303 DV |
815 | kfree(error_priv); |
816 | ||
edc3d884 MK |
817 | return 0; |
818 | } | |
819 | ||
4dc955f7 MK |
820 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
821 | size_t count, loff_t *pos) | |
822 | { | |
823 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
824 | struct drm_i915_error_state_buf error_str; | |
825 | loff_t tmp_pos = 0; | |
826 | ssize_t ret_count = 0; | |
827 | int ret; | |
828 | ||
829 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
830 | if (ret) | |
831 | return ret; | |
edc3d884 | 832 | |
fc16b48b | 833 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
834 | if (ret) |
835 | goto out; | |
836 | ||
edc3d884 MK |
837 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
838 | error_str.buf, | |
839 | error_str.bytes); | |
840 | ||
841 | if (ret_count < 0) | |
842 | ret = ret_count; | |
843 | else | |
844 | *pos = error_str.start + ret_count; | |
845 | out: | |
4dc955f7 | 846 | i915_error_state_buf_release(&error_str); |
edc3d884 | 847 | return ret ?: ret_count; |
d5442303 DV |
848 | } |
849 | ||
850 | static const struct file_operations i915_error_state_fops = { | |
851 | .owner = THIS_MODULE, | |
852 | .open = i915_error_state_open, | |
edc3d884 | 853 | .read = i915_error_state_read, |
d5442303 DV |
854 | .write = i915_error_state_write, |
855 | .llseek = default_llseek, | |
856 | .release = i915_error_state_release, | |
857 | }; | |
858 | ||
647416f9 KC |
859 | static int |
860 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 861 | { |
647416f9 | 862 | struct drm_device *dev = data; |
40633219 | 863 | drm_i915_private_t *dev_priv = dev->dev_private; |
40633219 MK |
864 | int ret; |
865 | ||
866 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
867 | if (ret) | |
868 | return ret; | |
869 | ||
647416f9 | 870 | *val = dev_priv->next_seqno; |
40633219 MK |
871 | mutex_unlock(&dev->struct_mutex); |
872 | ||
647416f9 | 873 | return 0; |
40633219 MK |
874 | } |
875 | ||
647416f9 KC |
876 | static int |
877 | i915_next_seqno_set(void *data, u64 val) | |
878 | { | |
879 | struct drm_device *dev = data; | |
40633219 MK |
880 | int ret; |
881 | ||
40633219 MK |
882 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
883 | if (ret) | |
884 | return ret; | |
885 | ||
e94fbaa8 | 886 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
887 | mutex_unlock(&dev->struct_mutex); |
888 | ||
647416f9 | 889 | return ret; |
40633219 MK |
890 | } |
891 | ||
647416f9 KC |
892 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
893 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 894 | "0x%llx\n"); |
40633219 | 895 | |
f97108d1 JB |
896 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
897 | { | |
898 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
899 | struct drm_device *dev = node->minor->dev; | |
900 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
901 | u16 crstanddelay; |
902 | int ret; | |
903 | ||
904 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
905 | if (ret) | |
906 | return ret; | |
907 | ||
908 | crstanddelay = I915_READ16(CRSTANDVID); | |
909 | ||
910 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
911 | |
912 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
913 | ||
914 | return 0; | |
915 | } | |
916 | ||
917 | static int i915_cur_delayinfo(struct seq_file *m, void *unused) | |
918 | { | |
919 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
920 | struct drm_device *dev = node->minor->dev; | |
921 | drm_i915_private_t *dev_priv = dev->dev_private; | |
d1ebd816 | 922 | int ret; |
3b8d8d91 | 923 | |
5c9669ce TR |
924 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
925 | ||
3b8d8d91 JB |
926 | if (IS_GEN5(dev)) { |
927 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
928 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
929 | ||
930 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
931 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
932 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
933 | MEMSTAT_VID_SHIFT); | |
934 | seq_printf(m, "Current P-state: %d\n", | |
935 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
0a073b84 | 936 | } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
3b8d8d91 JB |
937 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
938 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
939 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
8e8c06cd | 940 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
941 | u32 rpupei, rpcurup, rpprevup; |
942 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
943 | int max_freq; |
944 | ||
945 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
946 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
947 | if (ret) | |
948 | return ret; | |
949 | ||
c8d9a590 | 950 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 951 | |
8e8c06cd CW |
952 | reqf = I915_READ(GEN6_RPNSWREQ); |
953 | reqf &= ~GEN6_TURBO_DISABLE; | |
954 | if (IS_HASWELL(dev)) | |
955 | reqf >>= 24; | |
956 | else | |
957 | reqf >>= 25; | |
958 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
959 | ||
ccab5c82 JB |
960 | rpstat = I915_READ(GEN6_RPSTAT1); |
961 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
962 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
963 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
964 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
965 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
966 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
f82855d3 BW |
967 | if (IS_HASWELL(dev)) |
968 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; | |
969 | else | |
970 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
971 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 972 | |
c8d9a590 | 973 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
974 | mutex_unlock(&dev->struct_mutex); |
975 | ||
3b8d8d91 | 976 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
ccab5c82 | 977 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
3b8d8d91 JB |
978 | seq_printf(m, "Render p-state ratio: %d\n", |
979 | (gt_perf_status & 0xff00) >> 8); | |
980 | seq_printf(m, "Render p-state VID: %d\n", | |
981 | gt_perf_status & 0xff); | |
982 | seq_printf(m, "Render p-state limit: %d\n", | |
983 | rp_state_limits & 0xff); | |
8e8c06cd | 984 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 985 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
986 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
987 | GEN6_CURICONT_MASK); | |
988 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
989 | GEN6_CURBSYTAVG_MASK); | |
990 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
991 | GEN6_CURBSYTAVG_MASK); | |
992 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
993 | GEN6_CURIAVG_MASK); | |
994 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
995 | GEN6_CURBSYTAVG_MASK); | |
996 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
997 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
998 | |
999 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
1000 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 1001 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1002 | |
1003 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
1004 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 1005 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1006 | |
1007 | max_freq = rp_state_cap & 0xff; | |
1008 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 1009 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
1010 | |
1011 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
1012 | dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER); | |
0a073b84 JB |
1013 | } else if (IS_VALLEYVIEW(dev)) { |
1014 | u32 freq_sts, val; | |
1015 | ||
259bd5d4 | 1016 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1017 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1018 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1019 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1020 | ||
c5bd2bf6 | 1021 | val = valleyview_rps_max_freq(dev_priv); |
0a073b84 | 1022 | seq_printf(m, "max GPU freq: %d MHz\n", |
2ec3815f | 1023 | vlv_gpu_freq(dev_priv, val)); |
0a073b84 | 1024 | |
c5bd2bf6 | 1025 | val = valleyview_rps_min_freq(dev_priv); |
0a073b84 | 1026 | seq_printf(m, "min GPU freq: %d MHz\n", |
2ec3815f | 1027 | vlv_gpu_freq(dev_priv, val)); |
0a073b84 JB |
1028 | |
1029 | seq_printf(m, "current GPU freq: %d MHz\n", | |
2ec3815f | 1030 | vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
259bd5d4 | 1031 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1032 | } else { |
267f0c90 | 1033 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1034 | } |
f97108d1 JB |
1035 | |
1036 | return 0; | |
1037 | } | |
1038 | ||
1039 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
1040 | { | |
1041 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1042 | struct drm_device *dev = node->minor->dev; | |
1043 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1044 | u32 delayfreq; | |
616fdb5a BW |
1045 | int ret, i; |
1046 | ||
1047 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1048 | if (ret) | |
1049 | return ret; | |
f97108d1 JB |
1050 | |
1051 | for (i = 0; i < 16; i++) { | |
1052 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
1053 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
1054 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
1055 | } |
1056 | ||
616fdb5a BW |
1057 | mutex_unlock(&dev->struct_mutex); |
1058 | ||
f97108d1 JB |
1059 | return 0; |
1060 | } | |
1061 | ||
1062 | static inline int MAP_TO_MV(int map) | |
1063 | { | |
1064 | return 1250 - (map * 25); | |
1065 | } | |
1066 | ||
1067 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
1068 | { | |
1069 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1070 | struct drm_device *dev = node->minor->dev; | |
1071 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1072 | u32 inttoext; | |
616fdb5a BW |
1073 | int ret, i; |
1074 | ||
1075 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1076 | if (ret) | |
1077 | return ret; | |
f97108d1 JB |
1078 | |
1079 | for (i = 1; i <= 32; i++) { | |
1080 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1081 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1082 | } | |
1083 | ||
616fdb5a BW |
1084 | mutex_unlock(&dev->struct_mutex); |
1085 | ||
f97108d1 JB |
1086 | return 0; |
1087 | } | |
1088 | ||
4d85529d | 1089 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 JB |
1090 | { |
1091 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1092 | struct drm_device *dev = node->minor->dev; | |
1093 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1094 | u32 rgvmodectl, rstdbyctl; |
1095 | u16 crstandvid; | |
1096 | int ret; | |
1097 | ||
1098 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1099 | if (ret) | |
1100 | return ret; | |
1101 | ||
1102 | rgvmodectl = I915_READ(MEMMODECTL); | |
1103 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1104 | crstandvid = I915_READ16(CRSTANDVID); | |
1105 | ||
1106 | mutex_unlock(&dev->struct_mutex); | |
f97108d1 JB |
1107 | |
1108 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1109 | "yes" : "no"); | |
1110 | seq_printf(m, "Boost freq: %d\n", | |
1111 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1112 | MEMMODE_BOOST_FREQ_SHIFT); | |
1113 | seq_printf(m, "HW control enabled: %s\n", | |
1114 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1115 | seq_printf(m, "SW control enabled: %s\n", | |
1116 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1117 | seq_printf(m, "Gated voltage change: %s\n", | |
1118 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1119 | seq_printf(m, "Starting frequency: P%d\n", | |
1120 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1121 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1122 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1123 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1124 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1125 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1126 | seq_printf(m, "Render standby enabled: %s\n", | |
1127 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1128 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1129 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1130 | case RSX_STATUS_ON: | |
267f0c90 | 1131 | seq_puts(m, "on\n"); |
88271da3 JB |
1132 | break; |
1133 | case RSX_STATUS_RC1: | |
267f0c90 | 1134 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1135 | break; |
1136 | case RSX_STATUS_RC1E: | |
267f0c90 | 1137 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1138 | break; |
1139 | case RSX_STATUS_RS1: | |
267f0c90 | 1140 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1141 | break; |
1142 | case RSX_STATUS_RS2: | |
267f0c90 | 1143 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1144 | break; |
1145 | case RSX_STATUS_RS3: | |
267f0c90 | 1146 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1147 | break; |
1148 | default: | |
267f0c90 | 1149 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1150 | break; |
1151 | } | |
f97108d1 JB |
1152 | |
1153 | return 0; | |
1154 | } | |
1155 | ||
4d85529d BW |
1156 | static int gen6_drpc_info(struct seq_file *m) |
1157 | { | |
1158 | ||
1159 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1160 | struct drm_device *dev = node->minor->dev; | |
1161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1162 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1163 | unsigned forcewake_count; |
aee56cff | 1164 | int count = 0, ret; |
4d85529d BW |
1165 | |
1166 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1167 | if (ret) | |
1168 | return ret; | |
1169 | ||
907b28c5 CW |
1170 | spin_lock_irq(&dev_priv->uncore.lock); |
1171 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1172 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1173 | |
1174 | if (forcewake_count) { | |
267f0c90 DL |
1175 | seq_puts(m, "RC information inaccurate because somebody " |
1176 | "holds a forcewake reference \n"); | |
4d85529d BW |
1177 | } else { |
1178 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1179 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1180 | udelay(10); | |
1181 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1182 | } | |
1183 | ||
1184 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1185 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1186 | |
1187 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1188 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1189 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1190 | mutex_lock(&dev_priv->rps.hw_lock); |
1191 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1192 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d BW |
1193 | |
1194 | seq_printf(m, "Video Turbo Mode: %s\n", | |
1195 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1196 | seq_printf(m, "HW control enabled: %s\n", | |
1197 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1198 | seq_printf(m, "SW control enabled: %s\n", | |
1199 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1200 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1201 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1202 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1203 | seq_printf(m, "RC6 Enabled: %s\n", | |
1204 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1205 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1206 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1207 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1208 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1209 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1210 | switch (gt_core_status & GEN6_RCn_MASK) { |
1211 | case GEN6_RC0: | |
1212 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1213 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1214 | else |
267f0c90 | 1215 | seq_puts(m, "on\n"); |
4d85529d BW |
1216 | break; |
1217 | case GEN6_RC3: | |
267f0c90 | 1218 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1219 | break; |
1220 | case GEN6_RC6: | |
267f0c90 | 1221 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1222 | break; |
1223 | case GEN6_RC7: | |
267f0c90 | 1224 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1225 | break; |
1226 | default: | |
267f0c90 | 1227 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1228 | break; |
1229 | } | |
1230 | ||
1231 | seq_printf(m, "Core Power Down: %s\n", | |
1232 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1233 | |
1234 | /* Not exactly sure what this is */ | |
1235 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1236 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1237 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1238 | I915_READ(GEN6_GT_GFX_RC6)); | |
1239 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1240 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1241 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1242 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1243 | ||
ecd8faea BW |
1244 | seq_printf(m, "RC6 voltage: %dmV\n", |
1245 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1246 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1247 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1248 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1249 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1250 | return 0; |
1251 | } | |
1252 | ||
1253 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1254 | { | |
1255 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1256 | struct drm_device *dev = node->minor->dev; | |
1257 | ||
1258 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1259 | return gen6_drpc_info(m); | |
1260 | else | |
1261 | return ironlake_drpc_info(m); | |
1262 | } | |
1263 | ||
b5e50c3f JB |
1264 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1265 | { | |
1266 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1267 | struct drm_device *dev = node->minor->dev; | |
b5e50c3f | 1268 | drm_i915_private_t *dev_priv = dev->dev_private; |
b5e50c3f | 1269 | |
ee5382ae | 1270 | if (!I915_HAS_FBC(dev)) { |
267f0c90 | 1271 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1272 | return 0; |
1273 | } | |
1274 | ||
ee5382ae | 1275 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1276 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1277 | } else { |
267f0c90 | 1278 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1279 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1280 | case FBC_OK: |
1281 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1282 | break; | |
1283 | case FBC_UNSUPPORTED: | |
1284 | seq_puts(m, "unsupported by this chipset"); | |
1285 | break; | |
bed4a673 | 1286 | case FBC_NO_OUTPUT: |
267f0c90 | 1287 | seq_puts(m, "no outputs"); |
bed4a673 | 1288 | break; |
b5e50c3f | 1289 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1290 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1291 | break; |
1292 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1293 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1294 | break; |
1295 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1296 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1297 | break; |
1298 | case FBC_BAD_PLANE: | |
267f0c90 | 1299 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1300 | break; |
1301 | case FBC_NOT_TILED: | |
267f0c90 | 1302 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1303 | break; |
9c928d16 | 1304 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1305 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1306 | break; |
c1a9f047 | 1307 | case FBC_MODULE_PARAM: |
267f0c90 | 1308 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1309 | break; |
8a5729a3 | 1310 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1311 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1312 | break; |
b5e50c3f | 1313 | default: |
267f0c90 | 1314 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1315 | } |
267f0c90 | 1316 | seq_putc(m, '\n'); |
b5e50c3f JB |
1317 | } |
1318 | return 0; | |
1319 | } | |
1320 | ||
92d44621 PZ |
1321 | static int i915_ips_status(struct seq_file *m, void *unused) |
1322 | { | |
1323 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1324 | struct drm_device *dev = node->minor->dev; | |
1325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1326 | ||
f5adf94e | 1327 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1328 | seq_puts(m, "not supported\n"); |
1329 | return 0; | |
1330 | } | |
1331 | ||
1332 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1333 | seq_puts(m, "enabled\n"); | |
1334 | else | |
1335 | seq_puts(m, "disabled\n"); | |
1336 | ||
1337 | return 0; | |
1338 | } | |
1339 | ||
4a9bef37 JB |
1340 | static int i915_sr_status(struct seq_file *m, void *unused) |
1341 | { | |
1342 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1343 | struct drm_device *dev = node->minor->dev; | |
1344 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1345 | bool sr_enabled = false; | |
1346 | ||
1398261a | 1347 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1348 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1349 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1350 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1351 | else if (IS_I915GM(dev)) | |
1352 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1353 | else if (IS_PINEVIEW(dev)) | |
1354 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1355 | ||
5ba2aaaa CW |
1356 | seq_printf(m, "self-refresh: %s\n", |
1357 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1358 | |
1359 | return 0; | |
1360 | } | |
1361 | ||
7648fa99 JB |
1362 | static int i915_emon_status(struct seq_file *m, void *unused) |
1363 | { | |
1364 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1365 | struct drm_device *dev = node->minor->dev; | |
1366 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1367 | unsigned long temp, chipset, gfx; | |
de227ef0 CW |
1368 | int ret; |
1369 | ||
582be6b4 CW |
1370 | if (!IS_GEN5(dev)) |
1371 | return -ENODEV; | |
1372 | ||
de227ef0 CW |
1373 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1374 | if (ret) | |
1375 | return ret; | |
7648fa99 JB |
1376 | |
1377 | temp = i915_mch_val(dev_priv); | |
1378 | chipset = i915_chipset_val(dev_priv); | |
1379 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1380 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1381 | |
1382 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1383 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1384 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1385 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1386 | ||
1387 | return 0; | |
1388 | } | |
1389 | ||
23b2f8bb JB |
1390 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1391 | { | |
1392 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1393 | struct drm_device *dev = node->minor->dev; | |
1394 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1395 | int ret; | |
1396 | int gpu_freq, ia_freq; | |
1397 | ||
1c70c0ce | 1398 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1399 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1400 | return 0; |
1401 | } | |
1402 | ||
5c9669ce TR |
1403 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1404 | ||
4fc688ce | 1405 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1406 | if (ret) |
1407 | return ret; | |
1408 | ||
267f0c90 | 1409 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1410 | |
c6a828d3 DV |
1411 | for (gpu_freq = dev_priv->rps.min_delay; |
1412 | gpu_freq <= dev_priv->rps.max_delay; | |
23b2f8bb | 1413 | gpu_freq++) { |
42c0526c BW |
1414 | ia_freq = gpu_freq; |
1415 | sandybridge_pcode_read(dev_priv, | |
1416 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1417 | &ia_freq); | |
3ebecd07 CW |
1418 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1419 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1420 | ((ia_freq >> 0) & 0xff) * 100, | |
1421 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1422 | } |
1423 | ||
4fc688ce | 1424 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb JB |
1425 | |
1426 | return 0; | |
1427 | } | |
1428 | ||
7648fa99 JB |
1429 | static int i915_gfxec(struct seq_file *m, void *unused) |
1430 | { | |
1431 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1432 | struct drm_device *dev = node->minor->dev; | |
1433 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616fdb5a BW |
1434 | int ret; |
1435 | ||
1436 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1437 | if (ret) | |
1438 | return ret; | |
7648fa99 JB |
1439 | |
1440 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
1441 | ||
616fdb5a BW |
1442 | mutex_unlock(&dev->struct_mutex); |
1443 | ||
7648fa99 JB |
1444 | return 0; |
1445 | } | |
1446 | ||
44834a67 CW |
1447 | static int i915_opregion(struct seq_file *m, void *unused) |
1448 | { | |
1449 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1450 | struct drm_device *dev = node->minor->dev; | |
1451 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1452 | struct intel_opregion *opregion = &dev_priv->opregion; | |
0d38f009 | 1453 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1454 | int ret; |
1455 | ||
0d38f009 DV |
1456 | if (data == NULL) |
1457 | return -ENOMEM; | |
1458 | ||
44834a67 CW |
1459 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1460 | if (ret) | |
0d38f009 | 1461 | goto out; |
44834a67 | 1462 | |
0d38f009 DV |
1463 | if (opregion->header) { |
1464 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1465 | seq_write(m, data, OPREGION_SIZE); | |
1466 | } | |
44834a67 CW |
1467 | |
1468 | mutex_unlock(&dev->struct_mutex); | |
1469 | ||
0d38f009 DV |
1470 | out: |
1471 | kfree(data); | |
44834a67 CW |
1472 | return 0; |
1473 | } | |
1474 | ||
37811fcc CW |
1475 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1476 | { | |
1477 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1478 | struct drm_device *dev = node->minor->dev; | |
4520f53a | 1479 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1480 | struct intel_framebuffer *fb; |
37811fcc | 1481 | |
4520f53a DV |
1482 | #ifdef CONFIG_DRM_I915_FBDEV |
1483 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1484 | int ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
37811fcc CW |
1485 | if (ret) |
1486 | return ret; | |
1487 | ||
1488 | ifbdev = dev_priv->fbdev; | |
1489 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1490 | ||
623f9783 | 1491 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1492 | fb->base.width, |
1493 | fb->base.height, | |
1494 | fb->base.depth, | |
623f9783 DV |
1495 | fb->base.bits_per_pixel, |
1496 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1497 | describe_obj(m, fb->obj); |
267f0c90 | 1498 | seq_putc(m, '\n'); |
4b096ac1 | 1499 | mutex_unlock(&dev->mode_config.mutex); |
4520f53a | 1500 | #endif |
37811fcc | 1501 | |
4b096ac1 | 1502 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc | 1503 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
131a56dc | 1504 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
37811fcc CW |
1505 | continue; |
1506 | ||
623f9783 | 1507 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1508 | fb->base.width, |
1509 | fb->base.height, | |
1510 | fb->base.depth, | |
623f9783 DV |
1511 | fb->base.bits_per_pixel, |
1512 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1513 | describe_obj(m, fb->obj); |
267f0c90 | 1514 | seq_putc(m, '\n'); |
37811fcc | 1515 | } |
4b096ac1 | 1516 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1517 | |
1518 | return 0; | |
1519 | } | |
1520 | ||
e76d3630 BW |
1521 | static int i915_context_status(struct seq_file *m, void *unused) |
1522 | { | |
1523 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1524 | struct drm_device *dev = node->minor->dev; | |
1525 | drm_i915_private_t *dev_priv = dev->dev_private; | |
a168c293 | 1526 | struct intel_ring_buffer *ring; |
a33afea5 | 1527 | struct i915_hw_context *ctx; |
a168c293 | 1528 | int ret, i; |
e76d3630 BW |
1529 | |
1530 | ret = mutex_lock_interruptible(&dev->mode_config.mutex); | |
1531 | if (ret) | |
1532 | return ret; | |
1533 | ||
3e373948 | 1534 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1535 | seq_puts(m, "power context "); |
3e373948 | 1536 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1537 | seq_putc(m, '\n'); |
dc501fbc | 1538 | } |
e76d3630 | 1539 | |
3e373948 | 1540 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1541 | seq_puts(m, "render context "); |
3e373948 | 1542 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1543 | seq_putc(m, '\n'); |
dc501fbc | 1544 | } |
e76d3630 | 1545 | |
a33afea5 BW |
1546 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
1547 | seq_puts(m, "HW context "); | |
3ccfd19d | 1548 | describe_ctx(m, ctx); |
a33afea5 BW |
1549 | for_each_ring(ring, dev_priv, i) |
1550 | if (ring->default_context == ctx) | |
1551 | seq_printf(m, "(default context %s) ", ring->name); | |
1552 | ||
1553 | describe_obj(m, ctx->obj); | |
1554 | seq_putc(m, '\n'); | |
a168c293 BW |
1555 | } |
1556 | ||
e76d3630 BW |
1557 | mutex_unlock(&dev->mode_config.mutex); |
1558 | ||
1559 | return 0; | |
1560 | } | |
1561 | ||
6d794d42 BW |
1562 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1563 | { | |
1564 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1565 | struct drm_device *dev = node->minor->dev; | |
1566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43709ba0 | 1567 | unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0; |
6d794d42 | 1568 | |
907b28c5 | 1569 | spin_lock_irq(&dev_priv->uncore.lock); |
43709ba0 D |
1570 | if (IS_VALLEYVIEW(dev)) { |
1571 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1572 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1573 | } else | |
1574 | forcewake_count = dev_priv->uncore.forcewake_count; | |
907b28c5 | 1575 | spin_unlock_irq(&dev_priv->uncore.lock); |
6d794d42 | 1576 | |
43709ba0 D |
1577 | if (IS_VALLEYVIEW(dev)) { |
1578 | seq_printf(m, "fw_rendercount = %u\n", fw_rendercount); | |
1579 | seq_printf(m, "fw_mediacount = %u\n", fw_mediacount); | |
1580 | } else | |
1581 | seq_printf(m, "forcewake count = %u\n", forcewake_count); | |
6d794d42 BW |
1582 | |
1583 | return 0; | |
1584 | } | |
1585 | ||
ea16a3cd DV |
1586 | static const char *swizzle_string(unsigned swizzle) |
1587 | { | |
aee56cff | 1588 | switch (swizzle) { |
ea16a3cd DV |
1589 | case I915_BIT_6_SWIZZLE_NONE: |
1590 | return "none"; | |
1591 | case I915_BIT_6_SWIZZLE_9: | |
1592 | return "bit9"; | |
1593 | case I915_BIT_6_SWIZZLE_9_10: | |
1594 | return "bit9/bit10"; | |
1595 | case I915_BIT_6_SWIZZLE_9_11: | |
1596 | return "bit9/bit11"; | |
1597 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1598 | return "bit9/bit10/bit11"; | |
1599 | case I915_BIT_6_SWIZZLE_9_17: | |
1600 | return "bit9/bit17"; | |
1601 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1602 | return "bit9/bit10/bit17"; | |
1603 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1604 | return "unknown"; |
ea16a3cd DV |
1605 | } |
1606 | ||
1607 | return "bug"; | |
1608 | } | |
1609 | ||
1610 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1611 | { | |
1612 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1613 | struct drm_device *dev = node->minor->dev; | |
1614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1615 | int ret; |
1616 | ||
1617 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1618 | if (ret) | |
1619 | return ret; | |
ea16a3cd | 1620 | |
ea16a3cd DV |
1621 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1622 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1623 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1624 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1625 | ||
1626 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1627 | seq_printf(m, "DDC = 0x%08x\n", | |
1628 | I915_READ(DCC)); | |
1629 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1630 | I915_READ16(C0DRB3)); | |
1631 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1632 | I915_READ16(C1DRB3)); | |
9d3203e1 | 1633 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
1634 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
1635 | I915_READ(MAD_DIMM_C0)); | |
1636 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1637 | I915_READ(MAD_DIMM_C1)); | |
1638 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1639 | I915_READ(MAD_DIMM_C2)); | |
1640 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1641 | I915_READ(TILECTL)); | |
9d3203e1 BW |
1642 | if (IS_GEN8(dev)) |
1643 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", | |
1644 | I915_READ(GAMTARBMODE)); | |
1645 | else | |
1646 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1647 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
1648 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
1649 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd DV |
1650 | } |
1651 | mutex_unlock(&dev->struct_mutex); | |
1652 | ||
1653 | return 0; | |
1654 | } | |
1655 | ||
77df6772 | 1656 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 1657 | { |
3cf17fc5 DV |
1658 | struct drm_i915_private *dev_priv = dev->dev_private; |
1659 | struct intel_ring_buffer *ring; | |
77df6772 BW |
1660 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1661 | int unused, i; | |
3cf17fc5 | 1662 | |
77df6772 BW |
1663 | if (!ppgtt) |
1664 | return; | |
1665 | ||
1666 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); | |
1667 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pt_pages); | |
1668 | for_each_ring(ring, dev_priv, unused) { | |
1669 | seq_printf(m, "%s\n", ring->name); | |
1670 | for (i = 0; i < 4; i++) { | |
1671 | u32 offset = 0x270 + i * 8; | |
1672 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); | |
1673 | pdp <<= 32; | |
1674 | pdp |= I915_READ(ring->mmio_base + offset); | |
1675 | for (i = 0; i < 4; i++) | |
1676 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); | |
1677 | } | |
1678 | } | |
1679 | } | |
1680 | ||
1681 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
1682 | { | |
1683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1684 | struct intel_ring_buffer *ring; | |
1685 | int i; | |
3cf17fc5 | 1686 | |
3cf17fc5 DV |
1687 | if (INTEL_INFO(dev)->gen == 6) |
1688 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1689 | ||
a2c7f6fd | 1690 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1691 | seq_printf(m, "%s\n", ring->name); |
1692 | if (INTEL_INFO(dev)->gen == 7) | |
1693 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1694 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1695 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1696 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1697 | } | |
1698 | if (dev_priv->mm.aliasing_ppgtt) { | |
1699 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1700 | ||
267f0c90 | 1701 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 DV |
1702 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1703 | } | |
1704 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
77df6772 BW |
1705 | } |
1706 | ||
1707 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
1708 | { | |
1709 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1710 | struct drm_device *dev = node->minor->dev; | |
1711 | ||
1712 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1713 | if (ret) | |
1714 | return ret; | |
1715 | ||
1716 | if (INTEL_INFO(dev)->gen >= 8) | |
1717 | gen8_ppgtt_info(m, dev); | |
1718 | else if (INTEL_INFO(dev)->gen >= 6) | |
1719 | gen6_ppgtt_info(m, dev); | |
1720 | ||
3cf17fc5 DV |
1721 | mutex_unlock(&dev->struct_mutex); |
1722 | ||
1723 | return 0; | |
1724 | } | |
1725 | ||
57f350b6 JB |
1726 | static int i915_dpio_info(struct seq_file *m, void *data) |
1727 | { | |
1728 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1729 | struct drm_device *dev = node->minor->dev; | |
1730 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1731 | int ret; | |
1732 | ||
1733 | ||
1734 | if (!IS_VALLEYVIEW(dev)) { | |
267f0c90 | 1735 | seq_puts(m, "unsupported\n"); |
57f350b6 JB |
1736 | return 0; |
1737 | } | |
1738 | ||
09153000 | 1739 | ret = mutex_lock_interruptible(&dev_priv->dpio_lock); |
57f350b6 JB |
1740 | if (ret) |
1741 | return ret; | |
1742 | ||
1743 | seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); | |
1744 | ||
ab3c759a CML |
1745 | seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n", |
1746 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0))); | |
1747 | seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n", | |
1748 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1))); | |
1749 | ||
1750 | seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n", | |
1751 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0))); | |
1752 | seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n", | |
1753 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1))); | |
1754 | ||
1755 | seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n", | |
1756 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0))); | |
1757 | seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n", | |
1758 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1))); | |
1759 | ||
1760 | seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n", | |
1761 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0))); | |
1762 | seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n", | |
1763 | vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1))); | |
57f350b6 JB |
1764 | |
1765 | seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", | |
ab3c759a | 1766 | vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0)); |
57f350b6 | 1767 | |
09153000 | 1768 | mutex_unlock(&dev_priv->dpio_lock); |
57f350b6 JB |
1769 | |
1770 | return 0; | |
1771 | } | |
1772 | ||
63573eb7 BW |
1773 | static int i915_llc(struct seq_file *m, void *data) |
1774 | { | |
1775 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1776 | struct drm_device *dev = node->minor->dev; | |
1777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1778 | ||
1779 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1780 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1781 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1782 | ||
1783 | return 0; | |
1784 | } | |
1785 | ||
e91fd8c6 RV |
1786 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1787 | { | |
1788 | struct drm_info_node *node = m->private; | |
1789 | struct drm_device *dev = node->minor->dev; | |
1790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1791 | u32 psrperf = 0; |
1792 | bool enabled = false; | |
e91fd8c6 | 1793 | |
a031d709 RV |
1794 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1795 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
e91fd8c6 | 1796 | |
a031d709 RV |
1797 | enabled = HAS_PSR(dev) && |
1798 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
1799 | seq_printf(m, "Enabled: %s\n", yesno(enabled)); | |
e91fd8c6 | 1800 | |
a031d709 RV |
1801 | if (HAS_PSR(dev)) |
1802 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1803 | EDP_PSR_PERF_CNT_MASK; | |
1804 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
e91fd8c6 RV |
1805 | |
1806 | return 0; | |
1807 | } | |
1808 | ||
ec013e7f JB |
1809 | static int i915_energy_uJ(struct seq_file *m, void *data) |
1810 | { | |
1811 | struct drm_info_node *node = m->private; | |
1812 | struct drm_device *dev = node->minor->dev; | |
1813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1814 | u64 power; | |
1815 | u32 units; | |
1816 | ||
1817 | if (INTEL_INFO(dev)->gen < 6) | |
1818 | return -ENODEV; | |
1819 | ||
1820 | rdmsrl(MSR_RAPL_POWER_UNIT, power); | |
1821 | power = (power & 0x1f00) >> 8; | |
1822 | units = 1000000 / (1 << power); /* convert to uJ */ | |
1823 | power = I915_READ(MCH_SECP_NRG_STTS); | |
1824 | power *= units; | |
1825 | ||
1826 | seq_printf(m, "%llu", (long long unsigned)power); | |
371db66a PZ |
1827 | |
1828 | return 0; | |
1829 | } | |
1830 | ||
1831 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
1832 | { | |
1833 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1834 | struct drm_device *dev = node->minor->dev; | |
1835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1836 | ||
1837 | if (!IS_HASWELL(dev)) { | |
1838 | seq_puts(m, "not supported\n"); | |
1839 | return 0; | |
1840 | } | |
1841 | ||
1842 | mutex_lock(&dev_priv->pc8.lock); | |
1843 | seq_printf(m, "Requirements met: %s\n", | |
1844 | yesno(dev_priv->pc8.requirements_met)); | |
1845 | seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle)); | |
1846 | seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count); | |
1847 | seq_printf(m, "IRQs disabled: %s\n", | |
1848 | yesno(dev_priv->pc8.irqs_disabled)); | |
1849 | seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled)); | |
1850 | mutex_unlock(&dev_priv->pc8.lock); | |
1851 | ||
ec013e7f JB |
1852 | return 0; |
1853 | } | |
1854 | ||
1da51581 ID |
1855 | static const char *power_domain_str(enum intel_display_power_domain domain) |
1856 | { | |
1857 | switch (domain) { | |
1858 | case POWER_DOMAIN_PIPE_A: | |
1859 | return "PIPE_A"; | |
1860 | case POWER_DOMAIN_PIPE_B: | |
1861 | return "PIPE_B"; | |
1862 | case POWER_DOMAIN_PIPE_C: | |
1863 | return "PIPE_C"; | |
1864 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
1865 | return "PIPE_A_PANEL_FITTER"; | |
1866 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
1867 | return "PIPE_B_PANEL_FITTER"; | |
1868 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
1869 | return "PIPE_C_PANEL_FITTER"; | |
1870 | case POWER_DOMAIN_TRANSCODER_A: | |
1871 | return "TRANSCODER_A"; | |
1872 | case POWER_DOMAIN_TRANSCODER_B: | |
1873 | return "TRANSCODER_B"; | |
1874 | case POWER_DOMAIN_TRANSCODER_C: | |
1875 | return "TRANSCODER_C"; | |
1876 | case POWER_DOMAIN_TRANSCODER_EDP: | |
1877 | return "TRANSCODER_EDP"; | |
1878 | case POWER_DOMAIN_VGA: | |
1879 | return "VGA"; | |
1880 | case POWER_DOMAIN_AUDIO: | |
1881 | return "AUDIO"; | |
1882 | case POWER_DOMAIN_INIT: | |
1883 | return "INIT"; | |
1884 | default: | |
1885 | WARN_ON(1); | |
1886 | return "?"; | |
1887 | } | |
1888 | } | |
1889 | ||
1890 | static int i915_power_domain_info(struct seq_file *m, void *unused) | |
1891 | { | |
1892 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
1893 | struct drm_device *dev = node->minor->dev; | |
1894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1895 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1896 | int i; | |
1897 | ||
1898 | mutex_lock(&power_domains->lock); | |
1899 | ||
1900 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
1901 | for (i = 0; i < power_domains->power_well_count; i++) { | |
1902 | struct i915_power_well *power_well; | |
1903 | enum intel_display_power_domain power_domain; | |
1904 | ||
1905 | power_well = &power_domains->power_wells[i]; | |
1906 | seq_printf(m, "%-25s %d\n", power_well->name, | |
1907 | power_well->count); | |
1908 | ||
1909 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
1910 | power_domain++) { | |
1911 | if (!(BIT(power_domain) & power_well->domains)) | |
1912 | continue; | |
1913 | ||
1914 | seq_printf(m, " %-23s %d\n", | |
1915 | power_domain_str(power_domain), | |
1916 | power_domains->domain_use_count[power_domain]); | |
1917 | } | |
1918 | } | |
1919 | ||
1920 | mutex_unlock(&power_domains->lock); | |
1921 | ||
1922 | return 0; | |
1923 | } | |
1924 | ||
07144428 DL |
1925 | struct pipe_crc_info { |
1926 | const char *name; | |
1927 | struct drm_device *dev; | |
1928 | enum pipe pipe; | |
1929 | }; | |
1930 | ||
1931 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) | |
1932 | { | |
be5c7a90 DL |
1933 | struct pipe_crc_info *info = inode->i_private; |
1934 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
1935 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
1936 | ||
7eb1c496 DV |
1937 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
1938 | return -ENODEV; | |
1939 | ||
d538bbdf DL |
1940 | spin_lock_irq(&pipe_crc->lock); |
1941 | ||
1942 | if (pipe_crc->opened) { | |
1943 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
1944 | return -EBUSY; /* already open */ |
1945 | } | |
1946 | ||
d538bbdf | 1947 | pipe_crc->opened = true; |
07144428 DL |
1948 | filep->private_data = inode->i_private; |
1949 | ||
d538bbdf DL |
1950 | spin_unlock_irq(&pipe_crc->lock); |
1951 | ||
07144428 DL |
1952 | return 0; |
1953 | } | |
1954 | ||
1955 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
1956 | { | |
be5c7a90 DL |
1957 | struct pipe_crc_info *info = inode->i_private; |
1958 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
1959 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
1960 | ||
d538bbdf DL |
1961 | spin_lock_irq(&pipe_crc->lock); |
1962 | pipe_crc->opened = false; | |
1963 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 1964 | |
07144428 DL |
1965 | return 0; |
1966 | } | |
1967 | ||
1968 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
1969 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
1970 | /* account for \'0' */ | |
1971 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
1972 | ||
1973 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 1974 | { |
d538bbdf DL |
1975 | assert_spin_locked(&pipe_crc->lock); |
1976 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
1977 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
1978 | } |
1979 | ||
1980 | static ssize_t | |
1981 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
1982 | loff_t *pos) | |
1983 | { | |
1984 | struct pipe_crc_info *info = filep->private_data; | |
1985 | struct drm_device *dev = info->dev; | |
1986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1987 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
1988 | char buf[PIPE_CRC_BUFFER_LEN]; | |
1989 | int head, tail, n_entries, n; | |
1990 | ssize_t bytes_read; | |
1991 | ||
1992 | /* | |
1993 | * Don't allow user space to provide buffers not big enough to hold | |
1994 | * a line of data. | |
1995 | */ | |
1996 | if (count < PIPE_CRC_LINE_LEN) | |
1997 | return -EINVAL; | |
1998 | ||
1999 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 2000 | return 0; |
07144428 DL |
2001 | |
2002 | /* nothing to read */ | |
d538bbdf | 2003 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 2004 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
2005 | int ret; |
2006 | ||
2007 | if (filep->f_flags & O_NONBLOCK) { | |
2008 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 2009 | return -EAGAIN; |
d538bbdf | 2010 | } |
07144428 | 2011 | |
d538bbdf DL |
2012 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
2013 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
2014 | if (ret) { | |
2015 | spin_unlock_irq(&pipe_crc->lock); | |
2016 | return ret; | |
2017 | } | |
8bf1e9f1 SH |
2018 | } |
2019 | ||
07144428 | 2020 | /* We now have one or more entries to read */ |
d538bbdf DL |
2021 | head = pipe_crc->head; |
2022 | tail = pipe_crc->tail; | |
07144428 DL |
2023 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
2024 | count / PIPE_CRC_LINE_LEN); | |
d538bbdf DL |
2025 | spin_unlock_irq(&pipe_crc->lock); |
2026 | ||
07144428 DL |
2027 | bytes_read = 0; |
2028 | n = 0; | |
2029 | do { | |
b2c88f5b | 2030 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
07144428 | 2031 | int ret; |
8bf1e9f1 | 2032 | |
07144428 DL |
2033 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
2034 | "%8u %8x %8x %8x %8x %8x\n", | |
2035 | entry->frame, entry->crc[0], | |
2036 | entry->crc[1], entry->crc[2], | |
2037 | entry->crc[3], entry->crc[4]); | |
2038 | ||
2039 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, | |
2040 | buf, PIPE_CRC_LINE_LEN); | |
2041 | if (ret == PIPE_CRC_LINE_LEN) | |
2042 | return -EFAULT; | |
b2c88f5b DL |
2043 | |
2044 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
2045 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
07144428 DL |
2046 | n++; |
2047 | } while (--n_entries); | |
8bf1e9f1 | 2048 | |
d538bbdf DL |
2049 | spin_lock_irq(&pipe_crc->lock); |
2050 | pipe_crc->tail = tail; | |
2051 | spin_unlock_irq(&pipe_crc->lock); | |
2052 | ||
07144428 DL |
2053 | return bytes_read; |
2054 | } | |
2055 | ||
2056 | static const struct file_operations i915_pipe_crc_fops = { | |
2057 | .owner = THIS_MODULE, | |
2058 | .open = i915_pipe_crc_open, | |
2059 | .read = i915_pipe_crc_read, | |
2060 | .release = i915_pipe_crc_release, | |
2061 | }; | |
2062 | ||
2063 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
2064 | { | |
2065 | .name = "i915_pipe_A_crc", | |
2066 | .pipe = PIPE_A, | |
2067 | }, | |
2068 | { | |
2069 | .name = "i915_pipe_B_crc", | |
2070 | .pipe = PIPE_B, | |
2071 | }, | |
2072 | { | |
2073 | .name = "i915_pipe_C_crc", | |
2074 | .pipe = PIPE_C, | |
2075 | }, | |
2076 | }; | |
2077 | ||
2078 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
2079 | enum pipe pipe) | |
2080 | { | |
2081 | struct drm_device *dev = minor->dev; | |
2082 | struct dentry *ent; | |
2083 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
2084 | ||
2085 | info->dev = dev; | |
2086 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
2087 | &i915_pipe_crc_fops); | |
2088 | if (IS_ERR(ent)) | |
2089 | return PTR_ERR(ent); | |
2090 | ||
2091 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
2092 | } |
2093 | ||
e8dfcf78 | 2094 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
2095 | "none", |
2096 | "plane1", | |
2097 | "plane2", | |
2098 | "pf", | |
5b3a856b | 2099 | "pipe", |
3d099a05 DV |
2100 | "TV", |
2101 | "DP-B", | |
2102 | "DP-C", | |
2103 | "DP-D", | |
46a19188 | 2104 | "auto", |
926321d5 DV |
2105 | }; |
2106 | ||
2107 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
2108 | { | |
2109 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
2110 | return pipe_crc_sources[source]; | |
2111 | } | |
2112 | ||
bd9db02f | 2113 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
2114 | { |
2115 | struct drm_device *dev = m->private; | |
2116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2117 | int i; | |
2118 | ||
2119 | for (i = 0; i < I915_MAX_PIPES; i++) | |
2120 | seq_printf(m, "%c %s\n", pipe_name(i), | |
2121 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
2122 | ||
2123 | return 0; | |
2124 | } | |
2125 | ||
bd9db02f | 2126 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
2127 | { |
2128 | struct drm_device *dev = inode->i_private; | |
2129 | ||
bd9db02f | 2130 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
2131 | } |
2132 | ||
46a19188 | 2133 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
2134 | uint32_t *val) |
2135 | { | |
46a19188 DV |
2136 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2137 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2138 | ||
2139 | switch (*source) { | |
52f843f6 DV |
2140 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2141 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
2142 | break; | |
2143 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2144 | *val = 0; | |
2145 | break; | |
2146 | default: | |
2147 | return -EINVAL; | |
2148 | } | |
2149 | ||
2150 | return 0; | |
2151 | } | |
2152 | ||
46a19188 DV |
2153 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
2154 | enum intel_pipe_crc_source *source) | |
2155 | { | |
2156 | struct intel_encoder *encoder; | |
2157 | struct intel_crtc *crtc; | |
26756809 | 2158 | struct intel_digital_port *dig_port; |
46a19188 DV |
2159 | int ret = 0; |
2160 | ||
2161 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2162 | ||
2163 | mutex_lock(&dev->mode_config.mutex); | |
2164 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
2165 | base.head) { | |
2166 | if (!encoder->base.crtc) | |
2167 | continue; | |
2168 | ||
2169 | crtc = to_intel_crtc(encoder->base.crtc); | |
2170 | ||
2171 | if (crtc->pipe != pipe) | |
2172 | continue; | |
2173 | ||
2174 | switch (encoder->type) { | |
2175 | case INTEL_OUTPUT_TVOUT: | |
2176 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
2177 | break; | |
2178 | case INTEL_OUTPUT_DISPLAYPORT: | |
2179 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
2180 | dig_port = enc_to_dig_port(&encoder->base); |
2181 | switch (dig_port->port) { | |
2182 | case PORT_B: | |
2183 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
2184 | break; | |
2185 | case PORT_C: | |
2186 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
2187 | break; | |
2188 | case PORT_D: | |
2189 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
2190 | break; | |
2191 | default: | |
2192 | WARN(1, "nonexisting DP port %c\n", | |
2193 | port_name(dig_port->port)); | |
2194 | break; | |
2195 | } | |
46a19188 DV |
2196 | break; |
2197 | } | |
2198 | } | |
2199 | mutex_unlock(&dev->mode_config.mutex); | |
2200 | ||
2201 | return ret; | |
2202 | } | |
2203 | ||
2204 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
2205 | enum pipe pipe, | |
2206 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
2207 | uint32_t *val) |
2208 | { | |
8d2f24ca DV |
2209 | struct drm_i915_private *dev_priv = dev->dev_private; |
2210 | bool need_stable_symbols = false; | |
2211 | ||
46a19188 DV |
2212 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2213 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2214 | if (ret) | |
2215 | return ret; | |
2216 | } | |
2217 | ||
2218 | switch (*source) { | |
7ac0129b DV |
2219 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2220 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
2221 | break; | |
2222 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2223 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 2224 | need_stable_symbols = true; |
7ac0129b DV |
2225 | break; |
2226 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2227 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 2228 | need_stable_symbols = true; |
7ac0129b DV |
2229 | break; |
2230 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2231 | *val = 0; | |
2232 | break; | |
2233 | default: | |
2234 | return -EINVAL; | |
2235 | } | |
2236 | ||
8d2f24ca DV |
2237 | /* |
2238 | * When the pipe CRC tap point is after the transcoders we need | |
2239 | * to tweak symbol-level features to produce a deterministic series of | |
2240 | * symbols for a given frame. We need to reset those features only once | |
2241 | * a frame (instead of every nth symbol): | |
2242 | * - DC-balance: used to ensure a better clock recovery from the data | |
2243 | * link (SDVO) | |
2244 | * - DisplayPort scrambling: used for EMI reduction | |
2245 | */ | |
2246 | if (need_stable_symbols) { | |
2247 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2248 | ||
2249 | WARN_ON(!IS_G4X(dev)); | |
2250 | ||
2251 | tmp |= DC_BALANCE_RESET_VLV; | |
2252 | if (pipe == PIPE_A) | |
2253 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2254 | else | |
2255 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2256 | ||
2257 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2258 | } | |
2259 | ||
7ac0129b DV |
2260 | return 0; |
2261 | } | |
2262 | ||
4b79ebf7 | 2263 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
2264 | enum pipe pipe, |
2265 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
2266 | uint32_t *val) |
2267 | { | |
84093603 DV |
2268 | struct drm_i915_private *dev_priv = dev->dev_private; |
2269 | bool need_stable_symbols = false; | |
2270 | ||
46a19188 DV |
2271 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2272 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2273 | if (ret) | |
2274 | return ret; | |
2275 | } | |
2276 | ||
2277 | switch (*source) { | |
4b79ebf7 DV |
2278 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2279 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
2280 | break; | |
2281 | case INTEL_PIPE_CRC_SOURCE_TV: | |
2282 | if (!SUPPORTS_TV(dev)) | |
2283 | return -EINVAL; | |
2284 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
2285 | break; | |
2286 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2287 | if (!IS_G4X(dev)) | |
2288 | return -EINVAL; | |
2289 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 2290 | need_stable_symbols = true; |
4b79ebf7 DV |
2291 | break; |
2292 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2293 | if (!IS_G4X(dev)) | |
2294 | return -EINVAL; | |
2295 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 2296 | need_stable_symbols = true; |
4b79ebf7 DV |
2297 | break; |
2298 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
2299 | if (!IS_G4X(dev)) | |
2300 | return -EINVAL; | |
2301 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 2302 | need_stable_symbols = true; |
4b79ebf7 DV |
2303 | break; |
2304 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2305 | *val = 0; | |
2306 | break; | |
2307 | default: | |
2308 | return -EINVAL; | |
2309 | } | |
2310 | ||
84093603 DV |
2311 | /* |
2312 | * When the pipe CRC tap point is after the transcoders we need | |
2313 | * to tweak symbol-level features to produce a deterministic series of | |
2314 | * symbols for a given frame. We need to reset those features only once | |
2315 | * a frame (instead of every nth symbol): | |
2316 | * - DC-balance: used to ensure a better clock recovery from the data | |
2317 | * link (SDVO) | |
2318 | * - DisplayPort scrambling: used for EMI reduction | |
2319 | */ | |
2320 | if (need_stable_symbols) { | |
2321 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2322 | ||
2323 | WARN_ON(!IS_G4X(dev)); | |
2324 | ||
2325 | I915_WRITE(PORT_DFT_I9XX, | |
2326 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
2327 | ||
2328 | if (pipe == PIPE_A) | |
2329 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2330 | else | |
2331 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2332 | ||
2333 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2334 | } | |
2335 | ||
4b79ebf7 DV |
2336 | return 0; |
2337 | } | |
2338 | ||
8d2f24ca DV |
2339 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
2340 | enum pipe pipe) | |
2341 | { | |
2342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2343 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2344 | ||
2345 | if (pipe == PIPE_A) | |
2346 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2347 | else | |
2348 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2349 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) | |
2350 | tmp &= ~DC_BALANCE_RESET_VLV; | |
2351 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2352 | ||
2353 | } | |
2354 | ||
84093603 DV |
2355 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
2356 | enum pipe pipe) | |
2357 | { | |
2358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2359 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2360 | ||
2361 | if (pipe == PIPE_A) | |
2362 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2363 | else | |
2364 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2365 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2366 | ||
2367 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
2368 | I915_WRITE(PORT_DFT_I9XX, | |
2369 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
2370 | } | |
2371 | } | |
2372 | ||
46a19188 | 2373 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2374 | uint32_t *val) |
2375 | { | |
46a19188 DV |
2376 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2377 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2378 | ||
2379 | switch (*source) { | |
5b3a856b DV |
2380 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2381 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
2382 | break; | |
2383 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2384 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
2385 | break; | |
5b3a856b DV |
2386 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2387 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
2388 | break; | |
3d099a05 | 2389 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2390 | *val = 0; |
2391 | break; | |
3d099a05 DV |
2392 | default: |
2393 | return -EINVAL; | |
5b3a856b DV |
2394 | } |
2395 | ||
2396 | return 0; | |
2397 | } | |
2398 | ||
46a19188 | 2399 | static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2400 | uint32_t *val) |
2401 | { | |
46a19188 DV |
2402 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2403 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
2404 | ||
2405 | switch (*source) { | |
5b3a856b DV |
2406 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2407 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
2408 | break; | |
2409 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2410 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
2411 | break; | |
2412 | case INTEL_PIPE_CRC_SOURCE_PF: | |
2413 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; | |
2414 | break; | |
3d099a05 | 2415 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2416 | *val = 0; |
2417 | break; | |
3d099a05 DV |
2418 | default: |
2419 | return -EINVAL; | |
5b3a856b DV |
2420 | } |
2421 | ||
2422 | return 0; | |
2423 | } | |
2424 | ||
926321d5 DV |
2425 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
2426 | enum intel_pipe_crc_source source) | |
2427 | { | |
2428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 2429 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
432f3342 | 2430 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 2431 | int ret; |
926321d5 | 2432 | |
cc3da175 DL |
2433 | if (pipe_crc->source == source) |
2434 | return 0; | |
2435 | ||
ae676fcd DL |
2436 | /* forbid changing the source without going back to 'none' */ |
2437 | if (pipe_crc->source && source) | |
2438 | return -EINVAL; | |
2439 | ||
52f843f6 | 2440 | if (IS_GEN2(dev)) |
46a19188 | 2441 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 2442 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 2443 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
7ac0129b | 2444 | else if (IS_VALLEYVIEW(dev)) |
46a19188 | 2445 | ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val); |
4b79ebf7 | 2446 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 2447 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 2448 | else |
46a19188 | 2449 | ret = ivb_pipe_crc_ctl_reg(&source, &val); |
5b3a856b DV |
2450 | |
2451 | if (ret != 0) | |
2452 | return ret; | |
2453 | ||
4b584369 DL |
2454 | /* none -> real source transition */ |
2455 | if (source) { | |
7cd6ccff DL |
2456 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
2457 | pipe_name(pipe), pipe_crc_source_name(source)); | |
2458 | ||
e5f75aca DL |
2459 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
2460 | INTEL_PIPE_CRC_ENTRIES_NR, | |
2461 | GFP_KERNEL); | |
2462 | if (!pipe_crc->entries) | |
2463 | return -ENOMEM; | |
2464 | ||
d538bbdf DL |
2465 | spin_lock_irq(&pipe_crc->lock); |
2466 | pipe_crc->head = 0; | |
2467 | pipe_crc->tail = 0; | |
2468 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
2469 | } |
2470 | ||
cc3da175 | 2471 | pipe_crc->source = source; |
926321d5 | 2472 | |
926321d5 DV |
2473 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
2474 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
2475 | ||
e5f75aca DL |
2476 | /* real source -> none transition */ |
2477 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf DL |
2478 | struct intel_pipe_crc_entry *entries; |
2479 | ||
7cd6ccff DL |
2480 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
2481 | pipe_name(pipe)); | |
2482 | ||
bcf17ab2 DV |
2483 | intel_wait_for_vblank(dev, pipe); |
2484 | ||
d538bbdf DL |
2485 | spin_lock_irq(&pipe_crc->lock); |
2486 | entries = pipe_crc->entries; | |
e5f75aca | 2487 | pipe_crc->entries = NULL; |
d538bbdf DL |
2488 | spin_unlock_irq(&pipe_crc->lock); |
2489 | ||
2490 | kfree(entries); | |
84093603 DV |
2491 | |
2492 | if (IS_G4X(dev)) | |
2493 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
8d2f24ca DV |
2494 | else if (IS_VALLEYVIEW(dev)) |
2495 | vlv_undo_pipe_scramble_reset(dev, pipe); | |
e5f75aca DL |
2496 | } |
2497 | ||
926321d5 DV |
2498 | return 0; |
2499 | } | |
2500 | ||
2501 | /* | |
2502 | * Parse pipe CRC command strings: | |
b94dec87 DL |
2503 | * command: wsp* object wsp+ name wsp+ source wsp* |
2504 | * object: 'pipe' | |
2505 | * name: (A | B | C) | |
926321d5 DV |
2506 | * source: (none | plane1 | plane2 | pf) |
2507 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
2508 | * | |
2509 | * eg.: | |
b94dec87 DL |
2510 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
2511 | * "pipe A none" -> Stop CRC | |
926321d5 | 2512 | */ |
bd9db02f | 2513 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
2514 | { |
2515 | int n_words = 0; | |
2516 | ||
2517 | while (*buf) { | |
2518 | char *end; | |
2519 | ||
2520 | /* skip leading white space */ | |
2521 | buf = skip_spaces(buf); | |
2522 | if (!*buf) | |
2523 | break; /* end of buffer */ | |
2524 | ||
2525 | /* find end of word */ | |
2526 | for (end = buf; *end && !isspace(*end); end++) | |
2527 | ; | |
2528 | ||
2529 | if (n_words == max_words) { | |
2530 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
2531 | max_words); | |
2532 | return -EINVAL; /* ran out of words[] before bytes */ | |
2533 | } | |
2534 | ||
2535 | if (*end) | |
2536 | *end++ = '\0'; | |
2537 | words[n_words++] = buf; | |
2538 | buf = end; | |
2539 | } | |
2540 | ||
2541 | return n_words; | |
2542 | } | |
2543 | ||
b94dec87 DL |
2544 | enum intel_pipe_crc_object { |
2545 | PIPE_CRC_OBJECT_PIPE, | |
2546 | }; | |
2547 | ||
e8dfcf78 | 2548 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
2549 | "pipe", |
2550 | }; | |
2551 | ||
2552 | static int | |
bd9db02f | 2553 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
2554 | { |
2555 | int i; | |
2556 | ||
2557 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
2558 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 2559 | *o = i; |
b94dec87 DL |
2560 | return 0; |
2561 | } | |
2562 | ||
2563 | return -EINVAL; | |
2564 | } | |
2565 | ||
bd9db02f | 2566 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
2567 | { |
2568 | const char name = buf[0]; | |
2569 | ||
2570 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
2571 | return -EINVAL; | |
2572 | ||
2573 | *pipe = name - 'A'; | |
2574 | ||
2575 | return 0; | |
2576 | } | |
2577 | ||
2578 | static int | |
bd9db02f | 2579 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
2580 | { |
2581 | int i; | |
2582 | ||
2583 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
2584 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 2585 | *s = i; |
926321d5 DV |
2586 | return 0; |
2587 | } | |
2588 | ||
2589 | return -EINVAL; | |
2590 | } | |
2591 | ||
bd9db02f | 2592 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 2593 | { |
b94dec87 | 2594 | #define N_WORDS 3 |
926321d5 | 2595 | int n_words; |
b94dec87 | 2596 | char *words[N_WORDS]; |
926321d5 | 2597 | enum pipe pipe; |
b94dec87 | 2598 | enum intel_pipe_crc_object object; |
926321d5 DV |
2599 | enum intel_pipe_crc_source source; |
2600 | ||
bd9db02f | 2601 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
2602 | if (n_words != N_WORDS) { |
2603 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
2604 | N_WORDS); | |
2605 | return -EINVAL; | |
2606 | } | |
2607 | ||
bd9db02f | 2608 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 2609 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
2610 | return -EINVAL; |
2611 | } | |
2612 | ||
bd9db02f | 2613 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 2614 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
2615 | return -EINVAL; |
2616 | } | |
2617 | ||
bd9db02f | 2618 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 2619 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
2620 | return -EINVAL; |
2621 | } | |
2622 | ||
2623 | return pipe_crc_set_source(dev, pipe, source); | |
2624 | } | |
2625 | ||
bd9db02f DL |
2626 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
2627 | size_t len, loff_t *offp) | |
926321d5 DV |
2628 | { |
2629 | struct seq_file *m = file->private_data; | |
2630 | struct drm_device *dev = m->private; | |
2631 | char *tmpbuf; | |
2632 | int ret; | |
2633 | ||
2634 | if (len == 0) | |
2635 | return 0; | |
2636 | ||
2637 | if (len > PAGE_SIZE - 1) { | |
2638 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
2639 | PAGE_SIZE); | |
2640 | return -E2BIG; | |
2641 | } | |
2642 | ||
2643 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
2644 | if (!tmpbuf) | |
2645 | return -ENOMEM; | |
2646 | ||
2647 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
2648 | ret = -EFAULT; | |
2649 | goto out; | |
2650 | } | |
2651 | tmpbuf[len] = '\0'; | |
2652 | ||
bd9db02f | 2653 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
2654 | |
2655 | out: | |
2656 | kfree(tmpbuf); | |
2657 | if (ret < 0) | |
2658 | return ret; | |
2659 | ||
2660 | *offp += len; | |
2661 | return len; | |
2662 | } | |
2663 | ||
bd9db02f | 2664 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 2665 | .owner = THIS_MODULE, |
bd9db02f | 2666 | .open = display_crc_ctl_open, |
926321d5 DV |
2667 | .read = seq_read, |
2668 | .llseek = seq_lseek, | |
2669 | .release = single_release, | |
bd9db02f | 2670 | .write = display_crc_ctl_write |
926321d5 DV |
2671 | }; |
2672 | ||
647416f9 KC |
2673 | static int |
2674 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 2675 | { |
647416f9 | 2676 | struct drm_device *dev = data; |
f3cd474b | 2677 | drm_i915_private_t *dev_priv = dev->dev_private; |
f3cd474b | 2678 | |
647416f9 | 2679 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 2680 | |
647416f9 | 2681 | return 0; |
f3cd474b CW |
2682 | } |
2683 | ||
647416f9 KC |
2684 | static int |
2685 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 2686 | { |
647416f9 | 2687 | struct drm_device *dev = data; |
f3cd474b | 2688 | |
647416f9 | 2689 | DRM_INFO("Manually setting wedged to %llu\n", val); |
527f9e90 | 2690 | i915_handle_error(dev, val); |
f3cd474b | 2691 | |
647416f9 | 2692 | return 0; |
f3cd474b CW |
2693 | } |
2694 | ||
647416f9 KC |
2695 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
2696 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 2697 | "%llu\n"); |
f3cd474b | 2698 | |
647416f9 KC |
2699 | static int |
2700 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 2701 | { |
647416f9 | 2702 | struct drm_device *dev = data; |
e5eb3d63 | 2703 | drm_i915_private_t *dev_priv = dev->dev_private; |
e5eb3d63 | 2704 | |
647416f9 | 2705 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 2706 | |
647416f9 | 2707 | return 0; |
e5eb3d63 DV |
2708 | } |
2709 | ||
647416f9 KC |
2710 | static int |
2711 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 2712 | { |
647416f9 | 2713 | struct drm_device *dev = data; |
e5eb3d63 | 2714 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2715 | int ret; |
e5eb3d63 | 2716 | |
647416f9 | 2717 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 2718 | |
22bcfc6a DV |
2719 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2720 | if (ret) | |
2721 | return ret; | |
2722 | ||
99584db3 | 2723 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
2724 | mutex_unlock(&dev->struct_mutex); |
2725 | ||
647416f9 | 2726 | return 0; |
e5eb3d63 DV |
2727 | } |
2728 | ||
647416f9 KC |
2729 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
2730 | i915_ring_stop_get, i915_ring_stop_set, | |
2731 | "0x%08llx\n"); | |
d5442303 | 2732 | |
094f9a54 CW |
2733 | static int |
2734 | i915_ring_missed_irq_get(void *data, u64 *val) | |
2735 | { | |
2736 | struct drm_device *dev = data; | |
2737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2738 | ||
2739 | *val = dev_priv->gpu_error.missed_irq_rings; | |
2740 | return 0; | |
2741 | } | |
2742 | ||
2743 | static int | |
2744 | i915_ring_missed_irq_set(void *data, u64 val) | |
2745 | { | |
2746 | struct drm_device *dev = data; | |
2747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2748 | int ret; | |
2749 | ||
2750 | /* Lock against concurrent debugfs callers */ | |
2751 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2752 | if (ret) | |
2753 | return ret; | |
2754 | dev_priv->gpu_error.missed_irq_rings = val; | |
2755 | mutex_unlock(&dev->struct_mutex); | |
2756 | ||
2757 | return 0; | |
2758 | } | |
2759 | ||
2760 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
2761 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
2762 | "0x%08llx\n"); | |
2763 | ||
2764 | static int | |
2765 | i915_ring_test_irq_get(void *data, u64 *val) | |
2766 | { | |
2767 | struct drm_device *dev = data; | |
2768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2769 | ||
2770 | *val = dev_priv->gpu_error.test_irq_rings; | |
2771 | ||
2772 | return 0; | |
2773 | } | |
2774 | ||
2775 | static int | |
2776 | i915_ring_test_irq_set(void *data, u64 val) | |
2777 | { | |
2778 | struct drm_device *dev = data; | |
2779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2780 | int ret; | |
2781 | ||
2782 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
2783 | ||
2784 | /* Lock against concurrent debugfs callers */ | |
2785 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2786 | if (ret) | |
2787 | return ret; | |
2788 | ||
2789 | dev_priv->gpu_error.test_irq_rings = val; | |
2790 | mutex_unlock(&dev->struct_mutex); | |
2791 | ||
2792 | return 0; | |
2793 | } | |
2794 | ||
2795 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
2796 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
2797 | "0x%08llx\n"); | |
2798 | ||
dd624afd CW |
2799 | #define DROP_UNBOUND 0x1 |
2800 | #define DROP_BOUND 0x2 | |
2801 | #define DROP_RETIRE 0x4 | |
2802 | #define DROP_ACTIVE 0x8 | |
2803 | #define DROP_ALL (DROP_UNBOUND | \ | |
2804 | DROP_BOUND | \ | |
2805 | DROP_RETIRE | \ | |
2806 | DROP_ACTIVE) | |
647416f9 KC |
2807 | static int |
2808 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 2809 | { |
647416f9 | 2810 | *val = DROP_ALL; |
dd624afd | 2811 | |
647416f9 | 2812 | return 0; |
dd624afd CW |
2813 | } |
2814 | ||
647416f9 KC |
2815 | static int |
2816 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 2817 | { |
647416f9 | 2818 | struct drm_device *dev = data; |
dd624afd CW |
2819 | struct drm_i915_private *dev_priv = dev->dev_private; |
2820 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
2821 | struct i915_address_space *vm; |
2822 | struct i915_vma *vma, *x; | |
647416f9 | 2823 | int ret; |
dd624afd | 2824 | |
2f9fe5ff | 2825 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
2826 | |
2827 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
2828 | * on ioctls on -EAGAIN. */ | |
2829 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2830 | if (ret) | |
2831 | return ret; | |
2832 | ||
2833 | if (val & DROP_ACTIVE) { | |
2834 | ret = i915_gpu_idle(dev); | |
2835 | if (ret) | |
2836 | goto unlock; | |
2837 | } | |
2838 | ||
2839 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
2840 | i915_gem_retire_requests(dev); | |
2841 | ||
2842 | if (val & DROP_BOUND) { | |
ca191b13 BW |
2843 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2844 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
2845 | mm_list) { | |
2846 | if (vma->obj->pin_count) | |
2847 | continue; | |
2848 | ||
2849 | ret = i915_vma_unbind(vma); | |
2850 | if (ret) | |
2851 | goto unlock; | |
2852 | } | |
31a46c9c | 2853 | } |
dd624afd CW |
2854 | } |
2855 | ||
2856 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
2857 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
2858 | global_list) | |
dd624afd CW |
2859 | if (obj->pages_pin_count == 0) { |
2860 | ret = i915_gem_object_put_pages(obj); | |
2861 | if (ret) | |
2862 | goto unlock; | |
2863 | } | |
2864 | } | |
2865 | ||
2866 | unlock: | |
2867 | mutex_unlock(&dev->struct_mutex); | |
2868 | ||
647416f9 | 2869 | return ret; |
dd624afd CW |
2870 | } |
2871 | ||
647416f9 KC |
2872 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
2873 | i915_drop_caches_get, i915_drop_caches_set, | |
2874 | "0x%08llx\n"); | |
dd624afd | 2875 | |
647416f9 KC |
2876 | static int |
2877 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 2878 | { |
647416f9 | 2879 | struct drm_device *dev = data; |
358733e9 | 2880 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2881 | int ret; |
004777cb DV |
2882 | |
2883 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2884 | return -ENODEV; | |
2885 | ||
5c9669ce TR |
2886 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2887 | ||
4fc688ce | 2888 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2889 | if (ret) |
2890 | return ret; | |
358733e9 | 2891 | |
0a073b84 | 2892 | if (IS_VALLEYVIEW(dev)) |
2ec3815f | 2893 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay); |
0a073b84 JB |
2894 | else |
2895 | *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2896 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2897 | |
647416f9 | 2898 | return 0; |
358733e9 JB |
2899 | } |
2900 | ||
647416f9 KC |
2901 | static int |
2902 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 2903 | { |
647416f9 | 2904 | struct drm_device *dev = data; |
358733e9 | 2905 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2906 | int ret; |
004777cb DV |
2907 | |
2908 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2909 | return -ENODEV; | |
358733e9 | 2910 | |
5c9669ce TR |
2911 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2912 | ||
647416f9 | 2913 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 2914 | |
4fc688ce | 2915 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2916 | if (ret) |
2917 | return ret; | |
2918 | ||
358733e9 JB |
2919 | /* |
2920 | * Turbo will still be enabled, but won't go above the set value. | |
2921 | */ | |
0a073b84 | 2922 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 2923 | val = vlv_freq_opcode(dev_priv, val); |
0a073b84 | 2924 | dev_priv->rps.max_delay = val; |
6917c7b9 | 2925 | valleyview_set_rps(dev, val); |
0a073b84 JB |
2926 | } else { |
2927 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2928 | dev_priv->rps.max_delay = val; | |
2929 | gen6_set_rps(dev, val); | |
2930 | } | |
2931 | ||
4fc688ce | 2932 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 2933 | |
647416f9 | 2934 | return 0; |
358733e9 JB |
2935 | } |
2936 | ||
647416f9 KC |
2937 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
2938 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 2939 | "%llu\n"); |
358733e9 | 2940 | |
647416f9 KC |
2941 | static int |
2942 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 2943 | { |
647416f9 | 2944 | struct drm_device *dev = data; |
1523c310 | 2945 | drm_i915_private_t *dev_priv = dev->dev_private; |
647416f9 | 2946 | int ret; |
004777cb DV |
2947 | |
2948 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2949 | return -ENODEV; | |
2950 | ||
5c9669ce TR |
2951 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2952 | ||
4fc688ce | 2953 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2954 | if (ret) |
2955 | return ret; | |
1523c310 | 2956 | |
0a073b84 | 2957 | if (IS_VALLEYVIEW(dev)) |
2ec3815f | 2958 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay); |
0a073b84 JB |
2959 | else |
2960 | *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; | |
4fc688ce | 2961 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2962 | |
647416f9 | 2963 | return 0; |
1523c310 JB |
2964 | } |
2965 | ||
647416f9 KC |
2966 | static int |
2967 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 2968 | { |
647416f9 | 2969 | struct drm_device *dev = data; |
1523c310 | 2970 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 2971 | int ret; |
004777cb DV |
2972 | |
2973 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) | |
2974 | return -ENODEV; | |
1523c310 | 2975 | |
5c9669ce TR |
2976 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
2977 | ||
647416f9 | 2978 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 2979 | |
4fc688ce | 2980 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
2981 | if (ret) |
2982 | return ret; | |
2983 | ||
1523c310 JB |
2984 | /* |
2985 | * Turbo will still be enabled, but won't go below the set value. | |
2986 | */ | |
0a073b84 | 2987 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 2988 | val = vlv_freq_opcode(dev_priv, val); |
0a073b84 JB |
2989 | dev_priv->rps.min_delay = val; |
2990 | valleyview_set_rps(dev, val); | |
2991 | } else { | |
2992 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
2993 | dev_priv->rps.min_delay = val; | |
2994 | gen6_set_rps(dev, val); | |
2995 | } | |
4fc688ce | 2996 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 2997 | |
647416f9 | 2998 | return 0; |
1523c310 JB |
2999 | } |
3000 | ||
647416f9 KC |
3001 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
3002 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 3003 | "%llu\n"); |
1523c310 | 3004 | |
647416f9 KC |
3005 | static int |
3006 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 3007 | { |
647416f9 | 3008 | struct drm_device *dev = data; |
07b7ddd9 | 3009 | drm_i915_private_t *dev_priv = dev->dev_private; |
07b7ddd9 | 3010 | u32 snpcr; |
647416f9 | 3011 | int ret; |
07b7ddd9 | 3012 | |
004777cb DV |
3013 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3014 | return -ENODEV; | |
3015 | ||
22bcfc6a DV |
3016 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3017 | if (ret) | |
3018 | return ret; | |
3019 | ||
07b7ddd9 JB |
3020 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
3021 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
3022 | ||
647416f9 | 3023 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 3024 | |
647416f9 | 3025 | return 0; |
07b7ddd9 JB |
3026 | } |
3027 | ||
647416f9 KC |
3028 | static int |
3029 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 3030 | { |
647416f9 | 3031 | struct drm_device *dev = data; |
07b7ddd9 | 3032 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 3033 | u32 snpcr; |
07b7ddd9 | 3034 | |
004777cb DV |
3035 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3036 | return -ENODEV; | |
3037 | ||
647416f9 | 3038 | if (val > 3) |
07b7ddd9 JB |
3039 | return -EINVAL; |
3040 | ||
647416f9 | 3041 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
3042 | |
3043 | /* Update the cache sharing policy here as well */ | |
3044 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
3045 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
3046 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
3047 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3048 | ||
647416f9 | 3049 | return 0; |
07b7ddd9 JB |
3050 | } |
3051 | ||
647416f9 KC |
3052 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
3053 | i915_cache_sharing_get, i915_cache_sharing_set, | |
3054 | "%llu\n"); | |
07b7ddd9 | 3055 | |
6d794d42 BW |
3056 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
3057 | { | |
3058 | struct drm_device *dev = inode->i_private; | |
3059 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 3060 | |
075edca4 | 3061 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3062 | return 0; |
3063 | ||
c8d9a590 | 3064 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3065 | |
3066 | return 0; | |
3067 | } | |
3068 | ||
c43b5634 | 3069 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
3070 | { |
3071 | struct drm_device *dev = inode->i_private; | |
3072 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3073 | ||
075edca4 | 3074 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3075 | return 0; |
3076 | ||
c8d9a590 | 3077 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3078 | |
3079 | return 0; | |
3080 | } | |
3081 | ||
3082 | static const struct file_operations i915_forcewake_fops = { | |
3083 | .owner = THIS_MODULE, | |
3084 | .open = i915_forcewake_open, | |
3085 | .release = i915_forcewake_release, | |
3086 | }; | |
3087 | ||
3088 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
3089 | { | |
3090 | struct drm_device *dev = minor->dev; | |
3091 | struct dentry *ent; | |
3092 | ||
3093 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 3094 | S_IRUSR, |
6d794d42 BW |
3095 | root, dev, |
3096 | &i915_forcewake_fops); | |
3097 | if (IS_ERR(ent)) | |
3098 | return PTR_ERR(ent); | |
3099 | ||
8eb57294 | 3100 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
3101 | } |
3102 | ||
6a9c308d DV |
3103 | static int i915_debugfs_create(struct dentry *root, |
3104 | struct drm_minor *minor, | |
3105 | const char *name, | |
3106 | const struct file_operations *fops) | |
07b7ddd9 JB |
3107 | { |
3108 | struct drm_device *dev = minor->dev; | |
3109 | struct dentry *ent; | |
3110 | ||
6a9c308d | 3111 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
3112 | S_IRUGO | S_IWUSR, |
3113 | root, dev, | |
6a9c308d | 3114 | fops); |
07b7ddd9 JB |
3115 | if (IS_ERR(ent)) |
3116 | return PTR_ERR(ent); | |
3117 | ||
6a9c308d | 3118 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
3119 | } |
3120 | ||
06c5bf8c | 3121 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 3122 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 3123 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 3124 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 3125 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 3126 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 3127 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 3128 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 3129 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
3130 | {"i915_gem_request", i915_gem_request_info, 0}, |
3131 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 3132 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 3133 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
3134 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
3135 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
3136 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 3137 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 JB |
3138 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
3139 | {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, | |
3140 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, | |
3141 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
3142 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 3143 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 3144 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 3145 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 3146 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 3147 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 3148 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 3149 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 3150 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 3151 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 3152 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 3153 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 3154 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
57f350b6 | 3155 | {"i915_dpio", i915_dpio_info, 0}, |
63573eb7 | 3156 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 3157 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
ec013e7f | 3158 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 3159 | {"i915_pc8_status", i915_pc8_status, 0}, |
1da51581 | 3160 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
2017263e | 3161 | }; |
27c202ad | 3162 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 3163 | |
06c5bf8c | 3164 | static const struct i915_debugfs_files { |
34b9674c DV |
3165 | const char *name; |
3166 | const struct file_operations *fops; | |
3167 | } i915_debugfs_files[] = { | |
3168 | {"i915_wedged", &i915_wedged_fops}, | |
3169 | {"i915_max_freq", &i915_max_freq_fops}, | |
3170 | {"i915_min_freq", &i915_min_freq_fops}, | |
3171 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
3172 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
3173 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
3174 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
3175 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
3176 | {"i915_error_state", &i915_error_state_fops}, | |
3177 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 3178 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
34b9674c DV |
3179 | }; |
3180 | ||
07144428 DL |
3181 | void intel_display_crc_init(struct drm_device *dev) |
3182 | { | |
3183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 3184 | enum pipe pipe; |
07144428 | 3185 | |
b378360e DV |
3186 | for_each_pipe(pipe) { |
3187 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
07144428 | 3188 | |
d538bbdf DL |
3189 | pipe_crc->opened = false; |
3190 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
3191 | init_waitqueue_head(&pipe_crc->wq); |
3192 | } | |
3193 | } | |
3194 | ||
27c202ad | 3195 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 3196 | { |
34b9674c | 3197 | int ret, i; |
f3cd474b | 3198 | |
6d794d42 | 3199 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
3200 | if (ret) |
3201 | return ret; | |
6a9c308d | 3202 | |
07144428 DL |
3203 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
3204 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
3205 | if (ret) | |
3206 | return ret; | |
3207 | } | |
3208 | ||
34b9674c DV |
3209 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3210 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
3211 | i915_debugfs_files[i].name, | |
3212 | i915_debugfs_files[i].fops); | |
3213 | if (ret) | |
3214 | return ret; | |
3215 | } | |
40633219 | 3216 | |
27c202ad BG |
3217 | return drm_debugfs_create_files(i915_debugfs_list, |
3218 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
3219 | minor->debugfs_root, minor); |
3220 | } | |
3221 | ||
27c202ad | 3222 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 3223 | { |
34b9674c DV |
3224 | int i; |
3225 | ||
27c202ad BG |
3226 | drm_debugfs_remove_files(i915_debugfs_list, |
3227 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 3228 | |
6d794d42 BW |
3229 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
3230 | 1, minor); | |
07144428 | 3231 | |
e309a997 | 3232 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
3233 | struct drm_info_list *info_list = |
3234 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
3235 | ||
3236 | drm_debugfs_remove_files(info_list, 1, minor); | |
3237 | } | |
3238 | ||
34b9674c DV |
3239 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3240 | struct drm_info_list *info_list = | |
3241 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
3242 | ||
3243 | drm_debugfs_remove_files(info_list, 1, minor); | |
3244 | } | |
2017263e BG |
3245 | } |
3246 | ||
3247 | #endif /* CONFIG_DEBUG_FS */ |