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drm/i915: i915_sysfs.c cleanup
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
497666d8
DL		 43/* As the drm_debugfs_init() routines are called before dev->dev_private is
44 * allocated we need to hook into the minor for release. */
45static int
46drm_add_fake_info_node(struct drm_minor *minor,
47 struct dentry *ent,
48 const void *key)
49{
50 struct drm_info_node *node;
51
52 node = kmalloc(sizeof(*node), GFP_KERNEL);
53 if (node == NULL) {
54 debugfs_remove(ent);
55 return -ENOMEM;
56 }
57
58 node->minor = minor;
59 node->dent = ent;
60 node->info_ent = (void *) key;
61
62 mutex_lock(&minor->debugfs_lock);
63 list_add(&node->list, &minor->debugfs_list);
64 mutex_unlock(&minor->debugfs_lock);
65
66 return 0;
67}
68
70d39fe4
CW		 69static int i915_capabilities(struct seq_file *m, void *data)
70{
9f25d007 71 struct drm_info_node *node = m->private;
70d39fe4
CW		 72 struct drm_device *dev = node->minor->dev;
73 const struct intel_device_info *info = INTEL_INFO(dev);
74
75 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 76 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 77#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
78#define SEP_SEMICOLON ;
79 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
80#undef PRINT_FLAG
81#undef SEP_SEMICOLON
70d39fe4
CW		 82
83 return 0;
84}
2017263e 85
a7363de7 86static char get_active_flag(struct drm_i915_gem_object *obj)
a6172a80 87{
573adb39 88 return i915_gem_object_is_active(obj) ? '*' : ' ';
a6172a80
CW		 89}
90
a7363de7 91static char get_pin_flag(struct drm_i915_gem_object *obj)
be12a86b
TU		 92{
93 return obj->pin_display ? 'p' : ' ';
94}
95
a7363de7 96static char get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 97{
3e510a8e 98 switch (i915_gem_object_get_tiling(obj)) {
0206e353 99 default:
be12a86b
TU		 100 case I915_TILING_NONE: return ' ';
101 case I915_TILING_X: return 'X';
102 case I915_TILING_Y: return 'Y';
0206e353 103 }
a6172a80
CW		 104}
105
a7363de7 106static char get_global_flag(struct drm_i915_gem_object *obj)
be12a86b 107{
058d88c4 108 return i915_gem_object_to_ggtt(obj, NULL) ? 'g' : ' ';
be12a86b
TU		 109}
110
a7363de7 111static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
1d693bcc 112{
be12a86b 113 return obj->mapping ? 'M' : ' ';
1d693bcc
BW		 114}
115
ca1543be
TU		 116static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
117{
118 u64 size = 0;
119 struct i915_vma *vma;
120
1c7f4bca 121 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3272db53 122 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
ca1543be
TU		 123 size += vma->node.size;
124 }
125
126 return size;
127}
128
37811fcc
CW		 129static void
130describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
131{
b4716185 132 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
e2f80391 133 struct intel_engine_cs *engine;
1d693bcc 134 struct i915_vma *vma;
faf5bf0a 135 unsigned int frontbuffer_bits;
d7f46fc4 136 int pin_count = 0;
c3232b18 137 enum intel_engine_id id;
d7f46fc4 138
188c1ab7
CW		 139 lockdep_assert_held(&obj->base.dev->struct_mutex);
140
be12a86b 141 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
37811fcc 142 &obj->base,
be12a86b 143 get_active_flag(obj),
37811fcc
CW		 144 get_pin_flag(obj),
145 get_tiling_flag(obj),
1d693bcc 146 get_global_flag(obj),
be12a86b 147 get_pin_mapped_flag(obj),
a05a5862 148 obj->base.size / 1024,
37811fcc 149 obj->base.read_domains,
b4716185 150 obj->base.write_domain);
c3232b18 151 for_each_engine_id(engine, dev_priv, id)
b4716185 152 seq_printf(m, "%x ",
d72d908b
CW		 153 i915_gem_active_get_seqno(&obj->last_read[id],
154 &obj->base.dev->struct_mutex));
49ef5294 155 seq_printf(m, "] %x %s%s%s",
d72d908b
CW		 156 i915_gem_active_get_seqno(&obj->last_write,
157 &obj->base.dev->struct_mutex),
0a4cd7c8 158 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 159 obj->dirty ? " dirty" : "",
160 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
161 if (obj->base.name)
162 seq_printf(m, " (name: %d)", obj->base.name);
1c7f4bca 163 list_for_each_entry(vma, &obj->vma_list, obj_link) {
20dfbde4 164 if (i915_vma_is_pinned(vma))
d7f46fc4 165 pin_count++;
ba0635ff
DC		 166 }
167 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 168 if (obj->pin_display)
169 seq_printf(m, " (display)");
1c7f4bca 170 list_for_each_entry(vma, &obj->vma_list, obj_link) {
15717de2
CW		 171 if (!drm_mm_node_allocated(&vma->node))
172 continue;
173
8d2fdc3f 174 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
3272db53 175 i915_vma_is_ggtt(vma) ? "g" : "pp",
8d2fdc3f 176 vma->node.start, vma->node.size);
3272db53 177 if (i915_vma_is_ggtt(vma))
596c5923 178 seq_printf(m, ", type: %u", vma->ggtt_view.type);
49ef5294
CW		 179 if (vma->fence)
180 seq_printf(m, " , fence: %d%s",
181 vma->fence->id,
182 i915_gem_active_isset(&vma->last_fence) ? "*" : "");
596c5923 183 seq_puts(m, ")");
1d693bcc 184 }
c1ad11fc 185 if (obj->stolen)
440fd528 186 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 187 if (obj->pin_display || obj->fault_mappable) {
6299f992 188 char s[3], *t = s;
30154650 189 if (obj->pin_display)
6299f992
CW		 190 *t++ = 'p';
191 if (obj->fault_mappable)
192 *t++ = 'f';
193 *t = '\0';
194 seq_printf(m, " (%s mappable)", s);
195 }
27c01aae 196
d72d908b
CW		 197 engine = i915_gem_active_get_engine(&obj->last_write,
198 &obj->base.dev->struct_mutex);
27c01aae
CW		 199 if (engine)
200 seq_printf(m, " (%s)", engine->name);
201
faf5bf0a
CW		 202 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
203 if (frontbuffer_bits)
204 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
37811fcc
CW		 205}
206
6d2b8885
CW		 207static int obj_rank_by_stolen(void *priv,
208 struct list_head *A, struct list_head *B)
209{
210 struct drm_i915_gem_object *a =
b25cb2f8 211 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 212 struct drm_i915_gem_object *b =
b25cb2f8 213 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 214
2d05fa16
RV		 215 if (a->stolen->start < b->stolen->start)
216 return -1;
217 if (a->stolen->start > b->stolen->start)
218 return 1;
219 return 0;
6d2b8885
CW		 220}
221
222static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
223{
9f25d007 224 struct drm_info_node *node = m->private;
6d2b8885 225 struct drm_device *dev = node->minor->dev;
fac5e23e 226 struct drm_i915_private *dev_priv = to_i915(dev);
6d2b8885 227 struct drm_i915_gem_object *obj;
c44ef60e 228 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 229 LIST_HEAD(stolen);
230 int count, ret;
231
232 ret = mutex_lock_interruptible(&dev->struct_mutex);
233 if (ret)
234 return ret;
235
236 total_obj_size = total_gtt_size = count = 0;
237 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
238 if (obj->stolen == NULL)
239 continue;
240
b25cb2f8 241 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 242
243 total_obj_size += obj->base.size;
ca1543be 244 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 245 count++;
246 }
247 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
248 if (obj->stolen == NULL)
249 continue;
250
b25cb2f8 251 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 252
253 total_obj_size += obj->base.size;
254 count++;
255 }
256 list_sort(NULL, &stolen, obj_rank_by_stolen);
257 seq_puts(m, "Stolen:\n");
258 while (!list_empty(&stolen)) {
b25cb2f8 259 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 260 seq_puts(m, " ");
261 describe_obj(m, obj);
262 seq_putc(m, '\n');
b25cb2f8 263 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 264 }
265 mutex_unlock(&dev->struct_mutex);
266
c44ef60e 267 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 268 count, total_obj_size, total_gtt_size);
269 return 0;
270}
271
2db8e9d6 272struct file_stats {
6313c204 273 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 274 unsigned long count;
275 u64 total, unbound;
276 u64 global, shared;
277 u64 active, inactive;
2db8e9d6
CW		 278};
279
280static int per_file_stats(int id, void *ptr, void *data)
281{
282 struct drm_i915_gem_object *obj = ptr;
283 struct file_stats *stats = data;
6313c204 284 struct i915_vma *vma;
2db8e9d6
CW		 285
286 stats->count++;
287 stats->total += obj->base.size;
15717de2
CW		 288 if (!obj->bind_count)
289 stats->unbound += obj->base.size;
c67a17e9
CW		 290 if (obj->base.name || obj->base.dma_buf)
291 stats->shared += obj->base.size;
292
894eeecc
CW		 293 list_for_each_entry(vma, &obj->vma_list, obj_link) {
294 if (!drm_mm_node_allocated(&vma->node))
295 continue;
6313c204 296
3272db53 297 if (i915_vma_is_ggtt(vma)) {
894eeecc
CW		 298 stats->global += vma->node.size;
299 } else {
300 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
6313c204 301
2bfa996e 302 if (ppgtt->base.file != stats->file_priv)
6313c204 303 continue;
6313c204 304 }
894eeecc 305
b0decaf7 306 if (i915_vma_is_active(vma))
894eeecc
CW		 307 stats->active += vma->node.size;
308 else
309 stats->inactive += vma->node.size;
2db8e9d6
CW		 310 }
311
312 return 0;
313}
314
b0da1b79
CW		 315#define print_file_stats(m, name, stats) do { \
316 if (stats.count) \
c44ef60e 317 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 318 name, \
319 stats.count, \
320 stats.total, \
321 stats.active, \
322 stats.inactive, \
323 stats.global, \
324 stats.shared, \
325 stats.unbound); \
326} while (0)
493018dc
BV		 327
328static void print_batch_pool_stats(struct seq_file *m,
329 struct drm_i915_private *dev_priv)
330{
331 struct drm_i915_gem_object *obj;
332 struct file_stats stats;
e2f80391 333 struct intel_engine_cs *engine;
b4ac5afc 334 int j;
493018dc
BV		 335
336 memset(&stats, 0, sizeof(stats));
337
b4ac5afc 338 for_each_engine(engine, dev_priv) {
e2f80391 339 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744 340 list_for_each_entry(obj,
e2f80391 341 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 342 batch_pool_link)
343 per_file_stats(0, obj, &stats);
344 }
06fbca71 345 }
493018dc 346
b0da1b79 347 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 348}
349
15da9565
CW		 350static int per_file_ctx_stats(int id, void *ptr, void *data)
351{
352 struct i915_gem_context *ctx = ptr;
353 int n;
354
355 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
356 if (ctx->engine[n].state)
bf3783e5 357 per_file_stats(0, ctx->engine[n].state->obj, data);
dca33ecc 358 if (ctx->engine[n].ring)
57e88531 359 per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
15da9565
CW		 360 }
361
362 return 0;
363}
364
365static void print_context_stats(struct seq_file *m,
366 struct drm_i915_private *dev_priv)
367{
368 struct file_stats stats;
369 struct drm_file *file;
370
371 memset(&stats, 0, sizeof(stats));
372
91c8a326 373 mutex_lock(&dev_priv->drm.struct_mutex);
15da9565
CW		 374 if (dev_priv->kernel_context)
375 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
376
91c8a326 377 list_for_each_entry(file, &dev_priv->drm.filelist, lhead) {
15da9565
CW		 378 struct drm_i915_file_private *fpriv = file->driver_priv;
379 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
380 }
91c8a326 381 mutex_unlock(&dev_priv->drm.struct_mutex);
15da9565
CW		 382
383 print_file_stats(m, "[k]contexts", stats);
384}
385
ca191b13 386static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 387{
9f25d007 388 struct drm_info_node *node = m->private;
73aa808f 389 struct drm_device *dev = node->minor->dev;
72e96d64
JL		 390 struct drm_i915_private *dev_priv = to_i915(dev);
391 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2bd160a1
CW		 392 u32 count, mapped_count, purgeable_count, dpy_count;
393 u64 size, mapped_size, purgeable_size, dpy_size;
6299f992 394 struct drm_i915_gem_object *obj;
2db8e9d6 395 struct drm_file *file;
73aa808f
CW		 396 int ret;
397
398 ret = mutex_lock_interruptible(&dev->struct_mutex);
399 if (ret)
400 return ret;
401
6299f992
CW		 402 seq_printf(m, "%u objects, %zu bytes\n",
403 dev_priv->mm.object_count,
404 dev_priv->mm.object_memory);
405
1544c42e
CW		 406 size = count = 0;
407 mapped_size = mapped_count = 0;
408 purgeable_size = purgeable_count = 0;
35c20a60 409 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
2bd160a1
CW		 410 size += obj->base.size;
411 ++count;
412
413 if (obj->madv == I915_MADV_DONTNEED) {
414 purgeable_size += obj->base.size;
415 ++purgeable_count;
416 }
417
be19b10d 418 if (obj->mapping) {
2bd160a1
CW		 419 mapped_count++;
420 mapped_size += obj->base.size;
be19b10d 421 }
b7abb714 422 }
c44ef60e 423 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 424
2bd160a1 425 size = count = dpy_size = dpy_count = 0;
35c20a60 426 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2bd160a1
CW		 427 size += obj->base.size;
428 ++count;
429
30154650 430 if (obj->pin_display) {
2bd160a1
CW		 431 dpy_size += obj->base.size;
432 ++dpy_count;
6299f992 433 }
2bd160a1 434
b7abb714
CW		 435 if (obj->madv == I915_MADV_DONTNEED) {
436 purgeable_size += obj->base.size;
437 ++purgeable_count;
438 }
2bd160a1 439
be19b10d 440 if (obj->mapping) {
2bd160a1
CW		 441 mapped_count++;
442 mapped_size += obj->base.size;
be19b10d 443 }
6299f992 444 }
2bd160a1
CW		 445 seq_printf(m, "%u bound objects, %llu bytes\n",
446 count, size);
c44ef60e 447 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 448 purgeable_count, purgeable_size);
2bd160a1
CW		 449 seq_printf(m, "%u mapped objects, %llu bytes\n",
450 mapped_count, mapped_size);
451 seq_printf(m, "%u display objects (pinned), %llu bytes\n",
452 dpy_count, dpy_size);
6299f992 453
c44ef60e 454 seq_printf(m, "%llu [%llu] gtt total\n",
72e96d64 455 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
73aa808f 456
493018dc
BV		 457 seq_putc(m, '\n');
458 print_batch_pool_stats(m, dev_priv);
1d2ac403
DV		 459 mutex_unlock(&dev->struct_mutex);
460
461 mutex_lock(&dev->filelist_mutex);
15da9565 462 print_context_stats(m, dev_priv);
2db8e9d6
CW		 463 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
464 struct file_stats stats;
c84455b4
CW		 465 struct drm_i915_file_private *file_priv = file->driver_priv;
466 struct drm_i915_gem_request *request;
3ec2f427 467 struct task_struct *task;
2db8e9d6
CW		 468
469 memset(&stats, 0, sizeof(stats));
6313c204 470 stats.file_priv = file->driver_priv;
5b5ffff0 471 spin_lock(&file->table_lock);
2db8e9d6 472 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 473 spin_unlock(&file->table_lock);
3ec2f427
TH		 474 /*
475 * Although we have a valid reference on file->pid, that does
476 * not guarantee that the task_struct who called get_pid() is
477 * still alive (e.g. get_pid(current) => fork() => exit()).
478 * Therefore, we need to protect this ->comm access using RCU.
479 */
c84455b4
CW		 480 mutex_lock(&dev->struct_mutex);
481 request = list_first_entry_or_null(&file_priv->mm.request_list,
482 struct drm_i915_gem_request,
483 client_list);
3ec2f427 484 rcu_read_lock();
c84455b4
CW		 485 task = pid_task(request && request->ctx->pid ?
486 request->ctx->pid : file->pid,
487 PIDTYPE_PID);
493018dc 488 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 489 rcu_read_unlock();
c84455b4 490 mutex_unlock(&dev->struct_mutex);
2db8e9d6 491 }
1d2ac403 492 mutex_unlock(&dev->filelist_mutex);
73aa808f
CW		 493
494 return 0;
495}
496
aee56cff 497static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 498{
9f25d007 499 struct drm_info_node *node = m->private;
08c18323 500 struct drm_device *dev = node->minor->dev;
fac5e23e 501 struct drm_i915_private *dev_priv = to_i915(dev);
5f4b091a 502 bool show_pin_display_only = !!node->info_ent->data;
08c18323 503 struct drm_i915_gem_object *obj;
c44ef60e 504 u64 total_obj_size, total_gtt_size;
08c18323
CW		 505 int count, ret;
506
507 ret = mutex_lock_interruptible(&dev->struct_mutex);
508 if (ret)
509 return ret;
510
511 total_obj_size = total_gtt_size = count = 0;
35c20a60 512 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6da84829 513 if (show_pin_display_only && !obj->pin_display)
1b50247a
CW		 514 continue;
515
267f0c90 516 seq_puts(m, " ");
08c18323 517 describe_obj(m, obj);
267f0c90 518 seq_putc(m, '\n');
08c18323 519 total_obj_size += obj->base.size;
ca1543be 520 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 521 count++;
522 }
523
524 mutex_unlock(&dev->struct_mutex);
525
c44ef60e 526 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 527 count, total_obj_size, total_gtt_size);
528
529 return 0;
530}
531
4e5359cd
SF		 532static int i915_gem_pageflip_info(struct seq_file *m, void *data)
533{
9f25d007 534 struct drm_info_node *node = m->private;
4e5359cd 535 struct drm_device *dev = node->minor->dev;
fac5e23e 536 struct drm_i915_private *dev_priv = to_i915(dev);
4e5359cd 537 struct intel_crtc *crtc;
8a270ebf
DV		 538 int ret;
539
540 ret = mutex_lock_interruptible(&dev->struct_mutex);
541 if (ret)
542 return ret;
4e5359cd 543
d3fcc808 544 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 545 const char pipe = pipe_name(crtc->pipe);
546 const char plane = plane_name(crtc->plane);
51cbaf01 547 struct intel_flip_work *work;
4e5359cd 548
5e2d7afc 549 spin_lock_irq(&dev->event_lock);
5a21b665
DV		 550 work = crtc->flip_work;
551 if (work == NULL) {
9db4a9c7 552 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 553 pipe, plane);
554 } else {
5a21b665
DV		 555 u32 pending;
556 u32 addr;
557
558 pending = atomic_read(&work->pending);
559 if (pending) {
560 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
561 pipe, plane);
562 } else {
563 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
564 pipe, plane);
565 }
566 if (work->flip_queued_req) {
567 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
568
569 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
570 engine->name,
571 i915_gem_request_get_seqno(work->flip_queued_req),
572 dev_priv->next_seqno,
1b7744e7 573 intel_engine_get_seqno(engine),
f69a02c9 574 i915_gem_request_completed(work->flip_queued_req));
5a21b665
DV		 575 } else
576 seq_printf(m, "Flip not associated with any ring\n");
577 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
578 work->flip_queued_vblank,
579 work->flip_ready_vblank,
580 intel_crtc_get_vblank_counter(crtc));
581 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
582
583 if (INTEL_INFO(dev)->gen >= 4)
584 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
585 else
586 addr = I915_READ(DSPADDR(crtc->plane));
587 seq_printf(m, "Current scanout address 0x%08x\n", addr);
588
589 if (work->pending_flip_obj) {
590 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
591 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 592 }
593 }
5e2d7afc 594 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 595 }
596
8a270ebf
DV		 597 mutex_unlock(&dev->struct_mutex);
598
4e5359cd
SF		 599 return 0;
600}
601
493018dc
BV		 602static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
603{
604 struct drm_info_node *node = m->private;
605 struct drm_device *dev = node->minor->dev;
fac5e23e 606 struct drm_i915_private *dev_priv = to_i915(dev);
493018dc 607 struct drm_i915_gem_object *obj;
e2f80391 608 struct intel_engine_cs *engine;
8d9d5744 609 int total = 0;
b4ac5afc 610 int ret, j;
493018dc
BV		 611
612 ret = mutex_lock_interruptible(&dev->struct_mutex);
613 if (ret)
614 return ret;
615
b4ac5afc 616 for_each_engine(engine, dev_priv) {
e2f80391 617 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744
CW		 618 int count;
619
620 count = 0;
621 list_for_each_entry(obj,
e2f80391 622 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 623 batch_pool_link)
624 count++;
625 seq_printf(m, "%s cache[%d]: %d objects\n",
e2f80391 626 engine->name, j, count);
8d9d5744
CW		 627
628 list_for_each_entry(obj,
e2f80391 629 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 630 batch_pool_link) {
631 seq_puts(m, " ");
632 describe_obj(m, obj);
633 seq_putc(m, '\n');
634 }
635
636 total += count;
06fbca71 637 }
493018dc
BV		 638 }
639
8d9d5744 640 seq_printf(m, "total: %d\n", total);
493018dc
BV		 641
642 mutex_unlock(&dev->struct_mutex);
643
644 return 0;
645}
646
2017263e
BG		 647static int i915_gem_request_info(struct seq_file *m, void *data)
648{
9f25d007 649 struct drm_info_node *node = m->private;
2017263e 650 struct drm_device *dev = node->minor->dev;
fac5e23e 651 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 652 struct intel_engine_cs *engine;
eed29a5b 653 struct drm_i915_gem_request *req;
b4ac5afc 654 int ret, any;
de227ef0
CW		 655
656 ret = mutex_lock_interruptible(&dev->struct_mutex);
657 if (ret)
658 return ret;
2017263e 659
2d1070b2 660 any = 0;
b4ac5afc 661 for_each_engine(engine, dev_priv) {
2d1070b2
CW		 662 int count;
663
664 count = 0;
efdf7c06 665 list_for_each_entry(req, &engine->request_list, link)
2d1070b2
CW		 666 count++;
667 if (count == 0)
a2c7f6fd
CW		 668 continue;
669
e2f80391 670 seq_printf(m, "%s requests: %d\n", engine->name, count);
efdf7c06 671 list_for_each_entry(req, &engine->request_list, link) {
c84455b4 672 struct pid *pid = req->ctx->pid;
2d1070b2
CW		 673 struct task_struct *task;
674
675 rcu_read_lock();
c84455b4 676 task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
2d1070b2 677 seq_printf(m, " %x @ %d: %s [%d]\n",
04769652 678 req->fence.seqno,
eed29a5b 679 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 680 task ? task->comm : "<unknown>",
681 task ? task->pid : -1);
682 rcu_read_unlock();
c2c347a9 683 }
2d1070b2
CW		 684
685 any++;
2017263e 686 }
de227ef0
CW		 687 mutex_unlock(&dev->struct_mutex);
688
2d1070b2 689 if (any == 0)
267f0c90 690 seq_puts(m, "No requests\n");
c2c347a9 691
2017263e
BG		 692 return 0;
693}
694
b2223497 695static void i915_ring_seqno_info(struct seq_file *m,
0bc40be8 696 struct intel_engine_cs *engine)
b2223497 697{
688e6c72
CW		 698 struct intel_breadcrumbs *b = &engine->breadcrumbs;
699 struct rb_node *rb;
700
12471ba8 701 seq_printf(m, "Current sequence (%s): %x\n",
1b7744e7 702 engine->name, intel_engine_get_seqno(engine));
688e6c72
CW		 703
704 spin_lock(&b->lock);
705 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
706 struct intel_wait *w = container_of(rb, typeof(*w), node);
707
708 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
709 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
710 }
711 spin_unlock(&b->lock);
b2223497
CW		 712}
713
2017263e
BG		 714static int i915_gem_seqno_info(struct seq_file *m, void *data)
715{
9f25d007 716 struct drm_info_node *node = m->private;
2017263e 717 struct drm_device *dev = node->minor->dev;
fac5e23e 718 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 719 struct intel_engine_cs *engine;
b4ac5afc 720 int ret;
de227ef0
CW		 721
722 ret = mutex_lock_interruptible(&dev->struct_mutex);
723 if (ret)
724 return ret;
c8c8fb33 725 intel_runtime_pm_get(dev_priv);
2017263e 726
b4ac5afc 727 for_each_engine(engine, dev_priv)
e2f80391 728 i915_ring_seqno_info(m, engine);
de227ef0 729
c8c8fb33 730 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 731 mutex_unlock(&dev->struct_mutex);
732
2017263e
BG		 733 return 0;
734}
735
736
737static int i915_interrupt_info(struct seq_file *m, void *data)
738{
9f25d007 739 struct drm_info_node *node = m->private;
2017263e 740 struct drm_device *dev = node->minor->dev;
fac5e23e 741 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 742 struct intel_engine_cs *engine;
9db4a9c7 743 int ret, i, pipe;
de227ef0
CW		 744
745 ret = mutex_lock_interruptible(&dev->struct_mutex);
746 if (ret)
747 return ret;
c8c8fb33 748 intel_runtime_pm_get(dev_priv);
2017263e 749
74e1ca8c 750 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 751 seq_printf(m, "Master Interrupt Control:\t%08x\n",
752 I915_READ(GEN8_MASTER_IRQ));
753
754 seq_printf(m, "Display IER:\t%08x\n",
755 I915_READ(VLV_IER));
756 seq_printf(m, "Display IIR:\t%08x\n",
757 I915_READ(VLV_IIR));
758 seq_printf(m, "Display IIR_RW:\t%08x\n",
759 I915_READ(VLV_IIR_RW));
760 seq_printf(m, "Display IMR:\t%08x\n",
761 I915_READ(VLV_IMR));
055e393f 762 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 763 seq_printf(m, "Pipe %c stat:\t%08x\n",
764 pipe_name(pipe),
765 I915_READ(PIPESTAT(pipe)));
766
767 seq_printf(m, "Port hotplug:\t%08x\n",
768 I915_READ(PORT_HOTPLUG_EN));
769 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
770 I915_READ(VLV_DPFLIPSTAT));
771 seq_printf(m, "DPINVGTT:\t%08x\n",
772 I915_READ(DPINVGTT));
773
774 for (i = 0; i < 4; i++) {
775 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
776 i, I915_READ(GEN8_GT_IMR(i)));
777 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
778 i, I915_READ(GEN8_GT_IIR(i)));
779 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
780 i, I915_READ(GEN8_GT_IER(i)));
781 }
782
783 seq_printf(m, "PCU interrupt mask:\t%08x\n",
784 I915_READ(GEN8_PCU_IMR));
785 seq_printf(m, "PCU interrupt identity:\t%08x\n",
786 I915_READ(GEN8_PCU_IIR));
787 seq_printf(m, "PCU interrupt enable:\t%08x\n",
788 I915_READ(GEN8_PCU_IER));
789 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 790 seq_printf(m, "Master Interrupt Control:\t%08x\n",
791 I915_READ(GEN8_MASTER_IRQ));
792
793 for (i = 0; i < 4; i++) {
794 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
795 i, I915_READ(GEN8_GT_IMR(i)));
796 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
797 i, I915_READ(GEN8_GT_IIR(i)));
798 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
799 i, I915_READ(GEN8_GT_IER(i)));
800 }
801
055e393f 802 for_each_pipe(dev_priv, pipe) {
e129649b
ID		 803 enum intel_display_power_domain power_domain;
804
805 power_domain = POWER_DOMAIN_PIPE(pipe);
806 if (!intel_display_power_get_if_enabled(dev_priv,
807 power_domain)) {
22c59960
PZ		 808 seq_printf(m, "Pipe %c power disabled\n",
809 pipe_name(pipe));
810 continue;
811 }
a123f157 812 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 813 pipe_name(pipe),
814 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 815 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 816 pipe_name(pipe),
817 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 818 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 819 pipe_name(pipe),
820 I915_READ(GEN8_DE_PIPE_IER(pipe)));
e129649b
ID		 821
822 intel_display_power_put(dev_priv, power_domain);
a123f157
BW		 823 }
824
825 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
826 I915_READ(GEN8_DE_PORT_IMR));
827 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
828 I915_READ(GEN8_DE_PORT_IIR));
829 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
830 I915_READ(GEN8_DE_PORT_IER));
831
832 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
833 I915_READ(GEN8_DE_MISC_IMR));
834 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
835 I915_READ(GEN8_DE_MISC_IIR));
836 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
837 I915_READ(GEN8_DE_MISC_IER));
838
839 seq_printf(m, "PCU interrupt mask:\t%08x\n",
840 I915_READ(GEN8_PCU_IMR));
841 seq_printf(m, "PCU interrupt identity:\t%08x\n",
842 I915_READ(GEN8_PCU_IIR));
843 seq_printf(m, "PCU interrupt enable:\t%08x\n",
844 I915_READ(GEN8_PCU_IER));
845 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 846 seq_printf(m, "Display IER:\t%08x\n",
847 I915_READ(VLV_IER));
848 seq_printf(m, "Display IIR:\t%08x\n",
849 I915_READ(VLV_IIR));
850 seq_printf(m, "Display IIR_RW:\t%08x\n",
851 I915_READ(VLV_IIR_RW));
852 seq_printf(m, "Display IMR:\t%08x\n",
853 I915_READ(VLV_IMR));
055e393f 854 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 855 seq_printf(m, "Pipe %c stat:\t%08x\n",
856 pipe_name(pipe),
857 I915_READ(PIPESTAT(pipe)));
858
859 seq_printf(m, "Master IER:\t%08x\n",
860 I915_READ(VLV_MASTER_IER));
861
862 seq_printf(m, "Render IER:\t%08x\n",
863 I915_READ(GTIER));
864 seq_printf(m, "Render IIR:\t%08x\n",
865 I915_READ(GTIIR));
866 seq_printf(m, "Render IMR:\t%08x\n",
867 I915_READ(GTIMR));
868
869 seq_printf(m, "PM IER:\t\t%08x\n",
870 I915_READ(GEN6_PMIER));
871 seq_printf(m, "PM IIR:\t\t%08x\n",
872 I915_READ(GEN6_PMIIR));
873 seq_printf(m, "PM IMR:\t\t%08x\n",
874 I915_READ(GEN6_PMIMR));
875
876 seq_printf(m, "Port hotplug:\t%08x\n",
877 I915_READ(PORT_HOTPLUG_EN));
878 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
879 I915_READ(VLV_DPFLIPSTAT));
880 seq_printf(m, "DPINVGTT:\t%08x\n",
881 I915_READ(DPINVGTT));
882
883 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 884 seq_printf(m, "Interrupt enable: %08x\n",
885 I915_READ(IER));
886 seq_printf(m, "Interrupt identity: %08x\n",
887 I915_READ(IIR));
888 seq_printf(m, "Interrupt mask: %08x\n",
889 I915_READ(IMR));
055e393f 890 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 891 seq_printf(m, "Pipe %c stat: %08x\n",
892 pipe_name(pipe),
893 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 894 } else {
895 seq_printf(m, "North Display Interrupt enable: %08x\n",
896 I915_READ(DEIER));
897 seq_printf(m, "North Display Interrupt identity: %08x\n",
898 I915_READ(DEIIR));
899 seq_printf(m, "North Display Interrupt mask: %08x\n",
900 I915_READ(DEIMR));
901 seq_printf(m, "South Display Interrupt enable: %08x\n",
902 I915_READ(SDEIER));
903 seq_printf(m, "South Display Interrupt identity: %08x\n",
904 I915_READ(SDEIIR));
905 seq_printf(m, "South Display Interrupt mask: %08x\n",
906 I915_READ(SDEIMR));
907 seq_printf(m, "Graphics Interrupt enable: %08x\n",
908 I915_READ(GTIER));
909 seq_printf(m, "Graphics Interrupt identity: %08x\n",
910 I915_READ(GTIIR));
911 seq_printf(m, "Graphics Interrupt mask: %08x\n",
912 I915_READ(GTIMR));
913 }
b4ac5afc 914 for_each_engine(engine, dev_priv) {
a123f157 915 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 916 seq_printf(m,
917 "Graphics Interrupt mask (%s): %08x\n",
e2f80391 918 engine->name, I915_READ_IMR(engine));
9862e600 919 }
e2f80391 920 i915_ring_seqno_info(m, engine);
9862e600 921 }
c8c8fb33 922 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 923 mutex_unlock(&dev->struct_mutex);
924
2017263e
BG		 925 return 0;
926}
927
a6172a80
CW		 928static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
929{
9f25d007 930 struct drm_info_node *node = m->private;
a6172a80 931 struct drm_device *dev = node->minor->dev;
fac5e23e 932 struct drm_i915_private *dev_priv = to_i915(dev);
de227ef0
CW		 933 int i, ret;
934
935 ret = mutex_lock_interruptible(&dev->struct_mutex);
936 if (ret)
937 return ret;
a6172a80 938
a6172a80
CW		 939 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
940 for (i = 0; i < dev_priv->num_fence_regs; i++) {
49ef5294 941 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
a6172a80 942
6c085a72
CW		 943 seq_printf(m, "Fence %d, pin count = %d, object = ",
944 i, dev_priv->fence_regs[i].pin_count);
49ef5294 945 if (!vma)
267f0c90 946 seq_puts(m, "unused");
c2c347a9 947 else
49ef5294 948 describe_obj(m, vma->obj);
267f0c90 949 seq_putc(m, '\n');
a6172a80
CW		 950 }
951
05394f39 952 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 953 return 0;
954}
955
2017263e
BG		 956static int i915_hws_info(struct seq_file *m, void *data)
957{
9f25d007 958 struct drm_info_node *node = m->private;
2017263e 959 struct drm_device *dev = node->minor->dev;
fac5e23e 960 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 961 struct intel_engine_cs *engine;
1a240d4d 962 const u32 *hws;
4066c0ae
CW		 963 int i;
964
4a570db5 965 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
e2f80391 966 hws = engine->status_page.page_addr;
2017263e
BG		 967 if (hws == NULL)
968 return 0;
969
970 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
971 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
972 i * 4,
973 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
974 }
975 return 0;
976}
977
d5442303
DV		 978static ssize_t
979i915_error_state_write(struct file *filp,
980 const char __user *ubuf,
981 size_t cnt,
982 loff_t *ppos)
983{
edc3d884 984 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 985 struct drm_device *dev = error_priv->dev;
22bcfc6a 986 int ret;
d5442303
DV		 987
988 DRM_DEBUG_DRIVER("Resetting error state\n");
989
22bcfc6a
DV		 990 ret = mutex_lock_interruptible(&dev->struct_mutex);
991 if (ret)
992 return ret;
993
d5442303
DV		 994 i915_destroy_error_state(dev);
995 mutex_unlock(&dev->struct_mutex);
996
997 return cnt;
998}
999
1000static int i915_error_state_open(struct inode *inode, struct file *file)
1001{
1002 struct drm_device *dev = inode->i_private;
d5442303 1003 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1004
1005 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1006 if (!error_priv)
1007 return -ENOMEM;
1008
1009 error_priv->dev = dev;
1010
95d5bfb3 1011 i915_error_state_get(dev, error_priv);
d5442303 1012
edc3d884
MK		 1013 file->private_data = error_priv;
1014
1015 return 0;
d5442303
DV		 1016}
1017
1018static int i915_error_state_release(struct inode *inode, struct file *file)
1019{
edc3d884 1020 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1021
95d5bfb3 1022 i915_error_state_put(error_priv);
d5442303
DV		 1023 kfree(error_priv);
1024
edc3d884
MK		 1025 return 0;
1026}
1027
4dc955f7
MK		 1028static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1029 size_t count, loff_t *pos)
1030{
1031 struct i915_error_state_file_priv *error_priv = file->private_data;
1032 struct drm_i915_error_state_buf error_str;
1033 loff_t tmp_pos = 0;
1034 ssize_t ret_count = 0;
1035 int ret;
1036
0a4cd7c8 1037 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1038 if (ret)
1039 return ret;
edc3d884 1040
fc16b48b 1041 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1042 if (ret)
1043 goto out;
1044
edc3d884
MK		 1045 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1046 error_str.buf,
1047 error_str.bytes);
1048
1049 if (ret_count < 0)
1050 ret = ret_count;
1051 else
1052 *pos = error_str.start + ret_count;
1053out:
4dc955f7 1054 i915_error_state_buf_release(&error_str);
edc3d884 1055 return ret ?: ret_count;
d5442303
DV		 1056}
1057
1058static const struct file_operations i915_error_state_fops = {
1059 .owner = THIS_MODULE,
1060 .open = i915_error_state_open,
edc3d884 1061 .read = i915_error_state_read,
d5442303
DV		 1062 .write = i915_error_state_write,
1063 .llseek = default_llseek,
1064 .release = i915_error_state_release,
1065};
1066
647416f9
KC		 1067static int
1068i915_next_seqno_get(void *data, u64 *val)
40633219 1069{
647416f9 1070 struct drm_device *dev = data;
fac5e23e 1071 struct drm_i915_private *dev_priv = to_i915(dev);
40633219
MK		 1072 int ret;
1073
1074 ret = mutex_lock_interruptible(&dev->struct_mutex);
1075 if (ret)
1076 return ret;
1077
647416f9 1078 *val = dev_priv->next_seqno;
40633219
MK		 1079 mutex_unlock(&dev->struct_mutex);
1080
647416f9 1081 return 0;
40633219
MK		 1082}
1083
647416f9
KC		 1084static int
1085i915_next_seqno_set(void *data, u64 val)
1086{
1087 struct drm_device *dev = data;
40633219
MK		 1088 int ret;
1089
40633219
MK		 1090 ret = mutex_lock_interruptible(&dev->struct_mutex);
1091 if (ret)
1092 return ret;
1093
e94fbaa8 1094 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1095 mutex_unlock(&dev->struct_mutex);
1096
647416f9 1097 return ret;
40633219
MK		 1098}
1099
647416f9
KC		 1100DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1101 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1102 "0x%llx\n");
40633219 1103
adb4bd12 1104static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1105{
9f25d007 1106 struct drm_info_node *node = m->private;
f97108d1 1107 struct drm_device *dev = node->minor->dev;
fac5e23e 1108 struct drm_i915_private *dev_priv = to_i915(dev);
c8c8fb33
PZ		 1109 int ret = 0;
1110
1111 intel_runtime_pm_get(dev_priv);
3b8d8d91
JB		 1112
1113 if (IS_GEN5(dev)) {
1114 u16 rgvswctl = I915_READ16(MEMSWCTL);
1115 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1116
1117 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1118 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1119 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1120 MEMSTAT_VID_SHIFT);
1121 seq_printf(m, "Current P-state: %d\n",
1122 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
666a4537
WB		 1123 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1124 u32 freq_sts;
1125
1126 mutex_lock(&dev_priv->rps.hw_lock);
1127 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1128 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1129 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1130
1131 seq_printf(m, "actual GPU freq: %d MHz\n",
1132 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1133
1134 seq_printf(m, "current GPU freq: %d MHz\n",
1135 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1136
1137 seq_printf(m, "max GPU freq: %d MHz\n",
1138 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1139
1140 seq_printf(m, "min GPU freq: %d MHz\n",
1141 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1142
1143 seq_printf(m, "idle GPU freq: %d MHz\n",
1144 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1145
1146 seq_printf(m,
1147 "efficient (RPe) frequency: %d MHz\n",
1148 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1149 mutex_unlock(&dev_priv->rps.hw_lock);
1150 } else if (INTEL_INFO(dev)->gen >= 6) {
35040562
BP		 1151 u32 rp_state_limits;
1152 u32 gt_perf_status;
1153 u32 rp_state_cap;
0d8f9491 1154 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1155 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1156 u32 rpupei, rpcurup, rpprevup;
1157 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1158 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1159 int max_freq;
1160
35040562
BP		 1161 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1162 if (IS_BROXTON(dev)) {
1163 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1164 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1165 } else {
1166 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1167 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1168 }
1169
3b8d8d91 1170 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1171 ret = mutex_lock_interruptible(&dev->struct_mutex);
1172 if (ret)
c8c8fb33 1173 goto out;
d1ebd816 1174
59bad947 1175 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1176
8e8c06cd 1177 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1178 if (IS_GEN9(dev))
1179 reqf >>= 23;
1180 else {
1181 reqf &= ~GEN6_TURBO_DISABLE;
1182 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1183 reqf >>= 24;
1184 else
1185 reqf >>= 25;
1186 }
7c59a9c1 1187 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1188
0d8f9491
CW		 1189 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1190 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1191 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1192
ccab5c82 1193 rpstat = I915_READ(GEN6_RPSTAT1);
d6cda9c7
AG		 1194 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1195 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1196 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1197 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1198 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1199 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
60260a5b
AG		 1200 if (IS_GEN9(dev))
1201 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1202 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1203 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1204 else
1205 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1206 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1207
59bad947 1208 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1209 mutex_unlock(&dev->struct_mutex);
1210
9dd3c605
PZ		 1211 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1212 pm_ier = I915_READ(GEN6_PMIER);
1213 pm_imr = I915_READ(GEN6_PMIMR);
1214 pm_isr = I915_READ(GEN6_PMISR);
1215 pm_iir = I915_READ(GEN6_PMIIR);
1216 pm_mask = I915_READ(GEN6_PMINTRMSK);
1217 } else {
1218 pm_ier = I915_READ(GEN8_GT_IER(2));
1219 pm_imr = I915_READ(GEN8_GT_IMR(2));
1220 pm_isr = I915_READ(GEN8_GT_ISR(2));
1221 pm_iir = I915_READ(GEN8_GT_IIR(2));
1222 pm_mask = I915_READ(GEN6_PMINTRMSK);
1223 }
0d8f9491 1224 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1225 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1800ad25 1226 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
3b8d8d91 1227 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1228 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1229 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1230 seq_printf(m, "Render p-state VID: %d\n",
1231 gt_perf_status & 0xff);
1232 seq_printf(m, "Render p-state limit: %d\n",
1233 rp_state_limits & 0xff);
0d8f9491
CW		 1234 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1235 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1236 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1237 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1238 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1239 seq_printf(m, "CAGF: %dMHz\n", cagf);
d6cda9c7
AG		 1240 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1241 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1242 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1243 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1244 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1245 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
d86ed34a
CW		 1246 seq_printf(m, "Up threshold: %d%%\n",
1247 dev_priv->rps.up_threshold);
1248
d6cda9c7
AG		 1249 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1250 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1251 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1252 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1253 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1254 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
d86ed34a
CW		 1255 seq_printf(m, "Down threshold: %d%%\n",
1256 dev_priv->rps.down_threshold);
3b8d8d91 1257
35040562
BP		 1258 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1259 rp_state_cap >> 16) & 0xff;
ef11bdb3
RV		 1260 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1261 GEN9_FREQ_SCALER : 1);
3b8d8d91 1262 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1263 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1264
1265 max_freq = (rp_state_cap & 0xff00) >> 8;
ef11bdb3
RV		 1266 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1267 GEN9_FREQ_SCALER : 1);
3b8d8d91 1268 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1269 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1270
35040562
BP		 1271 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1272 rp_state_cap >> 0) & 0xff;
ef11bdb3
RV		 1273 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1274 GEN9_FREQ_SCALER : 1);
3b8d8d91 1275 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1276 intel_gpu_freq(dev_priv, max_freq));
31c77388 1277 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1278 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1279
d86ed34a
CW		 1280 seq_printf(m, "Current freq: %d MHz\n",
1281 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1282 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1283 seq_printf(m, "Idle freq: %d MHz\n",
1284 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1285 seq_printf(m, "Min freq: %d MHz\n",
1286 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
29ecd78d
CW		 1287 seq_printf(m, "Boost freq: %d MHz\n",
1288 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
d86ed34a
CW		 1289 seq_printf(m, "Max freq: %d MHz\n",
1290 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1291 seq_printf(m,
1292 "efficient (RPe) frequency: %d MHz\n",
1293 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
3b8d8d91 1294 } else {
267f0c90 1295 seq_puts(m, "no P-state info available\n");
3b8d8d91 1296 }
f97108d1 1297
1170f28c
MK		 1298 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1299 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1300 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1301
c8c8fb33
PZ		 1302out:
1303 intel_runtime_pm_put(dev_priv);
1304 return ret;
f97108d1
JB		 1305}
1306
f654449a
CW		 1307static int i915_hangcheck_info(struct seq_file *m, void *unused)
1308{
1309 struct drm_info_node *node = m->private;
ebbc7546 1310 struct drm_device *dev = node->minor->dev;
fac5e23e 1311 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 1312 struct intel_engine_cs *engine;
666796da
TU		 1313 u64 acthd[I915_NUM_ENGINES];
1314 u32 seqno[I915_NUM_ENGINES];
61642ff0 1315 u32 instdone[I915_NUM_INSTDONE_REG];
c3232b18
DG		 1316 enum intel_engine_id id;
1317 int j;
f654449a
CW		 1318
1319 if (!i915.enable_hangcheck) {
1320 seq_printf(m, "Hangcheck disabled\n");
1321 return 0;
1322 }
1323
ebbc7546
MK		 1324 intel_runtime_pm_get(dev_priv);
1325
c3232b18 1326 for_each_engine_id(engine, dev_priv, id) {
7e37f889 1327 acthd[id] = intel_engine_get_active_head(engine);
1b7744e7 1328 seqno[id] = intel_engine_get_seqno(engine);
ebbc7546
MK		 1329 }
1330
c033666a 1331 i915_get_extra_instdone(dev_priv, instdone);
61642ff0 1332
ebbc7546
MK		 1333 intel_runtime_pm_put(dev_priv);
1334
f654449a
CW		 1335 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1336 seq_printf(m, "Hangcheck active, fires in %dms\n",
1337 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1338 jiffies));
1339 } else
1340 seq_printf(m, "Hangcheck inactive\n");
1341
c3232b18 1342 for_each_engine_id(engine, dev_priv, id) {
e2f80391 1343 seq_printf(m, "%s:\n", engine->name);
14fd0d6d
CW		 1344 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1345 engine->hangcheck.seqno,
1346 seqno[id],
1347 engine->last_submitted_seqno);
83348ba8
CW		 1348 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1349 yesno(intel_engine_has_waiter(engine)),
1350 yesno(test_bit(engine->id,
1351 &dev_priv->gpu_error.missed_irq_rings)));
f654449a 1352 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
e2f80391 1353 (long long)engine->hangcheck.acthd,
c3232b18 1354 (long long)acthd[id]);
e2f80391
TU		 1355 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1356 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
61642ff0 1357
e2f80391 1358 if (engine->id == RCS) {
61642ff0
MK		 1359 seq_puts(m, "\tinstdone read =");
1360
1361 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1362 seq_printf(m, " 0x%08x", instdone[j]);
1363
1364 seq_puts(m, "\n\tinstdone accu =");
1365
1366 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1367 seq_printf(m, " 0x%08x",
e2f80391 1368 engine->hangcheck.instdone[j]);
61642ff0
MK		 1369
1370 seq_puts(m, "\n");
1371 }
f654449a
CW		 1372 }
1373
1374 return 0;
1375}
1376
4d85529d 1377static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1378{
9f25d007 1379 struct drm_info_node *node = m->private;
f97108d1 1380 struct drm_device *dev = node->minor->dev;
fac5e23e 1381 struct drm_i915_private *dev_priv = to_i915(dev);
616fdb5a
BW		 1382 u32 rgvmodectl, rstdbyctl;
1383 u16 crstandvid;
1384 int ret;
1385
1386 ret = mutex_lock_interruptible(&dev->struct_mutex);
1387 if (ret)
1388 return ret;
c8c8fb33 1389 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1390
1391 rgvmodectl = I915_READ(MEMMODECTL);
1392 rstdbyctl = I915_READ(RSTDBYCTL);
1393 crstandvid = I915_READ16(CRSTANDVID);
1394
c8c8fb33 1395 intel_runtime_pm_put(dev_priv);
616fdb5a 1396 mutex_unlock(&dev->struct_mutex);
f97108d1 1397
742f491d 1398 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1399 seq_printf(m, "Boost freq: %d\n",
1400 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1401 MEMMODE_BOOST_FREQ_SHIFT);
1402 seq_printf(m, "HW control enabled: %s\n",
742f491d 1403 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1404 seq_printf(m, "SW control enabled: %s\n",
742f491d 1405 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1406 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1407 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1408 seq_printf(m, "Starting frequency: P%d\n",
1409 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1410 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1411 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1412 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1413 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1414 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1415 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1416 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1417 seq_puts(m, "Current RS state: ");
88271da3
JB		 1418 switch (rstdbyctl & RSX_STATUS_MASK) {
1419 case RSX_STATUS_ON:
267f0c90 1420 seq_puts(m, "on\n");
88271da3
JB		 1421 break;
1422 case RSX_STATUS_RC1:
267f0c90 1423 seq_puts(m, "RC1\n");
88271da3
JB		 1424 break;
1425 case RSX_STATUS_RC1E:
267f0c90 1426 seq_puts(m, "RC1E\n");
88271da3
JB		 1427 break;
1428 case RSX_STATUS_RS1:
267f0c90 1429 seq_puts(m, "RS1\n");
88271da3
JB		 1430 break;
1431 case RSX_STATUS_RS2:
267f0c90 1432 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1433 break;
1434 case RSX_STATUS_RS3:
267f0c90 1435 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1436 break;
1437 default:
267f0c90 1438 seq_puts(m, "unknown\n");
88271da3
JB		 1439 break;
1440 }
f97108d1
JB		 1441
1442 return 0;
1443}
1444
f65367b5 1445static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1446{
b2cff0db
CW		 1447 struct drm_info_node *node = m->private;
1448 struct drm_device *dev = node->minor->dev;
fac5e23e 1449 struct drm_i915_private *dev_priv = to_i915(dev);
b2cff0db 1450 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1451
1452 spin_lock_irq(&dev_priv->uncore.lock);
33c582c1 1453 for_each_fw_domain(fw_domain, dev_priv) {
b2cff0db 1454 seq_printf(m, "%s.wake_count = %u\n",
33c582c1 1455 intel_uncore_forcewake_domain_to_str(fw_domain->id),
b2cff0db
CW		 1456 fw_domain->wake_count);
1457 }
1458 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1459
b2cff0db
CW		 1460 return 0;
1461}
1462
1463static int vlv_drpc_info(struct seq_file *m)
1464{
9f25d007 1465 struct drm_info_node *node = m->private;
669ab5aa 1466 struct drm_device *dev = node->minor->dev;
fac5e23e 1467 struct drm_i915_private *dev_priv = to_i915(dev);
6b312cd3 1468 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1469
d46c0517
ID		 1470 intel_runtime_pm_get(dev_priv);
1471
6b312cd3 1472 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1473 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1474 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1475
d46c0517
ID		 1476 intel_runtime_pm_put(dev_priv);
1477
669ab5aa
D		 1478 seq_printf(m, "Video Turbo Mode: %s\n",
1479 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1480 seq_printf(m, "Turbo enabled: %s\n",
1481 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1482 seq_printf(m, "HW control enabled: %s\n",
1483 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1484 seq_printf(m, "SW control enabled: %s\n",
1485 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1486 GEN6_RP_MEDIA_SW_MODE));
1487 seq_printf(m, "RC6 Enabled: %s\n",
1488 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1489 GEN6_RC_CTL_EI_MODE(1))));
1490 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1491 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1492 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1493 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1494
9cc19be5
ID		 1495 seq_printf(m, "Render RC6 residency since boot: %u\n",
1496 I915_READ(VLV_GT_RENDER_RC6));
1497 seq_printf(m, "Media RC6 residency since boot: %u\n",
1498 I915_READ(VLV_GT_MEDIA_RC6));
1499
f65367b5 1500 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1501}
1502
4d85529d
BW		 1503static int gen6_drpc_info(struct seq_file *m)
1504{
9f25d007 1505 struct drm_info_node *node = m->private;
4d85529d 1506 struct drm_device *dev = node->minor->dev;
fac5e23e 1507 struct drm_i915_private *dev_priv = to_i915(dev);
ecd8faea 1508 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
f2dd7578 1509 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
93b525dc 1510 unsigned forcewake_count;
aee56cff 1511 int count = 0, ret;
4d85529d
BW		 1512
1513 ret = mutex_lock_interruptible(&dev->struct_mutex);
1514 if (ret)
1515 return ret;
c8c8fb33 1516 intel_runtime_pm_get(dev_priv);
4d85529d 1517
907b28c5 1518 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1519 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1520 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1521
1522 if (forcewake_count) {
267f0c90
DL		 1523 seq_puts(m, "RC information inaccurate because somebody "
1524 "holds a forcewake reference \n");
4d85529d
BW		 1525 } else {
1526 /* NB: we cannot use forcewake, else we read the wrong values */
1527 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1528 udelay(10);
1529 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1530 }
1531
75aa3f63 1532 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
ed71f1b4 1533 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1534
1535 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1536 rcctl1 = I915_READ(GEN6_RC_CONTROL);
f2dd7578
AG		 1537 if (INTEL_INFO(dev)->gen >= 9) {
1538 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1539 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1540 }
4d85529d 1541 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1542 mutex_lock(&dev_priv->rps.hw_lock);
1543 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1544 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1545
c8c8fb33
PZ		 1546 intel_runtime_pm_put(dev_priv);
1547
4d85529d
BW		 1548 seq_printf(m, "Video Turbo Mode: %s\n",
1549 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1550 seq_printf(m, "HW control enabled: %s\n",
1551 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1552 seq_printf(m, "SW control enabled: %s\n",
1553 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1554 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1555 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1556 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1557 seq_printf(m, "RC6 Enabled: %s\n",
1558 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
f2dd7578
AG		 1559 if (INTEL_INFO(dev)->gen >= 9) {
1560 seq_printf(m, "Render Well Gating Enabled: %s\n",
1561 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1562 seq_printf(m, "Media Well Gating Enabled: %s\n",
1563 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1564 }
4d85529d
BW		 1565 seq_printf(m, "Deep RC6 Enabled: %s\n",
1566 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1567 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1568 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1569 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1570 switch (gt_core_status & GEN6_RCn_MASK) {
1571 case GEN6_RC0:
1572 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1573 seq_puts(m, "Core Power Down\n");
4d85529d 1574 else
267f0c90 1575 seq_puts(m, "on\n");
4d85529d
BW		 1576 break;
1577 case GEN6_RC3:
267f0c90 1578 seq_puts(m, "RC3\n");
4d85529d
BW		 1579 break;
1580 case GEN6_RC6:
267f0c90 1581 seq_puts(m, "RC6\n");
4d85529d
BW		 1582 break;
1583 case GEN6_RC7:
267f0c90 1584 seq_puts(m, "RC7\n");
4d85529d
BW		 1585 break;
1586 default:
267f0c90 1587 seq_puts(m, "Unknown\n");
4d85529d
BW		 1588 break;
1589 }
1590
1591 seq_printf(m, "Core Power Down: %s\n",
1592 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
f2dd7578
AG		 1593 if (INTEL_INFO(dev)->gen >= 9) {
1594 seq_printf(m, "Render Power Well: %s\n",
1595 (gen9_powergate_status &
1596 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1597 seq_printf(m, "Media Power Well: %s\n",
1598 (gen9_powergate_status &
1599 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1600 }
cce66a28
BW		 1601
1602 /* Not exactly sure what this is */
1603 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1604 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1605 seq_printf(m, "RC6 residency since boot: %u\n",
1606 I915_READ(GEN6_GT_GFX_RC6));
1607 seq_printf(m, "RC6+ residency since boot: %u\n",
1608 I915_READ(GEN6_GT_GFX_RC6p));
1609 seq_printf(m, "RC6++ residency since boot: %u\n",
1610 I915_READ(GEN6_GT_GFX_RC6pp));
1611
ecd8faea
BW		 1612 seq_printf(m, "RC6 voltage: %dmV\n",
1613 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1614 seq_printf(m, "RC6+ voltage: %dmV\n",
1615 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1616 seq_printf(m, "RC6++ voltage: %dmV\n",
1617 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
f2dd7578 1618 return i915_forcewake_domains(m, NULL);
4d85529d
BW		 1619}
1620
1621static int i915_drpc_info(struct seq_file *m, void *unused)
1622{
9f25d007 1623 struct drm_info_node *node = m->private;
4d85529d
BW		 1624 struct drm_device *dev = node->minor->dev;
1625
666a4537 1626 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
669ab5aa 1627 return vlv_drpc_info(m);
ac66cf4b 1628 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1629 return gen6_drpc_info(m);
1630 else
1631 return ironlake_drpc_info(m);
1632}
1633
9a851789
DV		 1634static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1635{
1636 struct drm_info_node *node = m->private;
1637 struct drm_device *dev = node->minor->dev;
fac5e23e 1638 struct drm_i915_private *dev_priv = to_i915(dev);
9a851789
DV		 1639
1640 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1641 dev_priv->fb_tracking.busy_bits);
1642
1643 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1644 dev_priv->fb_tracking.flip_bits);
1645
1646 return 0;
1647}
1648
b5e50c3f
JB		 1649static int i915_fbc_status(struct seq_file *m, void *unused)
1650{
9f25d007 1651 struct drm_info_node *node = m->private;
b5e50c3f 1652 struct drm_device *dev = node->minor->dev;
fac5e23e 1653 struct drm_i915_private *dev_priv = to_i915(dev);
b5e50c3f 1654
3a77c4c4 1655 if (!HAS_FBC(dev)) {
267f0c90 1656 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1657 return 0;
1658 }
1659
36623ef8 1660 intel_runtime_pm_get(dev_priv);
25ad93fd 1661 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1662
0e631adc 1663 if (intel_fbc_is_active(dev_priv))
267f0c90 1664 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1665 else
1666 seq_printf(m, "FBC disabled: %s\n",
bf6189c6 1667 dev_priv->fbc.no_fbc_reason);
36623ef8 1668
31b9df10
PZ		 1669 if (INTEL_INFO(dev_priv)->gen >= 7)
1670 seq_printf(m, "Compressing: %s\n",
1671 yesno(I915_READ(FBC_STATUS2) &
1672 FBC_COMPRESSION_MASK));
1673
25ad93fd 1674 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1675 intel_runtime_pm_put(dev_priv);
1676
b5e50c3f
JB		 1677 return 0;
1678}
1679
da46f936
RV		 1680static int i915_fbc_fc_get(void *data, u64 *val)
1681{
1682 struct drm_device *dev = data;
fac5e23e 1683 struct drm_i915_private *dev_priv = to_i915(dev);
da46f936
RV		 1684
1685 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1686 return -ENODEV;
1687
da46f936 1688 *val = dev_priv->fbc.false_color;
da46f936
RV		 1689
1690 return 0;
1691}
1692
1693static int i915_fbc_fc_set(void *data, u64 val)
1694{
1695 struct drm_device *dev = data;
fac5e23e 1696 struct drm_i915_private *dev_priv = to_i915(dev);
da46f936
RV		 1697 u32 reg;
1698
1699 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1700 return -ENODEV;
1701
25ad93fd 1702 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1703
1704 reg = I915_READ(ILK_DPFC_CONTROL);
1705 dev_priv->fbc.false_color = val;
1706
1707 I915_WRITE(ILK_DPFC_CONTROL, val ?
1708 (reg | FBC_CTL_FALSE_COLOR) :
1709 (reg & ~FBC_CTL_FALSE_COLOR));
1710
25ad93fd 1711 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1712 return 0;
1713}
1714
1715DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1716 i915_fbc_fc_get, i915_fbc_fc_set,
1717 "%llu\n");
1718
92d44621
PZ		 1719static int i915_ips_status(struct seq_file *m, void *unused)
1720{
9f25d007 1721 struct drm_info_node *node = m->private;
92d44621 1722 struct drm_device *dev = node->minor->dev;
fac5e23e 1723 struct drm_i915_private *dev_priv = to_i915(dev);
92d44621 1724
f5adf94e 1725 if (!HAS_IPS(dev)) {
92d44621
PZ		 1726 seq_puts(m, "not supported\n");
1727 return 0;
1728 }
1729
36623ef8
PZ		 1730 intel_runtime_pm_get(dev_priv);
1731
0eaa53f0
RV		 1732 seq_printf(m, "Enabled by kernel parameter: %s\n",
1733 yesno(i915.enable_ips));
1734
1735 if (INTEL_INFO(dev)->gen >= 8) {
1736 seq_puts(m, "Currently: unknown\n");
1737 } else {
1738 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1739 seq_puts(m, "Currently: enabled\n");
1740 else
1741 seq_puts(m, "Currently: disabled\n");
1742 }
92d44621 1743
36623ef8
PZ		 1744 intel_runtime_pm_put(dev_priv);
1745
92d44621
PZ		 1746 return 0;
1747}
1748
4a9bef37
JB		 1749static int i915_sr_status(struct seq_file *m, void *unused)
1750{
9f25d007 1751 struct drm_info_node *node = m->private;
4a9bef37 1752 struct drm_device *dev = node->minor->dev;
fac5e23e 1753 struct drm_i915_private *dev_priv = to_i915(dev);
4a9bef37
JB		 1754 bool sr_enabled = false;
1755
36623ef8
PZ		 1756 intel_runtime_pm_get(dev_priv);
1757
1398261a 1758 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1759 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1760 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1761 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1762 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1763 else if (IS_I915GM(dev))
1764 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1765 else if (IS_PINEVIEW(dev))
1766 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
666a4537 1767 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
77b64555 1768 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1769
36623ef8
PZ		 1770 intel_runtime_pm_put(dev_priv);
1771
5ba2aaaa
CW		 1772 seq_printf(m, "self-refresh: %s\n",
1773 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1774
1775 return 0;
1776}
1777
7648fa99
JB		 1778static int i915_emon_status(struct seq_file *m, void *unused)
1779{
9f25d007 1780 struct drm_info_node *node = m->private;
7648fa99 1781 struct drm_device *dev = node->minor->dev;
fac5e23e 1782 struct drm_i915_private *dev_priv = to_i915(dev);
7648fa99 1783 unsigned long temp, chipset, gfx;
de227ef0
CW		 1784 int ret;
1785
582be6b4
CW		 1786 if (!IS_GEN5(dev))
1787 return -ENODEV;
1788
de227ef0
CW		 1789 ret = mutex_lock_interruptible(&dev->struct_mutex);
1790 if (ret)
1791 return ret;
7648fa99
JB		 1792
1793 temp = i915_mch_val(dev_priv);
1794 chipset = i915_chipset_val(dev_priv);
1795 gfx = i915_gfx_val(dev_priv);
de227ef0 1796 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1797
1798 seq_printf(m, "GMCH temp: %ld\n", temp);
1799 seq_printf(m, "Chipset power: %ld\n", chipset);
1800 seq_printf(m, "GFX power: %ld\n", gfx);
1801 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1802
1803 return 0;
1804}
1805
23b2f8bb
JB		 1806static int i915_ring_freq_table(struct seq_file *m, void *unused)
1807{
9f25d007 1808 struct drm_info_node *node = m->private;
23b2f8bb 1809 struct drm_device *dev = node->minor->dev;
fac5e23e 1810 struct drm_i915_private *dev_priv = to_i915(dev);
5bfa0199 1811 int ret = 0;
23b2f8bb 1812 int gpu_freq, ia_freq;
f936ec34 1813 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1814
97d3308a 1815 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1816 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1817 return 0;
1818 }
1819
5bfa0199
PZ		 1820 intel_runtime_pm_get(dev_priv);
1821
4fc688ce 1822 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1823 if (ret)
5bfa0199 1824 goto out;
23b2f8bb 1825
ef11bdb3 1826 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
f936ec34
AG		 1827 /* Convert GT frequency to 50 HZ units */
1828 min_gpu_freq =
1829 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1830 max_gpu_freq =
1831 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1832 } else {
1833 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1834 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1835 }
1836
267f0c90 1837 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1838
f936ec34 1839 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1840 ia_freq = gpu_freq;
1841 sandybridge_pcode_read(dev_priv,
1842 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1843 &ia_freq);
3ebecd07 1844 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34 1845 intel_gpu_freq(dev_priv, (gpu_freq *
ef11bdb3
RV		 1846 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1847 GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1848 ((ia_freq >> 0) & 0xff) * 100,
1849 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1850 }
1851
4fc688ce 1852 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1853
5bfa0199
PZ		 1854out:
1855 intel_runtime_pm_put(dev_priv);
1856 return ret;
23b2f8bb
JB		 1857}
1858
44834a67
CW		 1859static int i915_opregion(struct seq_file *m, void *unused)
1860{
9f25d007 1861 struct drm_info_node *node = m->private;
44834a67 1862 struct drm_device *dev = node->minor->dev;
fac5e23e 1863 struct drm_i915_private *dev_priv = to_i915(dev);
44834a67
CW		 1864 struct intel_opregion *opregion = &dev_priv->opregion;
1865 int ret;
1866
1867 ret = mutex_lock_interruptible(&dev->struct_mutex);
1868 if (ret)
0d38f009 1869 goto out;
44834a67 1870
2455a8e4
JN		 1871 if (opregion->header)
1872 seq_write(m, opregion->header, OPREGION_SIZE);
44834a67
CW		 1873
1874 mutex_unlock(&dev->struct_mutex);
1875
0d38f009 1876out:
44834a67
CW		 1877 return 0;
1878}
1879
ada8f955
JN		 1880static int i915_vbt(struct seq_file *m, void *unused)
1881{
1882 struct drm_info_node *node = m->private;
1883 struct drm_device *dev = node->minor->dev;
fac5e23e 1884 struct drm_i915_private *dev_priv = to_i915(dev);
ada8f955
JN		 1885 struct intel_opregion *opregion = &dev_priv->opregion;
1886
1887 if (opregion->vbt)
1888 seq_write(m, opregion->vbt, opregion->vbt_size);
1889
1890 return 0;
1891}
1892
37811fcc
CW		 1893static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1894{
9f25d007 1895 struct drm_info_node *node = m->private;
37811fcc 1896 struct drm_device *dev = node->minor->dev;
b13b8402 1897 struct intel_framebuffer *fbdev_fb = NULL;
3a58ee10 1898 struct drm_framebuffer *drm_fb;
188c1ab7
CW		 1899 int ret;
1900
1901 ret = mutex_lock_interruptible(&dev->struct_mutex);
1902 if (ret)
1903 return ret;
37811fcc 1904
0695726e 1905#ifdef CONFIG_DRM_FBDEV_EMULATION
25bcce94
CW		 1906 if (to_i915(dev)->fbdev) {
1907 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1908
1909 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1910 fbdev_fb->base.width,
1911 fbdev_fb->base.height,
1912 fbdev_fb->base.depth,
1913 fbdev_fb->base.bits_per_pixel,
1914 fbdev_fb->base.modifier[0],
1915 drm_framebuffer_read_refcount(&fbdev_fb->base));
1916 describe_obj(m, fbdev_fb->obj);
1917 seq_putc(m, '\n');
1918 }
4520f53a 1919#endif
37811fcc 1920
4b096ac1 1921 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10 1922 drm_for_each_fb(drm_fb, dev) {
b13b8402
NS		 1923 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1924 if (fb == fbdev_fb)
37811fcc
CW		 1925 continue;
1926
c1ca506d 1927 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1928 fb->base.width,
1929 fb->base.height,
1930 fb->base.depth,
623f9783 1931 fb->base.bits_per_pixel,
c1ca506d 1932 fb->base.modifier[0],
747a598f 1933 drm_framebuffer_read_refcount(&fb->base));
05394f39 1934 describe_obj(m, fb->obj);
267f0c90 1935 seq_putc(m, '\n');
37811fcc 1936 }
4b096ac1 1937 mutex_unlock(&dev->mode_config.fb_lock);
188c1ab7 1938 mutex_unlock(&dev->struct_mutex);
37811fcc
CW		 1939
1940 return 0;
1941}
1942
7e37f889 1943static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
c9fe99bd
OM		 1944{
1945 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
7e37f889
CW		 1946 ring->space, ring->head, ring->tail,
1947 ring->last_retired_head);
c9fe99bd
OM		 1948}
1949
e76d3630
BW		 1950static int i915_context_status(struct seq_file *m, void *unused)
1951{
9f25d007 1952 struct drm_info_node *node = m->private;
e76d3630 1953 struct drm_device *dev = node->minor->dev;
fac5e23e 1954 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 1955 struct intel_engine_cs *engine;
e2efd130 1956 struct i915_gem_context *ctx;
c3232b18 1957 int ret;
e76d3630 1958
f3d28878 1959 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1960 if (ret)
1961 return ret;
1962
a33afea5 1963 list_for_each_entry(ctx, &dev_priv->context_list, link) {
5d1808ec 1964 seq_printf(m, "HW context %u ", ctx->hw_id);
c84455b4 1965 if (ctx->pid) {
d28b99ab
CW		 1966 struct task_struct *task;
1967
c84455b4 1968 task = get_pid_task(ctx->pid, PIDTYPE_PID);
d28b99ab
CW		 1969 if (task) {
1970 seq_printf(m, "(%s [%d]) ",
1971 task->comm, task->pid);
1972 put_task_struct(task);
1973 }
c84455b4
CW		 1974 } else if (IS_ERR(ctx->file_priv)) {
1975 seq_puts(m, "(deleted) ");
d28b99ab
CW		 1976 } else {
1977 seq_puts(m, "(kernel) ");
1978 }
1979
bca44d80
CW		 1980 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1981 seq_putc(m, '\n');
c9fe99bd 1982
bca44d80
CW		 1983 for_each_engine(engine, dev_priv) {
1984 struct intel_context *ce = &ctx->engine[engine->id];
1985
1986 seq_printf(m, "%s: ", engine->name);
1987 seq_putc(m, ce->initialised ? 'I' : 'i');
1988 if (ce->state)
bf3783e5 1989 describe_obj(m, ce->state->obj);
dca33ecc 1990 if (ce->ring)
7e37f889 1991 describe_ctx_ring(m, ce->ring);
c9fe99bd 1992 seq_putc(m, '\n');
c9fe99bd 1993 }
a33afea5 1994
a33afea5 1995 seq_putc(m, '\n');
a168c293
BW		 1996 }
1997
f3d28878 1998 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1999
2000 return 0;
2001}
2002
064ca1d2 2003static void i915_dump_lrc_obj(struct seq_file *m,
e2efd130 2004 struct i915_gem_context *ctx,
0bc40be8 2005 struct intel_engine_cs *engine)
064ca1d2 2006{
bf3783e5 2007 struct i915_vma *vma = ctx->engine[engine->id].state;
064ca1d2 2008 struct page *page;
064ca1d2 2009 int j;
064ca1d2 2010
7069b144
CW		 2011 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2012
bf3783e5
CW		 2013 if (!vma) {
2014 seq_puts(m, "\tFake context\n");
064ca1d2
TD		 2015 return;
2016 }
2017
bf3783e5
CW		 2018 if (vma->flags & I915_VMA_GLOBAL_BIND)
2019 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
bde13ebd 2020 i915_ggtt_offset(vma));
064ca1d2 2021
bf3783e5
CW		 2022 if (i915_gem_object_get_pages(vma->obj)) {
2023 seq_puts(m, "\tFailed to get pages for context object\n\n");
064ca1d2
TD		 2024 return;
2025 }
2026
bf3783e5
CW		 2027 page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2028 if (page) {
2029 u32 *reg_state = kmap_atomic(page);
064ca1d2
TD		 2030
2031 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
bf3783e5
CW		 2032 seq_printf(m,
2033 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2034 j * 4,
064ca1d2
TD		 2035 reg_state[j], reg_state[j + 1],
2036 reg_state[j + 2], reg_state[j + 3]);
2037 }
2038 kunmap_atomic(reg_state);
2039 }
2040
2041 seq_putc(m, '\n');
2042}
2043
c0ab1ae9
BW		 2044static int i915_dump_lrc(struct seq_file *m, void *unused)
2045{
2046 struct drm_info_node *node = (struct drm_info_node *) m->private;
2047 struct drm_device *dev = node->minor->dev;
fac5e23e 2048 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 2049 struct intel_engine_cs *engine;
e2efd130 2050 struct i915_gem_context *ctx;
b4ac5afc 2051 int ret;
c0ab1ae9
BW		 2052
2053 if (!i915.enable_execlists) {
2054 seq_printf(m, "Logical Ring Contexts are disabled\n");
2055 return 0;
2056 }
2057
2058 ret = mutex_lock_interruptible(&dev->struct_mutex);
2059 if (ret)
2060 return ret;
2061
e28e404c 2062 list_for_each_entry(ctx, &dev_priv->context_list, link)
24f1d3cc
CW		 2063 for_each_engine(engine, dev_priv)
2064 i915_dump_lrc_obj(m, ctx, engine);
c0ab1ae9
BW		 2065
2066 mutex_unlock(&dev->struct_mutex);
2067
2068 return 0;
2069}
2070
4ba70e44
OM		 2071static int i915_execlists(struct seq_file *m, void *data)
2072{
2073 struct drm_info_node *node = (struct drm_info_node *)m->private;
2074 struct drm_device *dev = node->minor->dev;
fac5e23e 2075 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 2076 struct intel_engine_cs *engine;
4ba70e44
OM		 2077 u32 status_pointer;
2078 u8 read_pointer;
2079 u8 write_pointer;
2080 u32 status;
2081 u32 ctx_id;
2082 struct list_head *cursor;
b4ac5afc 2083 int i, ret;
4ba70e44
OM		 2084
2085 if (!i915.enable_execlists) {
2086 seq_puts(m, "Logical Ring Contexts are disabled\n");
2087 return 0;
2088 }
2089
2090 ret = mutex_lock_interruptible(&dev->struct_mutex);
2091 if (ret)
2092 return ret;
2093
fc0412ec
MT		 2094 intel_runtime_pm_get(dev_priv);
2095
b4ac5afc 2096 for_each_engine(engine, dev_priv) {
6d3d8274 2097 struct drm_i915_gem_request *head_req = NULL;
4ba70e44 2098 int count = 0;
4ba70e44 2099
e2f80391 2100 seq_printf(m, "%s\n", engine->name);
4ba70e44 2101
e2f80391
TU		 2102 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2103 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
4ba70e44
OM		 2104 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2105 status, ctx_id);
2106
e2f80391 2107 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
4ba70e44
OM		 2108 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2109
e2f80391 2110 read_pointer = engine->next_context_status_buffer;
5590a5f0 2111 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
4ba70e44 2112 if (read_pointer > write_pointer)
5590a5f0 2113 write_pointer += GEN8_CSB_ENTRIES;
4ba70e44
OM		 2114 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2115 read_pointer, write_pointer);
2116
5590a5f0 2117 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
e2f80391
TU		 2118 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2119 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
4ba70e44
OM		 2120
2121 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2122 i, status, ctx_id);
2123 }
2124
27af5eea 2125 spin_lock_bh(&engine->execlist_lock);
e2f80391 2126 list_for_each(cursor, &engine->execlist_queue)
4ba70e44 2127 count++;
e2f80391
TU		 2128 head_req = list_first_entry_or_null(&engine->execlist_queue,
2129 struct drm_i915_gem_request,
2130 execlist_link);
27af5eea 2131 spin_unlock_bh(&engine->execlist_lock);
4ba70e44
OM		 2132
2133 seq_printf(m, "\t%d requests in queue\n", count);
2134 if (head_req) {
7069b144
CW		 2135 seq_printf(m, "\tHead request context: %u\n",
2136 head_req->ctx->hw_id);
4ba70e44 2137 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2138 head_req->tail);
4ba70e44
OM		 2139 }
2140
2141 seq_putc(m, '\n');
2142 }
2143
fc0412ec 2144 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2145 mutex_unlock(&dev->struct_mutex);
2146
2147 return 0;
2148}
2149
ea16a3cd
DV		 2150static const char *swizzle_string(unsigned swizzle)
2151{
aee56cff 2152 switch (swizzle) {
ea16a3cd
DV		 2153 case I915_BIT_6_SWIZZLE_NONE:
2154 return "none";
2155 case I915_BIT_6_SWIZZLE_9:
2156 return "bit9";
2157 case I915_BIT_6_SWIZZLE_9_10:
2158 return "bit9/bit10";
2159 case I915_BIT_6_SWIZZLE_9_11:
2160 return "bit9/bit11";
2161 case I915_BIT_6_SWIZZLE_9_10_11:
2162 return "bit9/bit10/bit11";
2163 case I915_BIT_6_SWIZZLE_9_17:
2164 return "bit9/bit17";
2165 case I915_BIT_6_SWIZZLE_9_10_17:
2166 return "bit9/bit10/bit17";
2167 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2168 return "unknown";
ea16a3cd
DV		 2169 }
2170
2171 return "bug";
2172}
2173
2174static int i915_swizzle_info(struct seq_file *m, void *data)
2175{
9f25d007 2176 struct drm_info_node *node = m->private;
ea16a3cd 2177 struct drm_device *dev = node->minor->dev;
fac5e23e 2178 struct drm_i915_private *dev_priv = to_i915(dev);
22bcfc6a
DV		 2179 int ret;
2180
2181 ret = mutex_lock_interruptible(&dev->struct_mutex);
2182 if (ret)
2183 return ret;
c8c8fb33 2184 intel_runtime_pm_get(dev_priv);
ea16a3cd 2185
ea16a3cd
DV		 2186 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2187 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2188 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2189 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2190
2191 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2192 seq_printf(m, "DDC = 0x%08x\n",
2193 I915_READ(DCC));
656bfa3a
DV		 2194 seq_printf(m, "DDC2 = 0x%08x\n",
2195 I915_READ(DCC2));
ea16a3cd
DV		 2196 seq_printf(m, "C0DRB3 = 0x%04x\n",
2197 I915_READ16(C0DRB3));
2198 seq_printf(m, "C1DRB3 = 0x%04x\n",
2199 I915_READ16(C1DRB3));
9d3203e1 2200 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2201 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2202 I915_READ(MAD_DIMM_C0));
2203 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2204 I915_READ(MAD_DIMM_C1));
2205 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2206 I915_READ(MAD_DIMM_C2));
2207 seq_printf(m, "TILECTL = 0x%08x\n",
2208 I915_READ(TILECTL));
5907f5fb 2209 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2210 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2211 I915_READ(GAMTARBMODE));
2212 else
2213 seq_printf(m, "ARB_MODE = 0x%08x\n",
2214 I915_READ(ARB_MODE));
3fa7d235
DV		 2215 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2216 I915_READ(DISP_ARB_CTL));
ea16a3cd 2217 }
656bfa3a
DV		 2218
2219 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2220 seq_puts(m, "L-shaped memory detected\n");
2221
c8c8fb33 2222 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2223 mutex_unlock(&dev->struct_mutex);
2224
2225 return 0;
2226}
2227
1c60fef5
BW		 2228static int per_file_ctx(int id, void *ptr, void *data)
2229{
e2efd130 2230 struct i915_gem_context *ctx = ptr;
1c60fef5 2231 struct seq_file *m = data;
ae6c4806
DV		 2232 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2233
2234 if (!ppgtt) {
2235 seq_printf(m, " no ppgtt for context %d\n",
2236 ctx->user_handle);
2237 return 0;
2238 }
1c60fef5 2239
f83d6518
OM		 2240 if (i915_gem_context_is_default(ctx))
2241 seq_puts(m, " default context:\n");
2242 else
821d66dd 2243 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2244 ppgtt->debug_dump(ppgtt, m);
2245
2246 return 0;
2247}
2248
77df6772 2249static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2250{
fac5e23e 2251 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 2252 struct intel_engine_cs *engine;
77df6772 2253 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
b4ac5afc 2254 int i;
3cf17fc5 2255
77df6772
BW		 2256 if (!ppgtt)
2257 return;
2258
b4ac5afc 2259 for_each_engine(engine, dev_priv) {
e2f80391 2260 seq_printf(m, "%s\n", engine->name);
77df6772 2261 for (i = 0; i < 4; i++) {
e2f80391 2262 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
77df6772 2263 pdp <<= 32;
e2f80391 2264 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
a2a5b15c 2265 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2266 }
2267 }
2268}
2269
2270static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2271{
fac5e23e 2272 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 2273 struct intel_engine_cs *engine;
3cf17fc5 2274
7e22dbbb 2275 if (IS_GEN6(dev_priv))
3cf17fc5
DV		 2276 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2277
b4ac5afc 2278 for_each_engine(engine, dev_priv) {
e2f80391 2279 seq_printf(m, "%s\n", engine->name);
7e22dbbb 2280 if (IS_GEN7(dev_priv))
e2f80391
TU		 2281 seq_printf(m, "GFX_MODE: 0x%08x\n",
2282 I915_READ(RING_MODE_GEN7(engine)));
2283 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2284 I915_READ(RING_PP_DIR_BASE(engine)));
2285 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2286 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2287 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2288 I915_READ(RING_PP_DIR_DCLV(engine)));
3cf17fc5
DV		 2289 }
2290 if (dev_priv->mm.aliasing_ppgtt) {
2291 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2292
267f0c90 2293 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2294 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2295
87d60b63 2296 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2297 }
1c60fef5 2298
3cf17fc5 2299 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2300}
2301
2302static int i915_ppgtt_info(struct seq_file *m, void *data)
2303{
9f25d007 2304 struct drm_info_node *node = m->private;
77df6772 2305 struct drm_device *dev = node->minor->dev;
fac5e23e 2306 struct drm_i915_private *dev_priv = to_i915(dev);
ea91e401 2307 struct drm_file *file;
77df6772
BW		 2308
2309 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2310 if (ret)
2311 return ret;
c8c8fb33 2312 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2313
2314 if (INTEL_INFO(dev)->gen >= 8)
2315 gen8_ppgtt_info(m, dev);
2316 else if (INTEL_INFO(dev)->gen >= 6)
2317 gen6_ppgtt_info(m, dev);
2318
1d2ac403 2319 mutex_lock(&dev->filelist_mutex);
ea91e401
MT		 2320 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2321 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2322 struct task_struct *task;
ea91e401 2323
7cb5dff8 2324 task = get_pid_task(file->pid, PIDTYPE_PID);
06812760
DC		 2325 if (!task) {
2326 ret = -ESRCH;
b0212486 2327 goto out_unlock;
06812760 2328 }
7cb5dff8
GT		 2329 seq_printf(m, "\nproc: %s\n", task->comm);
2330 put_task_struct(task);
ea91e401
MT		 2331 idr_for_each(&file_priv->context_idr, per_file_ctx,
2332 (void *)(unsigned long)m);
2333 }
b0212486 2334out_unlock:
1d2ac403 2335 mutex_unlock(&dev->filelist_mutex);
ea91e401 2336
c8c8fb33 2337 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2338 mutex_unlock(&dev->struct_mutex);
2339
06812760 2340 return ret;
3cf17fc5
DV		 2341}
2342
f5a4c67d
CW		 2343static int count_irq_waiters(struct drm_i915_private *i915)
2344{
e2f80391 2345 struct intel_engine_cs *engine;
f5a4c67d 2346 int count = 0;
f5a4c67d 2347
b4ac5afc 2348 for_each_engine(engine, i915)
688e6c72 2349 count += intel_engine_has_waiter(engine);
f5a4c67d
CW		 2350
2351 return count;
2352}
2353
7466c291
CW		 2354static const char *rps_power_to_str(unsigned int power)
2355{
2356 static const char * const strings[] = {
2357 [LOW_POWER] = "low power",
2358 [BETWEEN] = "mixed",
2359 [HIGH_POWER] = "high power",
2360 };
2361
2362 if (power >= ARRAY_SIZE(strings) || !strings[power])
2363 return "unknown";
2364
2365 return strings[power];
2366}
2367
1854d5ca
CW		 2368static int i915_rps_boost_info(struct seq_file *m, void *data)
2369{
2370 struct drm_info_node *node = m->private;
2371 struct drm_device *dev = node->minor->dev;
fac5e23e 2372 struct drm_i915_private *dev_priv = to_i915(dev);
1854d5ca 2373 struct drm_file *file;
1854d5ca 2374
f5a4c67d 2375 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
67d97da3
CW		 2376 seq_printf(m, "GPU busy? %s [%x]\n",
2377 yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
f5a4c67d 2378 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
7466c291
CW		 2379 seq_printf(m, "Frequency requested %d\n",
2380 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2381 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
f5a4c67d
CW		 2382 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2383 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2384 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2385 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
7466c291
CW		 2386 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
2387 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2388 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2389 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1d2ac403
DV		 2390
2391 mutex_lock(&dev->filelist_mutex);
8d3afd7d 2392 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2393 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2394 struct drm_i915_file_private *file_priv = file->driver_priv;
2395 struct task_struct *task;
2396
2397 rcu_read_lock();
2398 task = pid_task(file->pid, PIDTYPE_PID);
2399 seq_printf(m, "%s [%d]: %d boosts%s\n",
2400 task ? task->comm : "<unknown>",
2401 task ? task->pid : -1,
2e1b8730
CW		 2402 file_priv->rps.boosts,
2403 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2404 rcu_read_unlock();
2405 }
197be2ae 2406 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2407 spin_unlock(&dev_priv->rps.client_lock);
1d2ac403 2408 mutex_unlock(&dev->filelist_mutex);
1854d5ca 2409
7466c291
CW		 2410 if (INTEL_GEN(dev_priv) >= 6 &&
2411 dev_priv->rps.enabled &&
2412 dev_priv->gt.active_engines) {
2413 u32 rpup, rpupei;
2414 u32 rpdown, rpdownei;
2415
2416 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2417 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2418 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2419 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2420 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2421 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2422
2423 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2424 rps_power_to_str(dev_priv->rps.power));
2425 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
2426 100 * rpup / rpupei,
2427 dev_priv->rps.up_threshold);
2428 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
2429 100 * rpdown / rpdownei,
2430 dev_priv->rps.down_threshold);
2431 } else {
2432 seq_puts(m, "\nRPS Autotuning inactive\n");
2433 }
2434
8d3afd7d 2435 return 0;
1854d5ca
CW		 2436}
2437
63573eb7
BW		 2438static int i915_llc(struct seq_file *m, void *data)
2439{
9f25d007 2440 struct drm_info_node *node = m->private;
63573eb7 2441 struct drm_device *dev = node->minor->dev;
fac5e23e 2442 struct drm_i915_private *dev_priv = to_i915(dev);
3accaf7e 2443 const bool edram = INTEL_GEN(dev_priv) > 8;
63573eb7 2444
63573eb7 2445 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
3accaf7e
MK		 2446 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2447 intel_uncore_edram_size(dev_priv)/1024/1024);
63573eb7
BW		 2448
2449 return 0;
2450}
2451
fdf5d357
AD		 2452static int i915_guc_load_status_info(struct seq_file *m, void *data)
2453{
2454 struct drm_info_node *node = m->private;
fac5e23e 2455 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
fdf5d357
AD		 2456 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2457 u32 tmp, i;
2458
2d1fe073 2459 if (!HAS_GUC_UCODE(dev_priv))
fdf5d357
AD		 2460 return 0;
2461
2462 seq_printf(m, "GuC firmware status:\n");
2463 seq_printf(m, "\tpath: %s\n",
2464 guc_fw->guc_fw_path);
2465 seq_printf(m, "\tfetch: %s\n",
2466 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2467 seq_printf(m, "\tload: %s\n",
2468 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2469 seq_printf(m, "\tversion wanted: %d.%d\n",
2470 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2471 seq_printf(m, "\tversion found: %d.%d\n",
2472 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
feda33ef
AD		 2473 seq_printf(m, "\theader: offset is %d; size = %d\n",
2474 guc_fw->header_offset, guc_fw->header_size);
2475 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2476 guc_fw->ucode_offset, guc_fw->ucode_size);
2477 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2478 guc_fw->rsa_offset, guc_fw->rsa_size);
fdf5d357
AD		 2479
2480 tmp = I915_READ(GUC_STATUS);
2481
2482 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2483 seq_printf(m, "\tBootrom status = 0x%x\n",
2484 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2485 seq_printf(m, "\tuKernel status = 0x%x\n",
2486 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2487 seq_printf(m, "\tMIA Core status = 0x%x\n",
2488 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2489 seq_puts(m, "\nScratch registers:\n");
2490 for (i = 0; i < 16; i++)
2491 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2492
2493 return 0;
2494}
2495
8b417c26
DG		 2496static void i915_guc_client_info(struct seq_file *m,
2497 struct drm_i915_private *dev_priv,
2498 struct i915_guc_client *client)
2499{
e2f80391 2500 struct intel_engine_cs *engine;
c18468c4 2501 enum intel_engine_id id;
8b417c26 2502 uint64_t tot = 0;
8b417c26
DG		 2503
2504 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2505 client->priority, client->ctx_index, client->proc_desc_offset);
2506 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2507 client->doorbell_id, client->doorbell_offset, client->cookie);
2508 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2509 client->wq_size, client->wq_offset, client->wq_tail);
2510
551aaecd 2511 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
8b417c26
DG		 2512 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2513 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2514
c18468c4
DG		 2515 for_each_engine_id(engine, dev_priv, id) {
2516 u64 submissions = client->submissions[id];
2517 tot += submissions;
8b417c26 2518 seq_printf(m, "\tSubmissions: %llu %s\n",
c18468c4 2519 submissions, engine->name);
8b417c26
DG		 2520 }
2521 seq_printf(m, "\tTotal: %llu\n", tot);
2522}
2523
2524static int i915_guc_info(struct seq_file *m, void *data)
2525{
2526 struct drm_info_node *node = m->private;
2527 struct drm_device *dev = node->minor->dev;
fac5e23e 2528 struct drm_i915_private *dev_priv = to_i915(dev);
8b417c26 2529 struct intel_guc guc;
0a0b457f 2530 struct i915_guc_client client = {};
e2f80391 2531 struct intel_engine_cs *engine;
c18468c4 2532 enum intel_engine_id id;
8b417c26
DG		 2533 u64 total = 0;
2534
2d1fe073 2535 if (!HAS_GUC_SCHED(dev_priv))
8b417c26
DG		 2536 return 0;
2537
5a843307
AD		 2538 if (mutex_lock_interruptible(&dev->struct_mutex))
2539 return 0;
2540
8b417c26 2541 /* Take a local copy of the GuC data, so we can dump it at leisure */
8b417c26 2542 guc = dev_priv->guc;
5a843307 2543 if (guc.execbuf_client)
8b417c26 2544 client = *guc.execbuf_client;
5a843307
AD		 2545
2546 mutex_unlock(&dev->struct_mutex);
8b417c26 2547
9636f6db
DG		 2548 seq_printf(m, "Doorbell map:\n");
2549 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2550 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2551
8b417c26
DG		 2552 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2553 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2554 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2555 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2556 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2557
2558 seq_printf(m, "\nGuC submissions:\n");
c18468c4
DG		 2559 for_each_engine_id(engine, dev_priv, id) {
2560 u64 submissions = guc.submissions[id];
2561 total += submissions;
397097b0 2562 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
c18468c4 2563 engine->name, submissions, guc.last_seqno[id]);
8b417c26
DG		 2564 }
2565 seq_printf(m, "\t%s: %llu\n", "Total", total);
2566
2567 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2568 i915_guc_client_info(m, dev_priv, &client);
2569
2570 /* Add more as required ... */
2571
2572 return 0;
2573}
2574
4c7e77fc
AD		 2575static int i915_guc_log_dump(struct seq_file *m, void *data)
2576{
2577 struct drm_info_node *node = m->private;
2578 struct drm_device *dev = node->minor->dev;
fac5e23e 2579 struct drm_i915_private *dev_priv = to_i915(dev);
8b797af1 2580 struct drm_i915_gem_object *obj;
4c7e77fc
AD		 2581 int i = 0, pg;
2582
8b797af1 2583 if (!dev_priv->guc.log_vma)
4c7e77fc
AD		 2584 return 0;
2585
8b797af1
CW		 2586 obj = dev_priv->guc.log_vma->obj;
2587 for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2588 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
4c7e77fc
AD		 2589
2590 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2591 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2592 *(log + i), *(log + i + 1),
2593 *(log + i + 2), *(log + i + 3));
2594
2595 kunmap_atomic(log);
2596 }
2597
2598 seq_putc(m, '\n');
2599
2600 return 0;
2601}
2602
e91fd8c6
RV		 2603static int i915_edp_psr_status(struct seq_file *m, void *data)
2604{
2605 struct drm_info_node *node = m->private;
2606 struct drm_device *dev = node->minor->dev;
fac5e23e 2607 struct drm_i915_private *dev_priv = to_i915(dev);
a031d709 2608 u32 psrperf = 0;
a6cbdb8e
RV		 2609 u32 stat[3];
2610 enum pipe pipe;
a031d709 2611 bool enabled = false;
e91fd8c6 2612
3553a8ea
DL		 2613 if (!HAS_PSR(dev)) {
2614 seq_puts(m, "PSR not supported\n");
2615 return 0;
2616 }
2617
c8c8fb33
PZ		 2618 intel_runtime_pm_get(dev_priv);
2619
fa128fa6 2620 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2621 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2622 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2623 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2624 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2625 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2626 dev_priv->psr.busy_frontbuffer_bits);
2627 seq_printf(m, "Re-enable work scheduled: %s\n",
2628 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2629
3553a8ea 2630 if (HAS_DDI(dev))
443a389f 2631 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
3553a8ea
DL		 2632 else {
2633 for_each_pipe(dev_priv, pipe) {
2634 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2635 VLV_EDP_PSR_CURR_STATE_MASK;
2636 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2637 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2638 enabled = true;
a6cbdb8e
RV		 2639 }
2640 }
60e5ffe3
RV		 2641
2642 seq_printf(m, "Main link in standby mode: %s\n",
2643 yesno(dev_priv->psr.link_standby));
2644
a6cbdb8e
RV		 2645 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2646
2647 if (!HAS_DDI(dev))
2648 for_each_pipe(dev_priv, pipe) {
2649 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2650 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2651 seq_printf(m, " pipe %c", pipe_name(pipe));
2652 }
2653 seq_puts(m, "\n");
e91fd8c6 2654
05eec3c2
RV		 2655 /*
2656 * VLV/CHV PSR has no kind of performance counter
2657 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2658 */
2659 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
443a389f 2660 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
a031d709 2661 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2662
2663 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2664 }
fa128fa6 2665 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2666
c8c8fb33 2667 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2668 return 0;
2669}
2670
d2e216d0
RV		 2671static int i915_sink_crc(struct seq_file *m, void *data)
2672{
2673 struct drm_info_node *node = m->private;
2674 struct drm_device *dev = node->minor->dev;
d2e216d0
RV		 2675 struct intel_connector *connector;
2676 struct intel_dp *intel_dp = NULL;
2677 int ret;
2678 u8 crc[6];
2679
2680 drm_modeset_lock_all(dev);
aca5e361 2681 for_each_intel_connector(dev, connector) {
26c17cf6 2682 struct drm_crtc *crtc;
d2e216d0 2683
26c17cf6 2684 if (!connector->base.state->best_encoder)
d2e216d0
RV		 2685 continue;
2686
26c17cf6
ML		 2687 crtc = connector->base.state->crtc;
2688 if (!crtc->state->active)
b6ae3c7c
PZ		 2689 continue;
2690
26c17cf6 2691 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
d2e216d0
RV		 2692 continue;
2693
26c17cf6 2694 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
d2e216d0
RV		 2695
2696 ret = intel_dp_sink_crc(intel_dp, crc);
2697 if (ret)
2698 goto out;
2699
2700 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2701 crc[0], crc[1], crc[2],
2702 crc[3], crc[4], crc[5]);
2703 goto out;
2704 }
2705 ret = -ENODEV;
2706out:
2707 drm_modeset_unlock_all(dev);
2708 return ret;
2709}
2710
ec013e7f
JB		 2711static int i915_energy_uJ(struct seq_file *m, void *data)
2712{
2713 struct drm_info_node *node = m->private;
2714 struct drm_device *dev = node->minor->dev;
fac5e23e 2715 struct drm_i915_private *dev_priv = to_i915(dev);
ec013e7f
JB		 2716 u64 power;
2717 u32 units;
2718
2719 if (INTEL_INFO(dev)->gen < 6)
2720 return -ENODEV;
2721
36623ef8
PZ		 2722 intel_runtime_pm_get(dev_priv);
2723
ec013e7f
JB		 2724 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2725 power = (power & 0x1f00) >> 8;
2726 units = 1000000 / (1 << power); /* convert to uJ */
2727 power = I915_READ(MCH_SECP_NRG_STTS);
2728 power *= units;
2729
36623ef8
PZ		 2730 intel_runtime_pm_put(dev_priv);
2731
ec013e7f 2732 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2733
2734 return 0;
2735}
2736
6455c870 2737static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2738{
9f25d007 2739 struct drm_info_node *node = m->private;
371db66a 2740 struct drm_device *dev = node->minor->dev;
fac5e23e 2741 struct drm_i915_private *dev_priv = to_i915(dev);
371db66a 2742
a156e64d
CW		 2743 if (!HAS_RUNTIME_PM(dev_priv))
2744 seq_puts(m, "Runtime power management not supported\n");
371db66a 2745
67d97da3 2746 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
371db66a 2747 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2748 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2749#ifdef CONFIG_PM
a6aaec8b
DL		 2750 seq_printf(m, "Usage count: %d\n",
2751 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2752#else
2753 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2754#endif
a156e64d 2755 seq_printf(m, "PCI device power state: %s [%d]\n",
91c8a326
CW		 2756 pci_power_name(dev_priv->drm.pdev->current_state),
2757 dev_priv->drm.pdev->current_state);
371db66a 2758
ec013e7f
JB		 2759 return 0;
2760}
2761
1da51581
ID		 2762static int i915_power_domain_info(struct seq_file *m, void *unused)
2763{
9f25d007 2764 struct drm_info_node *node = m->private;
1da51581 2765 struct drm_device *dev = node->minor->dev;
fac5e23e 2766 struct drm_i915_private *dev_priv = to_i915(dev);
1da51581
ID		 2767 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2768 int i;
2769
2770 mutex_lock(&power_domains->lock);
2771
2772 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2773 for (i = 0; i < power_domains->power_well_count; i++) {
2774 struct i915_power_well *power_well;
2775 enum intel_display_power_domain power_domain;
2776
2777 power_well = &power_domains->power_wells[i];
2778 seq_printf(m, "%-25s %d\n", power_well->name,
2779 power_well->count);
2780
2781 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2782 power_domain++) {
2783 if (!(BIT(power_domain) & power_well->domains))
2784 continue;
2785
2786 seq_printf(m, " %-23s %d\n",
9895ad03 2787 intel_display_power_domain_str(power_domain),
1da51581
ID		 2788 power_domains->domain_use_count[power_domain]);
2789 }
2790 }
2791
2792 mutex_unlock(&power_domains->lock);
2793
2794 return 0;
2795}
2796
b7cec66d
DL		 2797static int i915_dmc_info(struct seq_file *m, void *unused)
2798{
2799 struct drm_info_node *node = m->private;
2800 struct drm_device *dev = node->minor->dev;
fac5e23e 2801 struct drm_i915_private *dev_priv = to_i915(dev);
b7cec66d
DL		 2802 struct intel_csr *csr;
2803
2804 if (!HAS_CSR(dev)) {
2805 seq_puts(m, "not supported\n");
2806 return 0;
2807 }
2808
2809 csr = &dev_priv->csr;
2810
6fb403de
MK		 2811 intel_runtime_pm_get(dev_priv);
2812
b7cec66d
DL		 2813 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2814 seq_printf(m, "path: %s\n", csr->fw_path);
2815
2816 if (!csr->dmc_payload)
6fb403de 2817 goto out;
b7cec66d
DL		 2818
2819 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2820 CSR_VERSION_MINOR(csr->version));
2821
8337206d
DL		 2822 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2823 seq_printf(m, "DC3 -> DC5 count: %d\n",
2824 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2825 seq_printf(m, "DC5 -> DC6 count: %d\n",
2826 I915_READ(SKL_CSR_DC5_DC6_COUNT));
16e11b99
MK		 2827 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2828 seq_printf(m, "DC3 -> DC5 count: %d\n",
2829 I915_READ(BXT_CSR_DC3_DC5_COUNT));
8337206d
DL		 2830 }
2831
6fb403de
MK		 2832out:
2833 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2834 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2835 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2836
8337206d
DL		 2837 intel_runtime_pm_put(dev_priv);
2838
b7cec66d
DL		 2839 return 0;
2840}
2841
53f5e3ca
JB		 2842static void intel_seq_print_mode(struct seq_file *m, int tabs,
2843 struct drm_display_mode *mode)
2844{
2845 int i;
2846
2847 for (i = 0; i < tabs; i++)
2848 seq_putc(m, '\t');
2849
2850 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2851 mode->base.id, mode->name,
2852 mode->vrefresh, mode->clock,
2853 mode->hdisplay, mode->hsync_start,
2854 mode->hsync_end, mode->htotal,
2855 mode->vdisplay, mode->vsync_start,
2856 mode->vsync_end, mode->vtotal,
2857 mode->type, mode->flags);
2858}
2859
2860static void intel_encoder_info(struct seq_file *m,
2861 struct intel_crtc *intel_crtc,
2862 struct intel_encoder *intel_encoder)
2863{
9f25d007 2864 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2865 struct drm_device *dev = node->minor->dev;
2866 struct drm_crtc *crtc = &intel_crtc->base;
2867 struct intel_connector *intel_connector;
2868 struct drm_encoder *encoder;
2869
2870 encoder = &intel_encoder->base;
2871 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2872 encoder->base.id, encoder->name);
53f5e3ca
JB		 2873 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2874 struct drm_connector *connector = &intel_connector->base;
2875 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2876 connector->base.id,
c23cc417 2877 connector->name,
53f5e3ca
JB		 2878 drm_get_connector_status_name(connector->status));
2879 if (connector->status == connector_status_connected) {
2880 struct drm_display_mode *mode = &crtc->mode;
2881 seq_printf(m, ", mode:\n");
2882 intel_seq_print_mode(m, 2, mode);
2883 } else {
2884 seq_putc(m, '\n');
2885 }
2886 }
2887}
2888
2889static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2890{
9f25d007 2891 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2892 struct drm_device *dev = node->minor->dev;
2893 struct drm_crtc *crtc = &intel_crtc->base;
2894 struct intel_encoder *intel_encoder;
23a48d53
ML		 2895 struct drm_plane_state *plane_state = crtc->primary->state;
2896 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2897
23a48d53 2898 if (fb)
5aa8a937 2899 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2900 fb->base.id, plane_state->src_x >> 16,
2901 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2902 else
2903 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2904 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2905 intel_encoder_info(m, intel_crtc, intel_encoder);
2906}
2907
2908static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2909{
2910 struct drm_display_mode *mode = panel->fixed_mode;
2911
2912 seq_printf(m, "\tfixed mode:\n");
2913 intel_seq_print_mode(m, 2, mode);
2914}
2915
2916static void intel_dp_info(struct seq_file *m,
2917 struct intel_connector *intel_connector)
2918{
2919 struct intel_encoder *intel_encoder = intel_connector->encoder;
2920 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2921
2922 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2923 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
b6dabe3b 2924 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
53f5e3ca
JB		 2925 intel_panel_info(m, &intel_connector->panel);
2926}
2927
2928static void intel_hdmi_info(struct seq_file *m,
2929 struct intel_connector *intel_connector)
2930{
2931 struct intel_encoder *intel_encoder = intel_connector->encoder;
2932 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2933
742f491d 2934 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2935}
2936
2937static void intel_lvds_info(struct seq_file *m,
2938 struct intel_connector *intel_connector)
2939{
2940 intel_panel_info(m, &intel_connector->panel);
2941}
2942
2943static void intel_connector_info(struct seq_file *m,
2944 struct drm_connector *connector)
2945{
2946 struct intel_connector *intel_connector = to_intel_connector(connector);
2947 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2948 struct drm_display_mode *mode;
53f5e3ca
JB		 2949
2950 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2951 connector->base.id, connector->name,
53f5e3ca
JB		 2952 drm_get_connector_status_name(connector->status));
2953 if (connector->status == connector_status_connected) {
2954 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2955 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2956 connector->display_info.width_mm,
2957 connector->display_info.height_mm);
2958 seq_printf(m, "\tsubpixel order: %s\n",
2959 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2960 seq_printf(m, "\tCEA rev: %d\n",
2961 connector->display_info.cea_rev);
2962 }
ee648a74
ML		 2963
2964 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2965 return;
2966
2967 switch (connector->connector_type) {
2968 case DRM_MODE_CONNECTOR_DisplayPort:
2969 case DRM_MODE_CONNECTOR_eDP:
2970 intel_dp_info(m, intel_connector);
2971 break;
2972 case DRM_MODE_CONNECTOR_LVDS:
2973 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
36cd7444 2974 intel_lvds_info(m, intel_connector);
ee648a74
ML		 2975 break;
2976 case DRM_MODE_CONNECTOR_HDMIA:
2977 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2978 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2979 intel_hdmi_info(m, intel_connector);
2980 break;
2981 default:
2982 break;
36cd7444 2983 }
53f5e3ca 2984
f103fc7d
JB		 2985 seq_printf(m, "\tmodes:\n");
2986 list_for_each_entry(mode, &connector->modes, head)
2987 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2988}
2989
065f2ec2
CW		 2990static bool cursor_active(struct drm_device *dev, int pipe)
2991{
fac5e23e 2992 struct drm_i915_private *dev_priv = to_i915(dev);
065f2ec2
CW		 2993 u32 state;
2994
2995 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 2996 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
065f2ec2 2997 else
5efb3e28 2998 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2999
3000 return state;
3001}
3002
3003static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3004{
fac5e23e 3005 struct drm_i915_private *dev_priv = to_i915(dev);
065f2ec2
CW		 3006 u32 pos;
3007
5efb3e28 3008 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 3009
3010 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3011 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3012 *x = -*x;
3013
3014 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3015 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3016 *y = -*y;
3017
3018 return cursor_active(dev, pipe);
3019}
3020
3abc4e09
RF		 3021static const char *plane_type(enum drm_plane_type type)
3022{
3023 switch (type) {
3024 case DRM_PLANE_TYPE_OVERLAY:
3025 return "OVL";
3026 case DRM_PLANE_TYPE_PRIMARY:
3027 return "PRI";
3028 case DRM_PLANE_TYPE_CURSOR:
3029 return "CUR";
3030 /*
3031 * Deliberately omitting default: to generate compiler warnings
3032 * when a new drm_plane_type gets added.
3033 */
3034 }
3035
3036 return "unknown";
3037}
3038
3039static const char *plane_rotation(unsigned int rotation)
3040{
3041 static char buf[48];
3042 /*
3043 * According to doc only one DRM_ROTATE_ is allowed but this
3044 * will print them all to visualize if the values are misused
3045 */
3046 snprintf(buf, sizeof(buf),
3047 "%s%s%s%s%s%s(0x%08x)",
31ad61e4
JL		 3048 (rotation & DRM_ROTATE_0) ? "0 " : "",
3049 (rotation & DRM_ROTATE_90) ? "90 " : "",
3050 (rotation & DRM_ROTATE_180) ? "180 " : "",
3051 (rotation & DRM_ROTATE_270) ? "270 " : "",
3052 (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3053 (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3abc4e09
RF		 3054 rotation);
3055
3056 return buf;
3057}
3058
3059static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3060{
3061 struct drm_info_node *node = m->private;
3062 struct drm_device *dev = node->minor->dev;
3063 struct intel_plane *intel_plane;
3064
3065 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3066 struct drm_plane_state *state;
3067 struct drm_plane *plane = &intel_plane->base;
3068
3069 if (!plane->state) {
3070 seq_puts(m, "plane->state is NULL!\n");
3071 continue;
3072 }
3073
3074 state = plane->state;
3075
3076 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3077 plane->base.id,
3078 plane_type(intel_plane->base.type),
3079 state->crtc_x, state->crtc_y,
3080 state->crtc_w, state->crtc_h,
3081 (state->src_x >> 16),
3082 ((state->src_x & 0xffff) * 15625) >> 10,
3083 (state->src_y >> 16),
3084 ((state->src_y & 0xffff) * 15625) >> 10,
3085 (state->src_w >> 16),
3086 ((state->src_w & 0xffff) * 15625) >> 10,
3087 (state->src_h >> 16),
3088 ((state->src_h & 0xffff) * 15625) >> 10,
3089 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3090 plane_rotation(state->rotation));
3091 }
3092}
3093
3094static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3095{
3096 struct intel_crtc_state *pipe_config;
3097 int num_scalers = intel_crtc->num_scalers;
3098 int i;
3099
3100 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3101
3102 /* Not all platformas have a scaler */
3103 if (num_scalers) {
3104 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3105 num_scalers,
3106 pipe_config->scaler_state.scaler_users,
3107 pipe_config->scaler_state.scaler_id);
3108
3109 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3110 struct intel_scaler *sc =
3111 &pipe_config->scaler_state.scalers[i];
3112
3113 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3114 i, yesno(sc->in_use), sc->mode);
3115 }
3116 seq_puts(m, "\n");
3117 } else {
3118 seq_puts(m, "\tNo scalers available on this platform\n");
3119 }
3120}
3121
53f5e3ca
JB		 3122static int i915_display_info(struct seq_file *m, void *unused)
3123{
9f25d007 3124 struct drm_info_node *node = m->private;
53f5e3ca 3125 struct drm_device *dev = node->minor->dev;
fac5e23e 3126 struct drm_i915_private *dev_priv = to_i915(dev);
065f2ec2 3127 struct intel_crtc *crtc;
53f5e3ca
JB		 3128 struct drm_connector *connector;
3129
b0e5ddf3 3130 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 3131 drm_modeset_lock_all(dev);
3132 seq_printf(m, "CRTC info\n");
3133 seq_printf(m, "---------\n");
d3fcc808 3134 for_each_intel_crtc(dev, crtc) {
065f2ec2 3135 bool active;
f77076c9 3136 struct intel_crtc_state *pipe_config;
065f2ec2 3137 int x, y;
53f5e3ca 3138
f77076c9
ML		 3139 pipe_config = to_intel_crtc_state(crtc->base.state);
3140
3abc4e09 3141 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
065f2ec2 3142 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9 3143 yesno(pipe_config->base.active),
3abc4e09
RF		 3144 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3145 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3146
f77076c9 3147 if (pipe_config->base.active) {
065f2ec2
CW		 3148 intel_crtc_info(m, crtc);
3149
a23dc658 3150 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 3151 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 3152 yesno(crtc->cursor_base),
3dd512fb
MR		 3153 x, y, crtc->base.cursor->state->crtc_w,
3154 crtc->base.cursor->state->crtc_h,
57127efa 3155 crtc->cursor_addr, yesno(active));
3abc4e09
RF		 3156 intel_scaler_info(m, crtc);
3157 intel_plane_info(m, crtc);
a23dc658 3158 }
cace841c
DV		 3159
3160 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3161 yesno(!crtc->cpu_fifo_underrun_disabled),
3162 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 3163 }
3164
3165 seq_printf(m, "\n");
3166 seq_printf(m, "Connector info\n");
3167 seq_printf(m, "--------------\n");
3168 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3169 intel_connector_info(m, connector);
3170 }
3171 drm_modeset_unlock_all(dev);
b0e5ddf3 3172 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 3173
3174 return 0;
3175}
3176
e04934cf
BW		 3177static int i915_semaphore_status(struct seq_file *m, void *unused)
3178{
3179 struct drm_info_node *node = (struct drm_info_node *) m->private;
3180 struct drm_device *dev = node->minor->dev;
fac5e23e 3181 struct drm_i915_private *dev_priv = to_i915(dev);
e2f80391 3182 struct intel_engine_cs *engine;
c1bb1145 3183 int num_rings = INTEL_INFO(dev)->num_rings;
c3232b18
DG		 3184 enum intel_engine_id id;
3185 int j, ret;
e04934cf 3186
39df9190 3187 if (!i915.semaphores) {
e04934cf
BW		 3188 seq_puts(m, "Semaphores are disabled\n");
3189 return 0;
3190 }
3191
3192 ret = mutex_lock_interruptible(&dev->struct_mutex);
3193 if (ret)
3194 return ret;
03872064 3195 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 3196
3197 if (IS_BROADWELL(dev)) {
3198 struct page *page;
3199 uint64_t *seqno;
3200
51d545d0 3201 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
e04934cf
BW		 3202
3203 seqno = (uint64_t *)kmap_atomic(page);
c3232b18 3204 for_each_engine_id(engine, dev_priv, id) {
e04934cf
BW		 3205 uint64_t offset;
3206
e2f80391 3207 seq_printf(m, "%s\n", engine->name);
e04934cf
BW		 3208
3209 seq_puts(m, " Last signal:");
3210 for (j = 0; j < num_rings; j++) {
c3232b18 3211 offset = id * I915_NUM_ENGINES + j;
e04934cf
BW		 3212 seq_printf(m, "0x%08llx (0x%02llx) ",
3213 seqno[offset], offset * 8);
3214 }
3215 seq_putc(m, '\n');
3216
3217 seq_puts(m, " Last wait: ");
3218 for (j = 0; j < num_rings; j++) {
c3232b18 3219 offset = id + (j * I915_NUM_ENGINES);
e04934cf
BW		 3220 seq_printf(m, "0x%08llx (0x%02llx) ",
3221 seqno[offset], offset * 8);
3222 }
3223 seq_putc(m, '\n');
3224
3225 }
3226 kunmap_atomic(seqno);
3227 } else {
3228 seq_puts(m, " Last signal:");
b4ac5afc 3229 for_each_engine(engine, dev_priv)
e04934cf
BW		 3230 for (j = 0; j < num_rings; j++)
3231 seq_printf(m, "0x%08x\n",
e2f80391 3232 I915_READ(engine->semaphore.mbox.signal[j]));
e04934cf
BW		 3233 seq_putc(m, '\n');
3234 }
3235
3236 seq_puts(m, "\nSync seqno:\n");
b4ac5afc
DG		 3237 for_each_engine(engine, dev_priv) {
3238 for (j = 0; j < num_rings; j++)
e2f80391
TU		 3239 seq_printf(m, " 0x%08x ",
3240 engine->semaphore.sync_seqno[j]);
e04934cf
BW		 3241 seq_putc(m, '\n');
3242 }
3243 seq_putc(m, '\n');
3244
03872064 3245 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3246 mutex_unlock(&dev->struct_mutex);
3247 return 0;
3248}
3249
728e29d7
DV		 3250static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3251{
3252 struct drm_info_node *node = (struct drm_info_node *) m->private;
3253 struct drm_device *dev = node->minor->dev;
fac5e23e 3254 struct drm_i915_private *dev_priv = to_i915(dev);
728e29d7
DV		 3255 int i;
3256
3257 drm_modeset_lock_all(dev);
3258 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3259 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3260
3261 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2dd66ebd
ML		 3262 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3263 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
728e29d7 3264 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3265 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3266 seq_printf(m, " dpll_md: 0x%08x\n",
3267 pll->config.hw_state.dpll_md);
3268 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3269 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3270 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3271 }
3272 drm_modeset_unlock_all(dev);
3273
3274 return 0;
3275}
3276
1ed1ef9d 3277static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3278{
3279 int i;
3280 int ret;
e2f80391 3281 struct intel_engine_cs *engine;
888b5995
AS		 3282 struct drm_info_node *node = (struct drm_info_node *) m->private;
3283 struct drm_device *dev = node->minor->dev;
fac5e23e 3284 struct drm_i915_private *dev_priv = to_i915(dev);
33136b06 3285 struct i915_workarounds *workarounds = &dev_priv->workarounds;
c3232b18 3286 enum intel_engine_id id;
888b5995 3287
888b5995
AS		 3288 ret = mutex_lock_interruptible(&dev->struct_mutex);
3289 if (ret)
3290 return ret;
3291
3292 intel_runtime_pm_get(dev_priv);
3293
33136b06 3294 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
c3232b18 3295 for_each_engine_id(engine, dev_priv, id)
33136b06 3296 seq_printf(m, "HW whitelist count for %s: %d\n",
c3232b18 3297 engine->name, workarounds->hw_whitelist_count[id]);
33136b06 3298 for (i = 0; i < workarounds->count; ++i) {
f0f59a00
VS		 3299 i915_reg_t addr;
3300 u32 mask, value, read;
2fa60f6d 3301 bool ok;
888b5995 3302
33136b06
AS		 3303 addr = workarounds->reg[i].addr;
3304 mask = workarounds->reg[i].mask;
3305 value = workarounds->reg[i].value;
2fa60f6d
MK		 3306 read = I915_READ(addr);
3307 ok = (value & mask) == (read & mask);
3308 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
f0f59a00 3309 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3310 }
3311
3312 intel_runtime_pm_put(dev_priv);
3313 mutex_unlock(&dev->struct_mutex);
3314
3315 return 0;
3316}
3317
c5511e44
DL		 3318static int i915_ddb_info(struct seq_file *m, void *unused)
3319{
3320 struct drm_info_node *node = m->private;
3321 struct drm_device *dev = node->minor->dev;
fac5e23e 3322 struct drm_i915_private *dev_priv = to_i915(dev);
c5511e44
DL		 3323 struct skl_ddb_allocation *ddb;
3324 struct skl_ddb_entry *entry;
3325 enum pipe pipe;
3326 int plane;
3327
2fcffe19
DL		 3328 if (INTEL_INFO(dev)->gen < 9)
3329 return 0;
3330
c5511e44
DL		 3331 drm_modeset_lock_all(dev);
3332
3333 ddb = &dev_priv->wm.skl_hw.ddb;
3334
3335 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3336
3337 for_each_pipe(dev_priv, pipe) {
3338 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3339
dd740780 3340 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3341 entry = &ddb->plane[pipe][plane];
3342 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3343 entry->start, entry->end,
3344 skl_ddb_entry_size(entry));
3345 }
3346
4969d33e 3347 entry = &ddb->plane[pipe][PLANE_CURSOR];
c5511e44
DL		 3348 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3349 entry->end, skl_ddb_entry_size(entry));
3350 }
3351
3352 drm_modeset_unlock_all(dev);
3353
3354 return 0;
3355}
3356
a54746e3
VK		 3357static void drrs_status_per_crtc(struct seq_file *m,
3358 struct drm_device *dev, struct intel_crtc *intel_crtc)
3359{
fac5e23e 3360 struct drm_i915_private *dev_priv = to_i915(dev);
a54746e3
VK		 3361 struct i915_drrs *drrs = &dev_priv->drrs;
3362 int vrefresh = 0;
26875fe5 3363 struct drm_connector *connector;
a54746e3 3364
26875fe5
ML		 3365 drm_for_each_connector(connector, dev) {
3366 if (connector->state->crtc != &intel_crtc->base)
3367 continue;
3368
3369 seq_printf(m, "%s:\n", connector->name);
a54746e3
VK		 3370 }
3371
3372 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3373 seq_puts(m, "\tVBT: DRRS_type: Static");
3374 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3375 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3376 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3377 seq_puts(m, "\tVBT: DRRS_type: None");
3378 else
3379 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3380
3381 seq_puts(m, "\n\n");
3382
f77076c9 3383 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3384 struct intel_panel *panel;
3385
3386 mutex_lock(&drrs->mutex);
3387 /* DRRS Supported */
3388 seq_puts(m, "\tDRRS Supported: Yes\n");
3389
3390 /* disable_drrs() will make drrs->dp NULL */
3391 if (!drrs->dp) {
3392 seq_puts(m, "Idleness DRRS: Disabled");
3393 mutex_unlock(&drrs->mutex);
3394 return;
3395 }
3396
3397 panel = &drrs->dp->attached_connector->panel;
3398 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3399 drrs->busy_frontbuffer_bits);
3400
3401 seq_puts(m, "\n\t\t");
3402 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3403 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3404 vrefresh = panel->fixed_mode->vrefresh;
3405 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3406 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3407 vrefresh = panel->downclock_mode->vrefresh;
3408 } else {
3409 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3410 drrs->refresh_rate_type);
3411 mutex_unlock(&drrs->mutex);
3412 return;
3413 }
3414 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3415
3416 seq_puts(m, "\n\t\t");
3417 mutex_unlock(&drrs->mutex);
3418 } else {
3419 /* DRRS not supported. Print the VBT parameter*/
3420 seq_puts(m, "\tDRRS Supported : No");
3421 }
3422 seq_puts(m, "\n");
3423}
3424
3425static int i915_drrs_status(struct seq_file *m, void *unused)
3426{
3427 struct drm_info_node *node = m->private;
3428 struct drm_device *dev = node->minor->dev;
3429 struct intel_crtc *intel_crtc;
3430 int active_crtc_cnt = 0;
3431
26875fe5 3432 drm_modeset_lock_all(dev);
a54746e3 3433 for_each_intel_crtc(dev, intel_crtc) {
f77076c9 3434 if (intel_crtc->base.state->active) {
a54746e3
VK		 3435 active_crtc_cnt++;
3436 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3437
3438 drrs_status_per_crtc(m, dev, intel_crtc);
3439 }
a54746e3 3440 }
26875fe5 3441 drm_modeset_unlock_all(dev);
a54746e3
VK		 3442
3443 if (!active_crtc_cnt)
3444 seq_puts(m, "No active crtc found\n");
3445
3446 return 0;
3447}
3448
07144428
DL		 3449struct pipe_crc_info {
3450 const char *name;
3451 struct drm_device *dev;
3452 enum pipe pipe;
3453};
3454
11bed958
DA		 3455static int i915_dp_mst_info(struct seq_file *m, void *unused)
3456{
3457 struct drm_info_node *node = (struct drm_info_node *) m->private;
3458 struct drm_device *dev = node->minor->dev;
11bed958
DA		 3459 struct intel_encoder *intel_encoder;
3460 struct intel_digital_port *intel_dig_port;
b6dabe3b
ML		 3461 struct drm_connector *connector;
3462
11bed958 3463 drm_modeset_lock_all(dev);
b6dabe3b
ML		 3464 drm_for_each_connector(connector, dev) {
3465 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
11bed958 3466 continue;
b6dabe3b
ML		 3467
3468 intel_encoder = intel_attached_encoder(connector);
3469 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3470 continue;
3471
3472 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
11bed958
DA		 3473 if (!intel_dig_port->dp.can_mst)
3474 continue;
b6dabe3b 3475
40ae80cc
JB		 3476 seq_printf(m, "MST Source Port %c\n",
3477 port_name(intel_dig_port->port));
11bed958
DA		 3478 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3479 }
3480 drm_modeset_unlock_all(dev);
3481 return 0;
3482}
3483
07144428
DL		 3484static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3485{
be5c7a90 3486 struct pipe_crc_info *info = inode->i_private;
fac5e23e 3487 struct drm_i915_private *dev_priv = to_i915(info->dev);
be5c7a90
DL		 3488 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3489
7eb1c496
DV		 3490 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3491 return -ENODEV;
3492
d538bbdf
DL		 3493 spin_lock_irq(&pipe_crc->lock);
3494
3495 if (pipe_crc->opened) {
3496 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3497 return -EBUSY; /* already open */
3498 }
3499
d538bbdf 3500 pipe_crc->opened = true;
07144428
DL		 3501 filep->private_data = inode->i_private;
3502
d538bbdf
DL		 3503 spin_unlock_irq(&pipe_crc->lock);
3504
07144428
DL		 3505 return 0;
3506}
3507
3508static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3509{
be5c7a90 3510 struct pipe_crc_info *info = inode->i_private;
fac5e23e 3511 struct drm_i915_private *dev_priv = to_i915(info->dev);
be5c7a90
DL		 3512 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3513
d538bbdf
DL		 3514 spin_lock_irq(&pipe_crc->lock);
3515 pipe_crc->opened = false;
3516 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3517
07144428
DL		 3518 return 0;
3519}
3520
3521/* (6 fields, 8 chars each, space separated (5) + '\n') */
3522#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3523/* account for \'0' */
3524#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3525
3526static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3527{
d538bbdf
DL		 3528 assert_spin_locked(&pipe_crc->lock);
3529 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3530 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3531}
3532
3533static ssize_t
3534i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3535 loff_t *pos)
3536{
3537 struct pipe_crc_info *info = filep->private_data;
3538 struct drm_device *dev = info->dev;
fac5e23e 3539 struct drm_i915_private *dev_priv = to_i915(dev);
07144428
DL		 3540 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3541 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3542 int n_entries;
07144428
DL		 3543 ssize_t bytes_read;
3544
3545 /*
3546 * Don't allow user space to provide buffers not big enough to hold
3547 * a line of data.
3548 */
3549 if (count < PIPE_CRC_LINE_LEN)
3550 return -EINVAL;
3551
3552 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3553 return 0;
07144428
DL		 3554
3555 /* nothing to read */
d538bbdf 3556 spin_lock_irq(&pipe_crc->lock);
07144428 3557 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3558 int ret;
3559
3560 if (filep->f_flags & O_NONBLOCK) {
3561 spin_unlock_irq(&pipe_crc->lock);
07144428 3562 return -EAGAIN;
d538bbdf 3563 }
07144428 3564
d538bbdf
DL		 3565 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3566 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3567 if (ret) {
3568 spin_unlock_irq(&pipe_crc->lock);
3569 return ret;
3570 }
8bf1e9f1
SH		 3571 }
3572
07144428 3573 /* We now have one or more entries to read */
9ad6d99f 3574 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3575
07144428 3576 bytes_read = 0;
9ad6d99f
VS		 3577 while (n_entries > 0) {
3578 struct intel_pipe_crc_entry *entry =
3579 &pipe_crc->entries[pipe_crc->tail];
8bf1e9f1 3580
9ad6d99f
VS		 3581 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3582 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3583 break;
3584
3585 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3586 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3587
07144428
DL		 3588 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3589 "%8u %8x %8x %8x %8x %8x\n",
3590 entry->frame, entry->crc[0],
3591 entry->crc[1], entry->crc[2],
3592 entry->crc[3], entry->crc[4]);
3593
9ad6d99f
VS		 3594 spin_unlock_irq(&pipe_crc->lock);
3595
4e9121e6 3596 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
07144428 3597 return -EFAULT;
b2c88f5b 3598
9ad6d99f
VS		 3599 user_buf += PIPE_CRC_LINE_LEN;
3600 n_entries--;
3601
3602 spin_lock_irq(&pipe_crc->lock);
3603 }
8bf1e9f1 3604
d538bbdf
DL		 3605 spin_unlock_irq(&pipe_crc->lock);
3606
07144428
DL		 3607 return bytes_read;
3608}
3609
3610static const struct file_operations i915_pipe_crc_fops = {
3611 .owner = THIS_MODULE,
3612 .open = i915_pipe_crc_open,
3613 .read = i915_pipe_crc_read,
3614 .release = i915_pipe_crc_release,
3615};
3616
3617static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3618 {
3619 .name = "i915_pipe_A_crc",
3620 .pipe = PIPE_A,
3621 },
3622 {
3623 .name = "i915_pipe_B_crc",
3624 .pipe = PIPE_B,
3625 },
3626 {
3627 .name = "i915_pipe_C_crc",
3628 .pipe = PIPE_C,
3629 },
3630};
3631
3632static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3633 enum pipe pipe)
3634{
3635 struct drm_device *dev = minor->dev;
3636 struct dentry *ent;
3637 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3638
3639 info->dev = dev;
3640 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3641 &i915_pipe_crc_fops);
f3c5fe97
WY		 3642 if (!ent)
3643 return -ENOMEM;
07144428
DL		 3644
3645 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3646}
3647
e8dfcf78 3648static const char * const pipe_crc_sources[] = {
926321d5
DV		 3649 "none",
3650 "plane1",
3651 "plane2",
3652 "pf",
5b3a856b 3653 "pipe",
3d099a05
DV		 3654 "TV",
3655 "DP-B",
3656 "DP-C",
3657 "DP-D",
46a19188 3658 "auto",
926321d5
DV		 3659};
3660
3661static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3662{
3663 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3664 return pipe_crc_sources[source];
3665}
3666
bd9db02f 3667static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3668{
3669 struct drm_device *dev = m->private;
fac5e23e 3670 struct drm_i915_private *dev_priv = to_i915(dev);
926321d5
DV		 3671 int i;
3672
3673 for (i = 0; i < I915_MAX_PIPES; i++)
3674 seq_printf(m, "%c %s\n", pipe_name(i),
3675 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3676
3677 return 0;
3678}
3679
bd9db02f 3680static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3681{
3682 struct drm_device *dev = inode->i_private;
3683
bd9db02f 3684 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3685}
3686
46a19188 3687static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3688 uint32_t *val)
3689{
46a19188
DV		 3690 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3691 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3692
3693 switch (*source) {
52f843f6
DV		 3694 case INTEL_PIPE_CRC_SOURCE_PIPE:
3695 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3696 break;
3697 case INTEL_PIPE_CRC_SOURCE_NONE:
3698 *val = 0;
3699 break;
3700 default:
3701 return -EINVAL;
3702 }
3703
3704 return 0;
3705}
3706
46a19188
DV		 3707static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3708 enum intel_pipe_crc_source *source)
3709{
3710 struct intel_encoder *encoder;
3711 struct intel_crtc *crtc;
26756809 3712 struct intel_digital_port *dig_port;
46a19188
DV		 3713 int ret = 0;
3714
3715 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3716
6e9f798d 3717 drm_modeset_lock_all(dev);
b2784e15 3718 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3719 if (!encoder->base.crtc)
3720 continue;
3721
3722 crtc = to_intel_crtc(encoder->base.crtc);
3723
3724 if (crtc->pipe != pipe)
3725 continue;
3726
3727 switch (encoder->type) {
3728 case INTEL_OUTPUT_TVOUT:
3729 *source = INTEL_PIPE_CRC_SOURCE_TV;
3730 break;
cca0502b 3731 case INTEL_OUTPUT_DP:
46a19188 3732 case INTEL_OUTPUT_EDP:
26756809
DV		 3733 dig_port = enc_to_dig_port(&encoder->base);
3734 switch (dig_port->port) {
3735 case PORT_B:
3736 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3737 break;
3738 case PORT_C:
3739 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3740 break;
3741 case PORT_D:
3742 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3743 break;
3744 default:
3745 WARN(1, "nonexisting DP port %c\n",
3746 port_name(dig_port->port));
3747 break;
3748 }
46a19188 3749 break;
6847d71b
PZ		 3750 default:
3751 break;
46a19188
DV		 3752 }
3753 }
6e9f798d 3754 drm_modeset_unlock_all(dev);
46a19188
DV		 3755
3756 return ret;
3757}
3758
3759static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3760 enum pipe pipe,
3761 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3762 uint32_t *val)
3763{
fac5e23e 3764 struct drm_i915_private *dev_priv = to_i915(dev);
8d2f24ca
DV		 3765 bool need_stable_symbols = false;
3766
46a19188
DV		 3767 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3768 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3769 if (ret)
3770 return ret;
3771 }
3772
3773 switch (*source) {
7ac0129b
DV		 3774 case INTEL_PIPE_CRC_SOURCE_PIPE:
3775 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3776 break;
3777 case INTEL_PIPE_CRC_SOURCE_DP_B:
3778 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3779 need_stable_symbols = true;
7ac0129b
DV		 3780 break;
3781 case INTEL_PIPE_CRC_SOURCE_DP_C:
3782 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3783 need_stable_symbols = true;
7ac0129b 3784 break;
2be57922
VS		 3785 case INTEL_PIPE_CRC_SOURCE_DP_D:
3786 if (!IS_CHERRYVIEW(dev))
3787 return -EINVAL;
3788 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3789 need_stable_symbols = true;
3790 break;
7ac0129b
DV		 3791 case INTEL_PIPE_CRC_SOURCE_NONE:
3792 *val = 0;
3793 break;
3794 default:
3795 return -EINVAL;
3796 }
3797
8d2f24ca
DV		 3798 /*
3799 * When the pipe CRC tap point is after the transcoders we need
3800 * to tweak symbol-level features to produce a deterministic series of
3801 * symbols for a given frame. We need to reset those features only once
3802 * a frame (instead of every nth symbol):
3803 * - DC-balance: used to ensure a better clock recovery from the data
3804 * link (SDVO)
3805 * - DisplayPort scrambling: used for EMI reduction
3806 */
3807 if (need_stable_symbols) {
3808 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3809
8d2f24ca 3810 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3811 switch (pipe) {
3812 case PIPE_A:
8d2f24ca 3813 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3814 break;
3815 case PIPE_B:
8d2f24ca 3816 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3817 break;
3818 case PIPE_C:
3819 tmp |= PIPE_C_SCRAMBLE_RESET;
3820 break;
3821 default:
3822 return -EINVAL;
3823 }
8d2f24ca
DV		 3824 I915_WRITE(PORT_DFT2_G4X, tmp);
3825 }
3826
7ac0129b
DV		 3827 return 0;
3828}
3829
4b79ebf7 3830static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3831 enum pipe pipe,
3832 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3833 uint32_t *val)
3834{
fac5e23e 3835 struct drm_i915_private *dev_priv = to_i915(dev);
84093603
DV		 3836 bool need_stable_symbols = false;
3837
46a19188
DV		 3838 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3839 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3840 if (ret)
3841 return ret;
3842 }
3843
3844 switch (*source) {
4b79ebf7
DV		 3845 case INTEL_PIPE_CRC_SOURCE_PIPE:
3846 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3847 break;
3848 case INTEL_PIPE_CRC_SOURCE_TV:
3849 if (!SUPPORTS_TV(dev))
3850 return -EINVAL;
3851 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3852 break;
3853 case INTEL_PIPE_CRC_SOURCE_DP_B:
3854 if (!IS_G4X(dev))
3855 return -EINVAL;
3856 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3857 need_stable_symbols = true;
4b79ebf7
DV		 3858 break;
3859 case INTEL_PIPE_CRC_SOURCE_DP_C:
3860 if (!IS_G4X(dev))
3861 return -EINVAL;
3862 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3863 need_stable_symbols = true;
4b79ebf7
DV		 3864 break;
3865 case INTEL_PIPE_CRC_SOURCE_DP_D:
3866 if (!IS_G4X(dev))
3867 return -EINVAL;
3868 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3869 need_stable_symbols = true;
4b79ebf7
DV		 3870 break;
3871 case INTEL_PIPE_CRC_SOURCE_NONE:
3872 *val = 0;
3873 break;
3874 default:
3875 return -EINVAL;
3876 }
3877
84093603
DV		 3878 /*
3879 * When the pipe CRC tap point is after the transcoders we need
3880 * to tweak symbol-level features to produce a deterministic series of
3881 * symbols for a given frame. We need to reset those features only once
3882 * a frame (instead of every nth symbol):
3883 * - DC-balance: used to ensure a better clock recovery from the data
3884 * link (SDVO)
3885 * - DisplayPort scrambling: used for EMI reduction
3886 */
3887 if (need_stable_symbols) {
3888 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3889
3890 WARN_ON(!IS_G4X(dev));
3891
3892 I915_WRITE(PORT_DFT_I9XX,
3893 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3894
3895 if (pipe == PIPE_A)
3896 tmp |= PIPE_A_SCRAMBLE_RESET;
3897 else
3898 tmp |= PIPE_B_SCRAMBLE_RESET;
3899
3900 I915_WRITE(PORT_DFT2_G4X, tmp);
3901 }
3902
4b79ebf7
DV		 3903 return 0;
3904}
3905
8d2f24ca
DV		 3906static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3907 enum pipe pipe)
3908{
fac5e23e 3909 struct drm_i915_private *dev_priv = to_i915(dev);
8d2f24ca
DV		 3910 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3911
eb736679
VS		 3912 switch (pipe) {
3913 case PIPE_A:
8d2f24ca 3914 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3915 break;
3916 case PIPE_B:
8d2f24ca 3917 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3918 break;
3919 case PIPE_C:
3920 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3921 break;
3922 default:
3923 return;
3924 }
8d2f24ca
DV		 3925 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3926 tmp &= ~DC_BALANCE_RESET_VLV;
3927 I915_WRITE(PORT_DFT2_G4X, tmp);
3928
3929}
3930
84093603
DV		 3931static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3932 enum pipe pipe)
3933{
fac5e23e 3934 struct drm_i915_private *dev_priv = to_i915(dev);
84093603
DV		 3935 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3936
3937 if (pipe == PIPE_A)
3938 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3939 else
3940 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3941 I915_WRITE(PORT_DFT2_G4X, tmp);
3942
3943 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3944 I915_WRITE(PORT_DFT_I9XX,
3945 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3946 }
3947}
3948
46a19188 3949static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3950 uint32_t *val)
3951{
46a19188
DV		 3952 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3953 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3954
3955 switch (*source) {
5b3a856b
DV		 3956 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3957 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3958 break;
3959 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3960 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3961 break;
5b3a856b
DV		 3962 case INTEL_PIPE_CRC_SOURCE_PIPE:
3963 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3964 break;
3d099a05 3965 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3966 *val = 0;
3967 break;
3d099a05
DV		 3968 default:
3969 return -EINVAL;
5b3a856b
DV		 3970 }
3971
3972 return 0;
3973}
3974
c4e2d043 3975static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51 3976{
fac5e23e 3977 struct drm_i915_private *dev_priv = to_i915(dev);
fabf6e51
DV		 3978 struct intel_crtc *crtc =
3979 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3980 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3981 struct drm_atomic_state *state;
3982 int ret = 0;
fabf6e51
DV		 3983
3984 drm_modeset_lock_all(dev);
c4e2d043
ML		 3985 state = drm_atomic_state_alloc(dev);
3986 if (!state) {
3987 ret = -ENOMEM;
3988 goto out;
fabf6e51 3989 }
fabf6e51 3990
c4e2d043
ML		 3991 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3992 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3993 if (IS_ERR(pipe_config)) {
3994 ret = PTR_ERR(pipe_config);
3995 goto out;
3996 }
fabf6e51 3997
c4e2d043
ML		 3998 pipe_config->pch_pfit.force_thru = enable;
3999 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4000 pipe_config->pch_pfit.enabled != enable)
4001 pipe_config->base.connectors_changed = true;
1b509259 4002
c4e2d043
ML		 4003 ret = drm_atomic_commit(state);
4004out:
fabf6e51 4005 drm_modeset_unlock_all(dev);
c4e2d043
ML		 4006 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4007 if (ret)
4008 drm_atomic_state_free(state);
fabf6e51
DV		 4009}
4010
4011static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4012 enum pipe pipe,
4013 enum intel_pipe_crc_source *source,
5b3a856b
DV		 4014 uint32_t *val)
4015{
46a19188
DV		 4016 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4017 *source = INTEL_PIPE_CRC_SOURCE_PF;
4018
4019 switch (*source) {
5b3a856b
DV		 4020 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4021 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4022 break;
4023 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4024 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4025 break;
4026 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 4027 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4028 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 4029
5b3a856b
DV		 4030 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4031 break;
3d099a05 4032 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 4033 *val = 0;
4034 break;
3d099a05
DV		 4035 default:
4036 return -EINVAL;
5b3a856b
DV		 4037 }
4038
4039 return 0;
4040}
4041
926321d5
DV		 4042static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4043 enum intel_pipe_crc_source source)
4044{
fac5e23e 4045 struct drm_i915_private *dev_priv = to_i915(dev);
cc3da175 4046 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 4047 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4048 pipe));
e129649b 4049 enum intel_display_power_domain power_domain;
432f3342 4050 u32 val = 0; /* shut up gcc */
5b3a856b 4051 int ret;
926321d5 4052
cc3da175
DL		 4053 if (pipe_crc->source == source)
4054 return 0;
4055
ae676fcd
DL		 4056 /* forbid changing the source without going back to 'none' */
4057 if (pipe_crc->source && source)
4058 return -EINVAL;
4059
e129649b
ID		 4060 power_domain = POWER_DOMAIN_PIPE(pipe);
4061 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9d8b0588
DV		 4062 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4063 return -EIO;
4064 }
4065
52f843f6 4066 if (IS_GEN2(dev))
46a19188 4067 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 4068 else if (INTEL_INFO(dev)->gen < 5)
46a19188 4069 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
666a4537 4070 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
fabf6e51 4071 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 4072 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 4073 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 4074 else
fabf6e51 4075 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 4076
4077 if (ret != 0)
e129649b 4078 goto out;
5b3a856b 4079
4b584369
DL		 4080 /* none -> real source transition */
4081 if (source) {
4252fbc3
VS		 4082 struct intel_pipe_crc_entry *entries;
4083
7cd6ccff
DL		 4084 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4085 pipe_name(pipe), pipe_crc_source_name(source));
4086
3cf54b34
VS		 4087 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4088 sizeof(pipe_crc->entries[0]),
4252fbc3 4089 GFP_KERNEL);
e129649b
ID		 4090 if (!entries) {
4091 ret = -ENOMEM;
4092 goto out;
4093 }
e5f75aca 4094
8c740dce
PZ		 4095 /*
4096 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4097 * enabled and disabled dynamically based on package C states,
4098 * user space can't make reliable use of the CRCs, so let's just
4099 * completely disable it.
4100 */
4101 hsw_disable_ips(crtc);
4102
d538bbdf 4103 spin_lock_irq(&pipe_crc->lock);
64387b61 4104 kfree(pipe_crc->entries);
4252fbc3 4105 pipe_crc->entries = entries;
d538bbdf
DL		 4106 pipe_crc->head = 0;
4107 pipe_crc->tail = 0;
4108 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 4109 }
4110
cc3da175 4111 pipe_crc->source = source;
926321d5 4112
926321d5
DV		 4113 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4114 POSTING_READ(PIPE_CRC_CTL(pipe));
4115
e5f75aca
DL		 4116 /* real source -> none transition */
4117 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 4118 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 4119 struct intel_crtc *crtc =
4120 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 4121
7cd6ccff
DL		 4122 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4123 pipe_name(pipe));
4124
a33d7105 4125 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 4126 if (crtc->base.state->active)
a33d7105
DV		 4127 intel_wait_for_vblank(dev, pipe);
4128 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 4129
d538bbdf
DL		 4130 spin_lock_irq(&pipe_crc->lock);
4131 entries = pipe_crc->entries;
e5f75aca 4132 pipe_crc->entries = NULL;
9ad6d99f
VS		 4133 pipe_crc->head = 0;
4134 pipe_crc->tail = 0;
d538bbdf
DL		 4135 spin_unlock_irq(&pipe_crc->lock);
4136
4137 kfree(entries);
84093603
DV		 4138
4139 if (IS_G4X(dev))
4140 g4x_undo_pipe_scramble_reset(dev, pipe);
666a4537 4141 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
8d2f24ca 4142 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 4143 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4144 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 4145
4146 hsw_enable_ips(crtc);
e5f75aca
DL		 4147 }
4148
e129649b
ID		 4149 ret = 0;
4150
4151out:
4152 intel_display_power_put(dev_priv, power_domain);
4153
4154 return ret;
926321d5
DV		 4155}
4156
4157/*
4158 * Parse pipe CRC command strings:
b94dec87
DL		 4159 * command: wsp* object wsp+ name wsp+ source wsp*
4160 * object: 'pipe'
4161 * name: (A | B | C)
926321d5
DV		 4162 * source: (none | plane1 | plane2 | pf)
4163 * wsp: (#0x20 | #0x9 | #0xA)+
4164 *
4165 * eg.:
b94dec87
DL		 4166 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4167 * "pipe A none" -> Stop CRC
926321d5 4168 */
bd9db02f 4169static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 4170{
4171 int n_words = 0;
4172
4173 while (*buf) {
4174 char *end;
4175
4176 /* skip leading white space */
4177 buf = skip_spaces(buf);
4178 if (!*buf)
4179 break; /* end of buffer */
4180
4181 /* find end of word */
4182 for (end = buf; *end && !isspace(*end); end++)
4183 ;
4184
4185 if (n_words == max_words) {
4186 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4187 max_words);
4188 return -EINVAL; /* ran out of words[] before bytes */
4189 }
4190
4191 if (*end)
4192 *end++ = '\0';
4193 words[n_words++] = buf;
4194 buf = end;
4195 }
4196
4197 return n_words;
4198}
4199
b94dec87
DL		 4200enum intel_pipe_crc_object {
4201 PIPE_CRC_OBJECT_PIPE,
4202};
4203
e8dfcf78 4204static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4205 "pipe",
4206};
4207
4208static int
bd9db02f 4209display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4210{
4211 int i;
4212
4213 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4214 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4215 *o = i;
b94dec87
DL		 4216 return 0;
4217 }
4218
4219 return -EINVAL;
4220}
4221
bd9db02f 4222static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4223{
4224 const char name = buf[0];
4225
4226 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4227 return -EINVAL;
4228
4229 *pipe = name - 'A';
4230
4231 return 0;
4232}
4233
4234static int
bd9db02f 4235display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4236{
4237 int i;
4238
4239 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4240 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4241 *s = i;
926321d5
DV		 4242 return 0;
4243 }
4244
4245 return -EINVAL;
4246}
4247
bd9db02f 4248static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 4249{
b94dec87 4250#define N_WORDS 3
926321d5 4251 int n_words;
b94dec87 4252 char *words[N_WORDS];
926321d5 4253 enum pipe pipe;
b94dec87 4254 enum intel_pipe_crc_object object;
926321d5
DV		 4255 enum intel_pipe_crc_source source;
4256
bd9db02f 4257 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4258 if (n_words != N_WORDS) {
4259 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4260 N_WORDS);
4261 return -EINVAL;
4262 }
4263
bd9db02f 4264 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4265 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4266 return -EINVAL;
4267 }
4268
bd9db02f 4269 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4270 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4271 return -EINVAL;
4272 }
4273
bd9db02f 4274 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4275 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4276 return -EINVAL;
4277 }
4278
4279 return pipe_crc_set_source(dev, pipe, source);
4280}
4281
bd9db02f
DL		 4282static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4283 size_t len, loff_t *offp)
926321d5
DV		 4284{
4285 struct seq_file *m = file->private_data;
4286 struct drm_device *dev = m->private;
4287 char *tmpbuf;
4288 int ret;
4289
4290 if (len == 0)
4291 return 0;
4292
4293 if (len > PAGE_SIZE - 1) {
4294 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4295 PAGE_SIZE);
4296 return -E2BIG;
4297 }
4298
4299 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4300 if (!tmpbuf)
4301 return -ENOMEM;
4302
4303 if (copy_from_user(tmpbuf, ubuf, len)) {
4304 ret = -EFAULT;
4305 goto out;
4306 }
4307 tmpbuf[len] = '\0';
4308
bd9db02f 4309 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4310
4311out:
4312 kfree(tmpbuf);
4313 if (ret < 0)
4314 return ret;
4315
4316 *offp += len;
4317 return len;
4318}
4319
bd9db02f 4320static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4321 .owner = THIS_MODULE,
bd9db02f 4322 .open = display_crc_ctl_open,
926321d5
DV		 4323 .read = seq_read,
4324 .llseek = seq_lseek,
4325 .release = single_release,
bd9db02f 4326 .write = display_crc_ctl_write
926321d5
DV		 4327};
4328
eb3394fa
TP		 4329static ssize_t i915_displayport_test_active_write(struct file *file,
4330 const char __user *ubuf,
4331 size_t len, loff_t *offp)
4332{
4333 char *input_buffer;
4334 int status = 0;
eb3394fa
TP		 4335 struct drm_device *dev;
4336 struct drm_connector *connector;
4337 struct list_head *connector_list;
4338 struct intel_dp *intel_dp;
4339 int val = 0;
4340
9aaffa34 4341 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4342
eb3394fa
TP		 4343 connector_list = &dev->mode_config.connector_list;
4344
4345 if (len == 0)
4346 return 0;
4347
4348 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4349 if (!input_buffer)
4350 return -ENOMEM;
4351
4352 if (copy_from_user(input_buffer, ubuf, len)) {
4353 status = -EFAULT;
4354 goto out;
4355 }
4356
4357 input_buffer[len] = '\0';
4358 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4359
4360 list_for_each_entry(connector, connector_list, head) {
4361
4362 if (connector->connector_type !=
4363 DRM_MODE_CONNECTOR_DisplayPort)
4364 continue;
4365
b8bb08ec 4366 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4367 connector->encoder != NULL) {
4368 intel_dp = enc_to_intel_dp(connector->encoder);
4369 status = kstrtoint(input_buffer, 10, &val);
4370 if (status < 0)
4371 goto out;
4372 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4373 /* To prevent erroneous activation of the compliance
4374 * testing code, only accept an actual value of 1 here
4375 */
4376 if (val == 1)
4377 intel_dp->compliance_test_active = 1;
4378 else
4379 intel_dp->compliance_test_active = 0;
4380 }
4381 }
4382out:
4383 kfree(input_buffer);
4384 if (status < 0)
4385 return status;
4386
4387 *offp += len;
4388 return len;
4389}
4390
4391static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4392{
4393 struct drm_device *dev = m->private;
4394 struct drm_connector *connector;
4395 struct list_head *connector_list = &dev->mode_config.connector_list;
4396 struct intel_dp *intel_dp;
4397
eb3394fa
TP		 4398 list_for_each_entry(connector, connector_list, head) {
4399
4400 if (connector->connector_type !=
4401 DRM_MODE_CONNECTOR_DisplayPort)
4402 continue;
4403
4404 if (connector->status == connector_status_connected &&
4405 connector->encoder != NULL) {
4406 intel_dp = enc_to_intel_dp(connector->encoder);
4407 if (intel_dp->compliance_test_active)
4408 seq_puts(m, "1");
4409 else
4410 seq_puts(m, "0");
4411 } else
4412 seq_puts(m, "0");
4413 }
4414
4415 return 0;
4416}
4417
4418static int i915_displayport_test_active_open(struct inode *inode,
4419 struct file *file)
4420{
4421 struct drm_device *dev = inode->i_private;
4422
4423 return single_open(file, i915_displayport_test_active_show, dev);
4424}
4425
4426static const struct file_operations i915_displayport_test_active_fops = {
4427 .owner = THIS_MODULE,
4428 .open = i915_displayport_test_active_open,
4429 .read = seq_read,
4430 .llseek = seq_lseek,
4431 .release = single_release,
4432 .write = i915_displayport_test_active_write
4433};
4434
4435static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4436{
4437 struct drm_device *dev = m->private;
4438 struct drm_connector *connector;
4439 struct list_head *connector_list = &dev->mode_config.connector_list;
4440 struct intel_dp *intel_dp;
4441
eb3394fa
TP		 4442 list_for_each_entry(connector, connector_list, head) {
4443
4444 if (connector->connector_type !=
4445 DRM_MODE_CONNECTOR_DisplayPort)
4446 continue;
4447
4448 if (connector->status == connector_status_connected &&
4449 connector->encoder != NULL) {
4450 intel_dp = enc_to_intel_dp(connector->encoder);
4451 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4452 } else
4453 seq_puts(m, "0");
4454 }
4455
4456 return 0;
4457}
4458static int i915_displayport_test_data_open(struct inode *inode,
4459 struct file *file)
4460{
4461 struct drm_device *dev = inode->i_private;
4462
4463 return single_open(file, i915_displayport_test_data_show, dev);
4464}
4465
4466static const struct file_operations i915_displayport_test_data_fops = {
4467 .owner = THIS_MODULE,
4468 .open = i915_displayport_test_data_open,
4469 .read = seq_read,
4470 .llseek = seq_lseek,
4471 .release = single_release
4472};
4473
4474static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4475{
4476 struct drm_device *dev = m->private;
4477 struct drm_connector *connector;
4478 struct list_head *connector_list = &dev->mode_config.connector_list;
4479 struct intel_dp *intel_dp;
4480
eb3394fa
TP		 4481 list_for_each_entry(connector, connector_list, head) {
4482
4483 if (connector->connector_type !=
4484 DRM_MODE_CONNECTOR_DisplayPort)
4485 continue;
4486
4487 if (connector->status == connector_status_connected &&
4488 connector->encoder != NULL) {
4489 intel_dp = enc_to_intel_dp(connector->encoder);
4490 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4491 } else
4492 seq_puts(m, "0");
4493 }
4494
4495 return 0;
4496}
4497
4498static int i915_displayport_test_type_open(struct inode *inode,
4499 struct file *file)
4500{
4501 struct drm_device *dev = inode->i_private;
4502
4503 return single_open(file, i915_displayport_test_type_show, dev);
4504}
4505
4506static const struct file_operations i915_displayport_test_type_fops = {
4507 .owner = THIS_MODULE,
4508 .open = i915_displayport_test_type_open,
4509 .read = seq_read,
4510 .llseek = seq_lseek,
4511 .release = single_release
4512};
4513
97e94b22 4514static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4515{
4516 struct drm_device *dev = m->private;
369a1342 4517 int level;
de38b95c
VS		 4518 int num_levels;
4519
4520 if (IS_CHERRYVIEW(dev))
4521 num_levels = 3;
4522 else if (IS_VALLEYVIEW(dev))
4523 num_levels = 1;
4524 else
4525 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4526
4527 drm_modeset_lock_all(dev);
4528
4529 for (level = 0; level < num_levels; level++) {
4530 unsigned int latency = wm[level];
4531
97e94b22
DL		 4532 /*
4533 * - WM1+ latency values in 0.5us units
de38b95c 4534 * - latencies are in us on gen9/vlv/chv
97e94b22 4535 */
666a4537
WB		 4536 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4537 IS_CHERRYVIEW(dev))
97e94b22
DL		 4538 latency *= 10;
4539 else if (level > 0)
369a1342
VS		 4540 latency *= 5;
4541
4542 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4543 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4544 }
4545
4546 drm_modeset_unlock_all(dev);
4547}
4548
4549static int pri_wm_latency_show(struct seq_file *m, void *data)
4550{
4551 struct drm_device *dev = m->private;
fac5e23e 4552 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22
DL		 4553 const uint16_t *latencies;
4554
4555 if (INTEL_INFO(dev)->gen >= 9)
4556 latencies = dev_priv->wm.skl_latency;
4557 else
4558 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4559
97e94b22 4560 wm_latency_show(m, latencies);
369a1342
VS		 4561
4562 return 0;
4563}
4564
4565static int spr_wm_latency_show(struct seq_file *m, void *data)
4566{
4567 struct drm_device *dev = m->private;
fac5e23e 4568 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22
DL		 4569 const uint16_t *latencies;
4570
4571 if (INTEL_INFO(dev)->gen >= 9)
4572 latencies = dev_priv->wm.skl_latency;
4573 else
4574 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4575
97e94b22 4576 wm_latency_show(m, latencies);
369a1342
VS		 4577
4578 return 0;
4579}
4580
4581static int cur_wm_latency_show(struct seq_file *m, void *data)
4582{
4583 struct drm_device *dev = m->private;
fac5e23e 4584 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22
DL		 4585 const uint16_t *latencies;
4586
4587 if (INTEL_INFO(dev)->gen >= 9)
4588 latencies = dev_priv->wm.skl_latency;
4589 else
4590 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4591
97e94b22 4592 wm_latency_show(m, latencies);
369a1342
VS		 4593
4594 return 0;
4595}
4596
4597static int pri_wm_latency_open(struct inode *inode, struct file *file)
4598{
4599 struct drm_device *dev = inode->i_private;
4600
de38b95c 4601 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4602 return -ENODEV;
4603
4604 return single_open(file, pri_wm_latency_show, dev);
4605}
4606
4607static int spr_wm_latency_open(struct inode *inode, struct file *file)
4608{
4609 struct drm_device *dev = inode->i_private;
4610
9ad0257c 4611 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4612 return -ENODEV;
4613
4614 return single_open(file, spr_wm_latency_show, dev);
4615}
4616
4617static int cur_wm_latency_open(struct inode *inode, struct file *file)
4618{
4619 struct drm_device *dev = inode->i_private;
4620
9ad0257c 4621 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4622 return -ENODEV;
4623
4624 return single_open(file, cur_wm_latency_show, dev);
4625}
4626
4627static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4628 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4629{
4630 struct seq_file *m = file->private_data;
4631 struct drm_device *dev = m->private;
97e94b22 4632 uint16_t new[8] = { 0 };
de38b95c 4633 int num_levels;
369a1342
VS		 4634 int level;
4635 int ret;
4636 char tmp[32];
4637
de38b95c
VS		 4638 if (IS_CHERRYVIEW(dev))
4639 num_levels = 3;
4640 else if (IS_VALLEYVIEW(dev))
4641 num_levels = 1;
4642 else
4643 num_levels = ilk_wm_max_level(dev) + 1;
4644
369a1342
VS		 4645 if (len >= sizeof(tmp))
4646 return -EINVAL;
4647
4648 if (copy_from_user(tmp, ubuf, len))
4649 return -EFAULT;
4650
4651 tmp[len] = '\0';
4652
97e94b22
DL		 4653 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4654 &new[0], &new[1], &new[2], &new[3],
4655 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4656 if (ret != num_levels)
4657 return -EINVAL;
4658
4659 drm_modeset_lock_all(dev);
4660
4661 for (level = 0; level < num_levels; level++)
4662 wm[level] = new[level];
4663
4664 drm_modeset_unlock_all(dev);
4665
4666 return len;
4667}
4668
4669
4670static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4671 size_t len, loff_t *offp)
4672{
4673 struct seq_file *m = file->private_data;
4674 struct drm_device *dev = m->private;
fac5e23e 4675 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22 4676 uint16_t *latencies;
369a1342 4677
97e94b22
DL		 4678 if (INTEL_INFO(dev)->gen >= 9)
4679 latencies = dev_priv->wm.skl_latency;
4680 else
4681 latencies = to_i915(dev)->wm.pri_latency;
4682
4683 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4684}
4685
4686static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4687 size_t len, loff_t *offp)
4688{
4689 struct seq_file *m = file->private_data;
4690 struct drm_device *dev = m->private;
fac5e23e 4691 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22 4692 uint16_t *latencies;
369a1342 4693
97e94b22
DL		 4694 if (INTEL_INFO(dev)->gen >= 9)
4695 latencies = dev_priv->wm.skl_latency;
4696 else
4697 latencies = to_i915(dev)->wm.spr_latency;
4698
4699 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4700}
4701
4702static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4703 size_t len, loff_t *offp)
4704{
4705 struct seq_file *m = file->private_data;
4706 struct drm_device *dev = m->private;
fac5e23e 4707 struct drm_i915_private *dev_priv = to_i915(dev);
97e94b22
DL		 4708 uint16_t *latencies;
4709
4710 if (INTEL_INFO(dev)->gen >= 9)
4711 latencies = dev_priv->wm.skl_latency;
4712 else
4713 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4714
97e94b22 4715 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4716}
4717
4718static const struct file_operations i915_pri_wm_latency_fops = {
4719 .owner = THIS_MODULE,
4720 .open = pri_wm_latency_open,
4721 .read = seq_read,
4722 .llseek = seq_lseek,
4723 .release = single_release,
4724 .write = pri_wm_latency_write
4725};
4726
4727static const struct file_operations i915_spr_wm_latency_fops = {
4728 .owner = THIS_MODULE,
4729 .open = spr_wm_latency_open,
4730 .read = seq_read,
4731 .llseek = seq_lseek,
4732 .release = single_release,
4733 .write = spr_wm_latency_write
4734};
4735
4736static const struct file_operations i915_cur_wm_latency_fops = {
4737 .owner = THIS_MODULE,
4738 .open = cur_wm_latency_open,
4739 .read = seq_read,
4740 .llseek = seq_lseek,
4741 .release = single_release,
4742 .write = cur_wm_latency_write
4743};
4744
647416f9
KC		 4745static int
4746i915_wedged_get(void *data, u64 *val)
f3cd474b 4747{
647416f9 4748 struct drm_device *dev = data;
fac5e23e 4749 struct drm_i915_private *dev_priv = to_i915(dev);
f3cd474b 4750
d98c52cf 4751 *val = i915_terminally_wedged(&dev_priv->gpu_error);
f3cd474b 4752
647416f9 4753 return 0;
f3cd474b
CW		 4754}
4755
647416f9
KC		 4756static int
4757i915_wedged_set(void *data, u64 val)
f3cd474b 4758{
647416f9 4759 struct drm_device *dev = data;
fac5e23e 4760 struct drm_i915_private *dev_priv = to_i915(dev);
d46c0517 4761
b8d24a06
MK		 4762 /*
4763 * There is no safeguard against this debugfs entry colliding
4764 * with the hangcheck calling same i915_handle_error() in
4765 * parallel, causing an explosion. For now we assume that the
4766 * test harness is responsible enough not to inject gpu hangs
4767 * while it is writing to 'i915_wedged'
4768 */
4769
d98c52cf 4770 if (i915_reset_in_progress(&dev_priv->gpu_error))
b8d24a06
MK		 4771 return -EAGAIN;
4772
d46c0517 4773 intel_runtime_pm_get(dev_priv);
f3cd474b 4774
c033666a 4775 i915_handle_error(dev_priv, val,
58174462 4776 "Manually setting wedged to %llu", val);
d46c0517
ID		 4777
4778 intel_runtime_pm_put(dev_priv);
4779
647416f9 4780 return 0;
f3cd474b
CW		 4781}
4782
647416f9
KC		 4783DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4784 i915_wedged_get, i915_wedged_set,
3a3b4f98 4785 "%llu\n");
f3cd474b 4786
094f9a54
CW		 4787static int
4788i915_ring_missed_irq_get(void *data, u64 *val)
4789{
4790 struct drm_device *dev = data;
fac5e23e 4791 struct drm_i915_private *dev_priv = to_i915(dev);
094f9a54
CW		 4792
4793 *val = dev_priv->gpu_error.missed_irq_rings;
4794 return 0;
4795}
4796
4797static int
4798i915_ring_missed_irq_set(void *data, u64 val)
4799{
4800 struct drm_device *dev = data;
fac5e23e 4801 struct drm_i915_private *dev_priv = to_i915(dev);
094f9a54
CW		 4802 int ret;
4803
4804 /* Lock against concurrent debugfs callers */
4805 ret = mutex_lock_interruptible(&dev->struct_mutex);
4806 if (ret)
4807 return ret;
4808 dev_priv->gpu_error.missed_irq_rings = val;
4809 mutex_unlock(&dev->struct_mutex);
4810
4811 return 0;
4812}
4813
4814DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4815 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4816 "0x%08llx\n");
4817
4818static int
4819i915_ring_test_irq_get(void *data, u64 *val)
4820{
4821 struct drm_device *dev = data;
fac5e23e 4822 struct drm_i915_private *dev_priv = to_i915(dev);
094f9a54
CW		 4823
4824 *val = dev_priv->gpu_error.test_irq_rings;
4825
4826 return 0;
4827}
4828
4829static int
4830i915_ring_test_irq_set(void *data, u64 val)
4831{
4832 struct drm_device *dev = data;
fac5e23e 4833 struct drm_i915_private *dev_priv = to_i915(dev);
094f9a54 4834
3a122c27 4835 val &= INTEL_INFO(dev_priv)->ring_mask;
094f9a54 4836 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
094f9a54 4837 dev_priv->gpu_error.test_irq_rings = val;
094f9a54
CW		 4838
4839 return 0;
4840}
4841
4842DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4843 i915_ring_test_irq_get, i915_ring_test_irq_set,
4844 "0x%08llx\n");
4845
dd624afd
CW		 4846#define DROP_UNBOUND 0x1
4847#define DROP_BOUND 0x2
4848#define DROP_RETIRE 0x4
4849#define DROP_ACTIVE 0x8
4850#define DROP_ALL (DROP_UNBOUND | \
4851 DROP_BOUND | \
4852 DROP_RETIRE | \
4853 DROP_ACTIVE)
647416f9
KC		 4854static int
4855i915_drop_caches_get(void *data, u64 *val)
dd624afd 4856{
647416f9 4857 *val = DROP_ALL;
dd624afd 4858
647416f9 4859 return 0;
dd624afd
CW		 4860}
4861
647416f9
KC		 4862static int
4863i915_drop_caches_set(void *data, u64 val)
dd624afd 4864{
647416f9 4865 struct drm_device *dev = data;
fac5e23e 4866 struct drm_i915_private *dev_priv = to_i915(dev);
647416f9 4867 int ret;
dd624afd 4868
2f9fe5ff 4869 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4870
4871 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4872 * on ioctls on -EAGAIN. */
4873 ret = mutex_lock_interruptible(&dev->struct_mutex);
4874 if (ret)
4875 return ret;
4876
4877 if (val & DROP_ACTIVE) {
dcff85c8 4878 ret = i915_gem_wait_for_idle(dev_priv, true);
dd624afd
CW		 4879 if (ret)
4880 goto unlock;
4881 }
4882
4883 if (val & (DROP_RETIRE | DROP_ACTIVE))
c033666a 4884 i915_gem_retire_requests(dev_priv);
dd624afd 4885
21ab4e74
CW		 4886 if (val & DROP_BOUND)
4887 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4888
21ab4e74
CW		 4889 if (val & DROP_UNBOUND)
4890 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4891
4892unlock:
4893 mutex_unlock(&dev->struct_mutex);
4894
647416f9 4895 return ret;
dd624afd
CW		 4896}
4897
647416f9
KC		 4898DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4899 i915_drop_caches_get, i915_drop_caches_set,
4900 "0x%08llx\n");
dd624afd 4901
647416f9
KC		 4902static int
4903i915_max_freq_get(void *data, u64 *val)
358733e9 4904{
647416f9 4905 struct drm_device *dev = data;
fac5e23e 4906 struct drm_i915_private *dev_priv = to_i915(dev);
004777cb 4907
daa3afb2 4908 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4909 return -ENODEV;
4910
7c59a9c1 4911 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
647416f9 4912 return 0;
358733e9
JB		 4913}
4914
647416f9
KC		 4915static int
4916i915_max_freq_set(void *data, u64 val)
358733e9 4917{
647416f9 4918 struct drm_device *dev = data;
fac5e23e 4919 struct drm_i915_private *dev_priv = to_i915(dev);
bc4d91f6 4920 u32 hw_max, hw_min;
647416f9 4921 int ret;
004777cb 4922
daa3afb2 4923 if (INTEL_INFO(dev)->gen < 6)
004777cb 4924 return -ENODEV;
358733e9 4925
647416f9 4926 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4927
4fc688ce 4928 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4929 if (ret)
4930 return ret;
4931
358733e9
JB		 4932 /*
4933 * Turbo will still be enabled, but won't go above the set value.
4934 */
bc4d91f6 4935 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4936
bc4d91f6
AG		 4937 hw_max = dev_priv->rps.max_freq;
4938 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4939
b39fb297 4940 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4941 mutex_unlock(&dev_priv->rps.hw_lock);
4942 return -EINVAL;
0a073b84
JB		 4943 }
4944
b39fb297 4945 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4946
dc97997a 4947 intel_set_rps(dev_priv, val);
dd0a1aa1 4948
4fc688ce 4949 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4950
647416f9 4951 return 0;
358733e9
JB		 4952}
4953
647416f9
KC		 4954DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4955 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4956 "%llu\n");
358733e9 4957
647416f9
KC		 4958static int
4959i915_min_freq_get(void *data, u64 *val)
1523c310 4960{
647416f9 4961 struct drm_device *dev = data;
fac5e23e 4962 struct drm_i915_private *dev_priv = to_i915(dev);
004777cb 4963
62e1baa1 4964 if (INTEL_GEN(dev_priv) < 6)
004777cb
DV		 4965 return -ENODEV;
4966
7c59a9c1 4967 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
647416f9 4968 return 0;
1523c310
JB		 4969}
4970
647416f9
KC		 4971static int
4972i915_min_freq_set(void *data, u64 val)
1523c310 4973{
647416f9 4974 struct drm_device *dev = data;
fac5e23e 4975 struct drm_i915_private *dev_priv = to_i915(dev);
bc4d91f6 4976 u32 hw_max, hw_min;
647416f9 4977 int ret;
004777cb 4978
62e1baa1 4979 if (INTEL_GEN(dev_priv) < 6)
004777cb 4980 return -ENODEV;
1523c310 4981
647416f9 4982 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4983
4fc688ce 4984 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4985 if (ret)
4986 return ret;
4987
1523c310
JB		 4988 /*
4989 * Turbo will still be enabled, but won't go below the set value.
4990 */
bc4d91f6 4991 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4992
bc4d91f6
AG		 4993 hw_max = dev_priv->rps.max_freq;
4994 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4995
b39fb297 4996 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4997 mutex_unlock(&dev_priv->rps.hw_lock);
4998 return -EINVAL;
0a073b84 4999 }
dd0a1aa1 5000
b39fb297 5001 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 5002
dc97997a 5003 intel_set_rps(dev_priv, val);
dd0a1aa1 5004
4fc688ce 5005 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 5006
647416f9 5007 return 0;
1523c310
JB		 5008}
5009
647416f9
KC		 5010DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5011 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 5012 "%llu\n");
1523c310 5013
647416f9
KC		 5014static int
5015i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 5016{
647416f9 5017 struct drm_device *dev = data;
fac5e23e 5018 struct drm_i915_private *dev_priv = to_i915(dev);
07b7ddd9 5019 u32 snpcr;
647416f9 5020 int ret;
07b7ddd9 5021
004777cb
DV		 5022 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5023 return -ENODEV;
5024
22bcfc6a
DV		 5025 ret = mutex_lock_interruptible(&dev->struct_mutex);
5026 if (ret)
5027 return ret;
c8c8fb33 5028 intel_runtime_pm_get(dev_priv);
22bcfc6a 5029
07b7ddd9 5030 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 5031
5032 intel_runtime_pm_put(dev_priv);
91c8a326 5033 mutex_unlock(&dev_priv->drm.struct_mutex);
07b7ddd9 5034
647416f9 5035 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 5036
647416f9 5037 return 0;
07b7ddd9
JB		 5038}
5039
647416f9
KC		 5040static int
5041i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 5042{
647416f9 5043 struct drm_device *dev = data;
fac5e23e 5044 struct drm_i915_private *dev_priv = to_i915(dev);
07b7ddd9 5045 u32 snpcr;
07b7ddd9 5046
004777cb
DV		 5047 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5048 return -ENODEV;
5049
647416f9 5050 if (val > 3)
07b7ddd9
JB		 5051 return -EINVAL;
5052
c8c8fb33 5053 intel_runtime_pm_get(dev_priv);
647416f9 5054 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 5055
5056 /* Update the cache sharing policy here as well */
5057 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5058 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5059 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5060 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5061
c8c8fb33 5062 intel_runtime_pm_put(dev_priv);
647416f9 5063 return 0;
07b7ddd9
JB		 5064}
5065
647416f9
KC		 5066DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5067 i915_cache_sharing_get, i915_cache_sharing_set,
5068 "%llu\n");
07b7ddd9 5069
5d39525a
JM		 5070struct sseu_dev_status {
5071 unsigned int slice_total;
5072 unsigned int subslice_total;
5073 unsigned int subslice_per_slice;
5074 unsigned int eu_total;
5075 unsigned int eu_per_subslice;
5076};
5077
5078static void cherryview_sseu_device_status(struct drm_device *dev,
5079 struct sseu_dev_status *stat)
5080{
fac5e23e 5081 struct drm_i915_private *dev_priv = to_i915(dev);
0a0b457f 5082 int ss_max = 2;
5d39525a
JM		 5083 int ss;
5084 u32 sig1[ss_max], sig2[ss_max];
5085
5086 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5087 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5088 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5089 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5090
5091 for (ss = 0; ss < ss_max; ss++) {
5092 unsigned int eu_cnt;
5093
5094 if (sig1[ss] & CHV_SS_PG_ENABLE)
5095 /* skip disabled subslice */
5096 continue;
5097
5098 stat->slice_total = 1;
5099 stat->subslice_per_slice++;
5100 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5101 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5102 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5103 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5104 stat->eu_total += eu_cnt;
5105 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5106 }
5107 stat->subslice_total = stat->subslice_per_slice;
5108}
5109
5110static void gen9_sseu_device_status(struct drm_device *dev,
5111 struct sseu_dev_status *stat)
5112{
fac5e23e 5113 struct drm_i915_private *dev_priv = to_i915(dev);
1c046bc1 5114 int s_max = 3, ss_max = 4;
5d39525a
JM		 5115 int s, ss;
5116 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5117
1c046bc1
JM		 5118 /* BXT has a single slice and at most 3 subslices. */
5119 if (IS_BROXTON(dev)) {
5120 s_max = 1;
5121 ss_max = 3;
5122 }
5123
5124 for (s = 0; s < s_max; s++) {
5125 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5126 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5127 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5128 }
5129
5d39525a
JM		 5130 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5131 GEN9_PGCTL_SSA_EU19_ACK |
5132 GEN9_PGCTL_SSA_EU210_ACK |
5133 GEN9_PGCTL_SSA_EU311_ACK;
5134 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5135 GEN9_PGCTL_SSB_EU19_ACK |
5136 GEN9_PGCTL_SSB_EU210_ACK |
5137 GEN9_PGCTL_SSB_EU311_ACK;
5138
5139 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 5140 unsigned int ss_cnt = 0;
5141
5d39525a
JM		 5142 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5143 /* skip disabled slice */
5144 continue;
5145
5146 stat->slice_total++;
1c046bc1 5147
ef11bdb3 5148 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1c046bc1
JM		 5149 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5150
5d39525a
JM		 5151 for (ss = 0; ss < ss_max; ss++) {
5152 unsigned int eu_cnt;
5153
1c046bc1
JM		 5154 if (IS_BROXTON(dev) &&
5155 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5156 /* skip disabled subslice */
5157 continue;
5158
5159 if (IS_BROXTON(dev))
5160 ss_cnt++;
5161
5d39525a
JM		 5162 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5163 eu_mask[ss%2]);
5164 stat->eu_total += eu_cnt;
5165 stat->eu_per_subslice = max(stat->eu_per_subslice,
5166 eu_cnt);
5167 }
1c046bc1
JM		 5168
5169 stat->subslice_total += ss_cnt;
5170 stat->subslice_per_slice = max(stat->subslice_per_slice,
5171 ss_cnt);
5d39525a
JM		 5172 }
5173}
5174
91bedd34
ŁD		 5175static void broadwell_sseu_device_status(struct drm_device *dev,
5176 struct sseu_dev_status *stat)
5177{
fac5e23e 5178 struct drm_i915_private *dev_priv = to_i915(dev);
91bedd34
ŁD		 5179 int s;
5180 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5181
5182 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5183
5184 if (stat->slice_total) {
5185 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5186 stat->subslice_total = stat->slice_total *
5187 stat->subslice_per_slice;
5188 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5189 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5190
5191 /* subtract fused off EU(s) from enabled slice(s) */
5192 for (s = 0; s < stat->slice_total; s++) {
5193 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5194
5195 stat->eu_total -= hweight8(subslice_7eu);
5196 }
5197 }
5198}
5199
3873218f
JM		 5200static int i915_sseu_status(struct seq_file *m, void *unused)
5201{
5202 struct drm_info_node *node = (struct drm_info_node *) m->private;
238010ed
DW		 5203 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
5204 struct drm_device *dev = &dev_priv->drm;
5d39525a 5205 struct sseu_dev_status stat;
3873218f 5206
91bedd34 5207 if (INTEL_INFO(dev)->gen < 8)
3873218f
JM		 5208 return -ENODEV;
5209
5210 seq_puts(m, "SSEU Device Info\n");
5211 seq_printf(m, " Available Slice Total: %u\n",
5212 INTEL_INFO(dev)->slice_total);
5213 seq_printf(m, " Available Subslice Total: %u\n",
5214 INTEL_INFO(dev)->subslice_total);
5215 seq_printf(m, " Available Subslice Per Slice: %u\n",
5216 INTEL_INFO(dev)->subslice_per_slice);
5217 seq_printf(m, " Available EU Total: %u\n",
5218 INTEL_INFO(dev)->eu_total);
5219 seq_printf(m, " Available EU Per Subslice: %u\n",
5220 INTEL_INFO(dev)->eu_per_subslice);
33e141ed 5221 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5222 if (HAS_POOLED_EU(dev))
5223 seq_printf(m, " Min EU in pool: %u\n",
5224 INTEL_INFO(dev)->min_eu_in_pool);
3873218f
JM		 5225 seq_printf(m, " Has Slice Power Gating: %s\n",
5226 yesno(INTEL_INFO(dev)->has_slice_pg));
5227 seq_printf(m, " Has Subslice Power Gating: %s\n",
5228 yesno(INTEL_INFO(dev)->has_subslice_pg));
5229 seq_printf(m, " Has EU Power Gating: %s\n",
5230 yesno(INTEL_INFO(dev)->has_eu_pg));
5231
7f992aba 5232 seq_puts(m, "SSEU Device Status\n");
5d39525a 5233 memset(&stat, 0, sizeof(stat));
238010ed
DW		 5234
5235 intel_runtime_pm_get(dev_priv);
5236
5575f03a 5237 if (IS_CHERRYVIEW(dev)) {
5d39525a 5238 cherryview_sseu_device_status(dev, &stat);
91bedd34
ŁD		 5239 } else if (IS_BROADWELL(dev)) {
5240 broadwell_sseu_device_status(dev, &stat);
1c046bc1 5241 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 5242 gen9_sseu_device_status(dev, &stat);
7f992aba 5243 }
238010ed
DW		 5244
5245 intel_runtime_pm_put(dev_priv);
5246
5d39525a
JM		 5247 seq_printf(m, " Enabled Slice Total: %u\n",
5248 stat.slice_total);
5249 seq_printf(m, " Enabled Subslice Total: %u\n",
5250 stat.subslice_total);
5251 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5252 stat.subslice_per_slice);
5253 seq_printf(m, " Enabled EU Total: %u\n",
5254 stat.eu_total);
5255 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5256 stat.eu_per_subslice);
7f992aba 5257
3873218f
JM		 5258 return 0;
5259}
5260
6d794d42
BW		 5261static int i915_forcewake_open(struct inode *inode, struct file *file)
5262{
5263 struct drm_device *dev = inode->i_private;
fac5e23e 5264 struct drm_i915_private *dev_priv = to_i915(dev);
6d794d42 5265
075edca4 5266 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5267 return 0;
5268
6daccb0b 5269 intel_runtime_pm_get(dev_priv);
59bad947 5270 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5271
5272 return 0;
5273}
5274
c43b5634 5275static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5276{
5277 struct drm_device *dev = inode->i_private;
fac5e23e 5278 struct drm_i915_private *dev_priv = to_i915(dev);
6d794d42 5279
075edca4 5280 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5281 return 0;
5282
59bad947 5283 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5284 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5285
5286 return 0;
5287}
5288
5289static const struct file_operations i915_forcewake_fops = {
5290 .owner = THIS_MODULE,
5291 .open = i915_forcewake_open,
5292 .release = i915_forcewake_release,
5293};
5294
5295static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5296{
5297 struct drm_device *dev = minor->dev;
5298 struct dentry *ent;
5299
5300 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5301 S_IRUSR,
6d794d42
BW		 5302 root, dev,
5303 &i915_forcewake_fops);
f3c5fe97
WY		 5304 if (!ent)
5305 return -ENOMEM;
6d794d42 5306
8eb57294 5307 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5308}
5309
6a9c308d
DV		 5310static int i915_debugfs_create(struct dentry *root,
5311 struct drm_minor *minor,
5312 const char *name,
5313 const struct file_operations *fops)
07b7ddd9
JB		 5314{
5315 struct drm_device *dev = minor->dev;
5316 struct dentry *ent;
5317
6a9c308d 5318 ent = debugfs_create_file(name,
07b7ddd9
JB		 5319 S_IRUGO | S_IWUSR,
5320 root, dev,
6a9c308d 5321 fops);
f3c5fe97
WY		 5322 if (!ent)
5323 return -ENOMEM;
07b7ddd9 5324
6a9c308d 5325 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5326}
5327
06c5bf8c 5328static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5329 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5330 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5331 {"i915_gem_gtt", i915_gem_gtt_info, 0},
6da84829 5332 {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
6d2b8885 5333 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5334 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5335 {"i915_gem_request", i915_gem_request_info, 0},
5336 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5337 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5338 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5339 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5340 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5341 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5342 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5343 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5344 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5345 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5346 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5347 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5348 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5349 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5350 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5351 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5352 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5353 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5354 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5355 {"i915_sr_status", i915_sr_status, 0},
44834a67 5356 {"i915_opregion", i915_opregion, 0},
ada8f955 5357 {"i915_vbt", i915_vbt, 0},
37811fcc 5358 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5359 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5360 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5361 {"i915_execlists", i915_execlists, 0},
f65367b5 5362 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5363 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5364 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5365 {"i915_llc", i915_llc, 0},
e91fd8c6 5366 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5367 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5368 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5369 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5370 {"i915_power_domain_info", i915_power_domain_info, 0},
b7cec66d 5371 {"i915_dmc_info", i915_dmc_info, 0},
53f5e3ca 5372 {"i915_display_info", i915_display_info, 0},
e04934cf 5373 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5374 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5375 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5376 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5377 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5378 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5379 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5380 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5381};
27c202ad 5382#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5383
06c5bf8c 5384static const struct i915_debugfs_files {
34b9674c
DV		 5385 const char *name;
5386 const struct file_operations *fops;
5387} i915_debugfs_files[] = {
5388 {"i915_wedged", &i915_wedged_fops},
5389 {"i915_max_freq", &i915_max_freq_fops},
5390 {"i915_min_freq", &i915_min_freq_fops},
5391 {"i915_cache_sharing", &i915_cache_sharing_fops},
094f9a54
CW		 5392 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5393 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5394 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5395 {"i915_error_state", &i915_error_state_fops},
5396 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5397 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5398 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5399 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5400 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5401 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5402 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5403 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5404 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5405};
5406
07144428
DL		 5407void intel_display_crc_init(struct drm_device *dev)
5408{
fac5e23e 5409 struct drm_i915_private *dev_priv = to_i915(dev);
b378360e 5410 enum pipe pipe;
07144428 5411
055e393f 5412 for_each_pipe(dev_priv, pipe) {
b378360e 5413 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5414
d538bbdf
DL		 5415 pipe_crc->opened = false;
5416 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5417 init_waitqueue_head(&pipe_crc->wq);
5418 }
5419}
5420
1dac891c 5421int i915_debugfs_register(struct drm_i915_private *dev_priv)
2017263e 5422{
91c8a326 5423 struct drm_minor *minor = dev_priv->drm.primary;
34b9674c 5424 int ret, i;
f3cd474b 5425
6d794d42 5426 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5427 if (ret)
5428 return ret;
6a9c308d 5429
07144428
DL		 5430 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5431 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5432 if (ret)
5433 return ret;
5434 }
5435
34b9674c
DV		 5436 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5437 ret = i915_debugfs_create(minor->debugfs_root, minor,
5438 i915_debugfs_files[i].name,
5439 i915_debugfs_files[i].fops);
5440 if (ret)
5441 return ret;
5442 }
40633219 5443
27c202ad
BG		 5444 return drm_debugfs_create_files(i915_debugfs_list,
5445 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5446 minor->debugfs_root, minor);
5447}
5448
1dac891c 5449void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
2017263e 5450{
91c8a326 5451 struct drm_minor *minor = dev_priv->drm.primary;
34b9674c
DV		 5452 int i;
5453
27c202ad
BG		 5454 drm_debugfs_remove_files(i915_debugfs_list,
5455 I915_DEBUGFS_ENTRIES, minor);
07144428 5456
6d794d42
BW		 5457 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5458 1, minor);
07144428 5459
e309a997 5460 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5461 struct drm_info_list *info_list =
5462 (struct drm_info_list *)&i915_pipe_crc_data[i];
5463
5464 drm_debugfs_remove_files(info_list, 1, minor);
5465 }
5466
34b9674c
DV		 5467 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5468 struct drm_info_list *info_list =
5469 (struct drm_info_list *) i915_debugfs_files[i].fops;
5470
5471 drm_debugfs_remove_files(info_list, 1, minor);
5472 }
2017263e 5473}
aa7471d2
JN		 5474
5475struct dpcd_block {
5476 /* DPCD dump start address. */
5477 unsigned int offset;
5478 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5479 unsigned int end;
5480 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5481 size_t size;
5482 /* Only valid for eDP. */
5483 bool edp;
5484};
5485
5486static const struct dpcd_block i915_dpcd_debug[] = {
5487 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5488 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5489 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5490 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5491 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5492 { .offset = DP_SET_POWER },
5493 { .offset = DP_EDP_DPCD_REV },
5494 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5495 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5496 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5497};
5498
5499static int i915_dpcd_show(struct seq_file *m, void *data)
5500{
5501 struct drm_connector *connector = m->private;
5502 struct intel_dp *intel_dp =
5503 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5504 uint8_t buf[16];
5505 ssize_t err;
5506 int i;
5507
5c1a8875
MK		 5508 if (connector->status != connector_status_connected)
5509 return -ENODEV;
5510
aa7471d2
JN		 5511 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5512 const struct dpcd_block *b = &i915_dpcd_debug[i];
5513 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5514
5515 if (b->edp &&
5516 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5517 continue;
5518
5519 /* low tech for now */
5520 if (WARN_ON(size > sizeof(buf)))
5521 continue;
5522
5523 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5524 if (err <= 0) {
5525 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5526 size, b->offset, err);
5527 continue;
5528 }
5529
5530 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5531 }
aa7471d2
JN		 5532
5533 return 0;
5534}
5535
5536static int i915_dpcd_open(struct inode *inode, struct file *file)
5537{
5538 return single_open(file, i915_dpcd_show, inode->i_private);
5539}
5540
5541static const struct file_operations i915_dpcd_fops = {
5542 .owner = THIS_MODULE,
5543 .open = i915_dpcd_open,
5544 .read = seq_read,
5545 .llseek = seq_lseek,
5546 .release = single_release,
5547};
5548
5549/**
5550 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5551 * @connector: pointer to a registered drm_connector
5552 *
5553 * Cleanup will be done by drm_connector_unregister() through a call to
5554 * drm_debugfs_connector_remove().
5555 *
5556 * Returns 0 on success, negative error codes on error.
5557 */
5558int i915_debugfs_connector_add(struct drm_connector *connector)
5559{
5560 struct dentry *root = connector->debugfs_entry;
5561
5562 /* The connector must have been registered beforehands. */
5563 if (!root)
5564 return -ENODEV;
5565
5566 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5567 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5568 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5569 &i915_dpcd_fops);
5570
5571 return 0;
5572}
Linux kernel - Deliverables
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