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drm/i915/BXT: Get pipe conf from the port registers
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
497666d8
DL		 49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
70d39fe4
CW		 75static int i915_capabilities(struct seq_file *m, void *data)
76{
9f25d007 77 struct drm_info_node *node = m->private;
70d39fe4
CW		 78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
70d39fe4
CW		 88
89 return 0;
90}
2017263e 91
05394f39 92static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 93{
baaa5cfb 94 if (obj->pin_display)
a6172a80
CW		 95 return "p";
96 else
97 return " ";
98}
99
05394f39 100static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 101{
0206e353
AJ		 102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
a6172a80
CW		 108}
109
1d693bcc
BW		 110static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111{
aff43766 112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 113}
114
ca1543be
TU		 115static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116{
117 u64 size = 0;
118 struct i915_vma *vma;
119
1c7f4bca 120 list_for_each_entry(vma, &obj->vma_list, obj_link) {
596c5923 121 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
ca1543be
TU		 122 size += vma->node.size;
123 }
124
125 return size;
126}
127
37811fcc
CW		 128static void
129describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
130{
b4716185 131 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
e2f80391 132 struct intel_engine_cs *engine;
1d693bcc 133 struct i915_vma *vma;
d7f46fc4 134 int pin_count = 0;
c3232b18 135 enum intel_engine_id id;
d7f46fc4 136
188c1ab7
CW		 137 lockdep_assert_held(&obj->base.dev->struct_mutex);
138
b4716185 139 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 140 &obj->base,
481a3d43 141 obj->active ? "*" : " ",
37811fcc
CW		 142 get_pin_flag(obj),
143 get_tiling_flag(obj),
1d693bcc 144 get_global_flag(obj),
a05a5862 145 obj->base.size / 1024,
37811fcc 146 obj->base.read_domains,
b4716185 147 obj->base.write_domain);
c3232b18 148 for_each_engine_id(engine, dev_priv, id)
b4716185 149 seq_printf(m, "%x ",
c3232b18 150 i915_gem_request_get_seqno(obj->last_read_req[id]));
b4716185 151 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 152 i915_gem_request_get_seqno(obj->last_write_req),
153 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 154 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 155 obj->dirty ? " dirty" : "",
156 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
157 if (obj->base.name)
158 seq_printf(m, " (name: %d)", obj->base.name);
1c7f4bca 159 list_for_each_entry(vma, &obj->vma_list, obj_link) {
d7f46fc4
BW		 160 if (vma->pin_count > 0)
161 pin_count++;
ba0635ff
DC		 162 }
163 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 164 if (obj->pin_display)
165 seq_printf(m, " (display)");
37811fcc
CW		 166 if (obj->fence_reg != I915_FENCE_REG_NONE)
167 seq_printf(m, " (fence: %d)", obj->fence_reg);
1c7f4bca 168 list_for_each_entry(vma, &obj->vma_list, obj_link) {
8d2fdc3f 169 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
596c5923 170 vma->is_ggtt ? "g" : "pp",
8d2fdc3f 171 vma->node.start, vma->node.size);
596c5923
CW		 172 if (vma->is_ggtt)
173 seq_printf(m, ", type: %u", vma->ggtt_view.type);
174 seq_puts(m, ")");
1d693bcc 175 }
c1ad11fc 176 if (obj->stolen)
440fd528 177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 178 if (obj->pin_display || obj->fault_mappable) {
6299f992 179 char s[3], *t = s;
30154650 180 if (obj->pin_display)
6299f992
CW		 181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
b4716185 187 if (obj->last_write_req != NULL)
41c52415 188 seq_printf(m, " (%s)",
666796da 189 i915_gem_request_get_engine(obj->last_write_req)->name);
d5a81ef1
DV		 190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 192}
193
273497e5 194static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 195{
ea0c76f8 196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199}
200
433e12f7 201static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 202{
9f25d007 203 struct drm_info_node *node = m->private;
433e12f7
BG		 204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
2017263e 206 struct drm_device *dev = node->minor->dev;
72e96d64
JL		 207 struct drm_i915_private *dev_priv = to_i915(dev);
208 struct i915_ggtt *ggtt = &dev_priv->ggtt;
ca191b13 209 struct i915_vma *vma;
c44ef60e 210 u64 total_obj_size, total_gtt_size;
8f2480fb 211 int count, ret;
de227ef0
CW		 212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
2017263e 216
ca191b13 217 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 218 switch (list) {
219 case ACTIVE_LIST:
267f0c90 220 seq_puts(m, "Active:\n");
72e96d64 221 head = &ggtt->base.active_list;
433e12f7
BG		 222 break;
223 case INACTIVE_LIST:
267f0c90 224 seq_puts(m, "Inactive:\n");
72e96d64 225 head = &ggtt->base.inactive_list;
433e12f7 226 break;
433e12f7 227 default:
de227ef0
CW		 228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
2017263e 230 }
2017263e 231
8f2480fb 232 total_obj_size = total_gtt_size = count = 0;
1c7f4bca 233 list_for_each_entry(vma, head, vm_link) {
ca191b13
BW		 234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
8f2480fb 239 count++;
2017263e 240 }
de227ef0 241 mutex_unlock(&dev->struct_mutex);
5e118f41 242
c44ef60e 243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 244 count, total_obj_size, total_gtt_size);
2017263e
BG		 245 return 0;
246}
247
6d2b8885
CW		 248static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250{
251 struct drm_i915_gem_object *a =
b25cb2f8 252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 253 struct drm_i915_gem_object *b =
b25cb2f8 254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 255
2d05fa16
RV		 256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
6d2b8885
CW		 261}
262
263static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264{
9f25d007 265 struct drm_info_node *node = m->private;
6d2b8885
CW		 266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
c44ef60e 269 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
b25cb2f8 282 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 283
284 total_obj_size += obj->base.size;
ca1543be 285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
b25cb2f8 292 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
b25cb2f8 300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
b25cb2f8 304 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 305 }
306 mutex_unlock(&dev->struct_mutex);
307
c44ef60e 308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 309 count, total_obj_size, total_gtt_size);
310 return 0;
311}
312
6299f992
CW		 313#define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
ca1543be 315 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 316 ++count; \
317 if (obj->map_and_fenceable) { \
f343c5f6 318 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 319 ++mappable_count; \
320 } \
321 } \
0206e353 322} while (0)
6299f992 323
2db8e9d6 324struct file_stats {
6313c204 325 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
2db8e9d6
CW		 330};
331
332static int per_file_stats(int id, void *ptr, void *data)
333{
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
6313c204 336 struct i915_vma *vma;
2db8e9d6
CW		 337
338 stats->count++;
339 stats->total += obj->base.size;
340
c67a17e9
CW		 341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
6313c204 344 if (USES_FULL_PPGTT(obj->base.dev)) {
1c7f4bca 345 list_for_each_entry(vma, &obj->vma_list, obj_link) {
6313c204
CW		 346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
596c5923 351 if (vma->is_ggtt) {
6313c204
CW		 352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 357 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 358 continue;
359
41c52415 360 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
2db8e9d6 367 } else {
6313c204
CW		 368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
41c52415 370 if (obj->active)
6313c204
CW		 371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
2db8e9d6
CW		 376 }
377
6313c204
CW		 378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
2db8e9d6
CW		 381 return 0;
382}
383
b0da1b79
CW		 384#define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
c44ef60e 386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395} while (0)
493018dc
BV		 396
397static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399{
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
e2f80391 402 struct intel_engine_cs *engine;
b4ac5afc 403 int j;
493018dc
BV		 404
405 memset(&stats, 0, sizeof(stats));
406
b4ac5afc 407 for_each_engine(engine, dev_priv) {
e2f80391 408 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744 409 list_for_each_entry(obj,
e2f80391 410 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
06fbca71 414 }
493018dc 415
b0da1b79 416 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 417}
418
ca191b13
BW		 419#define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
ca1543be 421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428} while (0)
429
430static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 431{
9f25d007 432 struct drm_info_node *node = m->private;
73aa808f 433 struct drm_device *dev = node->minor->dev;
72e96d64
JL		 434 struct drm_i915_private *dev_priv = to_i915(dev);
435 struct i915_ggtt *ggtt = &dev_priv->ggtt;
b7abb714 436 u32 count, mappable_count, purgeable_count;
c44ef60e 437 u64 size, mappable_size, purgeable_size;
6299f992 438 struct drm_i915_gem_object *obj;
2db8e9d6 439 struct drm_file *file;
ca191b13 440 struct i915_vma *vma;
73aa808f
CW		 441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
6299f992
CW		 447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
35c20a60 452 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
72e96d64 457 count_vmas(&ggtt->base.active_list, vm_link);
c44ef60e 458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 459 count, mappable_count, size, mappable_size);
460
6299f992 461 size = count = mappable_size = mappable_count = 0;
72e96d64 462 count_vmas(&ggtt->base.inactive_list, vm_link);
c44ef60e 463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 464 count, mappable_count, size, mappable_size);
465
b7abb714 466 size = count = purgeable_size = purgeable_count = 0;
35c20a60 467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 468 size += obj->base.size, ++count;
b7abb714
CW		 469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
c44ef60e 472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 473
6299f992 474 size = count = mappable_size = mappable_count = 0;
35c20a60 475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 476 if (obj->fault_mappable) {
f343c5f6 477 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 478 ++count;
479 }
30154650 480 if (obj->pin_display) {
f343c5f6 481 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 482 ++mappable_count;
483 }
b7abb714
CW		 484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
6299f992 488 }
c44ef60e 489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 490 purgeable_count, purgeable_size);
c44ef60e 491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 492 mappable_count, mappable_size);
c44ef60e 493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992
CW		 494 count, size);
495
c44ef60e 496 seq_printf(m, "%llu [%llu] gtt total\n",
72e96d64 497 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
73aa808f 498
493018dc
BV		 499 seq_putc(m, '\n');
500 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 501 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
502 struct file_stats stats;
3ec2f427 503 struct task_struct *task;
2db8e9d6
CW		 504
505 memset(&stats, 0, sizeof(stats));
6313c204 506 stats.file_priv = file->driver_priv;
5b5ffff0 507 spin_lock(&file->table_lock);
2db8e9d6 508 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 509 spin_unlock(&file->table_lock);
3ec2f427
TH		 510 /*
511 * Although we have a valid reference on file->pid, that does
512 * not guarantee that the task_struct who called get_pid() is
513 * still alive (e.g. get_pid(current) => fork() => exit()).
514 * Therefore, we need to protect this ->comm access using RCU.
515 */
516 rcu_read_lock();
517 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 518 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 519 rcu_read_unlock();
2db8e9d6
CW		 520 }
521
73aa808f
CW		 522 mutex_unlock(&dev->struct_mutex);
523
524 return 0;
525}
526
aee56cff 527static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 528{
9f25d007 529 struct drm_info_node *node = m->private;
08c18323 530 struct drm_device *dev = node->minor->dev;
1b50247a 531 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 532 struct drm_i915_private *dev_priv = dev->dev_private;
533 struct drm_i915_gem_object *obj;
c44ef60e 534 u64 total_obj_size, total_gtt_size;
08c18323
CW		 535 int count, ret;
536
537 ret = mutex_lock_interruptible(&dev->struct_mutex);
538 if (ret)
539 return ret;
540
541 total_obj_size = total_gtt_size = count = 0;
35c20a60 542 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 543 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 544 continue;
545
267f0c90 546 seq_puts(m, " ");
08c18323 547 describe_obj(m, obj);
267f0c90 548 seq_putc(m, '\n');
08c18323 549 total_obj_size += obj->base.size;
ca1543be 550 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 551 count++;
552 }
553
554 mutex_unlock(&dev->struct_mutex);
555
c44ef60e 556 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 557 count, total_obj_size, total_gtt_size);
558
559 return 0;
560}
561
4e5359cd
SF		 562static int i915_gem_pageflip_info(struct seq_file *m, void *data)
563{
9f25d007 564 struct drm_info_node *node = m->private;
4e5359cd 565 struct drm_device *dev = node->minor->dev;
d6bbafa1 566 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 567 struct intel_crtc *crtc;
8a270ebf
DV		 568 int ret;
569
570 ret = mutex_lock_interruptible(&dev->struct_mutex);
571 if (ret)
572 return ret;
4e5359cd 573
d3fcc808 574 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 575 const char pipe = pipe_name(crtc->pipe);
576 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 577 struct intel_unpin_work *work;
578
5e2d7afc 579 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 580 work = crtc->unpin_work;
581 if (work == NULL) {
9db4a9c7 582 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 583 pipe, plane);
584 } else {
d6bbafa1
CW		 585 u32 addr;
586
e7d841ca 587 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 588 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 589 pipe, plane);
590 } else {
9db4a9c7 591 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 592 pipe, plane);
593 }
3a8a946e 594 if (work->flip_queued_req) {
666796da 595 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
3a8a946e 596
20e28fba 597 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
e2f80391 598 engine->name,
f06cc1b9 599 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 600 dev_priv->next_seqno,
e2f80391 601 engine->get_seqno(engine, true),
1b5a433a 602 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 603 } else
604 seq_printf(m, "Flip not associated with any ring\n");
605 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
606 work->flip_queued_vblank,
607 work->flip_ready_vblank,
1e3feefd 608 drm_crtc_vblank_count(&crtc->base));
4e5359cd 609 if (work->enable_stall_check)
267f0c90 610 seq_puts(m, "Stall check enabled, ");
4e5359cd 611 else
267f0c90 612 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 613 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 614
d6bbafa1
CW		 615 if (INTEL_INFO(dev)->gen >= 4)
616 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
617 else
618 addr = I915_READ(DSPADDR(crtc->plane));
619 seq_printf(m, "Current scanout address 0x%08x\n", addr);
620
4e5359cd 621 if (work->pending_flip_obj) {
d6bbafa1
CW		 622 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
623 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 624 }
625 }
5e2d7afc 626 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 627 }
628
8a270ebf
DV		 629 mutex_unlock(&dev->struct_mutex);
630
4e5359cd
SF		 631 return 0;
632}
633
493018dc
BV		 634static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
635{
636 struct drm_info_node *node = m->private;
637 struct drm_device *dev = node->minor->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 struct drm_i915_gem_object *obj;
e2f80391 640 struct intel_engine_cs *engine;
8d9d5744 641 int total = 0;
b4ac5afc 642 int ret, j;
493018dc
BV		 643
644 ret = mutex_lock_interruptible(&dev->struct_mutex);
645 if (ret)
646 return ret;
647
b4ac5afc 648 for_each_engine(engine, dev_priv) {
e2f80391 649 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744
CW		 650 int count;
651
652 count = 0;
653 list_for_each_entry(obj,
e2f80391 654 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 655 batch_pool_link)
656 count++;
657 seq_printf(m, "%s cache[%d]: %d objects\n",
e2f80391 658 engine->name, j, count);
8d9d5744
CW		 659
660 list_for_each_entry(obj,
e2f80391 661 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 662 batch_pool_link) {
663 seq_puts(m, " ");
664 describe_obj(m, obj);
665 seq_putc(m, '\n');
666 }
667
668 total += count;
06fbca71 669 }
493018dc
BV		 670 }
671
8d9d5744 672 seq_printf(m, "total: %d\n", total);
493018dc
BV		 673
674 mutex_unlock(&dev->struct_mutex);
675
676 return 0;
677}
678
2017263e
BG		 679static int i915_gem_request_info(struct seq_file *m, void *data)
680{
9f25d007 681 struct drm_info_node *node = m->private;
2017263e 682 struct drm_device *dev = node->minor->dev;
e277a1f8 683 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 684 struct intel_engine_cs *engine;
eed29a5b 685 struct drm_i915_gem_request *req;
b4ac5afc 686 int ret, any;
de227ef0
CW		 687
688 ret = mutex_lock_interruptible(&dev->struct_mutex);
689 if (ret)
690 return ret;
2017263e 691
2d1070b2 692 any = 0;
b4ac5afc 693 for_each_engine(engine, dev_priv) {
2d1070b2
CW		 694 int count;
695
696 count = 0;
e2f80391 697 list_for_each_entry(req, &engine->request_list, list)
2d1070b2
CW		 698 count++;
699 if (count == 0)
a2c7f6fd
CW		 700 continue;
701
e2f80391
TU		 702 seq_printf(m, "%s requests: %d\n", engine->name, count);
703 list_for_each_entry(req, &engine->request_list, list) {
2d1070b2
CW		 704 struct task_struct *task;
705
706 rcu_read_lock();
707 task = NULL;
eed29a5b
DV		 708 if (req->pid)
709 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 710 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 711 req->seqno,
712 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 713 task ? task->comm : "<unknown>",
714 task ? task->pid : -1);
715 rcu_read_unlock();
c2c347a9 716 }
2d1070b2
CW		 717
718 any++;
2017263e 719 }
de227ef0
CW		 720 mutex_unlock(&dev->struct_mutex);
721
2d1070b2 722 if (any == 0)
267f0c90 723 seq_puts(m, "No requests\n");
c2c347a9 724
2017263e
BG		 725 return 0;
726}
727
b2223497 728static void i915_ring_seqno_info(struct seq_file *m,
0bc40be8 729 struct intel_engine_cs *engine)
b2223497 730{
0bc40be8 731 if (engine->get_seqno) {
20e28fba 732 seq_printf(m, "Current sequence (%s): %x\n",
0bc40be8 733 engine->name, engine->get_seqno(engine, false));
b2223497
CW		 734 }
735}
736
2017263e
BG		 737static int i915_gem_seqno_info(struct seq_file *m, void *data)
738{
9f25d007 739 struct drm_info_node *node = m->private;
2017263e 740 struct drm_device *dev = node->minor->dev;
e277a1f8 741 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 742 struct intel_engine_cs *engine;
b4ac5afc 743 int ret;
de227ef0
CW		 744
745 ret = mutex_lock_interruptible(&dev->struct_mutex);
746 if (ret)
747 return ret;
c8c8fb33 748 intel_runtime_pm_get(dev_priv);
2017263e 749
b4ac5afc 750 for_each_engine(engine, dev_priv)
e2f80391 751 i915_ring_seqno_info(m, engine);
de227ef0 752
c8c8fb33 753 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 754 mutex_unlock(&dev->struct_mutex);
755
2017263e
BG		 756 return 0;
757}
758
759
760static int i915_interrupt_info(struct seq_file *m, void *data)
761{
9f25d007 762 struct drm_info_node *node = m->private;
2017263e 763 struct drm_device *dev = node->minor->dev;
e277a1f8 764 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 765 struct intel_engine_cs *engine;
9db4a9c7 766 int ret, i, pipe;
de227ef0
CW		 767
768 ret = mutex_lock_interruptible(&dev->struct_mutex);
769 if (ret)
770 return ret;
c8c8fb33 771 intel_runtime_pm_get(dev_priv);
2017263e 772
74e1ca8c 773 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 774 seq_printf(m, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ));
776
777 seq_printf(m, "Display IER:\t%08x\n",
778 I915_READ(VLV_IER));
779 seq_printf(m, "Display IIR:\t%08x\n",
780 I915_READ(VLV_IIR));
781 seq_printf(m, "Display IIR_RW:\t%08x\n",
782 I915_READ(VLV_IIR_RW));
783 seq_printf(m, "Display IMR:\t%08x\n",
784 I915_READ(VLV_IMR));
055e393f 785 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 786 seq_printf(m, "Pipe %c stat:\t%08x\n",
787 pipe_name(pipe),
788 I915_READ(PIPESTAT(pipe)));
789
790 seq_printf(m, "Port hotplug:\t%08x\n",
791 I915_READ(PORT_HOTPLUG_EN));
792 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
793 I915_READ(VLV_DPFLIPSTAT));
794 seq_printf(m, "DPINVGTT:\t%08x\n",
795 I915_READ(DPINVGTT));
796
797 for (i = 0; i < 4; i++) {
798 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
799 i, I915_READ(GEN8_GT_IMR(i)));
800 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IIR(i)));
802 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IER(i)));
804 }
805
806 seq_printf(m, "PCU interrupt mask:\t%08x\n",
807 I915_READ(GEN8_PCU_IMR));
808 seq_printf(m, "PCU interrupt identity:\t%08x\n",
809 I915_READ(GEN8_PCU_IIR));
810 seq_printf(m, "PCU interrupt enable:\t%08x\n",
811 I915_READ(GEN8_PCU_IER));
812 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 813 seq_printf(m, "Master Interrupt Control:\t%08x\n",
814 I915_READ(GEN8_MASTER_IRQ));
815
816 for (i = 0; i < 4; i++) {
817 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
818 i, I915_READ(GEN8_GT_IMR(i)));
819 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IIR(i)));
821 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IER(i)));
823 }
824
055e393f 825 for_each_pipe(dev_priv, pipe) {
e129649b
ID		 826 enum intel_display_power_domain power_domain;
827
828 power_domain = POWER_DOMAIN_PIPE(pipe);
829 if (!intel_display_power_get_if_enabled(dev_priv,
830 power_domain)) {
22c59960
PZ		 831 seq_printf(m, "Pipe %c power disabled\n",
832 pipe_name(pipe));
833 continue;
834 }
a123f157 835 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 836 pipe_name(pipe),
837 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 838 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 839 pipe_name(pipe),
840 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 841 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 842 pipe_name(pipe),
843 I915_READ(GEN8_DE_PIPE_IER(pipe)));
e129649b
ID		 844
845 intel_display_power_put(dev_priv, power_domain);
a123f157
BW		 846 }
847
848 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IMR));
850 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IIR));
852 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
853 I915_READ(GEN8_DE_PORT_IER));
854
855 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IMR));
857 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IIR));
859 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
860 I915_READ(GEN8_DE_MISC_IER));
861
862 seq_printf(m, "PCU interrupt mask:\t%08x\n",
863 I915_READ(GEN8_PCU_IMR));
864 seq_printf(m, "PCU interrupt identity:\t%08x\n",
865 I915_READ(GEN8_PCU_IIR));
866 seq_printf(m, "PCU interrupt enable:\t%08x\n",
867 I915_READ(GEN8_PCU_IER));
868 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 869 seq_printf(m, "Display IER:\t%08x\n",
870 I915_READ(VLV_IER));
871 seq_printf(m, "Display IIR:\t%08x\n",
872 I915_READ(VLV_IIR));
873 seq_printf(m, "Display IIR_RW:\t%08x\n",
874 I915_READ(VLV_IIR_RW));
875 seq_printf(m, "Display IMR:\t%08x\n",
876 I915_READ(VLV_IMR));
055e393f 877 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 878 seq_printf(m, "Pipe %c stat:\t%08x\n",
879 pipe_name(pipe),
880 I915_READ(PIPESTAT(pipe)));
881
882 seq_printf(m, "Master IER:\t%08x\n",
883 I915_READ(VLV_MASTER_IER));
884
885 seq_printf(m, "Render IER:\t%08x\n",
886 I915_READ(GTIER));
887 seq_printf(m, "Render IIR:\t%08x\n",
888 I915_READ(GTIIR));
889 seq_printf(m, "Render IMR:\t%08x\n",
890 I915_READ(GTIMR));
891
892 seq_printf(m, "PM IER:\t\t%08x\n",
893 I915_READ(GEN6_PMIER));
894 seq_printf(m, "PM IIR:\t\t%08x\n",
895 I915_READ(GEN6_PMIIR));
896 seq_printf(m, "PM IMR:\t\t%08x\n",
897 I915_READ(GEN6_PMIMR));
898
899 seq_printf(m, "Port hotplug:\t%08x\n",
900 I915_READ(PORT_HOTPLUG_EN));
901 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
902 I915_READ(VLV_DPFLIPSTAT));
903 seq_printf(m, "DPINVGTT:\t%08x\n",
904 I915_READ(DPINVGTT));
905
906 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 907 seq_printf(m, "Interrupt enable: %08x\n",
908 I915_READ(IER));
909 seq_printf(m, "Interrupt identity: %08x\n",
910 I915_READ(IIR));
911 seq_printf(m, "Interrupt mask: %08x\n",
912 I915_READ(IMR));
055e393f 913 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 914 seq_printf(m, "Pipe %c stat: %08x\n",
915 pipe_name(pipe),
916 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 917 } else {
918 seq_printf(m, "North Display Interrupt enable: %08x\n",
919 I915_READ(DEIER));
920 seq_printf(m, "North Display Interrupt identity: %08x\n",
921 I915_READ(DEIIR));
922 seq_printf(m, "North Display Interrupt mask: %08x\n",
923 I915_READ(DEIMR));
924 seq_printf(m, "South Display Interrupt enable: %08x\n",
925 I915_READ(SDEIER));
926 seq_printf(m, "South Display Interrupt identity: %08x\n",
927 I915_READ(SDEIIR));
928 seq_printf(m, "South Display Interrupt mask: %08x\n",
929 I915_READ(SDEIMR));
930 seq_printf(m, "Graphics Interrupt enable: %08x\n",
931 I915_READ(GTIER));
932 seq_printf(m, "Graphics Interrupt identity: %08x\n",
933 I915_READ(GTIIR));
934 seq_printf(m, "Graphics Interrupt mask: %08x\n",
935 I915_READ(GTIMR));
936 }
b4ac5afc 937 for_each_engine(engine, dev_priv) {
a123f157 938 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 939 seq_printf(m,
940 "Graphics Interrupt mask (%s): %08x\n",
e2f80391 941 engine->name, I915_READ_IMR(engine));
9862e600 942 }
e2f80391 943 i915_ring_seqno_info(m, engine);
9862e600 944 }
c8c8fb33 945 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 946 mutex_unlock(&dev->struct_mutex);
947
2017263e
BG		 948 return 0;
949}
950
a6172a80
CW		 951static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
952{
9f25d007 953 struct drm_info_node *node = m->private;
a6172a80 954 struct drm_device *dev = node->minor->dev;
e277a1f8 955 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 956 int i, ret;
957
958 ret = mutex_lock_interruptible(&dev->struct_mutex);
959 if (ret)
960 return ret;
a6172a80 961
a6172a80
CW		 962 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
963 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 964 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 965
6c085a72
CW		 966 seq_printf(m, "Fence %d, pin count = %d, object = ",
967 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 968 if (obj == NULL)
267f0c90 969 seq_puts(m, "unused");
c2c347a9 970 else
05394f39 971 describe_obj(m, obj);
267f0c90 972 seq_putc(m, '\n');
a6172a80
CW		 973 }
974
05394f39 975 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 976 return 0;
977}
978
2017263e
BG		 979static int i915_hws_info(struct seq_file *m, void *data)
980{
9f25d007 981 struct drm_info_node *node = m->private;
2017263e 982 struct drm_device *dev = node->minor->dev;
e277a1f8 983 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 984 struct intel_engine_cs *engine;
1a240d4d 985 const u32 *hws;
4066c0ae
CW		 986 int i;
987
4a570db5 988 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
e2f80391 989 hws = engine->status_page.page_addr;
2017263e
BG		 990 if (hws == NULL)
991 return 0;
992
993 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
994 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
995 i * 4,
996 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
997 }
998 return 0;
999}
1000
d5442303
DV		 1001static ssize_t
1002i915_error_state_write(struct file *filp,
1003 const char __user *ubuf,
1004 size_t cnt,
1005 loff_t *ppos)
1006{
edc3d884 1007 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1008 struct drm_device *dev = error_priv->dev;
22bcfc6a 1009 int ret;
d5442303
DV		 1010
1011 DRM_DEBUG_DRIVER("Resetting error state\n");
1012
22bcfc6a
DV		 1013 ret = mutex_lock_interruptible(&dev->struct_mutex);
1014 if (ret)
1015 return ret;
1016
d5442303
DV		 1017 i915_destroy_error_state(dev);
1018 mutex_unlock(&dev->struct_mutex);
1019
1020 return cnt;
1021}
1022
1023static int i915_error_state_open(struct inode *inode, struct file *file)
1024{
1025 struct drm_device *dev = inode->i_private;
d5442303 1026 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1027
1028 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1029 if (!error_priv)
1030 return -ENOMEM;
1031
1032 error_priv->dev = dev;
1033
95d5bfb3 1034 i915_error_state_get(dev, error_priv);
d5442303 1035
edc3d884
MK		 1036 file->private_data = error_priv;
1037
1038 return 0;
d5442303
DV		 1039}
1040
1041static int i915_error_state_release(struct inode *inode, struct file *file)
1042{
edc3d884 1043 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1044
95d5bfb3 1045 i915_error_state_put(error_priv);
d5442303
DV		 1046 kfree(error_priv);
1047
edc3d884
MK		 1048 return 0;
1049}
1050
4dc955f7
MK		 1051static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1052 size_t count, loff_t *pos)
1053{
1054 struct i915_error_state_file_priv *error_priv = file->private_data;
1055 struct drm_i915_error_state_buf error_str;
1056 loff_t tmp_pos = 0;
1057 ssize_t ret_count = 0;
1058 int ret;
1059
0a4cd7c8 1060 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1061 if (ret)
1062 return ret;
edc3d884 1063
fc16b48b 1064 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1065 if (ret)
1066 goto out;
1067
edc3d884
MK		 1068 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1069 error_str.buf,
1070 error_str.bytes);
1071
1072 if (ret_count < 0)
1073 ret = ret_count;
1074 else
1075 *pos = error_str.start + ret_count;
1076out:
4dc955f7 1077 i915_error_state_buf_release(&error_str);
edc3d884 1078 return ret ?: ret_count;
d5442303
DV		 1079}
1080
1081static const struct file_operations i915_error_state_fops = {
1082 .owner = THIS_MODULE,
1083 .open = i915_error_state_open,
edc3d884 1084 .read = i915_error_state_read,
d5442303
DV		 1085 .write = i915_error_state_write,
1086 .llseek = default_llseek,
1087 .release = i915_error_state_release,
1088};
1089
647416f9
KC		 1090static int
1091i915_next_seqno_get(void *data, u64 *val)
40633219 1092{
647416f9 1093 struct drm_device *dev = data;
e277a1f8 1094 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1095 int ret;
1096
1097 ret = mutex_lock_interruptible(&dev->struct_mutex);
1098 if (ret)
1099 return ret;
1100
647416f9 1101 *val = dev_priv->next_seqno;
40633219
MK		 1102 mutex_unlock(&dev->struct_mutex);
1103
647416f9 1104 return 0;
40633219
MK		 1105}
1106
647416f9
KC		 1107static int
1108i915_next_seqno_set(void *data, u64 val)
1109{
1110 struct drm_device *dev = data;
40633219
MK		 1111 int ret;
1112
40633219
MK		 1113 ret = mutex_lock_interruptible(&dev->struct_mutex);
1114 if (ret)
1115 return ret;
1116
e94fbaa8 1117 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1118 mutex_unlock(&dev->struct_mutex);
1119
647416f9 1120 return ret;
40633219
MK		 1121}
1122
647416f9
KC		 1123DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1124 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1125 "0x%llx\n");
40633219 1126
adb4bd12 1127static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1128{
9f25d007 1129 struct drm_info_node *node = m->private;
f97108d1 1130 struct drm_device *dev = node->minor->dev;
e277a1f8 1131 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1132 int ret = 0;
1133
1134 intel_runtime_pm_get(dev_priv);
3b8d8d91 1135
5c9669ce
TR		 1136 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1137
3b8d8d91
JB		 1138 if (IS_GEN5(dev)) {
1139 u16 rgvswctl = I915_READ16(MEMSWCTL);
1140 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1141
1142 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1143 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1144 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1145 MEMSTAT_VID_SHIFT);
1146 seq_printf(m, "Current P-state: %d\n",
1147 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
666a4537
WB		 1148 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1149 u32 freq_sts;
1150
1151 mutex_lock(&dev_priv->rps.hw_lock);
1152 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1153 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1154 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1155
1156 seq_printf(m, "actual GPU freq: %d MHz\n",
1157 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1158
1159 seq_printf(m, "current GPU freq: %d MHz\n",
1160 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1161
1162 seq_printf(m, "max GPU freq: %d MHz\n",
1163 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1164
1165 seq_printf(m, "min GPU freq: %d MHz\n",
1166 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1167
1168 seq_printf(m, "idle GPU freq: %d MHz\n",
1169 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1170
1171 seq_printf(m,
1172 "efficient (RPe) frequency: %d MHz\n",
1173 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1174 mutex_unlock(&dev_priv->rps.hw_lock);
1175 } else if (INTEL_INFO(dev)->gen >= 6) {
35040562
BP		 1176 u32 rp_state_limits;
1177 u32 gt_perf_status;
1178 u32 rp_state_cap;
0d8f9491 1179 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1180 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1181 u32 rpupei, rpcurup, rpprevup;
1182 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1183 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1184 int max_freq;
1185
35040562
BP		 1186 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1187 if (IS_BROXTON(dev)) {
1188 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1189 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1190 } else {
1191 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1192 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1193 }
1194
3b8d8d91 1195 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1196 ret = mutex_lock_interruptible(&dev->struct_mutex);
1197 if (ret)
c8c8fb33 1198 goto out;
d1ebd816 1199
59bad947 1200 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1201
8e8c06cd 1202 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1203 if (IS_GEN9(dev))
1204 reqf >>= 23;
1205 else {
1206 reqf &= ~GEN6_TURBO_DISABLE;
1207 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1208 reqf >>= 24;
1209 else
1210 reqf >>= 25;
1211 }
7c59a9c1 1212 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1213
0d8f9491
CW		 1214 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1215 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1216 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1217
ccab5c82
JB		 1218 rpstat = I915_READ(GEN6_RPSTAT1);
1219 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1220 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1221 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1222 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1223 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1224 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1225 if (IS_GEN9(dev))
1226 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1227 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1228 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1229 else
1230 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1231 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1232
59bad947 1233 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1234 mutex_unlock(&dev->struct_mutex);
1235
9dd3c605
PZ		 1236 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1237 pm_ier = I915_READ(GEN6_PMIER);
1238 pm_imr = I915_READ(GEN6_PMIMR);
1239 pm_isr = I915_READ(GEN6_PMISR);
1240 pm_iir = I915_READ(GEN6_PMIIR);
1241 pm_mask = I915_READ(GEN6_PMINTRMSK);
1242 } else {
1243 pm_ier = I915_READ(GEN8_GT_IER(2));
1244 pm_imr = I915_READ(GEN8_GT_IMR(2));
1245 pm_isr = I915_READ(GEN8_GT_ISR(2));
1246 pm_iir = I915_READ(GEN8_GT_IIR(2));
1247 pm_mask = I915_READ(GEN6_PMINTRMSK);
1248 }
0d8f9491 1249 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1250 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1251 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1252 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1253 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1254 seq_printf(m, "Render p-state VID: %d\n",
1255 gt_perf_status & 0xff);
1256 seq_printf(m, "Render p-state limit: %d\n",
1257 rp_state_limits & 0xff);
0d8f9491
CW		 1258 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1259 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1260 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1261 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1262 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1263 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1264 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1265 GEN6_CURICONT_MASK);
1266 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1267 GEN6_CURBSYTAVG_MASK);
1268 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1269 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1270 seq_printf(m, "Up threshold: %d%%\n",
1271 dev_priv->rps.up_threshold);
1272
ccab5c82
JB		 1273 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1274 GEN6_CURIAVG_MASK);
1275 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1276 GEN6_CURBSYTAVG_MASK);
1277 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1278 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1279 seq_printf(m, "Down threshold: %d%%\n",
1280 dev_priv->rps.down_threshold);
3b8d8d91 1281
35040562
BP		 1282 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1283 rp_state_cap >> 16) & 0xff;
ef11bdb3
RV		 1284 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1285 GEN9_FREQ_SCALER : 1);
3b8d8d91 1286 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1287 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1288
1289 max_freq = (rp_state_cap & 0xff00) >> 8;
ef11bdb3
RV		 1290 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1291 GEN9_FREQ_SCALER : 1);
3b8d8d91 1292 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1293 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1294
35040562
BP		 1295 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1296 rp_state_cap >> 0) & 0xff;
ef11bdb3
RV		 1297 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1298 GEN9_FREQ_SCALER : 1);
3b8d8d91 1299 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1300 intel_gpu_freq(dev_priv, max_freq));
31c77388 1301 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1302 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1303
d86ed34a
CW		 1304 seq_printf(m, "Current freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1306 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1307 seq_printf(m, "Idle freq: %d MHz\n",
1308 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1309 seq_printf(m, "Min freq: %d MHz\n",
1310 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1311 seq_printf(m, "Max freq: %d MHz\n",
1312 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1313 seq_printf(m,
1314 "efficient (RPe) frequency: %d MHz\n",
1315 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
3b8d8d91 1316 } else {
267f0c90 1317 seq_puts(m, "no P-state info available\n");
3b8d8d91 1318 }
f97108d1 1319
1170f28c
MK		 1320 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1321 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1322 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1323
c8c8fb33
PZ		 1324out:
1325 intel_runtime_pm_put(dev_priv);
1326 return ret;
f97108d1
JB		 1327}
1328
f654449a
CW		 1329static int i915_hangcheck_info(struct seq_file *m, void *unused)
1330{
1331 struct drm_info_node *node = m->private;
ebbc7546
MK		 1332 struct drm_device *dev = node->minor->dev;
1333 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1334 struct intel_engine_cs *engine;
666796da
TU		 1335 u64 acthd[I915_NUM_ENGINES];
1336 u32 seqno[I915_NUM_ENGINES];
61642ff0 1337 u32 instdone[I915_NUM_INSTDONE_REG];
c3232b18
DG		 1338 enum intel_engine_id id;
1339 int j;
f654449a
CW		 1340
1341 if (!i915.enable_hangcheck) {
1342 seq_printf(m, "Hangcheck disabled\n");
1343 return 0;
1344 }
1345
ebbc7546
MK		 1346 intel_runtime_pm_get(dev_priv);
1347
c3232b18
DG		 1348 for_each_engine_id(engine, dev_priv, id) {
1349 seqno[id] = engine->get_seqno(engine, false);
1350 acthd[id] = intel_ring_get_active_head(engine);
ebbc7546
MK		 1351 }
1352
61642ff0
MK		 1353 i915_get_extra_instdone(dev, instdone);
1354
ebbc7546
MK		 1355 intel_runtime_pm_put(dev_priv);
1356
f654449a
CW		 1357 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1358 seq_printf(m, "Hangcheck active, fires in %dms\n",
1359 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1360 jiffies));
1361 } else
1362 seq_printf(m, "Hangcheck inactive\n");
1363
c3232b18 1364 for_each_engine_id(engine, dev_priv, id) {
e2f80391 1365 seq_printf(m, "%s:\n", engine->name);
f654449a 1366 seq_printf(m, "\tseqno = %x [current %x]\n",
c3232b18 1367 engine->hangcheck.seqno, seqno[id]);
f654449a 1368 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
e2f80391 1369 (long long)engine->hangcheck.acthd,
c3232b18 1370 (long long)acthd[id]);
e2f80391
TU		 1371 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1372 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
61642ff0 1373
e2f80391 1374 if (engine->id == RCS) {
61642ff0
MK		 1375 seq_puts(m, "\tinstdone read =");
1376
1377 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1378 seq_printf(m, " 0x%08x", instdone[j]);
1379
1380 seq_puts(m, "\n\tinstdone accu =");
1381
1382 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1383 seq_printf(m, " 0x%08x",
e2f80391 1384 engine->hangcheck.instdone[j]);
61642ff0
MK		 1385
1386 seq_puts(m, "\n");
1387 }
f654449a
CW		 1388 }
1389
1390 return 0;
1391}
1392
4d85529d 1393static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1394{
9f25d007 1395 struct drm_info_node *node = m->private;
f97108d1 1396 struct drm_device *dev = node->minor->dev;
e277a1f8 1397 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1398 u32 rgvmodectl, rstdbyctl;
1399 u16 crstandvid;
1400 int ret;
1401
1402 ret = mutex_lock_interruptible(&dev->struct_mutex);
1403 if (ret)
1404 return ret;
c8c8fb33 1405 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1406
1407 rgvmodectl = I915_READ(MEMMODECTL);
1408 rstdbyctl = I915_READ(RSTDBYCTL);
1409 crstandvid = I915_READ16(CRSTANDVID);
1410
c8c8fb33 1411 intel_runtime_pm_put(dev_priv);
616fdb5a 1412 mutex_unlock(&dev->struct_mutex);
f97108d1 1413
742f491d 1414 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1415 seq_printf(m, "Boost freq: %d\n",
1416 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1417 MEMMODE_BOOST_FREQ_SHIFT);
1418 seq_printf(m, "HW control enabled: %s\n",
742f491d 1419 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1420 seq_printf(m, "SW control enabled: %s\n",
742f491d 1421 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1422 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1423 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1424 seq_printf(m, "Starting frequency: P%d\n",
1425 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1426 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1427 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1428 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1429 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1430 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1431 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1432 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1433 seq_puts(m, "Current RS state: ");
88271da3
JB		 1434 switch (rstdbyctl & RSX_STATUS_MASK) {
1435 case RSX_STATUS_ON:
267f0c90 1436 seq_puts(m, "on\n");
88271da3
JB		 1437 break;
1438 case RSX_STATUS_RC1:
267f0c90 1439 seq_puts(m, "RC1\n");
88271da3
JB		 1440 break;
1441 case RSX_STATUS_RC1E:
267f0c90 1442 seq_puts(m, "RC1E\n");
88271da3
JB		 1443 break;
1444 case RSX_STATUS_RS1:
267f0c90 1445 seq_puts(m, "RS1\n");
88271da3
JB		 1446 break;
1447 case RSX_STATUS_RS2:
267f0c90 1448 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1449 break;
1450 case RSX_STATUS_RS3:
267f0c90 1451 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1452 break;
1453 default:
267f0c90 1454 seq_puts(m, "unknown\n");
88271da3
JB		 1455 break;
1456 }
f97108d1
JB		 1457
1458 return 0;
1459}
1460
f65367b5 1461static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1462{
b2cff0db
CW		 1463 struct drm_info_node *node = m->private;
1464 struct drm_device *dev = node->minor->dev;
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1466 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1467 int i;
1468
1469 spin_lock_irq(&dev_priv->uncore.lock);
1470 for_each_fw_domain(fw_domain, dev_priv, i) {
1471 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1472 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1473 fw_domain->wake_count);
1474 }
1475 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1476
b2cff0db
CW		 1477 return 0;
1478}
1479
1480static int vlv_drpc_info(struct seq_file *m)
1481{
9f25d007 1482 struct drm_info_node *node = m->private;
669ab5aa
D		 1483 struct drm_device *dev = node->minor->dev;
1484 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1485 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1486
d46c0517
ID		 1487 intel_runtime_pm_get(dev_priv);
1488
6b312cd3 1489 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1490 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1491 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1492
d46c0517
ID		 1493 intel_runtime_pm_put(dev_priv);
1494
669ab5aa
D		 1495 seq_printf(m, "Video Turbo Mode: %s\n",
1496 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1497 seq_printf(m, "Turbo enabled: %s\n",
1498 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1499 seq_printf(m, "HW control enabled: %s\n",
1500 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1501 seq_printf(m, "SW control enabled: %s\n",
1502 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1503 GEN6_RP_MEDIA_SW_MODE));
1504 seq_printf(m, "RC6 Enabled: %s\n",
1505 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1506 GEN6_RC_CTL_EI_MODE(1))));
1507 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1508 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1509 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1510 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1511
9cc19be5
ID		 1512 seq_printf(m, "Render RC6 residency since boot: %u\n",
1513 I915_READ(VLV_GT_RENDER_RC6));
1514 seq_printf(m, "Media RC6 residency since boot: %u\n",
1515 I915_READ(VLV_GT_MEDIA_RC6));
1516
f65367b5 1517 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1518}
1519
4d85529d
BW		 1520static int gen6_drpc_info(struct seq_file *m)
1521{
9f25d007 1522 struct drm_info_node *node = m->private;
4d85529d
BW		 1523 struct drm_device *dev = node->minor->dev;
1524 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1525 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1526 unsigned forcewake_count;
aee56cff 1527 int count = 0, ret;
4d85529d
BW		 1528
1529 ret = mutex_lock_interruptible(&dev->struct_mutex);
1530 if (ret)
1531 return ret;
c8c8fb33 1532 intel_runtime_pm_get(dev_priv);
4d85529d 1533
907b28c5 1534 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1535 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1536 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1537
1538 if (forcewake_count) {
267f0c90
DL		 1539 seq_puts(m, "RC information inaccurate because somebody "
1540 "holds a forcewake reference \n");
4d85529d
BW		 1541 } else {
1542 /* NB: we cannot use forcewake, else we read the wrong values */
1543 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1544 udelay(10);
1545 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1546 }
1547
75aa3f63 1548 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
ed71f1b4 1549 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1550
1551 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1552 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1553 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1554 mutex_lock(&dev_priv->rps.hw_lock);
1555 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1556 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1557
c8c8fb33
PZ		 1558 intel_runtime_pm_put(dev_priv);
1559
4d85529d
BW		 1560 seq_printf(m, "Video Turbo Mode: %s\n",
1561 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1562 seq_printf(m, "HW control enabled: %s\n",
1563 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1564 seq_printf(m, "SW control enabled: %s\n",
1565 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1566 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1567 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1568 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1569 seq_printf(m, "RC6 Enabled: %s\n",
1570 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1571 seq_printf(m, "Deep RC6 Enabled: %s\n",
1572 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1573 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1574 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1575 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1576 switch (gt_core_status & GEN6_RCn_MASK) {
1577 case GEN6_RC0:
1578 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1579 seq_puts(m, "Core Power Down\n");
4d85529d 1580 else
267f0c90 1581 seq_puts(m, "on\n");
4d85529d
BW		 1582 break;
1583 case GEN6_RC3:
267f0c90 1584 seq_puts(m, "RC3\n");
4d85529d
BW		 1585 break;
1586 case GEN6_RC6:
267f0c90 1587 seq_puts(m, "RC6\n");
4d85529d
BW		 1588 break;
1589 case GEN6_RC7:
267f0c90 1590 seq_puts(m, "RC7\n");
4d85529d
BW		 1591 break;
1592 default:
267f0c90 1593 seq_puts(m, "Unknown\n");
4d85529d
BW		 1594 break;
1595 }
1596
1597 seq_printf(m, "Core Power Down: %s\n",
1598 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1599
1600 /* Not exactly sure what this is */
1601 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1602 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1603 seq_printf(m, "RC6 residency since boot: %u\n",
1604 I915_READ(GEN6_GT_GFX_RC6));
1605 seq_printf(m, "RC6+ residency since boot: %u\n",
1606 I915_READ(GEN6_GT_GFX_RC6p));
1607 seq_printf(m, "RC6++ residency since boot: %u\n",
1608 I915_READ(GEN6_GT_GFX_RC6pp));
1609
ecd8faea
BW		 1610 seq_printf(m, "RC6 voltage: %dmV\n",
1611 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1612 seq_printf(m, "RC6+ voltage: %dmV\n",
1613 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1614 seq_printf(m, "RC6++ voltage: %dmV\n",
1615 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1616 return 0;
1617}
1618
1619static int i915_drpc_info(struct seq_file *m, void *unused)
1620{
9f25d007 1621 struct drm_info_node *node = m->private;
4d85529d
BW		 1622 struct drm_device *dev = node->minor->dev;
1623
666a4537 1624 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
669ab5aa 1625 return vlv_drpc_info(m);
ac66cf4b 1626 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1627 return gen6_drpc_info(m);
1628 else
1629 return ironlake_drpc_info(m);
1630}
1631
9a851789
DV		 1632static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1633{
1634 struct drm_info_node *node = m->private;
1635 struct drm_device *dev = node->minor->dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637
1638 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1639 dev_priv->fb_tracking.busy_bits);
1640
1641 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1642 dev_priv->fb_tracking.flip_bits);
1643
1644 return 0;
1645}
1646
b5e50c3f
JB		 1647static int i915_fbc_status(struct seq_file *m, void *unused)
1648{
9f25d007 1649 struct drm_info_node *node = m->private;
b5e50c3f 1650 struct drm_device *dev = node->minor->dev;
e277a1f8 1651 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1652
3a77c4c4 1653 if (!HAS_FBC(dev)) {
267f0c90 1654 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1655 return 0;
1656 }
1657
36623ef8 1658 intel_runtime_pm_get(dev_priv);
25ad93fd 1659 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1660
0e631adc 1661 if (intel_fbc_is_active(dev_priv))
267f0c90 1662 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1663 else
1664 seq_printf(m, "FBC disabled: %s\n",
bf6189c6 1665 dev_priv->fbc.no_fbc_reason);
36623ef8 1666
31b9df10
PZ		 1667 if (INTEL_INFO(dev_priv)->gen >= 7)
1668 seq_printf(m, "Compressing: %s\n",
1669 yesno(I915_READ(FBC_STATUS2) &
1670 FBC_COMPRESSION_MASK));
1671
25ad93fd 1672 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1673 intel_runtime_pm_put(dev_priv);
1674
b5e50c3f
JB		 1675 return 0;
1676}
1677
da46f936
RV		 1678static int i915_fbc_fc_get(void *data, u64 *val)
1679{
1680 struct drm_device *dev = data;
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682
1683 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1684 return -ENODEV;
1685
da46f936 1686 *val = dev_priv->fbc.false_color;
da46f936
RV		 1687
1688 return 0;
1689}
1690
1691static int i915_fbc_fc_set(void *data, u64 val)
1692{
1693 struct drm_device *dev = data;
1694 struct drm_i915_private *dev_priv = dev->dev_private;
1695 u32 reg;
1696
1697 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1698 return -ENODEV;
1699
25ad93fd 1700 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1701
1702 reg = I915_READ(ILK_DPFC_CONTROL);
1703 dev_priv->fbc.false_color = val;
1704
1705 I915_WRITE(ILK_DPFC_CONTROL, val ?
1706 (reg | FBC_CTL_FALSE_COLOR) :
1707 (reg & ~FBC_CTL_FALSE_COLOR));
1708
25ad93fd 1709 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1710 return 0;
1711}
1712
1713DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1714 i915_fbc_fc_get, i915_fbc_fc_set,
1715 "%llu\n");
1716
92d44621
PZ		 1717static int i915_ips_status(struct seq_file *m, void *unused)
1718{
9f25d007 1719 struct drm_info_node *node = m->private;
92d44621
PZ		 1720 struct drm_device *dev = node->minor->dev;
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722
f5adf94e 1723 if (!HAS_IPS(dev)) {
92d44621
PZ		 1724 seq_puts(m, "not supported\n");
1725 return 0;
1726 }
1727
36623ef8
PZ		 1728 intel_runtime_pm_get(dev_priv);
1729
0eaa53f0
RV		 1730 seq_printf(m, "Enabled by kernel parameter: %s\n",
1731 yesno(i915.enable_ips));
1732
1733 if (INTEL_INFO(dev)->gen >= 8) {
1734 seq_puts(m, "Currently: unknown\n");
1735 } else {
1736 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1737 seq_puts(m, "Currently: enabled\n");
1738 else
1739 seq_puts(m, "Currently: disabled\n");
1740 }
92d44621 1741
36623ef8
PZ		 1742 intel_runtime_pm_put(dev_priv);
1743
92d44621
PZ		 1744 return 0;
1745}
1746
4a9bef37
JB		 1747static int i915_sr_status(struct seq_file *m, void *unused)
1748{
9f25d007 1749 struct drm_info_node *node = m->private;
4a9bef37 1750 struct drm_device *dev = node->minor->dev;
e277a1f8 1751 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1752 bool sr_enabled = false;
1753
36623ef8
PZ		 1754 intel_runtime_pm_get(dev_priv);
1755
1398261a 1756 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1757 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1758 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1759 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1760 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1761 else if (IS_I915GM(dev))
1762 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1763 else if (IS_PINEVIEW(dev))
1764 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
666a4537 1765 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
77b64555 1766 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1767
36623ef8
PZ		 1768 intel_runtime_pm_put(dev_priv);
1769
5ba2aaaa
CW		 1770 seq_printf(m, "self-refresh: %s\n",
1771 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1772
1773 return 0;
1774}
1775
7648fa99
JB		 1776static int i915_emon_status(struct seq_file *m, void *unused)
1777{
9f25d007 1778 struct drm_info_node *node = m->private;
7648fa99 1779 struct drm_device *dev = node->minor->dev;
e277a1f8 1780 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1781 unsigned long temp, chipset, gfx;
de227ef0
CW		 1782 int ret;
1783
582be6b4
CW		 1784 if (!IS_GEN5(dev))
1785 return -ENODEV;
1786
de227ef0
CW		 1787 ret = mutex_lock_interruptible(&dev->struct_mutex);
1788 if (ret)
1789 return ret;
7648fa99
JB		 1790
1791 temp = i915_mch_val(dev_priv);
1792 chipset = i915_chipset_val(dev_priv);
1793 gfx = i915_gfx_val(dev_priv);
de227ef0 1794 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1795
1796 seq_printf(m, "GMCH temp: %ld\n", temp);
1797 seq_printf(m, "Chipset power: %ld\n", chipset);
1798 seq_printf(m, "GFX power: %ld\n", gfx);
1799 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1800
1801 return 0;
1802}
1803
23b2f8bb
JB		 1804static int i915_ring_freq_table(struct seq_file *m, void *unused)
1805{
9f25d007 1806 struct drm_info_node *node = m->private;
23b2f8bb 1807 struct drm_device *dev = node->minor->dev;
e277a1f8 1808 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1809 int ret = 0;
23b2f8bb 1810 int gpu_freq, ia_freq;
f936ec34 1811 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1812
97d3308a 1813 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1814 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1815 return 0;
1816 }
1817
5bfa0199
PZ		 1818 intel_runtime_pm_get(dev_priv);
1819
5c9669ce
TR		 1820 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1821
4fc688ce 1822 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1823 if (ret)
5bfa0199 1824 goto out;
23b2f8bb 1825
ef11bdb3 1826 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
f936ec34
AG		 1827 /* Convert GT frequency to 50 HZ units */
1828 min_gpu_freq =
1829 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1830 max_gpu_freq =
1831 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1832 } else {
1833 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1834 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1835 }
1836
267f0c90 1837 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1838
f936ec34 1839 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1840 ia_freq = gpu_freq;
1841 sandybridge_pcode_read(dev_priv,
1842 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1843 &ia_freq);
3ebecd07 1844 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34 1845 intel_gpu_freq(dev_priv, (gpu_freq *
ef11bdb3
RV		 1846 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1847 GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1848 ((ia_freq >> 0) & 0xff) * 100,
1849 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1850 }
1851
4fc688ce 1852 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1853
5bfa0199
PZ		 1854out:
1855 intel_runtime_pm_put(dev_priv);
1856 return ret;
23b2f8bb
JB		 1857}
1858
44834a67
CW		 1859static int i915_opregion(struct seq_file *m, void *unused)
1860{
9f25d007 1861 struct drm_info_node *node = m->private;
44834a67 1862 struct drm_device *dev = node->minor->dev;
e277a1f8 1863 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67
CW		 1864 struct intel_opregion *opregion = &dev_priv->opregion;
1865 int ret;
1866
1867 ret = mutex_lock_interruptible(&dev->struct_mutex);
1868 if (ret)
0d38f009 1869 goto out;
44834a67 1870
2455a8e4
JN		 1871 if (opregion->header)
1872 seq_write(m, opregion->header, OPREGION_SIZE);
44834a67
CW		 1873
1874 mutex_unlock(&dev->struct_mutex);
1875
0d38f009 1876out:
44834a67
CW		 1877 return 0;
1878}
1879
ada8f955
JN		 1880static int i915_vbt(struct seq_file *m, void *unused)
1881{
1882 struct drm_info_node *node = m->private;
1883 struct drm_device *dev = node->minor->dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 struct intel_opregion *opregion = &dev_priv->opregion;
1886
1887 if (opregion->vbt)
1888 seq_write(m, opregion->vbt, opregion->vbt_size);
1889
1890 return 0;
1891}
1892
37811fcc
CW		 1893static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1894{
9f25d007 1895 struct drm_info_node *node = m->private;
37811fcc 1896 struct drm_device *dev = node->minor->dev;
b13b8402 1897 struct intel_framebuffer *fbdev_fb = NULL;
3a58ee10 1898 struct drm_framebuffer *drm_fb;
188c1ab7
CW		 1899 int ret;
1900
1901 ret = mutex_lock_interruptible(&dev->struct_mutex);
1902 if (ret)
1903 return ret;
37811fcc 1904
0695726e 1905#ifdef CONFIG_DRM_FBDEV_EMULATION
b13b8402
NS		 1906 if (to_i915(dev)->fbdev) {
1907 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1908
1909 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1910 fbdev_fb->base.width,
1911 fbdev_fb->base.height,
1912 fbdev_fb->base.depth,
1913 fbdev_fb->base.bits_per_pixel,
1914 fbdev_fb->base.modifier[0],
1915 atomic_read(&fbdev_fb->base.refcount.refcount));
1916 describe_obj(m, fbdev_fb->obj);
1917 seq_putc(m, '\n');
1918 }
4520f53a 1919#endif
37811fcc 1920
4b096ac1 1921 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10 1922 drm_for_each_fb(drm_fb, dev) {
b13b8402
NS		 1923 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1924 if (fb == fbdev_fb)
37811fcc
CW		 1925 continue;
1926
c1ca506d 1927 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1928 fb->base.width,
1929 fb->base.height,
1930 fb->base.depth,
623f9783 1931 fb->base.bits_per_pixel,
c1ca506d 1932 fb->base.modifier[0],
623f9783 1933 atomic_read(&fb->base.refcount.refcount));
05394f39 1934 describe_obj(m, fb->obj);
267f0c90 1935 seq_putc(m, '\n');
37811fcc 1936 }
4b096ac1 1937 mutex_unlock(&dev->mode_config.fb_lock);
188c1ab7 1938 mutex_unlock(&dev->struct_mutex);
37811fcc
CW		 1939
1940 return 0;
1941}
1942
c9fe99bd
OM		 1943static void describe_ctx_ringbuf(struct seq_file *m,
1944 struct intel_ringbuffer *ringbuf)
1945{
1946 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1947 ringbuf->space, ringbuf->head, ringbuf->tail,
1948 ringbuf->last_retired_head);
1949}
1950
e76d3630
BW		 1951static int i915_context_status(struct seq_file *m, void *unused)
1952{
9f25d007 1953 struct drm_info_node *node = m->private;
e76d3630 1954 struct drm_device *dev = node->minor->dev;
e277a1f8 1955 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 1956 struct intel_engine_cs *engine;
273497e5 1957 struct intel_context *ctx;
c3232b18
DG		 1958 enum intel_engine_id id;
1959 int ret;
e76d3630 1960
f3d28878 1961 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1962 if (ret)
1963 return ret;
1964
a33afea5 1965 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1966 if (!i915.enable_execlists &&
1967 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1968 continue;
1969
a33afea5 1970 seq_puts(m, "HW context ");
3ccfd19d 1971 describe_ctx(m, ctx);
e28e404c
DG		 1972 if (ctx == dev_priv->kernel_context)
1973 seq_printf(m, "(kernel context) ");
c9fe99bd
OM		 1974
1975 if (i915.enable_execlists) {
1976 seq_putc(m, '\n');
c3232b18 1977 for_each_engine_id(engine, dev_priv, id) {
c9fe99bd 1978 struct drm_i915_gem_object *ctx_obj =
c3232b18 1979 ctx->engine[id].state;
c9fe99bd 1980 struct intel_ringbuffer *ringbuf =
c3232b18 1981 ctx->engine[id].ringbuf;
c9fe99bd 1982
e2f80391 1983 seq_printf(m, "%s: ", engine->name);
c9fe99bd
OM		 1984 if (ctx_obj)
1985 describe_obj(m, ctx_obj);
1986 if (ringbuf)
1987 describe_ctx_ringbuf(m, ringbuf);
1988 seq_putc(m, '\n');
1989 }
1990 } else {
1991 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1992 }
a33afea5 1993
a33afea5 1994 seq_putc(m, '\n');
a168c293
BW		 1995 }
1996
f3d28878 1997 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1998
1999 return 0;
2000}
2001
064ca1d2 2002static void i915_dump_lrc_obj(struct seq_file *m,
ca82580c 2003 struct intel_context *ctx,
0bc40be8 2004 struct intel_engine_cs *engine)
064ca1d2
TD		 2005{
2006 struct page *page;
2007 uint32_t *reg_state;
2008 int j;
0bc40be8 2009 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
064ca1d2
TD		 2010 unsigned long ggtt_offset = 0;
2011
2012 if (ctx_obj == NULL) {
2013 seq_printf(m, "Context on %s with no gem object\n",
0bc40be8 2014 engine->name);
064ca1d2
TD		 2015 return;
2016 }
2017
0bc40be8
TU		 2018 seq_printf(m, "CONTEXT: %s %u\n", engine->name,
2019 intel_execlists_ctx_id(ctx, engine));
064ca1d2
TD		 2020
2021 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2022 seq_puts(m, "\tNot bound in GGTT\n");
2023 else
2024 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2025
2026 if (i915_gem_object_get_pages(ctx_obj)) {
2027 seq_puts(m, "\tFailed to get pages for context object\n");
2028 return;
2029 }
2030
d1675198 2031 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
064ca1d2
TD		 2032 if (!WARN_ON(page == NULL)) {
2033 reg_state = kmap_atomic(page);
2034
2035 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2036 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2037 ggtt_offset + 4096 + (j * 4),
2038 reg_state[j], reg_state[j + 1],
2039 reg_state[j + 2], reg_state[j + 3]);
2040 }
2041 kunmap_atomic(reg_state);
2042 }
2043
2044 seq_putc(m, '\n');
2045}
2046
c0ab1ae9
BW		 2047static int i915_dump_lrc(struct seq_file *m, void *unused)
2048{
2049 struct drm_info_node *node = (struct drm_info_node *) m->private;
2050 struct drm_device *dev = node->minor->dev;
2051 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2052 struct intel_engine_cs *engine;
c0ab1ae9 2053 struct intel_context *ctx;
b4ac5afc 2054 int ret;
c0ab1ae9
BW		 2055
2056 if (!i915.enable_execlists) {
2057 seq_printf(m, "Logical Ring Contexts are disabled\n");
2058 return 0;
2059 }
2060
2061 ret = mutex_lock_interruptible(&dev->struct_mutex);
2062 if (ret)
2063 return ret;
2064
e28e404c
DG		 2065 list_for_each_entry(ctx, &dev_priv->context_list, link)
2066 if (ctx != dev_priv->kernel_context)
b4ac5afc 2067 for_each_engine(engine, dev_priv)
e2f80391 2068 i915_dump_lrc_obj(m, ctx, engine);
c0ab1ae9
BW		 2069
2070 mutex_unlock(&dev->struct_mutex);
2071
2072 return 0;
2073}
2074
4ba70e44
OM		 2075static int i915_execlists(struct seq_file *m, void *data)
2076{
2077 struct drm_info_node *node = (struct drm_info_node *)m->private;
2078 struct drm_device *dev = node->minor->dev;
2079 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2080 struct intel_engine_cs *engine;
4ba70e44
OM		 2081 u32 status_pointer;
2082 u8 read_pointer;
2083 u8 write_pointer;
2084 u32 status;
2085 u32 ctx_id;
2086 struct list_head *cursor;
b4ac5afc 2087 int i, ret;
4ba70e44
OM		 2088
2089 if (!i915.enable_execlists) {
2090 seq_puts(m, "Logical Ring Contexts are disabled\n");
2091 return 0;
2092 }
2093
2094 ret = mutex_lock_interruptible(&dev->struct_mutex);
2095 if (ret)
2096 return ret;
2097
fc0412ec
MT		 2098 intel_runtime_pm_get(dev_priv);
2099
b4ac5afc 2100 for_each_engine(engine, dev_priv) {
6d3d8274 2101 struct drm_i915_gem_request *head_req = NULL;
4ba70e44 2102 int count = 0;
4ba70e44 2103
e2f80391 2104 seq_printf(m, "%s\n", engine->name);
4ba70e44 2105
e2f80391
TU		 2106 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2107 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
4ba70e44
OM		 2108 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2109 status, ctx_id);
2110
e2f80391 2111 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
4ba70e44
OM		 2112 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2113
e2f80391 2114 read_pointer = engine->next_context_status_buffer;
5590a5f0 2115 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
4ba70e44 2116 if (read_pointer > write_pointer)
5590a5f0 2117 write_pointer += GEN8_CSB_ENTRIES;
4ba70e44
OM		 2118 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2119 read_pointer, write_pointer);
2120
5590a5f0 2121 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
e2f80391
TU		 2122 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2123 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
4ba70e44
OM		 2124
2125 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2126 i, status, ctx_id);
2127 }
2128
27af5eea 2129 spin_lock_bh(&engine->execlist_lock);
e2f80391 2130 list_for_each(cursor, &engine->execlist_queue)
4ba70e44 2131 count++;
e2f80391
TU		 2132 head_req = list_first_entry_or_null(&engine->execlist_queue,
2133 struct drm_i915_gem_request,
2134 execlist_link);
27af5eea 2135 spin_unlock_bh(&engine->execlist_lock);
4ba70e44
OM		 2136
2137 seq_printf(m, "\t%d requests in queue\n", count);
2138 if (head_req) {
4ba70e44 2139 seq_printf(m, "\tHead request id: %u\n",
e2f80391 2140 intel_execlists_ctx_id(head_req->ctx, engine));
4ba70e44 2141 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2142 head_req->tail);
4ba70e44
OM		 2143 }
2144
2145 seq_putc(m, '\n');
2146 }
2147
fc0412ec 2148 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2149 mutex_unlock(&dev->struct_mutex);
2150
2151 return 0;
2152}
2153
ea16a3cd
DV		 2154static const char *swizzle_string(unsigned swizzle)
2155{
aee56cff 2156 switch (swizzle) {
ea16a3cd
DV		 2157 case I915_BIT_6_SWIZZLE_NONE:
2158 return "none";
2159 case I915_BIT_6_SWIZZLE_9:
2160 return "bit9";
2161 case I915_BIT_6_SWIZZLE_9_10:
2162 return "bit9/bit10";
2163 case I915_BIT_6_SWIZZLE_9_11:
2164 return "bit9/bit11";
2165 case I915_BIT_6_SWIZZLE_9_10_11:
2166 return "bit9/bit10/bit11";
2167 case I915_BIT_6_SWIZZLE_9_17:
2168 return "bit9/bit17";
2169 case I915_BIT_6_SWIZZLE_9_10_17:
2170 return "bit9/bit10/bit17";
2171 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2172 return "unknown";
ea16a3cd
DV		 2173 }
2174
2175 return "bug";
2176}
2177
2178static int i915_swizzle_info(struct seq_file *m, void *data)
2179{
9f25d007 2180 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2181 struct drm_device *dev = node->minor->dev;
2182 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2183 int ret;
2184
2185 ret = mutex_lock_interruptible(&dev->struct_mutex);
2186 if (ret)
2187 return ret;
c8c8fb33 2188 intel_runtime_pm_get(dev_priv);
ea16a3cd 2189
ea16a3cd
DV		 2190 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2191 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2192 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2193 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2194
2195 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2196 seq_printf(m, "DDC = 0x%08x\n",
2197 I915_READ(DCC));
656bfa3a
DV		 2198 seq_printf(m, "DDC2 = 0x%08x\n",
2199 I915_READ(DCC2));
ea16a3cd
DV		 2200 seq_printf(m, "C0DRB3 = 0x%04x\n",
2201 I915_READ16(C0DRB3));
2202 seq_printf(m, "C1DRB3 = 0x%04x\n",
2203 I915_READ16(C1DRB3));
9d3203e1 2204 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2205 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2206 I915_READ(MAD_DIMM_C0));
2207 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2208 I915_READ(MAD_DIMM_C1));
2209 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2210 I915_READ(MAD_DIMM_C2));
2211 seq_printf(m, "TILECTL = 0x%08x\n",
2212 I915_READ(TILECTL));
5907f5fb 2213 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2214 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2215 I915_READ(GAMTARBMODE));
2216 else
2217 seq_printf(m, "ARB_MODE = 0x%08x\n",
2218 I915_READ(ARB_MODE));
3fa7d235
DV		 2219 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2220 I915_READ(DISP_ARB_CTL));
ea16a3cd 2221 }
656bfa3a
DV		 2222
2223 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2224 seq_puts(m, "L-shaped memory detected\n");
2225
c8c8fb33 2226 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2227 mutex_unlock(&dev->struct_mutex);
2228
2229 return 0;
2230}
2231
1c60fef5
BW		 2232static int per_file_ctx(int id, void *ptr, void *data)
2233{
273497e5 2234 struct intel_context *ctx = ptr;
1c60fef5 2235 struct seq_file *m = data;
ae6c4806
DV		 2236 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2237
2238 if (!ppgtt) {
2239 seq_printf(m, " no ppgtt for context %d\n",
2240 ctx->user_handle);
2241 return 0;
2242 }
1c60fef5 2243
f83d6518
OM		 2244 if (i915_gem_context_is_default(ctx))
2245 seq_puts(m, " default context:\n");
2246 else
821d66dd 2247 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2248 ppgtt->debug_dump(ppgtt, m);
2249
2250 return 0;
2251}
2252
77df6772 2253static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2254{
3cf17fc5 2255 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2256 struct intel_engine_cs *engine;
77df6772 2257 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
b4ac5afc 2258 int i;
3cf17fc5 2259
77df6772
BW		 2260 if (!ppgtt)
2261 return;
2262
b4ac5afc 2263 for_each_engine(engine, dev_priv) {
e2f80391 2264 seq_printf(m, "%s\n", engine->name);
77df6772 2265 for (i = 0; i < 4; i++) {
e2f80391 2266 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
77df6772 2267 pdp <<= 32;
e2f80391 2268 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
a2a5b15c 2269 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2270 }
2271 }
2272}
2273
2274static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2275{
2276 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2277 struct intel_engine_cs *engine;
3cf17fc5 2278
3cf17fc5
DV		 2279 if (INTEL_INFO(dev)->gen == 6)
2280 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2281
b4ac5afc 2282 for_each_engine(engine, dev_priv) {
e2f80391 2283 seq_printf(m, "%s\n", engine->name);
3cf17fc5 2284 if (INTEL_INFO(dev)->gen == 7)
e2f80391
TU		 2285 seq_printf(m, "GFX_MODE: 0x%08x\n",
2286 I915_READ(RING_MODE_GEN7(engine)));
2287 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2288 I915_READ(RING_PP_DIR_BASE(engine)));
2289 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2290 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2291 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2292 I915_READ(RING_PP_DIR_DCLV(engine)));
3cf17fc5
DV		 2293 }
2294 if (dev_priv->mm.aliasing_ppgtt) {
2295 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2296
267f0c90 2297 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2298 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2299
87d60b63 2300 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2301 }
1c60fef5 2302
3cf17fc5 2303 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2304}
2305
2306static int i915_ppgtt_info(struct seq_file *m, void *data)
2307{
9f25d007 2308 struct drm_info_node *node = m->private;
77df6772 2309 struct drm_device *dev = node->minor->dev;
c8c8fb33 2310 struct drm_i915_private *dev_priv = dev->dev_private;
ea91e401 2311 struct drm_file *file;
77df6772
BW		 2312
2313 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2314 if (ret)
2315 return ret;
c8c8fb33 2316 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2317
2318 if (INTEL_INFO(dev)->gen >= 8)
2319 gen8_ppgtt_info(m, dev);
2320 else if (INTEL_INFO(dev)->gen >= 6)
2321 gen6_ppgtt_info(m, dev);
2322
ea91e401
MT		 2323 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2324 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2325 struct task_struct *task;
ea91e401 2326
7cb5dff8 2327 task = get_pid_task(file->pid, PIDTYPE_PID);
06812760
DC		 2328 if (!task) {
2329 ret = -ESRCH;
2330 goto out_put;
2331 }
7cb5dff8
GT		 2332 seq_printf(m, "\nproc: %s\n", task->comm);
2333 put_task_struct(task);
ea91e401
MT		 2334 idr_for_each(&file_priv->context_idr, per_file_ctx,
2335 (void *)(unsigned long)m);
2336 }
2337
06812760 2338out_put:
c8c8fb33 2339 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2340 mutex_unlock(&dev->struct_mutex);
2341
06812760 2342 return ret;
3cf17fc5
DV		 2343}
2344
f5a4c67d
CW		 2345static int count_irq_waiters(struct drm_i915_private *i915)
2346{
e2f80391 2347 struct intel_engine_cs *engine;
f5a4c67d 2348 int count = 0;
f5a4c67d 2349
b4ac5afc 2350 for_each_engine(engine, i915)
e2f80391 2351 count += engine->irq_refcount;
f5a4c67d
CW		 2352
2353 return count;
2354}
2355
1854d5ca
CW		 2356static int i915_rps_boost_info(struct seq_file *m, void *data)
2357{
2358 struct drm_info_node *node = m->private;
2359 struct drm_device *dev = node->minor->dev;
2360 struct drm_i915_private *dev_priv = dev->dev_private;
2361 struct drm_file *file;
1854d5ca 2362
f5a4c67d
CW		 2363 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2364 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2365 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2366 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2367 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2368 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2369 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2370 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2371 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2372 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2373 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2374 struct drm_i915_file_private *file_priv = file->driver_priv;
2375 struct task_struct *task;
2376
2377 rcu_read_lock();
2378 task = pid_task(file->pid, PIDTYPE_PID);
2379 seq_printf(m, "%s [%d]: %d boosts%s\n",
2380 task ? task->comm : "<unknown>",
2381 task ? task->pid : -1,
2e1b8730
CW		 2382 file_priv->rps.boosts,
2383 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2384 rcu_read_unlock();
2385 }
2e1b8730
CW		 2386 seq_printf(m, "Semaphore boosts: %d%s\n",
2387 dev_priv->rps.semaphores.boosts,
2388 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2389 seq_printf(m, "MMIO flip boosts: %d%s\n",
2390 dev_priv->rps.mmioflips.boosts,
2391 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2392 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2393 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2394
8d3afd7d 2395 return 0;
1854d5ca
CW		 2396}
2397
63573eb7
BW		 2398static int i915_llc(struct seq_file *m, void *data)
2399{
9f25d007 2400 struct drm_info_node *node = m->private;
63573eb7
BW		 2401 struct drm_device *dev = node->minor->dev;
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2403
2404 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2405 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2406 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2407
2408 return 0;
2409}
2410
fdf5d357
AD		 2411static int i915_guc_load_status_info(struct seq_file *m, void *data)
2412{
2413 struct drm_info_node *node = m->private;
2414 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2415 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2416 u32 tmp, i;
2417
2d1fe073 2418 if (!HAS_GUC_UCODE(dev_priv))
fdf5d357
AD		 2419 return 0;
2420
2421 seq_printf(m, "GuC firmware status:\n");
2422 seq_printf(m, "\tpath: %s\n",
2423 guc_fw->guc_fw_path);
2424 seq_printf(m, "\tfetch: %s\n",
2425 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2426 seq_printf(m, "\tload: %s\n",
2427 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2428 seq_printf(m, "\tversion wanted: %d.%d\n",
2429 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2430 seq_printf(m, "\tversion found: %d.%d\n",
2431 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
feda33ef
AD		 2432 seq_printf(m, "\theader: offset is %d; size = %d\n",
2433 guc_fw->header_offset, guc_fw->header_size);
2434 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2435 guc_fw->ucode_offset, guc_fw->ucode_size);
2436 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2437 guc_fw->rsa_offset, guc_fw->rsa_size);
fdf5d357
AD		 2438
2439 tmp = I915_READ(GUC_STATUS);
2440
2441 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2442 seq_printf(m, "\tBootrom status = 0x%x\n",
2443 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2444 seq_printf(m, "\tuKernel status = 0x%x\n",
2445 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2446 seq_printf(m, "\tMIA Core status = 0x%x\n",
2447 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2448 seq_puts(m, "\nScratch registers:\n");
2449 for (i = 0; i < 16; i++)
2450 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2451
2452 return 0;
2453}
2454
8b417c26
DG		 2455static void i915_guc_client_info(struct seq_file *m,
2456 struct drm_i915_private *dev_priv,
2457 struct i915_guc_client *client)
2458{
e2f80391 2459 struct intel_engine_cs *engine;
8b417c26 2460 uint64_t tot = 0;
8b417c26
DG		 2461
2462 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2463 client->priority, client->ctx_index, client->proc_desc_offset);
2464 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2465 client->doorbell_id, client->doorbell_offset, client->cookie);
2466 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2467 client->wq_size, client->wq_offset, client->wq_tail);
2468
2469 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2470 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2471 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2472
b4ac5afc 2473 for_each_engine(engine, dev_priv) {
8b417c26 2474 seq_printf(m, "\tSubmissions: %llu %s\n",
e2f80391
TU		 2475 client->submissions[engine->guc_id],
2476 engine->name);
2477 tot += client->submissions[engine->guc_id];
8b417c26
DG		 2478 }
2479 seq_printf(m, "\tTotal: %llu\n", tot);
2480}
2481
2482static int i915_guc_info(struct seq_file *m, void *data)
2483{
2484 struct drm_info_node *node = m->private;
2485 struct drm_device *dev = node->minor->dev;
2486 struct drm_i915_private *dev_priv = dev->dev_private;
2487 struct intel_guc guc;
0a0b457f 2488 struct i915_guc_client client = {};
e2f80391 2489 struct intel_engine_cs *engine;
8b417c26
DG		 2490 u64 total = 0;
2491
2d1fe073 2492 if (!HAS_GUC_SCHED(dev_priv))
8b417c26
DG		 2493 return 0;
2494
5a843307
AD		 2495 if (mutex_lock_interruptible(&dev->struct_mutex))
2496 return 0;
2497
8b417c26 2498 /* Take a local copy of the GuC data, so we can dump it at leisure */
8b417c26 2499 guc = dev_priv->guc;
5a843307 2500 if (guc.execbuf_client)
8b417c26 2501 client = *guc.execbuf_client;
5a843307
AD		 2502
2503 mutex_unlock(&dev->struct_mutex);
8b417c26
DG		 2504
2505 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2506 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2507 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2508 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2509 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2510
2511 seq_printf(m, "\nGuC submissions:\n");
b4ac5afc 2512 for_each_engine(engine, dev_priv) {
397097b0 2513 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
e2f80391
TU		 2514 engine->name, guc.submissions[engine->guc_id],
2515 guc.last_seqno[engine->guc_id]);
2516 total += guc.submissions[engine->guc_id];
8b417c26
DG		 2517 }
2518 seq_printf(m, "\t%s: %llu\n", "Total", total);
2519
2520 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2521 i915_guc_client_info(m, dev_priv, &client);
2522
2523 /* Add more as required ... */
2524
2525 return 0;
2526}
2527
4c7e77fc
AD		 2528static int i915_guc_log_dump(struct seq_file *m, void *data)
2529{
2530 struct drm_info_node *node = m->private;
2531 struct drm_device *dev = node->minor->dev;
2532 struct drm_i915_private *dev_priv = dev->dev_private;
2533 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2534 u32 *log;
2535 int i = 0, pg;
2536
2537 if (!log_obj)
2538 return 0;
2539
2540 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2541 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2542
2543 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2544 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2545 *(log + i), *(log + i + 1),
2546 *(log + i + 2), *(log + i + 3));
2547
2548 kunmap_atomic(log);
2549 }
2550
2551 seq_putc(m, '\n');
2552
2553 return 0;
2554}
2555
e91fd8c6
RV		 2556static int i915_edp_psr_status(struct seq_file *m, void *data)
2557{
2558 struct drm_info_node *node = m->private;
2559 struct drm_device *dev = node->minor->dev;
2560 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2561 u32 psrperf = 0;
a6cbdb8e
RV		 2562 u32 stat[3];
2563 enum pipe pipe;
a031d709 2564 bool enabled = false;
e91fd8c6 2565
3553a8ea
DL		 2566 if (!HAS_PSR(dev)) {
2567 seq_puts(m, "PSR not supported\n");
2568 return 0;
2569 }
2570
c8c8fb33
PZ		 2571 intel_runtime_pm_get(dev_priv);
2572
fa128fa6 2573 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2574 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2575 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2576 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2577 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2578 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2579 dev_priv->psr.busy_frontbuffer_bits);
2580 seq_printf(m, "Re-enable work scheduled: %s\n",
2581 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2582
3553a8ea 2583 if (HAS_DDI(dev))
443a389f 2584 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
3553a8ea
DL		 2585 else {
2586 for_each_pipe(dev_priv, pipe) {
2587 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2588 VLV_EDP_PSR_CURR_STATE_MASK;
2589 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2590 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2591 enabled = true;
a6cbdb8e
RV		 2592 }
2593 }
60e5ffe3
RV		 2594
2595 seq_printf(m, "Main link in standby mode: %s\n",
2596 yesno(dev_priv->psr.link_standby));
2597
a6cbdb8e
RV		 2598 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2599
2600 if (!HAS_DDI(dev))
2601 for_each_pipe(dev_priv, pipe) {
2602 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2603 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2604 seq_printf(m, " pipe %c", pipe_name(pipe));
2605 }
2606 seq_puts(m, "\n");
e91fd8c6 2607
05eec3c2
RV		 2608 /*
2609 * VLV/CHV PSR has no kind of performance counter
2610 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2611 */
2612 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
443a389f 2613 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
a031d709 2614 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2615
2616 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2617 }
fa128fa6 2618 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2619
c8c8fb33 2620 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2621 return 0;
2622}
2623
d2e216d0
RV		 2624static int i915_sink_crc(struct seq_file *m, void *data)
2625{
2626 struct drm_info_node *node = m->private;
2627 struct drm_device *dev = node->minor->dev;
2628 struct intel_encoder *encoder;
2629 struct intel_connector *connector;
2630 struct intel_dp *intel_dp = NULL;
2631 int ret;
2632 u8 crc[6];
2633
2634 drm_modeset_lock_all(dev);
aca5e361 2635 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2636
2637 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2638 continue;
2639
b6ae3c7c
PZ		 2640 if (!connector->base.encoder)
2641 continue;
2642
d2e216d0
RV		 2643 encoder = to_intel_encoder(connector->base.encoder);
2644 if (encoder->type != INTEL_OUTPUT_EDP)
2645 continue;
2646
2647 intel_dp = enc_to_intel_dp(&encoder->base);
2648
2649 ret = intel_dp_sink_crc(intel_dp, crc);
2650 if (ret)
2651 goto out;
2652
2653 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2654 crc[0], crc[1], crc[2],
2655 crc[3], crc[4], crc[5]);
2656 goto out;
2657 }
2658 ret = -ENODEV;
2659out:
2660 drm_modeset_unlock_all(dev);
2661 return ret;
2662}
2663
ec013e7f
JB		 2664static int i915_energy_uJ(struct seq_file *m, void *data)
2665{
2666 struct drm_info_node *node = m->private;
2667 struct drm_device *dev = node->minor->dev;
2668 struct drm_i915_private *dev_priv = dev->dev_private;
2669 u64 power;
2670 u32 units;
2671
2672 if (INTEL_INFO(dev)->gen < 6)
2673 return -ENODEV;
2674
36623ef8
PZ		 2675 intel_runtime_pm_get(dev_priv);
2676
ec013e7f
JB		 2677 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2678 power = (power & 0x1f00) >> 8;
2679 units = 1000000 / (1 << power); /* convert to uJ */
2680 power = I915_READ(MCH_SECP_NRG_STTS);
2681 power *= units;
2682
36623ef8
PZ		 2683 intel_runtime_pm_put(dev_priv);
2684
ec013e7f 2685 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2686
2687 return 0;
2688}
2689
6455c870 2690static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2691{
9f25d007 2692 struct drm_info_node *node = m->private;
371db66a
PZ		 2693 struct drm_device *dev = node->minor->dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695
a156e64d
CW		 2696 if (!HAS_RUNTIME_PM(dev_priv))
2697 seq_puts(m, "Runtime power management not supported\n");
371db66a 2698
86c4ec0d 2699 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2700 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2701 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2702#ifdef CONFIG_PM
a6aaec8b
DL		 2703 seq_printf(m, "Usage count: %d\n",
2704 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2705#else
2706 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2707#endif
a156e64d
CW		 2708 seq_printf(m, "PCI device power state: %s [%d]\n",
2709 pci_power_name(dev_priv->dev->pdev->current_state),
2710 dev_priv->dev->pdev->current_state);
371db66a 2711
ec013e7f
JB		 2712 return 0;
2713}
2714
1da51581
ID		 2715static int i915_power_domain_info(struct seq_file *m, void *unused)
2716{
9f25d007 2717 struct drm_info_node *node = m->private;
1da51581
ID		 2718 struct drm_device *dev = node->minor->dev;
2719 struct drm_i915_private *dev_priv = dev->dev_private;
2720 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2721 int i;
2722
2723 mutex_lock(&power_domains->lock);
2724
2725 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2726 for (i = 0; i < power_domains->power_well_count; i++) {
2727 struct i915_power_well *power_well;
2728 enum intel_display_power_domain power_domain;
2729
2730 power_well = &power_domains->power_wells[i];
2731 seq_printf(m, "%-25s %d\n", power_well->name,
2732 power_well->count);
2733
2734 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2735 power_domain++) {
2736 if (!(BIT(power_domain) & power_well->domains))
2737 continue;
2738
2739 seq_printf(m, " %-23s %d\n",
9895ad03 2740 intel_display_power_domain_str(power_domain),
1da51581
ID		 2741 power_domains->domain_use_count[power_domain]);
2742 }
2743 }
2744
2745 mutex_unlock(&power_domains->lock);
2746
2747 return 0;
2748}
2749
b7cec66d
DL		 2750static int i915_dmc_info(struct seq_file *m, void *unused)
2751{
2752 struct drm_info_node *node = m->private;
2753 struct drm_device *dev = node->minor->dev;
2754 struct drm_i915_private *dev_priv = dev->dev_private;
2755 struct intel_csr *csr;
2756
2757 if (!HAS_CSR(dev)) {
2758 seq_puts(m, "not supported\n");
2759 return 0;
2760 }
2761
2762 csr = &dev_priv->csr;
2763
6fb403de
MK		 2764 intel_runtime_pm_get(dev_priv);
2765
b7cec66d
DL		 2766 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2767 seq_printf(m, "path: %s\n", csr->fw_path);
2768
2769 if (!csr->dmc_payload)
6fb403de 2770 goto out;
b7cec66d
DL		 2771
2772 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2773 CSR_VERSION_MINOR(csr->version));
2774
8337206d
DL		 2775 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2776 seq_printf(m, "DC3 -> DC5 count: %d\n",
2777 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2778 seq_printf(m, "DC5 -> DC6 count: %d\n",
2779 I915_READ(SKL_CSR_DC5_DC6_COUNT));
16e11b99
MK		 2780 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2781 seq_printf(m, "DC3 -> DC5 count: %d\n",
2782 I915_READ(BXT_CSR_DC3_DC5_COUNT));
8337206d
DL		 2783 }
2784
6fb403de
MK		 2785out:
2786 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2787 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2788 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2789
8337206d
DL		 2790 intel_runtime_pm_put(dev_priv);
2791
b7cec66d
DL		 2792 return 0;
2793}
2794
53f5e3ca
JB		 2795static void intel_seq_print_mode(struct seq_file *m, int tabs,
2796 struct drm_display_mode *mode)
2797{
2798 int i;
2799
2800 for (i = 0; i < tabs; i++)
2801 seq_putc(m, '\t');
2802
2803 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2804 mode->base.id, mode->name,
2805 mode->vrefresh, mode->clock,
2806 mode->hdisplay, mode->hsync_start,
2807 mode->hsync_end, mode->htotal,
2808 mode->vdisplay, mode->vsync_start,
2809 mode->vsync_end, mode->vtotal,
2810 mode->type, mode->flags);
2811}
2812
2813static void intel_encoder_info(struct seq_file *m,
2814 struct intel_crtc *intel_crtc,
2815 struct intel_encoder *intel_encoder)
2816{
9f25d007 2817 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2818 struct drm_device *dev = node->minor->dev;
2819 struct drm_crtc *crtc = &intel_crtc->base;
2820 struct intel_connector *intel_connector;
2821 struct drm_encoder *encoder;
2822
2823 encoder = &intel_encoder->base;
2824 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2825 encoder->base.id, encoder->name);
53f5e3ca
JB		 2826 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2827 struct drm_connector *connector = &intel_connector->base;
2828 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2829 connector->base.id,
c23cc417 2830 connector->name,
53f5e3ca
JB		 2831 drm_get_connector_status_name(connector->status));
2832 if (connector->status == connector_status_connected) {
2833 struct drm_display_mode *mode = &crtc->mode;
2834 seq_printf(m, ", mode:\n");
2835 intel_seq_print_mode(m, 2, mode);
2836 } else {
2837 seq_putc(m, '\n');
2838 }
2839 }
2840}
2841
2842static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2843{
9f25d007 2844 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2845 struct drm_device *dev = node->minor->dev;
2846 struct drm_crtc *crtc = &intel_crtc->base;
2847 struct intel_encoder *intel_encoder;
23a48d53
ML		 2848 struct drm_plane_state *plane_state = crtc->primary->state;
2849 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2850
23a48d53 2851 if (fb)
5aa8a937 2852 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2853 fb->base.id, plane_state->src_x >> 16,
2854 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2855 else
2856 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2857 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2858 intel_encoder_info(m, intel_crtc, intel_encoder);
2859}
2860
2861static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2862{
2863 struct drm_display_mode *mode = panel->fixed_mode;
2864
2865 seq_printf(m, "\tfixed mode:\n");
2866 intel_seq_print_mode(m, 2, mode);
2867}
2868
2869static void intel_dp_info(struct seq_file *m,
2870 struct intel_connector *intel_connector)
2871{
2872 struct intel_encoder *intel_encoder = intel_connector->encoder;
2873 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2874
2875 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2876 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
53f5e3ca
JB		 2877 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2878 intel_panel_info(m, &intel_connector->panel);
2879}
2880
3d52ccf5
LY		 2881static void intel_dp_mst_info(struct seq_file *m,
2882 struct intel_connector *intel_connector)
2883{
2884 struct intel_encoder *intel_encoder = intel_connector->encoder;
2885 struct intel_dp_mst_encoder *intel_mst =
2886 enc_to_mst(&intel_encoder->base);
2887 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2888 struct intel_dp *intel_dp = &intel_dig_port->dp;
2889 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2890 intel_connector->port);
2891
2892 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2893}
2894
53f5e3ca
JB		 2895static void intel_hdmi_info(struct seq_file *m,
2896 struct intel_connector *intel_connector)
2897{
2898 struct intel_encoder *intel_encoder = intel_connector->encoder;
2899 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2900
742f491d 2901 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2902}
2903
2904static void intel_lvds_info(struct seq_file *m,
2905 struct intel_connector *intel_connector)
2906{
2907 intel_panel_info(m, &intel_connector->panel);
2908}
2909
2910static void intel_connector_info(struct seq_file *m,
2911 struct drm_connector *connector)
2912{
2913 struct intel_connector *intel_connector = to_intel_connector(connector);
2914 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2915 struct drm_display_mode *mode;
53f5e3ca
JB		 2916
2917 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2918 connector->base.id, connector->name,
53f5e3ca
JB		 2919 drm_get_connector_status_name(connector->status));
2920 if (connector->status == connector_status_connected) {
2921 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2922 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2923 connector->display_info.width_mm,
2924 connector->display_info.height_mm);
2925 seq_printf(m, "\tsubpixel order: %s\n",
2926 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2927 seq_printf(m, "\tCEA rev: %d\n",
2928 connector->display_info.cea_rev);
2929 }
36cd7444
DA		 2930 if (intel_encoder) {
2931 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2932 intel_encoder->type == INTEL_OUTPUT_EDP)
2933 intel_dp_info(m, intel_connector);
2934 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2935 intel_hdmi_info(m, intel_connector);
2936 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2937 intel_lvds_info(m, intel_connector);
3d52ccf5
LY		 2938 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2939 intel_dp_mst_info(m, intel_connector);
36cd7444 2940 }
53f5e3ca 2941
f103fc7d
JB		 2942 seq_printf(m, "\tmodes:\n");
2943 list_for_each_entry(mode, &connector->modes, head)
2944 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2945}
2946
065f2ec2
CW		 2947static bool cursor_active(struct drm_device *dev, int pipe)
2948{
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 u32 state;
2951
2952 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 2953 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
065f2ec2 2954 else
5efb3e28 2955 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2956
2957 return state;
2958}
2959
2960static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2961{
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 u32 pos;
2964
5efb3e28 2965 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2966
2967 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2968 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2969 *x = -*x;
2970
2971 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2972 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2973 *y = -*y;
2974
2975 return cursor_active(dev, pipe);
2976}
2977
3abc4e09
RF		 2978static const char *plane_type(enum drm_plane_type type)
2979{
2980 switch (type) {
2981 case DRM_PLANE_TYPE_OVERLAY:
2982 return "OVL";
2983 case DRM_PLANE_TYPE_PRIMARY:
2984 return "PRI";
2985 case DRM_PLANE_TYPE_CURSOR:
2986 return "CUR";
2987 /*
2988 * Deliberately omitting default: to generate compiler warnings
2989 * when a new drm_plane_type gets added.
2990 */
2991 }
2992
2993 return "unknown";
2994}
2995
2996static const char *plane_rotation(unsigned int rotation)
2997{
2998 static char buf[48];
2999 /*
3000 * According to doc only one DRM_ROTATE_ is allowed but this
3001 * will print them all to visualize if the values are misused
3002 */
3003 snprintf(buf, sizeof(buf),
3004 "%s%s%s%s%s%s(0x%08x)",
3005 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3006 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3007 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3008 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3009 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3010 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3011 rotation);
3012
3013 return buf;
3014}
3015
3016static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3017{
3018 struct drm_info_node *node = m->private;
3019 struct drm_device *dev = node->minor->dev;
3020 struct intel_plane *intel_plane;
3021
3022 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3023 struct drm_plane_state *state;
3024 struct drm_plane *plane = &intel_plane->base;
3025
3026 if (!plane->state) {
3027 seq_puts(m, "plane->state is NULL!\n");
3028 continue;
3029 }
3030
3031 state = plane->state;
3032
3033 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3034 plane->base.id,
3035 plane_type(intel_plane->base.type),
3036 state->crtc_x, state->crtc_y,
3037 state->crtc_w, state->crtc_h,
3038 (state->src_x >> 16),
3039 ((state->src_x & 0xffff) * 15625) >> 10,
3040 (state->src_y >> 16),
3041 ((state->src_y & 0xffff) * 15625) >> 10,
3042 (state->src_w >> 16),
3043 ((state->src_w & 0xffff) * 15625) >> 10,
3044 (state->src_h >> 16),
3045 ((state->src_h & 0xffff) * 15625) >> 10,
3046 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3047 plane_rotation(state->rotation));
3048 }
3049}
3050
3051static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3052{
3053 struct intel_crtc_state *pipe_config;
3054 int num_scalers = intel_crtc->num_scalers;
3055 int i;
3056
3057 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3058
3059 /* Not all platformas have a scaler */
3060 if (num_scalers) {
3061 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3062 num_scalers,
3063 pipe_config->scaler_state.scaler_users,
3064 pipe_config->scaler_state.scaler_id);
3065
3066 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3067 struct intel_scaler *sc =
3068 &pipe_config->scaler_state.scalers[i];
3069
3070 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3071 i, yesno(sc->in_use), sc->mode);
3072 }
3073 seq_puts(m, "\n");
3074 } else {
3075 seq_puts(m, "\tNo scalers available on this platform\n");
3076 }
3077}
3078
53f5e3ca
JB		 3079static int i915_display_info(struct seq_file *m, void *unused)
3080{
9f25d007 3081 struct drm_info_node *node = m->private;
53f5e3ca 3082 struct drm_device *dev = node->minor->dev;
b0e5ddf3 3083 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 3084 struct intel_crtc *crtc;
53f5e3ca
JB		 3085 struct drm_connector *connector;
3086
b0e5ddf3 3087 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 3088 drm_modeset_lock_all(dev);
3089 seq_printf(m, "CRTC info\n");
3090 seq_printf(m, "---------\n");
d3fcc808 3091 for_each_intel_crtc(dev, crtc) {
065f2ec2 3092 bool active;
f77076c9 3093 struct intel_crtc_state *pipe_config;
065f2ec2 3094 int x, y;
53f5e3ca 3095
f77076c9
ML		 3096 pipe_config = to_intel_crtc_state(crtc->base.state);
3097
3abc4e09 3098 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
065f2ec2 3099 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9 3100 yesno(pipe_config->base.active),
3abc4e09
RF		 3101 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3102 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3103
f77076c9 3104 if (pipe_config->base.active) {
065f2ec2
CW		 3105 intel_crtc_info(m, crtc);
3106
a23dc658 3107 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 3108 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 3109 yesno(crtc->cursor_base),
3dd512fb
MR		 3110 x, y, crtc->base.cursor->state->crtc_w,
3111 crtc->base.cursor->state->crtc_h,
57127efa 3112 crtc->cursor_addr, yesno(active));
3abc4e09
RF		 3113 intel_scaler_info(m, crtc);
3114 intel_plane_info(m, crtc);
a23dc658 3115 }
cace841c
DV		 3116
3117 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3118 yesno(!crtc->cpu_fifo_underrun_disabled),
3119 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 3120 }
3121
3122 seq_printf(m, "\n");
3123 seq_printf(m, "Connector info\n");
3124 seq_printf(m, "--------------\n");
3125 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3126 intel_connector_info(m, connector);
3127 }
3128 drm_modeset_unlock_all(dev);
b0e5ddf3 3129 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 3130
3131 return 0;
3132}
3133
e04934cf
BW		 3134static int i915_semaphore_status(struct seq_file *m, void *unused)
3135{
3136 struct drm_info_node *node = (struct drm_info_node *) m->private;
3137 struct drm_device *dev = node->minor->dev;
3138 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 3139 struct intel_engine_cs *engine;
e04934cf 3140 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
c3232b18
DG		 3141 enum intel_engine_id id;
3142 int j, ret;
e04934cf
BW		 3143
3144 if (!i915_semaphore_is_enabled(dev)) {
3145 seq_puts(m, "Semaphores are disabled\n");
3146 return 0;
3147 }
3148
3149 ret = mutex_lock_interruptible(&dev->struct_mutex);
3150 if (ret)
3151 return ret;
03872064 3152 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 3153
3154 if (IS_BROADWELL(dev)) {
3155 struct page *page;
3156 uint64_t *seqno;
3157
3158 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3159
3160 seqno = (uint64_t *)kmap_atomic(page);
c3232b18 3161 for_each_engine_id(engine, dev_priv, id) {
e04934cf
BW		 3162 uint64_t offset;
3163
e2f80391 3164 seq_printf(m, "%s\n", engine->name);
e04934cf
BW		 3165
3166 seq_puts(m, " Last signal:");
3167 for (j = 0; j < num_rings; j++) {
c3232b18 3168 offset = id * I915_NUM_ENGINES + j;
e04934cf
BW		 3169 seq_printf(m, "0x%08llx (0x%02llx) ",
3170 seqno[offset], offset * 8);
3171 }
3172 seq_putc(m, '\n');
3173
3174 seq_puts(m, " Last wait: ");
3175 for (j = 0; j < num_rings; j++) {
c3232b18 3176 offset = id + (j * I915_NUM_ENGINES);
e04934cf
BW		 3177 seq_printf(m, "0x%08llx (0x%02llx) ",
3178 seqno[offset], offset * 8);
3179 }
3180 seq_putc(m, '\n');
3181
3182 }
3183 kunmap_atomic(seqno);
3184 } else {
3185 seq_puts(m, " Last signal:");
b4ac5afc 3186 for_each_engine(engine, dev_priv)
e04934cf
BW		 3187 for (j = 0; j < num_rings; j++)
3188 seq_printf(m, "0x%08x\n",
e2f80391 3189 I915_READ(engine->semaphore.mbox.signal[j]));
e04934cf
BW		 3190 seq_putc(m, '\n');
3191 }
3192
3193 seq_puts(m, "\nSync seqno:\n");
b4ac5afc
DG		 3194 for_each_engine(engine, dev_priv) {
3195 for (j = 0; j < num_rings; j++)
e2f80391
TU		 3196 seq_printf(m, " 0x%08x ",
3197 engine->semaphore.sync_seqno[j]);
e04934cf
BW		 3198 seq_putc(m, '\n');
3199 }
3200 seq_putc(m, '\n');
3201
03872064 3202 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3203 mutex_unlock(&dev->struct_mutex);
3204 return 0;
3205}
3206
728e29d7
DV		 3207static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3208{
3209 struct drm_info_node *node = (struct drm_info_node *) m->private;
3210 struct drm_device *dev = node->minor->dev;
3211 struct drm_i915_private *dev_priv = dev->dev_private;
3212 int i;
3213
3214 drm_modeset_lock_all(dev);
3215 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3216 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3217
3218 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2dd66ebd
ML		 3219 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3220 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
728e29d7 3221 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3222 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3223 seq_printf(m, " dpll_md: 0x%08x\n",
3224 pll->config.hw_state.dpll_md);
3225 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3226 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3227 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3228 }
3229 drm_modeset_unlock_all(dev);
3230
3231 return 0;
3232}
3233
1ed1ef9d 3234static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3235{
3236 int i;
3237 int ret;
e2f80391 3238 struct intel_engine_cs *engine;
888b5995
AS		 3239 struct drm_info_node *node = (struct drm_info_node *) m->private;
3240 struct drm_device *dev = node->minor->dev;
3241 struct drm_i915_private *dev_priv = dev->dev_private;
33136b06 3242 struct i915_workarounds *workarounds = &dev_priv->workarounds;
c3232b18 3243 enum intel_engine_id id;
888b5995 3244
888b5995
AS		 3245 ret = mutex_lock_interruptible(&dev->struct_mutex);
3246 if (ret)
3247 return ret;
3248
3249 intel_runtime_pm_get(dev_priv);
3250
33136b06 3251 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
c3232b18 3252 for_each_engine_id(engine, dev_priv, id)
33136b06 3253 seq_printf(m, "HW whitelist count for %s: %d\n",
c3232b18 3254 engine->name, workarounds->hw_whitelist_count[id]);
33136b06 3255 for (i = 0; i < workarounds->count; ++i) {
f0f59a00
VS		 3256 i915_reg_t addr;
3257 u32 mask, value, read;
2fa60f6d 3258 bool ok;
888b5995 3259
33136b06
AS		 3260 addr = workarounds->reg[i].addr;
3261 mask = workarounds->reg[i].mask;
3262 value = workarounds->reg[i].value;
2fa60f6d
MK		 3263 read = I915_READ(addr);
3264 ok = (value & mask) == (read & mask);
3265 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
f0f59a00 3266 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3267 }
3268
3269 intel_runtime_pm_put(dev_priv);
3270 mutex_unlock(&dev->struct_mutex);
3271
3272 return 0;
3273}
3274
c5511e44
DL		 3275static int i915_ddb_info(struct seq_file *m, void *unused)
3276{
3277 struct drm_info_node *node = m->private;
3278 struct drm_device *dev = node->minor->dev;
3279 struct drm_i915_private *dev_priv = dev->dev_private;
3280 struct skl_ddb_allocation *ddb;
3281 struct skl_ddb_entry *entry;
3282 enum pipe pipe;
3283 int plane;
3284
2fcffe19
DL		 3285 if (INTEL_INFO(dev)->gen < 9)
3286 return 0;
3287
c5511e44
DL		 3288 drm_modeset_lock_all(dev);
3289
3290 ddb = &dev_priv->wm.skl_hw.ddb;
3291
3292 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3293
3294 for_each_pipe(dev_priv, pipe) {
3295 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3296
dd740780 3297 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3298 entry = &ddb->plane[pipe][plane];
3299 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3300 entry->start, entry->end,
3301 skl_ddb_entry_size(entry));
3302 }
3303
4969d33e 3304 entry = &ddb->plane[pipe][PLANE_CURSOR];
c5511e44
DL		 3305 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3306 entry->end, skl_ddb_entry_size(entry));
3307 }
3308
3309 drm_modeset_unlock_all(dev);
3310
3311 return 0;
3312}
3313
a54746e3
VK		 3314static void drrs_status_per_crtc(struct seq_file *m,
3315 struct drm_device *dev, struct intel_crtc *intel_crtc)
3316{
3317 struct intel_encoder *intel_encoder;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319 struct i915_drrs *drrs = &dev_priv->drrs;
3320 int vrefresh = 0;
3321
3322 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3323 /* Encoder connected on this CRTC */
3324 switch (intel_encoder->type) {
3325 case INTEL_OUTPUT_EDP:
3326 seq_puts(m, "eDP:\n");
3327 break;
3328 case INTEL_OUTPUT_DSI:
3329 seq_puts(m, "DSI:\n");
3330 break;
3331 case INTEL_OUTPUT_HDMI:
3332 seq_puts(m, "HDMI:\n");
3333 break;
3334 case INTEL_OUTPUT_DISPLAYPORT:
3335 seq_puts(m, "DP:\n");
3336 break;
3337 default:
3338 seq_printf(m, "Other encoder (id=%d).\n",
3339 intel_encoder->type);
3340 return;
3341 }
3342 }
3343
3344 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3345 seq_puts(m, "\tVBT: DRRS_type: Static");
3346 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3347 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3348 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3349 seq_puts(m, "\tVBT: DRRS_type: None");
3350 else
3351 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3352
3353 seq_puts(m, "\n\n");
3354
f77076c9 3355 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3356 struct intel_panel *panel;
3357
3358 mutex_lock(&drrs->mutex);
3359 /* DRRS Supported */
3360 seq_puts(m, "\tDRRS Supported: Yes\n");
3361
3362 /* disable_drrs() will make drrs->dp NULL */
3363 if (!drrs->dp) {
3364 seq_puts(m, "Idleness DRRS: Disabled");
3365 mutex_unlock(&drrs->mutex);
3366 return;
3367 }
3368
3369 panel = &drrs->dp->attached_connector->panel;
3370 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3371 drrs->busy_frontbuffer_bits);
3372
3373 seq_puts(m, "\n\t\t");
3374 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3375 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3376 vrefresh = panel->fixed_mode->vrefresh;
3377 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3378 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3379 vrefresh = panel->downclock_mode->vrefresh;
3380 } else {
3381 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3382 drrs->refresh_rate_type);
3383 mutex_unlock(&drrs->mutex);
3384 return;
3385 }
3386 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3387
3388 seq_puts(m, "\n\t\t");
3389 mutex_unlock(&drrs->mutex);
3390 } else {
3391 /* DRRS not supported. Print the VBT parameter*/
3392 seq_puts(m, "\tDRRS Supported : No");
3393 }
3394 seq_puts(m, "\n");
3395}
3396
3397static int i915_drrs_status(struct seq_file *m, void *unused)
3398{
3399 struct drm_info_node *node = m->private;
3400 struct drm_device *dev = node->minor->dev;
3401 struct intel_crtc *intel_crtc;
3402 int active_crtc_cnt = 0;
3403
3404 for_each_intel_crtc(dev, intel_crtc) {
3405 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3406
f77076c9 3407 if (intel_crtc->base.state->active) {
a54746e3
VK		 3408 active_crtc_cnt++;
3409 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3410
3411 drrs_status_per_crtc(m, dev, intel_crtc);
3412 }
3413
3414 drm_modeset_unlock(&intel_crtc->base.mutex);
3415 }
3416
3417 if (!active_crtc_cnt)
3418 seq_puts(m, "No active crtc found\n");
3419
3420 return 0;
3421}
3422
07144428
DL		 3423struct pipe_crc_info {
3424 const char *name;
3425 struct drm_device *dev;
3426 enum pipe pipe;
3427};
3428
11bed958
DA		 3429static int i915_dp_mst_info(struct seq_file *m, void *unused)
3430{
3431 struct drm_info_node *node = (struct drm_info_node *) m->private;
3432 struct drm_device *dev = node->minor->dev;
3433 struct drm_encoder *encoder;
3434 struct intel_encoder *intel_encoder;
3435 struct intel_digital_port *intel_dig_port;
3436 drm_modeset_lock_all(dev);
3437 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3438 intel_encoder = to_intel_encoder(encoder);
3439 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3440 continue;
3441 intel_dig_port = enc_to_dig_port(encoder);
3442 if (!intel_dig_port->dp.can_mst)
3443 continue;
3444
3445 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3446 }
3447 drm_modeset_unlock_all(dev);
3448 return 0;
3449}
3450
07144428
DL		 3451static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3452{
be5c7a90
DL		 3453 struct pipe_crc_info *info = inode->i_private;
3454 struct drm_i915_private *dev_priv = info->dev->dev_private;
3455 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3456
7eb1c496
DV		 3457 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3458 return -ENODEV;
3459
d538bbdf
DL		 3460 spin_lock_irq(&pipe_crc->lock);
3461
3462 if (pipe_crc->opened) {
3463 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3464 return -EBUSY; /* already open */
3465 }
3466
d538bbdf 3467 pipe_crc->opened = true;
07144428
DL		 3468 filep->private_data = inode->i_private;
3469
d538bbdf
DL		 3470 spin_unlock_irq(&pipe_crc->lock);
3471
07144428
DL		 3472 return 0;
3473}
3474
3475static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3476{
be5c7a90
DL		 3477 struct pipe_crc_info *info = inode->i_private;
3478 struct drm_i915_private *dev_priv = info->dev->dev_private;
3479 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3480
d538bbdf
DL		 3481 spin_lock_irq(&pipe_crc->lock);
3482 pipe_crc->opened = false;
3483 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3484
07144428
DL		 3485 return 0;
3486}
3487
3488/* (6 fields, 8 chars each, space separated (5) + '\n') */
3489#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3490/* account for \'0' */
3491#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3492
3493static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3494{
d538bbdf
DL		 3495 assert_spin_locked(&pipe_crc->lock);
3496 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3497 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3498}
3499
3500static ssize_t
3501i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3502 loff_t *pos)
3503{
3504 struct pipe_crc_info *info = filep->private_data;
3505 struct drm_device *dev = info->dev;
3506 struct drm_i915_private *dev_priv = dev->dev_private;
3507 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3508 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3509 int n_entries;
07144428
DL		 3510 ssize_t bytes_read;
3511
3512 /*
3513 * Don't allow user space to provide buffers not big enough to hold
3514 * a line of data.
3515 */
3516 if (count < PIPE_CRC_LINE_LEN)
3517 return -EINVAL;
3518
3519 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3520 return 0;
07144428
DL		 3521
3522 /* nothing to read */
d538bbdf 3523 spin_lock_irq(&pipe_crc->lock);
07144428 3524 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3525 int ret;
3526
3527 if (filep->f_flags & O_NONBLOCK) {
3528 spin_unlock_irq(&pipe_crc->lock);
07144428 3529 return -EAGAIN;
d538bbdf 3530 }
07144428 3531
d538bbdf
DL		 3532 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3533 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3534 if (ret) {
3535 spin_unlock_irq(&pipe_crc->lock);
3536 return ret;
3537 }
8bf1e9f1
SH		 3538 }
3539
07144428 3540 /* We now have one or more entries to read */
9ad6d99f 3541 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3542
07144428 3543 bytes_read = 0;
9ad6d99f
VS		 3544 while (n_entries > 0) {
3545 struct intel_pipe_crc_entry *entry =
3546 &pipe_crc->entries[pipe_crc->tail];
07144428 3547 int ret;
8bf1e9f1 3548
9ad6d99f
VS		 3549 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3550 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3551 break;
3552
3553 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3554 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3555
07144428
DL		 3556 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3557 "%8u %8x %8x %8x %8x %8x\n",
3558 entry->frame, entry->crc[0],
3559 entry->crc[1], entry->crc[2],
3560 entry->crc[3], entry->crc[4]);
3561
9ad6d99f
VS		 3562 spin_unlock_irq(&pipe_crc->lock);
3563
3564 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3565 if (ret == PIPE_CRC_LINE_LEN)
3566 return -EFAULT;
b2c88f5b 3567
9ad6d99f
VS		 3568 user_buf += PIPE_CRC_LINE_LEN;
3569 n_entries--;
3570
3571 spin_lock_irq(&pipe_crc->lock);
3572 }
8bf1e9f1 3573
d538bbdf
DL		 3574 spin_unlock_irq(&pipe_crc->lock);
3575
07144428
DL		 3576 return bytes_read;
3577}
3578
3579static const struct file_operations i915_pipe_crc_fops = {
3580 .owner = THIS_MODULE,
3581 .open = i915_pipe_crc_open,
3582 .read = i915_pipe_crc_read,
3583 .release = i915_pipe_crc_release,
3584};
3585
3586static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3587 {
3588 .name = "i915_pipe_A_crc",
3589 .pipe = PIPE_A,
3590 },
3591 {
3592 .name = "i915_pipe_B_crc",
3593 .pipe = PIPE_B,
3594 },
3595 {
3596 .name = "i915_pipe_C_crc",
3597 .pipe = PIPE_C,
3598 },
3599};
3600
3601static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3602 enum pipe pipe)
3603{
3604 struct drm_device *dev = minor->dev;
3605 struct dentry *ent;
3606 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3607
3608 info->dev = dev;
3609 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3610 &i915_pipe_crc_fops);
f3c5fe97
WY		 3611 if (!ent)
3612 return -ENOMEM;
07144428
DL		 3613
3614 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3615}
3616
e8dfcf78 3617static const char * const pipe_crc_sources[] = {
926321d5
DV		 3618 "none",
3619 "plane1",
3620 "plane2",
3621 "pf",
5b3a856b 3622 "pipe",
3d099a05
DV		 3623 "TV",
3624 "DP-B",
3625 "DP-C",
3626 "DP-D",
46a19188 3627 "auto",
926321d5
DV		 3628};
3629
3630static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3631{
3632 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3633 return pipe_crc_sources[source];
3634}
3635
bd9db02f 3636static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3637{
3638 struct drm_device *dev = m->private;
3639 struct drm_i915_private *dev_priv = dev->dev_private;
3640 int i;
3641
3642 for (i = 0; i < I915_MAX_PIPES; i++)
3643 seq_printf(m, "%c %s\n", pipe_name(i),
3644 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3645
3646 return 0;
3647}
3648
bd9db02f 3649static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3650{
3651 struct drm_device *dev = inode->i_private;
3652
bd9db02f 3653 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3654}
3655
46a19188 3656static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3657 uint32_t *val)
3658{
46a19188
DV		 3659 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3660 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3661
3662 switch (*source) {
52f843f6
DV		 3663 case INTEL_PIPE_CRC_SOURCE_PIPE:
3664 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3665 break;
3666 case INTEL_PIPE_CRC_SOURCE_NONE:
3667 *val = 0;
3668 break;
3669 default:
3670 return -EINVAL;
3671 }
3672
3673 return 0;
3674}
3675
46a19188
DV		 3676static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3677 enum intel_pipe_crc_source *source)
3678{
3679 struct intel_encoder *encoder;
3680 struct intel_crtc *crtc;
26756809 3681 struct intel_digital_port *dig_port;
46a19188
DV		 3682 int ret = 0;
3683
3684 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3685
6e9f798d 3686 drm_modeset_lock_all(dev);
b2784e15 3687 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3688 if (!encoder->base.crtc)
3689 continue;
3690
3691 crtc = to_intel_crtc(encoder->base.crtc);
3692
3693 if (crtc->pipe != pipe)
3694 continue;
3695
3696 switch (encoder->type) {
3697 case INTEL_OUTPUT_TVOUT:
3698 *source = INTEL_PIPE_CRC_SOURCE_TV;
3699 break;
3700 case INTEL_OUTPUT_DISPLAYPORT:
3701 case INTEL_OUTPUT_EDP:
26756809
DV		 3702 dig_port = enc_to_dig_port(&encoder->base);
3703 switch (dig_port->port) {
3704 case PORT_B:
3705 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3706 break;
3707 case PORT_C:
3708 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3709 break;
3710 case PORT_D:
3711 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3712 break;
3713 default:
3714 WARN(1, "nonexisting DP port %c\n",
3715 port_name(dig_port->port));
3716 break;
3717 }
46a19188 3718 break;
6847d71b
PZ		 3719 default:
3720 break;
46a19188
DV		 3721 }
3722 }
6e9f798d 3723 drm_modeset_unlock_all(dev);
46a19188
DV		 3724
3725 return ret;
3726}
3727
3728static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3729 enum pipe pipe,
3730 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3731 uint32_t *val)
3732{
8d2f24ca
DV		 3733 struct drm_i915_private *dev_priv = dev->dev_private;
3734 bool need_stable_symbols = false;
3735
46a19188
DV		 3736 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3737 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3738 if (ret)
3739 return ret;
3740 }
3741
3742 switch (*source) {
7ac0129b
DV		 3743 case INTEL_PIPE_CRC_SOURCE_PIPE:
3744 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3745 break;
3746 case INTEL_PIPE_CRC_SOURCE_DP_B:
3747 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3748 need_stable_symbols = true;
7ac0129b
DV		 3749 break;
3750 case INTEL_PIPE_CRC_SOURCE_DP_C:
3751 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3752 need_stable_symbols = true;
7ac0129b 3753 break;
2be57922
VS		 3754 case INTEL_PIPE_CRC_SOURCE_DP_D:
3755 if (!IS_CHERRYVIEW(dev))
3756 return -EINVAL;
3757 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3758 need_stable_symbols = true;
3759 break;
7ac0129b
DV		 3760 case INTEL_PIPE_CRC_SOURCE_NONE:
3761 *val = 0;
3762 break;
3763 default:
3764 return -EINVAL;
3765 }
3766
8d2f24ca
DV		 3767 /*
3768 * When the pipe CRC tap point is after the transcoders we need
3769 * to tweak symbol-level features to produce a deterministic series of
3770 * symbols for a given frame. We need to reset those features only once
3771 * a frame (instead of every nth symbol):
3772 * - DC-balance: used to ensure a better clock recovery from the data
3773 * link (SDVO)
3774 * - DisplayPort scrambling: used for EMI reduction
3775 */
3776 if (need_stable_symbols) {
3777 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3778
8d2f24ca 3779 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3780 switch (pipe) {
3781 case PIPE_A:
8d2f24ca 3782 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3783 break;
3784 case PIPE_B:
8d2f24ca 3785 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3786 break;
3787 case PIPE_C:
3788 tmp |= PIPE_C_SCRAMBLE_RESET;
3789 break;
3790 default:
3791 return -EINVAL;
3792 }
8d2f24ca
DV		 3793 I915_WRITE(PORT_DFT2_G4X, tmp);
3794 }
3795
7ac0129b
DV		 3796 return 0;
3797}
3798
4b79ebf7 3799static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3800 enum pipe pipe,
3801 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3802 uint32_t *val)
3803{
84093603
DV		 3804 struct drm_i915_private *dev_priv = dev->dev_private;
3805 bool need_stable_symbols = false;
3806
46a19188
DV		 3807 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3808 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3809 if (ret)
3810 return ret;
3811 }
3812
3813 switch (*source) {
4b79ebf7
DV		 3814 case INTEL_PIPE_CRC_SOURCE_PIPE:
3815 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3816 break;
3817 case INTEL_PIPE_CRC_SOURCE_TV:
3818 if (!SUPPORTS_TV(dev))
3819 return -EINVAL;
3820 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3821 break;
3822 case INTEL_PIPE_CRC_SOURCE_DP_B:
3823 if (!IS_G4X(dev))
3824 return -EINVAL;
3825 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3826 need_stable_symbols = true;
4b79ebf7
DV		 3827 break;
3828 case INTEL_PIPE_CRC_SOURCE_DP_C:
3829 if (!IS_G4X(dev))
3830 return -EINVAL;
3831 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3832 need_stable_symbols = true;
4b79ebf7
DV		 3833 break;
3834 case INTEL_PIPE_CRC_SOURCE_DP_D:
3835 if (!IS_G4X(dev))
3836 return -EINVAL;
3837 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3838 need_stable_symbols = true;
4b79ebf7
DV		 3839 break;
3840 case INTEL_PIPE_CRC_SOURCE_NONE:
3841 *val = 0;
3842 break;
3843 default:
3844 return -EINVAL;
3845 }
3846
84093603
DV		 3847 /*
3848 * When the pipe CRC tap point is after the transcoders we need
3849 * to tweak symbol-level features to produce a deterministic series of
3850 * symbols for a given frame. We need to reset those features only once
3851 * a frame (instead of every nth symbol):
3852 * - DC-balance: used to ensure a better clock recovery from the data
3853 * link (SDVO)
3854 * - DisplayPort scrambling: used for EMI reduction
3855 */
3856 if (need_stable_symbols) {
3857 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3858
3859 WARN_ON(!IS_G4X(dev));
3860
3861 I915_WRITE(PORT_DFT_I9XX,
3862 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3863
3864 if (pipe == PIPE_A)
3865 tmp |= PIPE_A_SCRAMBLE_RESET;
3866 else
3867 tmp |= PIPE_B_SCRAMBLE_RESET;
3868
3869 I915_WRITE(PORT_DFT2_G4X, tmp);
3870 }
3871
4b79ebf7
DV		 3872 return 0;
3873}
3874
8d2f24ca
DV		 3875static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3876 enum pipe pipe)
3877{
3878 struct drm_i915_private *dev_priv = dev->dev_private;
3879 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3880
eb736679
VS		 3881 switch (pipe) {
3882 case PIPE_A:
8d2f24ca 3883 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3884 break;
3885 case PIPE_B:
8d2f24ca 3886 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3887 break;
3888 case PIPE_C:
3889 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3890 break;
3891 default:
3892 return;
3893 }
8d2f24ca
DV		 3894 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3895 tmp &= ~DC_BALANCE_RESET_VLV;
3896 I915_WRITE(PORT_DFT2_G4X, tmp);
3897
3898}
3899
84093603
DV		 3900static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3901 enum pipe pipe)
3902{
3903 struct drm_i915_private *dev_priv = dev->dev_private;
3904 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3905
3906 if (pipe == PIPE_A)
3907 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3908 else
3909 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3910 I915_WRITE(PORT_DFT2_G4X, tmp);
3911
3912 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3913 I915_WRITE(PORT_DFT_I9XX,
3914 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3915 }
3916}
3917
46a19188 3918static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3919 uint32_t *val)
3920{
46a19188
DV		 3921 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3922 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3923
3924 switch (*source) {
5b3a856b
DV		 3925 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3926 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3927 break;
3928 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3929 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3930 break;
5b3a856b
DV		 3931 case INTEL_PIPE_CRC_SOURCE_PIPE:
3932 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3933 break;
3d099a05 3934 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3935 *val = 0;
3936 break;
3d099a05
DV		 3937 default:
3938 return -EINVAL;
5b3a856b
DV		 3939 }
3940
3941 return 0;
3942}
3943
c4e2d043 3944static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51
DV		 3945{
3946 struct drm_i915_private *dev_priv = dev->dev_private;
3947 struct intel_crtc *crtc =
3948 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3949 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3950 struct drm_atomic_state *state;
3951 int ret = 0;
fabf6e51
DV		 3952
3953 drm_modeset_lock_all(dev);
c4e2d043
ML		 3954 state = drm_atomic_state_alloc(dev);
3955 if (!state) {
3956 ret = -ENOMEM;
3957 goto out;
fabf6e51 3958 }
fabf6e51 3959
c4e2d043
ML		 3960 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3961 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3962 if (IS_ERR(pipe_config)) {
3963 ret = PTR_ERR(pipe_config);
3964 goto out;
3965 }
fabf6e51 3966
c4e2d043
ML		 3967 pipe_config->pch_pfit.force_thru = enable;
3968 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3969 pipe_config->pch_pfit.enabled != enable)
3970 pipe_config->base.connectors_changed = true;
1b509259 3971
c4e2d043
ML		 3972 ret = drm_atomic_commit(state);
3973out:
fabf6e51 3974 drm_modeset_unlock_all(dev);
c4e2d043
ML		 3975 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3976 if (ret)
3977 drm_atomic_state_free(state);
fabf6e51
DV		 3978}
3979
3980static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3981 enum pipe pipe,
3982 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3983 uint32_t *val)
3984{
46a19188
DV		 3985 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3986 *source = INTEL_PIPE_CRC_SOURCE_PF;
3987
3988 switch (*source) {
5b3a856b
DV		 3989 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3990 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3991 break;
3992 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3993 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3994 break;
3995 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 3996 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 3997 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 3998
5b3a856b
DV		 3999 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4000 break;
3d099a05 4001 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 4002 *val = 0;
4003 break;
3d099a05
DV		 4004 default:
4005 return -EINVAL;
5b3a856b
DV		 4006 }
4007
4008 return 0;
4009}
4010
926321d5
DV		 4011static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4012 enum intel_pipe_crc_source source)
4013{
4014 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 4015 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 4016 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4017 pipe));
e129649b 4018 enum intel_display_power_domain power_domain;
432f3342 4019 u32 val = 0; /* shut up gcc */
5b3a856b 4020 int ret;
926321d5 4021
cc3da175
DL		 4022 if (pipe_crc->source == source)
4023 return 0;
4024
ae676fcd
DL		 4025 /* forbid changing the source without going back to 'none' */
4026 if (pipe_crc->source && source)
4027 return -EINVAL;
4028
e129649b
ID		 4029 power_domain = POWER_DOMAIN_PIPE(pipe);
4030 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9d8b0588
DV		 4031 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4032 return -EIO;
4033 }
4034
52f843f6 4035 if (IS_GEN2(dev))
46a19188 4036 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 4037 else if (INTEL_INFO(dev)->gen < 5)
46a19188 4038 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
666a4537 4039 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
fabf6e51 4040 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 4041 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 4042 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 4043 else
fabf6e51 4044 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 4045
4046 if (ret != 0)
e129649b 4047 goto out;
5b3a856b 4048
4b584369
DL		 4049 /* none -> real source transition */
4050 if (source) {
4252fbc3
VS		 4051 struct intel_pipe_crc_entry *entries;
4052
7cd6ccff
DL		 4053 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4054 pipe_name(pipe), pipe_crc_source_name(source));
4055
3cf54b34
VS		 4056 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4057 sizeof(pipe_crc->entries[0]),
4252fbc3 4058 GFP_KERNEL);
e129649b
ID		 4059 if (!entries) {
4060 ret = -ENOMEM;
4061 goto out;
4062 }
e5f75aca 4063
8c740dce
PZ		 4064 /*
4065 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4066 * enabled and disabled dynamically based on package C states,
4067 * user space can't make reliable use of the CRCs, so let's just
4068 * completely disable it.
4069 */
4070 hsw_disable_ips(crtc);
4071
d538bbdf 4072 spin_lock_irq(&pipe_crc->lock);
64387b61 4073 kfree(pipe_crc->entries);
4252fbc3 4074 pipe_crc->entries = entries;
d538bbdf
DL		 4075 pipe_crc->head = 0;
4076 pipe_crc->tail = 0;
4077 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 4078 }
4079
cc3da175 4080 pipe_crc->source = source;
926321d5 4081
926321d5
DV		 4082 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4083 POSTING_READ(PIPE_CRC_CTL(pipe));
4084
e5f75aca
DL		 4085 /* real source -> none transition */
4086 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 4087 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 4088 struct intel_crtc *crtc =
4089 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 4090
7cd6ccff
DL		 4091 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4092 pipe_name(pipe));
4093
a33d7105 4094 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 4095 if (crtc->base.state->active)
a33d7105
DV		 4096 intel_wait_for_vblank(dev, pipe);
4097 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 4098
d538bbdf
DL		 4099 spin_lock_irq(&pipe_crc->lock);
4100 entries = pipe_crc->entries;
e5f75aca 4101 pipe_crc->entries = NULL;
9ad6d99f
VS		 4102 pipe_crc->head = 0;
4103 pipe_crc->tail = 0;
d538bbdf
DL		 4104 spin_unlock_irq(&pipe_crc->lock);
4105
4106 kfree(entries);
84093603
DV		 4107
4108 if (IS_G4X(dev))
4109 g4x_undo_pipe_scramble_reset(dev, pipe);
666a4537 4110 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
8d2f24ca 4111 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 4112 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4113 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 4114
4115 hsw_enable_ips(crtc);
e5f75aca
DL		 4116 }
4117
e129649b
ID		 4118 ret = 0;
4119
4120out:
4121 intel_display_power_put(dev_priv, power_domain);
4122
4123 return ret;
926321d5
DV		 4124}
4125
4126/*
4127 * Parse pipe CRC command strings:
b94dec87
DL		 4128 * command: wsp* object wsp+ name wsp+ source wsp*
4129 * object: 'pipe'
4130 * name: (A | B | C)
926321d5
DV		 4131 * source: (none | plane1 | plane2 | pf)
4132 * wsp: (#0x20 | #0x9 | #0xA)+
4133 *
4134 * eg.:
b94dec87
DL		 4135 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4136 * "pipe A none" -> Stop CRC
926321d5 4137 */
bd9db02f 4138static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 4139{
4140 int n_words = 0;
4141
4142 while (*buf) {
4143 char *end;
4144
4145 /* skip leading white space */
4146 buf = skip_spaces(buf);
4147 if (!*buf)
4148 break; /* end of buffer */
4149
4150 /* find end of word */
4151 for (end = buf; *end && !isspace(*end); end++)
4152 ;
4153
4154 if (n_words == max_words) {
4155 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4156 max_words);
4157 return -EINVAL; /* ran out of words[] before bytes */
4158 }
4159
4160 if (*end)
4161 *end++ = '\0';
4162 words[n_words++] = buf;
4163 buf = end;
4164 }
4165
4166 return n_words;
4167}
4168
b94dec87
DL		 4169enum intel_pipe_crc_object {
4170 PIPE_CRC_OBJECT_PIPE,
4171};
4172
e8dfcf78 4173static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4174 "pipe",
4175};
4176
4177static int
bd9db02f 4178display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4179{
4180 int i;
4181
4182 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4183 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4184 *o = i;
b94dec87
DL		 4185 return 0;
4186 }
4187
4188 return -EINVAL;
4189}
4190
bd9db02f 4191static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4192{
4193 const char name = buf[0];
4194
4195 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4196 return -EINVAL;
4197
4198 *pipe = name - 'A';
4199
4200 return 0;
4201}
4202
4203static int
bd9db02f 4204display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4205{
4206 int i;
4207
4208 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4209 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4210 *s = i;
926321d5
DV		 4211 return 0;
4212 }
4213
4214 return -EINVAL;
4215}
4216
bd9db02f 4217static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 4218{
b94dec87 4219#define N_WORDS 3
926321d5 4220 int n_words;
b94dec87 4221 char *words[N_WORDS];
926321d5 4222 enum pipe pipe;
b94dec87 4223 enum intel_pipe_crc_object object;
926321d5
DV		 4224 enum intel_pipe_crc_source source;
4225
bd9db02f 4226 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4227 if (n_words != N_WORDS) {
4228 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4229 N_WORDS);
4230 return -EINVAL;
4231 }
4232
bd9db02f 4233 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4234 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4235 return -EINVAL;
4236 }
4237
bd9db02f 4238 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4239 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4240 return -EINVAL;
4241 }
4242
bd9db02f 4243 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4244 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4245 return -EINVAL;
4246 }
4247
4248 return pipe_crc_set_source(dev, pipe, source);
4249}
4250
bd9db02f
DL		 4251static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4252 size_t len, loff_t *offp)
926321d5
DV		 4253{
4254 struct seq_file *m = file->private_data;
4255 struct drm_device *dev = m->private;
4256 char *tmpbuf;
4257 int ret;
4258
4259 if (len == 0)
4260 return 0;
4261
4262 if (len > PAGE_SIZE - 1) {
4263 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4264 PAGE_SIZE);
4265 return -E2BIG;
4266 }
4267
4268 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4269 if (!tmpbuf)
4270 return -ENOMEM;
4271
4272 if (copy_from_user(tmpbuf, ubuf, len)) {
4273 ret = -EFAULT;
4274 goto out;
4275 }
4276 tmpbuf[len] = '\0';
4277
bd9db02f 4278 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4279
4280out:
4281 kfree(tmpbuf);
4282 if (ret < 0)
4283 return ret;
4284
4285 *offp += len;
4286 return len;
4287}
4288
bd9db02f 4289static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4290 .owner = THIS_MODULE,
bd9db02f 4291 .open = display_crc_ctl_open,
926321d5
DV		 4292 .read = seq_read,
4293 .llseek = seq_lseek,
4294 .release = single_release,
bd9db02f 4295 .write = display_crc_ctl_write
926321d5
DV		 4296};
4297
eb3394fa
TP		 4298static ssize_t i915_displayport_test_active_write(struct file *file,
4299 const char __user *ubuf,
4300 size_t len, loff_t *offp)
4301{
4302 char *input_buffer;
4303 int status = 0;
eb3394fa
TP		 4304 struct drm_device *dev;
4305 struct drm_connector *connector;
4306 struct list_head *connector_list;
4307 struct intel_dp *intel_dp;
4308 int val = 0;
4309
9aaffa34 4310 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4311
eb3394fa
TP		 4312 connector_list = &dev->mode_config.connector_list;
4313
4314 if (len == 0)
4315 return 0;
4316
4317 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4318 if (!input_buffer)
4319 return -ENOMEM;
4320
4321 if (copy_from_user(input_buffer, ubuf, len)) {
4322 status = -EFAULT;
4323 goto out;
4324 }
4325
4326 input_buffer[len] = '\0';
4327 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4328
4329 list_for_each_entry(connector, connector_list, head) {
4330
4331 if (connector->connector_type !=
4332 DRM_MODE_CONNECTOR_DisplayPort)
4333 continue;
4334
b8bb08ec 4335 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4336 connector->encoder != NULL) {
4337 intel_dp = enc_to_intel_dp(connector->encoder);
4338 status = kstrtoint(input_buffer, 10, &val);
4339 if (status < 0)
4340 goto out;
4341 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4342 /* To prevent erroneous activation of the compliance
4343 * testing code, only accept an actual value of 1 here
4344 */
4345 if (val == 1)
4346 intel_dp->compliance_test_active = 1;
4347 else
4348 intel_dp->compliance_test_active = 0;
4349 }
4350 }
4351out:
4352 kfree(input_buffer);
4353 if (status < 0)
4354 return status;
4355
4356 *offp += len;
4357 return len;
4358}
4359
4360static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4361{
4362 struct drm_device *dev = m->private;
4363 struct drm_connector *connector;
4364 struct list_head *connector_list = &dev->mode_config.connector_list;
4365 struct intel_dp *intel_dp;
4366
eb3394fa
TP		 4367 list_for_each_entry(connector, connector_list, head) {
4368
4369 if (connector->connector_type !=
4370 DRM_MODE_CONNECTOR_DisplayPort)
4371 continue;
4372
4373 if (connector->status == connector_status_connected &&
4374 connector->encoder != NULL) {
4375 intel_dp = enc_to_intel_dp(connector->encoder);
4376 if (intel_dp->compliance_test_active)
4377 seq_puts(m, "1");
4378 else
4379 seq_puts(m, "0");
4380 } else
4381 seq_puts(m, "0");
4382 }
4383
4384 return 0;
4385}
4386
4387static int i915_displayport_test_active_open(struct inode *inode,
4388 struct file *file)
4389{
4390 struct drm_device *dev = inode->i_private;
4391
4392 return single_open(file, i915_displayport_test_active_show, dev);
4393}
4394
4395static const struct file_operations i915_displayport_test_active_fops = {
4396 .owner = THIS_MODULE,
4397 .open = i915_displayport_test_active_open,
4398 .read = seq_read,
4399 .llseek = seq_lseek,
4400 .release = single_release,
4401 .write = i915_displayport_test_active_write
4402};
4403
4404static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4405{
4406 struct drm_device *dev = m->private;
4407 struct drm_connector *connector;
4408 struct list_head *connector_list = &dev->mode_config.connector_list;
4409 struct intel_dp *intel_dp;
4410
eb3394fa
TP		 4411 list_for_each_entry(connector, connector_list, head) {
4412
4413 if (connector->connector_type !=
4414 DRM_MODE_CONNECTOR_DisplayPort)
4415 continue;
4416
4417 if (connector->status == connector_status_connected &&
4418 connector->encoder != NULL) {
4419 intel_dp = enc_to_intel_dp(connector->encoder);
4420 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4421 } else
4422 seq_puts(m, "0");
4423 }
4424
4425 return 0;
4426}
4427static int i915_displayport_test_data_open(struct inode *inode,
4428 struct file *file)
4429{
4430 struct drm_device *dev = inode->i_private;
4431
4432 return single_open(file, i915_displayport_test_data_show, dev);
4433}
4434
4435static const struct file_operations i915_displayport_test_data_fops = {
4436 .owner = THIS_MODULE,
4437 .open = i915_displayport_test_data_open,
4438 .read = seq_read,
4439 .llseek = seq_lseek,
4440 .release = single_release
4441};
4442
4443static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4444{
4445 struct drm_device *dev = m->private;
4446 struct drm_connector *connector;
4447 struct list_head *connector_list = &dev->mode_config.connector_list;
4448 struct intel_dp *intel_dp;
4449
eb3394fa
TP		 4450 list_for_each_entry(connector, connector_list, head) {
4451
4452 if (connector->connector_type !=
4453 DRM_MODE_CONNECTOR_DisplayPort)
4454 continue;
4455
4456 if (connector->status == connector_status_connected &&
4457 connector->encoder != NULL) {
4458 intel_dp = enc_to_intel_dp(connector->encoder);
4459 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4460 } else
4461 seq_puts(m, "0");
4462 }
4463
4464 return 0;
4465}
4466
4467static int i915_displayport_test_type_open(struct inode *inode,
4468 struct file *file)
4469{
4470 struct drm_device *dev = inode->i_private;
4471
4472 return single_open(file, i915_displayport_test_type_show, dev);
4473}
4474
4475static const struct file_operations i915_displayport_test_type_fops = {
4476 .owner = THIS_MODULE,
4477 .open = i915_displayport_test_type_open,
4478 .read = seq_read,
4479 .llseek = seq_lseek,
4480 .release = single_release
4481};
4482
97e94b22 4483static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4484{
4485 struct drm_device *dev = m->private;
369a1342 4486 int level;
de38b95c
VS		 4487 int num_levels;
4488
4489 if (IS_CHERRYVIEW(dev))
4490 num_levels = 3;
4491 else if (IS_VALLEYVIEW(dev))
4492 num_levels = 1;
4493 else
4494 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4495
4496 drm_modeset_lock_all(dev);
4497
4498 for (level = 0; level < num_levels; level++) {
4499 unsigned int latency = wm[level];
4500
97e94b22
DL		 4501 /*
4502 * - WM1+ latency values in 0.5us units
de38b95c 4503 * - latencies are in us on gen9/vlv/chv
97e94b22 4504 */
666a4537
WB		 4505 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4506 IS_CHERRYVIEW(dev))
97e94b22
DL		 4507 latency *= 10;
4508 else if (level > 0)
369a1342
VS		 4509 latency *= 5;
4510
4511 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4512 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4513 }
4514
4515 drm_modeset_unlock_all(dev);
4516}
4517
4518static int pri_wm_latency_show(struct seq_file *m, void *data)
4519{
4520 struct drm_device *dev = m->private;
97e94b22
DL		 4521 struct drm_i915_private *dev_priv = dev->dev_private;
4522 const uint16_t *latencies;
4523
4524 if (INTEL_INFO(dev)->gen >= 9)
4525 latencies = dev_priv->wm.skl_latency;
4526 else
4527 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4528
97e94b22 4529 wm_latency_show(m, latencies);
369a1342
VS		 4530
4531 return 0;
4532}
4533
4534static int spr_wm_latency_show(struct seq_file *m, void *data)
4535{
4536 struct drm_device *dev = m->private;
97e94b22
DL		 4537 struct drm_i915_private *dev_priv = dev->dev_private;
4538 const uint16_t *latencies;
4539
4540 if (INTEL_INFO(dev)->gen >= 9)
4541 latencies = dev_priv->wm.skl_latency;
4542 else
4543 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4544
97e94b22 4545 wm_latency_show(m, latencies);
369a1342
VS		 4546
4547 return 0;
4548}
4549
4550static int cur_wm_latency_show(struct seq_file *m, void *data)
4551{
4552 struct drm_device *dev = m->private;
97e94b22
DL		 4553 struct drm_i915_private *dev_priv = dev->dev_private;
4554 const uint16_t *latencies;
4555
4556 if (INTEL_INFO(dev)->gen >= 9)
4557 latencies = dev_priv->wm.skl_latency;
4558 else
4559 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4560
97e94b22 4561 wm_latency_show(m, latencies);
369a1342
VS		 4562
4563 return 0;
4564}
4565
4566static int pri_wm_latency_open(struct inode *inode, struct file *file)
4567{
4568 struct drm_device *dev = inode->i_private;
4569
de38b95c 4570 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4571 return -ENODEV;
4572
4573 return single_open(file, pri_wm_latency_show, dev);
4574}
4575
4576static int spr_wm_latency_open(struct inode *inode, struct file *file)
4577{
4578 struct drm_device *dev = inode->i_private;
4579
9ad0257c 4580 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4581 return -ENODEV;
4582
4583 return single_open(file, spr_wm_latency_show, dev);
4584}
4585
4586static int cur_wm_latency_open(struct inode *inode, struct file *file)
4587{
4588 struct drm_device *dev = inode->i_private;
4589
9ad0257c 4590 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4591 return -ENODEV;
4592
4593 return single_open(file, cur_wm_latency_show, dev);
4594}
4595
4596static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4597 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4598{
4599 struct seq_file *m = file->private_data;
4600 struct drm_device *dev = m->private;
97e94b22 4601 uint16_t new[8] = { 0 };
de38b95c 4602 int num_levels;
369a1342
VS		 4603 int level;
4604 int ret;
4605 char tmp[32];
4606
de38b95c
VS		 4607 if (IS_CHERRYVIEW(dev))
4608 num_levels = 3;
4609 else if (IS_VALLEYVIEW(dev))
4610 num_levels = 1;
4611 else
4612 num_levels = ilk_wm_max_level(dev) + 1;
4613
369a1342
VS		 4614 if (len >= sizeof(tmp))
4615 return -EINVAL;
4616
4617 if (copy_from_user(tmp, ubuf, len))
4618 return -EFAULT;
4619
4620 tmp[len] = '\0';
4621
97e94b22
DL		 4622 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4623 &new[0], &new[1], &new[2], &new[3],
4624 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4625 if (ret != num_levels)
4626 return -EINVAL;
4627
4628 drm_modeset_lock_all(dev);
4629
4630 for (level = 0; level < num_levels; level++)
4631 wm[level] = new[level];
4632
4633 drm_modeset_unlock_all(dev);
4634
4635 return len;
4636}
4637
4638
4639static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4640 size_t len, loff_t *offp)
4641{
4642 struct seq_file *m = file->private_data;
4643 struct drm_device *dev = m->private;
97e94b22
DL		 4644 struct drm_i915_private *dev_priv = dev->dev_private;
4645 uint16_t *latencies;
369a1342 4646
97e94b22
DL		 4647 if (INTEL_INFO(dev)->gen >= 9)
4648 latencies = dev_priv->wm.skl_latency;
4649 else
4650 latencies = to_i915(dev)->wm.pri_latency;
4651
4652 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4653}
4654
4655static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4656 size_t len, loff_t *offp)
4657{
4658 struct seq_file *m = file->private_data;
4659 struct drm_device *dev = m->private;
97e94b22
DL		 4660 struct drm_i915_private *dev_priv = dev->dev_private;
4661 uint16_t *latencies;
369a1342 4662
97e94b22
DL		 4663 if (INTEL_INFO(dev)->gen >= 9)
4664 latencies = dev_priv->wm.skl_latency;
4665 else
4666 latencies = to_i915(dev)->wm.spr_latency;
4667
4668 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4669}
4670
4671static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4672 size_t len, loff_t *offp)
4673{
4674 struct seq_file *m = file->private_data;
4675 struct drm_device *dev = m->private;
97e94b22
DL		 4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677 uint16_t *latencies;
4678
4679 if (INTEL_INFO(dev)->gen >= 9)
4680 latencies = dev_priv->wm.skl_latency;
4681 else
4682 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4683
97e94b22 4684 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4685}
4686
4687static const struct file_operations i915_pri_wm_latency_fops = {
4688 .owner = THIS_MODULE,
4689 .open = pri_wm_latency_open,
4690 .read = seq_read,
4691 .llseek = seq_lseek,
4692 .release = single_release,
4693 .write = pri_wm_latency_write
4694};
4695
4696static const struct file_operations i915_spr_wm_latency_fops = {
4697 .owner = THIS_MODULE,
4698 .open = spr_wm_latency_open,
4699 .read = seq_read,
4700 .llseek = seq_lseek,
4701 .release = single_release,
4702 .write = spr_wm_latency_write
4703};
4704
4705static const struct file_operations i915_cur_wm_latency_fops = {
4706 .owner = THIS_MODULE,
4707 .open = cur_wm_latency_open,
4708 .read = seq_read,
4709 .llseek = seq_lseek,
4710 .release = single_release,
4711 .write = cur_wm_latency_write
4712};
4713
647416f9
KC		 4714static int
4715i915_wedged_get(void *data, u64 *val)
f3cd474b 4716{
647416f9 4717 struct drm_device *dev = data;
e277a1f8 4718 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4719
647416f9 4720 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4721
647416f9 4722 return 0;
f3cd474b
CW		 4723}
4724
647416f9
KC		 4725static int
4726i915_wedged_set(void *data, u64 val)
f3cd474b 4727{
647416f9 4728 struct drm_device *dev = data;
d46c0517
ID		 4729 struct drm_i915_private *dev_priv = dev->dev_private;
4730
b8d24a06
MK		 4731 /*
4732 * There is no safeguard against this debugfs entry colliding
4733 * with the hangcheck calling same i915_handle_error() in
4734 * parallel, causing an explosion. For now we assume that the
4735 * test harness is responsible enough not to inject gpu hangs
4736 * while it is writing to 'i915_wedged'
4737 */
4738
4739 if (i915_reset_in_progress(&dev_priv->gpu_error))
4740 return -EAGAIN;
4741
d46c0517 4742 intel_runtime_pm_get(dev_priv);
f3cd474b 4743
58174462
MK		 4744 i915_handle_error(dev, val,
4745 "Manually setting wedged to %llu", val);
d46c0517
ID		 4746
4747 intel_runtime_pm_put(dev_priv);
4748
647416f9 4749 return 0;
f3cd474b
CW		 4750}
4751
647416f9
KC		 4752DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4753 i915_wedged_get, i915_wedged_set,
3a3b4f98 4754 "%llu\n");
f3cd474b 4755
647416f9
KC		 4756static int
4757i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4758{
647416f9 4759 struct drm_device *dev = data;
e277a1f8 4760 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4761
647416f9 4762 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4763
647416f9 4764 return 0;
e5eb3d63
DV		 4765}
4766
647416f9
KC		 4767static int
4768i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4769{
647416f9 4770 struct drm_device *dev = data;
e5eb3d63 4771 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4772 int ret;
e5eb3d63 4773
647416f9 4774 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4775
22bcfc6a
DV		 4776 ret = mutex_lock_interruptible(&dev->struct_mutex);
4777 if (ret)
4778 return ret;
4779
99584db3 4780 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4781 mutex_unlock(&dev->struct_mutex);
4782
647416f9 4783 return 0;
e5eb3d63
DV		 4784}
4785
647416f9
KC		 4786DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4787 i915_ring_stop_get, i915_ring_stop_set,
4788 "0x%08llx\n");
d5442303 4789
094f9a54
CW		 4790static int
4791i915_ring_missed_irq_get(void *data, u64 *val)
4792{
4793 struct drm_device *dev = data;
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795
4796 *val = dev_priv->gpu_error.missed_irq_rings;
4797 return 0;
4798}
4799
4800static int
4801i915_ring_missed_irq_set(void *data, u64 val)
4802{
4803 struct drm_device *dev = data;
4804 struct drm_i915_private *dev_priv = dev->dev_private;
4805 int ret;
4806
4807 /* Lock against concurrent debugfs callers */
4808 ret = mutex_lock_interruptible(&dev->struct_mutex);
4809 if (ret)
4810 return ret;
4811 dev_priv->gpu_error.missed_irq_rings = val;
4812 mutex_unlock(&dev->struct_mutex);
4813
4814 return 0;
4815}
4816
4817DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4818 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4819 "0x%08llx\n");
4820
4821static int
4822i915_ring_test_irq_get(void *data, u64 *val)
4823{
4824 struct drm_device *dev = data;
4825 struct drm_i915_private *dev_priv = dev->dev_private;
4826
4827 *val = dev_priv->gpu_error.test_irq_rings;
4828
4829 return 0;
4830}
4831
4832static int
4833i915_ring_test_irq_set(void *data, u64 val)
4834{
4835 struct drm_device *dev = data;
4836 struct drm_i915_private *dev_priv = dev->dev_private;
4837 int ret;
4838
4839 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4840
4841 /* Lock against concurrent debugfs callers */
4842 ret = mutex_lock_interruptible(&dev->struct_mutex);
4843 if (ret)
4844 return ret;
4845
4846 dev_priv->gpu_error.test_irq_rings = val;
4847 mutex_unlock(&dev->struct_mutex);
4848
4849 return 0;
4850}
4851
4852DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4853 i915_ring_test_irq_get, i915_ring_test_irq_set,
4854 "0x%08llx\n");
4855
dd624afd
CW		 4856#define DROP_UNBOUND 0x1
4857#define DROP_BOUND 0x2
4858#define DROP_RETIRE 0x4
4859#define DROP_ACTIVE 0x8
4860#define DROP_ALL (DROP_UNBOUND | \
4861 DROP_BOUND | \
4862 DROP_RETIRE | \
4863 DROP_ACTIVE)
647416f9
KC		 4864static int
4865i915_drop_caches_get(void *data, u64 *val)
dd624afd 4866{
647416f9 4867 *val = DROP_ALL;
dd624afd 4868
647416f9 4869 return 0;
dd624afd
CW		 4870}
4871
647416f9
KC		 4872static int
4873i915_drop_caches_set(void *data, u64 val)
dd624afd 4874{
647416f9 4875 struct drm_device *dev = data;
dd624afd 4876 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4877 int ret;
dd624afd 4878
2f9fe5ff 4879 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4880
4881 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4882 * on ioctls on -EAGAIN. */
4883 ret = mutex_lock_interruptible(&dev->struct_mutex);
4884 if (ret)
4885 return ret;
4886
4887 if (val & DROP_ACTIVE) {
4888 ret = i915_gpu_idle(dev);
4889 if (ret)
4890 goto unlock;
4891 }
4892
4893 if (val & (DROP_RETIRE | DROP_ACTIVE))
4894 i915_gem_retire_requests(dev);
4895
21ab4e74
CW		 4896 if (val & DROP_BOUND)
4897 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4898
21ab4e74
CW		 4899 if (val & DROP_UNBOUND)
4900 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4901
4902unlock:
4903 mutex_unlock(&dev->struct_mutex);
4904
647416f9 4905 return ret;
dd624afd
CW		 4906}
4907
647416f9
KC		 4908DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4909 i915_drop_caches_get, i915_drop_caches_set,
4910 "0x%08llx\n");
dd624afd 4911
647416f9
KC		 4912static int
4913i915_max_freq_get(void *data, u64 *val)
358733e9 4914{
647416f9 4915 struct drm_device *dev = data;
e277a1f8 4916 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4917 int ret;
004777cb 4918
daa3afb2 4919 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4920 return -ENODEV;
4921
5c9669ce
TR		 4922 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4923
4fc688ce 4924 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4925 if (ret)
4926 return ret;
358733e9 4927
7c59a9c1 4928 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4929 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4930
647416f9 4931 return 0;
358733e9
JB		 4932}
4933
647416f9
KC		 4934static int
4935i915_max_freq_set(void *data, u64 val)
358733e9 4936{
647416f9 4937 struct drm_device *dev = data;
358733e9 4938 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4939 u32 hw_max, hw_min;
647416f9 4940 int ret;
004777cb 4941
daa3afb2 4942 if (INTEL_INFO(dev)->gen < 6)
004777cb 4943 return -ENODEV;
358733e9 4944
5c9669ce
TR		 4945 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4946
647416f9 4947 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4948
4fc688ce 4949 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4950 if (ret)
4951 return ret;
4952
358733e9
JB		 4953 /*
4954 * Turbo will still be enabled, but won't go above the set value.
4955 */
bc4d91f6 4956 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4957
bc4d91f6
AG		 4958 hw_max = dev_priv->rps.max_freq;
4959 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4960
b39fb297 4961 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4962 mutex_unlock(&dev_priv->rps.hw_lock);
4963 return -EINVAL;
0a073b84
JB		 4964 }
4965
b39fb297 4966 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4967
ffe02b40 4968 intel_set_rps(dev, val);
dd0a1aa1 4969
4fc688ce 4970 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4971
647416f9 4972 return 0;
358733e9
JB		 4973}
4974
647416f9
KC		 4975DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4976 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4977 "%llu\n");
358733e9 4978
647416f9
KC		 4979static int
4980i915_min_freq_get(void *data, u64 *val)
1523c310 4981{
647416f9 4982 struct drm_device *dev = data;
e277a1f8 4983 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4984 int ret;
004777cb 4985
daa3afb2 4986 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4987 return -ENODEV;
4988
5c9669ce
TR		 4989 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4990
4fc688ce 4991 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4992 if (ret)
4993 return ret;
1523c310 4994
7c59a9c1 4995 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4996 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4997
647416f9 4998 return 0;
1523c310
JB		 4999}
5000
647416f9
KC		 5001static int
5002i915_min_freq_set(void *data, u64 val)
1523c310 5003{
647416f9 5004 struct drm_device *dev = data;
1523c310 5005 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 5006 u32 hw_max, hw_min;
647416f9 5007 int ret;
004777cb 5008
daa3afb2 5009 if (INTEL_INFO(dev)->gen < 6)
004777cb 5010 return -ENODEV;
1523c310 5011
5c9669ce
TR		 5012 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5013
647416f9 5014 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 5015
4fc688ce 5016 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 5017 if (ret)
5018 return ret;
5019
1523c310
JB		 5020 /*
5021 * Turbo will still be enabled, but won't go below the set value.
5022 */
bc4d91f6 5023 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 5024
bc4d91f6
AG		 5025 hw_max = dev_priv->rps.max_freq;
5026 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 5027
b39fb297 5028 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 5029 mutex_unlock(&dev_priv->rps.hw_lock);
5030 return -EINVAL;
0a073b84 5031 }
dd0a1aa1 5032
b39fb297 5033 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 5034
ffe02b40 5035 intel_set_rps(dev, val);
dd0a1aa1 5036
4fc688ce 5037 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 5038
647416f9 5039 return 0;
1523c310
JB		 5040}
5041
647416f9
KC		 5042DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5043 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 5044 "%llu\n");
1523c310 5045
647416f9
KC		 5046static int
5047i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 5048{
647416f9 5049 struct drm_device *dev = data;
e277a1f8 5050 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5051 u32 snpcr;
647416f9 5052 int ret;
07b7ddd9 5053
004777cb
DV		 5054 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5055 return -ENODEV;
5056
22bcfc6a
DV		 5057 ret = mutex_lock_interruptible(&dev->struct_mutex);
5058 if (ret)
5059 return ret;
c8c8fb33 5060 intel_runtime_pm_get(dev_priv);
22bcfc6a 5061
07b7ddd9 5062 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 5063
5064 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 5065 mutex_unlock(&dev_priv->dev->struct_mutex);
5066
647416f9 5067 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 5068
647416f9 5069 return 0;
07b7ddd9
JB		 5070}
5071
647416f9
KC		 5072static int
5073i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 5074{
647416f9 5075 struct drm_device *dev = data;
07b7ddd9 5076 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5077 u32 snpcr;
07b7ddd9 5078
004777cb
DV		 5079 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5080 return -ENODEV;
5081
647416f9 5082 if (val > 3)
07b7ddd9
JB		 5083 return -EINVAL;
5084
c8c8fb33 5085 intel_runtime_pm_get(dev_priv);
647416f9 5086 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 5087
5088 /* Update the cache sharing policy here as well */
5089 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5090 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5091 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5092 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5093
c8c8fb33 5094 intel_runtime_pm_put(dev_priv);
647416f9 5095 return 0;
07b7ddd9
JB		 5096}
5097
647416f9
KC		 5098DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5099 i915_cache_sharing_get, i915_cache_sharing_set,
5100 "%llu\n");
07b7ddd9 5101
5d39525a
JM		 5102struct sseu_dev_status {
5103 unsigned int slice_total;
5104 unsigned int subslice_total;
5105 unsigned int subslice_per_slice;
5106 unsigned int eu_total;
5107 unsigned int eu_per_subslice;
5108};
5109
5110static void cherryview_sseu_device_status(struct drm_device *dev,
5111 struct sseu_dev_status *stat)
5112{
5113 struct drm_i915_private *dev_priv = dev->dev_private;
0a0b457f 5114 int ss_max = 2;
5d39525a
JM		 5115 int ss;
5116 u32 sig1[ss_max], sig2[ss_max];
5117
5118 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5119 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5120 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5121 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5122
5123 for (ss = 0; ss < ss_max; ss++) {
5124 unsigned int eu_cnt;
5125
5126 if (sig1[ss] & CHV_SS_PG_ENABLE)
5127 /* skip disabled subslice */
5128 continue;
5129
5130 stat->slice_total = 1;
5131 stat->subslice_per_slice++;
5132 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5133 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5134 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5135 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5136 stat->eu_total += eu_cnt;
5137 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5138 }
5139 stat->subslice_total = stat->subslice_per_slice;
5140}
5141
5142static void gen9_sseu_device_status(struct drm_device *dev,
5143 struct sseu_dev_status *stat)
5144{
5145 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 5146 int s_max = 3, ss_max = 4;
5d39525a
JM		 5147 int s, ss;
5148 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5149
1c046bc1
JM		 5150 /* BXT has a single slice and at most 3 subslices. */
5151 if (IS_BROXTON(dev)) {
5152 s_max = 1;
5153 ss_max = 3;
5154 }
5155
5156 for (s = 0; s < s_max; s++) {
5157 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5158 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5159 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5160 }
5161
5d39525a
JM		 5162 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5163 GEN9_PGCTL_SSA_EU19_ACK |
5164 GEN9_PGCTL_SSA_EU210_ACK |
5165 GEN9_PGCTL_SSA_EU311_ACK;
5166 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5167 GEN9_PGCTL_SSB_EU19_ACK |
5168 GEN9_PGCTL_SSB_EU210_ACK |
5169 GEN9_PGCTL_SSB_EU311_ACK;
5170
5171 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 5172 unsigned int ss_cnt = 0;
5173
5d39525a
JM		 5174 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5175 /* skip disabled slice */
5176 continue;
5177
5178 stat->slice_total++;
1c046bc1 5179
ef11bdb3 5180 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1c046bc1
JM		 5181 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5182
5d39525a
JM		 5183 for (ss = 0; ss < ss_max; ss++) {
5184 unsigned int eu_cnt;
5185
1c046bc1
JM		 5186 if (IS_BROXTON(dev) &&
5187 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5188 /* skip disabled subslice */
5189 continue;
5190
5191 if (IS_BROXTON(dev))
5192 ss_cnt++;
5193
5d39525a
JM		 5194 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5195 eu_mask[ss%2]);
5196 stat->eu_total += eu_cnt;
5197 stat->eu_per_subslice = max(stat->eu_per_subslice,
5198 eu_cnt);
5199 }
1c046bc1
JM		 5200
5201 stat->subslice_total += ss_cnt;
5202 stat->subslice_per_slice = max(stat->subslice_per_slice,
5203 ss_cnt);
5d39525a
JM		 5204 }
5205}
5206
91bedd34
ŁD		 5207static void broadwell_sseu_device_status(struct drm_device *dev,
5208 struct sseu_dev_status *stat)
5209{
5210 struct drm_i915_private *dev_priv = dev->dev_private;
5211 int s;
5212 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5213
5214 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5215
5216 if (stat->slice_total) {
5217 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5218 stat->subslice_total = stat->slice_total *
5219 stat->subslice_per_slice;
5220 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5221 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5222
5223 /* subtract fused off EU(s) from enabled slice(s) */
5224 for (s = 0; s < stat->slice_total; s++) {
5225 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5226
5227 stat->eu_total -= hweight8(subslice_7eu);
5228 }
5229 }
5230}
5231
3873218f
JM		 5232static int i915_sseu_status(struct seq_file *m, void *unused)
5233{
5234 struct drm_info_node *node = (struct drm_info_node *) m->private;
5235 struct drm_device *dev = node->minor->dev;
5d39525a 5236 struct sseu_dev_status stat;
3873218f 5237
91bedd34 5238 if (INTEL_INFO(dev)->gen < 8)
3873218f
JM		 5239 return -ENODEV;
5240
5241 seq_puts(m, "SSEU Device Info\n");
5242 seq_printf(m, " Available Slice Total: %u\n",
5243 INTEL_INFO(dev)->slice_total);
5244 seq_printf(m, " Available Subslice Total: %u\n",
5245 INTEL_INFO(dev)->subslice_total);
5246 seq_printf(m, " Available Subslice Per Slice: %u\n",
5247 INTEL_INFO(dev)->subslice_per_slice);
5248 seq_printf(m, " Available EU Total: %u\n",
5249 INTEL_INFO(dev)->eu_total);
5250 seq_printf(m, " Available EU Per Subslice: %u\n",
5251 INTEL_INFO(dev)->eu_per_subslice);
5252 seq_printf(m, " Has Slice Power Gating: %s\n",
5253 yesno(INTEL_INFO(dev)->has_slice_pg));
5254 seq_printf(m, " Has Subslice Power Gating: %s\n",
5255 yesno(INTEL_INFO(dev)->has_subslice_pg));
5256 seq_printf(m, " Has EU Power Gating: %s\n",
5257 yesno(INTEL_INFO(dev)->has_eu_pg));
5258
7f992aba 5259 seq_puts(m, "SSEU Device Status\n");
5d39525a 5260 memset(&stat, 0, sizeof(stat));
5575f03a 5261 if (IS_CHERRYVIEW(dev)) {
5d39525a 5262 cherryview_sseu_device_status(dev, &stat);
91bedd34
ŁD		 5263 } else if (IS_BROADWELL(dev)) {
5264 broadwell_sseu_device_status(dev, &stat);
1c046bc1 5265 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 5266 gen9_sseu_device_status(dev, &stat);
7f992aba 5267 }
5d39525a
JM		 5268 seq_printf(m, " Enabled Slice Total: %u\n",
5269 stat.slice_total);
5270 seq_printf(m, " Enabled Subslice Total: %u\n",
5271 stat.subslice_total);
5272 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5273 stat.subslice_per_slice);
5274 seq_printf(m, " Enabled EU Total: %u\n",
5275 stat.eu_total);
5276 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5277 stat.eu_per_subslice);
7f992aba 5278
3873218f
JM		 5279 return 0;
5280}
5281
6d794d42
BW		 5282static int i915_forcewake_open(struct inode *inode, struct file *file)
5283{
5284 struct drm_device *dev = inode->i_private;
5285 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 5286
075edca4 5287 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5288 return 0;
5289
6daccb0b 5290 intel_runtime_pm_get(dev_priv);
59bad947 5291 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5292
5293 return 0;
5294}
5295
c43b5634 5296static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5297{
5298 struct drm_device *dev = inode->i_private;
5299 struct drm_i915_private *dev_priv = dev->dev_private;
5300
075edca4 5301 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5302 return 0;
5303
59bad947 5304 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5305 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5306
5307 return 0;
5308}
5309
5310static const struct file_operations i915_forcewake_fops = {
5311 .owner = THIS_MODULE,
5312 .open = i915_forcewake_open,
5313 .release = i915_forcewake_release,
5314};
5315
5316static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5317{
5318 struct drm_device *dev = minor->dev;
5319 struct dentry *ent;
5320
5321 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5322 S_IRUSR,
6d794d42
BW		 5323 root, dev,
5324 &i915_forcewake_fops);
f3c5fe97
WY		 5325 if (!ent)
5326 return -ENOMEM;
6d794d42 5327
8eb57294 5328 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5329}
5330
6a9c308d
DV		 5331static int i915_debugfs_create(struct dentry *root,
5332 struct drm_minor *minor,
5333 const char *name,
5334 const struct file_operations *fops)
07b7ddd9
JB		 5335{
5336 struct drm_device *dev = minor->dev;
5337 struct dentry *ent;
5338
6a9c308d 5339 ent = debugfs_create_file(name,
07b7ddd9
JB		 5340 S_IRUGO | S_IWUSR,
5341 root, dev,
6a9c308d 5342 fops);
f3c5fe97
WY		 5343 if (!ent)
5344 return -ENOMEM;
07b7ddd9 5345
6a9c308d 5346 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5347}
5348
06c5bf8c 5349static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5350 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5351 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5352 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5353 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5354 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5355 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5356 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5357 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5358 {"i915_gem_request", i915_gem_request_info, 0},
5359 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5360 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5361 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5362 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5363 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5364 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5365 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5366 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5367 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5368 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5369 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5370 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5371 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5372 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5373 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5374 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5375 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5376 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5377 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5378 {"i915_sr_status", i915_sr_status, 0},
44834a67 5379 {"i915_opregion", i915_opregion, 0},
ada8f955 5380 {"i915_vbt", i915_vbt, 0},
37811fcc 5381 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5382 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5383 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5384 {"i915_execlists", i915_execlists, 0},
f65367b5 5385 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5386 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5387 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5388 {"i915_llc", i915_llc, 0},
e91fd8c6 5389 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5390 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5391 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5392 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5393 {"i915_power_domain_info", i915_power_domain_info, 0},
b7cec66d 5394 {"i915_dmc_info", i915_dmc_info, 0},
53f5e3ca 5395 {"i915_display_info", i915_display_info, 0},
e04934cf 5396 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5397 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5398 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5399 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5400 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5401 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5402 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5403 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5404};
27c202ad 5405#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5406
06c5bf8c 5407static const struct i915_debugfs_files {
34b9674c
DV		 5408 const char *name;
5409 const struct file_operations *fops;
5410} i915_debugfs_files[] = {
5411 {"i915_wedged", &i915_wedged_fops},
5412 {"i915_max_freq", &i915_max_freq_fops},
5413 {"i915_min_freq", &i915_min_freq_fops},
5414 {"i915_cache_sharing", &i915_cache_sharing_fops},
5415 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5416 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5417 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5418 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5419 {"i915_error_state", &i915_error_state_fops},
5420 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5421 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5422 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5423 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5424 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5425 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5426 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5427 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5428 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5429};
5430
07144428
DL		 5431void intel_display_crc_init(struct drm_device *dev)
5432{
5433 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5434 enum pipe pipe;
07144428 5435
055e393f 5436 for_each_pipe(dev_priv, pipe) {
b378360e 5437 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5438
d538bbdf
DL		 5439 pipe_crc->opened = false;
5440 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5441 init_waitqueue_head(&pipe_crc->wq);
5442 }
5443}
5444
27c202ad 5445int i915_debugfs_init(struct drm_minor *minor)
2017263e 5446{
34b9674c 5447 int ret, i;
f3cd474b 5448
6d794d42 5449 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5450 if (ret)
5451 return ret;
6a9c308d 5452
07144428
DL		 5453 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5454 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5455 if (ret)
5456 return ret;
5457 }
5458
34b9674c
DV		 5459 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5460 ret = i915_debugfs_create(minor->debugfs_root, minor,
5461 i915_debugfs_files[i].name,
5462 i915_debugfs_files[i].fops);
5463 if (ret)
5464 return ret;
5465 }
40633219 5466
27c202ad
BG		 5467 return drm_debugfs_create_files(i915_debugfs_list,
5468 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5469 minor->debugfs_root, minor);
5470}
5471
27c202ad 5472void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5473{
34b9674c
DV		 5474 int i;
5475
27c202ad
BG		 5476 drm_debugfs_remove_files(i915_debugfs_list,
5477 I915_DEBUGFS_ENTRIES, minor);
07144428 5478
6d794d42
BW		 5479 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5480 1, minor);
07144428 5481
e309a997 5482 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5483 struct drm_info_list *info_list =
5484 (struct drm_info_list *)&i915_pipe_crc_data[i];
5485
5486 drm_debugfs_remove_files(info_list, 1, minor);
5487 }
5488
34b9674c
DV		 5489 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5490 struct drm_info_list *info_list =
5491 (struct drm_info_list *) i915_debugfs_files[i].fops;
5492
5493 drm_debugfs_remove_files(info_list, 1, minor);
5494 }
2017263e 5495}
aa7471d2
JN		 5496
5497struct dpcd_block {
5498 /* DPCD dump start address. */
5499 unsigned int offset;
5500 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5501 unsigned int end;
5502 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5503 size_t size;
5504 /* Only valid for eDP. */
5505 bool edp;
5506};
5507
5508static const struct dpcd_block i915_dpcd_debug[] = {
5509 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5510 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5511 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5512 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5513 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5514 { .offset = DP_SET_POWER },
5515 { .offset = DP_EDP_DPCD_REV },
5516 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5517 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5518 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5519};
5520
5521static int i915_dpcd_show(struct seq_file *m, void *data)
5522{
5523 struct drm_connector *connector = m->private;
5524 struct intel_dp *intel_dp =
5525 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5526 uint8_t buf[16];
5527 ssize_t err;
5528 int i;
5529
5c1a8875
MK		 5530 if (connector->status != connector_status_connected)
5531 return -ENODEV;
5532
aa7471d2
JN		 5533 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5534 const struct dpcd_block *b = &i915_dpcd_debug[i];
5535 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5536
5537 if (b->edp &&
5538 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5539 continue;
5540
5541 /* low tech for now */
5542 if (WARN_ON(size > sizeof(buf)))
5543 continue;
5544
5545 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5546 if (err <= 0) {
5547 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5548 size, b->offset, err);
5549 continue;
5550 }
5551
5552 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5553 }
aa7471d2
JN		 5554
5555 return 0;
5556}
5557
5558static int i915_dpcd_open(struct inode *inode, struct file *file)
5559{
5560 return single_open(file, i915_dpcd_show, inode->i_private);
5561}
5562
5563static const struct file_operations i915_dpcd_fops = {
5564 .owner = THIS_MODULE,
5565 .open = i915_dpcd_open,
5566 .read = seq_read,
5567 .llseek = seq_lseek,
5568 .release = single_release,
5569};
5570
5571/**
5572 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5573 * @connector: pointer to a registered drm_connector
5574 *
5575 * Cleanup will be done by drm_connector_unregister() through a call to
5576 * drm_debugfs_connector_remove().
5577 *
5578 * Returns 0 on success, negative error codes on error.
5579 */
5580int i915_debugfs_connector_add(struct drm_connector *connector)
5581{
5582 struct dentry *root = connector->debugfs_entry;
5583
5584 /* The connector must have been registered beforehands. */
5585 if (!root)
5586 return -ENODEV;
5587
5588 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5589 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5590 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5591 &i915_dpcd_fops);
5592
5593 return 0;
5594}
Linux kernel - Deliverables
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