Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
497666d8 DL |
49 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
50 | * allocated we need to hook into the minor for release. */ | |
51 | static int | |
52 | drm_add_fake_info_node(struct drm_minor *minor, | |
53 | struct dentry *ent, | |
54 | const void *key) | |
55 | { | |
56 | struct drm_info_node *node; | |
57 | ||
58 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
59 | if (node == NULL) { | |
60 | debugfs_remove(ent); | |
61 | return -ENOMEM; | |
62 | } | |
63 | ||
64 | node->minor = minor; | |
65 | node->dent = ent; | |
66 | node->info_ent = (void *) key; | |
67 | ||
68 | mutex_lock(&minor->debugfs_lock); | |
69 | list_add(&node->list, &minor->debugfs_list); | |
70 | mutex_unlock(&minor->debugfs_lock); | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
70d39fe4 CW |
75 | static int i915_capabilities(struct seq_file *m, void *data) |
76 | { | |
9f25d007 | 77 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
78 | struct drm_device *dev = node->minor->dev; |
79 | const struct intel_device_info *info = INTEL_INFO(dev); | |
80 | ||
81 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 82 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
83 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
84 | #define SEP_SEMICOLON ; | |
85 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
86 | #undef PRINT_FLAG | |
87 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
88 | |
89 | return 0; | |
90 | } | |
2017263e | 91 | |
be12a86b | 92 | static const char get_active_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 93 | { |
be12a86b | 94 | return obj->active ? '*' : ' '; |
a6172a80 CW |
95 | } |
96 | ||
be12a86b TU |
97 | static const char get_pin_flag(struct drm_i915_gem_object *obj) |
98 | { | |
99 | return obj->pin_display ? 'p' : ' '; | |
100 | } | |
101 | ||
102 | static const char get_tiling_flag(struct drm_i915_gem_object *obj) | |
a6172a80 | 103 | { |
0206e353 AJ |
104 | switch (obj->tiling_mode) { |
105 | default: | |
be12a86b TU |
106 | case I915_TILING_NONE: return ' '; |
107 | case I915_TILING_X: return 'X'; | |
108 | case I915_TILING_Y: return 'Y'; | |
0206e353 | 109 | } |
a6172a80 CW |
110 | } |
111 | ||
be12a86b TU |
112 | static inline const char get_global_flag(struct drm_i915_gem_object *obj) |
113 | { | |
114 | return i915_gem_obj_to_ggtt(obj) ? 'g' : ' '; | |
115 | } | |
116 | ||
117 | static inline const char get_pin_mapped_flag(struct drm_i915_gem_object *obj) | |
1d693bcc | 118 | { |
be12a86b | 119 | return obj->mapping ? 'M' : ' '; |
1d693bcc BW |
120 | } |
121 | ||
ca1543be TU |
122 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
123 | { | |
124 | u64 size = 0; | |
125 | struct i915_vma *vma; | |
126 | ||
1c7f4bca | 127 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
596c5923 | 128 | if (vma->is_ggtt && drm_mm_node_allocated(&vma->node)) |
ca1543be TU |
129 | size += vma->node.size; |
130 | } | |
131 | ||
132 | return size; | |
133 | } | |
134 | ||
37811fcc CW |
135 | static void |
136 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
137 | { | |
b4716185 | 138 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e2f80391 | 139 | struct intel_engine_cs *engine; |
1d693bcc | 140 | struct i915_vma *vma; |
d7f46fc4 | 141 | int pin_count = 0; |
c3232b18 | 142 | enum intel_engine_id id; |
d7f46fc4 | 143 | |
188c1ab7 CW |
144 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
145 | ||
be12a86b | 146 | seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ", |
37811fcc | 147 | &obj->base, |
be12a86b | 148 | get_active_flag(obj), |
37811fcc CW |
149 | get_pin_flag(obj), |
150 | get_tiling_flag(obj), | |
1d693bcc | 151 | get_global_flag(obj), |
be12a86b | 152 | get_pin_mapped_flag(obj), |
a05a5862 | 153 | obj->base.size / 1024, |
37811fcc | 154 | obj->base.read_domains, |
b4716185 | 155 | obj->base.write_domain); |
c3232b18 | 156 | for_each_engine_id(engine, dev_priv, id) |
b4716185 | 157 | seq_printf(m, "%x ", |
c3232b18 | 158 | i915_gem_request_get_seqno(obj->last_read_req[id])); |
b4716185 | 159 | seq_printf(m, "] %x %x%s%s%s", |
97b2a6a1 JH |
160 | i915_gem_request_get_seqno(obj->last_write_req), |
161 | i915_gem_request_get_seqno(obj->last_fenced_req), | |
0a4cd7c8 | 162 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
37811fcc CW |
163 | obj->dirty ? " dirty" : "", |
164 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
165 | if (obj->base.name) | |
166 | seq_printf(m, " (name: %d)", obj->base.name); | |
1c7f4bca | 167 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
d7f46fc4 BW |
168 | if (vma->pin_count > 0) |
169 | pin_count++; | |
ba0635ff DC |
170 | } |
171 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
172 | if (obj->pin_display) |
173 | seq_printf(m, " (display)"); | |
37811fcc CW |
174 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
175 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1c7f4bca | 176 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
8d2fdc3f | 177 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
596c5923 | 178 | vma->is_ggtt ? "g" : "pp", |
8d2fdc3f | 179 | vma->node.start, vma->node.size); |
596c5923 CW |
180 | if (vma->is_ggtt) |
181 | seq_printf(m, ", type: %u", vma->ggtt_view.type); | |
182 | seq_puts(m, ")"); | |
1d693bcc | 183 | } |
c1ad11fc | 184 | if (obj->stolen) |
440fd528 | 185 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
30154650 | 186 | if (obj->pin_display || obj->fault_mappable) { |
6299f992 | 187 | char s[3], *t = s; |
30154650 | 188 | if (obj->pin_display) |
6299f992 CW |
189 | *t++ = 'p'; |
190 | if (obj->fault_mappable) | |
191 | *t++ = 'f'; | |
192 | *t = '\0'; | |
193 | seq_printf(m, " (%s mappable)", s); | |
194 | } | |
b4716185 | 195 | if (obj->last_write_req != NULL) |
41c52415 | 196 | seq_printf(m, " (%s)", |
666796da | 197 | i915_gem_request_get_engine(obj->last_write_req)->name); |
d5a81ef1 DV |
198 | if (obj->frontbuffer_bits) |
199 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); | |
37811fcc CW |
200 | } |
201 | ||
273497e5 | 202 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
3ccfd19d | 203 | { |
ea0c76f8 | 204 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
3ccfd19d BW |
205 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
206 | seq_putc(m, ' '); | |
207 | } | |
208 | ||
433e12f7 | 209 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e | 210 | { |
9f25d007 | 211 | struct drm_info_node *node = m->private; |
433e12f7 BG |
212 | uintptr_t list = (uintptr_t) node->info_ent->data; |
213 | struct list_head *head; | |
2017263e | 214 | struct drm_device *dev = node->minor->dev; |
72e96d64 JL |
215 | struct drm_i915_private *dev_priv = to_i915(dev); |
216 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
ca191b13 | 217 | struct i915_vma *vma; |
c44ef60e | 218 | u64 total_obj_size, total_gtt_size; |
8f2480fb | 219 | int count, ret; |
de227ef0 CW |
220 | |
221 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
222 | if (ret) | |
223 | return ret; | |
2017263e | 224 | |
ca191b13 | 225 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
226 | switch (list) { |
227 | case ACTIVE_LIST: | |
267f0c90 | 228 | seq_puts(m, "Active:\n"); |
72e96d64 | 229 | head = &ggtt->base.active_list; |
433e12f7 BG |
230 | break; |
231 | case INACTIVE_LIST: | |
267f0c90 | 232 | seq_puts(m, "Inactive:\n"); |
72e96d64 | 233 | head = &ggtt->base.inactive_list; |
433e12f7 | 234 | break; |
433e12f7 | 235 | default: |
de227ef0 CW |
236 | mutex_unlock(&dev->struct_mutex); |
237 | return -EINVAL; | |
2017263e | 238 | } |
2017263e | 239 | |
8f2480fb | 240 | total_obj_size = total_gtt_size = count = 0; |
1c7f4bca | 241 | list_for_each_entry(vma, head, vm_link) { |
ca191b13 BW |
242 | seq_printf(m, " "); |
243 | describe_obj(m, vma->obj); | |
244 | seq_printf(m, "\n"); | |
245 | total_obj_size += vma->obj->base.size; | |
246 | total_gtt_size += vma->node.size; | |
8f2480fb | 247 | count++; |
2017263e | 248 | } |
de227ef0 | 249 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 250 | |
c44ef60e | 251 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
8f2480fb | 252 | count, total_obj_size, total_gtt_size); |
2017263e BG |
253 | return 0; |
254 | } | |
255 | ||
6d2b8885 CW |
256 | static int obj_rank_by_stolen(void *priv, |
257 | struct list_head *A, struct list_head *B) | |
258 | { | |
259 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 260 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 261 | struct drm_i915_gem_object *b = |
b25cb2f8 | 262 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 263 | |
2d05fa16 RV |
264 | if (a->stolen->start < b->stolen->start) |
265 | return -1; | |
266 | if (a->stolen->start > b->stolen->start) | |
267 | return 1; | |
268 | return 0; | |
6d2b8885 CW |
269 | } |
270 | ||
271 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
272 | { | |
9f25d007 | 273 | struct drm_info_node *node = m->private; |
6d2b8885 CW |
274 | struct drm_device *dev = node->minor->dev; |
275 | struct drm_i915_private *dev_priv = dev->dev_private; | |
276 | struct drm_i915_gem_object *obj; | |
c44ef60e | 277 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
278 | LIST_HEAD(stolen); |
279 | int count, ret; | |
280 | ||
281 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
282 | if (ret) | |
283 | return ret; | |
284 | ||
285 | total_obj_size = total_gtt_size = count = 0; | |
286 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
287 | if (obj->stolen == NULL) | |
288 | continue; | |
289 | ||
b25cb2f8 | 290 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
291 | |
292 | total_obj_size += obj->base.size; | |
ca1543be | 293 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
294 | count++; |
295 | } | |
296 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
297 | if (obj->stolen == NULL) | |
298 | continue; | |
299 | ||
b25cb2f8 | 300 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
301 | |
302 | total_obj_size += obj->base.size; | |
303 | count++; | |
304 | } | |
305 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
306 | seq_puts(m, "Stolen:\n"); | |
307 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 308 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
309 | seq_puts(m, " "); |
310 | describe_obj(m, obj); | |
311 | seq_putc(m, '\n'); | |
b25cb2f8 | 312 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
313 | } |
314 | mutex_unlock(&dev->struct_mutex); | |
315 | ||
c44ef60e | 316 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
317 | count, total_obj_size, total_gtt_size); |
318 | return 0; | |
319 | } | |
320 | ||
6299f992 CW |
321 | #define count_objects(list, member) do { \ |
322 | list_for_each_entry(obj, list, member) { \ | |
ca1543be | 323 | size += i915_gem_obj_total_ggtt_size(obj); \ |
6299f992 CW |
324 | ++count; \ |
325 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 326 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
327 | ++mappable_count; \ |
328 | } \ | |
329 | } \ | |
0206e353 | 330 | } while (0) |
6299f992 | 331 | |
2db8e9d6 | 332 | struct file_stats { |
6313c204 | 333 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
334 | unsigned long count; |
335 | u64 total, unbound; | |
336 | u64 global, shared; | |
337 | u64 active, inactive; | |
2db8e9d6 CW |
338 | }; |
339 | ||
340 | static int per_file_stats(int id, void *ptr, void *data) | |
341 | { | |
342 | struct drm_i915_gem_object *obj = ptr; | |
343 | struct file_stats *stats = data; | |
6313c204 | 344 | struct i915_vma *vma; |
2db8e9d6 CW |
345 | |
346 | stats->count++; | |
347 | stats->total += obj->base.size; | |
348 | ||
c67a17e9 CW |
349 | if (obj->base.name || obj->base.dma_buf) |
350 | stats->shared += obj->base.size; | |
351 | ||
6313c204 | 352 | if (USES_FULL_PPGTT(obj->base.dev)) { |
1c7f4bca | 353 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
6313c204 CW |
354 | struct i915_hw_ppgtt *ppgtt; |
355 | ||
356 | if (!drm_mm_node_allocated(&vma->node)) | |
357 | continue; | |
358 | ||
596c5923 | 359 | if (vma->is_ggtt) { |
6313c204 CW |
360 | stats->global += obj->base.size; |
361 | continue; | |
362 | } | |
363 | ||
364 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
4d884705 | 365 | if (ppgtt->file_priv != stats->file_priv) |
6313c204 CW |
366 | continue; |
367 | ||
41c52415 | 368 | if (obj->active) /* XXX per-vma statistic */ |
6313c204 CW |
369 | stats->active += obj->base.size; |
370 | else | |
371 | stats->inactive += obj->base.size; | |
372 | ||
373 | return 0; | |
374 | } | |
2db8e9d6 | 375 | } else { |
6313c204 CW |
376 | if (i915_gem_obj_ggtt_bound(obj)) { |
377 | stats->global += obj->base.size; | |
41c52415 | 378 | if (obj->active) |
6313c204 CW |
379 | stats->active += obj->base.size; |
380 | else | |
381 | stats->inactive += obj->base.size; | |
382 | return 0; | |
383 | } | |
2db8e9d6 CW |
384 | } |
385 | ||
6313c204 CW |
386 | if (!list_empty(&obj->global_list)) |
387 | stats->unbound += obj->base.size; | |
388 | ||
2db8e9d6 CW |
389 | return 0; |
390 | } | |
391 | ||
b0da1b79 CW |
392 | #define print_file_stats(m, name, stats) do { \ |
393 | if (stats.count) \ | |
c44ef60e | 394 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
395 | name, \ |
396 | stats.count, \ | |
397 | stats.total, \ | |
398 | stats.active, \ | |
399 | stats.inactive, \ | |
400 | stats.global, \ | |
401 | stats.shared, \ | |
402 | stats.unbound); \ | |
403 | } while (0) | |
493018dc BV |
404 | |
405 | static void print_batch_pool_stats(struct seq_file *m, | |
406 | struct drm_i915_private *dev_priv) | |
407 | { | |
408 | struct drm_i915_gem_object *obj; | |
409 | struct file_stats stats; | |
e2f80391 | 410 | struct intel_engine_cs *engine; |
b4ac5afc | 411 | int j; |
493018dc BV |
412 | |
413 | memset(&stats, 0, sizeof(stats)); | |
414 | ||
b4ac5afc | 415 | for_each_engine(engine, dev_priv) { |
e2f80391 | 416 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 | 417 | list_for_each_entry(obj, |
e2f80391 | 418 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
419 | batch_pool_link) |
420 | per_file_stats(0, obj, &stats); | |
421 | } | |
06fbca71 | 422 | } |
493018dc | 423 | |
b0da1b79 | 424 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
425 | } |
426 | ||
ca191b13 BW |
427 | #define count_vmas(list, member) do { \ |
428 | list_for_each_entry(vma, list, member) { \ | |
ca1543be | 429 | size += i915_gem_obj_total_ggtt_size(vma->obj); \ |
ca191b13 BW |
430 | ++count; \ |
431 | if (vma->obj->map_and_fenceable) { \ | |
432 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
433 | ++mappable_count; \ | |
434 | } \ | |
435 | } \ | |
436 | } while (0) | |
437 | ||
438 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 439 | { |
9f25d007 | 440 | struct drm_info_node *node = m->private; |
73aa808f | 441 | struct drm_device *dev = node->minor->dev; |
72e96d64 JL |
442 | struct drm_i915_private *dev_priv = to_i915(dev); |
443 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b7abb714 | 444 | u32 count, mappable_count, purgeable_count; |
c44ef60e | 445 | u64 size, mappable_size, purgeable_size; |
be19b10d TU |
446 | unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0; |
447 | u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0; | |
6299f992 | 448 | struct drm_i915_gem_object *obj; |
2db8e9d6 | 449 | struct drm_file *file; |
ca191b13 | 450 | struct i915_vma *vma; |
73aa808f CW |
451 | int ret; |
452 | ||
453 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
454 | if (ret) | |
455 | return ret; | |
456 | ||
6299f992 CW |
457 | seq_printf(m, "%u objects, %zu bytes\n", |
458 | dev_priv->mm.object_count, | |
459 | dev_priv->mm.object_memory); | |
460 | ||
461 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 462 | count_objects(&dev_priv->mm.bound_list, global_list); |
c44ef60e | 463 | seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n", |
6299f992 CW |
464 | count, mappable_count, size, mappable_size); |
465 | ||
466 | size = count = mappable_size = mappable_count = 0; | |
72e96d64 | 467 | count_vmas(&ggtt->base.active_list, vm_link); |
c44ef60e | 468 | seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n", |
6299f992 CW |
469 | count, mappable_count, size, mappable_size); |
470 | ||
6299f992 | 471 | size = count = mappable_size = mappable_count = 0; |
72e96d64 | 472 | count_vmas(&ggtt->base.inactive_list, vm_link); |
c44ef60e | 473 | seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n", |
6299f992 CW |
474 | count, mappable_count, size, mappable_size); |
475 | ||
b7abb714 | 476 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 477 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 478 | size += obj->base.size, ++count; |
b7abb714 CW |
479 | if (obj->madv == I915_MADV_DONTNEED) |
480 | purgeable_size += obj->base.size, ++purgeable_count; | |
be19b10d TU |
481 | if (obj->mapping) { |
482 | pin_mapped_count++; | |
483 | pin_mapped_size += obj->base.size; | |
484 | if (obj->pages_pin_count == 0) { | |
485 | pin_mapped_purgeable_count++; | |
486 | pin_mapped_purgeable_size += obj->base.size; | |
487 | } | |
488 | } | |
b7abb714 | 489 | } |
c44ef60e | 490 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 491 | |
6299f992 | 492 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 493 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 494 | if (obj->fault_mappable) { |
f343c5f6 | 495 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
496 | ++count; |
497 | } | |
30154650 | 498 | if (obj->pin_display) { |
f343c5f6 | 499 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
500 | ++mappable_count; |
501 | } | |
b7abb714 CW |
502 | if (obj->madv == I915_MADV_DONTNEED) { |
503 | purgeable_size += obj->base.size; | |
504 | ++purgeable_count; | |
505 | } | |
be19b10d TU |
506 | if (obj->mapping) { |
507 | pin_mapped_count++; | |
508 | pin_mapped_size += obj->base.size; | |
509 | if (obj->pages_pin_count == 0) { | |
510 | pin_mapped_purgeable_count++; | |
511 | pin_mapped_purgeable_size += obj->base.size; | |
512 | } | |
513 | } | |
6299f992 | 514 | } |
c44ef60e | 515 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 516 | purgeable_count, purgeable_size); |
c44ef60e | 517 | seq_printf(m, "%u pinned mappable objects, %llu bytes\n", |
6299f992 | 518 | mappable_count, mappable_size); |
c44ef60e | 519 | seq_printf(m, "%u fault mappable objects, %llu bytes\n", |
6299f992 | 520 | count, size); |
be19b10d TU |
521 | seq_printf(m, |
522 | "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n", | |
523 | pin_mapped_count, pin_mapped_purgeable_count, | |
524 | pin_mapped_size, pin_mapped_purgeable_size); | |
6299f992 | 525 | |
c44ef60e | 526 | seq_printf(m, "%llu [%llu] gtt total\n", |
72e96d64 | 527 | ggtt->base.total, ggtt->mappable_end - ggtt->base.start); |
73aa808f | 528 | |
493018dc BV |
529 | seq_putc(m, '\n'); |
530 | print_batch_pool_stats(m, dev_priv); | |
2db8e9d6 CW |
531 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
532 | struct file_stats stats; | |
3ec2f427 | 533 | struct task_struct *task; |
2db8e9d6 CW |
534 | |
535 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 536 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 537 | spin_lock(&file->table_lock); |
2db8e9d6 | 538 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 539 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
540 | /* |
541 | * Although we have a valid reference on file->pid, that does | |
542 | * not guarantee that the task_struct who called get_pid() is | |
543 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
544 | * Therefore, we need to protect this ->comm access using RCU. | |
545 | */ | |
546 | rcu_read_lock(); | |
547 | task = pid_task(file->pid, PIDTYPE_PID); | |
493018dc | 548 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 549 | rcu_read_unlock(); |
2db8e9d6 CW |
550 | } |
551 | ||
73aa808f CW |
552 | mutex_unlock(&dev->struct_mutex); |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
aee56cff | 557 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 558 | { |
9f25d007 | 559 | struct drm_info_node *node = m->private; |
08c18323 | 560 | struct drm_device *dev = node->minor->dev; |
1b50247a | 561 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
562 | struct drm_i915_private *dev_priv = dev->dev_private; |
563 | struct drm_i915_gem_object *obj; | |
c44ef60e | 564 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
565 | int count, ret; |
566 | ||
567 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
568 | if (ret) | |
569 | return ret; | |
570 | ||
571 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 572 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 573 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
574 | continue; |
575 | ||
267f0c90 | 576 | seq_puts(m, " "); |
08c18323 | 577 | describe_obj(m, obj); |
267f0c90 | 578 | seq_putc(m, '\n'); |
08c18323 | 579 | total_obj_size += obj->base.size; |
ca1543be | 580 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
581 | count++; |
582 | } | |
583 | ||
584 | mutex_unlock(&dev->struct_mutex); | |
585 | ||
c44ef60e | 586 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
587 | count, total_obj_size, total_gtt_size); |
588 | ||
589 | return 0; | |
590 | } | |
591 | ||
4e5359cd SF |
592 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
593 | { | |
9f25d007 | 594 | struct drm_info_node *node = m->private; |
4e5359cd | 595 | struct drm_device *dev = node->minor->dev; |
d6bbafa1 | 596 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd | 597 | struct intel_crtc *crtc; |
8a270ebf DV |
598 | int ret; |
599 | ||
600 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
601 | if (ret) | |
602 | return ret; | |
4e5359cd | 603 | |
d3fcc808 | 604 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
605 | const char pipe = pipe_name(crtc->pipe); |
606 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
607 | struct intel_unpin_work *work; |
608 | ||
5e2d7afc | 609 | spin_lock_irq(&dev->event_lock); |
4e5359cd SF |
610 | work = crtc->unpin_work; |
611 | if (work == NULL) { | |
9db4a9c7 | 612 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
613 | pipe, plane); |
614 | } else { | |
d6bbafa1 CW |
615 | u32 addr; |
616 | ||
e7d841ca | 617 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 618 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
619 | pipe, plane); |
620 | } else { | |
9db4a9c7 | 621 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
622 | pipe, plane); |
623 | } | |
3a8a946e | 624 | if (work->flip_queued_req) { |
666796da | 625 | struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req); |
3a8a946e | 626 | |
20e28fba | 627 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", |
e2f80391 | 628 | engine->name, |
f06cc1b9 | 629 | i915_gem_request_get_seqno(work->flip_queued_req), |
d6bbafa1 | 630 | dev_priv->next_seqno, |
c04e0f3b | 631 | engine->get_seqno(engine), |
1b5a433a | 632 | i915_gem_request_completed(work->flip_queued_req, true)); |
d6bbafa1 CW |
633 | } else |
634 | seq_printf(m, "Flip not associated with any ring\n"); | |
635 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
636 | work->flip_queued_vblank, | |
637 | work->flip_ready_vblank, | |
1e3feefd | 638 | drm_crtc_vblank_count(&crtc->base)); |
4e5359cd | 639 | if (work->enable_stall_check) |
267f0c90 | 640 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 641 | else |
267f0c90 | 642 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 643 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd | 644 | |
d6bbafa1 CW |
645 | if (INTEL_INFO(dev)->gen >= 4) |
646 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); | |
647 | else | |
648 | addr = I915_READ(DSPADDR(crtc->plane)); | |
649 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
650 | ||
4e5359cd | 651 | if (work->pending_flip_obj) { |
d6bbafa1 CW |
652 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); |
653 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
654 | } |
655 | } | |
5e2d7afc | 656 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
657 | } |
658 | ||
8a270ebf DV |
659 | mutex_unlock(&dev->struct_mutex); |
660 | ||
4e5359cd SF |
661 | return 0; |
662 | } | |
663 | ||
493018dc BV |
664 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
665 | { | |
666 | struct drm_info_node *node = m->private; | |
667 | struct drm_device *dev = node->minor->dev; | |
668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
669 | struct drm_i915_gem_object *obj; | |
e2f80391 | 670 | struct intel_engine_cs *engine; |
8d9d5744 | 671 | int total = 0; |
b4ac5afc | 672 | int ret, j; |
493018dc BV |
673 | |
674 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
675 | if (ret) | |
676 | return ret; | |
677 | ||
b4ac5afc | 678 | for_each_engine(engine, dev_priv) { |
e2f80391 | 679 | for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { |
8d9d5744 CW |
680 | int count; |
681 | ||
682 | count = 0; | |
683 | list_for_each_entry(obj, | |
e2f80391 | 684 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
685 | batch_pool_link) |
686 | count++; | |
687 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
e2f80391 | 688 | engine->name, j, count); |
8d9d5744 CW |
689 | |
690 | list_for_each_entry(obj, | |
e2f80391 | 691 | &engine->batch_pool.cache_list[j], |
8d9d5744 CW |
692 | batch_pool_link) { |
693 | seq_puts(m, " "); | |
694 | describe_obj(m, obj); | |
695 | seq_putc(m, '\n'); | |
696 | } | |
697 | ||
698 | total += count; | |
06fbca71 | 699 | } |
493018dc BV |
700 | } |
701 | ||
8d9d5744 | 702 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
703 | |
704 | mutex_unlock(&dev->struct_mutex); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
2017263e BG |
709 | static int i915_gem_request_info(struct seq_file *m, void *data) |
710 | { | |
9f25d007 | 711 | struct drm_info_node *node = m->private; |
2017263e | 712 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 713 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 714 | struct intel_engine_cs *engine; |
eed29a5b | 715 | struct drm_i915_gem_request *req; |
b4ac5afc | 716 | int ret, any; |
de227ef0 CW |
717 | |
718 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
719 | if (ret) | |
720 | return ret; | |
2017263e | 721 | |
2d1070b2 | 722 | any = 0; |
b4ac5afc | 723 | for_each_engine(engine, dev_priv) { |
2d1070b2 CW |
724 | int count; |
725 | ||
726 | count = 0; | |
e2f80391 | 727 | list_for_each_entry(req, &engine->request_list, list) |
2d1070b2 CW |
728 | count++; |
729 | if (count == 0) | |
a2c7f6fd CW |
730 | continue; |
731 | ||
e2f80391 TU |
732 | seq_printf(m, "%s requests: %d\n", engine->name, count); |
733 | list_for_each_entry(req, &engine->request_list, list) { | |
2d1070b2 CW |
734 | struct task_struct *task; |
735 | ||
736 | rcu_read_lock(); | |
737 | task = NULL; | |
eed29a5b DV |
738 | if (req->pid) |
739 | task = pid_task(req->pid, PIDTYPE_PID); | |
2d1070b2 | 740 | seq_printf(m, " %x @ %d: %s [%d]\n", |
eed29a5b DV |
741 | req->seqno, |
742 | (int) (jiffies - req->emitted_jiffies), | |
2d1070b2 CW |
743 | task ? task->comm : "<unknown>", |
744 | task ? task->pid : -1); | |
745 | rcu_read_unlock(); | |
c2c347a9 | 746 | } |
2d1070b2 CW |
747 | |
748 | any++; | |
2017263e | 749 | } |
de227ef0 CW |
750 | mutex_unlock(&dev->struct_mutex); |
751 | ||
2d1070b2 | 752 | if (any == 0) |
267f0c90 | 753 | seq_puts(m, "No requests\n"); |
c2c347a9 | 754 | |
2017263e BG |
755 | return 0; |
756 | } | |
757 | ||
b2223497 | 758 | static void i915_ring_seqno_info(struct seq_file *m, |
0bc40be8 | 759 | struct intel_engine_cs *engine) |
b2223497 | 760 | { |
12471ba8 CW |
761 | seq_printf(m, "Current sequence (%s): %x\n", |
762 | engine->name, engine->get_seqno(engine)); | |
763 | seq_printf(m, "Current user interrupts (%s): %x\n", | |
764 | engine->name, READ_ONCE(engine->user_interrupts)); | |
b2223497 CW |
765 | } |
766 | ||
2017263e BG |
767 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
768 | { | |
9f25d007 | 769 | struct drm_info_node *node = m->private; |
2017263e | 770 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 771 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 772 | struct intel_engine_cs *engine; |
b4ac5afc | 773 | int ret; |
de227ef0 CW |
774 | |
775 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
776 | if (ret) | |
777 | return ret; | |
c8c8fb33 | 778 | intel_runtime_pm_get(dev_priv); |
2017263e | 779 | |
b4ac5afc | 780 | for_each_engine(engine, dev_priv) |
e2f80391 | 781 | i915_ring_seqno_info(m, engine); |
de227ef0 | 782 | |
c8c8fb33 | 783 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
784 | mutex_unlock(&dev->struct_mutex); |
785 | ||
2017263e BG |
786 | return 0; |
787 | } | |
788 | ||
789 | ||
790 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
791 | { | |
9f25d007 | 792 | struct drm_info_node *node = m->private; |
2017263e | 793 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 794 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 795 | struct intel_engine_cs *engine; |
9db4a9c7 | 796 | int ret, i, pipe; |
de227ef0 CW |
797 | |
798 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
799 | if (ret) | |
800 | return ret; | |
c8c8fb33 | 801 | intel_runtime_pm_get(dev_priv); |
2017263e | 802 | |
74e1ca8c | 803 | if (IS_CHERRYVIEW(dev)) { |
74e1ca8c VS |
804 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
805 | I915_READ(GEN8_MASTER_IRQ)); | |
806 | ||
807 | seq_printf(m, "Display IER:\t%08x\n", | |
808 | I915_READ(VLV_IER)); | |
809 | seq_printf(m, "Display IIR:\t%08x\n", | |
810 | I915_READ(VLV_IIR)); | |
811 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
812 | I915_READ(VLV_IIR_RW)); | |
813 | seq_printf(m, "Display IMR:\t%08x\n", | |
814 | I915_READ(VLV_IMR)); | |
055e393f | 815 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
816 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
817 | pipe_name(pipe), | |
818 | I915_READ(PIPESTAT(pipe))); | |
819 | ||
820 | seq_printf(m, "Port hotplug:\t%08x\n", | |
821 | I915_READ(PORT_HOTPLUG_EN)); | |
822 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
823 | I915_READ(VLV_DPFLIPSTAT)); | |
824 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
825 | I915_READ(DPINVGTT)); | |
826 | ||
827 | for (i = 0; i < 4; i++) { | |
828 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
829 | i, I915_READ(GEN8_GT_IMR(i))); | |
830 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
831 | i, I915_READ(GEN8_GT_IIR(i))); | |
832 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
833 | i, I915_READ(GEN8_GT_IER(i))); | |
834 | } | |
835 | ||
836 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
837 | I915_READ(GEN8_PCU_IMR)); | |
838 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
839 | I915_READ(GEN8_PCU_IIR)); | |
840 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
841 | I915_READ(GEN8_PCU_IER)); | |
842 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
843 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
844 | I915_READ(GEN8_MASTER_IRQ)); | |
845 | ||
846 | for (i = 0; i < 4; i++) { | |
847 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
848 | i, I915_READ(GEN8_GT_IMR(i))); | |
849 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
850 | i, I915_READ(GEN8_GT_IIR(i))); | |
851 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
852 | i, I915_READ(GEN8_GT_IER(i))); | |
853 | } | |
854 | ||
055e393f | 855 | for_each_pipe(dev_priv, pipe) { |
e129649b ID |
856 | enum intel_display_power_domain power_domain; |
857 | ||
858 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
859 | if (!intel_display_power_get_if_enabled(dev_priv, | |
860 | power_domain)) { | |
22c59960 PZ |
861 | seq_printf(m, "Pipe %c power disabled\n", |
862 | pipe_name(pipe)); | |
863 | continue; | |
864 | } | |
a123f157 | 865 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
866 | pipe_name(pipe), |
867 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 868 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
869 | pipe_name(pipe), |
870 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 871 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
872 | pipe_name(pipe), |
873 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
e129649b ID |
874 | |
875 | intel_display_power_put(dev_priv, power_domain); | |
a123f157 BW |
876 | } |
877 | ||
878 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
879 | I915_READ(GEN8_DE_PORT_IMR)); | |
880 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
881 | I915_READ(GEN8_DE_PORT_IIR)); | |
882 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
883 | I915_READ(GEN8_DE_PORT_IER)); | |
884 | ||
885 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
886 | I915_READ(GEN8_DE_MISC_IMR)); | |
887 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
888 | I915_READ(GEN8_DE_MISC_IIR)); | |
889 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
890 | I915_READ(GEN8_DE_MISC_IER)); | |
891 | ||
892 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
893 | I915_READ(GEN8_PCU_IMR)); | |
894 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
895 | I915_READ(GEN8_PCU_IIR)); | |
896 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
897 | I915_READ(GEN8_PCU_IER)); | |
898 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
899 | seq_printf(m, "Display IER:\t%08x\n", |
900 | I915_READ(VLV_IER)); | |
901 | seq_printf(m, "Display IIR:\t%08x\n", | |
902 | I915_READ(VLV_IIR)); | |
903 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
904 | I915_READ(VLV_IIR_RW)); | |
905 | seq_printf(m, "Display IMR:\t%08x\n", | |
906 | I915_READ(VLV_IMR)); | |
055e393f | 907 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
908 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
909 | pipe_name(pipe), | |
910 | I915_READ(PIPESTAT(pipe))); | |
911 | ||
912 | seq_printf(m, "Master IER:\t%08x\n", | |
913 | I915_READ(VLV_MASTER_IER)); | |
914 | ||
915 | seq_printf(m, "Render IER:\t%08x\n", | |
916 | I915_READ(GTIER)); | |
917 | seq_printf(m, "Render IIR:\t%08x\n", | |
918 | I915_READ(GTIIR)); | |
919 | seq_printf(m, "Render IMR:\t%08x\n", | |
920 | I915_READ(GTIMR)); | |
921 | ||
922 | seq_printf(m, "PM IER:\t\t%08x\n", | |
923 | I915_READ(GEN6_PMIER)); | |
924 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
925 | I915_READ(GEN6_PMIIR)); | |
926 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
927 | I915_READ(GEN6_PMIMR)); | |
928 | ||
929 | seq_printf(m, "Port hotplug:\t%08x\n", | |
930 | I915_READ(PORT_HOTPLUG_EN)); | |
931 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
932 | I915_READ(VLV_DPFLIPSTAT)); | |
933 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
934 | I915_READ(DPINVGTT)); | |
935 | ||
936 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
937 | seq_printf(m, "Interrupt enable: %08x\n", |
938 | I915_READ(IER)); | |
939 | seq_printf(m, "Interrupt identity: %08x\n", | |
940 | I915_READ(IIR)); | |
941 | seq_printf(m, "Interrupt mask: %08x\n", | |
942 | I915_READ(IMR)); | |
055e393f | 943 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
944 | seq_printf(m, "Pipe %c stat: %08x\n", |
945 | pipe_name(pipe), | |
946 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
947 | } else { |
948 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
949 | I915_READ(DEIER)); | |
950 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
951 | I915_READ(DEIIR)); | |
952 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
953 | I915_READ(DEIMR)); | |
954 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
955 | I915_READ(SDEIER)); | |
956 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
957 | I915_READ(SDEIIR)); | |
958 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
959 | I915_READ(SDEIMR)); | |
960 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
961 | I915_READ(GTIER)); | |
962 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
963 | I915_READ(GTIIR)); | |
964 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
965 | I915_READ(GTIMR)); | |
966 | } | |
b4ac5afc | 967 | for_each_engine(engine, dev_priv) { |
a123f157 | 968 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
969 | seq_printf(m, |
970 | "Graphics Interrupt mask (%s): %08x\n", | |
e2f80391 | 971 | engine->name, I915_READ_IMR(engine)); |
9862e600 | 972 | } |
e2f80391 | 973 | i915_ring_seqno_info(m, engine); |
9862e600 | 974 | } |
c8c8fb33 | 975 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
976 | mutex_unlock(&dev->struct_mutex); |
977 | ||
2017263e BG |
978 | return 0; |
979 | } | |
980 | ||
a6172a80 CW |
981 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
982 | { | |
9f25d007 | 983 | struct drm_info_node *node = m->private; |
a6172a80 | 984 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 985 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
986 | int i, ret; |
987 | ||
988 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
989 | if (ret) | |
990 | return ret; | |
a6172a80 | 991 | |
a6172a80 CW |
992 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
993 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 994 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 995 | |
6c085a72 CW |
996 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
997 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 998 | if (obj == NULL) |
267f0c90 | 999 | seq_puts(m, "unused"); |
c2c347a9 | 1000 | else |
05394f39 | 1001 | describe_obj(m, obj); |
267f0c90 | 1002 | seq_putc(m, '\n'); |
a6172a80 CW |
1003 | } |
1004 | ||
05394f39 | 1005 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
1006 | return 0; |
1007 | } | |
1008 | ||
2017263e BG |
1009 | static int i915_hws_info(struct seq_file *m, void *data) |
1010 | { | |
9f25d007 | 1011 | struct drm_info_node *node = m->private; |
2017263e | 1012 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1013 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 1014 | struct intel_engine_cs *engine; |
1a240d4d | 1015 | const u32 *hws; |
4066c0ae CW |
1016 | int i; |
1017 | ||
4a570db5 | 1018 | engine = &dev_priv->engine[(uintptr_t)node->info_ent->data]; |
e2f80391 | 1019 | hws = engine->status_page.page_addr; |
2017263e BG |
1020 | if (hws == NULL) |
1021 | return 0; | |
1022 | ||
1023 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
1024 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
1025 | i * 4, | |
1026 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
1027 | } | |
1028 | return 0; | |
1029 | } | |
1030 | ||
d5442303 DV |
1031 | static ssize_t |
1032 | i915_error_state_write(struct file *filp, | |
1033 | const char __user *ubuf, | |
1034 | size_t cnt, | |
1035 | loff_t *ppos) | |
1036 | { | |
edc3d884 | 1037 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 1038 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 1039 | int ret; |
d5442303 DV |
1040 | |
1041 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
1042 | ||
22bcfc6a DV |
1043 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1044 | if (ret) | |
1045 | return ret; | |
1046 | ||
d5442303 DV |
1047 | i915_destroy_error_state(dev); |
1048 | mutex_unlock(&dev->struct_mutex); | |
1049 | ||
1050 | return cnt; | |
1051 | } | |
1052 | ||
1053 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
1054 | { | |
1055 | struct drm_device *dev = inode->i_private; | |
d5442303 | 1056 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
1057 | |
1058 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
1059 | if (!error_priv) | |
1060 | return -ENOMEM; | |
1061 | ||
1062 | error_priv->dev = dev; | |
1063 | ||
95d5bfb3 | 1064 | i915_error_state_get(dev, error_priv); |
d5442303 | 1065 | |
edc3d884 MK |
1066 | file->private_data = error_priv; |
1067 | ||
1068 | return 0; | |
d5442303 DV |
1069 | } |
1070 | ||
1071 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
1072 | { | |
edc3d884 | 1073 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 1074 | |
95d5bfb3 | 1075 | i915_error_state_put(error_priv); |
d5442303 DV |
1076 | kfree(error_priv); |
1077 | ||
edc3d884 MK |
1078 | return 0; |
1079 | } | |
1080 | ||
4dc955f7 MK |
1081 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1082 | size_t count, loff_t *pos) | |
1083 | { | |
1084 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1085 | struct drm_i915_error_state_buf error_str; | |
1086 | loff_t tmp_pos = 0; | |
1087 | ssize_t ret_count = 0; | |
1088 | int ret; | |
1089 | ||
0a4cd7c8 | 1090 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
4dc955f7 MK |
1091 | if (ret) |
1092 | return ret; | |
edc3d884 | 1093 | |
fc16b48b | 1094 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1095 | if (ret) |
1096 | goto out; | |
1097 | ||
edc3d884 MK |
1098 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1099 | error_str.buf, | |
1100 | error_str.bytes); | |
1101 | ||
1102 | if (ret_count < 0) | |
1103 | ret = ret_count; | |
1104 | else | |
1105 | *pos = error_str.start + ret_count; | |
1106 | out: | |
4dc955f7 | 1107 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1108 | return ret ?: ret_count; |
d5442303 DV |
1109 | } |
1110 | ||
1111 | static const struct file_operations i915_error_state_fops = { | |
1112 | .owner = THIS_MODULE, | |
1113 | .open = i915_error_state_open, | |
edc3d884 | 1114 | .read = i915_error_state_read, |
d5442303 DV |
1115 | .write = i915_error_state_write, |
1116 | .llseek = default_llseek, | |
1117 | .release = i915_error_state_release, | |
1118 | }; | |
1119 | ||
647416f9 KC |
1120 | static int |
1121 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1122 | { |
647416f9 | 1123 | struct drm_device *dev = data; |
e277a1f8 | 1124 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
1125 | int ret; |
1126 | ||
1127 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1128 | if (ret) | |
1129 | return ret; | |
1130 | ||
647416f9 | 1131 | *val = dev_priv->next_seqno; |
40633219 MK |
1132 | mutex_unlock(&dev->struct_mutex); |
1133 | ||
647416f9 | 1134 | return 0; |
40633219 MK |
1135 | } |
1136 | ||
647416f9 KC |
1137 | static int |
1138 | i915_next_seqno_set(void *data, u64 val) | |
1139 | { | |
1140 | struct drm_device *dev = data; | |
40633219 MK |
1141 | int ret; |
1142 | ||
40633219 MK |
1143 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1144 | if (ret) | |
1145 | return ret; | |
1146 | ||
e94fbaa8 | 1147 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1148 | mutex_unlock(&dev->struct_mutex); |
1149 | ||
647416f9 | 1150 | return ret; |
40633219 MK |
1151 | } |
1152 | ||
647416f9 KC |
1153 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1154 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1155 | "0x%llx\n"); |
40633219 | 1156 | |
adb4bd12 | 1157 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1158 | { |
9f25d007 | 1159 | struct drm_info_node *node = m->private; |
f97108d1 | 1160 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1161 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
1162 | int ret = 0; |
1163 | ||
1164 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1165 | |
5c9669ce TR |
1166 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1167 | ||
3b8d8d91 JB |
1168 | if (IS_GEN5(dev)) { |
1169 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1170 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1171 | ||
1172 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1173 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1174 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1175 | MEMSTAT_VID_SHIFT); | |
1176 | seq_printf(m, "Current P-state: %d\n", | |
1177 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
666a4537 WB |
1178 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
1179 | u32 freq_sts; | |
1180 | ||
1181 | mutex_lock(&dev_priv->rps.hw_lock); | |
1182 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1183 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1184 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1185 | ||
1186 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1187 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1188 | ||
1189 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1190 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1191 | ||
1192 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1193 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1194 | ||
1195 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1196 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1197 | ||
1198 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1199 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1200 | ||
1201 | seq_printf(m, | |
1202 | "efficient (RPe) frequency: %d MHz\n", | |
1203 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1204 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1205 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
35040562 BP |
1206 | u32 rp_state_limits; |
1207 | u32 gt_perf_status; | |
1208 | u32 rp_state_cap; | |
0d8f9491 | 1209 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1210 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1211 | u32 rpupei, rpcurup, rpprevup; |
1212 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1213 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1214 | int max_freq; |
1215 | ||
35040562 BP |
1216 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
1217 | if (IS_BROXTON(dev)) { | |
1218 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); | |
1219 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1220 | } else { | |
1221 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1222 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1223 | } | |
1224 | ||
3b8d8d91 | 1225 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1226 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1227 | if (ret) | |
c8c8fb33 | 1228 | goto out; |
d1ebd816 | 1229 | |
59bad947 | 1230 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1231 | |
8e8c06cd | 1232 | reqf = I915_READ(GEN6_RPNSWREQ); |
60260a5b AG |
1233 | if (IS_GEN9(dev)) |
1234 | reqf >>= 23; | |
1235 | else { | |
1236 | reqf &= ~GEN6_TURBO_DISABLE; | |
1237 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
1238 | reqf >>= 24; | |
1239 | else | |
1240 | reqf >>= 25; | |
1241 | } | |
7c59a9c1 | 1242 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1243 | |
0d8f9491 CW |
1244 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1245 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1246 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1247 | ||
ccab5c82 | 1248 | rpstat = I915_READ(GEN6_RPSTAT1); |
d6cda9c7 AG |
1249 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; |
1250 | rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; | |
1251 | rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; | |
1252 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; | |
1253 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; | |
1254 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; | |
60260a5b AG |
1255 | if (IS_GEN9(dev)) |
1256 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
1257 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
f82855d3 BW |
1258 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1259 | else | |
1260 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1261 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1262 | |
59bad947 | 1263 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1264 | mutex_unlock(&dev->struct_mutex); |
1265 | ||
9dd3c605 PZ |
1266 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1267 | pm_ier = I915_READ(GEN6_PMIER); | |
1268 | pm_imr = I915_READ(GEN6_PMIMR); | |
1269 | pm_isr = I915_READ(GEN6_PMISR); | |
1270 | pm_iir = I915_READ(GEN6_PMIIR); | |
1271 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1272 | } else { | |
1273 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1274 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1275 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1276 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1277 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1278 | } | |
0d8f9491 | 1279 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1280 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
3b8d8d91 | 1281 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1282 | seq_printf(m, "Render p-state ratio: %d\n", |
60260a5b | 1283 | (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1284 | seq_printf(m, "Render p-state VID: %d\n", |
1285 | gt_perf_status & 0xff); | |
1286 | seq_printf(m, "Render p-state limit: %d\n", | |
1287 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1288 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1289 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1290 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1291 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1292 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1293 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
d6cda9c7 AG |
1294 | seq_printf(m, "RP CUR UP EI: %d (%dus)\n", |
1295 | rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); | |
1296 | seq_printf(m, "RP CUR UP: %d (%dus)\n", | |
1297 | rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); | |
1298 | seq_printf(m, "RP PREV UP: %d (%dus)\n", | |
1299 | rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); | |
d86ed34a CW |
1300 | seq_printf(m, "Up threshold: %d%%\n", |
1301 | dev_priv->rps.up_threshold); | |
1302 | ||
d6cda9c7 AG |
1303 | seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", |
1304 | rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); | |
1305 | seq_printf(m, "RP CUR DOWN: %d (%dus)\n", | |
1306 | rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); | |
1307 | seq_printf(m, "RP PREV DOWN: %d (%dus)\n", | |
1308 | rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); | |
d86ed34a CW |
1309 | seq_printf(m, "Down threshold: %d%%\n", |
1310 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1311 | |
35040562 BP |
1312 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : |
1313 | rp_state_cap >> 16) & 0xff; | |
ef11bdb3 RV |
1314 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1315 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1316 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1317 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1318 | |
1319 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
ef11bdb3 RV |
1320 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1321 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1322 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1323 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1324 | |
35040562 BP |
1325 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : |
1326 | rp_state_cap >> 0) & 0xff; | |
ef11bdb3 RV |
1327 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1328 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1329 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1330 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1331 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1332 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1333 | |
d86ed34a CW |
1334 | seq_printf(m, "Current freq: %d MHz\n", |
1335 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1336 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1337 | seq_printf(m, "Idle freq: %d MHz\n", |
1338 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1339 | seq_printf(m, "Min freq: %d MHz\n", |
1340 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1341 | seq_printf(m, "Max freq: %d MHz\n", | |
1342 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1343 | seq_printf(m, | |
1344 | "efficient (RPe) frequency: %d MHz\n", | |
1345 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1346 | } else { |
267f0c90 | 1347 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1348 | } |
f97108d1 | 1349 | |
1170f28c MK |
1350 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1351 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1352 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1353 | ||
c8c8fb33 PZ |
1354 | out: |
1355 | intel_runtime_pm_put(dev_priv); | |
1356 | return ret; | |
f97108d1 JB |
1357 | } |
1358 | ||
f654449a CW |
1359 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1360 | { | |
1361 | struct drm_info_node *node = m->private; | |
ebbc7546 MK |
1362 | struct drm_device *dev = node->minor->dev; |
1363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 1364 | struct intel_engine_cs *engine; |
666796da TU |
1365 | u64 acthd[I915_NUM_ENGINES]; |
1366 | u32 seqno[I915_NUM_ENGINES]; | |
61642ff0 | 1367 | u32 instdone[I915_NUM_INSTDONE_REG]; |
c3232b18 DG |
1368 | enum intel_engine_id id; |
1369 | int j; | |
f654449a CW |
1370 | |
1371 | if (!i915.enable_hangcheck) { | |
1372 | seq_printf(m, "Hangcheck disabled\n"); | |
1373 | return 0; | |
1374 | } | |
1375 | ||
ebbc7546 MK |
1376 | intel_runtime_pm_get(dev_priv); |
1377 | ||
c3232b18 | 1378 | for_each_engine_id(engine, dev_priv, id) { |
c3232b18 | 1379 | acthd[id] = intel_ring_get_active_head(engine); |
c04e0f3b | 1380 | seqno[id] = engine->get_seqno(engine); |
ebbc7546 MK |
1381 | } |
1382 | ||
61642ff0 MK |
1383 | i915_get_extra_instdone(dev, instdone); |
1384 | ||
ebbc7546 MK |
1385 | intel_runtime_pm_put(dev_priv); |
1386 | ||
f654449a CW |
1387 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1388 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1389 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1390 | jiffies)); | |
1391 | } else | |
1392 | seq_printf(m, "Hangcheck inactive\n"); | |
1393 | ||
c3232b18 | 1394 | for_each_engine_id(engine, dev_priv, id) { |
e2f80391 | 1395 | seq_printf(m, "%s:\n", engine->name); |
14fd0d6d CW |
1396 | seq_printf(m, "\tseqno = %x [current %x, last %x]\n", |
1397 | engine->hangcheck.seqno, | |
1398 | seqno[id], | |
1399 | engine->last_submitted_seqno); | |
12471ba8 CW |
1400 | seq_printf(m, "\tuser interrupts = %x [current %x]\n", |
1401 | engine->hangcheck.user_interrupts, | |
1402 | READ_ONCE(engine->user_interrupts)); | |
f654449a | 1403 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
e2f80391 | 1404 | (long long)engine->hangcheck.acthd, |
c3232b18 | 1405 | (long long)acthd[id]); |
e2f80391 TU |
1406 | seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); |
1407 | seq_printf(m, "\taction = %d\n", engine->hangcheck.action); | |
61642ff0 | 1408 | |
e2f80391 | 1409 | if (engine->id == RCS) { |
61642ff0 MK |
1410 | seq_puts(m, "\tinstdone read ="); |
1411 | ||
1412 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1413 | seq_printf(m, " 0x%08x", instdone[j]); | |
1414 | ||
1415 | seq_puts(m, "\n\tinstdone accu ="); | |
1416 | ||
1417 | for (j = 0; j < I915_NUM_INSTDONE_REG; j++) | |
1418 | seq_printf(m, " 0x%08x", | |
e2f80391 | 1419 | engine->hangcheck.instdone[j]); |
61642ff0 MK |
1420 | |
1421 | seq_puts(m, "\n"); | |
1422 | } | |
f654449a CW |
1423 | } |
1424 | ||
1425 | return 0; | |
1426 | } | |
1427 | ||
4d85529d | 1428 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1429 | { |
9f25d007 | 1430 | struct drm_info_node *node = m->private; |
f97108d1 | 1431 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1432 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1433 | u32 rgvmodectl, rstdbyctl; |
1434 | u16 crstandvid; | |
1435 | int ret; | |
1436 | ||
1437 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1438 | if (ret) | |
1439 | return ret; | |
c8c8fb33 | 1440 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1441 | |
1442 | rgvmodectl = I915_READ(MEMMODECTL); | |
1443 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1444 | crstandvid = I915_READ16(CRSTANDVID); | |
1445 | ||
c8c8fb33 | 1446 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1447 | mutex_unlock(&dev->struct_mutex); |
f97108d1 | 1448 | |
742f491d | 1449 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1450 | seq_printf(m, "Boost freq: %d\n", |
1451 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1452 | MEMMODE_BOOST_FREQ_SHIFT); | |
1453 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1454 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1455 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1456 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1457 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1458 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1459 | seq_printf(m, "Starting frequency: P%d\n", |
1460 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1461 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1462 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1463 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1464 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1465 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1466 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1467 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1468 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1469 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1470 | case RSX_STATUS_ON: | |
267f0c90 | 1471 | seq_puts(m, "on\n"); |
88271da3 JB |
1472 | break; |
1473 | case RSX_STATUS_RC1: | |
267f0c90 | 1474 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1475 | break; |
1476 | case RSX_STATUS_RC1E: | |
267f0c90 | 1477 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1478 | break; |
1479 | case RSX_STATUS_RS1: | |
267f0c90 | 1480 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1481 | break; |
1482 | case RSX_STATUS_RS2: | |
267f0c90 | 1483 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1484 | break; |
1485 | case RSX_STATUS_RS3: | |
267f0c90 | 1486 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1487 | break; |
1488 | default: | |
267f0c90 | 1489 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1490 | break; |
1491 | } | |
f97108d1 JB |
1492 | |
1493 | return 0; | |
1494 | } | |
1495 | ||
f65367b5 | 1496 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1497 | { |
b2cff0db CW |
1498 | struct drm_info_node *node = m->private; |
1499 | struct drm_device *dev = node->minor->dev; | |
1500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1501 | struct intel_uncore_forcewake_domain *fw_domain; | |
b2cff0db CW |
1502 | |
1503 | spin_lock_irq(&dev_priv->uncore.lock); | |
33c582c1 | 1504 | for_each_fw_domain(fw_domain, dev_priv) { |
b2cff0db | 1505 | seq_printf(m, "%s.wake_count = %u\n", |
33c582c1 | 1506 | intel_uncore_forcewake_domain_to_str(fw_domain->id), |
b2cff0db CW |
1507 | fw_domain->wake_count); |
1508 | } | |
1509 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1510 | |
b2cff0db CW |
1511 | return 0; |
1512 | } | |
1513 | ||
1514 | static int vlv_drpc_info(struct seq_file *m) | |
1515 | { | |
9f25d007 | 1516 | struct drm_info_node *node = m->private; |
669ab5aa D |
1517 | struct drm_device *dev = node->minor->dev; |
1518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6b312cd3 | 1519 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1520 | |
d46c0517 ID |
1521 | intel_runtime_pm_get(dev_priv); |
1522 | ||
6b312cd3 | 1523 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1524 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1525 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1526 | ||
d46c0517 ID |
1527 | intel_runtime_pm_put(dev_priv); |
1528 | ||
669ab5aa D |
1529 | seq_printf(m, "Video Turbo Mode: %s\n", |
1530 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1531 | seq_printf(m, "Turbo enabled: %s\n", | |
1532 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1533 | seq_printf(m, "HW control enabled: %s\n", | |
1534 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1535 | seq_printf(m, "SW control enabled: %s\n", | |
1536 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1537 | GEN6_RP_MEDIA_SW_MODE)); | |
1538 | seq_printf(m, "RC6 Enabled: %s\n", | |
1539 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1540 | GEN6_RC_CTL_EI_MODE(1)))); | |
1541 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1542 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1543 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1544 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1545 | |
9cc19be5 ID |
1546 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1547 | I915_READ(VLV_GT_RENDER_RC6)); | |
1548 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1549 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1550 | ||
f65367b5 | 1551 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1552 | } |
1553 | ||
4d85529d BW |
1554 | static int gen6_drpc_info(struct seq_file *m) |
1555 | { | |
9f25d007 | 1556 | struct drm_info_node *node = m->private; |
4d85529d BW |
1557 | struct drm_device *dev = node->minor->dev; |
1558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1559 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1560 | unsigned forcewake_count; |
aee56cff | 1561 | int count = 0, ret; |
4d85529d BW |
1562 | |
1563 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1564 | if (ret) | |
1565 | return ret; | |
c8c8fb33 | 1566 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1567 | |
907b28c5 | 1568 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1569 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1570 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1571 | |
1572 | if (forcewake_count) { | |
267f0c90 DL |
1573 | seq_puts(m, "RC information inaccurate because somebody " |
1574 | "holds a forcewake reference \n"); | |
4d85529d BW |
1575 | } else { |
1576 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1577 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1578 | udelay(10); | |
1579 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1580 | } | |
1581 | ||
75aa3f63 | 1582 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1583 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1584 | |
1585 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1586 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1587 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1588 | mutex_lock(&dev_priv->rps.hw_lock); |
1589 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1590 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1591 | |
c8c8fb33 PZ |
1592 | intel_runtime_pm_put(dev_priv); |
1593 | ||
4d85529d BW |
1594 | seq_printf(m, "Video Turbo Mode: %s\n", |
1595 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1596 | seq_printf(m, "HW control enabled: %s\n", | |
1597 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1598 | seq_printf(m, "SW control enabled: %s\n", | |
1599 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1600 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1601 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1602 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1603 | seq_printf(m, "RC6 Enabled: %s\n", | |
1604 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1605 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1606 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1607 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1608 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1609 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1610 | switch (gt_core_status & GEN6_RCn_MASK) { |
1611 | case GEN6_RC0: | |
1612 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1613 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1614 | else |
267f0c90 | 1615 | seq_puts(m, "on\n"); |
4d85529d BW |
1616 | break; |
1617 | case GEN6_RC3: | |
267f0c90 | 1618 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1619 | break; |
1620 | case GEN6_RC6: | |
267f0c90 | 1621 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1622 | break; |
1623 | case GEN6_RC7: | |
267f0c90 | 1624 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1625 | break; |
1626 | default: | |
267f0c90 | 1627 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1628 | break; |
1629 | } | |
1630 | ||
1631 | seq_printf(m, "Core Power Down: %s\n", | |
1632 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1633 | |
1634 | /* Not exactly sure what this is */ | |
1635 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1636 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1637 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1638 | I915_READ(GEN6_GT_GFX_RC6)); | |
1639 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1640 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1641 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1642 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1643 | ||
ecd8faea BW |
1644 | seq_printf(m, "RC6 voltage: %dmV\n", |
1645 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1646 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1647 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1648 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1649 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1650 | return 0; |
1651 | } | |
1652 | ||
1653 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1654 | { | |
9f25d007 | 1655 | struct drm_info_node *node = m->private; |
4d85529d BW |
1656 | struct drm_device *dev = node->minor->dev; |
1657 | ||
666a4537 | 1658 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
669ab5aa | 1659 | return vlv_drpc_info(m); |
ac66cf4b | 1660 | else if (INTEL_INFO(dev)->gen >= 6) |
4d85529d BW |
1661 | return gen6_drpc_info(m); |
1662 | else | |
1663 | return ironlake_drpc_info(m); | |
1664 | } | |
1665 | ||
9a851789 DV |
1666 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1667 | { | |
1668 | struct drm_info_node *node = m->private; | |
1669 | struct drm_device *dev = node->minor->dev; | |
1670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1671 | ||
1672 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1673 | dev_priv->fb_tracking.busy_bits); | |
1674 | ||
1675 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1676 | dev_priv->fb_tracking.flip_bits); | |
1677 | ||
1678 | return 0; | |
1679 | } | |
1680 | ||
b5e50c3f JB |
1681 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1682 | { | |
9f25d007 | 1683 | struct drm_info_node *node = m->private; |
b5e50c3f | 1684 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1685 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1686 | |
3a77c4c4 | 1687 | if (!HAS_FBC(dev)) { |
267f0c90 | 1688 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1689 | return 0; |
1690 | } | |
1691 | ||
36623ef8 | 1692 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1693 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1694 | |
0e631adc | 1695 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1696 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1697 | else |
1698 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1699 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1700 | |
31b9df10 PZ |
1701 | if (INTEL_INFO(dev_priv)->gen >= 7) |
1702 | seq_printf(m, "Compressing: %s\n", | |
1703 | yesno(I915_READ(FBC_STATUS2) & | |
1704 | FBC_COMPRESSION_MASK)); | |
1705 | ||
25ad93fd | 1706 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1707 | intel_runtime_pm_put(dev_priv); |
1708 | ||
b5e50c3f JB |
1709 | return 0; |
1710 | } | |
1711 | ||
da46f936 RV |
1712 | static int i915_fbc_fc_get(void *data, u64 *val) |
1713 | { | |
1714 | struct drm_device *dev = data; | |
1715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1716 | ||
1717 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1718 | return -ENODEV; | |
1719 | ||
da46f936 | 1720 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1721 | |
1722 | return 0; | |
1723 | } | |
1724 | ||
1725 | static int i915_fbc_fc_set(void *data, u64 val) | |
1726 | { | |
1727 | struct drm_device *dev = data; | |
1728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729 | u32 reg; | |
1730 | ||
1731 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1732 | return -ENODEV; | |
1733 | ||
25ad93fd | 1734 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1735 | |
1736 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1737 | dev_priv->fbc.false_color = val; | |
1738 | ||
1739 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1740 | (reg | FBC_CTL_FALSE_COLOR) : | |
1741 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1742 | ||
25ad93fd | 1743 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1744 | return 0; |
1745 | } | |
1746 | ||
1747 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1748 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1749 | "%llu\n"); | |
1750 | ||
92d44621 PZ |
1751 | static int i915_ips_status(struct seq_file *m, void *unused) |
1752 | { | |
9f25d007 | 1753 | struct drm_info_node *node = m->private; |
92d44621 PZ |
1754 | struct drm_device *dev = node->minor->dev; |
1755 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1756 | ||
f5adf94e | 1757 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1758 | seq_puts(m, "not supported\n"); |
1759 | return 0; | |
1760 | } | |
1761 | ||
36623ef8 PZ |
1762 | intel_runtime_pm_get(dev_priv); |
1763 | ||
0eaa53f0 RV |
1764 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1765 | yesno(i915.enable_ips)); | |
1766 | ||
1767 | if (INTEL_INFO(dev)->gen >= 8) { | |
1768 | seq_puts(m, "Currently: unknown\n"); | |
1769 | } else { | |
1770 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1771 | seq_puts(m, "Currently: enabled\n"); | |
1772 | else | |
1773 | seq_puts(m, "Currently: disabled\n"); | |
1774 | } | |
92d44621 | 1775 | |
36623ef8 PZ |
1776 | intel_runtime_pm_put(dev_priv); |
1777 | ||
92d44621 PZ |
1778 | return 0; |
1779 | } | |
1780 | ||
4a9bef37 JB |
1781 | static int i915_sr_status(struct seq_file *m, void *unused) |
1782 | { | |
9f25d007 | 1783 | struct drm_info_node *node = m->private; |
4a9bef37 | 1784 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1785 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1786 | bool sr_enabled = false; |
1787 | ||
36623ef8 PZ |
1788 | intel_runtime_pm_get(dev_priv); |
1789 | ||
1398261a | 1790 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1791 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
77b64555 ACO |
1792 | else if (IS_CRESTLINE(dev) || IS_G4X(dev) || |
1793 | IS_I945G(dev) || IS_I945GM(dev)) | |
4a9bef37 JB |
1794 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1795 | else if (IS_I915GM(dev)) | |
1796 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1797 | else if (IS_PINEVIEW(dev)) | |
1798 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
666a4537 | 1799 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
77b64555 | 1800 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1801 | |
36623ef8 PZ |
1802 | intel_runtime_pm_put(dev_priv); |
1803 | ||
5ba2aaaa CW |
1804 | seq_printf(m, "self-refresh: %s\n", |
1805 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1806 | |
1807 | return 0; | |
1808 | } | |
1809 | ||
7648fa99 JB |
1810 | static int i915_emon_status(struct seq_file *m, void *unused) |
1811 | { | |
9f25d007 | 1812 | struct drm_info_node *node = m->private; |
7648fa99 | 1813 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1814 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1815 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1816 | int ret; |
1817 | ||
582be6b4 CW |
1818 | if (!IS_GEN5(dev)) |
1819 | return -ENODEV; | |
1820 | ||
de227ef0 CW |
1821 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1822 | if (ret) | |
1823 | return ret; | |
7648fa99 JB |
1824 | |
1825 | temp = i915_mch_val(dev_priv); | |
1826 | chipset = i915_chipset_val(dev_priv); | |
1827 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1828 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1829 | |
1830 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1831 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1832 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1833 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1834 | ||
1835 | return 0; | |
1836 | } | |
1837 | ||
23b2f8bb JB |
1838 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1839 | { | |
9f25d007 | 1840 | struct drm_info_node *node = m->private; |
23b2f8bb | 1841 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1842 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1843 | int ret = 0; |
23b2f8bb | 1844 | int gpu_freq, ia_freq; |
f936ec34 | 1845 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1846 | |
97d3308a | 1847 | if (!HAS_CORE_RING_FREQ(dev)) { |
267f0c90 | 1848 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1849 | return 0; |
1850 | } | |
1851 | ||
5bfa0199 PZ |
1852 | intel_runtime_pm_get(dev_priv); |
1853 | ||
5c9669ce TR |
1854 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1855 | ||
4fc688ce | 1856 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1857 | if (ret) |
5bfa0199 | 1858 | goto out; |
23b2f8bb | 1859 | |
ef11bdb3 | 1860 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
f936ec34 AG |
1861 | /* Convert GT frequency to 50 HZ units */ |
1862 | min_gpu_freq = | |
1863 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1864 | max_gpu_freq = | |
1865 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1866 | } else { | |
1867 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1868 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1869 | } | |
1870 | ||
267f0c90 | 1871 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1872 | |
f936ec34 | 1873 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1874 | ia_freq = gpu_freq; |
1875 | sandybridge_pcode_read(dev_priv, | |
1876 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1877 | &ia_freq); | |
3ebecd07 | 1878 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1879 | intel_gpu_freq(dev_priv, (gpu_freq * |
ef11bdb3 RV |
1880 | (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1881 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1882 | ((ia_freq >> 0) & 0xff) * 100, |
1883 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1884 | } |
1885 | ||
4fc688ce | 1886 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1887 | |
5bfa0199 PZ |
1888 | out: |
1889 | intel_runtime_pm_put(dev_priv); | |
1890 | return ret; | |
23b2f8bb JB |
1891 | } |
1892 | ||
44834a67 CW |
1893 | static int i915_opregion(struct seq_file *m, void *unused) |
1894 | { | |
9f25d007 | 1895 | struct drm_info_node *node = m->private; |
44834a67 | 1896 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1897 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 CW |
1898 | struct intel_opregion *opregion = &dev_priv->opregion; |
1899 | int ret; | |
1900 | ||
1901 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1902 | if (ret) | |
0d38f009 | 1903 | goto out; |
44834a67 | 1904 | |
2455a8e4 JN |
1905 | if (opregion->header) |
1906 | seq_write(m, opregion->header, OPREGION_SIZE); | |
44834a67 CW |
1907 | |
1908 | mutex_unlock(&dev->struct_mutex); | |
1909 | ||
0d38f009 | 1910 | out: |
44834a67 CW |
1911 | return 0; |
1912 | } | |
1913 | ||
ada8f955 JN |
1914 | static int i915_vbt(struct seq_file *m, void *unused) |
1915 | { | |
1916 | struct drm_info_node *node = m->private; | |
1917 | struct drm_device *dev = node->minor->dev; | |
1918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1919 | struct intel_opregion *opregion = &dev_priv->opregion; | |
1920 | ||
1921 | if (opregion->vbt) | |
1922 | seq_write(m, opregion->vbt, opregion->vbt_size); | |
1923 | ||
1924 | return 0; | |
1925 | } | |
1926 | ||
37811fcc CW |
1927 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1928 | { | |
9f25d007 | 1929 | struct drm_info_node *node = m->private; |
37811fcc | 1930 | struct drm_device *dev = node->minor->dev; |
b13b8402 | 1931 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1932 | struct drm_framebuffer *drm_fb; |
188c1ab7 CW |
1933 | int ret; |
1934 | ||
1935 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1936 | if (ret) | |
1937 | return ret; | |
37811fcc | 1938 | |
0695726e | 1939 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
b13b8402 NS |
1940 | if (to_i915(dev)->fbdev) { |
1941 | fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb); | |
1942 | ||
1943 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1944 | fbdev_fb->base.width, | |
1945 | fbdev_fb->base.height, | |
1946 | fbdev_fb->base.depth, | |
1947 | fbdev_fb->base.bits_per_pixel, | |
1948 | fbdev_fb->base.modifier[0], | |
1949 | atomic_read(&fbdev_fb->base.refcount.refcount)); | |
1950 | describe_obj(m, fbdev_fb->obj); | |
1951 | seq_putc(m, '\n'); | |
1952 | } | |
4520f53a | 1953 | #endif |
37811fcc | 1954 | |
4b096ac1 | 1955 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1956 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1957 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1958 | if (fb == fbdev_fb) | |
37811fcc CW |
1959 | continue; |
1960 | ||
c1ca506d | 1961 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1962 | fb->base.width, |
1963 | fb->base.height, | |
1964 | fb->base.depth, | |
623f9783 | 1965 | fb->base.bits_per_pixel, |
c1ca506d | 1966 | fb->base.modifier[0], |
623f9783 | 1967 | atomic_read(&fb->base.refcount.refcount)); |
05394f39 | 1968 | describe_obj(m, fb->obj); |
267f0c90 | 1969 | seq_putc(m, '\n'); |
37811fcc | 1970 | } |
4b096ac1 | 1971 | mutex_unlock(&dev->mode_config.fb_lock); |
188c1ab7 | 1972 | mutex_unlock(&dev->struct_mutex); |
37811fcc CW |
1973 | |
1974 | return 0; | |
1975 | } | |
1976 | ||
c9fe99bd OM |
1977 | static void describe_ctx_ringbuf(struct seq_file *m, |
1978 | struct intel_ringbuffer *ringbuf) | |
1979 | { | |
1980 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
1981 | ringbuf->space, ringbuf->head, ringbuf->tail, | |
1982 | ringbuf->last_retired_head); | |
1983 | } | |
1984 | ||
e76d3630 BW |
1985 | static int i915_context_status(struct seq_file *m, void *unused) |
1986 | { | |
9f25d007 | 1987 | struct drm_info_node *node = m->private; |
e76d3630 | 1988 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1989 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 1990 | struct intel_engine_cs *engine; |
273497e5 | 1991 | struct intel_context *ctx; |
c3232b18 DG |
1992 | enum intel_engine_id id; |
1993 | int ret; | |
e76d3630 | 1994 | |
f3d28878 | 1995 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1996 | if (ret) |
1997 | return ret; | |
1998 | ||
a33afea5 | 1999 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
c9fe99bd OM |
2000 | if (!i915.enable_execlists && |
2001 | ctx->legacy_hw_ctx.rcs_state == NULL) | |
b77f6997 CW |
2002 | continue; |
2003 | ||
5d1808ec | 2004 | seq_printf(m, "HW context %u ", ctx->hw_id); |
3ccfd19d | 2005 | describe_ctx(m, ctx); |
e28e404c DG |
2006 | if (ctx == dev_priv->kernel_context) |
2007 | seq_printf(m, "(kernel context) "); | |
c9fe99bd OM |
2008 | |
2009 | if (i915.enable_execlists) { | |
2010 | seq_putc(m, '\n'); | |
c3232b18 | 2011 | for_each_engine_id(engine, dev_priv, id) { |
c9fe99bd | 2012 | struct drm_i915_gem_object *ctx_obj = |
c3232b18 | 2013 | ctx->engine[id].state; |
c9fe99bd | 2014 | struct intel_ringbuffer *ringbuf = |
c3232b18 | 2015 | ctx->engine[id].ringbuf; |
c9fe99bd | 2016 | |
e2f80391 | 2017 | seq_printf(m, "%s: ", engine->name); |
c9fe99bd OM |
2018 | if (ctx_obj) |
2019 | describe_obj(m, ctx_obj); | |
2020 | if (ringbuf) | |
2021 | describe_ctx_ringbuf(m, ringbuf); | |
2022 | seq_putc(m, '\n'); | |
2023 | } | |
2024 | } else { | |
2025 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); | |
2026 | } | |
a33afea5 | 2027 | |
a33afea5 | 2028 | seq_putc(m, '\n'); |
a168c293 BW |
2029 | } |
2030 | ||
f3d28878 | 2031 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
2032 | |
2033 | return 0; | |
2034 | } | |
2035 | ||
064ca1d2 | 2036 | static void i915_dump_lrc_obj(struct seq_file *m, |
ca82580c | 2037 | struct intel_context *ctx, |
0bc40be8 | 2038 | struct intel_engine_cs *engine) |
064ca1d2 TD |
2039 | { |
2040 | struct page *page; | |
2041 | uint32_t *reg_state; | |
2042 | int j; | |
0bc40be8 | 2043 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
064ca1d2 TD |
2044 | unsigned long ggtt_offset = 0; |
2045 | ||
7069b144 CW |
2046 | seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); |
2047 | ||
064ca1d2 | 2048 | if (ctx_obj == NULL) { |
7069b144 | 2049 | seq_puts(m, "\tNot allocated\n"); |
064ca1d2 TD |
2050 | return; |
2051 | } | |
2052 | ||
064ca1d2 TD |
2053 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) |
2054 | seq_puts(m, "\tNot bound in GGTT\n"); | |
2055 | else | |
2056 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); | |
2057 | ||
2058 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2059 | seq_puts(m, "\tFailed to get pages for context object\n"); | |
2060 | return; | |
2061 | } | |
2062 | ||
d1675198 | 2063 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
064ca1d2 TD |
2064 | if (!WARN_ON(page == NULL)) { |
2065 | reg_state = kmap_atomic(page); | |
2066 | ||
2067 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
2068 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2069 | ggtt_offset + 4096 + (j * 4), | |
2070 | reg_state[j], reg_state[j + 1], | |
2071 | reg_state[j + 2], reg_state[j + 3]); | |
2072 | } | |
2073 | kunmap_atomic(reg_state); | |
2074 | } | |
2075 | ||
2076 | seq_putc(m, '\n'); | |
2077 | } | |
2078 | ||
c0ab1ae9 BW |
2079 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2080 | { | |
2081 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2082 | struct drm_device *dev = node->minor->dev; | |
2083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2084 | struct intel_engine_cs *engine; |
c0ab1ae9 | 2085 | struct intel_context *ctx; |
b4ac5afc | 2086 | int ret; |
c0ab1ae9 BW |
2087 | |
2088 | if (!i915.enable_execlists) { | |
2089 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2090 | return 0; | |
2091 | } | |
2092 | ||
2093 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2094 | if (ret) | |
2095 | return ret; | |
2096 | ||
e28e404c DG |
2097 | list_for_each_entry(ctx, &dev_priv->context_list, link) |
2098 | if (ctx != dev_priv->kernel_context) | |
b4ac5afc | 2099 | for_each_engine(engine, dev_priv) |
e2f80391 | 2100 | i915_dump_lrc_obj(m, ctx, engine); |
c0ab1ae9 BW |
2101 | |
2102 | mutex_unlock(&dev->struct_mutex); | |
2103 | ||
2104 | return 0; | |
2105 | } | |
2106 | ||
4ba70e44 OM |
2107 | static int i915_execlists(struct seq_file *m, void *data) |
2108 | { | |
2109 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
2110 | struct drm_device *dev = node->minor->dev; | |
2111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2112 | struct intel_engine_cs *engine; |
4ba70e44 OM |
2113 | u32 status_pointer; |
2114 | u8 read_pointer; | |
2115 | u8 write_pointer; | |
2116 | u32 status; | |
2117 | u32 ctx_id; | |
2118 | struct list_head *cursor; | |
b4ac5afc | 2119 | int i, ret; |
4ba70e44 OM |
2120 | |
2121 | if (!i915.enable_execlists) { | |
2122 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
2123 | return 0; | |
2124 | } | |
2125 | ||
2126 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2127 | if (ret) | |
2128 | return ret; | |
2129 | ||
fc0412ec MT |
2130 | intel_runtime_pm_get(dev_priv); |
2131 | ||
b4ac5afc | 2132 | for_each_engine(engine, dev_priv) { |
6d3d8274 | 2133 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 | 2134 | int count = 0; |
4ba70e44 | 2135 | |
e2f80391 | 2136 | seq_printf(m, "%s\n", engine->name); |
4ba70e44 | 2137 | |
e2f80391 TU |
2138 | status = I915_READ(RING_EXECLIST_STATUS_LO(engine)); |
2139 | ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine)); | |
4ba70e44 OM |
2140 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
2141 | status, ctx_id); | |
2142 | ||
e2f80391 | 2143 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); |
4ba70e44 OM |
2144 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); |
2145 | ||
e2f80391 | 2146 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 2147 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
4ba70e44 | 2148 | if (read_pointer > write_pointer) |
5590a5f0 | 2149 | write_pointer += GEN8_CSB_ENTRIES; |
4ba70e44 OM |
2150 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", |
2151 | read_pointer, write_pointer); | |
2152 | ||
5590a5f0 | 2153 | for (i = 0; i < GEN8_CSB_ENTRIES; i++) { |
e2f80391 TU |
2154 | status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i)); |
2155 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i)); | |
4ba70e44 OM |
2156 | |
2157 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
2158 | i, status, ctx_id); | |
2159 | } | |
2160 | ||
27af5eea | 2161 | spin_lock_bh(&engine->execlist_lock); |
e2f80391 | 2162 | list_for_each(cursor, &engine->execlist_queue) |
4ba70e44 | 2163 | count++; |
e2f80391 TU |
2164 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
2165 | struct drm_i915_gem_request, | |
2166 | execlist_link); | |
27af5eea | 2167 | spin_unlock_bh(&engine->execlist_lock); |
4ba70e44 OM |
2168 | |
2169 | seq_printf(m, "\t%d requests in queue\n", count); | |
2170 | if (head_req) { | |
7069b144 CW |
2171 | seq_printf(m, "\tHead request context: %u\n", |
2172 | head_req->ctx->hw_id); | |
4ba70e44 | 2173 | seq_printf(m, "\tHead request tail: %u\n", |
6d3d8274 | 2174 | head_req->tail); |
4ba70e44 OM |
2175 | } |
2176 | ||
2177 | seq_putc(m, '\n'); | |
2178 | } | |
2179 | ||
fc0412ec | 2180 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2181 | mutex_unlock(&dev->struct_mutex); |
2182 | ||
2183 | return 0; | |
2184 | } | |
2185 | ||
ea16a3cd DV |
2186 | static const char *swizzle_string(unsigned swizzle) |
2187 | { | |
aee56cff | 2188 | switch (swizzle) { |
ea16a3cd DV |
2189 | case I915_BIT_6_SWIZZLE_NONE: |
2190 | return "none"; | |
2191 | case I915_BIT_6_SWIZZLE_9: | |
2192 | return "bit9"; | |
2193 | case I915_BIT_6_SWIZZLE_9_10: | |
2194 | return "bit9/bit10"; | |
2195 | case I915_BIT_6_SWIZZLE_9_11: | |
2196 | return "bit9/bit11"; | |
2197 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2198 | return "bit9/bit10/bit11"; | |
2199 | case I915_BIT_6_SWIZZLE_9_17: | |
2200 | return "bit9/bit17"; | |
2201 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2202 | return "bit9/bit10/bit17"; | |
2203 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2204 | return "unknown"; |
ea16a3cd DV |
2205 | } |
2206 | ||
2207 | return "bug"; | |
2208 | } | |
2209 | ||
2210 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2211 | { | |
9f25d007 | 2212 | struct drm_info_node *node = m->private; |
ea16a3cd DV |
2213 | struct drm_device *dev = node->minor->dev; |
2214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
2215 | int ret; |
2216 | ||
2217 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2218 | if (ret) | |
2219 | return ret; | |
c8c8fb33 | 2220 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2221 | |
ea16a3cd DV |
2222 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2223 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2224 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2225 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2226 | ||
2227 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
2228 | seq_printf(m, "DDC = 0x%08x\n", | |
2229 | I915_READ(DCC)); | |
656bfa3a DV |
2230 | seq_printf(m, "DDC2 = 0x%08x\n", |
2231 | I915_READ(DCC2)); | |
ea16a3cd DV |
2232 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2233 | I915_READ16(C0DRB3)); | |
2234 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2235 | I915_READ16(C1DRB3)); | |
9d3203e1 | 2236 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
2237 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2238 | I915_READ(MAD_DIMM_C0)); | |
2239 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2240 | I915_READ(MAD_DIMM_C1)); | |
2241 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2242 | I915_READ(MAD_DIMM_C2)); | |
2243 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2244 | I915_READ(TILECTL)); | |
5907f5fb | 2245 | if (INTEL_INFO(dev)->gen >= 8) |
9d3203e1 BW |
2246 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2247 | I915_READ(GAMTARBMODE)); | |
2248 | else | |
2249 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2250 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2251 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2252 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2253 | } |
656bfa3a DV |
2254 | |
2255 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2256 | seq_puts(m, "L-shaped memory detected\n"); | |
2257 | ||
c8c8fb33 | 2258 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2259 | mutex_unlock(&dev->struct_mutex); |
2260 | ||
2261 | return 0; | |
2262 | } | |
2263 | ||
1c60fef5 BW |
2264 | static int per_file_ctx(int id, void *ptr, void *data) |
2265 | { | |
273497e5 | 2266 | struct intel_context *ctx = ptr; |
1c60fef5 | 2267 | struct seq_file *m = data; |
ae6c4806 DV |
2268 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2269 | ||
2270 | if (!ppgtt) { | |
2271 | seq_printf(m, " no ppgtt for context %d\n", | |
2272 | ctx->user_handle); | |
2273 | return 0; | |
2274 | } | |
1c60fef5 | 2275 | |
f83d6518 OM |
2276 | if (i915_gem_context_is_default(ctx)) |
2277 | seq_puts(m, " default context:\n"); | |
2278 | else | |
821d66dd | 2279 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2280 | ppgtt->debug_dump(ppgtt, m); |
2281 | ||
2282 | return 0; | |
2283 | } | |
2284 | ||
77df6772 | 2285 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 2286 | { |
3cf17fc5 | 2287 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 2288 | struct intel_engine_cs *engine; |
77df6772 | 2289 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
b4ac5afc | 2290 | int i; |
3cf17fc5 | 2291 | |
77df6772 BW |
2292 | if (!ppgtt) |
2293 | return; | |
2294 | ||
b4ac5afc | 2295 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2296 | seq_printf(m, "%s\n", engine->name); |
77df6772 | 2297 | for (i = 0; i < 4; i++) { |
e2f80391 | 2298 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); |
77df6772 | 2299 | pdp <<= 32; |
e2f80391 | 2300 | pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); |
a2a5b15c | 2301 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2302 | } |
2303 | } | |
2304 | } | |
2305 | ||
2306 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
2307 | { | |
2308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2309 | struct intel_engine_cs *engine; |
3cf17fc5 | 2310 | |
3cf17fc5 DV |
2311 | if (INTEL_INFO(dev)->gen == 6) |
2312 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
2313 | ||
b4ac5afc | 2314 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2315 | seq_printf(m, "%s\n", engine->name); |
3cf17fc5 | 2316 | if (INTEL_INFO(dev)->gen == 7) |
e2f80391 TU |
2317 | seq_printf(m, "GFX_MODE: 0x%08x\n", |
2318 | I915_READ(RING_MODE_GEN7(engine))); | |
2319 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", | |
2320 | I915_READ(RING_PP_DIR_BASE(engine))); | |
2321 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", | |
2322 | I915_READ(RING_PP_DIR_BASE_READ(engine))); | |
2323 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", | |
2324 | I915_READ(RING_PP_DIR_DCLV(engine))); | |
3cf17fc5 DV |
2325 | } |
2326 | if (dev_priv->mm.aliasing_ppgtt) { | |
2327 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2328 | ||
267f0c90 | 2329 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2330 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2331 | |
87d60b63 | 2332 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2333 | } |
1c60fef5 | 2334 | |
3cf17fc5 | 2335 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2336 | } |
2337 | ||
2338 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2339 | { | |
9f25d007 | 2340 | struct drm_info_node *node = m->private; |
77df6772 | 2341 | struct drm_device *dev = node->minor->dev; |
c8c8fb33 | 2342 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea91e401 | 2343 | struct drm_file *file; |
77df6772 BW |
2344 | |
2345 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2346 | if (ret) | |
2347 | return ret; | |
c8c8fb33 | 2348 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
2349 | |
2350 | if (INTEL_INFO(dev)->gen >= 8) | |
2351 | gen8_ppgtt_info(m, dev); | |
2352 | else if (INTEL_INFO(dev)->gen >= 6) | |
2353 | gen6_ppgtt_info(m, dev); | |
2354 | ||
ea91e401 MT |
2355 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2356 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2357 | struct task_struct *task; |
ea91e401 | 2358 | |
7cb5dff8 | 2359 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2360 | if (!task) { |
2361 | ret = -ESRCH; | |
2362 | goto out_put; | |
2363 | } | |
7cb5dff8 GT |
2364 | seq_printf(m, "\nproc: %s\n", task->comm); |
2365 | put_task_struct(task); | |
ea91e401 MT |
2366 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2367 | (void *)(unsigned long)m); | |
2368 | } | |
2369 | ||
06812760 | 2370 | out_put: |
c8c8fb33 | 2371 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
2372 | mutex_unlock(&dev->struct_mutex); |
2373 | ||
06812760 | 2374 | return ret; |
3cf17fc5 DV |
2375 | } |
2376 | ||
f5a4c67d CW |
2377 | static int count_irq_waiters(struct drm_i915_private *i915) |
2378 | { | |
e2f80391 | 2379 | struct intel_engine_cs *engine; |
f5a4c67d | 2380 | int count = 0; |
f5a4c67d | 2381 | |
b4ac5afc | 2382 | for_each_engine(engine, i915) |
e2f80391 | 2383 | count += engine->irq_refcount; |
f5a4c67d CW |
2384 | |
2385 | return count; | |
2386 | } | |
2387 | ||
1854d5ca CW |
2388 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2389 | { | |
2390 | struct drm_info_node *node = m->private; | |
2391 | struct drm_device *dev = node->minor->dev; | |
2392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2393 | struct drm_file *file; | |
1854d5ca | 2394 | |
f5a4c67d CW |
2395 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
2396 | seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); | |
2397 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); | |
2398 | seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
2399 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
2400 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
2401 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2402 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2403 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
8d3afd7d | 2404 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2405 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2406 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2407 | struct task_struct *task; | |
2408 | ||
2409 | rcu_read_lock(); | |
2410 | task = pid_task(file->pid, PIDTYPE_PID); | |
2411 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2412 | task ? task->comm : "<unknown>", | |
2413 | task ? task->pid : -1, | |
2e1b8730 CW |
2414 | file_priv->rps.boosts, |
2415 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2416 | rcu_read_unlock(); |
2417 | } | |
2e1b8730 CW |
2418 | seq_printf(m, "Semaphore boosts: %d%s\n", |
2419 | dev_priv->rps.semaphores.boosts, | |
2420 | list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active"); | |
2421 | seq_printf(m, "MMIO flip boosts: %d%s\n", | |
2422 | dev_priv->rps.mmioflips.boosts, | |
2423 | list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); | |
1854d5ca | 2424 | seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2425 | spin_unlock(&dev_priv->rps.client_lock); |
1854d5ca | 2426 | |
8d3afd7d | 2427 | return 0; |
1854d5ca CW |
2428 | } |
2429 | ||
63573eb7 BW |
2430 | static int i915_llc(struct seq_file *m, void *data) |
2431 | { | |
9f25d007 | 2432 | struct drm_info_node *node = m->private; |
63573eb7 BW |
2433 | struct drm_device *dev = node->minor->dev; |
2434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3accaf7e | 2435 | const bool edram = INTEL_GEN(dev_priv) > 8; |
63573eb7 | 2436 | |
63573eb7 | 2437 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); |
3accaf7e MK |
2438 | seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", |
2439 | intel_uncore_edram_size(dev_priv)/1024/1024); | |
63573eb7 BW |
2440 | |
2441 | return 0; | |
2442 | } | |
2443 | ||
fdf5d357 AD |
2444 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2445 | { | |
2446 | struct drm_info_node *node = m->private; | |
2447 | struct drm_i915_private *dev_priv = node->minor->dev->dev_private; | |
2448 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
2449 | u32 tmp, i; | |
2450 | ||
2d1fe073 | 2451 | if (!HAS_GUC_UCODE(dev_priv)) |
fdf5d357 AD |
2452 | return 0; |
2453 | ||
2454 | seq_printf(m, "GuC firmware status:\n"); | |
2455 | seq_printf(m, "\tpath: %s\n", | |
2456 | guc_fw->guc_fw_path); | |
2457 | seq_printf(m, "\tfetch: %s\n", | |
2458 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2459 | seq_printf(m, "\tload: %s\n", | |
2460 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2461 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2462 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2463 | seq_printf(m, "\tversion found: %d.%d\n", | |
2464 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2465 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2466 | guc_fw->header_offset, guc_fw->header_size); | |
2467 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2468 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2469 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2470 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2471 | |
2472 | tmp = I915_READ(GUC_STATUS); | |
2473 | ||
2474 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2475 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2476 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2477 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2478 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2479 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2480 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2481 | seq_puts(m, "\nScratch registers:\n"); | |
2482 | for (i = 0; i < 16; i++) | |
2483 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2484 | ||
2485 | return 0; | |
2486 | } | |
2487 | ||
8b417c26 DG |
2488 | static void i915_guc_client_info(struct seq_file *m, |
2489 | struct drm_i915_private *dev_priv, | |
2490 | struct i915_guc_client *client) | |
2491 | { | |
e2f80391 | 2492 | struct intel_engine_cs *engine; |
8b417c26 | 2493 | uint64_t tot = 0; |
8b417c26 DG |
2494 | |
2495 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2496 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2497 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
2498 | client->doorbell_id, client->doorbell_offset, client->cookie); | |
2499 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", | |
2500 | client->wq_size, client->wq_offset, client->wq_tail); | |
2501 | ||
2502 | seq_printf(m, "\tFailed to queue: %u\n", client->q_fail); | |
2503 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); | |
2504 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2505 | ||
b4ac5afc | 2506 | for_each_engine(engine, dev_priv) { |
8b417c26 | 2507 | seq_printf(m, "\tSubmissions: %llu %s\n", |
e2f80391 TU |
2508 | client->submissions[engine->guc_id], |
2509 | engine->name); | |
2510 | tot += client->submissions[engine->guc_id]; | |
8b417c26 DG |
2511 | } |
2512 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2513 | } | |
2514 | ||
2515 | static int i915_guc_info(struct seq_file *m, void *data) | |
2516 | { | |
2517 | struct drm_info_node *node = m->private; | |
2518 | struct drm_device *dev = node->minor->dev; | |
2519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2520 | struct intel_guc guc; | |
0a0b457f | 2521 | struct i915_guc_client client = {}; |
e2f80391 | 2522 | struct intel_engine_cs *engine; |
8b417c26 DG |
2523 | u64 total = 0; |
2524 | ||
2d1fe073 | 2525 | if (!HAS_GUC_SCHED(dev_priv)) |
8b417c26 DG |
2526 | return 0; |
2527 | ||
5a843307 AD |
2528 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
2529 | return 0; | |
2530 | ||
8b417c26 | 2531 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
8b417c26 | 2532 | guc = dev_priv->guc; |
5a843307 | 2533 | if (guc.execbuf_client) |
8b417c26 | 2534 | client = *guc.execbuf_client; |
5a843307 AD |
2535 | |
2536 | mutex_unlock(&dev->struct_mutex); | |
8b417c26 DG |
2537 | |
2538 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); | |
2539 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); | |
2540 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); | |
2541 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); | |
2542 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); | |
2543 | ||
2544 | seq_printf(m, "\nGuC submissions:\n"); | |
b4ac5afc | 2545 | for_each_engine(engine, dev_priv) { |
397097b0 | 2546 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", |
e2f80391 TU |
2547 | engine->name, guc.submissions[engine->guc_id], |
2548 | guc.last_seqno[engine->guc_id]); | |
2549 | total += guc.submissions[engine->guc_id]; | |
8b417c26 DG |
2550 | } |
2551 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2552 | ||
2553 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); | |
2554 | i915_guc_client_info(m, dev_priv, &client); | |
2555 | ||
2556 | /* Add more as required ... */ | |
2557 | ||
2558 | return 0; | |
2559 | } | |
2560 | ||
4c7e77fc AD |
2561 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2562 | { | |
2563 | struct drm_info_node *node = m->private; | |
2564 | struct drm_device *dev = node->minor->dev; | |
2565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2566 | struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj; | |
2567 | u32 *log; | |
2568 | int i = 0, pg; | |
2569 | ||
2570 | if (!log_obj) | |
2571 | return 0; | |
2572 | ||
2573 | for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) { | |
2574 | log = kmap_atomic(i915_gem_object_get_page(log_obj, pg)); | |
2575 | ||
2576 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2577 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2578 | *(log + i), *(log + i + 1), | |
2579 | *(log + i + 2), *(log + i + 3)); | |
2580 | ||
2581 | kunmap_atomic(log); | |
2582 | } | |
2583 | ||
2584 | seq_putc(m, '\n'); | |
2585 | ||
2586 | return 0; | |
2587 | } | |
2588 | ||
e91fd8c6 RV |
2589 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2590 | { | |
2591 | struct drm_info_node *node = m->private; | |
2592 | struct drm_device *dev = node->minor->dev; | |
2593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 | 2594 | u32 psrperf = 0; |
a6cbdb8e RV |
2595 | u32 stat[3]; |
2596 | enum pipe pipe; | |
a031d709 | 2597 | bool enabled = false; |
e91fd8c6 | 2598 | |
3553a8ea DL |
2599 | if (!HAS_PSR(dev)) { |
2600 | seq_puts(m, "PSR not supported\n"); | |
2601 | return 0; | |
2602 | } | |
2603 | ||
c8c8fb33 PZ |
2604 | intel_runtime_pm_get(dev_priv); |
2605 | ||
fa128fa6 | 2606 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2607 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2608 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2609 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2610 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2611 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2612 | dev_priv->psr.busy_frontbuffer_bits); | |
2613 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2614 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2615 | |
3553a8ea | 2616 | if (HAS_DDI(dev)) |
443a389f | 2617 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
3553a8ea DL |
2618 | else { |
2619 | for_each_pipe(dev_priv, pipe) { | |
2620 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2621 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2622 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2623 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2624 | enabled = true; | |
a6cbdb8e RV |
2625 | } |
2626 | } | |
60e5ffe3 RV |
2627 | |
2628 | seq_printf(m, "Main link in standby mode: %s\n", | |
2629 | yesno(dev_priv->psr.link_standby)); | |
2630 | ||
a6cbdb8e RV |
2631 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); |
2632 | ||
2633 | if (!HAS_DDI(dev)) | |
2634 | for_each_pipe(dev_priv, pipe) { | |
2635 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2636 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2637 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2638 | } | |
2639 | seq_puts(m, "\n"); | |
e91fd8c6 | 2640 | |
05eec3c2 RV |
2641 | /* |
2642 | * VLV/CHV PSR has no kind of performance counter | |
2643 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2644 | */ | |
2645 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
443a389f | 2646 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2647 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2648 | |
2649 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2650 | } | |
fa128fa6 | 2651 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2652 | |
c8c8fb33 | 2653 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2654 | return 0; |
2655 | } | |
2656 | ||
d2e216d0 RV |
2657 | static int i915_sink_crc(struct seq_file *m, void *data) |
2658 | { | |
2659 | struct drm_info_node *node = m->private; | |
2660 | struct drm_device *dev = node->minor->dev; | |
2661 | struct intel_encoder *encoder; | |
2662 | struct intel_connector *connector; | |
2663 | struct intel_dp *intel_dp = NULL; | |
2664 | int ret; | |
2665 | u8 crc[6]; | |
2666 | ||
2667 | drm_modeset_lock_all(dev); | |
aca5e361 | 2668 | for_each_intel_connector(dev, connector) { |
d2e216d0 RV |
2669 | |
2670 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
2671 | continue; | |
2672 | ||
b6ae3c7c PZ |
2673 | if (!connector->base.encoder) |
2674 | continue; | |
2675 | ||
d2e216d0 RV |
2676 | encoder = to_intel_encoder(connector->base.encoder); |
2677 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2678 | continue; | |
2679 | ||
2680 | intel_dp = enc_to_intel_dp(&encoder->base); | |
2681 | ||
2682 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2683 | if (ret) | |
2684 | goto out; | |
2685 | ||
2686 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2687 | crc[0], crc[1], crc[2], | |
2688 | crc[3], crc[4], crc[5]); | |
2689 | goto out; | |
2690 | } | |
2691 | ret = -ENODEV; | |
2692 | out: | |
2693 | drm_modeset_unlock_all(dev); | |
2694 | return ret; | |
2695 | } | |
2696 | ||
ec013e7f JB |
2697 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2698 | { | |
2699 | struct drm_info_node *node = m->private; | |
2700 | struct drm_device *dev = node->minor->dev; | |
2701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2702 | u64 power; | |
2703 | u32 units; | |
2704 | ||
2705 | if (INTEL_INFO(dev)->gen < 6) | |
2706 | return -ENODEV; | |
2707 | ||
36623ef8 PZ |
2708 | intel_runtime_pm_get(dev_priv); |
2709 | ||
ec013e7f JB |
2710 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2711 | power = (power & 0x1f00) >> 8; | |
2712 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2713 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2714 | power *= units; | |
2715 | ||
36623ef8 PZ |
2716 | intel_runtime_pm_put(dev_priv); |
2717 | ||
ec013e7f | 2718 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2719 | |
2720 | return 0; | |
2721 | } | |
2722 | ||
6455c870 | 2723 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2724 | { |
9f25d007 | 2725 | struct drm_info_node *node = m->private; |
371db66a PZ |
2726 | struct drm_device *dev = node->minor->dev; |
2727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2728 | ||
a156e64d CW |
2729 | if (!HAS_RUNTIME_PM(dev_priv)) |
2730 | seq_puts(m, "Runtime power management not supported\n"); | |
371db66a | 2731 | |
86c4ec0d | 2732 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2733 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2734 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2735 | #ifdef CONFIG_PM |
a6aaec8b DL |
2736 | seq_printf(m, "Usage count: %d\n", |
2737 | atomic_read(&dev->dev->power.usage_count)); | |
0d804184 CW |
2738 | #else |
2739 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2740 | #endif | |
a156e64d CW |
2741 | seq_printf(m, "PCI device power state: %s [%d]\n", |
2742 | pci_power_name(dev_priv->dev->pdev->current_state), | |
2743 | dev_priv->dev->pdev->current_state); | |
371db66a | 2744 | |
ec013e7f JB |
2745 | return 0; |
2746 | } | |
2747 | ||
1da51581 ID |
2748 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2749 | { | |
9f25d007 | 2750 | struct drm_info_node *node = m->private; |
1da51581 ID |
2751 | struct drm_device *dev = node->minor->dev; |
2752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2753 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2754 | int i; | |
2755 | ||
2756 | mutex_lock(&power_domains->lock); | |
2757 | ||
2758 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2759 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2760 | struct i915_power_well *power_well; | |
2761 | enum intel_display_power_domain power_domain; | |
2762 | ||
2763 | power_well = &power_domains->power_wells[i]; | |
2764 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2765 | power_well->count); | |
2766 | ||
2767 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2768 | power_domain++) { | |
2769 | if (!(BIT(power_domain) & power_well->domains)) | |
2770 | continue; | |
2771 | ||
2772 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2773 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2774 | power_domains->domain_use_count[power_domain]); |
2775 | } | |
2776 | } | |
2777 | ||
2778 | mutex_unlock(&power_domains->lock); | |
2779 | ||
2780 | return 0; | |
2781 | } | |
2782 | ||
b7cec66d DL |
2783 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2784 | { | |
2785 | struct drm_info_node *node = m->private; | |
2786 | struct drm_device *dev = node->minor->dev; | |
2787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2788 | struct intel_csr *csr; | |
2789 | ||
2790 | if (!HAS_CSR(dev)) { | |
2791 | seq_puts(m, "not supported\n"); | |
2792 | return 0; | |
2793 | } | |
2794 | ||
2795 | csr = &dev_priv->csr; | |
2796 | ||
6fb403de MK |
2797 | intel_runtime_pm_get(dev_priv); |
2798 | ||
b7cec66d DL |
2799 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2800 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2801 | ||
2802 | if (!csr->dmc_payload) | |
6fb403de | 2803 | goto out; |
b7cec66d DL |
2804 | |
2805 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2806 | CSR_VERSION_MINOR(csr->version)); | |
2807 | ||
8337206d DL |
2808 | if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { |
2809 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2810 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2811 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2812 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
16e11b99 MK |
2813 | } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) { |
2814 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2815 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2816 | } |
2817 | ||
6fb403de MK |
2818 | out: |
2819 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2820 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2821 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2822 | ||
8337206d DL |
2823 | intel_runtime_pm_put(dev_priv); |
2824 | ||
b7cec66d DL |
2825 | return 0; |
2826 | } | |
2827 | ||
53f5e3ca JB |
2828 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2829 | struct drm_display_mode *mode) | |
2830 | { | |
2831 | int i; | |
2832 | ||
2833 | for (i = 0; i < tabs; i++) | |
2834 | seq_putc(m, '\t'); | |
2835 | ||
2836 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2837 | mode->base.id, mode->name, | |
2838 | mode->vrefresh, mode->clock, | |
2839 | mode->hdisplay, mode->hsync_start, | |
2840 | mode->hsync_end, mode->htotal, | |
2841 | mode->vdisplay, mode->vsync_start, | |
2842 | mode->vsync_end, mode->vtotal, | |
2843 | mode->type, mode->flags); | |
2844 | } | |
2845 | ||
2846 | static void intel_encoder_info(struct seq_file *m, | |
2847 | struct intel_crtc *intel_crtc, | |
2848 | struct intel_encoder *intel_encoder) | |
2849 | { | |
9f25d007 | 2850 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2851 | struct drm_device *dev = node->minor->dev; |
2852 | struct drm_crtc *crtc = &intel_crtc->base; | |
2853 | struct intel_connector *intel_connector; | |
2854 | struct drm_encoder *encoder; | |
2855 | ||
2856 | encoder = &intel_encoder->base; | |
2857 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2858 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2859 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2860 | struct drm_connector *connector = &intel_connector->base; | |
2861 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2862 | connector->base.id, | |
c23cc417 | 2863 | connector->name, |
53f5e3ca JB |
2864 | drm_get_connector_status_name(connector->status)); |
2865 | if (connector->status == connector_status_connected) { | |
2866 | struct drm_display_mode *mode = &crtc->mode; | |
2867 | seq_printf(m, ", mode:\n"); | |
2868 | intel_seq_print_mode(m, 2, mode); | |
2869 | } else { | |
2870 | seq_putc(m, '\n'); | |
2871 | } | |
2872 | } | |
2873 | } | |
2874 | ||
2875 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2876 | { | |
9f25d007 | 2877 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2878 | struct drm_device *dev = node->minor->dev; |
2879 | struct drm_crtc *crtc = &intel_crtc->base; | |
2880 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2881 | struct drm_plane_state *plane_state = crtc->primary->state; |
2882 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2883 | |
23a48d53 | 2884 | if (fb) |
5aa8a937 | 2885 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2886 | fb->base.id, plane_state->src_x >> 16, |
2887 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2888 | else |
2889 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2890 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2891 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2892 | } | |
2893 | ||
2894 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2895 | { | |
2896 | struct drm_display_mode *mode = panel->fixed_mode; | |
2897 | ||
2898 | seq_printf(m, "\tfixed mode:\n"); | |
2899 | intel_seq_print_mode(m, 2, mode); | |
2900 | } | |
2901 | ||
2902 | static void intel_dp_info(struct seq_file *m, | |
2903 | struct intel_connector *intel_connector) | |
2904 | { | |
2905 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2906 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2907 | ||
2908 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2909 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
53f5e3ca JB |
2910 | if (intel_encoder->type == INTEL_OUTPUT_EDP) |
2911 | intel_panel_info(m, &intel_connector->panel); | |
2912 | } | |
2913 | ||
3d52ccf5 LY |
2914 | static void intel_dp_mst_info(struct seq_file *m, |
2915 | struct intel_connector *intel_connector) | |
2916 | { | |
2917 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2918 | struct intel_dp_mst_encoder *intel_mst = | |
2919 | enc_to_mst(&intel_encoder->base); | |
2920 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2921 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2922 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2923 | intel_connector->port); | |
2924 | ||
2925 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2926 | } | |
2927 | ||
53f5e3ca JB |
2928 | static void intel_hdmi_info(struct seq_file *m, |
2929 | struct intel_connector *intel_connector) | |
2930 | { | |
2931 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2932 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2933 | ||
742f491d | 2934 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2935 | } |
2936 | ||
2937 | static void intel_lvds_info(struct seq_file *m, | |
2938 | struct intel_connector *intel_connector) | |
2939 | { | |
2940 | intel_panel_info(m, &intel_connector->panel); | |
2941 | } | |
2942 | ||
2943 | static void intel_connector_info(struct seq_file *m, | |
2944 | struct drm_connector *connector) | |
2945 | { | |
2946 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2947 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2948 | struct drm_display_mode *mode; |
53f5e3ca JB |
2949 | |
2950 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2951 | connector->base.id, connector->name, |
53f5e3ca JB |
2952 | drm_get_connector_status_name(connector->status)); |
2953 | if (connector->status == connector_status_connected) { | |
2954 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2955 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2956 | connector->display_info.width_mm, | |
2957 | connector->display_info.height_mm); | |
2958 | seq_printf(m, "\tsubpixel order: %s\n", | |
2959 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2960 | seq_printf(m, "\tCEA rev: %d\n", | |
2961 | connector->display_info.cea_rev); | |
2962 | } | |
36cd7444 DA |
2963 | if (intel_encoder) { |
2964 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2965 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2966 | intel_dp_info(m, intel_connector); | |
2967 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2968 | intel_hdmi_info(m, intel_connector); | |
2969 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2970 | intel_lvds_info(m, intel_connector); | |
3d52ccf5 LY |
2971 | else if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
2972 | intel_dp_mst_info(m, intel_connector); | |
36cd7444 | 2973 | } |
53f5e3ca | 2974 | |
f103fc7d JB |
2975 | seq_printf(m, "\tmodes:\n"); |
2976 | list_for_each_entry(mode, &connector->modes, head) | |
2977 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2978 | } |
2979 | ||
065f2ec2 CW |
2980 | static bool cursor_active(struct drm_device *dev, int pipe) |
2981 | { | |
2982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2983 | u32 state; | |
2984 | ||
2985 | if (IS_845G(dev) || IS_I865G(dev)) | |
0b87c24e | 2986 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 2987 | else |
5efb3e28 | 2988 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2989 | |
2990 | return state; | |
2991 | } | |
2992 | ||
2993 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2994 | { | |
2995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2996 | u32 pos; | |
2997 | ||
5efb3e28 | 2998 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2999 | |
3000 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
3001 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
3002 | *x = -*x; | |
3003 | ||
3004 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
3005 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
3006 | *y = -*y; | |
3007 | ||
3008 | return cursor_active(dev, pipe); | |
3009 | } | |
3010 | ||
3abc4e09 RF |
3011 | static const char *plane_type(enum drm_plane_type type) |
3012 | { | |
3013 | switch (type) { | |
3014 | case DRM_PLANE_TYPE_OVERLAY: | |
3015 | return "OVL"; | |
3016 | case DRM_PLANE_TYPE_PRIMARY: | |
3017 | return "PRI"; | |
3018 | case DRM_PLANE_TYPE_CURSOR: | |
3019 | return "CUR"; | |
3020 | /* | |
3021 | * Deliberately omitting default: to generate compiler warnings | |
3022 | * when a new drm_plane_type gets added. | |
3023 | */ | |
3024 | } | |
3025 | ||
3026 | return "unknown"; | |
3027 | } | |
3028 | ||
3029 | static const char *plane_rotation(unsigned int rotation) | |
3030 | { | |
3031 | static char buf[48]; | |
3032 | /* | |
3033 | * According to doc only one DRM_ROTATE_ is allowed but this | |
3034 | * will print them all to visualize if the values are misused | |
3035 | */ | |
3036 | snprintf(buf, sizeof(buf), | |
3037 | "%s%s%s%s%s%s(0x%08x)", | |
3038 | (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "", | |
3039 | (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "", | |
3040 | (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "", | |
3041 | (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "", | |
3042 | (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "", | |
3043 | (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "", | |
3044 | rotation); | |
3045 | ||
3046 | return buf; | |
3047 | } | |
3048 | ||
3049 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3050 | { | |
3051 | struct drm_info_node *node = m->private; | |
3052 | struct drm_device *dev = node->minor->dev; | |
3053 | struct intel_plane *intel_plane; | |
3054 | ||
3055 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3056 | struct drm_plane_state *state; | |
3057 | struct drm_plane *plane = &intel_plane->base; | |
3058 | ||
3059 | if (!plane->state) { | |
3060 | seq_puts(m, "plane->state is NULL!\n"); | |
3061 | continue; | |
3062 | } | |
3063 | ||
3064 | state = plane->state; | |
3065 | ||
3066 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", | |
3067 | plane->base.id, | |
3068 | plane_type(intel_plane->base.type), | |
3069 | state->crtc_x, state->crtc_y, | |
3070 | state->crtc_w, state->crtc_h, | |
3071 | (state->src_x >> 16), | |
3072 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3073 | (state->src_y >> 16), | |
3074 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3075 | (state->src_w >> 16), | |
3076 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3077 | (state->src_h >> 16), | |
3078 | ((state->src_h & 0xffff) * 15625) >> 10, | |
3079 | state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A", | |
3080 | plane_rotation(state->rotation)); | |
3081 | } | |
3082 | } | |
3083 | ||
3084 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3085 | { | |
3086 | struct intel_crtc_state *pipe_config; | |
3087 | int num_scalers = intel_crtc->num_scalers; | |
3088 | int i; | |
3089 | ||
3090 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3091 | ||
3092 | /* Not all platformas have a scaler */ | |
3093 | if (num_scalers) { | |
3094 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3095 | num_scalers, | |
3096 | pipe_config->scaler_state.scaler_users, | |
3097 | pipe_config->scaler_state.scaler_id); | |
3098 | ||
3099 | for (i = 0; i < SKL_NUM_SCALERS; i++) { | |
3100 | struct intel_scaler *sc = | |
3101 | &pipe_config->scaler_state.scalers[i]; | |
3102 | ||
3103 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3104 | i, yesno(sc->in_use), sc->mode); | |
3105 | } | |
3106 | seq_puts(m, "\n"); | |
3107 | } else { | |
3108 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3109 | } | |
3110 | } | |
3111 | ||
53f5e3ca JB |
3112 | static int i915_display_info(struct seq_file *m, void *unused) |
3113 | { | |
9f25d007 | 3114 | struct drm_info_node *node = m->private; |
53f5e3ca | 3115 | struct drm_device *dev = node->minor->dev; |
b0e5ddf3 | 3116 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 3117 | struct intel_crtc *crtc; |
53f5e3ca JB |
3118 | struct drm_connector *connector; |
3119 | ||
b0e5ddf3 | 3120 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3121 | drm_modeset_lock_all(dev); |
3122 | seq_printf(m, "CRTC info\n"); | |
3123 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3124 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3125 | bool active; |
f77076c9 | 3126 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3127 | int x, y; |
53f5e3ca | 3128 | |
f77076c9 ML |
3129 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3130 | ||
3abc4e09 | 3131 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3132 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3133 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3134 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3135 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3136 | ||
f77076c9 | 3137 | if (pipe_config->base.active) { |
065f2ec2 CW |
3138 | intel_crtc_info(m, crtc); |
3139 | ||
a23dc658 | 3140 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 3141 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3142 | yesno(crtc->cursor_base), |
3dd512fb MR |
3143 | x, y, crtc->base.cursor->state->crtc_w, |
3144 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3145 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3146 | intel_scaler_info(m, crtc); |
3147 | intel_plane_info(m, crtc); | |
a23dc658 | 3148 | } |
cace841c DV |
3149 | |
3150 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3151 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3152 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3153 | } |
3154 | ||
3155 | seq_printf(m, "\n"); | |
3156 | seq_printf(m, "Connector info\n"); | |
3157 | seq_printf(m, "--------------\n"); | |
3158 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3159 | intel_connector_info(m, connector); | |
3160 | } | |
3161 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3162 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3163 | |
3164 | return 0; | |
3165 | } | |
3166 | ||
e04934cf BW |
3167 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3168 | { | |
3169 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3170 | struct drm_device *dev = node->minor->dev; | |
3171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 3172 | struct intel_engine_cs *engine; |
e04934cf | 3173 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); |
c3232b18 DG |
3174 | enum intel_engine_id id; |
3175 | int j, ret; | |
e04934cf BW |
3176 | |
3177 | if (!i915_semaphore_is_enabled(dev)) { | |
3178 | seq_puts(m, "Semaphores are disabled\n"); | |
3179 | return 0; | |
3180 | } | |
3181 | ||
3182 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3183 | if (ret) | |
3184 | return ret; | |
03872064 | 3185 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
3186 | |
3187 | if (IS_BROADWELL(dev)) { | |
3188 | struct page *page; | |
3189 | uint64_t *seqno; | |
3190 | ||
3191 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
3192 | ||
3193 | seqno = (uint64_t *)kmap_atomic(page); | |
c3232b18 | 3194 | for_each_engine_id(engine, dev_priv, id) { |
e04934cf BW |
3195 | uint64_t offset; |
3196 | ||
e2f80391 | 3197 | seq_printf(m, "%s\n", engine->name); |
e04934cf BW |
3198 | |
3199 | seq_puts(m, " Last signal:"); | |
3200 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3201 | offset = id * I915_NUM_ENGINES + j; |
e04934cf BW |
3202 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3203 | seqno[offset], offset * 8); | |
3204 | } | |
3205 | seq_putc(m, '\n'); | |
3206 | ||
3207 | seq_puts(m, " Last wait: "); | |
3208 | for (j = 0; j < num_rings; j++) { | |
c3232b18 | 3209 | offset = id + (j * I915_NUM_ENGINES); |
e04934cf BW |
3210 | seq_printf(m, "0x%08llx (0x%02llx) ", |
3211 | seqno[offset], offset * 8); | |
3212 | } | |
3213 | seq_putc(m, '\n'); | |
3214 | ||
3215 | } | |
3216 | kunmap_atomic(seqno); | |
3217 | } else { | |
3218 | seq_puts(m, " Last signal:"); | |
b4ac5afc | 3219 | for_each_engine(engine, dev_priv) |
e04934cf BW |
3220 | for (j = 0; j < num_rings; j++) |
3221 | seq_printf(m, "0x%08x\n", | |
e2f80391 | 3222 | I915_READ(engine->semaphore.mbox.signal[j])); |
e04934cf BW |
3223 | seq_putc(m, '\n'); |
3224 | } | |
3225 | ||
3226 | seq_puts(m, "\nSync seqno:\n"); | |
b4ac5afc DG |
3227 | for_each_engine(engine, dev_priv) { |
3228 | for (j = 0; j < num_rings; j++) | |
e2f80391 TU |
3229 | seq_printf(m, " 0x%08x ", |
3230 | engine->semaphore.sync_seqno[j]); | |
e04934cf BW |
3231 | seq_putc(m, '\n'); |
3232 | } | |
3233 | seq_putc(m, '\n'); | |
3234 | ||
03872064 | 3235 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3236 | mutex_unlock(&dev->struct_mutex); |
3237 | return 0; | |
3238 | } | |
3239 | ||
728e29d7 DV |
3240 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3241 | { | |
3242 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3243 | struct drm_device *dev = node->minor->dev; | |
3244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3245 | int i; | |
3246 | ||
3247 | drm_modeset_lock_all(dev); | |
3248 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3249 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3250 | ||
3251 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
2dd66ebd ML |
3252 | seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", |
3253 | pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); | |
728e29d7 | 3254 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3255 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3256 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3257 | pll->config.hw_state.dpll_md); | |
3258 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3259 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3260 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3261 | } |
3262 | drm_modeset_unlock_all(dev); | |
3263 | ||
3264 | return 0; | |
3265 | } | |
3266 | ||
1ed1ef9d | 3267 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3268 | { |
3269 | int i; | |
3270 | int ret; | |
e2f80391 | 3271 | struct intel_engine_cs *engine; |
888b5995 AS |
3272 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
3273 | struct drm_device *dev = node->minor->dev; | |
3274 | struct drm_i915_private *dev_priv = dev->dev_private; | |
33136b06 | 3275 | struct i915_workarounds *workarounds = &dev_priv->workarounds; |
c3232b18 | 3276 | enum intel_engine_id id; |
888b5995 | 3277 | |
888b5995 AS |
3278 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3279 | if (ret) | |
3280 | return ret; | |
3281 | ||
3282 | intel_runtime_pm_get(dev_priv); | |
3283 | ||
33136b06 | 3284 | seq_printf(m, "Workarounds applied: %d\n", workarounds->count); |
c3232b18 | 3285 | for_each_engine_id(engine, dev_priv, id) |
33136b06 | 3286 | seq_printf(m, "HW whitelist count for %s: %d\n", |
c3232b18 | 3287 | engine->name, workarounds->hw_whitelist_count[id]); |
33136b06 | 3288 | for (i = 0; i < workarounds->count; ++i) { |
f0f59a00 VS |
3289 | i915_reg_t addr; |
3290 | u32 mask, value, read; | |
2fa60f6d | 3291 | bool ok; |
888b5995 | 3292 | |
33136b06 AS |
3293 | addr = workarounds->reg[i].addr; |
3294 | mask = workarounds->reg[i].mask; | |
3295 | value = workarounds->reg[i].value; | |
2fa60f6d MK |
3296 | read = I915_READ(addr); |
3297 | ok = (value & mask) == (read & mask); | |
3298 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3299 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3300 | } |
3301 | ||
3302 | intel_runtime_pm_put(dev_priv); | |
3303 | mutex_unlock(&dev->struct_mutex); | |
3304 | ||
3305 | return 0; | |
3306 | } | |
3307 | ||
c5511e44 DL |
3308 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3309 | { | |
3310 | struct drm_info_node *node = m->private; | |
3311 | struct drm_device *dev = node->minor->dev; | |
3312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3313 | struct skl_ddb_allocation *ddb; | |
3314 | struct skl_ddb_entry *entry; | |
3315 | enum pipe pipe; | |
3316 | int plane; | |
3317 | ||
2fcffe19 DL |
3318 | if (INTEL_INFO(dev)->gen < 9) |
3319 | return 0; | |
3320 | ||
c5511e44 DL |
3321 | drm_modeset_lock_all(dev); |
3322 | ||
3323 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3324 | ||
3325 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3326 | ||
3327 | for_each_pipe(dev_priv, pipe) { | |
3328 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3329 | ||
dd740780 | 3330 | for_each_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3331 | entry = &ddb->plane[pipe][plane]; |
3332 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3333 | entry->start, entry->end, | |
3334 | skl_ddb_entry_size(entry)); | |
3335 | } | |
3336 | ||
4969d33e | 3337 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3338 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3339 | entry->end, skl_ddb_entry_size(entry)); | |
3340 | } | |
3341 | ||
3342 | drm_modeset_unlock_all(dev); | |
3343 | ||
3344 | return 0; | |
3345 | } | |
3346 | ||
a54746e3 VK |
3347 | static void drrs_status_per_crtc(struct seq_file *m, |
3348 | struct drm_device *dev, struct intel_crtc *intel_crtc) | |
3349 | { | |
3350 | struct intel_encoder *intel_encoder; | |
3351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3352 | struct i915_drrs *drrs = &dev_priv->drrs; | |
3353 | int vrefresh = 0; | |
3354 | ||
3355 | for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { | |
3356 | /* Encoder connected on this CRTC */ | |
3357 | switch (intel_encoder->type) { | |
3358 | case INTEL_OUTPUT_EDP: | |
3359 | seq_puts(m, "eDP:\n"); | |
3360 | break; | |
3361 | case INTEL_OUTPUT_DSI: | |
3362 | seq_puts(m, "DSI:\n"); | |
3363 | break; | |
3364 | case INTEL_OUTPUT_HDMI: | |
3365 | seq_puts(m, "HDMI:\n"); | |
3366 | break; | |
3367 | case INTEL_OUTPUT_DISPLAYPORT: | |
3368 | seq_puts(m, "DP:\n"); | |
3369 | break; | |
3370 | default: | |
3371 | seq_printf(m, "Other encoder (id=%d).\n", | |
3372 | intel_encoder->type); | |
3373 | return; | |
3374 | } | |
3375 | } | |
3376 | ||
3377 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3378 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3379 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3380 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3381 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3382 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3383 | else | |
3384 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3385 | ||
3386 | seq_puts(m, "\n\n"); | |
3387 | ||
f77076c9 | 3388 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3389 | struct intel_panel *panel; |
3390 | ||
3391 | mutex_lock(&drrs->mutex); | |
3392 | /* DRRS Supported */ | |
3393 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3394 | ||
3395 | /* disable_drrs() will make drrs->dp NULL */ | |
3396 | if (!drrs->dp) { | |
3397 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3398 | mutex_unlock(&drrs->mutex); | |
3399 | return; | |
3400 | } | |
3401 | ||
3402 | panel = &drrs->dp->attached_connector->panel; | |
3403 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3404 | drrs->busy_frontbuffer_bits); | |
3405 | ||
3406 | seq_puts(m, "\n\t\t"); | |
3407 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3408 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3409 | vrefresh = panel->fixed_mode->vrefresh; | |
3410 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3411 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3412 | vrefresh = panel->downclock_mode->vrefresh; | |
3413 | } else { | |
3414 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3415 | drrs->refresh_rate_type); | |
3416 | mutex_unlock(&drrs->mutex); | |
3417 | return; | |
3418 | } | |
3419 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3420 | ||
3421 | seq_puts(m, "\n\t\t"); | |
3422 | mutex_unlock(&drrs->mutex); | |
3423 | } else { | |
3424 | /* DRRS not supported. Print the VBT parameter*/ | |
3425 | seq_puts(m, "\tDRRS Supported : No"); | |
3426 | } | |
3427 | seq_puts(m, "\n"); | |
3428 | } | |
3429 | ||
3430 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3431 | { | |
3432 | struct drm_info_node *node = m->private; | |
3433 | struct drm_device *dev = node->minor->dev; | |
3434 | struct intel_crtc *intel_crtc; | |
3435 | int active_crtc_cnt = 0; | |
3436 | ||
3437 | for_each_intel_crtc(dev, intel_crtc) { | |
3438 | drm_modeset_lock(&intel_crtc->base.mutex, NULL); | |
3439 | ||
f77076c9 | 3440 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3441 | active_crtc_cnt++; |
3442 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3443 | ||
3444 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3445 | } | |
3446 | ||
3447 | drm_modeset_unlock(&intel_crtc->base.mutex); | |
3448 | } | |
3449 | ||
3450 | if (!active_crtc_cnt) | |
3451 | seq_puts(m, "No active crtc found\n"); | |
3452 | ||
3453 | return 0; | |
3454 | } | |
3455 | ||
07144428 DL |
3456 | struct pipe_crc_info { |
3457 | const char *name; | |
3458 | struct drm_device *dev; | |
3459 | enum pipe pipe; | |
3460 | }; | |
3461 | ||
11bed958 DA |
3462 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3463 | { | |
3464 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3465 | struct drm_device *dev = node->minor->dev; | |
3466 | struct drm_encoder *encoder; | |
3467 | struct intel_encoder *intel_encoder; | |
3468 | struct intel_digital_port *intel_dig_port; | |
3469 | drm_modeset_lock_all(dev); | |
3470 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
3471 | intel_encoder = to_intel_encoder(encoder); | |
3472 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) | |
3473 | continue; | |
3474 | intel_dig_port = enc_to_dig_port(encoder); | |
3475 | if (!intel_dig_port->dp.can_mst) | |
3476 | continue; | |
3477 | ||
3478 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); | |
3479 | } | |
3480 | drm_modeset_unlock_all(dev); | |
3481 | return 0; | |
3482 | } | |
3483 | ||
07144428 DL |
3484 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3485 | { | |
be5c7a90 DL |
3486 | struct pipe_crc_info *info = inode->i_private; |
3487 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3488 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3489 | ||
7eb1c496 DV |
3490 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
3491 | return -ENODEV; | |
3492 | ||
d538bbdf DL |
3493 | spin_lock_irq(&pipe_crc->lock); |
3494 | ||
3495 | if (pipe_crc->opened) { | |
3496 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3497 | return -EBUSY; /* already open */ |
3498 | } | |
3499 | ||
d538bbdf | 3500 | pipe_crc->opened = true; |
07144428 DL |
3501 | filep->private_data = inode->i_private; |
3502 | ||
d538bbdf DL |
3503 | spin_unlock_irq(&pipe_crc->lock); |
3504 | ||
07144428 DL |
3505 | return 0; |
3506 | } | |
3507 | ||
3508 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3509 | { | |
be5c7a90 DL |
3510 | struct pipe_crc_info *info = inode->i_private; |
3511 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3512 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3513 | ||
d538bbdf DL |
3514 | spin_lock_irq(&pipe_crc->lock); |
3515 | pipe_crc->opened = false; | |
3516 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3517 | |
07144428 DL |
3518 | return 0; |
3519 | } | |
3520 | ||
3521 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3522 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3523 | /* account for \'0' */ | |
3524 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3525 | ||
3526 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3527 | { |
d538bbdf DL |
3528 | assert_spin_locked(&pipe_crc->lock); |
3529 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3530 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3531 | } |
3532 | ||
3533 | static ssize_t | |
3534 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3535 | loff_t *pos) | |
3536 | { | |
3537 | struct pipe_crc_info *info = filep->private_data; | |
3538 | struct drm_device *dev = info->dev; | |
3539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3540 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3541 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3542 | int n_entries; |
07144428 DL |
3543 | ssize_t bytes_read; |
3544 | ||
3545 | /* | |
3546 | * Don't allow user space to provide buffers not big enough to hold | |
3547 | * a line of data. | |
3548 | */ | |
3549 | if (count < PIPE_CRC_LINE_LEN) | |
3550 | return -EINVAL; | |
3551 | ||
3552 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3553 | return 0; |
07144428 DL |
3554 | |
3555 | /* nothing to read */ | |
d538bbdf | 3556 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3557 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3558 | int ret; |
3559 | ||
3560 | if (filep->f_flags & O_NONBLOCK) { | |
3561 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3562 | return -EAGAIN; |
d538bbdf | 3563 | } |
07144428 | 3564 | |
d538bbdf DL |
3565 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3566 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3567 | if (ret) { | |
3568 | spin_unlock_irq(&pipe_crc->lock); | |
3569 | return ret; | |
3570 | } | |
8bf1e9f1 SH |
3571 | } |
3572 | ||
07144428 | 3573 | /* We now have one or more entries to read */ |
9ad6d99f | 3574 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3575 | |
07144428 | 3576 | bytes_read = 0; |
9ad6d99f VS |
3577 | while (n_entries > 0) { |
3578 | struct intel_pipe_crc_entry *entry = | |
3579 | &pipe_crc->entries[pipe_crc->tail]; | |
07144428 | 3580 | int ret; |
8bf1e9f1 | 3581 | |
9ad6d99f VS |
3582 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3583 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3584 | break; | |
3585 | ||
3586 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3587 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3588 | ||
07144428 DL |
3589 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3590 | "%8u %8x %8x %8x %8x %8x\n", | |
3591 | entry->frame, entry->crc[0], | |
3592 | entry->crc[1], entry->crc[2], | |
3593 | entry->crc[3], entry->crc[4]); | |
3594 | ||
9ad6d99f VS |
3595 | spin_unlock_irq(&pipe_crc->lock); |
3596 | ||
3597 | ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); | |
07144428 DL |
3598 | if (ret == PIPE_CRC_LINE_LEN) |
3599 | return -EFAULT; | |
b2c88f5b | 3600 | |
9ad6d99f VS |
3601 | user_buf += PIPE_CRC_LINE_LEN; |
3602 | n_entries--; | |
3603 | ||
3604 | spin_lock_irq(&pipe_crc->lock); | |
3605 | } | |
8bf1e9f1 | 3606 | |
d538bbdf DL |
3607 | spin_unlock_irq(&pipe_crc->lock); |
3608 | ||
07144428 DL |
3609 | return bytes_read; |
3610 | } | |
3611 | ||
3612 | static const struct file_operations i915_pipe_crc_fops = { | |
3613 | .owner = THIS_MODULE, | |
3614 | .open = i915_pipe_crc_open, | |
3615 | .read = i915_pipe_crc_read, | |
3616 | .release = i915_pipe_crc_release, | |
3617 | }; | |
3618 | ||
3619 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3620 | { | |
3621 | .name = "i915_pipe_A_crc", | |
3622 | .pipe = PIPE_A, | |
3623 | }, | |
3624 | { | |
3625 | .name = "i915_pipe_B_crc", | |
3626 | .pipe = PIPE_B, | |
3627 | }, | |
3628 | { | |
3629 | .name = "i915_pipe_C_crc", | |
3630 | .pipe = PIPE_C, | |
3631 | }, | |
3632 | }; | |
3633 | ||
3634 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3635 | enum pipe pipe) | |
3636 | { | |
3637 | struct drm_device *dev = minor->dev; | |
3638 | struct dentry *ent; | |
3639 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3640 | ||
3641 | info->dev = dev; | |
3642 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
3643 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3644 | if (!ent) |
3645 | return -ENOMEM; | |
07144428 DL |
3646 | |
3647 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3648 | } |
3649 | ||
e8dfcf78 | 3650 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3651 | "none", |
3652 | "plane1", | |
3653 | "plane2", | |
3654 | "pf", | |
5b3a856b | 3655 | "pipe", |
3d099a05 DV |
3656 | "TV", |
3657 | "DP-B", | |
3658 | "DP-C", | |
3659 | "DP-D", | |
46a19188 | 3660 | "auto", |
926321d5 DV |
3661 | }; |
3662 | ||
3663 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3664 | { | |
3665 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3666 | return pipe_crc_sources[source]; | |
3667 | } | |
3668 | ||
bd9db02f | 3669 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
3670 | { |
3671 | struct drm_device *dev = m->private; | |
3672 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3673 | int i; | |
3674 | ||
3675 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3676 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3677 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3678 | ||
3679 | return 0; | |
3680 | } | |
3681 | ||
bd9db02f | 3682 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
3683 | { |
3684 | struct drm_device *dev = inode->i_private; | |
3685 | ||
bd9db02f | 3686 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
3687 | } |
3688 | ||
46a19188 | 3689 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3690 | uint32_t *val) |
3691 | { | |
46a19188 DV |
3692 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3693 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3694 | ||
3695 | switch (*source) { | |
52f843f6 DV |
3696 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3697 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3698 | break; | |
3699 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3700 | *val = 0; | |
3701 | break; | |
3702 | default: | |
3703 | return -EINVAL; | |
3704 | } | |
3705 | ||
3706 | return 0; | |
3707 | } | |
3708 | ||
46a19188 DV |
3709 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
3710 | enum intel_pipe_crc_source *source) | |
3711 | { | |
3712 | struct intel_encoder *encoder; | |
3713 | struct intel_crtc *crtc; | |
26756809 | 3714 | struct intel_digital_port *dig_port; |
46a19188 DV |
3715 | int ret = 0; |
3716 | ||
3717 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3718 | ||
6e9f798d | 3719 | drm_modeset_lock_all(dev); |
b2784e15 | 3720 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3721 | if (!encoder->base.crtc) |
3722 | continue; | |
3723 | ||
3724 | crtc = to_intel_crtc(encoder->base.crtc); | |
3725 | ||
3726 | if (crtc->pipe != pipe) | |
3727 | continue; | |
3728 | ||
3729 | switch (encoder->type) { | |
3730 | case INTEL_OUTPUT_TVOUT: | |
3731 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3732 | break; | |
3733 | case INTEL_OUTPUT_DISPLAYPORT: | |
3734 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
3735 | dig_port = enc_to_dig_port(&encoder->base); |
3736 | switch (dig_port->port) { | |
3737 | case PORT_B: | |
3738 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3739 | break; | |
3740 | case PORT_C: | |
3741 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3742 | break; | |
3743 | case PORT_D: | |
3744 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3745 | break; | |
3746 | default: | |
3747 | WARN(1, "nonexisting DP port %c\n", | |
3748 | port_name(dig_port->port)); | |
3749 | break; | |
3750 | } | |
46a19188 | 3751 | break; |
6847d71b PZ |
3752 | default: |
3753 | break; | |
46a19188 DV |
3754 | } |
3755 | } | |
6e9f798d | 3756 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3757 | |
3758 | return ret; | |
3759 | } | |
3760 | ||
3761 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
3762 | enum pipe pipe, | |
3763 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3764 | uint32_t *val) |
3765 | { | |
8d2f24ca DV |
3766 | struct drm_i915_private *dev_priv = dev->dev_private; |
3767 | bool need_stable_symbols = false; | |
3768 | ||
46a19188 DV |
3769 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3770 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3771 | if (ret) | |
3772 | return ret; | |
3773 | } | |
3774 | ||
3775 | switch (*source) { | |
7ac0129b DV |
3776 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3777 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3778 | break; | |
3779 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3780 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3781 | need_stable_symbols = true; |
7ac0129b DV |
3782 | break; |
3783 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3784 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3785 | need_stable_symbols = true; |
7ac0129b | 3786 | break; |
2be57922 VS |
3787 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
3788 | if (!IS_CHERRYVIEW(dev)) | |
3789 | return -EINVAL; | |
3790 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3791 | need_stable_symbols = true; | |
3792 | break; | |
7ac0129b DV |
3793 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3794 | *val = 0; | |
3795 | break; | |
3796 | default: | |
3797 | return -EINVAL; | |
3798 | } | |
3799 | ||
8d2f24ca DV |
3800 | /* |
3801 | * When the pipe CRC tap point is after the transcoders we need | |
3802 | * to tweak symbol-level features to produce a deterministic series of | |
3803 | * symbols for a given frame. We need to reset those features only once | |
3804 | * a frame (instead of every nth symbol): | |
3805 | * - DC-balance: used to ensure a better clock recovery from the data | |
3806 | * link (SDVO) | |
3807 | * - DisplayPort scrambling: used for EMI reduction | |
3808 | */ | |
3809 | if (need_stable_symbols) { | |
3810 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3811 | ||
8d2f24ca | 3812 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3813 | switch (pipe) { |
3814 | case PIPE_A: | |
8d2f24ca | 3815 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3816 | break; |
3817 | case PIPE_B: | |
8d2f24ca | 3818 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3819 | break; |
3820 | case PIPE_C: | |
3821 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3822 | break; | |
3823 | default: | |
3824 | return -EINVAL; | |
3825 | } | |
8d2f24ca DV |
3826 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3827 | } | |
3828 | ||
7ac0129b DV |
3829 | return 0; |
3830 | } | |
3831 | ||
4b79ebf7 | 3832 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
3833 | enum pipe pipe, |
3834 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3835 | uint32_t *val) |
3836 | { | |
84093603 DV |
3837 | struct drm_i915_private *dev_priv = dev->dev_private; |
3838 | bool need_stable_symbols = false; | |
3839 | ||
46a19188 DV |
3840 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3841 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3842 | if (ret) | |
3843 | return ret; | |
3844 | } | |
3845 | ||
3846 | switch (*source) { | |
4b79ebf7 DV |
3847 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3848 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3849 | break; | |
3850 | case INTEL_PIPE_CRC_SOURCE_TV: | |
3851 | if (!SUPPORTS_TV(dev)) | |
3852 | return -EINVAL; | |
3853 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3854 | break; | |
3855 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3856 | if (!IS_G4X(dev)) | |
3857 | return -EINVAL; | |
3858 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3859 | need_stable_symbols = true; |
4b79ebf7 DV |
3860 | break; |
3861 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3862 | if (!IS_G4X(dev)) | |
3863 | return -EINVAL; | |
3864 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3865 | need_stable_symbols = true; |
4b79ebf7 DV |
3866 | break; |
3867 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
3868 | if (!IS_G4X(dev)) | |
3869 | return -EINVAL; | |
3870 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3871 | need_stable_symbols = true; |
4b79ebf7 DV |
3872 | break; |
3873 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3874 | *val = 0; | |
3875 | break; | |
3876 | default: | |
3877 | return -EINVAL; | |
3878 | } | |
3879 | ||
84093603 DV |
3880 | /* |
3881 | * When the pipe CRC tap point is after the transcoders we need | |
3882 | * to tweak symbol-level features to produce a deterministic series of | |
3883 | * symbols for a given frame. We need to reset those features only once | |
3884 | * a frame (instead of every nth symbol): | |
3885 | * - DC-balance: used to ensure a better clock recovery from the data | |
3886 | * link (SDVO) | |
3887 | * - DisplayPort scrambling: used for EMI reduction | |
3888 | */ | |
3889 | if (need_stable_symbols) { | |
3890 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3891 | ||
3892 | WARN_ON(!IS_G4X(dev)); | |
3893 | ||
3894 | I915_WRITE(PORT_DFT_I9XX, | |
3895 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3896 | ||
3897 | if (pipe == PIPE_A) | |
3898 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3899 | else | |
3900 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3901 | ||
3902 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3903 | } | |
3904 | ||
4b79ebf7 DV |
3905 | return 0; |
3906 | } | |
3907 | ||
8d2f24ca DV |
3908 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
3909 | enum pipe pipe) | |
3910 | { | |
3911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3912 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3913 | ||
eb736679 VS |
3914 | switch (pipe) { |
3915 | case PIPE_A: | |
8d2f24ca | 3916 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3917 | break; |
3918 | case PIPE_B: | |
8d2f24ca | 3919 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3920 | break; |
3921 | case PIPE_C: | |
3922 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3923 | break; | |
3924 | default: | |
3925 | return; | |
3926 | } | |
8d2f24ca DV |
3927 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3928 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3929 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3930 | ||
3931 | } | |
3932 | ||
84093603 DV |
3933 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
3934 | enum pipe pipe) | |
3935 | { | |
3936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3937 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3938 | ||
3939 | if (pipe == PIPE_A) | |
3940 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3941 | else | |
3942 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3943 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3944 | ||
3945 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3946 | I915_WRITE(PORT_DFT_I9XX, | |
3947 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3948 | } | |
3949 | } | |
3950 | ||
46a19188 | 3951 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3952 | uint32_t *val) |
3953 | { | |
46a19188 DV |
3954 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3955 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3956 | ||
3957 | switch (*source) { | |
5b3a856b DV |
3958 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3959 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
3960 | break; | |
3961 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3962 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
3963 | break; | |
5b3a856b DV |
3964 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3965 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
3966 | break; | |
3d099a05 | 3967 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3968 | *val = 0; |
3969 | break; | |
3d099a05 DV |
3970 | default: |
3971 | return -EINVAL; | |
5b3a856b DV |
3972 | } |
3973 | ||
3974 | return 0; | |
3975 | } | |
3976 | ||
c4e2d043 | 3977 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable) |
fabf6e51 DV |
3978 | { |
3979 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3980 | struct intel_crtc *crtc = | |
3981 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 3982 | struct intel_crtc_state *pipe_config; |
c4e2d043 ML |
3983 | struct drm_atomic_state *state; |
3984 | int ret = 0; | |
fabf6e51 DV |
3985 | |
3986 | drm_modeset_lock_all(dev); | |
c4e2d043 ML |
3987 | state = drm_atomic_state_alloc(dev); |
3988 | if (!state) { | |
3989 | ret = -ENOMEM; | |
3990 | goto out; | |
fabf6e51 | 3991 | } |
fabf6e51 | 3992 | |
c4e2d043 ML |
3993 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
3994 | pipe_config = intel_atomic_get_crtc_state(state, crtc); | |
3995 | if (IS_ERR(pipe_config)) { | |
3996 | ret = PTR_ERR(pipe_config); | |
3997 | goto out; | |
3998 | } | |
fabf6e51 | 3999 | |
c4e2d043 ML |
4000 | pipe_config->pch_pfit.force_thru = enable; |
4001 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
4002 | pipe_config->pch_pfit.enabled != enable) | |
4003 | pipe_config->base.connectors_changed = true; | |
1b509259 | 4004 | |
c4e2d043 ML |
4005 | ret = drm_atomic_commit(state); |
4006 | out: | |
fabf6e51 | 4007 | drm_modeset_unlock_all(dev); |
c4e2d043 ML |
4008 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
4009 | if (ret) | |
4010 | drm_atomic_state_free(state); | |
fabf6e51 DV |
4011 | } |
4012 | ||
4013 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
4014 | enum pipe pipe, | |
4015 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
4016 | uint32_t *val) |
4017 | { | |
46a19188 DV |
4018 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
4019 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
4020 | ||
4021 | switch (*source) { | |
5b3a856b DV |
4022 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
4023 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
4024 | break; | |
4025 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
4026 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
4027 | break; | |
4028 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 | 4029 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4030 | hsw_trans_edp_pipe_A_crc_wa(dev, true); |
fabf6e51 | 4031 | |
5b3a856b DV |
4032 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
4033 | break; | |
3d099a05 | 4034 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
4035 | *val = 0; |
4036 | break; | |
3d099a05 DV |
4037 | default: |
4038 | return -EINVAL; | |
5b3a856b DV |
4039 | } |
4040 | ||
4041 | return 0; | |
4042 | } | |
4043 | ||
926321d5 DV |
4044 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
4045 | enum intel_pipe_crc_source source) | |
4046 | { | |
4047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 4048 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
8c740dce PZ |
4049 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
4050 | pipe)); | |
e129649b | 4051 | enum intel_display_power_domain power_domain; |
432f3342 | 4052 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 4053 | int ret; |
926321d5 | 4054 | |
cc3da175 DL |
4055 | if (pipe_crc->source == source) |
4056 | return 0; | |
4057 | ||
ae676fcd DL |
4058 | /* forbid changing the source without going back to 'none' */ |
4059 | if (pipe_crc->source && source) | |
4060 | return -EINVAL; | |
4061 | ||
e129649b ID |
4062 | power_domain = POWER_DOMAIN_PIPE(pipe); |
4063 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
9d8b0588 DV |
4064 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); |
4065 | return -EIO; | |
4066 | } | |
4067 | ||
52f843f6 | 4068 | if (IS_GEN2(dev)) |
46a19188 | 4069 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 4070 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 4071 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
666a4537 | 4072 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
fabf6e51 | 4073 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 4074 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 4075 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 4076 | else |
fabf6e51 | 4077 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
4078 | |
4079 | if (ret != 0) | |
e129649b | 4080 | goto out; |
5b3a856b | 4081 | |
4b584369 DL |
4082 | /* none -> real source transition */ |
4083 | if (source) { | |
4252fbc3 VS |
4084 | struct intel_pipe_crc_entry *entries; |
4085 | ||
7cd6ccff DL |
4086 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
4087 | pipe_name(pipe), pipe_crc_source_name(source)); | |
4088 | ||
3cf54b34 VS |
4089 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
4090 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 | 4091 | GFP_KERNEL); |
e129649b ID |
4092 | if (!entries) { |
4093 | ret = -ENOMEM; | |
4094 | goto out; | |
4095 | } | |
e5f75aca | 4096 | |
8c740dce PZ |
4097 | /* |
4098 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
4099 | * enabled and disabled dynamically based on package C states, | |
4100 | * user space can't make reliable use of the CRCs, so let's just | |
4101 | * completely disable it. | |
4102 | */ | |
4103 | hsw_disable_ips(crtc); | |
4104 | ||
d538bbdf | 4105 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 4106 | kfree(pipe_crc->entries); |
4252fbc3 | 4107 | pipe_crc->entries = entries; |
d538bbdf DL |
4108 | pipe_crc->head = 0; |
4109 | pipe_crc->tail = 0; | |
4110 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
4111 | } |
4112 | ||
cc3da175 | 4113 | pipe_crc->source = source; |
926321d5 | 4114 | |
926321d5 DV |
4115 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
4116 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
4117 | ||
e5f75aca DL |
4118 | /* real source -> none transition */ |
4119 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 4120 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
4121 | struct intel_crtc *crtc = |
4122 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 4123 | |
7cd6ccff DL |
4124 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
4125 | pipe_name(pipe)); | |
4126 | ||
a33d7105 | 4127 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 4128 | if (crtc->base.state->active) |
a33d7105 DV |
4129 | intel_wait_for_vblank(dev, pipe); |
4130 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 4131 | |
d538bbdf DL |
4132 | spin_lock_irq(&pipe_crc->lock); |
4133 | entries = pipe_crc->entries; | |
e5f75aca | 4134 | pipe_crc->entries = NULL; |
9ad6d99f VS |
4135 | pipe_crc->head = 0; |
4136 | pipe_crc->tail = 0; | |
d538bbdf DL |
4137 | spin_unlock_irq(&pipe_crc->lock); |
4138 | ||
4139 | kfree(entries); | |
84093603 DV |
4140 | |
4141 | if (IS_G4X(dev)) | |
4142 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
666a4537 | 4143 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
8d2f24ca | 4144 | vlv_undo_pipe_scramble_reset(dev, pipe); |
fabf6e51 | 4145 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4146 | hsw_trans_edp_pipe_A_crc_wa(dev, false); |
8c740dce PZ |
4147 | |
4148 | hsw_enable_ips(crtc); | |
e5f75aca DL |
4149 | } |
4150 | ||
e129649b ID |
4151 | ret = 0; |
4152 | ||
4153 | out: | |
4154 | intel_display_power_put(dev_priv, power_domain); | |
4155 | ||
4156 | return ret; | |
926321d5 DV |
4157 | } |
4158 | ||
4159 | /* | |
4160 | * Parse pipe CRC command strings: | |
b94dec87 DL |
4161 | * command: wsp* object wsp+ name wsp+ source wsp* |
4162 | * object: 'pipe' | |
4163 | * name: (A | B | C) | |
926321d5 DV |
4164 | * source: (none | plane1 | plane2 | pf) |
4165 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
4166 | * | |
4167 | * eg.: | |
b94dec87 DL |
4168 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
4169 | * "pipe A none" -> Stop CRC | |
926321d5 | 4170 | */ |
bd9db02f | 4171 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
4172 | { |
4173 | int n_words = 0; | |
4174 | ||
4175 | while (*buf) { | |
4176 | char *end; | |
4177 | ||
4178 | /* skip leading white space */ | |
4179 | buf = skip_spaces(buf); | |
4180 | if (!*buf) | |
4181 | break; /* end of buffer */ | |
4182 | ||
4183 | /* find end of word */ | |
4184 | for (end = buf; *end && !isspace(*end); end++) | |
4185 | ; | |
4186 | ||
4187 | if (n_words == max_words) { | |
4188 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
4189 | max_words); | |
4190 | return -EINVAL; /* ran out of words[] before bytes */ | |
4191 | } | |
4192 | ||
4193 | if (*end) | |
4194 | *end++ = '\0'; | |
4195 | words[n_words++] = buf; | |
4196 | buf = end; | |
4197 | } | |
4198 | ||
4199 | return n_words; | |
4200 | } | |
4201 | ||
b94dec87 DL |
4202 | enum intel_pipe_crc_object { |
4203 | PIPE_CRC_OBJECT_PIPE, | |
4204 | }; | |
4205 | ||
e8dfcf78 | 4206 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
4207 | "pipe", |
4208 | }; | |
4209 | ||
4210 | static int | |
bd9db02f | 4211 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
4212 | { |
4213 | int i; | |
4214 | ||
4215 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
4216 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 4217 | *o = i; |
b94dec87 DL |
4218 | return 0; |
4219 | } | |
4220 | ||
4221 | return -EINVAL; | |
4222 | } | |
4223 | ||
bd9db02f | 4224 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
4225 | { |
4226 | const char name = buf[0]; | |
4227 | ||
4228 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
4229 | return -EINVAL; | |
4230 | ||
4231 | *pipe = name - 'A'; | |
4232 | ||
4233 | return 0; | |
4234 | } | |
4235 | ||
4236 | static int | |
bd9db02f | 4237 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
4238 | { |
4239 | int i; | |
4240 | ||
4241 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
4242 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 4243 | *s = i; |
926321d5 DV |
4244 | return 0; |
4245 | } | |
4246 | ||
4247 | return -EINVAL; | |
4248 | } | |
4249 | ||
bd9db02f | 4250 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 4251 | { |
b94dec87 | 4252 | #define N_WORDS 3 |
926321d5 | 4253 | int n_words; |
b94dec87 | 4254 | char *words[N_WORDS]; |
926321d5 | 4255 | enum pipe pipe; |
b94dec87 | 4256 | enum intel_pipe_crc_object object; |
926321d5 DV |
4257 | enum intel_pipe_crc_source source; |
4258 | ||
bd9db02f | 4259 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
4260 | if (n_words != N_WORDS) { |
4261 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
4262 | N_WORDS); | |
4263 | return -EINVAL; | |
4264 | } | |
4265 | ||
bd9db02f | 4266 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 4267 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
4268 | return -EINVAL; |
4269 | } | |
4270 | ||
bd9db02f | 4271 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 4272 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
4273 | return -EINVAL; |
4274 | } | |
4275 | ||
bd9db02f | 4276 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 4277 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
4278 | return -EINVAL; |
4279 | } | |
4280 | ||
4281 | return pipe_crc_set_source(dev, pipe, source); | |
4282 | } | |
4283 | ||
bd9db02f DL |
4284 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
4285 | size_t len, loff_t *offp) | |
926321d5 DV |
4286 | { |
4287 | struct seq_file *m = file->private_data; | |
4288 | struct drm_device *dev = m->private; | |
4289 | char *tmpbuf; | |
4290 | int ret; | |
4291 | ||
4292 | if (len == 0) | |
4293 | return 0; | |
4294 | ||
4295 | if (len > PAGE_SIZE - 1) { | |
4296 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
4297 | PAGE_SIZE); | |
4298 | return -E2BIG; | |
4299 | } | |
4300 | ||
4301 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
4302 | if (!tmpbuf) | |
4303 | return -ENOMEM; | |
4304 | ||
4305 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
4306 | ret = -EFAULT; | |
4307 | goto out; | |
4308 | } | |
4309 | tmpbuf[len] = '\0'; | |
4310 | ||
bd9db02f | 4311 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
4312 | |
4313 | out: | |
4314 | kfree(tmpbuf); | |
4315 | if (ret < 0) | |
4316 | return ret; | |
4317 | ||
4318 | *offp += len; | |
4319 | return len; | |
4320 | } | |
4321 | ||
bd9db02f | 4322 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4323 | .owner = THIS_MODULE, |
bd9db02f | 4324 | .open = display_crc_ctl_open, |
926321d5 DV |
4325 | .read = seq_read, |
4326 | .llseek = seq_lseek, | |
4327 | .release = single_release, | |
bd9db02f | 4328 | .write = display_crc_ctl_write |
926321d5 DV |
4329 | }; |
4330 | ||
eb3394fa TP |
4331 | static ssize_t i915_displayport_test_active_write(struct file *file, |
4332 | const char __user *ubuf, | |
4333 | size_t len, loff_t *offp) | |
4334 | { | |
4335 | char *input_buffer; | |
4336 | int status = 0; | |
eb3394fa TP |
4337 | struct drm_device *dev; |
4338 | struct drm_connector *connector; | |
4339 | struct list_head *connector_list; | |
4340 | struct intel_dp *intel_dp; | |
4341 | int val = 0; | |
4342 | ||
9aaffa34 | 4343 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 4344 | |
eb3394fa TP |
4345 | connector_list = &dev->mode_config.connector_list; |
4346 | ||
4347 | if (len == 0) | |
4348 | return 0; | |
4349 | ||
4350 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4351 | if (!input_buffer) | |
4352 | return -ENOMEM; | |
4353 | ||
4354 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4355 | status = -EFAULT; | |
4356 | goto out; | |
4357 | } | |
4358 | ||
4359 | input_buffer[len] = '\0'; | |
4360 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4361 | ||
4362 | list_for_each_entry(connector, connector_list, head) { | |
4363 | ||
4364 | if (connector->connector_type != | |
4365 | DRM_MODE_CONNECTOR_DisplayPort) | |
4366 | continue; | |
4367 | ||
b8bb08ec | 4368 | if (connector->status == connector_status_connected && |
eb3394fa TP |
4369 | connector->encoder != NULL) { |
4370 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4371 | status = kstrtoint(input_buffer, 10, &val); | |
4372 | if (status < 0) | |
4373 | goto out; | |
4374 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4375 | /* To prevent erroneous activation of the compliance | |
4376 | * testing code, only accept an actual value of 1 here | |
4377 | */ | |
4378 | if (val == 1) | |
4379 | intel_dp->compliance_test_active = 1; | |
4380 | else | |
4381 | intel_dp->compliance_test_active = 0; | |
4382 | } | |
4383 | } | |
4384 | out: | |
4385 | kfree(input_buffer); | |
4386 | if (status < 0) | |
4387 | return status; | |
4388 | ||
4389 | *offp += len; | |
4390 | return len; | |
4391 | } | |
4392 | ||
4393 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4394 | { | |
4395 | struct drm_device *dev = m->private; | |
4396 | struct drm_connector *connector; | |
4397 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4398 | struct intel_dp *intel_dp; | |
4399 | ||
eb3394fa TP |
4400 | list_for_each_entry(connector, connector_list, head) { |
4401 | ||
4402 | if (connector->connector_type != | |
4403 | DRM_MODE_CONNECTOR_DisplayPort) | |
4404 | continue; | |
4405 | ||
4406 | if (connector->status == connector_status_connected && | |
4407 | connector->encoder != NULL) { | |
4408 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4409 | if (intel_dp->compliance_test_active) | |
4410 | seq_puts(m, "1"); | |
4411 | else | |
4412 | seq_puts(m, "0"); | |
4413 | } else | |
4414 | seq_puts(m, "0"); | |
4415 | } | |
4416 | ||
4417 | return 0; | |
4418 | } | |
4419 | ||
4420 | static int i915_displayport_test_active_open(struct inode *inode, | |
4421 | struct file *file) | |
4422 | { | |
4423 | struct drm_device *dev = inode->i_private; | |
4424 | ||
4425 | return single_open(file, i915_displayport_test_active_show, dev); | |
4426 | } | |
4427 | ||
4428 | static const struct file_operations i915_displayport_test_active_fops = { | |
4429 | .owner = THIS_MODULE, | |
4430 | .open = i915_displayport_test_active_open, | |
4431 | .read = seq_read, | |
4432 | .llseek = seq_lseek, | |
4433 | .release = single_release, | |
4434 | .write = i915_displayport_test_active_write | |
4435 | }; | |
4436 | ||
4437 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4438 | { | |
4439 | struct drm_device *dev = m->private; | |
4440 | struct drm_connector *connector; | |
4441 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4442 | struct intel_dp *intel_dp; | |
4443 | ||
eb3394fa TP |
4444 | list_for_each_entry(connector, connector_list, head) { |
4445 | ||
4446 | if (connector->connector_type != | |
4447 | DRM_MODE_CONNECTOR_DisplayPort) | |
4448 | continue; | |
4449 | ||
4450 | if (connector->status == connector_status_connected && | |
4451 | connector->encoder != NULL) { | |
4452 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4453 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4454 | } else | |
4455 | seq_puts(m, "0"); | |
4456 | } | |
4457 | ||
4458 | return 0; | |
4459 | } | |
4460 | static int i915_displayport_test_data_open(struct inode *inode, | |
4461 | struct file *file) | |
4462 | { | |
4463 | struct drm_device *dev = inode->i_private; | |
4464 | ||
4465 | return single_open(file, i915_displayport_test_data_show, dev); | |
4466 | } | |
4467 | ||
4468 | static const struct file_operations i915_displayport_test_data_fops = { | |
4469 | .owner = THIS_MODULE, | |
4470 | .open = i915_displayport_test_data_open, | |
4471 | .read = seq_read, | |
4472 | .llseek = seq_lseek, | |
4473 | .release = single_release | |
4474 | }; | |
4475 | ||
4476 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4477 | { | |
4478 | struct drm_device *dev = m->private; | |
4479 | struct drm_connector *connector; | |
4480 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4481 | struct intel_dp *intel_dp; | |
4482 | ||
eb3394fa TP |
4483 | list_for_each_entry(connector, connector_list, head) { |
4484 | ||
4485 | if (connector->connector_type != | |
4486 | DRM_MODE_CONNECTOR_DisplayPort) | |
4487 | continue; | |
4488 | ||
4489 | if (connector->status == connector_status_connected && | |
4490 | connector->encoder != NULL) { | |
4491 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4492 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4493 | } else | |
4494 | seq_puts(m, "0"); | |
4495 | } | |
4496 | ||
4497 | return 0; | |
4498 | } | |
4499 | ||
4500 | static int i915_displayport_test_type_open(struct inode *inode, | |
4501 | struct file *file) | |
4502 | { | |
4503 | struct drm_device *dev = inode->i_private; | |
4504 | ||
4505 | return single_open(file, i915_displayport_test_type_show, dev); | |
4506 | } | |
4507 | ||
4508 | static const struct file_operations i915_displayport_test_type_fops = { | |
4509 | .owner = THIS_MODULE, | |
4510 | .open = i915_displayport_test_type_open, | |
4511 | .read = seq_read, | |
4512 | .llseek = seq_lseek, | |
4513 | .release = single_release | |
4514 | }; | |
4515 | ||
97e94b22 | 4516 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 VS |
4517 | { |
4518 | struct drm_device *dev = m->private; | |
369a1342 | 4519 | int level; |
de38b95c VS |
4520 | int num_levels; |
4521 | ||
4522 | if (IS_CHERRYVIEW(dev)) | |
4523 | num_levels = 3; | |
4524 | else if (IS_VALLEYVIEW(dev)) | |
4525 | num_levels = 1; | |
4526 | else | |
4527 | num_levels = ilk_wm_max_level(dev) + 1; | |
369a1342 VS |
4528 | |
4529 | drm_modeset_lock_all(dev); | |
4530 | ||
4531 | for (level = 0; level < num_levels; level++) { | |
4532 | unsigned int latency = wm[level]; | |
4533 | ||
97e94b22 DL |
4534 | /* |
4535 | * - WM1+ latency values in 0.5us units | |
de38b95c | 4536 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 4537 | */ |
666a4537 WB |
4538 | if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) || |
4539 | IS_CHERRYVIEW(dev)) | |
97e94b22 DL |
4540 | latency *= 10; |
4541 | else if (level > 0) | |
369a1342 VS |
4542 | latency *= 5; |
4543 | ||
4544 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4545 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4546 | } |
4547 | ||
4548 | drm_modeset_unlock_all(dev); | |
4549 | } | |
4550 | ||
4551 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4552 | { | |
4553 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4554 | struct drm_i915_private *dev_priv = dev->dev_private; |
4555 | const uint16_t *latencies; | |
4556 | ||
4557 | if (INTEL_INFO(dev)->gen >= 9) | |
4558 | latencies = dev_priv->wm.skl_latency; | |
4559 | else | |
4560 | latencies = to_i915(dev)->wm.pri_latency; | |
369a1342 | 4561 | |
97e94b22 | 4562 | wm_latency_show(m, latencies); |
369a1342 VS |
4563 | |
4564 | return 0; | |
4565 | } | |
4566 | ||
4567 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4568 | { | |
4569 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4570 | struct drm_i915_private *dev_priv = dev->dev_private; |
4571 | const uint16_t *latencies; | |
4572 | ||
4573 | if (INTEL_INFO(dev)->gen >= 9) | |
4574 | latencies = dev_priv->wm.skl_latency; | |
4575 | else | |
4576 | latencies = to_i915(dev)->wm.spr_latency; | |
369a1342 | 4577 | |
97e94b22 | 4578 | wm_latency_show(m, latencies); |
369a1342 VS |
4579 | |
4580 | return 0; | |
4581 | } | |
4582 | ||
4583 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4584 | { | |
4585 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4586 | struct drm_i915_private *dev_priv = dev->dev_private; |
4587 | const uint16_t *latencies; | |
4588 | ||
4589 | if (INTEL_INFO(dev)->gen >= 9) | |
4590 | latencies = dev_priv->wm.skl_latency; | |
4591 | else | |
4592 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4593 | |
97e94b22 | 4594 | wm_latency_show(m, latencies); |
369a1342 VS |
4595 | |
4596 | return 0; | |
4597 | } | |
4598 | ||
4599 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4600 | { | |
4601 | struct drm_device *dev = inode->i_private; | |
4602 | ||
de38b95c | 4603 | if (INTEL_INFO(dev)->gen < 5) |
369a1342 VS |
4604 | return -ENODEV; |
4605 | ||
4606 | return single_open(file, pri_wm_latency_show, dev); | |
4607 | } | |
4608 | ||
4609 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4610 | { | |
4611 | struct drm_device *dev = inode->i_private; | |
4612 | ||
9ad0257c | 4613 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4614 | return -ENODEV; |
4615 | ||
4616 | return single_open(file, spr_wm_latency_show, dev); | |
4617 | } | |
4618 | ||
4619 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4620 | { | |
4621 | struct drm_device *dev = inode->i_private; | |
4622 | ||
9ad0257c | 4623 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4624 | return -ENODEV; |
4625 | ||
4626 | return single_open(file, cur_wm_latency_show, dev); | |
4627 | } | |
4628 | ||
4629 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4630 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4631 | { |
4632 | struct seq_file *m = file->private_data; | |
4633 | struct drm_device *dev = m->private; | |
97e94b22 | 4634 | uint16_t new[8] = { 0 }; |
de38b95c | 4635 | int num_levels; |
369a1342 VS |
4636 | int level; |
4637 | int ret; | |
4638 | char tmp[32]; | |
4639 | ||
de38b95c VS |
4640 | if (IS_CHERRYVIEW(dev)) |
4641 | num_levels = 3; | |
4642 | else if (IS_VALLEYVIEW(dev)) | |
4643 | num_levels = 1; | |
4644 | else | |
4645 | num_levels = ilk_wm_max_level(dev) + 1; | |
4646 | ||
369a1342 VS |
4647 | if (len >= sizeof(tmp)) |
4648 | return -EINVAL; | |
4649 | ||
4650 | if (copy_from_user(tmp, ubuf, len)) | |
4651 | return -EFAULT; | |
4652 | ||
4653 | tmp[len] = '\0'; | |
4654 | ||
97e94b22 DL |
4655 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4656 | &new[0], &new[1], &new[2], &new[3], | |
4657 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4658 | if (ret != num_levels) |
4659 | return -EINVAL; | |
4660 | ||
4661 | drm_modeset_lock_all(dev); | |
4662 | ||
4663 | for (level = 0; level < num_levels; level++) | |
4664 | wm[level] = new[level]; | |
4665 | ||
4666 | drm_modeset_unlock_all(dev); | |
4667 | ||
4668 | return len; | |
4669 | } | |
4670 | ||
4671 | ||
4672 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4673 | size_t len, loff_t *offp) | |
4674 | { | |
4675 | struct seq_file *m = file->private_data; | |
4676 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4677 | struct drm_i915_private *dev_priv = dev->dev_private; |
4678 | uint16_t *latencies; | |
369a1342 | 4679 | |
97e94b22 DL |
4680 | if (INTEL_INFO(dev)->gen >= 9) |
4681 | latencies = dev_priv->wm.skl_latency; | |
4682 | else | |
4683 | latencies = to_i915(dev)->wm.pri_latency; | |
4684 | ||
4685 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4686 | } |
4687 | ||
4688 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4689 | size_t len, loff_t *offp) | |
4690 | { | |
4691 | struct seq_file *m = file->private_data; | |
4692 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4693 | struct drm_i915_private *dev_priv = dev->dev_private; |
4694 | uint16_t *latencies; | |
369a1342 | 4695 | |
97e94b22 DL |
4696 | if (INTEL_INFO(dev)->gen >= 9) |
4697 | latencies = dev_priv->wm.skl_latency; | |
4698 | else | |
4699 | latencies = to_i915(dev)->wm.spr_latency; | |
4700 | ||
4701 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4702 | } |
4703 | ||
4704 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4705 | size_t len, loff_t *offp) | |
4706 | { | |
4707 | struct seq_file *m = file->private_data; | |
4708 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4709 | struct drm_i915_private *dev_priv = dev->dev_private; |
4710 | uint16_t *latencies; | |
4711 | ||
4712 | if (INTEL_INFO(dev)->gen >= 9) | |
4713 | latencies = dev_priv->wm.skl_latency; | |
4714 | else | |
4715 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4716 | |
97e94b22 | 4717 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4718 | } |
4719 | ||
4720 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4721 | .owner = THIS_MODULE, | |
4722 | .open = pri_wm_latency_open, | |
4723 | .read = seq_read, | |
4724 | .llseek = seq_lseek, | |
4725 | .release = single_release, | |
4726 | .write = pri_wm_latency_write | |
4727 | }; | |
4728 | ||
4729 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4730 | .owner = THIS_MODULE, | |
4731 | .open = spr_wm_latency_open, | |
4732 | .read = seq_read, | |
4733 | .llseek = seq_lseek, | |
4734 | .release = single_release, | |
4735 | .write = spr_wm_latency_write | |
4736 | }; | |
4737 | ||
4738 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4739 | .owner = THIS_MODULE, | |
4740 | .open = cur_wm_latency_open, | |
4741 | .read = seq_read, | |
4742 | .llseek = seq_lseek, | |
4743 | .release = single_release, | |
4744 | .write = cur_wm_latency_write | |
4745 | }; | |
4746 | ||
647416f9 KC |
4747 | static int |
4748 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4749 | { |
647416f9 | 4750 | struct drm_device *dev = data; |
e277a1f8 | 4751 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 4752 | |
d98c52cf | 4753 | *val = i915_terminally_wedged(&dev_priv->gpu_error); |
f3cd474b | 4754 | |
647416f9 | 4755 | return 0; |
f3cd474b CW |
4756 | } |
4757 | ||
647416f9 KC |
4758 | static int |
4759 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4760 | { |
647416f9 | 4761 | struct drm_device *dev = data; |
d46c0517 ID |
4762 | struct drm_i915_private *dev_priv = dev->dev_private; |
4763 | ||
b8d24a06 MK |
4764 | /* |
4765 | * There is no safeguard against this debugfs entry colliding | |
4766 | * with the hangcheck calling same i915_handle_error() in | |
4767 | * parallel, causing an explosion. For now we assume that the | |
4768 | * test harness is responsible enough not to inject gpu hangs | |
4769 | * while it is writing to 'i915_wedged' | |
4770 | */ | |
4771 | ||
d98c52cf | 4772 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
b8d24a06 MK |
4773 | return -EAGAIN; |
4774 | ||
d46c0517 | 4775 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 4776 | |
58174462 MK |
4777 | i915_handle_error(dev, val, |
4778 | "Manually setting wedged to %llu", val); | |
d46c0517 ID |
4779 | |
4780 | intel_runtime_pm_put(dev_priv); | |
4781 | ||
647416f9 | 4782 | return 0; |
f3cd474b CW |
4783 | } |
4784 | ||
647416f9 KC |
4785 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4786 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4787 | "%llu\n"); |
f3cd474b | 4788 | |
647416f9 KC |
4789 | static int |
4790 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 4791 | { |
647416f9 | 4792 | struct drm_device *dev = data; |
e277a1f8 | 4793 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 4794 | |
647416f9 | 4795 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 4796 | |
647416f9 | 4797 | return 0; |
e5eb3d63 DV |
4798 | } |
4799 | ||
647416f9 KC |
4800 | static int |
4801 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 4802 | { |
647416f9 | 4803 | struct drm_device *dev = data; |
e5eb3d63 | 4804 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4805 | int ret; |
e5eb3d63 | 4806 | |
647416f9 | 4807 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 4808 | |
22bcfc6a DV |
4809 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4810 | if (ret) | |
4811 | return ret; | |
4812 | ||
99584db3 | 4813 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
4814 | mutex_unlock(&dev->struct_mutex); |
4815 | ||
647416f9 | 4816 | return 0; |
e5eb3d63 DV |
4817 | } |
4818 | ||
647416f9 KC |
4819 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
4820 | i915_ring_stop_get, i915_ring_stop_set, | |
4821 | "0x%08llx\n"); | |
d5442303 | 4822 | |
094f9a54 CW |
4823 | static int |
4824 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4825 | { | |
4826 | struct drm_device *dev = data; | |
4827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4828 | ||
4829 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4830 | return 0; | |
4831 | } | |
4832 | ||
4833 | static int | |
4834 | i915_ring_missed_irq_set(void *data, u64 val) | |
4835 | { | |
4836 | struct drm_device *dev = data; | |
4837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4838 | int ret; | |
4839 | ||
4840 | /* Lock against concurrent debugfs callers */ | |
4841 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4842 | if (ret) | |
4843 | return ret; | |
4844 | dev_priv->gpu_error.missed_irq_rings = val; | |
4845 | mutex_unlock(&dev->struct_mutex); | |
4846 | ||
4847 | return 0; | |
4848 | } | |
4849 | ||
4850 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4851 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4852 | "0x%08llx\n"); | |
4853 | ||
4854 | static int | |
4855 | i915_ring_test_irq_get(void *data, u64 *val) | |
4856 | { | |
4857 | struct drm_device *dev = data; | |
4858 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4859 | ||
4860 | *val = dev_priv->gpu_error.test_irq_rings; | |
4861 | ||
4862 | return 0; | |
4863 | } | |
4864 | ||
4865 | static int | |
4866 | i915_ring_test_irq_set(void *data, u64 val) | |
4867 | { | |
4868 | struct drm_device *dev = data; | |
4869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4870 | int ret; | |
4871 | ||
4872 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
4873 | ||
4874 | /* Lock against concurrent debugfs callers */ | |
4875 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4876 | if (ret) | |
4877 | return ret; | |
4878 | ||
4879 | dev_priv->gpu_error.test_irq_rings = val; | |
4880 | mutex_unlock(&dev->struct_mutex); | |
4881 | ||
4882 | return 0; | |
4883 | } | |
4884 | ||
4885 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4886 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4887 | "0x%08llx\n"); | |
4888 | ||
dd624afd CW |
4889 | #define DROP_UNBOUND 0x1 |
4890 | #define DROP_BOUND 0x2 | |
4891 | #define DROP_RETIRE 0x4 | |
4892 | #define DROP_ACTIVE 0x8 | |
4893 | #define DROP_ALL (DROP_UNBOUND | \ | |
4894 | DROP_BOUND | \ | |
4895 | DROP_RETIRE | \ | |
4896 | DROP_ACTIVE) | |
647416f9 KC |
4897 | static int |
4898 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4899 | { |
647416f9 | 4900 | *val = DROP_ALL; |
dd624afd | 4901 | |
647416f9 | 4902 | return 0; |
dd624afd CW |
4903 | } |
4904 | ||
647416f9 KC |
4905 | static int |
4906 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4907 | { |
647416f9 | 4908 | struct drm_device *dev = data; |
dd624afd | 4909 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4910 | int ret; |
dd624afd | 4911 | |
2f9fe5ff | 4912 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4913 | |
4914 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4915 | * on ioctls on -EAGAIN. */ | |
4916 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4917 | if (ret) | |
4918 | return ret; | |
4919 | ||
4920 | if (val & DROP_ACTIVE) { | |
4921 | ret = i915_gpu_idle(dev); | |
4922 | if (ret) | |
4923 | goto unlock; | |
4924 | } | |
4925 | ||
4926 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
4927 | i915_gem_retire_requests(dev); | |
4928 | ||
21ab4e74 CW |
4929 | if (val & DROP_BOUND) |
4930 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4931 | |
21ab4e74 CW |
4932 | if (val & DROP_UNBOUND) |
4933 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4934 | |
4935 | unlock: | |
4936 | mutex_unlock(&dev->struct_mutex); | |
4937 | ||
647416f9 | 4938 | return ret; |
dd624afd CW |
4939 | } |
4940 | ||
647416f9 KC |
4941 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4942 | i915_drop_caches_get, i915_drop_caches_set, | |
4943 | "0x%08llx\n"); | |
dd624afd | 4944 | |
647416f9 KC |
4945 | static int |
4946 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4947 | { |
647416f9 | 4948 | struct drm_device *dev = data; |
e277a1f8 | 4949 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4950 | int ret; |
004777cb | 4951 | |
daa3afb2 | 4952 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4953 | return -ENODEV; |
4954 | ||
5c9669ce TR |
4955 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4956 | ||
4fc688ce | 4957 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4958 | if (ret) |
4959 | return ret; | |
358733e9 | 4960 | |
7c59a9c1 | 4961 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
4fc688ce | 4962 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4963 | |
647416f9 | 4964 | return 0; |
358733e9 JB |
4965 | } |
4966 | ||
647416f9 KC |
4967 | static int |
4968 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4969 | { |
647416f9 | 4970 | struct drm_device *dev = data; |
358733e9 | 4971 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 4972 | u32 hw_max, hw_min; |
647416f9 | 4973 | int ret; |
004777cb | 4974 | |
daa3afb2 | 4975 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4976 | return -ENODEV; |
358733e9 | 4977 | |
5c9669ce TR |
4978 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4979 | ||
647416f9 | 4980 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4981 | |
4fc688ce | 4982 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4983 | if (ret) |
4984 | return ret; | |
4985 | ||
358733e9 JB |
4986 | /* |
4987 | * Turbo will still be enabled, but won't go above the set value. | |
4988 | */ | |
bc4d91f6 | 4989 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4990 | |
bc4d91f6 AG |
4991 | hw_max = dev_priv->rps.max_freq; |
4992 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4993 | |
b39fb297 | 4994 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4995 | mutex_unlock(&dev_priv->rps.hw_lock); |
4996 | return -EINVAL; | |
0a073b84 JB |
4997 | } |
4998 | ||
b39fb297 | 4999 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 5000 | |
ffe02b40 | 5001 | intel_set_rps(dev, val); |
dd0a1aa1 | 5002 | |
4fc688ce | 5003 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 5004 | |
647416f9 | 5005 | return 0; |
358733e9 JB |
5006 | } |
5007 | ||
647416f9 KC |
5008 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
5009 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 5010 | "%llu\n"); |
358733e9 | 5011 | |
647416f9 KC |
5012 | static int |
5013 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 5014 | { |
647416f9 | 5015 | struct drm_device *dev = data; |
e277a1f8 | 5016 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 5017 | int ret; |
004777cb | 5018 | |
daa3afb2 | 5019 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
5020 | return -ENODEV; |
5021 | ||
5c9669ce TR |
5022 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
5023 | ||
4fc688ce | 5024 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5025 | if (ret) |
5026 | return ret; | |
1523c310 | 5027 | |
7c59a9c1 | 5028 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
4fc688ce | 5029 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 5030 | |
647416f9 | 5031 | return 0; |
1523c310 JB |
5032 | } |
5033 | ||
647416f9 KC |
5034 | static int |
5035 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 5036 | { |
647416f9 | 5037 | struct drm_device *dev = data; |
1523c310 | 5038 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 5039 | u32 hw_max, hw_min; |
647416f9 | 5040 | int ret; |
004777cb | 5041 | |
daa3afb2 | 5042 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 5043 | return -ENODEV; |
1523c310 | 5044 | |
5c9669ce TR |
5045 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
5046 | ||
647416f9 | 5047 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 5048 | |
4fc688ce | 5049 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
5050 | if (ret) |
5051 | return ret; | |
5052 | ||
1523c310 JB |
5053 | /* |
5054 | * Turbo will still be enabled, but won't go below the set value. | |
5055 | */ | |
bc4d91f6 | 5056 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 5057 | |
bc4d91f6 AG |
5058 | hw_max = dev_priv->rps.max_freq; |
5059 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 5060 | |
b39fb297 | 5061 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
5062 | mutex_unlock(&dev_priv->rps.hw_lock); |
5063 | return -EINVAL; | |
0a073b84 | 5064 | } |
dd0a1aa1 | 5065 | |
b39fb297 | 5066 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 5067 | |
ffe02b40 | 5068 | intel_set_rps(dev, val); |
dd0a1aa1 | 5069 | |
4fc688ce | 5070 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 5071 | |
647416f9 | 5072 | return 0; |
1523c310 JB |
5073 | } |
5074 | ||
647416f9 KC |
5075 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
5076 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 5077 | "%llu\n"); |
1523c310 | 5078 | |
647416f9 KC |
5079 | static int |
5080 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 5081 | { |
647416f9 | 5082 | struct drm_device *dev = data; |
e277a1f8 | 5083 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 5084 | u32 snpcr; |
647416f9 | 5085 | int ret; |
07b7ddd9 | 5086 | |
004777cb DV |
5087 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5088 | return -ENODEV; | |
5089 | ||
22bcfc6a DV |
5090 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
5091 | if (ret) | |
5092 | return ret; | |
c8c8fb33 | 5093 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 5094 | |
07b7ddd9 | 5095 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
5096 | |
5097 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
5098 | mutex_unlock(&dev_priv->dev->struct_mutex); |
5099 | ||
647416f9 | 5100 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 5101 | |
647416f9 | 5102 | return 0; |
07b7ddd9 JB |
5103 | } |
5104 | ||
647416f9 KC |
5105 | static int |
5106 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 5107 | { |
647416f9 | 5108 | struct drm_device *dev = data; |
07b7ddd9 | 5109 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 5110 | u32 snpcr; |
07b7ddd9 | 5111 | |
004777cb DV |
5112 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5113 | return -ENODEV; | |
5114 | ||
647416f9 | 5115 | if (val > 3) |
07b7ddd9 JB |
5116 | return -EINVAL; |
5117 | ||
c8c8fb33 | 5118 | intel_runtime_pm_get(dev_priv); |
647416f9 | 5119 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
5120 | |
5121 | /* Update the cache sharing policy here as well */ | |
5122 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
5123 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5124 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
5125 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
5126 | ||
c8c8fb33 | 5127 | intel_runtime_pm_put(dev_priv); |
647416f9 | 5128 | return 0; |
07b7ddd9 JB |
5129 | } |
5130 | ||
647416f9 KC |
5131 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
5132 | i915_cache_sharing_get, i915_cache_sharing_set, | |
5133 | "%llu\n"); | |
07b7ddd9 | 5134 | |
5d39525a JM |
5135 | struct sseu_dev_status { |
5136 | unsigned int slice_total; | |
5137 | unsigned int subslice_total; | |
5138 | unsigned int subslice_per_slice; | |
5139 | unsigned int eu_total; | |
5140 | unsigned int eu_per_subslice; | |
5141 | }; | |
5142 | ||
5143 | static void cherryview_sseu_device_status(struct drm_device *dev, | |
5144 | struct sseu_dev_status *stat) | |
5145 | { | |
5146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0a0b457f | 5147 | int ss_max = 2; |
5d39525a JM |
5148 | int ss; |
5149 | u32 sig1[ss_max], sig2[ss_max]; | |
5150 | ||
5151 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
5152 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
5153 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
5154 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
5155 | ||
5156 | for (ss = 0; ss < ss_max; ss++) { | |
5157 | unsigned int eu_cnt; | |
5158 | ||
5159 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
5160 | /* skip disabled subslice */ | |
5161 | continue; | |
5162 | ||
5163 | stat->slice_total = 1; | |
5164 | stat->subslice_per_slice++; | |
5165 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + | |
5166 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
5167 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
5168 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
5169 | stat->eu_total += eu_cnt; | |
5170 | stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); | |
5171 | } | |
5172 | stat->subslice_total = stat->subslice_per_slice; | |
5173 | } | |
5174 | ||
5175 | static void gen9_sseu_device_status(struct drm_device *dev, | |
5176 | struct sseu_dev_status *stat) | |
5177 | { | |
5178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1c046bc1 | 5179 | int s_max = 3, ss_max = 4; |
5d39525a JM |
5180 | int s, ss; |
5181 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
5182 | ||
1c046bc1 JM |
5183 | /* BXT has a single slice and at most 3 subslices. */ |
5184 | if (IS_BROXTON(dev)) { | |
5185 | s_max = 1; | |
5186 | ss_max = 3; | |
5187 | } | |
5188 | ||
5189 | for (s = 0; s < s_max; s++) { | |
5190 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
5191 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
5192 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
5193 | } | |
5194 | ||
5d39525a JM |
5195 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
5196 | GEN9_PGCTL_SSA_EU19_ACK | | |
5197 | GEN9_PGCTL_SSA_EU210_ACK | | |
5198 | GEN9_PGCTL_SSA_EU311_ACK; | |
5199 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
5200 | GEN9_PGCTL_SSB_EU19_ACK | | |
5201 | GEN9_PGCTL_SSB_EU210_ACK | | |
5202 | GEN9_PGCTL_SSB_EU311_ACK; | |
5203 | ||
5204 | for (s = 0; s < s_max; s++) { | |
1c046bc1 JM |
5205 | unsigned int ss_cnt = 0; |
5206 | ||
5d39525a JM |
5207 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) |
5208 | /* skip disabled slice */ | |
5209 | continue; | |
5210 | ||
5211 | stat->slice_total++; | |
1c046bc1 | 5212 | |
ef11bdb3 | 5213 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1c046bc1 JM |
5214 | ss_cnt = INTEL_INFO(dev)->subslice_per_slice; |
5215 | ||
5d39525a JM |
5216 | for (ss = 0; ss < ss_max; ss++) { |
5217 | unsigned int eu_cnt; | |
5218 | ||
1c046bc1 JM |
5219 | if (IS_BROXTON(dev) && |
5220 | !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
5221 | /* skip disabled subslice */ | |
5222 | continue; | |
5223 | ||
5224 | if (IS_BROXTON(dev)) | |
5225 | ss_cnt++; | |
5226 | ||
5d39525a JM |
5227 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
5228 | eu_mask[ss%2]); | |
5229 | stat->eu_total += eu_cnt; | |
5230 | stat->eu_per_subslice = max(stat->eu_per_subslice, | |
5231 | eu_cnt); | |
5232 | } | |
1c046bc1 JM |
5233 | |
5234 | stat->subslice_total += ss_cnt; | |
5235 | stat->subslice_per_slice = max(stat->subslice_per_slice, | |
5236 | ss_cnt); | |
5d39525a JM |
5237 | } |
5238 | } | |
5239 | ||
91bedd34 ŁD |
5240 | static void broadwell_sseu_device_status(struct drm_device *dev, |
5241 | struct sseu_dev_status *stat) | |
5242 | { | |
5243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5244 | int s; | |
5245 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); | |
5246 | ||
5247 | stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); | |
5248 | ||
5249 | if (stat->slice_total) { | |
5250 | stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; | |
5251 | stat->subslice_total = stat->slice_total * | |
5252 | stat->subslice_per_slice; | |
5253 | stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice; | |
5254 | stat->eu_total = stat->eu_per_subslice * stat->subslice_total; | |
5255 | ||
5256 | /* subtract fused off EU(s) from enabled slice(s) */ | |
5257 | for (s = 0; s < stat->slice_total; s++) { | |
5258 | u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s]; | |
5259 | ||
5260 | stat->eu_total -= hweight8(subslice_7eu); | |
5261 | } | |
5262 | } | |
5263 | } | |
5264 | ||
3873218f JM |
5265 | static int i915_sseu_status(struct seq_file *m, void *unused) |
5266 | { | |
5267 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
5268 | struct drm_device *dev = node->minor->dev; | |
5d39525a | 5269 | struct sseu_dev_status stat; |
3873218f | 5270 | |
91bedd34 | 5271 | if (INTEL_INFO(dev)->gen < 8) |
3873218f JM |
5272 | return -ENODEV; |
5273 | ||
5274 | seq_puts(m, "SSEU Device Info\n"); | |
5275 | seq_printf(m, " Available Slice Total: %u\n", | |
5276 | INTEL_INFO(dev)->slice_total); | |
5277 | seq_printf(m, " Available Subslice Total: %u\n", | |
5278 | INTEL_INFO(dev)->subslice_total); | |
5279 | seq_printf(m, " Available Subslice Per Slice: %u\n", | |
5280 | INTEL_INFO(dev)->subslice_per_slice); | |
5281 | seq_printf(m, " Available EU Total: %u\n", | |
5282 | INTEL_INFO(dev)->eu_total); | |
5283 | seq_printf(m, " Available EU Per Subslice: %u\n", | |
5284 | INTEL_INFO(dev)->eu_per_subslice); | |
5285 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
5286 | yesno(INTEL_INFO(dev)->has_slice_pg)); | |
5287 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
5288 | yesno(INTEL_INFO(dev)->has_subslice_pg)); | |
5289 | seq_printf(m, " Has EU Power Gating: %s\n", | |
5290 | yesno(INTEL_INFO(dev)->has_eu_pg)); | |
5291 | ||
7f992aba | 5292 | seq_puts(m, "SSEU Device Status\n"); |
5d39525a | 5293 | memset(&stat, 0, sizeof(stat)); |
5575f03a | 5294 | if (IS_CHERRYVIEW(dev)) { |
5d39525a | 5295 | cherryview_sseu_device_status(dev, &stat); |
91bedd34 ŁD |
5296 | } else if (IS_BROADWELL(dev)) { |
5297 | broadwell_sseu_device_status(dev, &stat); | |
1c046bc1 | 5298 | } else if (INTEL_INFO(dev)->gen >= 9) { |
5d39525a | 5299 | gen9_sseu_device_status(dev, &stat); |
7f992aba | 5300 | } |
5d39525a JM |
5301 | seq_printf(m, " Enabled Slice Total: %u\n", |
5302 | stat.slice_total); | |
5303 | seq_printf(m, " Enabled Subslice Total: %u\n", | |
5304 | stat.subslice_total); | |
5305 | seq_printf(m, " Enabled Subslice Per Slice: %u\n", | |
5306 | stat.subslice_per_slice); | |
5307 | seq_printf(m, " Enabled EU Total: %u\n", | |
5308 | stat.eu_total); | |
5309 | seq_printf(m, " Enabled EU Per Subslice: %u\n", | |
5310 | stat.eu_per_subslice); | |
7f992aba | 5311 | |
3873218f JM |
5312 | return 0; |
5313 | } | |
5314 | ||
6d794d42 BW |
5315 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
5316 | { | |
5317 | struct drm_device *dev = inode->i_private; | |
5318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 5319 | |
075edca4 | 5320 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5321 | return 0; |
5322 | ||
6daccb0b | 5323 | intel_runtime_pm_get(dev_priv); |
59bad947 | 5324 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
5325 | |
5326 | return 0; | |
5327 | } | |
5328 | ||
c43b5634 | 5329 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
5330 | { |
5331 | struct drm_device *dev = inode->i_private; | |
5332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5333 | ||
075edca4 | 5334 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5335 | return 0; |
5336 | ||
59bad947 | 5337 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 5338 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
5339 | |
5340 | return 0; | |
5341 | } | |
5342 | ||
5343 | static const struct file_operations i915_forcewake_fops = { | |
5344 | .owner = THIS_MODULE, | |
5345 | .open = i915_forcewake_open, | |
5346 | .release = i915_forcewake_release, | |
5347 | }; | |
5348 | ||
5349 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5350 | { | |
5351 | struct drm_device *dev = minor->dev; | |
5352 | struct dentry *ent; | |
5353 | ||
5354 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5355 | S_IRUSR, |
6d794d42 BW |
5356 | root, dev, |
5357 | &i915_forcewake_fops); | |
f3c5fe97 WY |
5358 | if (!ent) |
5359 | return -ENOMEM; | |
6d794d42 | 5360 | |
8eb57294 | 5361 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5362 | } |
5363 | ||
6a9c308d DV |
5364 | static int i915_debugfs_create(struct dentry *root, |
5365 | struct drm_minor *minor, | |
5366 | const char *name, | |
5367 | const struct file_operations *fops) | |
07b7ddd9 JB |
5368 | { |
5369 | struct drm_device *dev = minor->dev; | |
5370 | struct dentry *ent; | |
5371 | ||
6a9c308d | 5372 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
5373 | S_IRUGO | S_IWUSR, |
5374 | root, dev, | |
6a9c308d | 5375 | fops); |
f3c5fe97 WY |
5376 | if (!ent) |
5377 | return -ENOMEM; | |
07b7ddd9 | 5378 | |
6a9c308d | 5379 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5380 | } |
5381 | ||
06c5bf8c | 5382 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5383 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5384 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5385 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 5386 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 5387 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 5388 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 5389 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5390 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5391 | {"i915_gem_request", i915_gem_request_info, 0}, |
5392 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5393 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5394 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5395 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5396 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5397 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5398 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5399 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 5400 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 5401 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 5402 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 5403 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5404 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5405 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5406 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5407 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 5408 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 5409 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5410 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5411 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5412 | {"i915_opregion", i915_opregion, 0}, |
ada8f955 | 5413 | {"i915_vbt", i915_vbt, 0}, |
37811fcc | 5414 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5415 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5416 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 5417 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 5418 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5419 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5420 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5421 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5422 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5423 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5424 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5425 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5426 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 5427 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 5428 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 5429 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5430 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5431 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5432 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5433 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5434 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5435 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5436 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5437 | }; |
27c202ad | 5438 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5439 | |
06c5bf8c | 5440 | static const struct i915_debugfs_files { |
34b9674c DV |
5441 | const char *name; |
5442 | const struct file_operations *fops; | |
5443 | } i915_debugfs_files[] = { | |
5444 | {"i915_wedged", &i915_wedged_fops}, | |
5445 | {"i915_max_freq", &i915_max_freq_fops}, | |
5446 | {"i915_min_freq", &i915_min_freq_fops}, | |
5447 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
5448 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
5449 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5450 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
5451 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
5452 | {"i915_error_state", &i915_error_state_fops}, | |
5453 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 5454 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5455 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5456 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5457 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5458 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5459 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5460 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
5461 | {"i915_dp_test_active", &i915_displayport_test_active_fops} | |
34b9674c DV |
5462 | }; |
5463 | ||
07144428 DL |
5464 | void intel_display_crc_init(struct drm_device *dev) |
5465 | { | |
5466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 5467 | enum pipe pipe; |
07144428 | 5468 | |
055e393f | 5469 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5470 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5471 | |
d538bbdf DL |
5472 | pipe_crc->opened = false; |
5473 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5474 | init_waitqueue_head(&pipe_crc->wq); |
5475 | } | |
5476 | } | |
5477 | ||
27c202ad | 5478 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 5479 | { |
34b9674c | 5480 | int ret, i; |
f3cd474b | 5481 | |
6d794d42 | 5482 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5483 | if (ret) |
5484 | return ret; | |
6a9c308d | 5485 | |
07144428 DL |
5486 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5487 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5488 | if (ret) | |
5489 | return ret; | |
5490 | } | |
5491 | ||
34b9674c DV |
5492 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5493 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5494 | i915_debugfs_files[i].name, | |
5495 | i915_debugfs_files[i].fops); | |
5496 | if (ret) | |
5497 | return ret; | |
5498 | } | |
40633219 | 5499 | |
27c202ad BG |
5500 | return drm_debugfs_create_files(i915_debugfs_list, |
5501 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5502 | minor->debugfs_root, minor); |
5503 | } | |
5504 | ||
27c202ad | 5505 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 5506 | { |
34b9674c DV |
5507 | int i; |
5508 | ||
27c202ad BG |
5509 | drm_debugfs_remove_files(i915_debugfs_list, |
5510 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5511 | |
6d794d42 BW |
5512 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
5513 | 1, minor); | |
07144428 | 5514 | |
e309a997 | 5515 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5516 | struct drm_info_list *info_list = |
5517 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5518 | ||
5519 | drm_debugfs_remove_files(info_list, 1, minor); | |
5520 | } | |
5521 | ||
34b9674c DV |
5522 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5523 | struct drm_info_list *info_list = | |
5524 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
5525 | ||
5526 | drm_debugfs_remove_files(info_list, 1, minor); | |
5527 | } | |
2017263e | 5528 | } |
aa7471d2 JN |
5529 | |
5530 | struct dpcd_block { | |
5531 | /* DPCD dump start address. */ | |
5532 | unsigned int offset; | |
5533 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5534 | unsigned int end; | |
5535 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5536 | size_t size; | |
5537 | /* Only valid for eDP. */ | |
5538 | bool edp; | |
5539 | }; | |
5540 | ||
5541 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5542 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5543 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5544 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5545 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5546 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5547 | { .offset = DP_SET_POWER }, | |
5548 | { .offset = DP_EDP_DPCD_REV }, | |
5549 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5550 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5551 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5552 | }; | |
5553 | ||
5554 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5555 | { | |
5556 | struct drm_connector *connector = m->private; | |
5557 | struct intel_dp *intel_dp = | |
5558 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5559 | uint8_t buf[16]; | |
5560 | ssize_t err; | |
5561 | int i; | |
5562 | ||
5c1a8875 MK |
5563 | if (connector->status != connector_status_connected) |
5564 | return -ENODEV; | |
5565 | ||
aa7471d2 JN |
5566 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5567 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5568 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5569 | ||
5570 | if (b->edp && | |
5571 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5572 | continue; | |
5573 | ||
5574 | /* low tech for now */ | |
5575 | if (WARN_ON(size > sizeof(buf))) | |
5576 | continue; | |
5577 | ||
5578 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5579 | if (err <= 0) { | |
5580 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5581 | size, b->offset, err); | |
5582 | continue; | |
5583 | } | |
5584 | ||
5585 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5586 | } |
aa7471d2 JN |
5587 | |
5588 | return 0; | |
5589 | } | |
5590 | ||
5591 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5592 | { | |
5593 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5594 | } | |
5595 | ||
5596 | static const struct file_operations i915_dpcd_fops = { | |
5597 | .owner = THIS_MODULE, | |
5598 | .open = i915_dpcd_open, | |
5599 | .read = seq_read, | |
5600 | .llseek = seq_lseek, | |
5601 | .release = single_release, | |
5602 | }; | |
5603 | ||
5604 | /** | |
5605 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5606 | * @connector: pointer to a registered drm_connector | |
5607 | * | |
5608 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5609 | * drm_debugfs_connector_remove(). | |
5610 | * | |
5611 | * Returns 0 on success, negative error codes on error. | |
5612 | */ | |
5613 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5614 | { | |
5615 | struct dentry *root = connector->debugfs_entry; | |
5616 | ||
5617 | /* The connector must have been registered beforehands. */ | |
5618 | if (!root) | |
5619 | return -ENODEV; | |
5620 | ||
5621 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5622 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5623 | debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, | |
5624 | &i915_dpcd_fops); | |
5625 | ||
5626 | return 0; | |
5627 | } |