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drm/i915: Simplify ELSP queue request tracking
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
36cdd013
DW		 43static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
44{
45 return to_i915(node->minor->dev);
46}
47
497666d8
DL		 48/* As the drm_debugfs_init() routines are called before dev->dev_private is
49 * allocated we need to hook into the minor for release. */
50static int
51drm_add_fake_info_node(struct drm_minor *minor,
52 struct dentry *ent,
53 const void *key)
54{
55 struct drm_info_node *node;
56
57 node = kmalloc(sizeof(*node), GFP_KERNEL);
58 if (node == NULL) {
59 debugfs_remove(ent);
60 return -ENOMEM;
61 }
62
63 node->minor = minor;
64 node->dent = ent;
36cdd013 65 node->info_ent = (void *)key;
497666d8
DL		 66
67 mutex_lock(&minor->debugfs_lock);
68 list_add(&node->list, &minor->debugfs_list);
69 mutex_unlock(&minor->debugfs_lock);
70
71 return 0;
72}
73
70d39fe4
CW		 74static int i915_capabilities(struct seq_file *m, void *data)
75{
36cdd013
DW		 76 struct drm_i915_private *dev_priv = node_to_i915(m->private);
77 const struct intel_device_info *info = INTEL_INFO(dev_priv);
70d39fe4 78
36cdd013
DW		 79 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
80 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
79fc46df
DL		 81#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
82#define SEP_SEMICOLON ;
83 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
84#undef PRINT_FLAG
85#undef SEP_SEMICOLON
70d39fe4
CW		 86
87 return 0;
88}
2017263e 89
a7363de7 90static char get_active_flag(struct drm_i915_gem_object *obj)
a6172a80 91{
573adb39 92 return i915_gem_object_is_active(obj) ? '*' : ' ';
a6172a80
CW		 93}
94
a7363de7 95static char get_pin_flag(struct drm_i915_gem_object *obj)
be12a86b
TU		 96{
97 return obj->pin_display ? 'p' : ' ';
98}
99
a7363de7 100static char get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 101{
3e510a8e 102 switch (i915_gem_object_get_tiling(obj)) {
0206e353 103 default:
be12a86b
TU		 104 case I915_TILING_NONE: return ' ';
105 case I915_TILING_X: return 'X';
106 case I915_TILING_Y: return 'Y';
0206e353 107 }
a6172a80
CW		 108}
109
a7363de7 110static char get_global_flag(struct drm_i915_gem_object *obj)
be12a86b 111{
058d88c4 112 return i915_gem_object_to_ggtt(obj, NULL) ? 'g' : ' ';
be12a86b
TU		 113}
114
a7363de7 115static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
1d693bcc 116{
be12a86b 117 return obj->mapping ? 'M' : ' ';
1d693bcc
BW		 118}
119
ca1543be
TU		 120static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
121{
122 u64 size = 0;
123 struct i915_vma *vma;
124
1c7f4bca 125 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3272db53 126 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
ca1543be
TU		 127 size += vma->node.size;
128 }
129
130 return size;
131}
132
37811fcc
CW		 133static void
134describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
135{
b4716185 136 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
e2f80391 137 struct intel_engine_cs *engine;
1d693bcc 138 struct i915_vma *vma;
faf5bf0a 139 unsigned int frontbuffer_bits;
d7f46fc4 140 int pin_count = 0;
c3232b18 141 enum intel_engine_id id;
d7f46fc4 142
188c1ab7
CW		 143 lockdep_assert_held(&obj->base.dev->struct_mutex);
144
be12a86b 145 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
37811fcc 146 &obj->base,
be12a86b 147 get_active_flag(obj),
37811fcc
CW		 148 get_pin_flag(obj),
149 get_tiling_flag(obj),
1d693bcc 150 get_global_flag(obj),
be12a86b 151 get_pin_mapped_flag(obj),
a05a5862 152 obj->base.size / 1024,
37811fcc 153 obj->base.read_domains,
b4716185 154 obj->base.write_domain);
c3232b18 155 for_each_engine_id(engine, dev_priv, id)
b4716185 156 seq_printf(m, "%x ",
d72d908b
CW		 157 i915_gem_active_get_seqno(&obj->last_read[id],
158 &obj->base.dev->struct_mutex));
49ef5294 159 seq_printf(m, "] %x %s%s%s",
d72d908b
CW		 160 i915_gem_active_get_seqno(&obj->last_write,
161 &obj->base.dev->struct_mutex),
36cdd013 162 i915_cache_level_str(dev_priv, obj->cache_level),
37811fcc
CW		 163 obj->dirty ? " dirty" : "",
164 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
165 if (obj->base.name)
166 seq_printf(m, " (name: %d)", obj->base.name);
1c7f4bca 167 list_for_each_entry(vma, &obj->vma_list, obj_link) {
20dfbde4 168 if (i915_vma_is_pinned(vma))
d7f46fc4 169 pin_count++;
ba0635ff
DC		 170 }
171 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 172 if (obj->pin_display)
173 seq_printf(m, " (display)");
1c7f4bca 174 list_for_each_entry(vma, &obj->vma_list, obj_link) {
15717de2
CW		 175 if (!drm_mm_node_allocated(&vma->node))
176 continue;
177
8d2fdc3f 178 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
3272db53 179 i915_vma_is_ggtt(vma) ? "g" : "pp",
8d2fdc3f 180 vma->node.start, vma->node.size);
3272db53 181 if (i915_vma_is_ggtt(vma))
596c5923 182 seq_printf(m, ", type: %u", vma->ggtt_view.type);
49ef5294
CW		 183 if (vma->fence)
184 seq_printf(m, " , fence: %d%s",
185 vma->fence->id,
186 i915_gem_active_isset(&vma->last_fence) ? "*" : "");
596c5923 187 seq_puts(m, ")");
1d693bcc 188 }
c1ad11fc 189 if (obj->stolen)
440fd528 190 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 191 if (obj->pin_display || obj->fault_mappable) {
6299f992 192 char s[3], *t = s;
30154650 193 if (obj->pin_display)
6299f992
CW		 194 *t++ = 'p';
195 if (obj->fault_mappable)
196 *t++ = 'f';
197 *t = '\0';
198 seq_printf(m, " (%s mappable)", s);
199 }
27c01aae 200
d72d908b 201 engine = i915_gem_active_get_engine(&obj->last_write,
36cdd013 202 &dev_priv->drm.struct_mutex);
27c01aae
CW		 203 if (engine)
204 seq_printf(m, " (%s)", engine->name);
205
faf5bf0a
CW		 206 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
207 if (frontbuffer_bits)
208 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
37811fcc
CW		 209}
210
6d2b8885
CW		 211static int obj_rank_by_stolen(void *priv,
212 struct list_head *A, struct list_head *B)
213{
214 struct drm_i915_gem_object *a =
b25cb2f8 215 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 216 struct drm_i915_gem_object *b =
b25cb2f8 217 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 218
2d05fa16
RV		 219 if (a->stolen->start < b->stolen->start)
220 return -1;
221 if (a->stolen->start > b->stolen->start)
222 return 1;
223 return 0;
6d2b8885
CW		 224}
225
226static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
227{
36cdd013
DW		 228 struct drm_i915_private *dev_priv = node_to_i915(m->private);
229 struct drm_device *dev = &dev_priv->drm;
6d2b8885 230 struct drm_i915_gem_object *obj;
c44ef60e 231 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 232 LIST_HEAD(stolen);
233 int count, ret;
234
235 ret = mutex_lock_interruptible(&dev->struct_mutex);
236 if (ret)
237 return ret;
238
239 total_obj_size = total_gtt_size = count = 0;
240 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
241 if (obj->stolen == NULL)
242 continue;
243
b25cb2f8 244 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 245
246 total_obj_size += obj->base.size;
ca1543be 247 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 248 count++;
249 }
250 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
251 if (obj->stolen == NULL)
252 continue;
253
b25cb2f8 254 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 255
256 total_obj_size += obj->base.size;
257 count++;
258 }
259 list_sort(NULL, &stolen, obj_rank_by_stolen);
260 seq_puts(m, "Stolen:\n");
261 while (!list_empty(&stolen)) {
b25cb2f8 262 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 263 seq_puts(m, " ");
264 describe_obj(m, obj);
265 seq_putc(m, '\n');
b25cb2f8 266 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 267 }
268 mutex_unlock(&dev->struct_mutex);
269
c44ef60e 270 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 271 count, total_obj_size, total_gtt_size);
272 return 0;
273}
274
2db8e9d6 275struct file_stats {
6313c204 276 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 277 unsigned long count;
278 u64 total, unbound;
279 u64 global, shared;
280 u64 active, inactive;
2db8e9d6
CW		 281};
282
283static int per_file_stats(int id, void *ptr, void *data)
284{
285 struct drm_i915_gem_object *obj = ptr;
286 struct file_stats *stats = data;
6313c204 287 struct i915_vma *vma;
2db8e9d6
CW		 288
289 stats->count++;
290 stats->total += obj->base.size;
15717de2
CW		 291 if (!obj->bind_count)
292 stats->unbound += obj->base.size;
c67a17e9
CW		 293 if (obj->base.name || obj->base.dma_buf)
294 stats->shared += obj->base.size;
295
894eeecc
CW		 296 list_for_each_entry(vma, &obj->vma_list, obj_link) {
297 if (!drm_mm_node_allocated(&vma->node))
298 continue;
6313c204 299
3272db53 300 if (i915_vma_is_ggtt(vma)) {
894eeecc
CW		 301 stats->global += vma->node.size;
302 } else {
303 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
6313c204 304
2bfa996e 305 if (ppgtt->base.file != stats->file_priv)
6313c204 306 continue;
6313c204 307 }
894eeecc 308
b0decaf7 309 if (i915_vma_is_active(vma))
894eeecc
CW		 310 stats->active += vma->node.size;
311 else
312 stats->inactive += vma->node.size;
2db8e9d6
CW		 313 }
314
315 return 0;
316}
317
b0da1b79
CW		 318#define print_file_stats(m, name, stats) do { \
319 if (stats.count) \
c44ef60e 320 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 321 name, \
322 stats.count, \
323 stats.total, \
324 stats.active, \
325 stats.inactive, \
326 stats.global, \
327 stats.shared, \
328 stats.unbound); \
329} while (0)
493018dc
BV		 330
331static void print_batch_pool_stats(struct seq_file *m,
332 struct drm_i915_private *dev_priv)
333{
334 struct drm_i915_gem_object *obj;
335 struct file_stats stats;
e2f80391 336 struct intel_engine_cs *engine;
b4ac5afc 337 int j;
493018dc
BV		 338
339 memset(&stats, 0, sizeof(stats));
340
b4ac5afc 341 for_each_engine(engine, dev_priv) {
e2f80391 342 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744 343 list_for_each_entry(obj,
e2f80391 344 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 345 batch_pool_link)
346 per_file_stats(0, obj, &stats);
347 }
06fbca71 348 }
493018dc 349
b0da1b79 350 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 351}
352
15da9565
CW		 353static int per_file_ctx_stats(int id, void *ptr, void *data)
354{
355 struct i915_gem_context *ctx = ptr;
356 int n;
357
358 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
359 if (ctx->engine[n].state)
bf3783e5 360 per_file_stats(0, ctx->engine[n].state->obj, data);
dca33ecc 361 if (ctx->engine[n].ring)
57e88531 362 per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
15da9565
CW		 363 }
364
365 return 0;
366}
367
368static void print_context_stats(struct seq_file *m,
369 struct drm_i915_private *dev_priv)
370{
36cdd013 371 struct drm_device *dev = &dev_priv->drm;
15da9565
CW		 372 struct file_stats stats;
373 struct drm_file *file;
374
375 memset(&stats, 0, sizeof(stats));
376
36cdd013 377 mutex_lock(&dev->struct_mutex);
15da9565
CW		 378 if (dev_priv->kernel_context)
379 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
380
36cdd013 381 list_for_each_entry(file, &dev->filelist, lhead) {
15da9565
CW		 382 struct drm_i915_file_private *fpriv = file->driver_priv;
383 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
384 }
36cdd013 385 mutex_unlock(&dev->struct_mutex);
15da9565
CW		 386
387 print_file_stats(m, "[k]contexts", stats);
388}
389
36cdd013 390static int i915_gem_object_info(struct seq_file *m, void *data)
73aa808f 391{
36cdd013
DW		 392 struct drm_i915_private *dev_priv = node_to_i915(m->private);
393 struct drm_device *dev = &dev_priv->drm;
72e96d64 394 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2bd160a1
CW		 395 u32 count, mapped_count, purgeable_count, dpy_count;
396 u64 size, mapped_size, purgeable_size, dpy_size;
6299f992 397 struct drm_i915_gem_object *obj;
2db8e9d6 398 struct drm_file *file;
73aa808f
CW		 399 int ret;
400
401 ret = mutex_lock_interruptible(&dev->struct_mutex);
402 if (ret)
403 return ret;
404
6299f992
CW		 405 seq_printf(m, "%u objects, %zu bytes\n",
406 dev_priv->mm.object_count,
407 dev_priv->mm.object_memory);
408
1544c42e
CW		 409 size = count = 0;
410 mapped_size = mapped_count = 0;
411 purgeable_size = purgeable_count = 0;
35c20a60 412 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
2bd160a1
CW		 413 size += obj->base.size;
414 ++count;
415
416 if (obj->madv == I915_MADV_DONTNEED) {
417 purgeable_size += obj->base.size;
418 ++purgeable_count;
419 }
420
be19b10d 421 if (obj->mapping) {
2bd160a1
CW		 422 mapped_count++;
423 mapped_size += obj->base.size;
be19b10d 424 }
b7abb714 425 }
c44ef60e 426 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 427
2bd160a1 428 size = count = dpy_size = dpy_count = 0;
35c20a60 429 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2bd160a1
CW		 430 size += obj->base.size;
431 ++count;
432
30154650 433 if (obj->pin_display) {
2bd160a1
CW		 434 dpy_size += obj->base.size;
435 ++dpy_count;
6299f992 436 }
2bd160a1 437
b7abb714
CW		 438 if (obj->madv == I915_MADV_DONTNEED) {
439 purgeable_size += obj->base.size;
440 ++purgeable_count;
441 }
2bd160a1 442
be19b10d 443 if (obj->mapping) {
2bd160a1
CW		 444 mapped_count++;
445 mapped_size += obj->base.size;
be19b10d 446 }
6299f992 447 }
2bd160a1
CW		 448 seq_printf(m, "%u bound objects, %llu bytes\n",
449 count, size);
c44ef60e 450 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 451 purgeable_count, purgeable_size);
2bd160a1
CW		 452 seq_printf(m, "%u mapped objects, %llu bytes\n",
453 mapped_count, mapped_size);
454 seq_printf(m, "%u display objects (pinned), %llu bytes\n",
455 dpy_count, dpy_size);
6299f992 456
c44ef60e 457 seq_printf(m, "%llu [%llu] gtt total\n",
72e96d64 458 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
73aa808f 459
493018dc
BV		 460 seq_putc(m, '\n');
461 print_batch_pool_stats(m, dev_priv);
1d2ac403
DV		 462 mutex_unlock(&dev->struct_mutex);
463
464 mutex_lock(&dev->filelist_mutex);
15da9565 465 print_context_stats(m, dev_priv);
2db8e9d6
CW		 466 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
467 struct file_stats stats;
c84455b4
CW		 468 struct drm_i915_file_private *file_priv = file->driver_priv;
469 struct drm_i915_gem_request *request;
3ec2f427 470 struct task_struct *task;
2db8e9d6
CW		 471
472 memset(&stats, 0, sizeof(stats));
6313c204 473 stats.file_priv = file->driver_priv;
5b5ffff0 474 spin_lock(&file->table_lock);
2db8e9d6 475 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 476 spin_unlock(&file->table_lock);
3ec2f427
TH		 477 /*
478 * Although we have a valid reference on file->pid, that does
479 * not guarantee that the task_struct who called get_pid() is
480 * still alive (e.g. get_pid(current) => fork() => exit()).
481 * Therefore, we need to protect this ->comm access using RCU.
482 */
c84455b4
CW		 483 mutex_lock(&dev->struct_mutex);
484 request = list_first_entry_or_null(&file_priv->mm.request_list,
485 struct drm_i915_gem_request,
486 client_list);
3ec2f427 487 rcu_read_lock();
c84455b4
CW		 488 task = pid_task(request && request->ctx->pid ?
489 request->ctx->pid : file->pid,
490 PIDTYPE_PID);
493018dc 491 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 492 rcu_read_unlock();
c84455b4 493 mutex_unlock(&dev->struct_mutex);
2db8e9d6 494 }
1d2ac403 495 mutex_unlock(&dev->filelist_mutex);
73aa808f
CW		 496
497 return 0;
498}
499
aee56cff 500static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 501{
9f25d007 502 struct drm_info_node *node = m->private;
36cdd013
DW		 503 struct drm_i915_private *dev_priv = node_to_i915(node);
504 struct drm_device *dev = &dev_priv->drm;
5f4b091a 505 bool show_pin_display_only = !!node->info_ent->data;
08c18323 506 struct drm_i915_gem_object *obj;
c44ef60e 507 u64 total_obj_size, total_gtt_size;
08c18323
CW		 508 int count, ret;
509
510 ret = mutex_lock_interruptible(&dev->struct_mutex);
511 if (ret)
512 return ret;
513
514 total_obj_size = total_gtt_size = count = 0;
35c20a60 515 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6da84829 516 if (show_pin_display_only && !obj->pin_display)
1b50247a
CW		 517 continue;
518
267f0c90 519 seq_puts(m, " ");
08c18323 520 describe_obj(m, obj);
267f0c90 521 seq_putc(m, '\n');
08c18323 522 total_obj_size += obj->base.size;
ca1543be 523 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 524 count++;
525 }
526
527 mutex_unlock(&dev->struct_mutex);
528
c44ef60e 529 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 530 count, total_obj_size, total_gtt_size);
531
532 return 0;
533}
534
4e5359cd
SF		 535static int i915_gem_pageflip_info(struct seq_file *m, void *data)
536{
36cdd013
DW		 537 struct drm_i915_private *dev_priv = node_to_i915(m->private);
538 struct drm_device *dev = &dev_priv->drm;
4e5359cd 539 struct intel_crtc *crtc;
8a270ebf
DV		 540 int ret;
541
542 ret = mutex_lock_interruptible(&dev->struct_mutex);
543 if (ret)
544 return ret;
4e5359cd 545
d3fcc808 546 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 547 const char pipe = pipe_name(crtc->pipe);
548 const char plane = plane_name(crtc->plane);
51cbaf01 549 struct intel_flip_work *work;
4e5359cd 550
5e2d7afc 551 spin_lock_irq(&dev->event_lock);
5a21b665
DV		 552 work = crtc->flip_work;
553 if (work == NULL) {
9db4a9c7 554 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 555 pipe, plane);
556 } else {
5a21b665
DV		 557 u32 pending;
558 u32 addr;
559
560 pending = atomic_read(&work->pending);
561 if (pending) {
562 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
563 pipe, plane);
564 } else {
565 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
566 pipe, plane);
567 }
568 if (work->flip_queued_req) {
569 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
570
571 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
572 engine->name,
573 i915_gem_request_get_seqno(work->flip_queued_req),
574 dev_priv->next_seqno,
1b7744e7 575 intel_engine_get_seqno(engine),
f69a02c9 576 i915_gem_request_completed(work->flip_queued_req));
5a21b665
DV		 577 } else
578 seq_printf(m, "Flip not associated with any ring\n");
579 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
580 work->flip_queued_vblank,
581 work->flip_ready_vblank,
582 intel_crtc_get_vblank_counter(crtc));
583 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
584
36cdd013 585 if (INTEL_GEN(dev_priv) >= 4)
5a21b665
DV		 586 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
587 else
588 addr = I915_READ(DSPADDR(crtc->plane));
589 seq_printf(m, "Current scanout address 0x%08x\n", addr);
590
591 if (work->pending_flip_obj) {
592 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
593 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 594 }
595 }
5e2d7afc 596 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 597 }
598
8a270ebf
DV		 599 mutex_unlock(&dev->struct_mutex);
600
4e5359cd
SF		 601 return 0;
602}
603
493018dc
BV		 604static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
605{
36cdd013
DW		 606 struct drm_i915_private *dev_priv = node_to_i915(m->private);
607 struct drm_device *dev = &dev_priv->drm;
493018dc 608 struct drm_i915_gem_object *obj;
e2f80391 609 struct intel_engine_cs *engine;
8d9d5744 610 int total = 0;
b4ac5afc 611 int ret, j;
493018dc
BV		 612
613 ret = mutex_lock_interruptible(&dev->struct_mutex);
614 if (ret)
615 return ret;
616
b4ac5afc 617 for_each_engine(engine, dev_priv) {
e2f80391 618 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
8d9d5744
CW		 619 int count;
620
621 count = 0;
622 list_for_each_entry(obj,
e2f80391 623 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 624 batch_pool_link)
625 count++;
626 seq_printf(m, "%s cache[%d]: %d objects\n",
e2f80391 627 engine->name, j, count);
8d9d5744
CW		 628
629 list_for_each_entry(obj,
e2f80391 630 &engine->batch_pool.cache_list[j],
8d9d5744
CW		 631 batch_pool_link) {
632 seq_puts(m, " ");
633 describe_obj(m, obj);
634 seq_putc(m, '\n');
635 }
636
637 total += count;
06fbca71 638 }
493018dc
BV		 639 }
640
8d9d5744 641 seq_printf(m, "total: %d\n", total);
493018dc
BV		 642
643 mutex_unlock(&dev->struct_mutex);
644
645 return 0;
646}
647
2017263e
BG		 648static int i915_gem_request_info(struct seq_file *m, void *data)
649{
36cdd013
DW		 650 struct drm_i915_private *dev_priv = node_to_i915(m->private);
651 struct drm_device *dev = &dev_priv->drm;
e2f80391 652 struct intel_engine_cs *engine;
eed29a5b 653 struct drm_i915_gem_request *req;
b4ac5afc 654 int ret, any;
de227ef0
CW		 655
656 ret = mutex_lock_interruptible(&dev->struct_mutex);
657 if (ret)
658 return ret;
2017263e 659
2d1070b2 660 any = 0;
b4ac5afc 661 for_each_engine(engine, dev_priv) {
2d1070b2
CW		 662 int count;
663
664 count = 0;
efdf7c06 665 list_for_each_entry(req, &engine->request_list, link)
2d1070b2
CW		 666 count++;
667 if (count == 0)
a2c7f6fd
CW		 668 continue;
669
e2f80391 670 seq_printf(m, "%s requests: %d\n", engine->name, count);
efdf7c06 671 list_for_each_entry(req, &engine->request_list, link) {
c84455b4 672 struct pid *pid = req->ctx->pid;
2d1070b2
CW		 673 struct task_struct *task;
674
675 rcu_read_lock();
c84455b4 676 task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
2d1070b2 677 seq_printf(m, " %x @ %d: %s [%d]\n",
04769652 678 req->fence.seqno,
eed29a5b 679 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 680 task ? task->comm : "<unknown>",
681 task ? task->pid : -1);
682 rcu_read_unlock();
c2c347a9 683 }
2d1070b2
CW		 684
685 any++;
2017263e 686 }
de227ef0
CW		 687 mutex_unlock(&dev->struct_mutex);
688
2d1070b2 689 if (any == 0)
267f0c90 690 seq_puts(m, "No requests\n");
c2c347a9 691
2017263e
BG		 692 return 0;
693}
694
b2223497 695static void i915_ring_seqno_info(struct seq_file *m,
0bc40be8 696 struct intel_engine_cs *engine)
b2223497 697{
688e6c72
CW		 698 struct intel_breadcrumbs *b = &engine->breadcrumbs;
699 struct rb_node *rb;
700
12471ba8 701 seq_printf(m, "Current sequence (%s): %x\n",
1b7744e7 702 engine->name, intel_engine_get_seqno(engine));
688e6c72
CW		 703
704 spin_lock(&b->lock);
705 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
706 struct intel_wait *w = container_of(rb, typeof(*w), node);
707
708 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
709 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
710 }
711 spin_unlock(&b->lock);
b2223497
CW		 712}
713
2017263e
BG		 714static int i915_gem_seqno_info(struct seq_file *m, void *data)
715{
36cdd013 716 struct drm_i915_private *dev_priv = node_to_i915(m->private);
e2f80391 717 struct intel_engine_cs *engine;
2017263e 718
b4ac5afc 719 for_each_engine(engine, dev_priv)
e2f80391 720 i915_ring_seqno_info(m, engine);
de227ef0 721
2017263e
BG		 722 return 0;
723}
724
725
726static int i915_interrupt_info(struct seq_file *m, void *data)
727{
36cdd013 728 struct drm_i915_private *dev_priv = node_to_i915(m->private);
e2f80391 729 struct intel_engine_cs *engine;
4bb05040 730 int i, pipe;
de227ef0 731
c8c8fb33 732 intel_runtime_pm_get(dev_priv);
2017263e 733
36cdd013 734 if (IS_CHERRYVIEW(dev_priv)) {
74e1ca8c
VS		 735 seq_printf(m, "Master Interrupt Control:\t%08x\n",
736 I915_READ(GEN8_MASTER_IRQ));
737
738 seq_printf(m, "Display IER:\t%08x\n",
739 I915_READ(VLV_IER));
740 seq_printf(m, "Display IIR:\t%08x\n",
741 I915_READ(VLV_IIR));
742 seq_printf(m, "Display IIR_RW:\t%08x\n",
743 I915_READ(VLV_IIR_RW));
744 seq_printf(m, "Display IMR:\t%08x\n",
745 I915_READ(VLV_IMR));
055e393f 746 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 747 seq_printf(m, "Pipe %c stat:\t%08x\n",
748 pipe_name(pipe),
749 I915_READ(PIPESTAT(pipe)));
750
751 seq_printf(m, "Port hotplug:\t%08x\n",
752 I915_READ(PORT_HOTPLUG_EN));
753 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
754 I915_READ(VLV_DPFLIPSTAT));
755 seq_printf(m, "DPINVGTT:\t%08x\n",
756 I915_READ(DPINVGTT));
757
758 for (i = 0; i < 4; i++) {
759 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
760 i, I915_READ(GEN8_GT_IMR(i)));
761 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
762 i, I915_READ(GEN8_GT_IIR(i)));
763 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
764 i, I915_READ(GEN8_GT_IER(i)));
765 }
766
767 seq_printf(m, "PCU interrupt mask:\t%08x\n",
768 I915_READ(GEN8_PCU_IMR));
769 seq_printf(m, "PCU interrupt identity:\t%08x\n",
770 I915_READ(GEN8_PCU_IIR));
771 seq_printf(m, "PCU interrupt enable:\t%08x\n",
772 I915_READ(GEN8_PCU_IER));
36cdd013 773 } else if (INTEL_GEN(dev_priv) >= 8) {
a123f157
BW		 774 seq_printf(m, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ));
776
777 for (i = 0; i < 4; i++) {
778 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
779 i, I915_READ(GEN8_GT_IMR(i)));
780 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
781 i, I915_READ(GEN8_GT_IIR(i)));
782 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
783 i, I915_READ(GEN8_GT_IER(i)));
784 }
785
055e393f 786 for_each_pipe(dev_priv, pipe) {
e129649b
ID		 787 enum intel_display_power_domain power_domain;
788
789 power_domain = POWER_DOMAIN_PIPE(pipe);
790 if (!intel_display_power_get_if_enabled(dev_priv,
791 power_domain)) {
22c59960
PZ		 792 seq_printf(m, "Pipe %c power disabled\n",
793 pipe_name(pipe));
794 continue;
795 }
a123f157 796 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 797 pipe_name(pipe),
798 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 799 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 800 pipe_name(pipe),
801 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 802 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 803 pipe_name(pipe),
804 I915_READ(GEN8_DE_PIPE_IER(pipe)));
e129649b
ID		 805
806 intel_display_power_put(dev_priv, power_domain);
a123f157
BW		 807 }
808
809 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
810 I915_READ(GEN8_DE_PORT_IMR));
811 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
812 I915_READ(GEN8_DE_PORT_IIR));
813 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
814 I915_READ(GEN8_DE_PORT_IER));
815
816 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
817 I915_READ(GEN8_DE_MISC_IMR));
818 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
819 I915_READ(GEN8_DE_MISC_IIR));
820 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
821 I915_READ(GEN8_DE_MISC_IER));
822
823 seq_printf(m, "PCU interrupt mask:\t%08x\n",
824 I915_READ(GEN8_PCU_IMR));
825 seq_printf(m, "PCU interrupt identity:\t%08x\n",
826 I915_READ(GEN8_PCU_IIR));
827 seq_printf(m, "PCU interrupt enable:\t%08x\n",
828 I915_READ(GEN8_PCU_IER));
36cdd013 829 } else if (IS_VALLEYVIEW(dev_priv)) {
7e231dbe
JB		 830 seq_printf(m, "Display IER:\t%08x\n",
831 I915_READ(VLV_IER));
832 seq_printf(m, "Display IIR:\t%08x\n",
833 I915_READ(VLV_IIR));
834 seq_printf(m, "Display IIR_RW:\t%08x\n",
835 I915_READ(VLV_IIR_RW));
836 seq_printf(m, "Display IMR:\t%08x\n",
837 I915_READ(VLV_IMR));
055e393f 838 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 839 seq_printf(m, "Pipe %c stat:\t%08x\n",
840 pipe_name(pipe),
841 I915_READ(PIPESTAT(pipe)));
842
843 seq_printf(m, "Master IER:\t%08x\n",
844 I915_READ(VLV_MASTER_IER));
845
846 seq_printf(m, "Render IER:\t%08x\n",
847 I915_READ(GTIER));
848 seq_printf(m, "Render IIR:\t%08x\n",
849 I915_READ(GTIIR));
850 seq_printf(m, "Render IMR:\t%08x\n",
851 I915_READ(GTIMR));
852
853 seq_printf(m, "PM IER:\t\t%08x\n",
854 I915_READ(GEN6_PMIER));
855 seq_printf(m, "PM IIR:\t\t%08x\n",
856 I915_READ(GEN6_PMIIR));
857 seq_printf(m, "PM IMR:\t\t%08x\n",
858 I915_READ(GEN6_PMIMR));
859
860 seq_printf(m, "Port hotplug:\t%08x\n",
861 I915_READ(PORT_HOTPLUG_EN));
862 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
863 I915_READ(VLV_DPFLIPSTAT));
864 seq_printf(m, "DPINVGTT:\t%08x\n",
865 I915_READ(DPINVGTT));
866
36cdd013 867 } else if (!HAS_PCH_SPLIT(dev_priv)) {
5f6a1695
ZW		 868 seq_printf(m, "Interrupt enable: %08x\n",
869 I915_READ(IER));
870 seq_printf(m, "Interrupt identity: %08x\n",
871 I915_READ(IIR));
872 seq_printf(m, "Interrupt mask: %08x\n",
873 I915_READ(IMR));
055e393f 874 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 875 seq_printf(m, "Pipe %c stat: %08x\n",
876 pipe_name(pipe),
877 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 878 } else {
879 seq_printf(m, "North Display Interrupt enable: %08x\n",
880 I915_READ(DEIER));
881 seq_printf(m, "North Display Interrupt identity: %08x\n",
882 I915_READ(DEIIR));
883 seq_printf(m, "North Display Interrupt mask: %08x\n",
884 I915_READ(DEIMR));
885 seq_printf(m, "South Display Interrupt enable: %08x\n",
886 I915_READ(SDEIER));
887 seq_printf(m, "South Display Interrupt identity: %08x\n",
888 I915_READ(SDEIIR));
889 seq_printf(m, "South Display Interrupt mask: %08x\n",
890 I915_READ(SDEIMR));
891 seq_printf(m, "Graphics Interrupt enable: %08x\n",
892 I915_READ(GTIER));
893 seq_printf(m, "Graphics Interrupt identity: %08x\n",
894 I915_READ(GTIIR));
895 seq_printf(m, "Graphics Interrupt mask: %08x\n",
896 I915_READ(GTIMR));
897 }
b4ac5afc 898 for_each_engine(engine, dev_priv) {
36cdd013 899 if (INTEL_GEN(dev_priv) >= 6) {
a2c7f6fd
CW		 900 seq_printf(m,
901 "Graphics Interrupt mask (%s): %08x\n",
e2f80391 902 engine->name, I915_READ_IMR(engine));
9862e600 903 }
e2f80391 904 i915_ring_seqno_info(m, engine);
9862e600 905 }
c8c8fb33 906 intel_runtime_pm_put(dev_priv);
de227ef0 907
2017263e
BG		 908 return 0;
909}
910
a6172a80
CW		 911static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
912{
36cdd013
DW		 913 struct drm_i915_private *dev_priv = node_to_i915(m->private);
914 struct drm_device *dev = &dev_priv->drm;
de227ef0
CW		 915 int i, ret;
916
917 ret = mutex_lock_interruptible(&dev->struct_mutex);
918 if (ret)
919 return ret;
a6172a80 920
a6172a80
CW		 921 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
922 for (i = 0; i < dev_priv->num_fence_regs; i++) {
49ef5294 923 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
a6172a80 924
6c085a72
CW		 925 seq_printf(m, "Fence %d, pin count = %d, object = ",
926 i, dev_priv->fence_regs[i].pin_count);
49ef5294 927 if (!vma)
267f0c90 928 seq_puts(m, "unused");
c2c347a9 929 else
49ef5294 930 describe_obj(m, vma->obj);
267f0c90 931 seq_putc(m, '\n');
a6172a80
CW		 932 }
933
05394f39 934 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 935 return 0;
936}
937
2017263e
BG		 938static int i915_hws_info(struct seq_file *m, void *data)
939{
9f25d007 940 struct drm_info_node *node = m->private;
36cdd013 941 struct drm_i915_private *dev_priv = node_to_i915(node);
e2f80391 942 struct intel_engine_cs *engine;
1a240d4d 943 const u32 *hws;
4066c0ae
CW		 944 int i;
945
4a570db5 946 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
e2f80391 947 hws = engine->status_page.page_addr;
2017263e
BG		 948 if (hws == NULL)
949 return 0;
950
951 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
952 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
953 i * 4,
954 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
955 }
956 return 0;
957}
958
d5442303
DV		 959static ssize_t
960i915_error_state_write(struct file *filp,
961 const char __user *ubuf,
962 size_t cnt,
963 loff_t *ppos)
964{
edc3d884 965 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303
DV		 966
967 DRM_DEBUG_DRIVER("Resetting error state\n");
662d19e7 968 i915_destroy_error_state(error_priv->dev);
d5442303
DV		 969
970 return cnt;
971}
972
973static int i915_error_state_open(struct inode *inode, struct file *file)
974{
36cdd013 975 struct drm_i915_private *dev_priv = inode->i_private;
d5442303 976 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 977
978 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
979 if (!error_priv)
980 return -ENOMEM;
981
36cdd013 982 error_priv->dev = &dev_priv->drm;
d5442303 983
36cdd013 984 i915_error_state_get(&dev_priv->drm, error_priv);
d5442303 985
edc3d884
MK		 986 file->private_data = error_priv;
987
988 return 0;
d5442303
DV		 989}
990
991static int i915_error_state_release(struct inode *inode, struct file *file)
992{
edc3d884 993 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 994
95d5bfb3 995 i915_error_state_put(error_priv);
d5442303
DV		 996 kfree(error_priv);
997
edc3d884
MK		 998 return 0;
999}
1000
4dc955f7
MK		 1001static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1002 size_t count, loff_t *pos)
1003{
1004 struct i915_error_state_file_priv *error_priv = file->private_data;
1005 struct drm_i915_error_state_buf error_str;
1006 loff_t tmp_pos = 0;
1007 ssize_t ret_count = 0;
1008 int ret;
1009
36cdd013
DW		 1010 ret = i915_error_state_buf_init(&error_str,
1011 to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1012 if (ret)
1013 return ret;
edc3d884 1014
fc16b48b 1015 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1016 if (ret)
1017 goto out;
1018
edc3d884
MK		 1019 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1020 error_str.buf,
1021 error_str.bytes);
1022
1023 if (ret_count < 0)
1024 ret = ret_count;
1025 else
1026 *pos = error_str.start + ret_count;
1027out:
4dc955f7 1028 i915_error_state_buf_release(&error_str);
edc3d884 1029 return ret ?: ret_count;
d5442303
DV		 1030}
1031
1032static const struct file_operations i915_error_state_fops = {
1033 .owner = THIS_MODULE,
1034 .open = i915_error_state_open,
edc3d884 1035 .read = i915_error_state_read,
d5442303
DV		 1036 .write = i915_error_state_write,
1037 .llseek = default_llseek,
1038 .release = i915_error_state_release,
1039};
1040
647416f9
KC		 1041static int
1042i915_next_seqno_get(void *data, u64 *val)
40633219 1043{
36cdd013 1044 struct drm_i915_private *dev_priv = data;
40633219
MK		 1045 int ret;
1046
36cdd013 1047 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
40633219
MK		 1048 if (ret)
1049 return ret;
1050
647416f9 1051 *val = dev_priv->next_seqno;
36cdd013 1052 mutex_unlock(&dev_priv->drm.struct_mutex);
40633219 1053
647416f9 1054 return 0;
40633219
MK		 1055}
1056
647416f9
KC		 1057static int
1058i915_next_seqno_set(void *data, u64 val)
1059{
36cdd013
DW		 1060 struct drm_i915_private *dev_priv = data;
1061 struct drm_device *dev = &dev_priv->drm;
40633219
MK		 1062 int ret;
1063
40633219
MK		 1064 ret = mutex_lock_interruptible(&dev->struct_mutex);
1065 if (ret)
1066 return ret;
1067
e94fbaa8 1068 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1069 mutex_unlock(&dev->struct_mutex);
1070
647416f9 1071 return ret;
40633219
MK		 1072}
1073
647416f9
KC		 1074DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1075 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1076 "0x%llx\n");
40633219 1077
adb4bd12 1078static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1079{
36cdd013
DW		 1080 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1081 struct drm_device *dev = &dev_priv->drm;
c8c8fb33
PZ		 1082 int ret = 0;
1083
1084 intel_runtime_pm_get(dev_priv);
3b8d8d91 1085
36cdd013 1086 if (IS_GEN5(dev_priv)) {
3b8d8d91
JB		 1087 u16 rgvswctl = I915_READ16(MEMSWCTL);
1088 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1089
1090 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1091 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1092 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1093 MEMSTAT_VID_SHIFT);
1094 seq_printf(m, "Current P-state: %d\n",
1095 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
36cdd013 1096 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
666a4537
WB		 1097 u32 freq_sts;
1098
1099 mutex_lock(&dev_priv->rps.hw_lock);
1100 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1101 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1102 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1103
1104 seq_printf(m, "actual GPU freq: %d MHz\n",
1105 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1106
1107 seq_printf(m, "current GPU freq: %d MHz\n",
1108 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1109
1110 seq_printf(m, "max GPU freq: %d MHz\n",
1111 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1112
1113 seq_printf(m, "min GPU freq: %d MHz\n",
1114 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1115
1116 seq_printf(m, "idle GPU freq: %d MHz\n",
1117 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1118
1119 seq_printf(m,
1120 "efficient (RPe) frequency: %d MHz\n",
1121 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1122 mutex_unlock(&dev_priv->rps.hw_lock);
36cdd013 1123 } else if (INTEL_GEN(dev_priv) >= 6) {
35040562
BP		 1124 u32 rp_state_limits;
1125 u32 gt_perf_status;
1126 u32 rp_state_cap;
0d8f9491 1127 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1128 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1129 u32 rpupei, rpcurup, rpprevup;
1130 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1131 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1132 int max_freq;
1133
35040562 1134 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
36cdd013 1135 if (IS_BROXTON(dev_priv)) {
35040562
BP		 1136 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1137 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1138 } else {
1139 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1140 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1141 }
1142
3b8d8d91 1143 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1144 ret = mutex_lock_interruptible(&dev->struct_mutex);
1145 if (ret)
c8c8fb33 1146 goto out;
d1ebd816 1147
59bad947 1148 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1149
8e8c06cd 1150 reqf = I915_READ(GEN6_RPNSWREQ);
36cdd013 1151 if (IS_GEN9(dev_priv))
60260a5b
AG		 1152 reqf >>= 23;
1153 else {
1154 reqf &= ~GEN6_TURBO_DISABLE;
36cdd013 1155 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
60260a5b
AG		 1156 reqf >>= 24;
1157 else
1158 reqf >>= 25;
1159 }
7c59a9c1 1160 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1161
0d8f9491
CW		 1162 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1163 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1164 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1165
ccab5c82 1166 rpstat = I915_READ(GEN6_RPSTAT1);
d6cda9c7
AG		 1167 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1168 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1169 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1170 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1171 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1172 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
36cdd013 1173 if (IS_GEN9(dev_priv))
60260a5b 1174 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
36cdd013 1175 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
f82855d3
BW		 1176 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1177 else
1178 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1179 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1180
59bad947 1181 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1182 mutex_unlock(&dev->struct_mutex);
1183
36cdd013 1184 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
9dd3c605
PZ		 1185 pm_ier = I915_READ(GEN6_PMIER);
1186 pm_imr = I915_READ(GEN6_PMIMR);
1187 pm_isr = I915_READ(GEN6_PMISR);
1188 pm_iir = I915_READ(GEN6_PMIIR);
1189 pm_mask = I915_READ(GEN6_PMINTRMSK);
1190 } else {
1191 pm_ier = I915_READ(GEN8_GT_IER(2));
1192 pm_imr = I915_READ(GEN8_GT_IMR(2));
1193 pm_isr = I915_READ(GEN8_GT_ISR(2));
1194 pm_iir = I915_READ(GEN8_GT_IIR(2));
1195 pm_mask = I915_READ(GEN6_PMINTRMSK);
1196 }
0d8f9491 1197 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1198 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1800ad25 1199 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
3b8d8d91 1200 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1201 seq_printf(m, "Render p-state ratio: %d\n",
36cdd013 1202 (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1203 seq_printf(m, "Render p-state VID: %d\n",
1204 gt_perf_status & 0xff);
1205 seq_printf(m, "Render p-state limit: %d\n",
1206 rp_state_limits & 0xff);
0d8f9491
CW		 1207 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1208 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1209 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1210 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1211 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1212 seq_printf(m, "CAGF: %dMHz\n", cagf);
d6cda9c7
AG		 1213 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1214 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1215 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1216 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1217 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1218 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
d86ed34a
CW		 1219 seq_printf(m, "Up threshold: %d%%\n",
1220 dev_priv->rps.up_threshold);
1221
d6cda9c7
AG		 1222 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1223 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1224 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1225 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1226 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1227 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
d86ed34a
CW		 1228 seq_printf(m, "Down threshold: %d%%\n",
1229 dev_priv->rps.down_threshold);
3b8d8d91 1230
36cdd013 1231 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
35040562 1232 rp_state_cap >> 16) & 0xff;
36cdd013 1233 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
ef11bdb3 1234 GEN9_FREQ_SCALER : 1);
3b8d8d91 1235 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1236 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1237
1238 max_freq = (rp_state_cap & 0xff00) >> 8;
36cdd013 1239 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
ef11bdb3 1240 GEN9_FREQ_SCALER : 1);
3b8d8d91 1241 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1242 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1243
36cdd013 1244 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
35040562 1245 rp_state_cap >> 0) & 0xff;
36cdd013 1246 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
ef11bdb3 1247 GEN9_FREQ_SCALER : 1);
3b8d8d91 1248 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1249 intel_gpu_freq(dev_priv, max_freq));
31c77388 1250 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1251 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1252
d86ed34a
CW		 1253 seq_printf(m, "Current freq: %d MHz\n",
1254 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1255 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1256 seq_printf(m, "Idle freq: %d MHz\n",
1257 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1258 seq_printf(m, "Min freq: %d MHz\n",
1259 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
29ecd78d
CW		 1260 seq_printf(m, "Boost freq: %d MHz\n",
1261 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
d86ed34a
CW		 1262 seq_printf(m, "Max freq: %d MHz\n",
1263 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1264 seq_printf(m,
1265 "efficient (RPe) frequency: %d MHz\n",
1266 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
3b8d8d91 1267 } else {
267f0c90 1268 seq_puts(m, "no P-state info available\n");
3b8d8d91 1269 }
f97108d1 1270
1170f28c
MK		 1271 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1272 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1273 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1274
c8c8fb33
PZ		 1275out:
1276 intel_runtime_pm_put(dev_priv);
1277 return ret;
f97108d1
JB		 1278}
1279
f654449a
CW		 1280static int i915_hangcheck_info(struct seq_file *m, void *unused)
1281{
36cdd013 1282 struct drm_i915_private *dev_priv = node_to_i915(m->private);
e2f80391 1283 struct intel_engine_cs *engine;
666796da
TU		 1284 u64 acthd[I915_NUM_ENGINES];
1285 u32 seqno[I915_NUM_ENGINES];
61642ff0 1286 u32 instdone[I915_NUM_INSTDONE_REG];
c3232b18
DG		 1287 enum intel_engine_id id;
1288 int j;
f654449a
CW		 1289
1290 if (!i915.enable_hangcheck) {
1291 seq_printf(m, "Hangcheck disabled\n");
1292 return 0;
1293 }
1294
ebbc7546
MK		 1295 intel_runtime_pm_get(dev_priv);
1296
c3232b18 1297 for_each_engine_id(engine, dev_priv, id) {
7e37f889 1298 acthd[id] = intel_engine_get_active_head(engine);
1b7744e7 1299 seqno[id] = intel_engine_get_seqno(engine);
ebbc7546
MK		 1300 }
1301
c033666a 1302 i915_get_extra_instdone(dev_priv, instdone);
61642ff0 1303
ebbc7546
MK		 1304 intel_runtime_pm_put(dev_priv);
1305
f654449a
CW		 1306 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1307 seq_printf(m, "Hangcheck active, fires in %dms\n",
1308 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1309 jiffies));
1310 } else
1311 seq_printf(m, "Hangcheck inactive\n");
1312
c3232b18 1313 for_each_engine_id(engine, dev_priv, id) {
e2f80391 1314 seq_printf(m, "%s:\n", engine->name);
14fd0d6d
CW		 1315 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1316 engine->hangcheck.seqno,
1317 seqno[id],
1318 engine->last_submitted_seqno);
83348ba8
CW		 1319 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1320 yesno(intel_engine_has_waiter(engine)),
1321 yesno(test_bit(engine->id,
1322 &dev_priv->gpu_error.missed_irq_rings)));
f654449a 1323 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
e2f80391 1324 (long long)engine->hangcheck.acthd,
c3232b18 1325 (long long)acthd[id]);
e2f80391
TU		 1326 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1327 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
61642ff0 1328
e2f80391 1329 if (engine->id == RCS) {
61642ff0
MK		 1330 seq_puts(m, "\tinstdone read =");
1331
1332 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1333 seq_printf(m, " 0x%08x", instdone[j]);
1334
1335 seq_puts(m, "\n\tinstdone accu =");
1336
1337 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1338 seq_printf(m, " 0x%08x",
e2f80391 1339 engine->hangcheck.instdone[j]);
61642ff0
MK		 1340
1341 seq_puts(m, "\n");
1342 }
f654449a
CW		 1343 }
1344
1345 return 0;
1346}
1347
4d85529d 1348static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1349{
36cdd013
DW		 1350 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1351 struct drm_device *dev = &dev_priv->drm;
616fdb5a
BW		 1352 u32 rgvmodectl, rstdbyctl;
1353 u16 crstandvid;
1354 int ret;
1355
1356 ret = mutex_lock_interruptible(&dev->struct_mutex);
1357 if (ret)
1358 return ret;
c8c8fb33 1359 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1360
1361 rgvmodectl = I915_READ(MEMMODECTL);
1362 rstdbyctl = I915_READ(RSTDBYCTL);
1363 crstandvid = I915_READ16(CRSTANDVID);
1364
c8c8fb33 1365 intel_runtime_pm_put(dev_priv);
616fdb5a 1366 mutex_unlock(&dev->struct_mutex);
f97108d1 1367
742f491d 1368 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1369 seq_printf(m, "Boost freq: %d\n",
1370 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1371 MEMMODE_BOOST_FREQ_SHIFT);
1372 seq_printf(m, "HW control enabled: %s\n",
742f491d 1373 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1374 seq_printf(m, "SW control enabled: %s\n",
742f491d 1375 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1376 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1377 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1378 seq_printf(m, "Starting frequency: P%d\n",
1379 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1380 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1381 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1382 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1383 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1384 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1385 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1386 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1387 seq_puts(m, "Current RS state: ");
88271da3
JB		 1388 switch (rstdbyctl & RSX_STATUS_MASK) {
1389 case RSX_STATUS_ON:
267f0c90 1390 seq_puts(m, "on\n");
88271da3
JB		 1391 break;
1392 case RSX_STATUS_RC1:
267f0c90 1393 seq_puts(m, "RC1\n");
88271da3
JB		 1394 break;
1395 case RSX_STATUS_RC1E:
267f0c90 1396 seq_puts(m, "RC1E\n");
88271da3
JB		 1397 break;
1398 case RSX_STATUS_RS1:
267f0c90 1399 seq_puts(m, "RS1\n");
88271da3
JB		 1400 break;
1401 case RSX_STATUS_RS2:
267f0c90 1402 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1403 break;
1404 case RSX_STATUS_RS3:
267f0c90 1405 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1406 break;
1407 default:
267f0c90 1408 seq_puts(m, "unknown\n");
88271da3
JB		 1409 break;
1410 }
f97108d1
JB		 1411
1412 return 0;
1413}
1414
f65367b5 1415static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1416{
36cdd013 1417 struct drm_i915_private *dev_priv = node_to_i915(m->private);
b2cff0db 1418 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1419
1420 spin_lock_irq(&dev_priv->uncore.lock);
33c582c1 1421 for_each_fw_domain(fw_domain, dev_priv) {
b2cff0db 1422 seq_printf(m, "%s.wake_count = %u\n",
33c582c1 1423 intel_uncore_forcewake_domain_to_str(fw_domain->id),
b2cff0db
CW		 1424 fw_domain->wake_count);
1425 }
1426 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1427
b2cff0db
CW		 1428 return 0;
1429}
1430
1431static int vlv_drpc_info(struct seq_file *m)
1432{
36cdd013 1433 struct drm_i915_private *dev_priv = node_to_i915(m->private);
6b312cd3 1434 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1435
d46c0517
ID		 1436 intel_runtime_pm_get(dev_priv);
1437
6b312cd3 1438 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1439 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1440 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1441
d46c0517
ID		 1442 intel_runtime_pm_put(dev_priv);
1443
669ab5aa
D		 1444 seq_printf(m, "Video Turbo Mode: %s\n",
1445 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1446 seq_printf(m, "Turbo enabled: %s\n",
1447 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1448 seq_printf(m, "HW control enabled: %s\n",
1449 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1450 seq_printf(m, "SW control enabled: %s\n",
1451 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1452 GEN6_RP_MEDIA_SW_MODE));
1453 seq_printf(m, "RC6 Enabled: %s\n",
1454 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1455 GEN6_RC_CTL_EI_MODE(1))));
1456 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1457 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1458 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1459 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1460
9cc19be5
ID		 1461 seq_printf(m, "Render RC6 residency since boot: %u\n",
1462 I915_READ(VLV_GT_RENDER_RC6));
1463 seq_printf(m, "Media RC6 residency since boot: %u\n",
1464 I915_READ(VLV_GT_MEDIA_RC6));
1465
f65367b5 1466 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1467}
1468
4d85529d
BW		 1469static int gen6_drpc_info(struct seq_file *m)
1470{
36cdd013
DW		 1471 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1472 struct drm_device *dev = &dev_priv->drm;
ecd8faea 1473 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
f2dd7578 1474 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
93b525dc 1475 unsigned forcewake_count;
aee56cff 1476 int count = 0, ret;
4d85529d
BW		 1477
1478 ret = mutex_lock_interruptible(&dev->struct_mutex);
1479 if (ret)
1480 return ret;
c8c8fb33 1481 intel_runtime_pm_get(dev_priv);
4d85529d 1482
907b28c5 1483 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1484 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1485 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1486
1487 if (forcewake_count) {
267f0c90
DL		 1488 seq_puts(m, "RC information inaccurate because somebody "
1489 "holds a forcewake reference \n");
4d85529d
BW		 1490 } else {
1491 /* NB: we cannot use forcewake, else we read the wrong values */
1492 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1493 udelay(10);
1494 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1495 }
1496
75aa3f63 1497 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
ed71f1b4 1498 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1499
1500 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1501 rcctl1 = I915_READ(GEN6_RC_CONTROL);
36cdd013 1502 if (INTEL_GEN(dev_priv) >= 9) {
f2dd7578
AG		 1503 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1504 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1505 }
4d85529d 1506 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1507 mutex_lock(&dev_priv->rps.hw_lock);
1508 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1509 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1510
c8c8fb33
PZ		 1511 intel_runtime_pm_put(dev_priv);
1512
4d85529d
BW		 1513 seq_printf(m, "Video Turbo Mode: %s\n",
1514 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1515 seq_printf(m, "HW control enabled: %s\n",
1516 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1517 seq_printf(m, "SW control enabled: %s\n",
1518 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1519 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1520 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1521 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1522 seq_printf(m, "RC6 Enabled: %s\n",
1523 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
36cdd013 1524 if (INTEL_GEN(dev_priv) >= 9) {
f2dd7578
AG		 1525 seq_printf(m, "Render Well Gating Enabled: %s\n",
1526 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1527 seq_printf(m, "Media Well Gating Enabled: %s\n",
1528 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1529 }
4d85529d
BW		 1530 seq_printf(m, "Deep RC6 Enabled: %s\n",
1531 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1532 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1533 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1534 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1535 switch (gt_core_status & GEN6_RCn_MASK) {
1536 case GEN6_RC0:
1537 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1538 seq_puts(m, "Core Power Down\n");
4d85529d 1539 else
267f0c90 1540 seq_puts(m, "on\n");
4d85529d
BW		 1541 break;
1542 case GEN6_RC3:
267f0c90 1543 seq_puts(m, "RC3\n");
4d85529d
BW		 1544 break;
1545 case GEN6_RC6:
267f0c90 1546 seq_puts(m, "RC6\n");
4d85529d
BW		 1547 break;
1548 case GEN6_RC7:
267f0c90 1549 seq_puts(m, "RC7\n");
4d85529d
BW		 1550 break;
1551 default:
267f0c90 1552 seq_puts(m, "Unknown\n");
4d85529d
BW		 1553 break;
1554 }
1555
1556 seq_printf(m, "Core Power Down: %s\n",
1557 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
36cdd013 1558 if (INTEL_GEN(dev_priv) >= 9) {
f2dd7578
AG		 1559 seq_printf(m, "Render Power Well: %s\n",
1560 (gen9_powergate_status &
1561 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1562 seq_printf(m, "Media Power Well: %s\n",
1563 (gen9_powergate_status &
1564 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1565 }
cce66a28
BW		 1566
1567 /* Not exactly sure what this is */
1568 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1569 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1570 seq_printf(m, "RC6 residency since boot: %u\n",
1571 I915_READ(GEN6_GT_GFX_RC6));
1572 seq_printf(m, "RC6+ residency since boot: %u\n",
1573 I915_READ(GEN6_GT_GFX_RC6p));
1574 seq_printf(m, "RC6++ residency since boot: %u\n",
1575 I915_READ(GEN6_GT_GFX_RC6pp));
1576
ecd8faea
BW		 1577 seq_printf(m, "RC6 voltage: %dmV\n",
1578 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1579 seq_printf(m, "RC6+ voltage: %dmV\n",
1580 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1581 seq_printf(m, "RC6++ voltage: %dmV\n",
1582 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
f2dd7578 1583 return i915_forcewake_domains(m, NULL);
4d85529d
BW		 1584}
1585
1586static int i915_drpc_info(struct seq_file *m, void *unused)
1587{
36cdd013 1588 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4d85529d 1589
36cdd013 1590 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
669ab5aa 1591 return vlv_drpc_info(m);
36cdd013 1592 else if (INTEL_GEN(dev_priv) >= 6)
4d85529d
BW		 1593 return gen6_drpc_info(m);
1594 else
1595 return ironlake_drpc_info(m);
1596}
1597
9a851789
DV		 1598static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1599{
36cdd013 1600 struct drm_i915_private *dev_priv = node_to_i915(m->private);
9a851789
DV		 1601
1602 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1603 dev_priv->fb_tracking.busy_bits);
1604
1605 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1606 dev_priv->fb_tracking.flip_bits);
1607
1608 return 0;
1609}
1610
b5e50c3f
JB		 1611static int i915_fbc_status(struct seq_file *m, void *unused)
1612{
36cdd013 1613 struct drm_i915_private *dev_priv = node_to_i915(m->private);
b5e50c3f 1614
36cdd013 1615 if (!HAS_FBC(dev_priv)) {
267f0c90 1616 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1617 return 0;
1618 }
1619
36623ef8 1620 intel_runtime_pm_get(dev_priv);
25ad93fd 1621 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1622
0e631adc 1623 if (intel_fbc_is_active(dev_priv))
267f0c90 1624 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1625 else
1626 seq_printf(m, "FBC disabled: %s\n",
bf6189c6 1627 dev_priv->fbc.no_fbc_reason);
36623ef8 1628
36cdd013 1629 if (INTEL_GEN(dev_priv) >= 7)
31b9df10
PZ		 1630 seq_printf(m, "Compressing: %s\n",
1631 yesno(I915_READ(FBC_STATUS2) &
1632 FBC_COMPRESSION_MASK));
1633
25ad93fd 1634 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1635 intel_runtime_pm_put(dev_priv);
1636
b5e50c3f
JB		 1637 return 0;
1638}
1639
da46f936
RV		 1640static int i915_fbc_fc_get(void *data, u64 *val)
1641{
36cdd013 1642 struct drm_i915_private *dev_priv = data;
da46f936 1643
36cdd013 1644 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
da46f936
RV		 1645 return -ENODEV;
1646
da46f936 1647 *val = dev_priv->fbc.false_color;
da46f936
RV		 1648
1649 return 0;
1650}
1651
1652static int i915_fbc_fc_set(void *data, u64 val)
1653{
36cdd013 1654 struct drm_i915_private *dev_priv = data;
da46f936
RV		 1655 u32 reg;
1656
36cdd013 1657 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
da46f936
RV		 1658 return -ENODEV;
1659
25ad93fd 1660 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1661
1662 reg = I915_READ(ILK_DPFC_CONTROL);
1663 dev_priv->fbc.false_color = val;
1664
1665 I915_WRITE(ILK_DPFC_CONTROL, val ?
1666 (reg | FBC_CTL_FALSE_COLOR) :
1667 (reg & ~FBC_CTL_FALSE_COLOR));
1668
25ad93fd 1669 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1670 return 0;
1671}
1672
1673DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1674 i915_fbc_fc_get, i915_fbc_fc_set,
1675 "%llu\n");
1676
92d44621
PZ		 1677static int i915_ips_status(struct seq_file *m, void *unused)
1678{
36cdd013 1679 struct drm_i915_private *dev_priv = node_to_i915(m->private);
92d44621 1680
36cdd013 1681 if (!HAS_IPS(dev_priv)) {
92d44621
PZ		 1682 seq_puts(m, "not supported\n");
1683 return 0;
1684 }
1685
36623ef8
PZ		 1686 intel_runtime_pm_get(dev_priv);
1687
0eaa53f0
RV		 1688 seq_printf(m, "Enabled by kernel parameter: %s\n",
1689 yesno(i915.enable_ips));
1690
36cdd013 1691 if (INTEL_GEN(dev_priv) >= 8) {
0eaa53f0
RV		 1692 seq_puts(m, "Currently: unknown\n");
1693 } else {
1694 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1695 seq_puts(m, "Currently: enabled\n");
1696 else
1697 seq_puts(m, "Currently: disabled\n");
1698 }
92d44621 1699
36623ef8
PZ		 1700 intel_runtime_pm_put(dev_priv);
1701
92d44621
PZ		 1702 return 0;
1703}
1704
4a9bef37
JB		 1705static int i915_sr_status(struct seq_file *m, void *unused)
1706{
36cdd013 1707 struct drm_i915_private *dev_priv = node_to_i915(m->private);
4a9bef37
JB		 1708 bool sr_enabled = false;
1709
36623ef8
PZ		 1710 intel_runtime_pm_get(dev_priv);
1711
36cdd013 1712 if (HAS_PCH_SPLIT(dev_priv))
5ba2aaaa 1713 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
36cdd013
DW		 1714 else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1715 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
4a9bef37 1716 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
36cdd013 1717 else if (IS_I915GM(dev_priv))
4a9bef37 1718 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
36cdd013 1719 else if (IS_PINEVIEW(dev_priv))
4a9bef37 1720 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
36cdd013 1721 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
77b64555 1722 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1723
36623ef8
PZ		 1724 intel_runtime_pm_put(dev_priv);
1725
5ba2aaaa
CW		 1726 seq_printf(m, "self-refresh: %s\n",
1727 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1728
1729 return 0;
1730}
1731
7648fa99
JB		 1732static int i915_emon_status(struct seq_file *m, void *unused)
1733{
36cdd013
DW		 1734 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1735 struct drm_device *dev = &dev_priv->drm;
7648fa99 1736 unsigned long temp, chipset, gfx;
de227ef0
CW		 1737 int ret;
1738
36cdd013 1739 if (!IS_GEN5(dev_priv))
582be6b4
CW		 1740 return -ENODEV;
1741
de227ef0
CW		 1742 ret = mutex_lock_interruptible(&dev->struct_mutex);
1743 if (ret)
1744 return ret;
7648fa99
JB		 1745
1746 temp = i915_mch_val(dev_priv);
1747 chipset = i915_chipset_val(dev_priv);
1748 gfx = i915_gfx_val(dev_priv);
de227ef0 1749 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1750
1751 seq_printf(m, "GMCH temp: %ld\n", temp);
1752 seq_printf(m, "Chipset power: %ld\n", chipset);
1753 seq_printf(m, "GFX power: %ld\n", gfx);
1754 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1755
1756 return 0;
1757}
1758
23b2f8bb
JB		 1759static int i915_ring_freq_table(struct seq_file *m, void *unused)
1760{
36cdd013 1761 struct drm_i915_private *dev_priv = node_to_i915(m->private);
5bfa0199 1762 int ret = 0;
23b2f8bb 1763 int gpu_freq, ia_freq;
f936ec34 1764 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1765
26310346 1766 if (!HAS_LLC(dev_priv)) {
267f0c90 1767 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1768 return 0;
1769 }
1770
5bfa0199
PZ		 1771 intel_runtime_pm_get(dev_priv);
1772
4fc688ce 1773 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1774 if (ret)
5bfa0199 1775 goto out;
23b2f8bb 1776
36cdd013 1777 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
f936ec34
AG		 1778 /* Convert GT frequency to 50 HZ units */
1779 min_gpu_freq =
1780 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1781 max_gpu_freq =
1782 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1783 } else {
1784 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1785 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1786 }
1787
267f0c90 1788 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1789
f936ec34 1790 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1791 ia_freq = gpu_freq;
1792 sandybridge_pcode_read(dev_priv,
1793 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1794 &ia_freq);
3ebecd07 1795 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34 1796 intel_gpu_freq(dev_priv, (gpu_freq *
36cdd013 1797 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
ef11bdb3 1798 GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1799 ((ia_freq >> 0) & 0xff) * 100,
1800 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1801 }
1802
4fc688ce 1803 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1804
5bfa0199
PZ		 1805out:
1806 intel_runtime_pm_put(dev_priv);
1807 return ret;
23b2f8bb
JB		 1808}
1809
44834a67
CW		 1810static int i915_opregion(struct seq_file *m, void *unused)
1811{
36cdd013
DW		 1812 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1813 struct drm_device *dev = &dev_priv->drm;
44834a67
CW		 1814 struct intel_opregion *opregion = &dev_priv->opregion;
1815 int ret;
1816
1817 ret = mutex_lock_interruptible(&dev->struct_mutex);
1818 if (ret)
0d38f009 1819 goto out;
44834a67 1820
2455a8e4
JN		 1821 if (opregion->header)
1822 seq_write(m, opregion->header, OPREGION_SIZE);
44834a67
CW		 1823
1824 mutex_unlock(&dev->struct_mutex);
1825
0d38f009 1826out:
44834a67
CW		 1827 return 0;
1828}
1829
ada8f955
JN		 1830static int i915_vbt(struct seq_file *m, void *unused)
1831{
36cdd013 1832 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
ada8f955
JN		 1833
1834 if (opregion->vbt)
1835 seq_write(m, opregion->vbt, opregion->vbt_size);
1836
1837 return 0;
1838}
1839
37811fcc
CW		 1840static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1841{
36cdd013
DW		 1842 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1843 struct drm_device *dev = &dev_priv->drm;
b13b8402 1844 struct intel_framebuffer *fbdev_fb = NULL;
3a58ee10 1845 struct drm_framebuffer *drm_fb;
188c1ab7
CW		 1846 int ret;
1847
1848 ret = mutex_lock_interruptible(&dev->struct_mutex);
1849 if (ret)
1850 return ret;
37811fcc 1851
0695726e 1852#ifdef CONFIG_DRM_FBDEV_EMULATION
36cdd013
DW		 1853 if (dev_priv->fbdev) {
1854 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
25bcce94
CW		 1855
1856 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1857 fbdev_fb->base.width,
1858 fbdev_fb->base.height,
1859 fbdev_fb->base.depth,
1860 fbdev_fb->base.bits_per_pixel,
1861 fbdev_fb->base.modifier[0],
1862 drm_framebuffer_read_refcount(&fbdev_fb->base));
1863 describe_obj(m, fbdev_fb->obj);
1864 seq_putc(m, '\n');
1865 }
4520f53a 1866#endif
37811fcc 1867
4b096ac1 1868 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10 1869 drm_for_each_fb(drm_fb, dev) {
b13b8402
NS		 1870 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1871 if (fb == fbdev_fb)
37811fcc
CW		 1872 continue;
1873
c1ca506d 1874 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1875 fb->base.width,
1876 fb->base.height,
1877 fb->base.depth,
623f9783 1878 fb->base.bits_per_pixel,
c1ca506d 1879 fb->base.modifier[0],
747a598f 1880 drm_framebuffer_read_refcount(&fb->base));
05394f39 1881 describe_obj(m, fb->obj);
267f0c90 1882 seq_putc(m, '\n');
37811fcc 1883 }
4b096ac1 1884 mutex_unlock(&dev->mode_config.fb_lock);
188c1ab7 1885 mutex_unlock(&dev->struct_mutex);
37811fcc
CW		 1886
1887 return 0;
1888}
1889
7e37f889 1890static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
c9fe99bd
OM		 1891{
1892 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
7e37f889
CW		 1893 ring->space, ring->head, ring->tail,
1894 ring->last_retired_head);
c9fe99bd
OM		 1895}
1896
e76d3630
BW		 1897static int i915_context_status(struct seq_file *m, void *unused)
1898{
36cdd013
DW		 1899 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1900 struct drm_device *dev = &dev_priv->drm;
e2f80391 1901 struct intel_engine_cs *engine;
e2efd130 1902 struct i915_gem_context *ctx;
c3232b18 1903 int ret;
e76d3630 1904
f3d28878 1905 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1906 if (ret)
1907 return ret;
1908
a33afea5 1909 list_for_each_entry(ctx, &dev_priv->context_list, link) {
5d1808ec 1910 seq_printf(m, "HW context %u ", ctx->hw_id);
c84455b4 1911 if (ctx->pid) {
d28b99ab
CW		 1912 struct task_struct *task;
1913
c84455b4 1914 task = get_pid_task(ctx->pid, PIDTYPE_PID);
d28b99ab
CW		 1915 if (task) {
1916 seq_printf(m, "(%s [%d]) ",
1917 task->comm, task->pid);
1918 put_task_struct(task);
1919 }
c84455b4
CW		 1920 } else if (IS_ERR(ctx->file_priv)) {
1921 seq_puts(m, "(deleted) ");
d28b99ab
CW		 1922 } else {
1923 seq_puts(m, "(kernel) ");
1924 }
1925
bca44d80
CW		 1926 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1927 seq_putc(m, '\n');
c9fe99bd 1928
bca44d80
CW		 1929 for_each_engine(engine, dev_priv) {
1930 struct intel_context *ce = &ctx->engine[engine->id];
1931
1932 seq_printf(m, "%s: ", engine->name);
1933 seq_putc(m, ce->initialised ? 'I' : 'i');
1934 if (ce->state)
bf3783e5 1935 describe_obj(m, ce->state->obj);
dca33ecc 1936 if (ce->ring)
7e37f889 1937 describe_ctx_ring(m, ce->ring);
c9fe99bd 1938 seq_putc(m, '\n');
c9fe99bd 1939 }
a33afea5 1940
a33afea5 1941 seq_putc(m, '\n');
a168c293
BW		 1942 }
1943
f3d28878 1944 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1945
1946 return 0;
1947}
1948
064ca1d2 1949static void i915_dump_lrc_obj(struct seq_file *m,
e2efd130 1950 struct i915_gem_context *ctx,
0bc40be8 1951 struct intel_engine_cs *engine)
064ca1d2 1952{
bf3783e5 1953 struct i915_vma *vma = ctx->engine[engine->id].state;
064ca1d2 1954 struct page *page;
064ca1d2 1955 int j;
064ca1d2 1956
7069b144
CW		 1957 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
1958
bf3783e5
CW		 1959 if (!vma) {
1960 seq_puts(m, "\tFake context\n");
064ca1d2
TD		 1961 return;
1962 }
1963
bf3783e5
CW		 1964 if (vma->flags & I915_VMA_GLOBAL_BIND)
1965 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
bde13ebd 1966 i915_ggtt_offset(vma));
064ca1d2 1967
bf3783e5
CW		 1968 if (i915_gem_object_get_pages(vma->obj)) {
1969 seq_puts(m, "\tFailed to get pages for context object\n\n");
064ca1d2
TD		 1970 return;
1971 }
1972
bf3783e5
CW		 1973 page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
1974 if (page) {
1975 u32 *reg_state = kmap_atomic(page);
064ca1d2
TD		 1976
1977 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
bf3783e5
CW		 1978 seq_printf(m,
1979 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1980 j * 4,
064ca1d2
TD		 1981 reg_state[j], reg_state[j + 1],
1982 reg_state[j + 2], reg_state[j + 3]);
1983 }
1984 kunmap_atomic(reg_state);
1985 }
1986
1987 seq_putc(m, '\n');
1988}
1989
c0ab1ae9
BW		 1990static int i915_dump_lrc(struct seq_file *m, void *unused)
1991{
36cdd013
DW		 1992 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1993 struct drm_device *dev = &dev_priv->drm;
e2f80391 1994 struct intel_engine_cs *engine;
e2efd130 1995 struct i915_gem_context *ctx;
b4ac5afc 1996 int ret;
c0ab1ae9
BW		 1997
1998 if (!i915.enable_execlists) {
1999 seq_printf(m, "Logical Ring Contexts are disabled\n");
2000 return 0;
2001 }
2002
2003 ret = mutex_lock_interruptible(&dev->struct_mutex);
2004 if (ret)
2005 return ret;
2006
e28e404c 2007 list_for_each_entry(ctx, &dev_priv->context_list, link)
24f1d3cc
CW		 2008 for_each_engine(engine, dev_priv)
2009 i915_dump_lrc_obj(m, ctx, engine);
c0ab1ae9
BW		 2010
2011 mutex_unlock(&dev->struct_mutex);
2012
2013 return 0;
2014}
2015
4ba70e44
OM		 2016static int i915_execlists(struct seq_file *m, void *data)
2017{
36cdd013
DW		 2018 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2019 struct drm_device *dev = &dev_priv->drm;
e2f80391 2020 struct intel_engine_cs *engine;
4ba70e44
OM		 2021 u32 status_pointer;
2022 u8 read_pointer;
2023 u8 write_pointer;
2024 u32 status;
2025 u32 ctx_id;
2026 struct list_head *cursor;
b4ac5afc 2027 int i, ret;
4ba70e44
OM		 2028
2029 if (!i915.enable_execlists) {
2030 seq_puts(m, "Logical Ring Contexts are disabled\n");
2031 return 0;
2032 }
2033
2034 ret = mutex_lock_interruptible(&dev->struct_mutex);
2035 if (ret)
2036 return ret;
2037
fc0412ec
MT		 2038 intel_runtime_pm_get(dev_priv);
2039
b4ac5afc 2040 for_each_engine(engine, dev_priv) {
6d3d8274 2041 struct drm_i915_gem_request *head_req = NULL;
4ba70e44 2042 int count = 0;
4ba70e44 2043
e2f80391 2044 seq_printf(m, "%s\n", engine->name);
4ba70e44 2045
e2f80391
TU		 2046 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2047 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
4ba70e44
OM		 2048 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2049 status, ctx_id);
2050
e2f80391 2051 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
4ba70e44
OM		 2052 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2053
70c2a24d 2054 read_pointer = GEN8_CSB_READ_PTR(status_pointer);
5590a5f0 2055 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
4ba70e44 2056 if (read_pointer > write_pointer)
5590a5f0 2057 write_pointer += GEN8_CSB_ENTRIES;
4ba70e44
OM		 2058 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2059 read_pointer, write_pointer);
2060
5590a5f0 2061 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
e2f80391
TU		 2062 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2063 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
4ba70e44
OM		 2064
2065 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2066 i, status, ctx_id);
2067 }
2068
27af5eea 2069 spin_lock_bh(&engine->execlist_lock);
e2f80391 2070 list_for_each(cursor, &engine->execlist_queue)
4ba70e44 2071 count++;
e2f80391
TU		 2072 head_req = list_first_entry_or_null(&engine->execlist_queue,
2073 struct drm_i915_gem_request,
2074 execlist_link);
27af5eea 2075 spin_unlock_bh(&engine->execlist_lock);
4ba70e44
OM		 2076
2077 seq_printf(m, "\t%d requests in queue\n", count);
2078 if (head_req) {
7069b144
CW		 2079 seq_printf(m, "\tHead request context: %u\n",
2080 head_req->ctx->hw_id);
4ba70e44 2081 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2082 head_req->tail);
4ba70e44
OM		 2083 }
2084
2085 seq_putc(m, '\n');
2086 }
2087
fc0412ec 2088 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2089 mutex_unlock(&dev->struct_mutex);
2090
2091 return 0;
2092}
2093
ea16a3cd
DV		 2094static const char *swizzle_string(unsigned swizzle)
2095{
aee56cff 2096 switch (swizzle) {
ea16a3cd
DV		 2097 case I915_BIT_6_SWIZZLE_NONE:
2098 return "none";
2099 case I915_BIT_6_SWIZZLE_9:
2100 return "bit9";
2101 case I915_BIT_6_SWIZZLE_9_10:
2102 return "bit9/bit10";
2103 case I915_BIT_6_SWIZZLE_9_11:
2104 return "bit9/bit11";
2105 case I915_BIT_6_SWIZZLE_9_10_11:
2106 return "bit9/bit10/bit11";
2107 case I915_BIT_6_SWIZZLE_9_17:
2108 return "bit9/bit17";
2109 case I915_BIT_6_SWIZZLE_9_10_17:
2110 return "bit9/bit10/bit17";
2111 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2112 return "unknown";
ea16a3cd
DV		 2113 }
2114
2115 return "bug";
2116}
2117
2118static int i915_swizzle_info(struct seq_file *m, void *data)
2119{
36cdd013
DW		 2120 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2121 struct drm_device *dev = &dev_priv->drm;
22bcfc6a
DV		 2122 int ret;
2123
2124 ret = mutex_lock_interruptible(&dev->struct_mutex);
2125 if (ret)
2126 return ret;
c8c8fb33 2127 intel_runtime_pm_get(dev_priv);
ea16a3cd 2128
ea16a3cd
DV		 2129 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2130 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2131 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2132 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2133
36cdd013 2134 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
ea16a3cd
DV		 2135 seq_printf(m, "DDC = 0x%08x\n",
2136 I915_READ(DCC));
656bfa3a
DV		 2137 seq_printf(m, "DDC2 = 0x%08x\n",
2138 I915_READ(DCC2));
ea16a3cd
DV		 2139 seq_printf(m, "C0DRB3 = 0x%04x\n",
2140 I915_READ16(C0DRB3));
2141 seq_printf(m, "C1DRB3 = 0x%04x\n",
2142 I915_READ16(C1DRB3));
36cdd013 2143 } else if (INTEL_GEN(dev_priv) >= 6) {
3fa7d235
DV		 2144 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2145 I915_READ(MAD_DIMM_C0));
2146 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2147 I915_READ(MAD_DIMM_C1));
2148 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2149 I915_READ(MAD_DIMM_C2));
2150 seq_printf(m, "TILECTL = 0x%08x\n",
2151 I915_READ(TILECTL));
36cdd013 2152 if (INTEL_GEN(dev_priv) >= 8)
9d3203e1
BW		 2153 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2154 I915_READ(GAMTARBMODE));
2155 else
2156 seq_printf(m, "ARB_MODE = 0x%08x\n",
2157 I915_READ(ARB_MODE));
3fa7d235
DV		 2158 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2159 I915_READ(DISP_ARB_CTL));
ea16a3cd 2160 }
656bfa3a
DV		 2161
2162 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2163 seq_puts(m, "L-shaped memory detected\n");
2164
c8c8fb33 2165 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2166 mutex_unlock(&dev->struct_mutex);
2167
2168 return 0;
2169}
2170
1c60fef5
BW		 2171static int per_file_ctx(int id, void *ptr, void *data)
2172{
e2efd130 2173 struct i915_gem_context *ctx = ptr;
1c60fef5 2174 struct seq_file *m = data;
ae6c4806
DV		 2175 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2176
2177 if (!ppgtt) {
2178 seq_printf(m, " no ppgtt for context %d\n",
2179 ctx->user_handle);
2180 return 0;
2181 }
1c60fef5 2182
f83d6518
OM		 2183 if (i915_gem_context_is_default(ctx))
2184 seq_puts(m, " default context:\n");
2185 else
821d66dd 2186 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2187 ppgtt->debug_dump(ppgtt, m);
2188
2189 return 0;
2190}
2191
36cdd013
DW		 2192static void gen8_ppgtt_info(struct seq_file *m,
2193 struct drm_i915_private *dev_priv)
3cf17fc5 2194{
e2f80391 2195 struct intel_engine_cs *engine;
77df6772 2196 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
b4ac5afc 2197 int i;
3cf17fc5 2198
77df6772
BW		 2199 if (!ppgtt)
2200 return;
2201
b4ac5afc 2202 for_each_engine(engine, dev_priv) {
e2f80391 2203 seq_printf(m, "%s\n", engine->name);
77df6772 2204 for (i = 0; i < 4; i++) {
e2f80391 2205 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
77df6772 2206 pdp <<= 32;
e2f80391 2207 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
a2a5b15c 2208 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2209 }
2210 }
2211}
2212
36cdd013
DW		 2213static void gen6_ppgtt_info(struct seq_file *m,
2214 struct drm_i915_private *dev_priv)
77df6772 2215{
e2f80391 2216 struct intel_engine_cs *engine;
3cf17fc5 2217
7e22dbbb 2218 if (IS_GEN6(dev_priv))
3cf17fc5
DV		 2219 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2220
b4ac5afc 2221 for_each_engine(engine, dev_priv) {
e2f80391 2222 seq_printf(m, "%s\n", engine->name);
7e22dbbb 2223 if (IS_GEN7(dev_priv))
e2f80391
TU		 2224 seq_printf(m, "GFX_MODE: 0x%08x\n",
2225 I915_READ(RING_MODE_GEN7(engine)));
2226 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2227 I915_READ(RING_PP_DIR_BASE(engine)));
2228 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2229 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2230 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2231 I915_READ(RING_PP_DIR_DCLV(engine)));
3cf17fc5
DV		 2232 }
2233 if (dev_priv->mm.aliasing_ppgtt) {
2234 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2235
267f0c90 2236 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2237 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2238
87d60b63 2239 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2240 }
1c60fef5 2241
3cf17fc5 2242 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2243}
2244
2245static int i915_ppgtt_info(struct seq_file *m, void *data)
2246{
36cdd013
DW		 2247 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2248 struct drm_device *dev = &dev_priv->drm;
ea91e401 2249 struct drm_file *file;
637ee29e 2250 int ret;
77df6772 2251
637ee29e
CW		 2252 mutex_lock(&dev->filelist_mutex);
2253 ret = mutex_lock_interruptible(&dev->struct_mutex);
77df6772 2254 if (ret)
637ee29e
CW		 2255 goto out_unlock;
2256
c8c8fb33 2257 intel_runtime_pm_get(dev_priv);
77df6772 2258
36cdd013
DW		 2259 if (INTEL_GEN(dev_priv) >= 8)
2260 gen8_ppgtt_info(m, dev_priv);
2261 else if (INTEL_GEN(dev_priv) >= 6)
2262 gen6_ppgtt_info(m, dev_priv);
77df6772 2263
ea91e401
MT		 2264 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2265 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2266 struct task_struct *task;
ea91e401 2267
7cb5dff8 2268 task = get_pid_task(file->pid, PIDTYPE_PID);
06812760
DC		 2269 if (!task) {
2270 ret = -ESRCH;
637ee29e 2271 goto out_rpm;
06812760 2272 }
7cb5dff8
GT		 2273 seq_printf(m, "\nproc: %s\n", task->comm);
2274 put_task_struct(task);
ea91e401
MT		 2275 idr_for_each(&file_priv->context_idr, per_file_ctx,
2276 (void *)(unsigned long)m);
2277 }
2278
637ee29e 2279out_rpm:
c8c8fb33 2280 intel_runtime_pm_put(dev_priv);
3cf17fc5 2281 mutex_unlock(&dev->struct_mutex);
637ee29e
CW		 2282out_unlock:
2283 mutex_unlock(&dev->filelist_mutex);
06812760 2284 return ret;
3cf17fc5
DV		 2285}
2286
f5a4c67d
CW		 2287static int count_irq_waiters(struct drm_i915_private *i915)
2288{
e2f80391 2289 struct intel_engine_cs *engine;
f5a4c67d 2290 int count = 0;
f5a4c67d 2291
b4ac5afc 2292 for_each_engine(engine, i915)
688e6c72 2293 count += intel_engine_has_waiter(engine);
f5a4c67d
CW		 2294
2295 return count;
2296}
2297
7466c291
CW		 2298static const char *rps_power_to_str(unsigned int power)
2299{
2300 static const char * const strings[] = {
2301 [LOW_POWER] = "low power",
2302 [BETWEEN] = "mixed",
2303 [HIGH_POWER] = "high power",
2304 };
2305
2306 if (power >= ARRAY_SIZE(strings) || !strings[power])
2307 return "unknown";
2308
2309 return strings[power];
2310}
2311
1854d5ca
CW		 2312static int i915_rps_boost_info(struct seq_file *m, void *data)
2313{
36cdd013
DW		 2314 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2315 struct drm_device *dev = &dev_priv->drm;
1854d5ca 2316 struct drm_file *file;
1854d5ca 2317
f5a4c67d 2318 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
67d97da3
CW		 2319 seq_printf(m, "GPU busy? %s [%x]\n",
2320 yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
f5a4c67d 2321 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
7466c291
CW		 2322 seq_printf(m, "Frequency requested %d\n",
2323 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2324 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
f5a4c67d
CW		 2325 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2326 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2327 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2328 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
7466c291
CW		 2329 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
2330 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2331 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2332 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1d2ac403
DV		 2333
2334 mutex_lock(&dev->filelist_mutex);
8d3afd7d 2335 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2336 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2337 struct drm_i915_file_private *file_priv = file->driver_priv;
2338 struct task_struct *task;
2339
2340 rcu_read_lock();
2341 task = pid_task(file->pid, PIDTYPE_PID);
2342 seq_printf(m, "%s [%d]: %d boosts%s\n",
2343 task ? task->comm : "<unknown>",
2344 task ? task->pid : -1,
2e1b8730
CW		 2345 file_priv->rps.boosts,
2346 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2347 rcu_read_unlock();
2348 }
197be2ae 2349 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2350 spin_unlock(&dev_priv->rps.client_lock);
1d2ac403 2351 mutex_unlock(&dev->filelist_mutex);
1854d5ca 2352
7466c291
CW		 2353 if (INTEL_GEN(dev_priv) >= 6 &&
2354 dev_priv->rps.enabled &&
2355 dev_priv->gt.active_engines) {
2356 u32 rpup, rpupei;
2357 u32 rpdown, rpdownei;
2358
2359 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2360 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2361 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2362 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2363 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2364 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2365
2366 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2367 rps_power_to_str(dev_priv->rps.power));
2368 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
2369 100 * rpup / rpupei,
2370 dev_priv->rps.up_threshold);
2371 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
2372 100 * rpdown / rpdownei,
2373 dev_priv->rps.down_threshold);
2374 } else {
2375 seq_puts(m, "\nRPS Autotuning inactive\n");
2376 }
2377
8d3afd7d 2378 return 0;
1854d5ca
CW		 2379}
2380
63573eb7
BW		 2381static int i915_llc(struct seq_file *m, void *data)
2382{
36cdd013 2383 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3accaf7e 2384 const bool edram = INTEL_GEN(dev_priv) > 8;
63573eb7 2385
36cdd013 2386 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
3accaf7e
MK		 2387 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2388 intel_uncore_edram_size(dev_priv)/1024/1024);
63573eb7
BW		 2389
2390 return 0;
2391}
2392
fdf5d357
AD		 2393static int i915_guc_load_status_info(struct seq_file *m, void *data)
2394{
36cdd013 2395 struct drm_i915_private *dev_priv = node_to_i915(m->private);
fdf5d357
AD		 2396 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2397 u32 tmp, i;
2398
2d1fe073 2399 if (!HAS_GUC_UCODE(dev_priv))
fdf5d357
AD		 2400 return 0;
2401
2402 seq_printf(m, "GuC firmware status:\n");
2403 seq_printf(m, "\tpath: %s\n",
2404 guc_fw->guc_fw_path);
2405 seq_printf(m, "\tfetch: %s\n",
2406 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2407 seq_printf(m, "\tload: %s\n",
2408 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2409 seq_printf(m, "\tversion wanted: %d.%d\n",
2410 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2411 seq_printf(m, "\tversion found: %d.%d\n",
2412 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
feda33ef
AD		 2413 seq_printf(m, "\theader: offset is %d; size = %d\n",
2414 guc_fw->header_offset, guc_fw->header_size);
2415 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2416 guc_fw->ucode_offset, guc_fw->ucode_size);
2417 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2418 guc_fw->rsa_offset, guc_fw->rsa_size);
fdf5d357
AD		 2419
2420 tmp = I915_READ(GUC_STATUS);
2421
2422 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2423 seq_printf(m, "\tBootrom status = 0x%x\n",
2424 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2425 seq_printf(m, "\tuKernel status = 0x%x\n",
2426 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2427 seq_printf(m, "\tMIA Core status = 0x%x\n",
2428 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2429 seq_puts(m, "\nScratch registers:\n");
2430 for (i = 0; i < 16; i++)
2431 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2432
2433 return 0;
2434}
2435
8b417c26
DG		 2436static void i915_guc_client_info(struct seq_file *m,
2437 struct drm_i915_private *dev_priv,
2438 struct i915_guc_client *client)
2439{
e2f80391 2440 struct intel_engine_cs *engine;
c18468c4 2441 enum intel_engine_id id;
8b417c26 2442 uint64_t tot = 0;
8b417c26
DG		 2443
2444 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2445 client->priority, client->ctx_index, client->proc_desc_offset);
2446 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2447 client->doorbell_id, client->doorbell_offset, client->cookie);
2448 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2449 client->wq_size, client->wq_offset, client->wq_tail);
2450
551aaecd 2451 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
8b417c26
DG		 2452 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2453 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2454
c18468c4
DG		 2455 for_each_engine_id(engine, dev_priv, id) {
2456 u64 submissions = client->submissions[id];
2457 tot += submissions;
8b417c26 2458 seq_printf(m, "\tSubmissions: %llu %s\n",
c18468c4 2459 submissions, engine->name);
8b417c26
DG		 2460 }
2461 seq_printf(m, "\tTotal: %llu\n", tot);
2462}
2463
2464static int i915_guc_info(struct seq_file *m, void *data)
2465{
36cdd013
DW		 2466 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2467 struct drm_device *dev = &dev_priv->drm;
8b417c26 2468 struct intel_guc guc;
0a0b457f 2469 struct i915_guc_client client = {};
e2f80391 2470 struct intel_engine_cs *engine;
c18468c4 2471 enum intel_engine_id id;
8b417c26
DG		 2472 u64 total = 0;
2473
2d1fe073 2474 if (!HAS_GUC_SCHED(dev_priv))
8b417c26
DG		 2475 return 0;
2476
5a843307
AD		 2477 if (mutex_lock_interruptible(&dev->struct_mutex))
2478 return 0;
2479
8b417c26 2480 /* Take a local copy of the GuC data, so we can dump it at leisure */
8b417c26 2481 guc = dev_priv->guc;
5a843307 2482 if (guc.execbuf_client)
8b417c26 2483 client = *guc.execbuf_client;
5a843307
AD		 2484
2485 mutex_unlock(&dev->struct_mutex);
8b417c26 2486
9636f6db
DG		 2487 seq_printf(m, "Doorbell map:\n");
2488 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2489 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2490
8b417c26
DG		 2491 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2492 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2493 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2494 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2495 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2496
2497 seq_printf(m, "\nGuC submissions:\n");
c18468c4
DG		 2498 for_each_engine_id(engine, dev_priv, id) {
2499 u64 submissions = guc.submissions[id];
2500 total += submissions;
397097b0 2501 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
c18468c4 2502 engine->name, submissions, guc.last_seqno[id]);
8b417c26
DG		 2503 }
2504 seq_printf(m, "\t%s: %llu\n", "Total", total);
2505
2506 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2507 i915_guc_client_info(m, dev_priv, &client);
2508
2509 /* Add more as required ... */
2510
2511 return 0;
2512}
2513
4c7e77fc
AD		 2514static int i915_guc_log_dump(struct seq_file *m, void *data)
2515{
36cdd013 2516 struct drm_i915_private *dev_priv = node_to_i915(m->private);
8b797af1 2517 struct drm_i915_gem_object *obj;
4c7e77fc
AD		 2518 int i = 0, pg;
2519
8b797af1 2520 if (!dev_priv->guc.log_vma)
4c7e77fc
AD		 2521 return 0;
2522
8b797af1
CW		 2523 obj = dev_priv->guc.log_vma->obj;
2524 for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2525 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
4c7e77fc
AD		 2526
2527 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2528 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2529 *(log + i), *(log + i + 1),
2530 *(log + i + 2), *(log + i + 3));
2531
2532 kunmap_atomic(log);
2533 }
2534
2535 seq_putc(m, '\n');
2536
2537 return 0;
2538}
2539
e91fd8c6
RV		 2540static int i915_edp_psr_status(struct seq_file *m, void *data)
2541{
36cdd013 2542 struct drm_i915_private *dev_priv = node_to_i915(m->private);
a031d709 2543 u32 psrperf = 0;
a6cbdb8e
RV		 2544 u32 stat[3];
2545 enum pipe pipe;
a031d709 2546 bool enabled = false;
e91fd8c6 2547
36cdd013 2548 if (!HAS_PSR(dev_priv)) {
3553a8ea
DL		 2549 seq_puts(m, "PSR not supported\n");
2550 return 0;
2551 }
2552
c8c8fb33
PZ		 2553 intel_runtime_pm_get(dev_priv);
2554
fa128fa6 2555 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2556 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2557 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2558 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2559 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2560 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2561 dev_priv->psr.busy_frontbuffer_bits);
2562 seq_printf(m, "Re-enable work scheduled: %s\n",
2563 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2564
36cdd013 2565 if (HAS_DDI(dev_priv))
443a389f 2566 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
3553a8ea
DL		 2567 else {
2568 for_each_pipe(dev_priv, pipe) {
2569 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2570 VLV_EDP_PSR_CURR_STATE_MASK;
2571 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2572 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2573 enabled = true;
a6cbdb8e
RV		 2574 }
2575 }
60e5ffe3
RV		 2576
2577 seq_printf(m, "Main link in standby mode: %s\n",
2578 yesno(dev_priv->psr.link_standby));
2579
a6cbdb8e
RV		 2580 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2581
36cdd013 2582 if (!HAS_DDI(dev_priv))
a6cbdb8e
RV		 2583 for_each_pipe(dev_priv, pipe) {
2584 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2585 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2586 seq_printf(m, " pipe %c", pipe_name(pipe));
2587 }
2588 seq_puts(m, "\n");
e91fd8c6 2589
05eec3c2
RV		 2590 /*
2591 * VLV/CHV PSR has no kind of performance counter
2592 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2593 */
36cdd013 2594 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
443a389f 2595 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
a031d709 2596 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2597
2598 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2599 }
fa128fa6 2600 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2601
c8c8fb33 2602 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2603 return 0;
2604}
2605
d2e216d0
RV		 2606static int i915_sink_crc(struct seq_file *m, void *data)
2607{
36cdd013
DW		 2608 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2609 struct drm_device *dev = &dev_priv->drm;
d2e216d0
RV		 2610 struct intel_connector *connector;
2611 struct intel_dp *intel_dp = NULL;
2612 int ret;
2613 u8 crc[6];
2614
2615 drm_modeset_lock_all(dev);
aca5e361 2616 for_each_intel_connector(dev, connector) {
26c17cf6 2617 struct drm_crtc *crtc;
d2e216d0 2618
26c17cf6 2619 if (!connector->base.state->best_encoder)
d2e216d0
RV		 2620 continue;
2621
26c17cf6
ML		 2622 crtc = connector->base.state->crtc;
2623 if (!crtc->state->active)
b6ae3c7c
PZ		 2624 continue;
2625
26c17cf6 2626 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
d2e216d0
RV		 2627 continue;
2628
26c17cf6 2629 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
d2e216d0
RV		 2630
2631 ret = intel_dp_sink_crc(intel_dp, crc);
2632 if (ret)
2633 goto out;
2634
2635 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2636 crc[0], crc[1], crc[2],
2637 crc[3], crc[4], crc[5]);
2638 goto out;
2639 }
2640 ret = -ENODEV;
2641out:
2642 drm_modeset_unlock_all(dev);
2643 return ret;
2644}
2645
ec013e7f
JB		 2646static int i915_energy_uJ(struct seq_file *m, void *data)
2647{
36cdd013 2648 struct drm_i915_private *dev_priv = node_to_i915(m->private);
ec013e7f
JB		 2649 u64 power;
2650 u32 units;
2651
36cdd013 2652 if (INTEL_GEN(dev_priv) < 6)
ec013e7f
JB		 2653 return -ENODEV;
2654
36623ef8
PZ		 2655 intel_runtime_pm_get(dev_priv);
2656
ec013e7f
JB		 2657 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2658 power = (power & 0x1f00) >> 8;
2659 units = 1000000 / (1 << power); /* convert to uJ */
2660 power = I915_READ(MCH_SECP_NRG_STTS);
2661 power *= units;
2662
36623ef8
PZ		 2663 intel_runtime_pm_put(dev_priv);
2664
ec013e7f 2665 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2666
2667 return 0;
2668}
2669
6455c870 2670static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2671{
36cdd013 2672 struct drm_i915_private *dev_priv = node_to_i915(m->private);
52a05c30 2673 struct pci_dev *pdev = dev_priv->drm.pdev;
371db66a 2674
a156e64d
CW		 2675 if (!HAS_RUNTIME_PM(dev_priv))
2676 seq_puts(m, "Runtime power management not supported\n");
371db66a 2677
67d97da3 2678 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
371db66a 2679 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2680 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2681#ifdef CONFIG_PM
a6aaec8b 2682 seq_printf(m, "Usage count: %d\n",
36cdd013 2683 atomic_read(&dev_priv->drm.dev->power.usage_count));
0d804184
CW		 2684#else
2685 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2686#endif
a156e64d 2687 seq_printf(m, "PCI device power state: %s [%d]\n",
52a05c30
DW		 2688 pci_power_name(pdev->current_state),
2689 pdev->current_state);
371db66a 2690
ec013e7f
JB		 2691 return 0;
2692}
2693
1da51581
ID		 2694static int i915_power_domain_info(struct seq_file *m, void *unused)
2695{
36cdd013 2696 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1da51581
ID		 2697 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2698 int i;
2699
2700 mutex_lock(&power_domains->lock);
2701
2702 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2703 for (i = 0; i < power_domains->power_well_count; i++) {
2704 struct i915_power_well *power_well;
2705 enum intel_display_power_domain power_domain;
2706
2707 power_well = &power_domains->power_wells[i];
2708 seq_printf(m, "%-25s %d\n", power_well->name,
2709 power_well->count);
2710
2711 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2712 power_domain++) {
2713 if (!(BIT(power_domain) & power_well->domains))
2714 continue;
2715
2716 seq_printf(m, " %-23s %d\n",
9895ad03 2717 intel_display_power_domain_str(power_domain),
1da51581
ID		 2718 power_domains->domain_use_count[power_domain]);
2719 }
2720 }
2721
2722 mutex_unlock(&power_domains->lock);
2723
2724 return 0;
2725}
2726
b7cec66d
DL		 2727static int i915_dmc_info(struct seq_file *m, void *unused)
2728{
36cdd013 2729 struct drm_i915_private *dev_priv = node_to_i915(m->private);
b7cec66d
DL		 2730 struct intel_csr *csr;
2731
36cdd013 2732 if (!HAS_CSR(dev_priv)) {
b7cec66d
DL		 2733 seq_puts(m, "not supported\n");
2734 return 0;
2735 }
2736
2737 csr = &dev_priv->csr;
2738
6fb403de
MK		 2739 intel_runtime_pm_get(dev_priv);
2740
b7cec66d
DL		 2741 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2742 seq_printf(m, "path: %s\n", csr->fw_path);
2743
2744 if (!csr->dmc_payload)
6fb403de 2745 goto out;
b7cec66d
DL		 2746
2747 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2748 CSR_VERSION_MINOR(csr->version));
2749
36cdd013 2750 if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
8337206d
DL		 2751 seq_printf(m, "DC3 -> DC5 count: %d\n",
2752 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2753 seq_printf(m, "DC5 -> DC6 count: %d\n",
2754 I915_READ(SKL_CSR_DC5_DC6_COUNT));
36cdd013 2755 } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
16e11b99
MK		 2756 seq_printf(m, "DC3 -> DC5 count: %d\n",
2757 I915_READ(BXT_CSR_DC3_DC5_COUNT));
8337206d
DL		 2758 }
2759
6fb403de
MK		 2760out:
2761 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2762 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2763 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2764
8337206d
DL		 2765 intel_runtime_pm_put(dev_priv);
2766
b7cec66d
DL		 2767 return 0;
2768}
2769
53f5e3ca
JB		 2770static void intel_seq_print_mode(struct seq_file *m, int tabs,
2771 struct drm_display_mode *mode)
2772{
2773 int i;
2774
2775 for (i = 0; i < tabs; i++)
2776 seq_putc(m, '\t');
2777
2778 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2779 mode->base.id, mode->name,
2780 mode->vrefresh, mode->clock,
2781 mode->hdisplay, mode->hsync_start,
2782 mode->hsync_end, mode->htotal,
2783 mode->vdisplay, mode->vsync_start,
2784 mode->vsync_end, mode->vtotal,
2785 mode->type, mode->flags);
2786}
2787
2788static void intel_encoder_info(struct seq_file *m,
2789 struct intel_crtc *intel_crtc,
2790 struct intel_encoder *intel_encoder)
2791{
36cdd013
DW		 2792 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2793 struct drm_device *dev = &dev_priv->drm;
53f5e3ca
JB		 2794 struct drm_crtc *crtc = &intel_crtc->base;
2795 struct intel_connector *intel_connector;
2796 struct drm_encoder *encoder;
2797
2798 encoder = &intel_encoder->base;
2799 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2800 encoder->base.id, encoder->name);
53f5e3ca
JB		 2801 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2802 struct drm_connector *connector = &intel_connector->base;
2803 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2804 connector->base.id,
c23cc417 2805 connector->name,
53f5e3ca
JB		 2806 drm_get_connector_status_name(connector->status));
2807 if (connector->status == connector_status_connected) {
2808 struct drm_display_mode *mode = &crtc->mode;
2809 seq_printf(m, ", mode:\n");
2810 intel_seq_print_mode(m, 2, mode);
2811 } else {
2812 seq_putc(m, '\n');
2813 }
2814 }
2815}
2816
2817static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2818{
36cdd013
DW		 2819 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2820 struct drm_device *dev = &dev_priv->drm;
53f5e3ca
JB		 2821 struct drm_crtc *crtc = &intel_crtc->base;
2822 struct intel_encoder *intel_encoder;
23a48d53
ML		 2823 struct drm_plane_state *plane_state = crtc->primary->state;
2824 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2825
23a48d53 2826 if (fb)
5aa8a937 2827 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2828 fb->base.id, plane_state->src_x >> 16,
2829 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2830 else
2831 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2832 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2833 intel_encoder_info(m, intel_crtc, intel_encoder);
2834}
2835
2836static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2837{
2838 struct drm_display_mode *mode = panel->fixed_mode;
2839
2840 seq_printf(m, "\tfixed mode:\n");
2841 intel_seq_print_mode(m, 2, mode);
2842}
2843
2844static void intel_dp_info(struct seq_file *m,
2845 struct intel_connector *intel_connector)
2846{
2847 struct intel_encoder *intel_encoder = intel_connector->encoder;
2848 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2849
2850 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2851 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
b6dabe3b 2852 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
53f5e3ca
JB		 2853 intel_panel_info(m, &intel_connector->panel);
2854}
2855
2856static void intel_hdmi_info(struct seq_file *m,
2857 struct intel_connector *intel_connector)
2858{
2859 struct intel_encoder *intel_encoder = intel_connector->encoder;
2860 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2861
742f491d 2862 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2863}
2864
2865static void intel_lvds_info(struct seq_file *m,
2866 struct intel_connector *intel_connector)
2867{
2868 intel_panel_info(m, &intel_connector->panel);
2869}
2870
2871static void intel_connector_info(struct seq_file *m,
2872 struct drm_connector *connector)
2873{
2874 struct intel_connector *intel_connector = to_intel_connector(connector);
2875 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2876 struct drm_display_mode *mode;
53f5e3ca
JB		 2877
2878 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2879 connector->base.id, connector->name,
53f5e3ca
JB		 2880 drm_get_connector_status_name(connector->status));
2881 if (connector->status == connector_status_connected) {
2882 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2883 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2884 connector->display_info.width_mm,
2885 connector->display_info.height_mm);
2886 seq_printf(m, "\tsubpixel order: %s\n",
2887 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2888 seq_printf(m, "\tCEA rev: %d\n",
2889 connector->display_info.cea_rev);
2890 }
ee648a74
ML		 2891
2892 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2893 return;
2894
2895 switch (connector->connector_type) {
2896 case DRM_MODE_CONNECTOR_DisplayPort:
2897 case DRM_MODE_CONNECTOR_eDP:
2898 intel_dp_info(m, intel_connector);
2899 break;
2900 case DRM_MODE_CONNECTOR_LVDS:
2901 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
36cd7444 2902 intel_lvds_info(m, intel_connector);
ee648a74
ML		 2903 break;
2904 case DRM_MODE_CONNECTOR_HDMIA:
2905 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2906 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2907 intel_hdmi_info(m, intel_connector);
2908 break;
2909 default:
2910 break;
36cd7444 2911 }
53f5e3ca 2912
f103fc7d
JB		 2913 seq_printf(m, "\tmodes:\n");
2914 list_for_each_entry(mode, &connector->modes, head)
2915 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2916}
2917
36cdd013 2918static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
065f2ec2 2919{
065f2ec2
CW		 2920 u32 state;
2921
36cdd013 2922 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
0b87c24e 2923 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
065f2ec2 2924 else
5efb3e28 2925 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2926
2927 return state;
2928}
2929
36cdd013
DW		 2930static bool cursor_position(struct drm_i915_private *dev_priv,
2931 int pipe, int *x, int *y)
065f2ec2 2932{
065f2ec2
CW		 2933 u32 pos;
2934
5efb3e28 2935 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2936
2937 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2938 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2939 *x = -*x;
2940
2941 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2942 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2943 *y = -*y;
2944
36cdd013 2945 return cursor_active(dev_priv, pipe);
065f2ec2
CW		 2946}
2947
3abc4e09
RF		 2948static const char *plane_type(enum drm_plane_type type)
2949{
2950 switch (type) {
2951 case DRM_PLANE_TYPE_OVERLAY:
2952 return "OVL";
2953 case DRM_PLANE_TYPE_PRIMARY:
2954 return "PRI";
2955 case DRM_PLANE_TYPE_CURSOR:
2956 return "CUR";
2957 /*
2958 * Deliberately omitting default: to generate compiler warnings
2959 * when a new drm_plane_type gets added.
2960 */
2961 }
2962
2963 return "unknown";
2964}
2965
2966static const char *plane_rotation(unsigned int rotation)
2967{
2968 static char buf[48];
2969 /*
2970 * According to doc only one DRM_ROTATE_ is allowed but this
2971 * will print them all to visualize if the values are misused
2972 */
2973 snprintf(buf, sizeof(buf),
2974 "%s%s%s%s%s%s(0x%08x)",
31ad61e4
JL		 2975 (rotation & DRM_ROTATE_0) ? "0 " : "",
2976 (rotation & DRM_ROTATE_90) ? "90 " : "",
2977 (rotation & DRM_ROTATE_180) ? "180 " : "",
2978 (rotation & DRM_ROTATE_270) ? "270 " : "",
2979 (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
2980 (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3abc4e09
RF		 2981 rotation);
2982
2983 return buf;
2984}
2985
2986static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2987{
36cdd013
DW		 2988 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2989 struct drm_device *dev = &dev_priv->drm;
3abc4e09
RF		 2990 struct intel_plane *intel_plane;
2991
2992 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2993 struct drm_plane_state *state;
2994 struct drm_plane *plane = &intel_plane->base;
2995
2996 if (!plane->state) {
2997 seq_puts(m, "plane->state is NULL!\n");
2998 continue;
2999 }
3000
3001 state = plane->state;
3002
3003 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3004 plane->base.id,
3005 plane_type(intel_plane->base.type),
3006 state->crtc_x, state->crtc_y,
3007 state->crtc_w, state->crtc_h,
3008 (state->src_x >> 16),
3009 ((state->src_x & 0xffff) * 15625) >> 10,
3010 (state->src_y >> 16),
3011 ((state->src_y & 0xffff) * 15625) >> 10,
3012 (state->src_w >> 16),
3013 ((state->src_w & 0xffff) * 15625) >> 10,
3014 (state->src_h >> 16),
3015 ((state->src_h & 0xffff) * 15625) >> 10,
3016 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3017 plane_rotation(state->rotation));
3018 }
3019}
3020
3021static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3022{
3023 struct intel_crtc_state *pipe_config;
3024 int num_scalers = intel_crtc->num_scalers;
3025 int i;
3026
3027 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3028
3029 /* Not all platformas have a scaler */
3030 if (num_scalers) {
3031 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3032 num_scalers,
3033 pipe_config->scaler_state.scaler_users,
3034 pipe_config->scaler_state.scaler_id);
3035
3036 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3037 struct intel_scaler *sc =
3038 &pipe_config->scaler_state.scalers[i];
3039
3040 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3041 i, yesno(sc->in_use), sc->mode);
3042 }
3043 seq_puts(m, "\n");
3044 } else {
3045 seq_puts(m, "\tNo scalers available on this platform\n");
3046 }
3047}
3048
53f5e3ca
JB		 3049static int i915_display_info(struct seq_file *m, void *unused)
3050{
36cdd013
DW		 3051 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3052 struct drm_device *dev = &dev_priv->drm;
065f2ec2 3053 struct intel_crtc *crtc;
53f5e3ca
JB		 3054 struct drm_connector *connector;
3055
b0e5ddf3 3056 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 3057 drm_modeset_lock_all(dev);
3058 seq_printf(m, "CRTC info\n");
3059 seq_printf(m, "---------\n");
d3fcc808 3060 for_each_intel_crtc(dev, crtc) {
065f2ec2 3061 bool active;
f77076c9 3062 struct intel_crtc_state *pipe_config;
065f2ec2 3063 int x, y;
53f5e3ca 3064
f77076c9
ML		 3065 pipe_config = to_intel_crtc_state(crtc->base.state);
3066
3abc4e09 3067 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
065f2ec2 3068 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9 3069 yesno(pipe_config->base.active),
3abc4e09
RF		 3070 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3071 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3072
f77076c9 3073 if (pipe_config->base.active) {
065f2ec2
CW		 3074 intel_crtc_info(m, crtc);
3075
36cdd013 3076 active = cursor_position(dev_priv, crtc->pipe, &x, &y);
57127efa 3077 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 3078 yesno(crtc->cursor_base),
3dd512fb
MR		 3079 x, y, crtc->base.cursor->state->crtc_w,
3080 crtc->base.cursor->state->crtc_h,
57127efa 3081 crtc->cursor_addr, yesno(active));
3abc4e09
RF		 3082 intel_scaler_info(m, crtc);
3083 intel_plane_info(m, crtc);
a23dc658 3084 }
cace841c
DV		 3085
3086 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3087 yesno(!crtc->cpu_fifo_underrun_disabled),
3088 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 3089 }
3090
3091 seq_printf(m, "\n");
3092 seq_printf(m, "Connector info\n");
3093 seq_printf(m, "--------------\n");
3094 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3095 intel_connector_info(m, connector);
3096 }
3097 drm_modeset_unlock_all(dev);
b0e5ddf3 3098 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 3099
3100 return 0;
3101}
3102
e04934cf
BW		 3103static int i915_semaphore_status(struct seq_file *m, void *unused)
3104{
36cdd013
DW		 3105 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3106 struct drm_device *dev = &dev_priv->drm;
e2f80391 3107 struct intel_engine_cs *engine;
36cdd013 3108 int num_rings = INTEL_INFO(dev_priv)->num_rings;
c3232b18
DG		 3109 enum intel_engine_id id;
3110 int j, ret;
e04934cf 3111
39df9190 3112 if (!i915.semaphores) {
e04934cf
BW		 3113 seq_puts(m, "Semaphores are disabled\n");
3114 return 0;
3115 }
3116
3117 ret = mutex_lock_interruptible(&dev->struct_mutex);
3118 if (ret)
3119 return ret;
03872064 3120 intel_runtime_pm_get(dev_priv);
e04934cf 3121
36cdd013 3122 if (IS_BROADWELL(dev_priv)) {
e04934cf
BW		 3123 struct page *page;
3124 uint64_t *seqno;
3125
51d545d0 3126 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
e04934cf
BW		 3127
3128 seqno = (uint64_t *)kmap_atomic(page);
c3232b18 3129 for_each_engine_id(engine, dev_priv, id) {
e04934cf
BW		 3130 uint64_t offset;
3131
e2f80391 3132 seq_printf(m, "%s\n", engine->name);
e04934cf
BW		 3133
3134 seq_puts(m, " Last signal:");
3135 for (j = 0; j < num_rings; j++) {
c3232b18 3136 offset = id * I915_NUM_ENGINES + j;
e04934cf
BW		 3137 seq_printf(m, "0x%08llx (0x%02llx) ",
3138 seqno[offset], offset * 8);
3139 }
3140 seq_putc(m, '\n');
3141
3142 seq_puts(m, " Last wait: ");
3143 for (j = 0; j < num_rings; j++) {
c3232b18 3144 offset = id + (j * I915_NUM_ENGINES);
e04934cf
BW		 3145 seq_printf(m, "0x%08llx (0x%02llx) ",
3146 seqno[offset], offset * 8);
3147 }
3148 seq_putc(m, '\n');
3149
3150 }
3151 kunmap_atomic(seqno);
3152 } else {
3153 seq_puts(m, " Last signal:");
b4ac5afc 3154 for_each_engine(engine, dev_priv)
e04934cf
BW		 3155 for (j = 0; j < num_rings; j++)
3156 seq_printf(m, "0x%08x\n",
e2f80391 3157 I915_READ(engine->semaphore.mbox.signal[j]));
e04934cf
BW		 3158 seq_putc(m, '\n');
3159 }
3160
3161 seq_puts(m, "\nSync seqno:\n");
b4ac5afc
DG		 3162 for_each_engine(engine, dev_priv) {
3163 for (j = 0; j < num_rings; j++)
e2f80391
TU		 3164 seq_printf(m, " 0x%08x ",
3165 engine->semaphore.sync_seqno[j]);
e04934cf
BW		 3166 seq_putc(m, '\n');
3167 }
3168 seq_putc(m, '\n');
3169
03872064 3170 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3171 mutex_unlock(&dev->struct_mutex);
3172 return 0;
3173}
3174
728e29d7
DV		 3175static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3176{
36cdd013
DW		 3177 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3178 struct drm_device *dev = &dev_priv->drm;
728e29d7
DV		 3179 int i;
3180
3181 drm_modeset_lock_all(dev);
3182 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3183 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3184
3185 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2dd66ebd
ML		 3186 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3187 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
728e29d7 3188 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3189 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3190 seq_printf(m, " dpll_md: 0x%08x\n",
3191 pll->config.hw_state.dpll_md);
3192 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3193 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3194 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3195 }
3196 drm_modeset_unlock_all(dev);
3197
3198 return 0;
3199}
3200
1ed1ef9d 3201static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3202{
3203 int i;
3204 int ret;
e2f80391 3205 struct intel_engine_cs *engine;
36cdd013
DW		 3206 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3207 struct drm_device *dev = &dev_priv->drm;
33136b06 3208 struct i915_workarounds *workarounds = &dev_priv->workarounds;
c3232b18 3209 enum intel_engine_id id;
888b5995 3210
888b5995
AS		 3211 ret = mutex_lock_interruptible(&dev->struct_mutex);
3212 if (ret)
3213 return ret;
3214
3215 intel_runtime_pm_get(dev_priv);
3216
33136b06 3217 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
c3232b18 3218 for_each_engine_id(engine, dev_priv, id)
33136b06 3219 seq_printf(m, "HW whitelist count for %s: %d\n",
c3232b18 3220 engine->name, workarounds->hw_whitelist_count[id]);
33136b06 3221 for (i = 0; i < workarounds->count; ++i) {
f0f59a00
VS		 3222 i915_reg_t addr;
3223 u32 mask, value, read;
2fa60f6d 3224 bool ok;
888b5995 3225
33136b06
AS		 3226 addr = workarounds->reg[i].addr;
3227 mask = workarounds->reg[i].mask;
3228 value = workarounds->reg[i].value;
2fa60f6d
MK		 3229 read = I915_READ(addr);
3230 ok = (value & mask) == (read & mask);
3231 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
f0f59a00 3232 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3233 }
3234
3235 intel_runtime_pm_put(dev_priv);
3236 mutex_unlock(&dev->struct_mutex);
3237
3238 return 0;
3239}
3240
c5511e44
DL		 3241static int i915_ddb_info(struct seq_file *m, void *unused)
3242{
36cdd013
DW		 3243 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3244 struct drm_device *dev = &dev_priv->drm;
c5511e44
DL		 3245 struct skl_ddb_allocation *ddb;
3246 struct skl_ddb_entry *entry;
3247 enum pipe pipe;
3248 int plane;
3249
36cdd013 3250 if (INTEL_GEN(dev_priv) < 9)
2fcffe19
DL		 3251 return 0;
3252
c5511e44
DL		 3253 drm_modeset_lock_all(dev);
3254
3255 ddb = &dev_priv->wm.skl_hw.ddb;
3256
3257 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3258
3259 for_each_pipe(dev_priv, pipe) {
3260 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3261
dd740780 3262 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3263 entry = &ddb->plane[pipe][plane];
3264 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3265 entry->start, entry->end,
3266 skl_ddb_entry_size(entry));
3267 }
3268
4969d33e 3269 entry = &ddb->plane[pipe][PLANE_CURSOR];
c5511e44
DL		 3270 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3271 entry->end, skl_ddb_entry_size(entry));
3272 }
3273
3274 drm_modeset_unlock_all(dev);
3275
3276 return 0;
3277}
3278
a54746e3 3279static void drrs_status_per_crtc(struct seq_file *m,
36cdd013
DW		 3280 struct drm_device *dev,
3281 struct intel_crtc *intel_crtc)
a54746e3 3282{
fac5e23e 3283 struct drm_i915_private *dev_priv = to_i915(dev);
a54746e3
VK		 3284 struct i915_drrs *drrs = &dev_priv->drrs;
3285 int vrefresh = 0;
26875fe5 3286 struct drm_connector *connector;
a54746e3 3287
26875fe5
ML		 3288 drm_for_each_connector(connector, dev) {
3289 if (connector->state->crtc != &intel_crtc->base)
3290 continue;
3291
3292 seq_printf(m, "%s:\n", connector->name);
a54746e3
VK		 3293 }
3294
3295 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3296 seq_puts(m, "\tVBT: DRRS_type: Static");
3297 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3298 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3299 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3300 seq_puts(m, "\tVBT: DRRS_type: None");
3301 else
3302 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3303
3304 seq_puts(m, "\n\n");
3305
f77076c9 3306 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3307 struct intel_panel *panel;
3308
3309 mutex_lock(&drrs->mutex);
3310 /* DRRS Supported */
3311 seq_puts(m, "\tDRRS Supported: Yes\n");
3312
3313 /* disable_drrs() will make drrs->dp NULL */
3314 if (!drrs->dp) {
3315 seq_puts(m, "Idleness DRRS: Disabled");
3316 mutex_unlock(&drrs->mutex);
3317 return;
3318 }
3319
3320 panel = &drrs->dp->attached_connector->panel;
3321 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3322 drrs->busy_frontbuffer_bits);
3323
3324 seq_puts(m, "\n\t\t");
3325 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3326 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3327 vrefresh = panel->fixed_mode->vrefresh;
3328 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3329 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3330 vrefresh = panel->downclock_mode->vrefresh;
3331 } else {
3332 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3333 drrs->refresh_rate_type);
3334 mutex_unlock(&drrs->mutex);
3335 return;
3336 }
3337 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3338
3339 seq_puts(m, "\n\t\t");
3340 mutex_unlock(&drrs->mutex);
3341 } else {
3342 /* DRRS not supported. Print the VBT parameter*/
3343 seq_puts(m, "\tDRRS Supported : No");
3344 }
3345 seq_puts(m, "\n");
3346}
3347
3348static int i915_drrs_status(struct seq_file *m, void *unused)
3349{
36cdd013
DW		 3350 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3351 struct drm_device *dev = &dev_priv->drm;
a54746e3
VK		 3352 struct intel_crtc *intel_crtc;
3353 int active_crtc_cnt = 0;
3354
26875fe5 3355 drm_modeset_lock_all(dev);
a54746e3 3356 for_each_intel_crtc(dev, intel_crtc) {
f77076c9 3357 if (intel_crtc->base.state->active) {
a54746e3
VK		 3358 active_crtc_cnt++;
3359 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3360
3361 drrs_status_per_crtc(m, dev, intel_crtc);
3362 }
a54746e3 3363 }
26875fe5 3364 drm_modeset_unlock_all(dev);
a54746e3
VK		 3365
3366 if (!active_crtc_cnt)
3367 seq_puts(m, "No active crtc found\n");
3368
3369 return 0;
3370}
3371
07144428
DL		 3372struct pipe_crc_info {
3373 const char *name;
36cdd013 3374 struct drm_i915_private *dev_priv;
07144428
DL		 3375 enum pipe pipe;
3376};
3377
11bed958
DA		 3378static int i915_dp_mst_info(struct seq_file *m, void *unused)
3379{
36cdd013
DW		 3380 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3381 struct drm_device *dev = &dev_priv->drm;
11bed958
DA		 3382 struct intel_encoder *intel_encoder;
3383 struct intel_digital_port *intel_dig_port;
b6dabe3b
ML		 3384 struct drm_connector *connector;
3385
11bed958 3386 drm_modeset_lock_all(dev);
b6dabe3b
ML		 3387 drm_for_each_connector(connector, dev) {
3388 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
11bed958 3389 continue;
b6dabe3b
ML		 3390
3391 intel_encoder = intel_attached_encoder(connector);
3392 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3393 continue;
3394
3395 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
11bed958
DA		 3396 if (!intel_dig_port->dp.can_mst)
3397 continue;
b6dabe3b 3398
40ae80cc
JB		 3399 seq_printf(m, "MST Source Port %c\n",
3400 port_name(intel_dig_port->port));
11bed958
DA		 3401 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3402 }
3403 drm_modeset_unlock_all(dev);
3404 return 0;
3405}
3406
07144428
DL		 3407static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3408{
be5c7a90 3409 struct pipe_crc_info *info = inode->i_private;
36cdd013 3410 struct drm_i915_private *dev_priv = info->dev_priv;
be5c7a90
DL		 3411 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3412
36cdd013 3413 if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
7eb1c496
DV		 3414 return -ENODEV;
3415
d538bbdf
DL		 3416 spin_lock_irq(&pipe_crc->lock);
3417
3418 if (pipe_crc->opened) {
3419 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3420 return -EBUSY; /* already open */
3421 }
3422
d538bbdf 3423 pipe_crc->opened = true;
07144428
DL		 3424 filep->private_data = inode->i_private;
3425
d538bbdf
DL		 3426 spin_unlock_irq(&pipe_crc->lock);
3427
07144428
DL		 3428 return 0;
3429}
3430
3431static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3432{
be5c7a90 3433 struct pipe_crc_info *info = inode->i_private;
36cdd013 3434 struct drm_i915_private *dev_priv = info->dev_priv;
be5c7a90
DL		 3435 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3436
d538bbdf
DL		 3437 spin_lock_irq(&pipe_crc->lock);
3438 pipe_crc->opened = false;
3439 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3440
07144428
DL		 3441 return 0;
3442}
3443
3444/* (6 fields, 8 chars each, space separated (5) + '\n') */
3445#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3446/* account for \'0' */
3447#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3448
3449static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3450{
d538bbdf
DL		 3451 assert_spin_locked(&pipe_crc->lock);
3452 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3453 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3454}
3455
3456static ssize_t
3457i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3458 loff_t *pos)
3459{
3460 struct pipe_crc_info *info = filep->private_data;
36cdd013 3461 struct drm_i915_private *dev_priv = info->dev_priv;
07144428
DL		 3462 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3463 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3464 int n_entries;
07144428
DL		 3465 ssize_t bytes_read;
3466
3467 /*
3468 * Don't allow user space to provide buffers not big enough to hold
3469 * a line of data.
3470 */
3471 if (count < PIPE_CRC_LINE_LEN)
3472 return -EINVAL;
3473
3474 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3475 return 0;
07144428
DL		 3476
3477 /* nothing to read */
d538bbdf 3478 spin_lock_irq(&pipe_crc->lock);
07144428 3479 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3480 int ret;
3481
3482 if (filep->f_flags & O_NONBLOCK) {
3483 spin_unlock_irq(&pipe_crc->lock);
07144428 3484 return -EAGAIN;
d538bbdf 3485 }
07144428 3486
d538bbdf
DL		 3487 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3488 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3489 if (ret) {
3490 spin_unlock_irq(&pipe_crc->lock);
3491 return ret;
3492 }
8bf1e9f1
SH		 3493 }
3494
07144428 3495 /* We now have one or more entries to read */
9ad6d99f 3496 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3497
07144428 3498 bytes_read = 0;
9ad6d99f
VS		 3499 while (n_entries > 0) {
3500 struct intel_pipe_crc_entry *entry =
3501 &pipe_crc->entries[pipe_crc->tail];
8bf1e9f1 3502
9ad6d99f
VS		 3503 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3504 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3505 break;
3506
3507 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3508 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3509
07144428
DL		 3510 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3511 "%8u %8x %8x %8x %8x %8x\n",
3512 entry->frame, entry->crc[0],
3513 entry->crc[1], entry->crc[2],
3514 entry->crc[3], entry->crc[4]);
3515
9ad6d99f
VS		 3516 spin_unlock_irq(&pipe_crc->lock);
3517
4e9121e6 3518 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
07144428 3519 return -EFAULT;
b2c88f5b 3520
9ad6d99f
VS		 3521 user_buf += PIPE_CRC_LINE_LEN;
3522 n_entries--;
3523
3524 spin_lock_irq(&pipe_crc->lock);
3525 }
8bf1e9f1 3526
d538bbdf
DL		 3527 spin_unlock_irq(&pipe_crc->lock);
3528
07144428
DL		 3529 return bytes_read;
3530}
3531
3532static const struct file_operations i915_pipe_crc_fops = {
3533 .owner = THIS_MODULE,
3534 .open = i915_pipe_crc_open,
3535 .read = i915_pipe_crc_read,
3536 .release = i915_pipe_crc_release,
3537};
3538
3539static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3540 {
3541 .name = "i915_pipe_A_crc",
3542 .pipe = PIPE_A,
3543 },
3544 {
3545 .name = "i915_pipe_B_crc",
3546 .pipe = PIPE_B,
3547 },
3548 {
3549 .name = "i915_pipe_C_crc",
3550 .pipe = PIPE_C,
3551 },
3552};
3553
3554static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3555 enum pipe pipe)
3556{
36cdd013 3557 struct drm_i915_private *dev_priv = to_i915(minor->dev);
07144428
DL		 3558 struct dentry *ent;
3559 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3560
36cdd013 3561 info->dev_priv = dev_priv;
07144428
DL		 3562 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3563 &i915_pipe_crc_fops);
f3c5fe97
WY		 3564 if (!ent)
3565 return -ENOMEM;
07144428
DL		 3566
3567 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3568}
3569
e8dfcf78 3570static const char * const pipe_crc_sources[] = {
926321d5
DV		 3571 "none",
3572 "plane1",
3573 "plane2",
3574 "pf",
5b3a856b 3575 "pipe",
3d099a05
DV		 3576 "TV",
3577 "DP-B",
3578 "DP-C",
3579 "DP-D",
46a19188 3580 "auto",
926321d5
DV		 3581};
3582
3583static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3584{
3585 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3586 return pipe_crc_sources[source];
3587}
3588
bd9db02f 3589static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5 3590{
36cdd013 3591 struct drm_i915_private *dev_priv = m->private;
926321d5
DV		 3592 int i;
3593
3594 for (i = 0; i < I915_MAX_PIPES; i++)
3595 seq_printf(m, "%c %s\n", pipe_name(i),
3596 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3597
3598 return 0;
3599}
3600
bd9db02f 3601static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5 3602{
36cdd013 3603 return single_open(file, display_crc_ctl_show, inode->i_private);
926321d5
DV		 3604}
3605
46a19188 3606static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3607 uint32_t *val)
3608{
46a19188
DV		 3609 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3610 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3611
3612 switch (*source) {
52f843f6
DV		 3613 case INTEL_PIPE_CRC_SOURCE_PIPE:
3614 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3615 break;
3616 case INTEL_PIPE_CRC_SOURCE_NONE:
3617 *val = 0;
3618 break;
3619 default:
3620 return -EINVAL;
3621 }
3622
3623 return 0;
3624}
3625
36cdd013
DW		 3626static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3627 enum pipe pipe,
46a19188
DV		 3628 enum intel_pipe_crc_source *source)
3629{
36cdd013 3630 struct drm_device *dev = &dev_priv->drm;
46a19188
DV		 3631 struct intel_encoder *encoder;
3632 struct intel_crtc *crtc;
26756809 3633 struct intel_digital_port *dig_port;
46a19188
DV		 3634 int ret = 0;
3635
3636 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3637
6e9f798d 3638 drm_modeset_lock_all(dev);
b2784e15 3639 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3640 if (!encoder->base.crtc)
3641 continue;
3642
3643 crtc = to_intel_crtc(encoder->base.crtc);
3644
3645 if (crtc->pipe != pipe)
3646 continue;
3647
3648 switch (encoder->type) {
3649 case INTEL_OUTPUT_TVOUT:
3650 *source = INTEL_PIPE_CRC_SOURCE_TV;
3651 break;
cca0502b 3652 case INTEL_OUTPUT_DP:
46a19188 3653 case INTEL_OUTPUT_EDP:
26756809
DV		 3654 dig_port = enc_to_dig_port(&encoder->base);
3655 switch (dig_port->port) {
3656 case PORT_B:
3657 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3658 break;
3659 case PORT_C:
3660 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3661 break;
3662 case PORT_D:
3663 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3664 break;
3665 default:
3666 WARN(1, "nonexisting DP port %c\n",
3667 port_name(dig_port->port));
3668 break;
3669 }
46a19188 3670 break;
6847d71b
PZ		 3671 default:
3672 break;
46a19188
DV		 3673 }
3674 }
6e9f798d 3675 drm_modeset_unlock_all(dev);
46a19188
DV		 3676
3677 return ret;
3678}
3679
36cdd013 3680static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
46a19188
DV		 3681 enum pipe pipe,
3682 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3683 uint32_t *val)
3684{
8d2f24ca
DV		 3685 bool need_stable_symbols = false;
3686
46a19188 3687 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
36cdd013 3688 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
46a19188
DV		 3689 if (ret)
3690 return ret;
3691 }
3692
3693 switch (*source) {
7ac0129b
DV		 3694 case INTEL_PIPE_CRC_SOURCE_PIPE:
3695 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3696 break;
3697 case INTEL_PIPE_CRC_SOURCE_DP_B:
3698 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3699 need_stable_symbols = true;
7ac0129b
DV		 3700 break;
3701 case INTEL_PIPE_CRC_SOURCE_DP_C:
3702 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3703 need_stable_symbols = true;
7ac0129b 3704 break;
2be57922 3705 case INTEL_PIPE_CRC_SOURCE_DP_D:
36cdd013 3706 if (!IS_CHERRYVIEW(dev_priv))
2be57922
VS		 3707 return -EINVAL;
3708 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3709 need_stable_symbols = true;
3710 break;
7ac0129b
DV		 3711 case INTEL_PIPE_CRC_SOURCE_NONE:
3712 *val = 0;
3713 break;
3714 default:
3715 return -EINVAL;
3716 }
3717
8d2f24ca
DV		 3718 /*
3719 * When the pipe CRC tap point is after the transcoders we need
3720 * to tweak symbol-level features to produce a deterministic series of
3721 * symbols for a given frame. We need to reset those features only once
3722 * a frame (instead of every nth symbol):
3723 * - DC-balance: used to ensure a better clock recovery from the data
3724 * link (SDVO)
3725 * - DisplayPort scrambling: used for EMI reduction
3726 */
3727 if (need_stable_symbols) {
3728 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3729
8d2f24ca 3730 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3731 switch (pipe) {
3732 case PIPE_A:
8d2f24ca 3733 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3734 break;
3735 case PIPE_B:
8d2f24ca 3736 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3737 break;
3738 case PIPE_C:
3739 tmp |= PIPE_C_SCRAMBLE_RESET;
3740 break;
3741 default:
3742 return -EINVAL;
3743 }
8d2f24ca
DV		 3744 I915_WRITE(PORT_DFT2_G4X, tmp);
3745 }
3746
7ac0129b
DV		 3747 return 0;
3748}
3749
36cdd013 3750static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
46a19188
DV		 3751 enum pipe pipe,
3752 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3753 uint32_t *val)
3754{
84093603
DV		 3755 bool need_stable_symbols = false;
3756
46a19188 3757 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
36cdd013 3758 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
46a19188
DV		 3759 if (ret)
3760 return ret;
3761 }
3762
3763 switch (*source) {
4b79ebf7
DV		 3764 case INTEL_PIPE_CRC_SOURCE_PIPE:
3765 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3766 break;
3767 case INTEL_PIPE_CRC_SOURCE_TV:
36cdd013 3768 if (!SUPPORTS_TV(dev_priv))
4b79ebf7
DV		 3769 return -EINVAL;
3770 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3771 break;
3772 case INTEL_PIPE_CRC_SOURCE_DP_B:
36cdd013 3773 if (!IS_G4X(dev_priv))
4b79ebf7
DV		 3774 return -EINVAL;
3775 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3776 need_stable_symbols = true;
4b79ebf7
DV		 3777 break;
3778 case INTEL_PIPE_CRC_SOURCE_DP_C:
36cdd013 3779 if (!IS_G4X(dev_priv))
4b79ebf7
DV		 3780 return -EINVAL;
3781 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3782 need_stable_symbols = true;
4b79ebf7
DV		 3783 break;
3784 case INTEL_PIPE_CRC_SOURCE_DP_D:
36cdd013 3785 if (!IS_G4X(dev_priv))
4b79ebf7
DV		 3786 return -EINVAL;
3787 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3788 need_stable_symbols = true;
4b79ebf7
DV		 3789 break;
3790 case INTEL_PIPE_CRC_SOURCE_NONE:
3791 *val = 0;
3792 break;
3793 default:
3794 return -EINVAL;
3795 }
3796
84093603
DV		 3797 /*
3798 * When the pipe CRC tap point is after the transcoders we need
3799 * to tweak symbol-level features to produce a deterministic series of
3800 * symbols for a given frame. We need to reset those features only once
3801 * a frame (instead of every nth symbol):
3802 * - DC-balance: used to ensure a better clock recovery from the data
3803 * link (SDVO)
3804 * - DisplayPort scrambling: used for EMI reduction
3805 */
3806 if (need_stable_symbols) {
3807 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3808
36cdd013 3809 WARN_ON(!IS_G4X(dev_priv));
84093603
DV		 3810
3811 I915_WRITE(PORT_DFT_I9XX,
3812 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3813
3814 if (pipe == PIPE_A)
3815 tmp |= PIPE_A_SCRAMBLE_RESET;
3816 else
3817 tmp |= PIPE_B_SCRAMBLE_RESET;
3818
3819 I915_WRITE(PORT_DFT2_G4X, tmp);
3820 }
3821
4b79ebf7
DV		 3822 return 0;
3823}
3824
36cdd013 3825static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
8d2f24ca
DV		 3826 enum pipe pipe)
3827{
8d2f24ca
DV		 3828 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3829
eb736679
VS		 3830 switch (pipe) {
3831 case PIPE_A:
8d2f24ca 3832 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3833 break;
3834 case PIPE_B:
8d2f24ca 3835 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3836 break;
3837 case PIPE_C:
3838 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3839 break;
3840 default:
3841 return;
3842 }
8d2f24ca
DV		 3843 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3844 tmp &= ~DC_BALANCE_RESET_VLV;
3845 I915_WRITE(PORT_DFT2_G4X, tmp);
3846
3847}
3848
36cdd013 3849static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
84093603
DV		 3850 enum pipe pipe)
3851{
84093603
DV		 3852 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3853
3854 if (pipe == PIPE_A)
3855 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3856 else
3857 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3858 I915_WRITE(PORT_DFT2_G4X, tmp);
3859
3860 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3861 I915_WRITE(PORT_DFT_I9XX,
3862 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3863 }
3864}
3865
46a19188 3866static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3867 uint32_t *val)
3868{
46a19188
DV		 3869 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3870 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3871
3872 switch (*source) {
5b3a856b
DV		 3873 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3874 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3875 break;
3876 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3877 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3878 break;
5b3a856b
DV		 3879 case INTEL_PIPE_CRC_SOURCE_PIPE:
3880 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3881 break;
3d099a05 3882 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3883 *val = 0;
3884 break;
3d099a05
DV		 3885 default:
3886 return -EINVAL;
5b3a856b
DV		 3887 }
3888
3889 return 0;
3890}
3891
36cdd013
DW		 3892static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
3893 bool enable)
fabf6e51 3894{
36cdd013 3895 struct drm_device *dev = &dev_priv->drm;
fabf6e51
DV		 3896 struct intel_crtc *crtc =
3897 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3898 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3899 struct drm_atomic_state *state;
3900 int ret = 0;
fabf6e51
DV		 3901
3902 drm_modeset_lock_all(dev);
c4e2d043
ML		 3903 state = drm_atomic_state_alloc(dev);
3904 if (!state) {
3905 ret = -ENOMEM;
3906 goto out;
fabf6e51 3907 }
fabf6e51 3908
c4e2d043
ML		 3909 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3910 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3911 if (IS_ERR(pipe_config)) {
3912 ret = PTR_ERR(pipe_config);
3913 goto out;
3914 }
fabf6e51 3915
c4e2d043
ML		 3916 pipe_config->pch_pfit.force_thru = enable;
3917 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3918 pipe_config->pch_pfit.enabled != enable)
3919 pipe_config->base.connectors_changed = true;
1b509259 3920
c4e2d043
ML		 3921 ret = drm_atomic_commit(state);
3922out:
fabf6e51 3923 drm_modeset_unlock_all(dev);
c4e2d043
ML		 3924 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3925 if (ret)
3926 drm_atomic_state_free(state);
fabf6e51
DV		 3927}
3928
36cdd013 3929static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
fabf6e51
DV		 3930 enum pipe pipe,
3931 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3932 uint32_t *val)
3933{
46a19188
DV		 3934 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3935 *source = INTEL_PIPE_CRC_SOURCE_PF;
3936
3937 switch (*source) {
5b3a856b
DV		 3938 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3939 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3940 break;
3941 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3942 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3943 break;
3944 case INTEL_PIPE_CRC_SOURCE_PF:
36cdd013
DW		 3945 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
3946 hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
fabf6e51 3947
5b3a856b
DV		 3948 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3949 break;
3d099a05 3950 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3951 *val = 0;
3952 break;
3d099a05
DV		 3953 default:
3954 return -EINVAL;
5b3a856b
DV		 3955 }
3956
3957 return 0;
3958}
3959
36cdd013
DW		 3960static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
3961 enum pipe pipe,
926321d5
DV		 3962 enum intel_pipe_crc_source source)
3963{
36cdd013 3964 struct drm_device *dev = &dev_priv->drm;
cc3da175 3965 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
36cdd013
DW		 3966 struct intel_crtc *crtc =
3967 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
e129649b 3968 enum intel_display_power_domain power_domain;
432f3342 3969 u32 val = 0; /* shut up gcc */
5b3a856b 3970 int ret;
926321d5 3971
cc3da175
DL		 3972 if (pipe_crc->source == source)
3973 return 0;
3974
ae676fcd
DL		 3975 /* forbid changing the source without going back to 'none' */
3976 if (pipe_crc->source && source)
3977 return -EINVAL;
3978
e129649b
ID		 3979 power_domain = POWER_DOMAIN_PIPE(pipe);
3980 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9d8b0588
DV		 3981 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3982 return -EIO;
3983 }
3984
36cdd013 3985 if (IS_GEN2(dev_priv))
46a19188 3986 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
36cdd013
DW		 3987 else if (INTEL_GEN(dev_priv) < 5)
3988 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
3989 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3990 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
3991 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
46a19188 3992 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3993 else
36cdd013 3994 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
5b3a856b
DV		 3995
3996 if (ret != 0)
e129649b 3997 goto out;
5b3a856b 3998
4b584369
DL		 3999 /* none -> real source transition */
4000 if (source) {
4252fbc3
VS		 4001 struct intel_pipe_crc_entry *entries;
4002
7cd6ccff
DL		 4003 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4004 pipe_name(pipe), pipe_crc_source_name(source));
4005
3cf54b34
VS		 4006 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4007 sizeof(pipe_crc->entries[0]),
4252fbc3 4008 GFP_KERNEL);
e129649b
ID		 4009 if (!entries) {
4010 ret = -ENOMEM;
4011 goto out;
4012 }
e5f75aca 4013
8c740dce
PZ		 4014 /*
4015 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4016 * enabled and disabled dynamically based on package C states,
4017 * user space can't make reliable use of the CRCs, so let's just
4018 * completely disable it.
4019 */
4020 hsw_disable_ips(crtc);
4021
d538bbdf 4022 spin_lock_irq(&pipe_crc->lock);
64387b61 4023 kfree(pipe_crc->entries);
4252fbc3 4024 pipe_crc->entries = entries;
d538bbdf
DL		 4025 pipe_crc->head = 0;
4026 pipe_crc->tail = 0;
4027 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 4028 }
4029
cc3da175 4030 pipe_crc->source = source;
926321d5 4031
926321d5
DV		 4032 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4033 POSTING_READ(PIPE_CRC_CTL(pipe));
4034
e5f75aca
DL		 4035 /* real source -> none transition */
4036 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 4037 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 4038 struct intel_crtc *crtc =
4039 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 4040
7cd6ccff
DL		 4041 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4042 pipe_name(pipe));
4043
a33d7105 4044 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 4045 if (crtc->base.state->active)
a33d7105
DV		 4046 intel_wait_for_vblank(dev, pipe);
4047 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 4048
d538bbdf
DL		 4049 spin_lock_irq(&pipe_crc->lock);
4050 entries = pipe_crc->entries;
e5f75aca 4051 pipe_crc->entries = NULL;
9ad6d99f
VS		 4052 pipe_crc->head = 0;
4053 pipe_crc->tail = 0;
d538bbdf
DL		 4054 spin_unlock_irq(&pipe_crc->lock);
4055
4056 kfree(entries);
84093603 4057
36cdd013
DW		 4058 if (IS_G4X(dev_priv))
4059 g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4060 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4061 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4062 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4063 hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
8c740dce
PZ		 4064
4065 hsw_enable_ips(crtc);
e5f75aca
DL		 4066 }
4067
e129649b
ID		 4068 ret = 0;
4069
4070out:
4071 intel_display_power_put(dev_priv, power_domain);
4072
4073 return ret;
926321d5
DV		 4074}
4075
4076/*
4077 * Parse pipe CRC command strings:
b94dec87
DL		 4078 * command: wsp* object wsp+ name wsp+ source wsp*
4079 * object: 'pipe'
4080 * name: (A | B | C)
926321d5
DV		 4081 * source: (none | plane1 | plane2 | pf)
4082 * wsp: (#0x20 | #0x9 | #0xA)+
4083 *
4084 * eg.:
b94dec87
DL		 4085 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4086 * "pipe A none" -> Stop CRC
926321d5 4087 */
bd9db02f 4088static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 4089{
4090 int n_words = 0;
4091
4092 while (*buf) {
4093 char *end;
4094
4095 /* skip leading white space */
4096 buf = skip_spaces(buf);
4097 if (!*buf)
4098 break; /* end of buffer */
4099
4100 /* find end of word */
4101 for (end = buf; *end && !isspace(*end); end++)
4102 ;
4103
4104 if (n_words == max_words) {
4105 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4106 max_words);
4107 return -EINVAL; /* ran out of words[] before bytes */
4108 }
4109
4110 if (*end)
4111 *end++ = '\0';
4112 words[n_words++] = buf;
4113 buf = end;
4114 }
4115
4116 return n_words;
4117}
4118
b94dec87
DL		 4119enum intel_pipe_crc_object {
4120 PIPE_CRC_OBJECT_PIPE,
4121};
4122
e8dfcf78 4123static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4124 "pipe",
4125};
4126
4127static int
bd9db02f 4128display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4129{
4130 int i;
4131
4132 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4133 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4134 *o = i;
b94dec87
DL		 4135 return 0;
4136 }
4137
4138 return -EINVAL;
4139}
4140
bd9db02f 4141static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4142{
4143 const char name = buf[0];
4144
4145 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4146 return -EINVAL;
4147
4148 *pipe = name - 'A';
4149
4150 return 0;
4151}
4152
4153static int
bd9db02f 4154display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4155{
4156 int i;
4157
4158 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4159 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4160 *s = i;
926321d5
DV		 4161 return 0;
4162 }
4163
4164 return -EINVAL;
4165}
4166
36cdd013
DW		 4167static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4168 char *buf, size_t len)
926321d5 4169{
b94dec87 4170#define N_WORDS 3
926321d5 4171 int n_words;
b94dec87 4172 char *words[N_WORDS];
926321d5 4173 enum pipe pipe;
b94dec87 4174 enum intel_pipe_crc_object object;
926321d5
DV		 4175 enum intel_pipe_crc_source source;
4176
bd9db02f 4177 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4178 if (n_words != N_WORDS) {
4179 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4180 N_WORDS);
4181 return -EINVAL;
4182 }
4183
bd9db02f 4184 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4185 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4186 return -EINVAL;
4187 }
4188
bd9db02f 4189 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4190 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4191 return -EINVAL;
4192 }
4193
bd9db02f 4194 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4195 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4196 return -EINVAL;
4197 }
4198
36cdd013 4199 return pipe_crc_set_source(dev_priv, pipe, source);
926321d5
DV		 4200}
4201
bd9db02f
DL		 4202static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4203 size_t len, loff_t *offp)
926321d5
DV		 4204{
4205 struct seq_file *m = file->private_data;
36cdd013 4206 struct drm_i915_private *dev_priv = m->private;
926321d5
DV		 4207 char *tmpbuf;
4208 int ret;
4209
4210 if (len == 0)
4211 return 0;
4212
4213 if (len > PAGE_SIZE - 1) {
4214 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4215 PAGE_SIZE);
4216 return -E2BIG;
4217 }
4218
4219 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4220 if (!tmpbuf)
4221 return -ENOMEM;
4222
4223 if (copy_from_user(tmpbuf, ubuf, len)) {
4224 ret = -EFAULT;
4225 goto out;
4226 }
4227 tmpbuf[len] = '\0';
4228
36cdd013 4229 ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
926321d5
DV		 4230
4231out:
4232 kfree(tmpbuf);
4233 if (ret < 0)
4234 return ret;
4235
4236 *offp += len;
4237 return len;
4238}
4239
bd9db02f 4240static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4241 .owner = THIS_MODULE,
bd9db02f 4242 .open = display_crc_ctl_open,
926321d5
DV		 4243 .read = seq_read,
4244 .llseek = seq_lseek,
4245 .release = single_release,
bd9db02f 4246 .write = display_crc_ctl_write
926321d5
DV		 4247};
4248
eb3394fa 4249static ssize_t i915_displayport_test_active_write(struct file *file,
36cdd013
DW		 4250 const char __user *ubuf,
4251 size_t len, loff_t *offp)
eb3394fa
TP		 4252{
4253 char *input_buffer;
4254 int status = 0;
eb3394fa
TP		 4255 struct drm_device *dev;
4256 struct drm_connector *connector;
4257 struct list_head *connector_list;
4258 struct intel_dp *intel_dp;
4259 int val = 0;
4260
9aaffa34 4261 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4262
eb3394fa
TP		 4263 connector_list = &dev->mode_config.connector_list;
4264
4265 if (len == 0)
4266 return 0;
4267
4268 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4269 if (!input_buffer)
4270 return -ENOMEM;
4271
4272 if (copy_from_user(input_buffer, ubuf, len)) {
4273 status = -EFAULT;
4274 goto out;
4275 }
4276
4277 input_buffer[len] = '\0';
4278 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4279
4280 list_for_each_entry(connector, connector_list, head) {
eb3394fa
TP		 4281 if (connector->connector_type !=
4282 DRM_MODE_CONNECTOR_DisplayPort)
4283 continue;
4284
b8bb08ec 4285 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4286 connector->encoder != NULL) {
4287 intel_dp = enc_to_intel_dp(connector->encoder);
4288 status = kstrtoint(input_buffer, 10, &val);
4289 if (status < 0)
4290 goto out;
4291 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4292 /* To prevent erroneous activation of the compliance
4293 * testing code, only accept an actual value of 1 here
4294 */
4295 if (val == 1)
4296 intel_dp->compliance_test_active = 1;
4297 else
4298 intel_dp->compliance_test_active = 0;
4299 }
4300 }
4301out:
4302 kfree(input_buffer);
4303 if (status < 0)
4304 return status;
4305
4306 *offp += len;
4307 return len;
4308}
4309
4310static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4311{
4312 struct drm_device *dev = m->private;
4313 struct drm_connector *connector;
4314 struct list_head *connector_list = &dev->mode_config.connector_list;
4315 struct intel_dp *intel_dp;
4316
eb3394fa 4317 list_for_each_entry(connector, connector_list, head) {
eb3394fa
TP		 4318 if (connector->connector_type !=
4319 DRM_MODE_CONNECTOR_DisplayPort)
4320 continue;
4321
4322 if (connector->status == connector_status_connected &&
4323 connector->encoder != NULL) {
4324 intel_dp = enc_to_intel_dp(connector->encoder);
4325 if (intel_dp->compliance_test_active)
4326 seq_puts(m, "1");
4327 else
4328 seq_puts(m, "0");
4329 } else
4330 seq_puts(m, "0");
4331 }
4332
4333 return 0;
4334}
4335
4336static int i915_displayport_test_active_open(struct inode *inode,
36cdd013 4337 struct file *file)
eb3394fa 4338{
36cdd013 4339 struct drm_i915_private *dev_priv = inode->i_private;
eb3394fa 4340
36cdd013
DW		 4341 return single_open(file, i915_displayport_test_active_show,
4342 &dev_priv->drm);
eb3394fa
TP		 4343}
4344
4345static const struct file_operations i915_displayport_test_active_fops = {
4346 .owner = THIS_MODULE,
4347 .open = i915_displayport_test_active_open,
4348 .read = seq_read,
4349 .llseek = seq_lseek,
4350 .release = single_release,
4351 .write = i915_displayport_test_active_write
4352};
4353
4354static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4355{
4356 struct drm_device *dev = m->private;
4357 struct drm_connector *connector;
4358 struct list_head *connector_list = &dev->mode_config.connector_list;
4359 struct intel_dp *intel_dp;
4360
eb3394fa 4361 list_for_each_entry(connector, connector_list, head) {
eb3394fa
TP		 4362 if (connector->connector_type !=
4363 DRM_MODE_CONNECTOR_DisplayPort)
4364 continue;
4365
4366 if (connector->status == connector_status_connected &&
4367 connector->encoder != NULL) {
4368 intel_dp = enc_to_intel_dp(connector->encoder);
4369 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4370 } else
4371 seq_puts(m, "0");
4372 }
4373
4374 return 0;
4375}
4376static int i915_displayport_test_data_open(struct inode *inode,
36cdd013 4377 struct file *file)
eb3394fa 4378{
36cdd013 4379 struct drm_i915_private *dev_priv = inode->i_private;
eb3394fa 4380
36cdd013
DW		 4381 return single_open(file, i915_displayport_test_data_show,
4382 &dev_priv->drm);
eb3394fa
TP		 4383}
4384
4385static const struct file_operations i915_displayport_test_data_fops = {
4386 .owner = THIS_MODULE,
4387 .open = i915_displayport_test_data_open,
4388 .read = seq_read,
4389 .llseek = seq_lseek,
4390 .release = single_release
4391};
4392
4393static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4394{
4395 struct drm_device *dev = m->private;
4396 struct drm_connector *connector;
4397 struct list_head *connector_list = &dev->mode_config.connector_list;
4398 struct intel_dp *intel_dp;
4399
eb3394fa 4400 list_for_each_entry(connector, connector_list, head) {
eb3394fa
TP		 4401 if (connector->connector_type !=
4402 DRM_MODE_CONNECTOR_DisplayPort)
4403 continue;
4404
4405 if (connector->status == connector_status_connected &&
4406 connector->encoder != NULL) {
4407 intel_dp = enc_to_intel_dp(connector->encoder);
4408 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4409 } else
4410 seq_puts(m, "0");
4411 }
4412
4413 return 0;
4414}
4415
4416static int i915_displayport_test_type_open(struct inode *inode,
4417 struct file *file)
4418{
36cdd013 4419 struct drm_i915_private *dev_priv = inode->i_private;
eb3394fa 4420
36cdd013
DW		 4421 return single_open(file, i915_displayport_test_type_show,
4422 &dev_priv->drm);
eb3394fa
TP		 4423}
4424
4425static const struct file_operations i915_displayport_test_type_fops = {
4426 .owner = THIS_MODULE,
4427 .open = i915_displayport_test_type_open,
4428 .read = seq_read,
4429 .llseek = seq_lseek,
4430 .release = single_release
4431};
4432
97e94b22 4433static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342 4434{
36cdd013
DW		 4435 struct drm_i915_private *dev_priv = m->private;
4436 struct drm_device *dev = &dev_priv->drm;
369a1342 4437 int level;
de38b95c
VS		 4438 int num_levels;
4439
36cdd013 4440 if (IS_CHERRYVIEW(dev_priv))
de38b95c 4441 num_levels = 3;
36cdd013 4442 else if (IS_VALLEYVIEW(dev_priv))
de38b95c
VS		 4443 num_levels = 1;
4444 else
4445 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4446
4447 drm_modeset_lock_all(dev);
4448
4449 for (level = 0; level < num_levels; level++) {
4450 unsigned int latency = wm[level];
4451
97e94b22
DL		 4452 /*
4453 * - WM1+ latency values in 0.5us units
de38b95c 4454 * - latencies are in us on gen9/vlv/chv
97e94b22 4455 */
36cdd013
DW		 4456 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4457 IS_CHERRYVIEW(dev_priv))
97e94b22
DL		 4458 latency *= 10;
4459 else if (level > 0)
369a1342
VS		 4460 latency *= 5;
4461
4462 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4463 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4464 }
4465
4466 drm_modeset_unlock_all(dev);
4467}
4468
4469static int pri_wm_latency_show(struct seq_file *m, void *data)
4470{
36cdd013 4471 struct drm_i915_private *dev_priv = m->private;
97e94b22
DL		 4472 const uint16_t *latencies;
4473
36cdd013 4474 if (INTEL_GEN(dev_priv) >= 9)
97e94b22
DL		 4475 latencies = dev_priv->wm.skl_latency;
4476 else
36cdd013 4477 latencies = dev_priv->wm.pri_latency;
369a1342 4478
97e94b22 4479 wm_latency_show(m, latencies);
369a1342
VS		 4480
4481 return 0;
4482}
4483
4484static int spr_wm_latency_show(struct seq_file *m, void *data)
4485{
36cdd013 4486 struct drm_i915_private *dev_priv = m->private;
97e94b22
DL		 4487 const uint16_t *latencies;
4488
36cdd013 4489 if (INTEL_GEN(dev_priv) >= 9)
97e94b22
DL		 4490 latencies = dev_priv->wm.skl_latency;
4491 else
36cdd013 4492 latencies = dev_priv->wm.spr_latency;
369a1342 4493
97e94b22 4494 wm_latency_show(m, latencies);
369a1342
VS		 4495
4496 return 0;
4497}
4498
4499static int cur_wm_latency_show(struct seq_file *m, void *data)
4500{
36cdd013 4501 struct drm_i915_private *dev_priv = m->private;
97e94b22
DL		 4502 const uint16_t *latencies;
4503
36cdd013 4504 if (INTEL_GEN(dev_priv) >= 9)
97e94b22
DL		 4505 latencies = dev_priv->wm.skl_latency;
4506 else
36cdd013 4507 latencies = dev_priv->wm.cur_latency;
369a1342 4508
97e94b22 4509 wm_latency_show(m, latencies);
369a1342
VS		 4510
4511 return 0;
4512}
4513
4514static int pri_wm_latency_open(struct inode *inode, struct file *file)
4515{
36cdd013 4516 struct drm_i915_private *dev_priv = inode->i_private;
369a1342 4517
36cdd013 4518 if (INTEL_GEN(dev_priv) < 5)
369a1342
VS		 4519 return -ENODEV;
4520
36cdd013 4521 return single_open(file, pri_wm_latency_show, dev_priv);
369a1342
VS		 4522}
4523
4524static int spr_wm_latency_open(struct inode *inode, struct file *file)
4525{
36cdd013 4526 struct drm_i915_private *dev_priv = inode->i_private;
369a1342 4527
36cdd013 4528 if (HAS_GMCH_DISPLAY(dev_priv))
369a1342
VS		 4529 return -ENODEV;
4530
36cdd013 4531 return single_open(file, spr_wm_latency_show, dev_priv);
369a1342
VS		 4532}
4533
4534static int cur_wm_latency_open(struct inode *inode, struct file *file)
4535{
36cdd013 4536 struct drm_i915_private *dev_priv = inode->i_private;
369a1342 4537
36cdd013 4538 if (HAS_GMCH_DISPLAY(dev_priv))
369a1342
VS		 4539 return -ENODEV;
4540
36cdd013 4541 return single_open(file, cur_wm_latency_show, dev_priv);
369a1342
VS		 4542}
4543
4544static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4545 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4546{
4547 struct seq_file *m = file->private_data;
36cdd013
DW		 4548 struct drm_i915_private *dev_priv = m->private;
4549 struct drm_device *dev = &dev_priv->drm;
97e94b22 4550 uint16_t new[8] = { 0 };
de38b95c 4551 int num_levels;
369a1342
VS		 4552 int level;
4553 int ret;
4554 char tmp[32];
4555
36cdd013 4556 if (IS_CHERRYVIEW(dev_priv))
de38b95c 4557 num_levels = 3;
36cdd013 4558 else if (IS_VALLEYVIEW(dev_priv))
de38b95c
VS		 4559 num_levels = 1;
4560 else
4561 num_levels = ilk_wm_max_level(dev) + 1;
4562
369a1342
VS		 4563 if (len >= sizeof(tmp))
4564 return -EINVAL;
4565
4566 if (copy_from_user(tmp, ubuf, len))
4567 return -EFAULT;
4568
4569 tmp[len] = '\0';
4570
97e94b22
DL		 4571 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4572 &new[0], &new[1], &new[2], &new[3],
4573 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4574 if (ret != num_levels)
4575 return -EINVAL;
4576
4577 drm_modeset_lock_all(dev);
4578
4579 for (level = 0; level < num_levels; level++)
4580 wm[level] = new[level];
4581
4582 drm_modeset_unlock_all(dev);
4583
4584 return len;
4585}
4586
4587
4588static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4589 size_t len, loff_t *offp)
4590{
4591 struct seq_file *m = file->private_data;
36cdd013 4592 struct drm_i915_private *dev_priv = m->private;
97e94b22 4593 uint16_t *latencies;
369a1342 4594
36cdd013 4595 if (INTEL_GEN(dev_priv) >= 9)
97e94b22
DL		 4596 latencies = dev_priv->wm.skl_latency;
4597 else
36cdd013 4598 latencies = dev_priv->wm.pri_latency;
97e94b22
DL		 4599
4600 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4601}
4602
4603static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4604 size_t len, loff_t *offp)
4605{
4606 struct seq_file *m = file->private_data;
36cdd013 4607 struct drm_i915_private *dev_priv = m->private;
97e94b22 4608 uint16_t *latencies;
369a1342 4609
36cdd013 4610 if (INTEL_GEN(dev_priv) >= 9)
97e94b22
DL		 4611 latencies = dev_priv->wm.skl_latency;
4612 else
36cdd013 4613 latencies = dev_priv->wm.spr_latency;
97e94b22
DL		 4614
4615 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4616}
4617
4618static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4619 size_t len, loff_t *offp)
4620{
4621 struct seq_file *m = file->private_data;
36cdd013 4622 struct drm_i915_private *dev_priv = m->private;
97e94b22
DL		 4623 uint16_t *latencies;
4624
36cdd013 4625 if (INTEL_GEN(dev_priv) >= 9)
97e94b22
DL		 4626 latencies = dev_priv->wm.skl_latency;
4627 else
36cdd013 4628 latencies = dev_priv->wm.cur_latency;
369a1342 4629
97e94b22 4630 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4631}
4632
4633static const struct file_operations i915_pri_wm_latency_fops = {
4634 .owner = THIS_MODULE,
4635 .open = pri_wm_latency_open,
4636 .read = seq_read,
4637 .llseek = seq_lseek,
4638 .release = single_release,
4639 .write = pri_wm_latency_write
4640};
4641
4642static const struct file_operations i915_spr_wm_latency_fops = {
4643 .owner = THIS_MODULE,
4644 .open = spr_wm_latency_open,
4645 .read = seq_read,
4646 .llseek = seq_lseek,
4647 .release = single_release,
4648 .write = spr_wm_latency_write
4649};
4650
4651static const struct file_operations i915_cur_wm_latency_fops = {
4652 .owner = THIS_MODULE,
4653 .open = cur_wm_latency_open,
4654 .read = seq_read,
4655 .llseek = seq_lseek,
4656 .release = single_release,
4657 .write = cur_wm_latency_write
4658};
4659
647416f9
KC		 4660static int
4661i915_wedged_get(void *data, u64 *val)
f3cd474b 4662{
36cdd013 4663 struct drm_i915_private *dev_priv = data;
f3cd474b 4664
d98c52cf 4665 *val = i915_terminally_wedged(&dev_priv->gpu_error);
f3cd474b 4666
647416f9 4667 return 0;
f3cd474b
CW		 4668}
4669
647416f9
KC		 4670static int
4671i915_wedged_set(void *data, u64 val)
f3cd474b 4672{
36cdd013 4673 struct drm_i915_private *dev_priv = data;
d46c0517 4674
b8d24a06
MK		 4675 /*
4676 * There is no safeguard against this debugfs entry colliding
4677 * with the hangcheck calling same i915_handle_error() in
4678 * parallel, causing an explosion. For now we assume that the
4679 * test harness is responsible enough not to inject gpu hangs
4680 * while it is writing to 'i915_wedged'
4681 */
4682
d98c52cf 4683 if (i915_reset_in_progress(&dev_priv->gpu_error))
b8d24a06
MK		 4684 return -EAGAIN;
4685
d46c0517 4686 intel_runtime_pm_get(dev_priv);
f3cd474b 4687
c033666a 4688 i915_handle_error(dev_priv, val,
58174462 4689 "Manually setting wedged to %llu", val);
d46c0517
ID		 4690
4691 intel_runtime_pm_put(dev_priv);
4692
647416f9 4693 return 0;
f3cd474b
CW		 4694}
4695
647416f9
KC		 4696DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4697 i915_wedged_get, i915_wedged_set,
3a3b4f98 4698 "%llu\n");
f3cd474b 4699
094f9a54
CW		 4700static int
4701i915_ring_missed_irq_get(void *data, u64 *val)
4702{
36cdd013 4703 struct drm_i915_private *dev_priv = data;
094f9a54
CW		 4704
4705 *val = dev_priv->gpu_error.missed_irq_rings;
4706 return 0;
4707}
4708
4709static int
4710i915_ring_missed_irq_set(void *data, u64 val)
4711{
36cdd013
DW		 4712 struct drm_i915_private *dev_priv = data;
4713 struct drm_device *dev = &dev_priv->drm;
094f9a54
CW		 4714 int ret;
4715
4716 /* Lock against concurrent debugfs callers */
4717 ret = mutex_lock_interruptible(&dev->struct_mutex);
4718 if (ret)
4719 return ret;
4720 dev_priv->gpu_error.missed_irq_rings = val;
4721 mutex_unlock(&dev->struct_mutex);
4722
4723 return 0;
4724}
4725
4726DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4727 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4728 "0x%08llx\n");
4729
4730static int
4731i915_ring_test_irq_get(void *data, u64 *val)
4732{
36cdd013 4733 struct drm_i915_private *dev_priv = data;
094f9a54
CW		 4734
4735 *val = dev_priv->gpu_error.test_irq_rings;
4736
4737 return 0;
4738}
4739
4740static int
4741i915_ring_test_irq_set(void *data, u64 val)
4742{
36cdd013 4743 struct drm_i915_private *dev_priv = data;
094f9a54 4744
3a122c27 4745 val &= INTEL_INFO(dev_priv)->ring_mask;
094f9a54 4746 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
094f9a54 4747 dev_priv->gpu_error.test_irq_rings = val;
094f9a54
CW		 4748
4749 return 0;
4750}
4751
4752DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4753 i915_ring_test_irq_get, i915_ring_test_irq_set,
4754 "0x%08llx\n");
4755
dd624afd
CW		 4756#define DROP_UNBOUND 0x1
4757#define DROP_BOUND 0x2
4758#define DROP_RETIRE 0x4
4759#define DROP_ACTIVE 0x8
4760#define DROP_ALL (DROP_UNBOUND | \
4761 DROP_BOUND | \
4762 DROP_RETIRE | \
4763 DROP_ACTIVE)
647416f9
KC		 4764static int
4765i915_drop_caches_get(void *data, u64 *val)
dd624afd 4766{
647416f9 4767 *val = DROP_ALL;
dd624afd 4768
647416f9 4769 return 0;
dd624afd
CW		 4770}
4771
647416f9
KC		 4772static int
4773i915_drop_caches_set(void *data, u64 val)
dd624afd 4774{
36cdd013
DW		 4775 struct drm_i915_private *dev_priv = data;
4776 struct drm_device *dev = &dev_priv->drm;
647416f9 4777 int ret;
dd624afd 4778
2f9fe5ff 4779 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4780
4781 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4782 * on ioctls on -EAGAIN. */
4783 ret = mutex_lock_interruptible(&dev->struct_mutex);
4784 if (ret)
4785 return ret;
4786
4787 if (val & DROP_ACTIVE) {
dcff85c8 4788 ret = i915_gem_wait_for_idle(dev_priv, true);
dd624afd
CW		 4789 if (ret)
4790 goto unlock;
4791 }
4792
4793 if (val & (DROP_RETIRE | DROP_ACTIVE))
c033666a 4794 i915_gem_retire_requests(dev_priv);
dd624afd 4795
21ab4e74
CW		 4796 if (val & DROP_BOUND)
4797 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4798
21ab4e74
CW		 4799 if (val & DROP_UNBOUND)
4800 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4801
4802unlock:
4803 mutex_unlock(&dev->struct_mutex);
4804
647416f9 4805 return ret;
dd624afd
CW		 4806}
4807
647416f9
KC		 4808DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4809 i915_drop_caches_get, i915_drop_caches_set,
4810 "0x%08llx\n");
dd624afd 4811
647416f9
KC		 4812static int
4813i915_max_freq_get(void *data, u64 *val)
358733e9 4814{
36cdd013 4815 struct drm_i915_private *dev_priv = data;
004777cb 4816
36cdd013 4817 if (INTEL_GEN(dev_priv) < 6)
004777cb
DV		 4818 return -ENODEV;
4819
7c59a9c1 4820 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
647416f9 4821 return 0;
358733e9
JB		 4822}
4823
647416f9
KC		 4824static int
4825i915_max_freq_set(void *data, u64 val)
358733e9 4826{
36cdd013 4827 struct drm_i915_private *dev_priv = data;
bc4d91f6 4828 u32 hw_max, hw_min;
647416f9 4829 int ret;
004777cb 4830
36cdd013 4831 if (INTEL_GEN(dev_priv) < 6)
004777cb 4832 return -ENODEV;
358733e9 4833
647416f9 4834 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4835
4fc688ce 4836 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4837 if (ret)
4838 return ret;
4839
358733e9
JB		 4840 /*
4841 * Turbo will still be enabled, but won't go above the set value.
4842 */
bc4d91f6 4843 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4844
bc4d91f6
AG		 4845 hw_max = dev_priv->rps.max_freq;
4846 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4847
b39fb297 4848 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4849 mutex_unlock(&dev_priv->rps.hw_lock);
4850 return -EINVAL;
0a073b84
JB		 4851 }
4852
b39fb297 4853 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4854
dc97997a 4855 intel_set_rps(dev_priv, val);
dd0a1aa1 4856
4fc688ce 4857 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4858
647416f9 4859 return 0;
358733e9
JB		 4860}
4861
647416f9
KC		 4862DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4863 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4864 "%llu\n");
358733e9 4865
647416f9
KC		 4866static int
4867i915_min_freq_get(void *data, u64 *val)
1523c310 4868{
36cdd013 4869 struct drm_i915_private *dev_priv = data;
004777cb 4870
62e1baa1 4871 if (INTEL_GEN(dev_priv) < 6)
004777cb
DV		 4872 return -ENODEV;
4873
7c59a9c1 4874 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
647416f9 4875 return 0;
1523c310
JB		 4876}
4877
647416f9
KC		 4878static int
4879i915_min_freq_set(void *data, u64 val)
1523c310 4880{
36cdd013 4881 struct drm_i915_private *dev_priv = data;
bc4d91f6 4882 u32 hw_max, hw_min;
647416f9 4883 int ret;
004777cb 4884
62e1baa1 4885 if (INTEL_GEN(dev_priv) < 6)
004777cb 4886 return -ENODEV;
1523c310 4887
647416f9 4888 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4889
4fc688ce 4890 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4891 if (ret)
4892 return ret;
4893
1523c310
JB		 4894 /*
4895 * Turbo will still be enabled, but won't go below the set value.
4896 */
bc4d91f6 4897 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4898
bc4d91f6
AG		 4899 hw_max = dev_priv->rps.max_freq;
4900 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4901
36cdd013
DW		 4902 if (val < hw_min ||
4903 val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4904 mutex_unlock(&dev_priv->rps.hw_lock);
4905 return -EINVAL;
0a073b84 4906 }
dd0a1aa1 4907
b39fb297 4908 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4909
dc97997a 4910 intel_set_rps(dev_priv, val);
dd0a1aa1 4911
4fc688ce 4912 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4913
647416f9 4914 return 0;
1523c310
JB		 4915}
4916
647416f9
KC		 4917DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4918 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4919 "%llu\n");
1523c310 4920
647416f9
KC		 4921static int
4922i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4923{
36cdd013
DW		 4924 struct drm_i915_private *dev_priv = data;
4925 struct drm_device *dev = &dev_priv->drm;
07b7ddd9 4926 u32 snpcr;
647416f9 4927 int ret;
07b7ddd9 4928
36cdd013 4929 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
004777cb
DV		 4930 return -ENODEV;
4931
22bcfc6a
DV		 4932 ret = mutex_lock_interruptible(&dev->struct_mutex);
4933 if (ret)
4934 return ret;
c8c8fb33 4935 intel_runtime_pm_get(dev_priv);
22bcfc6a 4936
07b7ddd9 4937 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4938
4939 intel_runtime_pm_put(dev_priv);
36cdd013 4940 mutex_unlock(&dev->struct_mutex);
07b7ddd9 4941
647416f9 4942 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4943
647416f9 4944 return 0;
07b7ddd9
JB		 4945}
4946
647416f9
KC		 4947static int
4948i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4949{
36cdd013 4950 struct drm_i915_private *dev_priv = data;
07b7ddd9 4951 u32 snpcr;
07b7ddd9 4952
36cdd013 4953 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
004777cb
DV		 4954 return -ENODEV;
4955
647416f9 4956 if (val > 3)
07b7ddd9
JB		 4957 return -EINVAL;
4958
c8c8fb33 4959 intel_runtime_pm_get(dev_priv);
647416f9 4960 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4961
4962 /* Update the cache sharing policy here as well */
4963 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4964 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4965 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4966 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4967
c8c8fb33 4968 intel_runtime_pm_put(dev_priv);
647416f9 4969 return 0;
07b7ddd9
JB		 4970}
4971
647416f9
KC		 4972DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4973 i915_cache_sharing_get, i915_cache_sharing_set,
4974 "%llu\n");
07b7ddd9 4975
36cdd013 4976static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
915490d5 4977 struct sseu_dev_info *sseu)
5d39525a 4978{
0a0b457f 4979 int ss_max = 2;
5d39525a
JM		 4980 int ss;
4981 u32 sig1[ss_max], sig2[ss_max];
4982
4983 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4984 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4985 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4986 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4987
4988 for (ss = 0; ss < ss_max; ss++) {
4989 unsigned int eu_cnt;
4990
4991 if (sig1[ss] & CHV_SS_PG_ENABLE)
4992 /* skip disabled subslice */
4993 continue;
4994
f08a0c92 4995 sseu->slice_mask = BIT(0);
57ec171e 4996 sseu->subslice_mask |= BIT(ss);
5d39525a
JM		 4997 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4998 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4999 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5000 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
915490d5
ID		 5001 sseu->eu_total += eu_cnt;
5002 sseu->eu_per_subslice = max_t(unsigned int,
5003 sseu->eu_per_subslice, eu_cnt);
5d39525a 5004 }
5d39525a
JM		 5005}
5006
36cdd013 5007static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
915490d5 5008 struct sseu_dev_info *sseu)
5d39525a 5009{
1c046bc1 5010 int s_max = 3, ss_max = 4;
5d39525a
JM		 5011 int s, ss;
5012 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5013
1c046bc1 5014 /* BXT has a single slice and at most 3 subslices. */
36cdd013 5015 if (IS_BROXTON(dev_priv)) {
1c046bc1
JM		 5016 s_max = 1;
5017 ss_max = 3;
5018 }
5019
5020 for (s = 0; s < s_max; s++) {
5021 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5022 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5023 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5024 }
5025
5d39525a
JM		 5026 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5027 GEN9_PGCTL_SSA_EU19_ACK |
5028 GEN9_PGCTL_SSA_EU210_ACK |
5029 GEN9_PGCTL_SSA_EU311_ACK;
5030 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5031 GEN9_PGCTL_SSB_EU19_ACK |
5032 GEN9_PGCTL_SSB_EU210_ACK |
5033 GEN9_PGCTL_SSB_EU311_ACK;
5034
5035 for (s = 0; s < s_max; s++) {
5036 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5037 /* skip disabled slice */
5038 continue;
5039
f08a0c92 5040 sseu->slice_mask |= BIT(s);
1c046bc1 5041
36cdd013 5042 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
57ec171e
ID		 5043 sseu->subslice_mask =
5044 INTEL_INFO(dev_priv)->sseu.subslice_mask;
1c046bc1 5045
5d39525a
JM		 5046 for (ss = 0; ss < ss_max; ss++) {
5047 unsigned int eu_cnt;
5048
57ec171e
ID		 5049 if (IS_BROXTON(dev_priv)) {
5050 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5051 /* skip disabled subslice */
5052 continue;
1c046bc1 5053
57ec171e
ID		 5054 sseu->subslice_mask |= BIT(ss);
5055 }
1c046bc1 5056
5d39525a
JM		 5057 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5058 eu_mask[ss%2]);
915490d5
ID		 5059 sseu->eu_total += eu_cnt;
5060 sseu->eu_per_subslice = max_t(unsigned int,
5061 sseu->eu_per_subslice,
5062 eu_cnt);
5d39525a
JM		 5063 }
5064 }
5065}
5066
36cdd013 5067static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
915490d5 5068 struct sseu_dev_info *sseu)
91bedd34 5069{
91bedd34 5070 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
36cdd013 5071 int s;
91bedd34 5072
f08a0c92 5073 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
91bedd34 5074
f08a0c92 5075 if (sseu->slice_mask) {
57ec171e 5076 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
43b67998
ID		 5077 sseu->eu_per_subslice =
5078 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
57ec171e
ID		 5079 sseu->eu_total = sseu->eu_per_subslice *
5080 sseu_subslice_total(sseu);
91bedd34
ŁD		 5081
5082 /* subtract fused off EU(s) from enabled slice(s) */
795b38b3 5083 for (s = 0; s < fls(sseu->slice_mask); s++) {
43b67998
ID		 5084 u8 subslice_7eu =
5085 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
91bedd34 5086
915490d5 5087 sseu->eu_total -= hweight8(subslice_7eu);
91bedd34
ŁD		 5088 }
5089 }
5090}
5091
615d8908
ID		 5092static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5093 const struct sseu_dev_info *sseu)
5094{
5095 struct drm_i915_private *dev_priv = node_to_i915(m->private);
5096 const char *type = is_available_info ? "Available" : "Enabled";
5097
c67ba538
ID		 5098 seq_printf(m, " %s Slice Mask: %04x\n", type,
5099 sseu->slice_mask);
615d8908 5100 seq_printf(m, " %s Slice Total: %u\n", type,
f08a0c92 5101 hweight8(sseu->slice_mask));
615d8908 5102 seq_printf(m, " %s Subslice Total: %u\n", type,
57ec171e 5103 sseu_subslice_total(sseu));
c67ba538
ID		 5104 seq_printf(m, " %s Subslice Mask: %04x\n", type,
5105 sseu->subslice_mask);
615d8908 5106 seq_printf(m, " %s Subslice Per Slice: %u\n", type,
57ec171e 5107 hweight8(sseu->subslice_mask));
615d8908
ID		 5108 seq_printf(m, " %s EU Total: %u\n", type,
5109 sseu->eu_total);
5110 seq_printf(m, " %s EU Per Subslice: %u\n", type,
5111 sseu->eu_per_subslice);
5112
5113 if (!is_available_info)
5114 return;
5115
5116 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5117 if (HAS_POOLED_EU(dev_priv))
5118 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool);
5119
5120 seq_printf(m, " Has Slice Power Gating: %s\n",
5121 yesno(sseu->has_slice_pg));
5122 seq_printf(m, " Has Subslice Power Gating: %s\n",
5123 yesno(sseu->has_subslice_pg));
5124 seq_printf(m, " Has EU Power Gating: %s\n",
5125 yesno(sseu->has_eu_pg));
5126}
5127
3873218f
JM		 5128static int i915_sseu_status(struct seq_file *m, void *unused)
5129{
36cdd013 5130 struct drm_i915_private *dev_priv = node_to_i915(m->private);
915490d5 5131 struct sseu_dev_info sseu;
3873218f 5132
36cdd013 5133 if (INTEL_GEN(dev_priv) < 8)
3873218f
JM		 5134 return -ENODEV;
5135
5136 seq_puts(m, "SSEU Device Info\n");
615d8908 5137 i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
3873218f 5138
7f992aba 5139 seq_puts(m, "SSEU Device Status\n");
915490d5 5140 memset(&sseu, 0, sizeof(sseu));
238010ed
DW		 5141
5142 intel_runtime_pm_get(dev_priv);
5143
36cdd013 5144 if (IS_CHERRYVIEW(dev_priv)) {
915490d5 5145 cherryview_sseu_device_status(dev_priv, &sseu);
36cdd013 5146 } else if (IS_BROADWELL(dev_priv)) {
915490d5 5147 broadwell_sseu_device_status(dev_priv, &sseu);
36cdd013 5148 } else if (INTEL_GEN(dev_priv) >= 9) {
915490d5 5149 gen9_sseu_device_status(dev_priv, &sseu);
7f992aba 5150 }
238010ed
DW		 5151
5152 intel_runtime_pm_put(dev_priv);
5153
615d8908 5154 i915_print_sseu_info(m, false, &sseu);
7f992aba 5155
3873218f
JM		 5156 return 0;
5157}
5158
6d794d42
BW		 5159static int i915_forcewake_open(struct inode *inode, struct file *file)
5160{
36cdd013 5161 struct drm_i915_private *dev_priv = inode->i_private;
6d794d42 5162
36cdd013 5163 if (INTEL_GEN(dev_priv) < 6)
6d794d42
BW		 5164 return 0;
5165
6daccb0b 5166 intel_runtime_pm_get(dev_priv);
59bad947 5167 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5168
5169 return 0;
5170}
5171
c43b5634 5172static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42 5173{
36cdd013 5174 struct drm_i915_private *dev_priv = inode->i_private;
6d794d42 5175
36cdd013 5176 if (INTEL_GEN(dev_priv) < 6)
6d794d42
BW		 5177 return 0;
5178
59bad947 5179 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5180 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5181
5182 return 0;
5183}
5184
5185static const struct file_operations i915_forcewake_fops = {
5186 .owner = THIS_MODULE,
5187 .open = i915_forcewake_open,
5188 .release = i915_forcewake_release,
5189};
5190
5191static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5192{
6d794d42
BW		 5193 struct dentry *ent;
5194
5195 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5196 S_IRUSR,
36cdd013 5197 root, to_i915(minor->dev),
6d794d42 5198 &i915_forcewake_fops);
f3c5fe97
WY		 5199 if (!ent)
5200 return -ENOMEM;
6d794d42 5201
8eb57294 5202 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5203}
5204
6a9c308d
DV		 5205static int i915_debugfs_create(struct dentry *root,
5206 struct drm_minor *minor,
5207 const char *name,
5208 const struct file_operations *fops)
07b7ddd9 5209{
07b7ddd9
JB		 5210 struct dentry *ent;
5211
6a9c308d 5212 ent = debugfs_create_file(name,
07b7ddd9 5213 S_IRUGO | S_IWUSR,
36cdd013 5214 root, to_i915(minor->dev),
6a9c308d 5215 fops);
f3c5fe97
WY		 5216 if (!ent)
5217 return -ENOMEM;
07b7ddd9 5218
6a9c308d 5219 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5220}
5221
06c5bf8c 5222static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5223 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5224 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5225 {"i915_gem_gtt", i915_gem_gtt_info, 0},
6da84829 5226 {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
6d2b8885 5227 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5228 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5229 {"i915_gem_request", i915_gem_request_info, 0},
5230 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5231 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5232 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5233 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5234 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5235 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5236 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5237 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5238 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5239 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5240 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5241 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5242 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5243 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5244 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5245 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5246 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5247 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5248 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5249 {"i915_sr_status", i915_sr_status, 0},
44834a67 5250 {"i915_opregion", i915_opregion, 0},
ada8f955 5251 {"i915_vbt", i915_vbt, 0},
37811fcc 5252 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5253 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5254 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5255 {"i915_execlists", i915_execlists, 0},
f65367b5 5256 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5257 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5258 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5259 {"i915_llc", i915_llc, 0},
e91fd8c6 5260 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5261 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5262 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5263 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5264 {"i915_power_domain_info", i915_power_domain_info, 0},
b7cec66d 5265 {"i915_dmc_info", i915_dmc_info, 0},
53f5e3ca 5266 {"i915_display_info", i915_display_info, 0},
e04934cf 5267 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5268 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5269 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5270 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5271 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5272 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5273 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5274 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5275};
27c202ad 5276#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5277
06c5bf8c 5278static const struct i915_debugfs_files {
34b9674c
DV		 5279 const char *name;
5280 const struct file_operations *fops;
5281} i915_debugfs_files[] = {
5282 {"i915_wedged", &i915_wedged_fops},
5283 {"i915_max_freq", &i915_max_freq_fops},
5284 {"i915_min_freq", &i915_min_freq_fops},
5285 {"i915_cache_sharing", &i915_cache_sharing_fops},
094f9a54
CW		 5286 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5287 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5288 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5289 {"i915_error_state", &i915_error_state_fops},
5290 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5291 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5292 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5293 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5294 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5295 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5296 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5297 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5298 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5299};
5300
36cdd013 5301void intel_display_crc_init(struct drm_i915_private *dev_priv)
07144428 5302{
b378360e 5303 enum pipe pipe;
07144428 5304
055e393f 5305 for_each_pipe(dev_priv, pipe) {
b378360e 5306 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5307
d538bbdf
DL		 5308 pipe_crc->opened = false;
5309 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5310 init_waitqueue_head(&pipe_crc->wq);
5311 }
5312}
5313
1dac891c 5314int i915_debugfs_register(struct drm_i915_private *dev_priv)
2017263e 5315{
91c8a326 5316 struct drm_minor *minor = dev_priv->drm.primary;
34b9674c 5317 int ret, i;
f3cd474b 5318
6d794d42 5319 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5320 if (ret)
5321 return ret;
6a9c308d 5322
07144428
DL		 5323 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5324 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5325 if (ret)
5326 return ret;
5327 }
5328
34b9674c
DV		 5329 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5330 ret = i915_debugfs_create(minor->debugfs_root, minor,
5331 i915_debugfs_files[i].name,
5332 i915_debugfs_files[i].fops);
5333 if (ret)
5334 return ret;
5335 }
40633219 5336
27c202ad
BG		 5337 return drm_debugfs_create_files(i915_debugfs_list,
5338 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5339 minor->debugfs_root, minor);
5340}
5341
1dac891c 5342void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
2017263e 5343{
91c8a326 5344 struct drm_minor *minor = dev_priv->drm.primary;
34b9674c
DV		 5345 int i;
5346
27c202ad
BG		 5347 drm_debugfs_remove_files(i915_debugfs_list,
5348 I915_DEBUGFS_ENTRIES, minor);
07144428 5349
36cdd013 5350 drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
6d794d42 5351 1, minor);
07144428 5352
e309a997 5353 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5354 struct drm_info_list *info_list =
5355 (struct drm_info_list *)&i915_pipe_crc_data[i];
5356
5357 drm_debugfs_remove_files(info_list, 1, minor);
5358 }
5359
34b9674c
DV		 5360 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5361 struct drm_info_list *info_list =
36cdd013 5362 (struct drm_info_list *)i915_debugfs_files[i].fops;
34b9674c
DV		 5363
5364 drm_debugfs_remove_files(info_list, 1, minor);
5365 }
2017263e 5366}
aa7471d2
JN		 5367
5368struct dpcd_block {
5369 /* DPCD dump start address. */
5370 unsigned int offset;
5371 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5372 unsigned int end;
5373 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5374 size_t size;
5375 /* Only valid for eDP. */
5376 bool edp;
5377};
5378
5379static const struct dpcd_block i915_dpcd_debug[] = {
5380 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5381 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5382 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5383 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5384 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5385 { .offset = DP_SET_POWER },
5386 { .offset = DP_EDP_DPCD_REV },
5387 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5388 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5389 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5390};
5391
5392static int i915_dpcd_show(struct seq_file *m, void *data)
5393{
5394 struct drm_connector *connector = m->private;
5395 struct intel_dp *intel_dp =
5396 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5397 uint8_t buf[16];
5398 ssize_t err;
5399 int i;
5400
5c1a8875
MK		 5401 if (connector->status != connector_status_connected)
5402 return -ENODEV;
5403
aa7471d2
JN		 5404 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5405 const struct dpcd_block *b = &i915_dpcd_debug[i];
5406 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5407
5408 if (b->edp &&
5409 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5410 continue;
5411
5412 /* low tech for now */
5413 if (WARN_ON(size > sizeof(buf)))
5414 continue;
5415
5416 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5417 if (err <= 0) {
5418 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5419 size, b->offset, err);
5420 continue;
5421 }
5422
5423 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5424 }
aa7471d2
JN		 5425
5426 return 0;
5427}
5428
5429static int i915_dpcd_open(struct inode *inode, struct file *file)
5430{
5431 return single_open(file, i915_dpcd_show, inode->i_private);
5432}
5433
5434static const struct file_operations i915_dpcd_fops = {
5435 .owner = THIS_MODULE,
5436 .open = i915_dpcd_open,
5437 .read = seq_read,
5438 .llseek = seq_lseek,
5439 .release = single_release,
5440};
5441
ecbd6781
DW		 5442static int i915_panel_show(struct seq_file *m, void *data)
5443{
5444 struct drm_connector *connector = m->private;
5445 struct intel_dp *intel_dp =
5446 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5447
5448 if (connector->status != connector_status_connected)
5449 return -ENODEV;
5450
5451 seq_printf(m, "Panel power up delay: %d\n",
5452 intel_dp->panel_power_up_delay);
5453 seq_printf(m, "Panel power down delay: %d\n",
5454 intel_dp->panel_power_down_delay);
5455 seq_printf(m, "Backlight on delay: %d\n",
5456 intel_dp->backlight_on_delay);
5457 seq_printf(m, "Backlight off delay: %d\n",
5458 intel_dp->backlight_off_delay);
5459
5460 return 0;
5461}
5462
5463static int i915_panel_open(struct inode *inode, struct file *file)
5464{
5465 return single_open(file, i915_panel_show, inode->i_private);
5466}
5467
5468static const struct file_operations i915_panel_fops = {
5469 .owner = THIS_MODULE,
5470 .open = i915_panel_open,
5471 .read = seq_read,
5472 .llseek = seq_lseek,
5473 .release = single_release,
5474};
5475
aa7471d2
JN		 5476/**
5477 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5478 * @connector: pointer to a registered drm_connector
5479 *
5480 * Cleanup will be done by drm_connector_unregister() through a call to
5481 * drm_debugfs_connector_remove().
5482 *
5483 * Returns 0 on success, negative error codes on error.
5484 */
5485int i915_debugfs_connector_add(struct drm_connector *connector)
5486{
5487 struct dentry *root = connector->debugfs_entry;
5488
5489 /* The connector must have been registered beforehands. */
5490 if (!root)
5491 return -ENODEV;
5492
5493 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5494 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
ecbd6781
DW		 5495 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5496 connector, &i915_dpcd_fops);
5497
5498 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5499 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5500 connector, &i915_panel_fops);
aa7471d2
JN		 5501
5502 return 0;
5503}
Linux kernel - Deliverables
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