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drm/i915: Convert hangcheck from a timer into a delayed work item
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
4feb7659 99 if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
fb1ae911 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
1d693bcc 130 get_global_flag(obj),
a05a5862 131 obj->base.size / 1024,
37811fcc
CW		 132 obj->base.read_domains,
133 obj->base.write_domain,
97b2a6a1
JH		 134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 142 list_for_each_entry(vma, &obj->vma_list, vma_link)
143 if (vma->pin_count > 0)
144 pin_count++;
145 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 146 if (obj->pin_display)
147 seq_printf(m, " (display)");
37811fcc
CW		 148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
fe14d5f4
TU		 155 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
156 vma->node.start, vma->node.size,
157 vma->ggtt_view.type);
1d693bcc 158 }
c1ad11fc
CW		 159 if (obj->stolen)
160 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 161 if (obj->pin_mappable || obj->fault_mappable) {
162 char s[3], *t = s;
163 if (obj->pin_mappable)
164 *t++ = 'p';
165 if (obj->fault_mappable)
166 *t++ = 'f';
167 *t = '\0';
168 seq_printf(m, " (%s mappable)", s);
169 }
41c52415
JH		 170 if (obj->last_read_req != NULL)
171 seq_printf(m, " (%s)",
172 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 175}
176
273497e5 177static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 178{
ea0c76f8 179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 185{
9f25d007 186 struct drm_info_node *node = m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
9f25d007 244 struct drm_info_node *node = m->private;
6d2b8885
CW		 245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6 303struct file_stats {
6313c204 304 struct drm_i915_file_private *file_priv;
2db8e9d6 305 int count;
c67a17e9
CW		 306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
2db8e9d6
CW		 309};
310
311static int per_file_stats(int id, void *ptr, void *data)
312{
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
6313c204 315 struct i915_vma *vma;
2db8e9d6
CW		 316
317 stats->count++;
318 stats->total += obj->base.size;
319
c67a17e9
CW		 320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
6313c204
CW		 323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 336 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 337 continue;
338
41c52415 339 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
2db8e9d6 346 } else {
6313c204
CW		 347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
41c52415 349 if (obj->active)
6313c204
CW		 350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
2db8e9d6
CW		 355 }
356
6313c204
CW		 357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
2db8e9d6
CW		 360 return 0;
361}
362
493018dc
BV		 363#define print_file_stats(m, name, stats) \
364 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
365 name, \
366 stats.count, \
367 stats.total, \
368 stats.active, \
369 stats.inactive, \
370 stats.global, \
371 stats.shared, \
372 stats.unbound)
373
374static void print_batch_pool_stats(struct seq_file *m,
375 struct drm_i915_private *dev_priv)
376{
377 struct drm_i915_gem_object *obj;
378 struct file_stats stats;
379
380 memset(&stats, 0, sizeof(stats));
381
382 list_for_each_entry(obj,
383 &dev_priv->mm.batch_pool.cache_list,
384 batch_pool_list)
385 per_file_stats(0, obj, &stats);
386
387 print_file_stats(m, "batch pool", stats);
388}
389
ca191b13
BW		 390#define count_vmas(list, member) do { \
391 list_for_each_entry(vma, list, member) { \
392 size += i915_gem_obj_ggtt_size(vma->obj); \
393 ++count; \
394 if (vma->obj->map_and_fenceable) { \
395 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
396 ++mappable_count; \
397 } \
398 } \
399} while (0)
400
401static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 402{
9f25d007 403 struct drm_info_node *node = m->private;
73aa808f
CW		 404 struct drm_device *dev = node->minor->dev;
405 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 406 u32 count, mappable_count, purgeable_count;
407 size_t size, mappable_size, purgeable_size;
6299f992 408 struct drm_i915_gem_object *obj;
5cef07e1 409 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 410 struct drm_file *file;
ca191b13 411 struct i915_vma *vma;
73aa808f
CW		 412 int ret;
413
414 ret = mutex_lock_interruptible(&dev->struct_mutex);
415 if (ret)
416 return ret;
417
6299f992
CW		 418 seq_printf(m, "%u objects, %zu bytes\n",
419 dev_priv->mm.object_count,
420 dev_priv->mm.object_memory);
421
422 size = count = mappable_size = mappable_count = 0;
35c20a60 423 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 424 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
425 count, mappable_count, size, mappable_size);
426
427 size = count = mappable_size = mappable_count = 0;
ca191b13 428 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 429 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
430 count, mappable_count, size, mappable_size);
431
6299f992 432 size = count = mappable_size = mappable_count = 0;
ca191b13 433 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 434 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
435 count, mappable_count, size, mappable_size);
436
b7abb714 437 size = count = purgeable_size = purgeable_count = 0;
35c20a60 438 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 439 size += obj->base.size, ++count;
b7abb714
CW		 440 if (obj->madv == I915_MADV_DONTNEED)
441 purgeable_size += obj->base.size, ++purgeable_count;
442 }
6c085a72
CW		 443 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
444
6299f992 445 size = count = mappable_size = mappable_count = 0;
35c20a60 446 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 447 if (obj->fault_mappable) {
f343c5f6 448 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 449 ++count;
450 }
451 if (obj->pin_mappable) {
f343c5f6 452 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 453 ++mappable_count;
454 }
b7abb714
CW		 455 if (obj->madv == I915_MADV_DONTNEED) {
456 purgeable_size += obj->base.size;
457 ++purgeable_count;
458 }
6299f992 459 }
b7abb714
CW		 460 seq_printf(m, "%u purgeable objects, %zu bytes\n",
461 purgeable_count, purgeable_size);
6299f992
CW		 462 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
463 mappable_count, mappable_size);
464 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
465 count, size);
466
93d18799 467 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 468 dev_priv->gtt.base.total,
469 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 470
493018dc
BV		 471 seq_putc(m, '\n');
472 print_batch_pool_stats(m, dev_priv);
473
267f0c90 474 seq_putc(m, '\n');
2db8e9d6
CW		 475 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
476 struct file_stats stats;
3ec2f427 477 struct task_struct *task;
2db8e9d6
CW		 478
479 memset(&stats, 0, sizeof(stats));
6313c204 480 stats.file_priv = file->driver_priv;
5b5ffff0 481 spin_lock(&file->table_lock);
2db8e9d6 482 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 483 spin_unlock(&file->table_lock);
3ec2f427
TH		 484 /*
485 * Although we have a valid reference on file->pid, that does
486 * not guarantee that the task_struct who called get_pid() is
487 * still alive (e.g. get_pid(current) => fork() => exit()).
488 * Therefore, we need to protect this ->comm access using RCU.
489 */
490 rcu_read_lock();
491 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 492 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 493 rcu_read_unlock();
2db8e9d6
CW		 494 }
495
73aa808f
CW		 496 mutex_unlock(&dev->struct_mutex);
497
498 return 0;
499}
500
aee56cff 501static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 502{
9f25d007 503 struct drm_info_node *node = m->private;
08c18323 504 struct drm_device *dev = node->minor->dev;
1b50247a 505 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 506 struct drm_i915_private *dev_priv = dev->dev_private;
507 struct drm_i915_gem_object *obj;
508 size_t total_obj_size, total_gtt_size;
509 int count, ret;
510
511 ret = mutex_lock_interruptible(&dev->struct_mutex);
512 if (ret)
513 return ret;
514
515 total_obj_size = total_gtt_size = count = 0;
35c20a60 516 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 517 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 518 continue;
519
267f0c90 520 seq_puts(m, " ");
08c18323 521 describe_obj(m, obj);
267f0c90 522 seq_putc(m, '\n');
08c18323 523 total_obj_size += obj->base.size;
f343c5f6 524 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 525 count++;
526 }
527
528 mutex_unlock(&dev->struct_mutex);
529
530 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
531 count, total_obj_size, total_gtt_size);
532
533 return 0;
534}
535
4e5359cd
SF		 536static int i915_gem_pageflip_info(struct seq_file *m, void *data)
537{
9f25d007 538 struct drm_info_node *node = m->private;
4e5359cd 539 struct drm_device *dev = node->minor->dev;
d6bbafa1 540 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 541 struct intel_crtc *crtc;
8a270ebf
DV		 542 int ret;
543
544 ret = mutex_lock_interruptible(&dev->struct_mutex);
545 if (ret)
546 return ret;
4e5359cd 547
d3fcc808 548 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 549 const char pipe = pipe_name(crtc->pipe);
550 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 551 struct intel_unpin_work *work;
552
5e2d7afc 553 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 554 work = crtc->unpin_work;
555 if (work == NULL) {
9db4a9c7 556 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 557 pipe, plane);
558 } else {
d6bbafa1
CW		 559 u32 addr;
560
e7d841ca 561 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 562 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 563 pipe, plane);
564 } else {
9db4a9c7 565 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 566 pipe, plane);
567 }
3a8a946e
DV		 568 if (work->flip_queued_req) {
569 struct intel_engine_cs *ring =
570 i915_gem_request_get_ring(work->flip_queued_req);
571
d6bbafa1 572 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
3a8a946e 573 ring->name,
f06cc1b9 574 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 575 dev_priv->next_seqno,
3a8a946e 576 ring->get_seqno(ring, true),
1b5a433a 577 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 578 } else
579 seq_printf(m, "Flip not associated with any ring\n");
580 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
581 work->flip_queued_vblank,
582 work->flip_ready_vblank,
583 drm_vblank_count(dev, crtc->pipe));
4e5359cd 584 if (work->enable_stall_check)
267f0c90 585 seq_puts(m, "Stall check enabled, ");
4e5359cd 586 else
267f0c90 587 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 588 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 589
d6bbafa1
CW		 590 if (INTEL_INFO(dev)->gen >= 4)
591 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
592 else
593 addr = I915_READ(DSPADDR(crtc->plane));
594 seq_printf(m, "Current scanout address 0x%08x\n", addr);
595
4e5359cd 596 if (work->pending_flip_obj) {
d6bbafa1
CW		 597 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
598 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 599 }
600 }
5e2d7afc 601 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 602 }
603
8a270ebf
DV		 604 mutex_unlock(&dev->struct_mutex);
605
4e5359cd
SF		 606 return 0;
607}
608
493018dc
BV		 609static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
610{
611 struct drm_info_node *node = m->private;
612 struct drm_device *dev = node->minor->dev;
613 struct drm_i915_private *dev_priv = dev->dev_private;
614 struct drm_i915_gem_object *obj;
615 int count = 0;
616 int ret;
617
618 ret = mutex_lock_interruptible(&dev->struct_mutex);
619 if (ret)
620 return ret;
621
622 seq_puts(m, "cache:\n");
623 list_for_each_entry(obj,
624 &dev_priv->mm.batch_pool.cache_list,
625 batch_pool_list) {
626 seq_puts(m, " ");
627 describe_obj(m, obj);
628 seq_putc(m, '\n');
629 count++;
630 }
631
632 seq_printf(m, "total: %d\n", count);
633
634 mutex_unlock(&dev->struct_mutex);
635
636 return 0;
637}
638
2017263e
BG		 639static int i915_gem_request_info(struct seq_file *m, void *data)
640{
9f25d007 641 struct drm_info_node *node = m->private;
2017263e 642 struct drm_device *dev = node->minor->dev;
e277a1f8 643 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 644 struct intel_engine_cs *ring;
2017263e 645 struct drm_i915_gem_request *gem_request;
a2c7f6fd 646 int ret, count, i;
de227ef0
CW		 647
648 ret = mutex_lock_interruptible(&dev->struct_mutex);
649 if (ret)
650 return ret;
2017263e 651
c2c347a9 652 count = 0;
a2c7f6fd
CW		 653 for_each_ring(ring, dev_priv, i) {
654 if (list_empty(&ring->request_list))
655 continue;
656
657 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 658 list_for_each_entry(gem_request,
a2c7f6fd 659 &ring->request_list,
c2c347a9
CW		 660 list) {
661 seq_printf(m, " %d @ %d\n",
662 gem_request->seqno,
663 (int) (jiffies - gem_request->emitted_jiffies));
664 }
665 count++;
2017263e 666 }
de227ef0
CW		 667 mutex_unlock(&dev->struct_mutex);
668
c2c347a9 669 if (count == 0)
267f0c90 670 seq_puts(m, "No requests\n");
c2c347a9 671
2017263e
BG		 672 return 0;
673}
674
b2223497 675static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 676 struct intel_engine_cs *ring)
b2223497
CW		 677{
678 if (ring->get_seqno) {
43a7b924 679 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 680 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 681 }
682}
683
2017263e
BG		 684static int i915_gem_seqno_info(struct seq_file *m, void *data)
685{
9f25d007 686 struct drm_info_node *node = m->private;
2017263e 687 struct drm_device *dev = node->minor->dev;
e277a1f8 688 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 689 struct intel_engine_cs *ring;
1ec14ad3 690 int ret, i;
de227ef0
CW		 691
692 ret = mutex_lock_interruptible(&dev->struct_mutex);
693 if (ret)
694 return ret;
c8c8fb33 695 intel_runtime_pm_get(dev_priv);
2017263e 696
a2c7f6fd
CW		 697 for_each_ring(ring, dev_priv, i)
698 i915_ring_seqno_info(m, ring);
de227ef0 699
c8c8fb33 700 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 701 mutex_unlock(&dev->struct_mutex);
702
2017263e
BG		 703 return 0;
704}
705
706
707static int i915_interrupt_info(struct seq_file *m, void *data)
708{
9f25d007 709 struct drm_info_node *node = m->private;
2017263e 710 struct drm_device *dev = node->minor->dev;
e277a1f8 711 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 712 struct intel_engine_cs *ring;
9db4a9c7 713 int ret, i, pipe;
de227ef0
CW		 714
715 ret = mutex_lock_interruptible(&dev->struct_mutex);
716 if (ret)
717 return ret;
c8c8fb33 718 intel_runtime_pm_get(dev_priv);
2017263e 719
74e1ca8c 720 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 721 seq_printf(m, "Master Interrupt Control:\t%08x\n",
722 I915_READ(GEN8_MASTER_IRQ));
723
724 seq_printf(m, "Display IER:\t%08x\n",
725 I915_READ(VLV_IER));
726 seq_printf(m, "Display IIR:\t%08x\n",
727 I915_READ(VLV_IIR));
728 seq_printf(m, "Display IIR_RW:\t%08x\n",
729 I915_READ(VLV_IIR_RW));
730 seq_printf(m, "Display IMR:\t%08x\n",
731 I915_READ(VLV_IMR));
055e393f 732 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 733 seq_printf(m, "Pipe %c stat:\t%08x\n",
734 pipe_name(pipe),
735 I915_READ(PIPESTAT(pipe)));
736
737 seq_printf(m, "Port hotplug:\t%08x\n",
738 I915_READ(PORT_HOTPLUG_EN));
739 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
740 I915_READ(VLV_DPFLIPSTAT));
741 seq_printf(m, "DPINVGTT:\t%08x\n",
742 I915_READ(DPINVGTT));
743
744 for (i = 0; i < 4; i++) {
745 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
746 i, I915_READ(GEN8_GT_IMR(i)));
747 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
748 i, I915_READ(GEN8_GT_IIR(i)));
749 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
750 i, I915_READ(GEN8_GT_IER(i)));
751 }
752
753 seq_printf(m, "PCU interrupt mask:\t%08x\n",
754 I915_READ(GEN8_PCU_IMR));
755 seq_printf(m, "PCU interrupt identity:\t%08x\n",
756 I915_READ(GEN8_PCU_IIR));
757 seq_printf(m, "PCU interrupt enable:\t%08x\n",
758 I915_READ(GEN8_PCU_IER));
759 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 760 seq_printf(m, "Master Interrupt Control:\t%08x\n",
761 I915_READ(GEN8_MASTER_IRQ));
762
763 for (i = 0; i < 4; i++) {
764 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
765 i, I915_READ(GEN8_GT_IMR(i)));
766 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
767 i, I915_READ(GEN8_GT_IIR(i)));
768 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
769 i, I915_READ(GEN8_GT_IER(i)));
770 }
771
055e393f 772 for_each_pipe(dev_priv, pipe) {
f458ebbc 773 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 774 POWER_DOMAIN_PIPE(pipe))) {
775 seq_printf(m, "Pipe %c power disabled\n",
776 pipe_name(pipe));
777 continue;
778 }
a123f157 779 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 780 pipe_name(pipe),
781 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 782 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 783 pipe_name(pipe),
784 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 785 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 786 pipe_name(pipe),
787 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 788 }
789
790 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
791 I915_READ(GEN8_DE_PORT_IMR));
792 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
793 I915_READ(GEN8_DE_PORT_IIR));
794 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
795 I915_READ(GEN8_DE_PORT_IER));
796
797 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
798 I915_READ(GEN8_DE_MISC_IMR));
799 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
800 I915_READ(GEN8_DE_MISC_IIR));
801 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
802 I915_READ(GEN8_DE_MISC_IER));
803
804 seq_printf(m, "PCU interrupt mask:\t%08x\n",
805 I915_READ(GEN8_PCU_IMR));
806 seq_printf(m, "PCU interrupt identity:\t%08x\n",
807 I915_READ(GEN8_PCU_IIR));
808 seq_printf(m, "PCU interrupt enable:\t%08x\n",
809 I915_READ(GEN8_PCU_IER));
810 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 811 seq_printf(m, "Display IER:\t%08x\n",
812 I915_READ(VLV_IER));
813 seq_printf(m, "Display IIR:\t%08x\n",
814 I915_READ(VLV_IIR));
815 seq_printf(m, "Display IIR_RW:\t%08x\n",
816 I915_READ(VLV_IIR_RW));
817 seq_printf(m, "Display IMR:\t%08x\n",
818 I915_READ(VLV_IMR));
055e393f 819 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 820 seq_printf(m, "Pipe %c stat:\t%08x\n",
821 pipe_name(pipe),
822 I915_READ(PIPESTAT(pipe)));
823
824 seq_printf(m, "Master IER:\t%08x\n",
825 I915_READ(VLV_MASTER_IER));
826
827 seq_printf(m, "Render IER:\t%08x\n",
828 I915_READ(GTIER));
829 seq_printf(m, "Render IIR:\t%08x\n",
830 I915_READ(GTIIR));
831 seq_printf(m, "Render IMR:\t%08x\n",
832 I915_READ(GTIMR));
833
834 seq_printf(m, "PM IER:\t\t%08x\n",
835 I915_READ(GEN6_PMIER));
836 seq_printf(m, "PM IIR:\t\t%08x\n",
837 I915_READ(GEN6_PMIIR));
838 seq_printf(m, "PM IMR:\t\t%08x\n",
839 I915_READ(GEN6_PMIMR));
840
841 seq_printf(m, "Port hotplug:\t%08x\n",
842 I915_READ(PORT_HOTPLUG_EN));
843 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
844 I915_READ(VLV_DPFLIPSTAT));
845 seq_printf(m, "DPINVGTT:\t%08x\n",
846 I915_READ(DPINVGTT));
847
848 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 849 seq_printf(m, "Interrupt enable: %08x\n",
850 I915_READ(IER));
851 seq_printf(m, "Interrupt identity: %08x\n",
852 I915_READ(IIR));
853 seq_printf(m, "Interrupt mask: %08x\n",
854 I915_READ(IMR));
055e393f 855 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 856 seq_printf(m, "Pipe %c stat: %08x\n",
857 pipe_name(pipe),
858 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 859 } else {
860 seq_printf(m, "North Display Interrupt enable: %08x\n",
861 I915_READ(DEIER));
862 seq_printf(m, "North Display Interrupt identity: %08x\n",
863 I915_READ(DEIIR));
864 seq_printf(m, "North Display Interrupt mask: %08x\n",
865 I915_READ(DEIMR));
866 seq_printf(m, "South Display Interrupt enable: %08x\n",
867 I915_READ(SDEIER));
868 seq_printf(m, "South Display Interrupt identity: %08x\n",
869 I915_READ(SDEIIR));
870 seq_printf(m, "South Display Interrupt mask: %08x\n",
871 I915_READ(SDEIMR));
872 seq_printf(m, "Graphics Interrupt enable: %08x\n",
873 I915_READ(GTIER));
874 seq_printf(m, "Graphics Interrupt identity: %08x\n",
875 I915_READ(GTIIR));
876 seq_printf(m, "Graphics Interrupt mask: %08x\n",
877 I915_READ(GTIMR));
878 }
a2c7f6fd 879 for_each_ring(ring, dev_priv, i) {
a123f157 880 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 881 seq_printf(m,
882 "Graphics Interrupt mask (%s): %08x\n",
883 ring->name, I915_READ_IMR(ring));
9862e600 884 }
a2c7f6fd 885 i915_ring_seqno_info(m, ring);
9862e600 886 }
c8c8fb33 887 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 888 mutex_unlock(&dev->struct_mutex);
889
2017263e
BG		 890 return 0;
891}
892
a6172a80
CW		 893static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
894{
9f25d007 895 struct drm_info_node *node = m->private;
a6172a80 896 struct drm_device *dev = node->minor->dev;
e277a1f8 897 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 898 int i, ret;
899
900 ret = mutex_lock_interruptible(&dev->struct_mutex);
901 if (ret)
902 return ret;
a6172a80
CW		 903
904 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
905 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
906 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 907 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 908
6c085a72
CW		 909 seq_printf(m, "Fence %d, pin count = %d, object = ",
910 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 911 if (obj == NULL)
267f0c90 912 seq_puts(m, "unused");
c2c347a9 913 else
05394f39 914 describe_obj(m, obj);
267f0c90 915 seq_putc(m, '\n');
a6172a80
CW		 916 }
917
05394f39 918 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 919 return 0;
920}
921
2017263e
BG		 922static int i915_hws_info(struct seq_file *m, void *data)
923{
9f25d007 924 struct drm_info_node *node = m->private;
2017263e 925 struct drm_device *dev = node->minor->dev;
e277a1f8 926 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 927 struct intel_engine_cs *ring;
1a240d4d 928 const u32 *hws;
4066c0ae
CW		 929 int i;
930
1ec14ad3 931 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 932 hws = ring->status_page.page_addr;
2017263e
BG		 933 if (hws == NULL)
934 return 0;
935
936 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
937 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
938 i * 4,
939 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
940 }
941 return 0;
942}
943
d5442303
DV		 944static ssize_t
945i915_error_state_write(struct file *filp,
946 const char __user *ubuf,
947 size_t cnt,
948 loff_t *ppos)
949{
edc3d884 950 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 951 struct drm_device *dev = error_priv->dev;
22bcfc6a 952 int ret;
d5442303
DV		 953
954 DRM_DEBUG_DRIVER("Resetting error state\n");
955
22bcfc6a
DV		 956 ret = mutex_lock_interruptible(&dev->struct_mutex);
957 if (ret)
958 return ret;
959
d5442303
DV		 960 i915_destroy_error_state(dev);
961 mutex_unlock(&dev->struct_mutex);
962
963 return cnt;
964}
965
966static int i915_error_state_open(struct inode *inode, struct file *file)
967{
968 struct drm_device *dev = inode->i_private;
d5442303 969 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 970
971 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
972 if (!error_priv)
973 return -ENOMEM;
974
975 error_priv->dev = dev;
976
95d5bfb3 977 i915_error_state_get(dev, error_priv);
d5442303 978
edc3d884
MK		 979 file->private_data = error_priv;
980
981 return 0;
d5442303
DV		 982}
983
984static int i915_error_state_release(struct inode *inode, struct file *file)
985{
edc3d884 986 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 987
95d5bfb3 988 i915_error_state_put(error_priv);
d5442303
DV		 989 kfree(error_priv);
990
edc3d884
MK		 991 return 0;
992}
993
4dc955f7
MK		 994static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
995 size_t count, loff_t *pos)
996{
997 struct i915_error_state_file_priv *error_priv = file->private_data;
998 struct drm_i915_error_state_buf error_str;
999 loff_t tmp_pos = 0;
1000 ssize_t ret_count = 0;
1001 int ret;
1002
0a4cd7c8 1003 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1004 if (ret)
1005 return ret;
edc3d884 1006
fc16b48b 1007 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1008 if (ret)
1009 goto out;
1010
edc3d884
MK		 1011 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1012 error_str.buf,
1013 error_str.bytes);
1014
1015 if (ret_count < 0)
1016 ret = ret_count;
1017 else
1018 *pos = error_str.start + ret_count;
1019out:
4dc955f7 1020 i915_error_state_buf_release(&error_str);
edc3d884 1021 return ret ?: ret_count;
d5442303
DV		 1022}
1023
1024static const struct file_operations i915_error_state_fops = {
1025 .owner = THIS_MODULE,
1026 .open = i915_error_state_open,
edc3d884 1027 .read = i915_error_state_read,
d5442303
DV		 1028 .write = i915_error_state_write,
1029 .llseek = default_llseek,
1030 .release = i915_error_state_release,
1031};
1032
647416f9
KC		 1033static int
1034i915_next_seqno_get(void *data, u64 *val)
40633219 1035{
647416f9 1036 struct drm_device *dev = data;
e277a1f8 1037 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1038 int ret;
1039
1040 ret = mutex_lock_interruptible(&dev->struct_mutex);
1041 if (ret)
1042 return ret;
1043
647416f9 1044 *val = dev_priv->next_seqno;
40633219
MK		 1045 mutex_unlock(&dev->struct_mutex);
1046
647416f9 1047 return 0;
40633219
MK		 1048}
1049
647416f9
KC		 1050static int
1051i915_next_seqno_set(void *data, u64 val)
1052{
1053 struct drm_device *dev = data;
40633219
MK		 1054 int ret;
1055
40633219
MK		 1056 ret = mutex_lock_interruptible(&dev->struct_mutex);
1057 if (ret)
1058 return ret;
1059
e94fbaa8 1060 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1061 mutex_unlock(&dev->struct_mutex);
1062
647416f9 1063 return ret;
40633219
MK		 1064}
1065
647416f9
KC		 1066DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1067 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1068 "0x%llx\n");
40633219 1069
adb4bd12 1070static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1071{
9f25d007 1072 struct drm_info_node *node = m->private;
f97108d1 1073 struct drm_device *dev = node->minor->dev;
e277a1f8 1074 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1075 int ret = 0;
1076
1077 intel_runtime_pm_get(dev_priv);
3b8d8d91 1078
5c9669ce
TR		 1079 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1080
3b8d8d91
JB		 1081 if (IS_GEN5(dev)) {
1082 u16 rgvswctl = I915_READ16(MEMSWCTL);
1083 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1084
1085 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1086 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1087 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1088 MEMSTAT_VID_SHIFT);
1089 seq_printf(m, "Current P-state: %d\n",
1090 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1091 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1092 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1093 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1094 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1095 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1096 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1097 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1098 u32 rpupei, rpcurup, rpprevup;
1099 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1100 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1101 int max_freq;
1102
1103 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1104 ret = mutex_lock_interruptible(&dev->struct_mutex);
1105 if (ret)
c8c8fb33 1106 goto out;
d1ebd816 1107
59bad947 1108 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1109
8e8c06cd
CW		 1110 reqf = I915_READ(GEN6_RPNSWREQ);
1111 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1112 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1113 reqf >>= 24;
1114 else
1115 reqf >>= 25;
7c59a9c1 1116 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1117
0d8f9491
CW		 1118 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1119 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1120 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1121
ccab5c82
JB		 1122 rpstat = I915_READ(GEN6_RPSTAT1);
1123 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1124 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1125 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1126 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1127 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1128 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1129 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1130 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1131 else
1132 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1133 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1134
59bad947 1135 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1136 mutex_unlock(&dev->struct_mutex);
1137
9dd3c605
PZ		 1138 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1139 pm_ier = I915_READ(GEN6_PMIER);
1140 pm_imr = I915_READ(GEN6_PMIMR);
1141 pm_isr = I915_READ(GEN6_PMISR);
1142 pm_iir = I915_READ(GEN6_PMIIR);
1143 pm_mask = I915_READ(GEN6_PMINTRMSK);
1144 } else {
1145 pm_ier = I915_READ(GEN8_GT_IER(2));
1146 pm_imr = I915_READ(GEN8_GT_IMR(2));
1147 pm_isr = I915_READ(GEN8_GT_ISR(2));
1148 pm_iir = I915_READ(GEN8_GT_IIR(2));
1149 pm_mask = I915_READ(GEN6_PMINTRMSK);
1150 }
0d8f9491 1151 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1152 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1153 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1154 seq_printf(m, "Render p-state ratio: %d\n",
1155 (gt_perf_status & 0xff00) >> 8);
1156 seq_printf(m, "Render p-state VID: %d\n",
1157 gt_perf_status & 0xff);
1158 seq_printf(m, "Render p-state limit: %d\n",
1159 rp_state_limits & 0xff);
0d8f9491
CW		 1160 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1161 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1162 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1163 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1164 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1165 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1166 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1167 GEN6_CURICONT_MASK);
1168 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1169 GEN6_CURBSYTAVG_MASK);
1170 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1171 GEN6_CURBSYTAVG_MASK);
1172 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1173 GEN6_CURIAVG_MASK);
1174 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1175 GEN6_CURBSYTAVG_MASK);
1176 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1177 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1178
1179 max_freq = (rp_state_cap & 0xff0000) >> 16;
1180 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1181 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1182
1183 max_freq = (rp_state_cap & 0xff00) >> 8;
1184 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1185 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1186
1187 max_freq = rp_state_cap & 0xff;
1188 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1189 intel_gpu_freq(dev_priv, max_freq));
31c77388
BW		 1190
1191 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1192 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1193 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1194 u32 freq_sts;
0a073b84 1195
259bd5d4 1196 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1197 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1198 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1199 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1200
0a073b84 1201 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1202 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1203
0a073b84 1204 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1205 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1206
7c59a9c1
VS		 1207 seq_printf(m,
1208 "efficient (RPe) frequency: %d MHz\n",
1209 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1210
1211 seq_printf(m, "current GPU freq: %d MHz\n",
7c59a9c1 1212 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1213 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1214 } else {
267f0c90 1215 seq_puts(m, "no P-state info available\n");
3b8d8d91 1216 }
f97108d1 1217
c8c8fb33
PZ		 1218out:
1219 intel_runtime_pm_put(dev_priv);
1220 return ret;
f97108d1
JB		 1221}
1222
4d85529d 1223static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1224{
9f25d007 1225 struct drm_info_node *node = m->private;
f97108d1 1226 struct drm_device *dev = node->minor->dev;
e277a1f8 1227 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1228 u32 rgvmodectl, rstdbyctl;
1229 u16 crstandvid;
1230 int ret;
1231
1232 ret = mutex_lock_interruptible(&dev->struct_mutex);
1233 if (ret)
1234 return ret;
c8c8fb33 1235 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1236
1237 rgvmodectl = I915_READ(MEMMODECTL);
1238 rstdbyctl = I915_READ(RSTDBYCTL);
1239 crstandvid = I915_READ16(CRSTANDVID);
1240
c8c8fb33 1241 intel_runtime_pm_put(dev_priv);
616fdb5a 1242 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1243
1244 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1245 "yes" : "no");
1246 seq_printf(m, "Boost freq: %d\n",
1247 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1248 MEMMODE_BOOST_FREQ_SHIFT);
1249 seq_printf(m, "HW control enabled: %s\n",
1250 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1251 seq_printf(m, "SW control enabled: %s\n",
1252 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1253 seq_printf(m, "Gated voltage change: %s\n",
1254 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1255 seq_printf(m, "Starting frequency: P%d\n",
1256 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1257 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1258 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1259 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1260 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1261 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1262 seq_printf(m, "Render standby enabled: %s\n",
1263 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1264 seq_puts(m, "Current RS state: ");
88271da3
JB		 1265 switch (rstdbyctl & RSX_STATUS_MASK) {
1266 case RSX_STATUS_ON:
267f0c90 1267 seq_puts(m, "on\n");
88271da3
JB		 1268 break;
1269 case RSX_STATUS_RC1:
267f0c90 1270 seq_puts(m, "RC1\n");
88271da3
JB		 1271 break;
1272 case RSX_STATUS_RC1E:
267f0c90 1273 seq_puts(m, "RC1E\n");
88271da3
JB		 1274 break;
1275 case RSX_STATUS_RS1:
267f0c90 1276 seq_puts(m, "RS1\n");
88271da3
JB		 1277 break;
1278 case RSX_STATUS_RS2:
267f0c90 1279 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1280 break;
1281 case RSX_STATUS_RS3:
267f0c90 1282 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1283 break;
1284 default:
267f0c90 1285 seq_puts(m, "unknown\n");
88271da3
JB		 1286 break;
1287 }
f97108d1
JB		 1288
1289 return 0;
1290}
1291
f65367b5 1292static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1293{
b2cff0db
CW		 1294 struct drm_info_node *node = m->private;
1295 struct drm_device *dev = node->minor->dev;
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1298 int i;
1299
1300 spin_lock_irq(&dev_priv->uncore.lock);
1301 for_each_fw_domain(fw_domain, dev_priv, i) {
1302 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1303 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1304 fw_domain->wake_count);
1305 }
1306 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1307
b2cff0db
CW		 1308 return 0;
1309}
1310
1311static int vlv_drpc_info(struct seq_file *m)
1312{
9f25d007 1313 struct drm_info_node *node = m->private;
669ab5aa
D		 1314 struct drm_device *dev = node->minor->dev;
1315 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1316 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1317
d46c0517
ID		 1318 intel_runtime_pm_get(dev_priv);
1319
6b312cd3 1320 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1321 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1322 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1323
d46c0517
ID		 1324 intel_runtime_pm_put(dev_priv);
1325
669ab5aa
D		 1326 seq_printf(m, "Video Turbo Mode: %s\n",
1327 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1328 seq_printf(m, "Turbo enabled: %s\n",
1329 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1330 seq_printf(m, "HW control enabled: %s\n",
1331 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1332 seq_printf(m, "SW control enabled: %s\n",
1333 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1334 GEN6_RP_MEDIA_SW_MODE));
1335 seq_printf(m, "RC6 Enabled: %s\n",
1336 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1337 GEN6_RC_CTL_EI_MODE(1))));
1338 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1339 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1340 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1341 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1342
9cc19be5
ID		 1343 seq_printf(m, "Render RC6 residency since boot: %u\n",
1344 I915_READ(VLV_GT_RENDER_RC6));
1345 seq_printf(m, "Media RC6 residency since boot: %u\n",
1346 I915_READ(VLV_GT_MEDIA_RC6));
1347
f65367b5 1348 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1349}
1350
4d85529d
BW		 1351static int gen6_drpc_info(struct seq_file *m)
1352{
9f25d007 1353 struct drm_info_node *node = m->private;
4d85529d
BW		 1354 struct drm_device *dev = node->minor->dev;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1356 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1357 unsigned forcewake_count;
aee56cff 1358 int count = 0, ret;
4d85529d
BW		 1359
1360 ret = mutex_lock_interruptible(&dev->struct_mutex);
1361 if (ret)
1362 return ret;
c8c8fb33 1363 intel_runtime_pm_get(dev_priv);
4d85529d 1364
907b28c5 1365 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1366 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1367 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1368
1369 if (forcewake_count) {
267f0c90
DL		 1370 seq_puts(m, "RC information inaccurate because somebody "
1371 "holds a forcewake reference \n");
4d85529d
BW		 1372 } else {
1373 /* NB: we cannot use forcewake, else we read the wrong values */
1374 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1375 udelay(10);
1376 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1377 }
1378
1379 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1380 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1381
1382 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1383 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1384 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1385 mutex_lock(&dev_priv->rps.hw_lock);
1386 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1387 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1388
c8c8fb33
PZ		 1389 intel_runtime_pm_put(dev_priv);
1390
4d85529d
BW		 1391 seq_printf(m, "Video Turbo Mode: %s\n",
1392 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1393 seq_printf(m, "HW control enabled: %s\n",
1394 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1395 seq_printf(m, "SW control enabled: %s\n",
1396 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1397 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1398 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1399 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1400 seq_printf(m, "RC6 Enabled: %s\n",
1401 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1402 seq_printf(m, "Deep RC6 Enabled: %s\n",
1403 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1404 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1405 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1406 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1407 switch (gt_core_status & GEN6_RCn_MASK) {
1408 case GEN6_RC0:
1409 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1410 seq_puts(m, "Core Power Down\n");
4d85529d 1411 else
267f0c90 1412 seq_puts(m, "on\n");
4d85529d
BW		 1413 break;
1414 case GEN6_RC3:
267f0c90 1415 seq_puts(m, "RC3\n");
4d85529d
BW		 1416 break;
1417 case GEN6_RC6:
267f0c90 1418 seq_puts(m, "RC6\n");
4d85529d
BW		 1419 break;
1420 case GEN6_RC7:
267f0c90 1421 seq_puts(m, "RC7\n");
4d85529d
BW		 1422 break;
1423 default:
267f0c90 1424 seq_puts(m, "Unknown\n");
4d85529d
BW		 1425 break;
1426 }
1427
1428 seq_printf(m, "Core Power Down: %s\n",
1429 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1430
1431 /* Not exactly sure what this is */
1432 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1433 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1434 seq_printf(m, "RC6 residency since boot: %u\n",
1435 I915_READ(GEN6_GT_GFX_RC6));
1436 seq_printf(m, "RC6+ residency since boot: %u\n",
1437 I915_READ(GEN6_GT_GFX_RC6p));
1438 seq_printf(m, "RC6++ residency since boot: %u\n",
1439 I915_READ(GEN6_GT_GFX_RC6pp));
1440
ecd8faea
BW		 1441 seq_printf(m, "RC6 voltage: %dmV\n",
1442 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1443 seq_printf(m, "RC6+ voltage: %dmV\n",
1444 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1445 seq_printf(m, "RC6++ voltage: %dmV\n",
1446 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1447 return 0;
1448}
1449
1450static int i915_drpc_info(struct seq_file *m, void *unused)
1451{
9f25d007 1452 struct drm_info_node *node = m->private;
4d85529d
BW		 1453 struct drm_device *dev = node->minor->dev;
1454
669ab5aa
D		 1455 if (IS_VALLEYVIEW(dev))
1456 return vlv_drpc_info(m);
ac66cf4b 1457 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1458 return gen6_drpc_info(m);
1459 else
1460 return ironlake_drpc_info(m);
1461}
1462
b5e50c3f
JB		 1463static int i915_fbc_status(struct seq_file *m, void *unused)
1464{
9f25d007 1465 struct drm_info_node *node = m->private;
b5e50c3f 1466 struct drm_device *dev = node->minor->dev;
e277a1f8 1467 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1468
3a77c4c4 1469 if (!HAS_FBC(dev)) {
267f0c90 1470 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1471 return 0;
1472 }
1473
36623ef8
PZ		 1474 intel_runtime_pm_get(dev_priv);
1475
ee5382ae 1476 if (intel_fbc_enabled(dev)) {
267f0c90 1477 seq_puts(m, "FBC enabled\n");
b5e50c3f 1478 } else {
267f0c90 1479 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1480 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1481 case FBC_OK:
1482 seq_puts(m, "FBC actived, but currently disabled in hardware");
1483 break;
1484 case FBC_UNSUPPORTED:
1485 seq_puts(m, "unsupported by this chipset");
1486 break;
bed4a673 1487 case FBC_NO_OUTPUT:
267f0c90 1488 seq_puts(m, "no outputs");
bed4a673 1489 break;
b5e50c3f 1490 case FBC_STOLEN_TOO_SMALL:
267f0c90 1491 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1492 break;
1493 case FBC_UNSUPPORTED_MODE:
267f0c90 1494 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1495 break;
1496 case FBC_MODE_TOO_LARGE:
267f0c90 1497 seq_puts(m, "mode too large");
b5e50c3f
JB		 1498 break;
1499 case FBC_BAD_PLANE:
267f0c90 1500 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1501 break;
1502 case FBC_NOT_TILED:
267f0c90 1503 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1504 break;
9c928d16 1505 case FBC_MULTIPLE_PIPES:
267f0c90 1506 seq_puts(m, "multiple pipes are enabled");
9c928d16 1507 break;
c1a9f047 1508 case FBC_MODULE_PARAM:
267f0c90 1509 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1510 break;
8a5729a3 1511 case FBC_CHIP_DEFAULT:
267f0c90 1512 seq_puts(m, "disabled per chip default");
8a5729a3 1513 break;
b5e50c3f 1514 default:
267f0c90 1515 seq_puts(m, "unknown reason");
b5e50c3f 1516 }
267f0c90 1517 seq_putc(m, '\n');
b5e50c3f 1518 }
36623ef8
PZ		 1519
1520 intel_runtime_pm_put(dev_priv);
1521
b5e50c3f
JB		 1522 return 0;
1523}
1524
da46f936
RV		 1525static int i915_fbc_fc_get(void *data, u64 *val)
1526{
1527 struct drm_device *dev = data;
1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529
1530 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1531 return -ENODEV;
1532
1533 drm_modeset_lock_all(dev);
1534 *val = dev_priv->fbc.false_color;
1535 drm_modeset_unlock_all(dev);
1536
1537 return 0;
1538}
1539
1540static int i915_fbc_fc_set(void *data, u64 val)
1541{
1542 struct drm_device *dev = data;
1543 struct drm_i915_private *dev_priv = dev->dev_private;
1544 u32 reg;
1545
1546 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1547 return -ENODEV;
1548
1549 drm_modeset_lock_all(dev);
1550
1551 reg = I915_READ(ILK_DPFC_CONTROL);
1552 dev_priv->fbc.false_color = val;
1553
1554 I915_WRITE(ILK_DPFC_CONTROL, val ?
1555 (reg | FBC_CTL_FALSE_COLOR) :
1556 (reg & ~FBC_CTL_FALSE_COLOR));
1557
1558 drm_modeset_unlock_all(dev);
1559 return 0;
1560}
1561
1562DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1563 i915_fbc_fc_get, i915_fbc_fc_set,
1564 "%llu\n");
1565
92d44621
PZ		 1566static int i915_ips_status(struct seq_file *m, void *unused)
1567{
9f25d007 1568 struct drm_info_node *node = m->private;
92d44621
PZ		 1569 struct drm_device *dev = node->minor->dev;
1570 struct drm_i915_private *dev_priv = dev->dev_private;
1571
f5adf94e 1572 if (!HAS_IPS(dev)) {
92d44621
PZ		 1573 seq_puts(m, "not supported\n");
1574 return 0;
1575 }
1576
36623ef8
PZ		 1577 intel_runtime_pm_get(dev_priv);
1578
0eaa53f0
RV		 1579 seq_printf(m, "Enabled by kernel parameter: %s\n",
1580 yesno(i915.enable_ips));
1581
1582 if (INTEL_INFO(dev)->gen >= 8) {
1583 seq_puts(m, "Currently: unknown\n");
1584 } else {
1585 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1586 seq_puts(m, "Currently: enabled\n");
1587 else
1588 seq_puts(m, "Currently: disabled\n");
1589 }
92d44621 1590
36623ef8
PZ		 1591 intel_runtime_pm_put(dev_priv);
1592
92d44621
PZ		 1593 return 0;
1594}
1595
4a9bef37
JB		 1596static int i915_sr_status(struct seq_file *m, void *unused)
1597{
9f25d007 1598 struct drm_info_node *node = m->private;
4a9bef37 1599 struct drm_device *dev = node->minor->dev;
e277a1f8 1600 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1601 bool sr_enabled = false;
1602
36623ef8
PZ		 1603 intel_runtime_pm_get(dev_priv);
1604
1398261a 1605 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1606 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1607 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1608 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1609 else if (IS_I915GM(dev))
1610 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1611 else if (IS_PINEVIEW(dev))
1612 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1613
36623ef8
PZ		 1614 intel_runtime_pm_put(dev_priv);
1615
5ba2aaaa
CW		 1616 seq_printf(m, "self-refresh: %s\n",
1617 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1618
1619 return 0;
1620}
1621
7648fa99
JB		 1622static int i915_emon_status(struct seq_file *m, void *unused)
1623{
9f25d007 1624 struct drm_info_node *node = m->private;
7648fa99 1625 struct drm_device *dev = node->minor->dev;
e277a1f8 1626 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1627 unsigned long temp, chipset, gfx;
de227ef0
CW		 1628 int ret;
1629
582be6b4
CW		 1630 if (!IS_GEN5(dev))
1631 return -ENODEV;
1632
de227ef0
CW		 1633 ret = mutex_lock_interruptible(&dev->struct_mutex);
1634 if (ret)
1635 return ret;
7648fa99
JB		 1636
1637 temp = i915_mch_val(dev_priv);
1638 chipset = i915_chipset_val(dev_priv);
1639 gfx = i915_gfx_val(dev_priv);
de227ef0 1640 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1641
1642 seq_printf(m, "GMCH temp: %ld\n", temp);
1643 seq_printf(m, "Chipset power: %ld\n", chipset);
1644 seq_printf(m, "GFX power: %ld\n", gfx);
1645 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1646
1647 return 0;
1648}
1649
23b2f8bb
JB		 1650static int i915_ring_freq_table(struct seq_file *m, void *unused)
1651{
9f25d007 1652 struct drm_info_node *node = m->private;
23b2f8bb 1653 struct drm_device *dev = node->minor->dev;
e277a1f8 1654 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1655 int ret = 0;
23b2f8bb
JB		 1656 int gpu_freq, ia_freq;
1657
1c70c0ce 1658 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1659 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1660 return 0;
1661 }
1662
5bfa0199
PZ		 1663 intel_runtime_pm_get(dev_priv);
1664
5c9669ce
TR		 1665 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1666
4fc688ce 1667 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1668 if (ret)
5bfa0199 1669 goto out;
23b2f8bb 1670
267f0c90 1671 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1672
b39fb297
BW		 1673 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1674 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1675 gpu_freq++) {
42c0526c
BW		 1676 ia_freq = gpu_freq;
1677 sandybridge_pcode_read(dev_priv,
1678 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1679 &ia_freq);
3ebecd07 1680 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
7c59a9c1 1681 intel_gpu_freq(dev_priv, gpu_freq),
3ebecd07
CW		 1682 ((ia_freq >> 0) & 0xff) * 100,
1683 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1684 }
1685
4fc688ce 1686 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1687
5bfa0199
PZ		 1688out:
1689 intel_runtime_pm_put(dev_priv);
1690 return ret;
23b2f8bb
JB		 1691}
1692
44834a67
CW		 1693static int i915_opregion(struct seq_file *m, void *unused)
1694{
9f25d007 1695 struct drm_info_node *node = m->private;
44834a67 1696 struct drm_device *dev = node->minor->dev;
e277a1f8 1697 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1698 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1699 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1700 int ret;
1701
0d38f009
DV		 1702 if (data == NULL)
1703 return -ENOMEM;
1704
44834a67
CW		 1705 ret = mutex_lock_interruptible(&dev->struct_mutex);
1706 if (ret)
0d38f009 1707 goto out;
44834a67 1708
0d38f009
DV		 1709 if (opregion->header) {
1710 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1711 seq_write(m, data, OPREGION_SIZE);
1712 }
44834a67
CW		 1713
1714 mutex_unlock(&dev->struct_mutex);
1715
0d38f009
DV		 1716out:
1717 kfree(data);
44834a67
CW		 1718 return 0;
1719}
1720
37811fcc
CW		 1721static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1722{
9f25d007 1723 struct drm_info_node *node = m->private;
37811fcc 1724 struct drm_device *dev = node->minor->dev;
4520f53a 1725 struct intel_fbdev *ifbdev = NULL;
37811fcc 1726 struct intel_framebuffer *fb;
37811fcc 1727
4520f53a
DV		 1728#ifdef CONFIG_DRM_I915_FBDEV
1729 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1730
1731 ifbdev = dev_priv->fbdev;
1732 fb = to_intel_framebuffer(ifbdev->helper.fb);
1733
623f9783 1734 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1735 fb->base.width,
1736 fb->base.height,
1737 fb->base.depth,
623f9783
DV		 1738 fb->base.bits_per_pixel,
1739 atomic_read(&fb->base.refcount.refcount));
05394f39 1740 describe_obj(m, fb->obj);
267f0c90 1741 seq_putc(m, '\n');
4520f53a 1742#endif
37811fcc 1743
4b096ac1 1744 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1745 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1746 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1747 continue;
1748
623f9783 1749 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1750 fb->base.width,
1751 fb->base.height,
1752 fb->base.depth,
623f9783
DV		 1753 fb->base.bits_per_pixel,
1754 atomic_read(&fb->base.refcount.refcount));
05394f39 1755 describe_obj(m, fb->obj);
267f0c90 1756 seq_putc(m, '\n');
37811fcc 1757 }
4b096ac1 1758 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1759
1760 return 0;
1761}
1762
c9fe99bd
OM		 1763static void describe_ctx_ringbuf(struct seq_file *m,
1764 struct intel_ringbuffer *ringbuf)
1765{
1766 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1767 ringbuf->space, ringbuf->head, ringbuf->tail,
1768 ringbuf->last_retired_head);
1769}
1770
e76d3630
BW		 1771static int i915_context_status(struct seq_file *m, void *unused)
1772{
9f25d007 1773 struct drm_info_node *node = m->private;
e76d3630 1774 struct drm_device *dev = node->minor->dev;
e277a1f8 1775 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1776 struct intel_engine_cs *ring;
273497e5 1777 struct intel_context *ctx;
a168c293 1778 int ret, i;
e76d3630 1779
f3d28878 1780 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1781 if (ret)
1782 return ret;
1783
3e373948 1784 if (dev_priv->ips.pwrctx) {
267f0c90 1785 seq_puts(m, "power context ");
3e373948 1786 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1787 seq_putc(m, '\n');
dc501fbc 1788 }
e76d3630 1789
3e373948 1790 if (dev_priv->ips.renderctx) {
267f0c90 1791 seq_puts(m, "render context ");
3e373948 1792 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1793 seq_putc(m, '\n');
dc501fbc 1794 }
e76d3630 1795
a33afea5 1796 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1797 if (!i915.enable_execlists &&
1798 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1799 continue;
1800
a33afea5 1801 seq_puts(m, "HW context ");
3ccfd19d 1802 describe_ctx(m, ctx);
c9fe99bd 1803 for_each_ring(ring, dev_priv, i) {
a33afea5 1804 if (ring->default_context == ctx)
c9fe99bd
OM		 1805 seq_printf(m, "(default context %s) ",
1806 ring->name);
1807 }
1808
1809 if (i915.enable_execlists) {
1810 seq_putc(m, '\n');
1811 for_each_ring(ring, dev_priv, i) {
1812 struct drm_i915_gem_object *ctx_obj =
1813 ctx->engine[i].state;
1814 struct intel_ringbuffer *ringbuf =
1815 ctx->engine[i].ringbuf;
1816
1817 seq_printf(m, "%s: ", ring->name);
1818 if (ctx_obj)
1819 describe_obj(m, ctx_obj);
1820 if (ringbuf)
1821 describe_ctx_ringbuf(m, ringbuf);
1822 seq_putc(m, '\n');
1823 }
1824 } else {
1825 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1826 }
a33afea5 1827
a33afea5 1828 seq_putc(m, '\n');
a168c293
BW		 1829 }
1830
f3d28878 1831 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1832
1833 return 0;
1834}
1835
064ca1d2
TD		 1836static void i915_dump_lrc_obj(struct seq_file *m,
1837 struct intel_engine_cs *ring,
1838 struct drm_i915_gem_object *ctx_obj)
1839{
1840 struct page *page;
1841 uint32_t *reg_state;
1842 int j;
1843 unsigned long ggtt_offset = 0;
1844
1845 if (ctx_obj == NULL) {
1846 seq_printf(m, "Context on %s with no gem object\n",
1847 ring->name);
1848 return;
1849 }
1850
1851 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1852 intel_execlists_ctx_id(ctx_obj));
1853
1854 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1855 seq_puts(m, "\tNot bound in GGTT\n");
1856 else
1857 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1858
1859 if (i915_gem_object_get_pages(ctx_obj)) {
1860 seq_puts(m, "\tFailed to get pages for context object\n");
1861 return;
1862 }
1863
1864 page = i915_gem_object_get_page(ctx_obj, 1);
1865 if (!WARN_ON(page == NULL)) {
1866 reg_state = kmap_atomic(page);
1867
1868 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1869 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1870 ggtt_offset + 4096 + (j * 4),
1871 reg_state[j], reg_state[j + 1],
1872 reg_state[j + 2], reg_state[j + 3]);
1873 }
1874 kunmap_atomic(reg_state);
1875 }
1876
1877 seq_putc(m, '\n');
1878}
1879
c0ab1ae9
BW		 1880static int i915_dump_lrc(struct seq_file *m, void *unused)
1881{
1882 struct drm_info_node *node = (struct drm_info_node *) m->private;
1883 struct drm_device *dev = node->minor->dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
1885 struct intel_engine_cs *ring;
1886 struct intel_context *ctx;
1887 int ret, i;
1888
1889 if (!i915.enable_execlists) {
1890 seq_printf(m, "Logical Ring Contexts are disabled\n");
1891 return 0;
1892 }
1893
1894 ret = mutex_lock_interruptible(&dev->struct_mutex);
1895 if (ret)
1896 return ret;
1897
1898 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1899 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 1900 if (ring->default_context != ctx)
1901 i915_dump_lrc_obj(m, ring,
1902 ctx->engine[i].state);
c0ab1ae9
BW		 1903 }
1904 }
1905
1906 mutex_unlock(&dev->struct_mutex);
1907
1908 return 0;
1909}
1910
4ba70e44
OM		 1911static int i915_execlists(struct seq_file *m, void *data)
1912{
1913 struct drm_info_node *node = (struct drm_info_node *)m->private;
1914 struct drm_device *dev = node->minor->dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
1916 struct intel_engine_cs *ring;
1917 u32 status_pointer;
1918 u8 read_pointer;
1919 u8 write_pointer;
1920 u32 status;
1921 u32 ctx_id;
1922 struct list_head *cursor;
1923 int ring_id, i;
1924 int ret;
1925
1926 if (!i915.enable_execlists) {
1927 seq_puts(m, "Logical Ring Contexts are disabled\n");
1928 return 0;
1929 }
1930
1931 ret = mutex_lock_interruptible(&dev->struct_mutex);
1932 if (ret)
1933 return ret;
1934
fc0412ec
MT		 1935 intel_runtime_pm_get(dev_priv);
1936
4ba70e44 1937 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 1938 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 1939 int count = 0;
1940 unsigned long flags;
1941
1942 seq_printf(m, "%s\n", ring->name);
1943
1944 status = I915_READ(RING_EXECLIST_STATUS(ring));
1945 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1946 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1947 status, ctx_id);
1948
1949 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1950 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1951
1952 read_pointer = ring->next_context_status_buffer;
1953 write_pointer = status_pointer & 0x07;
1954 if (read_pointer > write_pointer)
1955 write_pointer += 6;
1956 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1957 read_pointer, write_pointer);
1958
1959 for (i = 0; i < 6; i++) {
1960 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1961 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1962
1963 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1964 i, status, ctx_id);
1965 }
1966
1967 spin_lock_irqsave(&ring->execlist_lock, flags);
1968 list_for_each(cursor, &ring->execlist_queue)
1969 count++;
1970 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 1971 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 1972 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1973
1974 seq_printf(m, "\t%d requests in queue\n", count);
1975 if (head_req) {
1976 struct drm_i915_gem_object *ctx_obj;
1977
6d3d8274 1978 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 1979 seq_printf(m, "\tHead request id: %u\n",
1980 intel_execlists_ctx_id(ctx_obj));
1981 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 1982 head_req->tail);
4ba70e44
OM		 1983 }
1984
1985 seq_putc(m, '\n');
1986 }
1987
fc0412ec 1988 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 1989 mutex_unlock(&dev->struct_mutex);
1990
1991 return 0;
1992}
1993
ea16a3cd
DV		 1994static const char *swizzle_string(unsigned swizzle)
1995{
aee56cff 1996 switch (swizzle) {
ea16a3cd
DV		 1997 case I915_BIT_6_SWIZZLE_NONE:
1998 return "none";
1999 case I915_BIT_6_SWIZZLE_9:
2000 return "bit9";
2001 case I915_BIT_6_SWIZZLE_9_10:
2002 return "bit9/bit10";
2003 case I915_BIT_6_SWIZZLE_9_11:
2004 return "bit9/bit11";
2005 case I915_BIT_6_SWIZZLE_9_10_11:
2006 return "bit9/bit10/bit11";
2007 case I915_BIT_6_SWIZZLE_9_17:
2008 return "bit9/bit17";
2009 case I915_BIT_6_SWIZZLE_9_10_17:
2010 return "bit9/bit10/bit17";
2011 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2012 return "unknown";
ea16a3cd
DV		 2013 }
2014
2015 return "bug";
2016}
2017
2018static int i915_swizzle_info(struct seq_file *m, void *data)
2019{
9f25d007 2020 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2021 struct drm_device *dev = node->minor->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2023 int ret;
2024
2025 ret = mutex_lock_interruptible(&dev->struct_mutex);
2026 if (ret)
2027 return ret;
c8c8fb33 2028 intel_runtime_pm_get(dev_priv);
ea16a3cd 2029
ea16a3cd
DV		 2030 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2031 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2032 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2033 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2034
2035 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2036 seq_printf(m, "DDC = 0x%08x\n",
2037 I915_READ(DCC));
656bfa3a
DV		 2038 seq_printf(m, "DDC2 = 0x%08x\n",
2039 I915_READ(DCC2));
ea16a3cd
DV		 2040 seq_printf(m, "C0DRB3 = 0x%04x\n",
2041 I915_READ16(C0DRB3));
2042 seq_printf(m, "C1DRB3 = 0x%04x\n",
2043 I915_READ16(C1DRB3));
9d3203e1 2044 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2045 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2046 I915_READ(MAD_DIMM_C0));
2047 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2048 I915_READ(MAD_DIMM_C1));
2049 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2050 I915_READ(MAD_DIMM_C2));
2051 seq_printf(m, "TILECTL = 0x%08x\n",
2052 I915_READ(TILECTL));
5907f5fb 2053 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2054 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2055 I915_READ(GAMTARBMODE));
2056 else
2057 seq_printf(m, "ARB_MODE = 0x%08x\n",
2058 I915_READ(ARB_MODE));
3fa7d235
DV		 2059 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2060 I915_READ(DISP_ARB_CTL));
ea16a3cd 2061 }
656bfa3a
DV		 2062
2063 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2064 seq_puts(m, "L-shaped memory detected\n");
2065
c8c8fb33 2066 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2067 mutex_unlock(&dev->struct_mutex);
2068
2069 return 0;
2070}
2071
1c60fef5
BW		 2072static int per_file_ctx(int id, void *ptr, void *data)
2073{
273497e5 2074 struct intel_context *ctx = ptr;
1c60fef5 2075 struct seq_file *m = data;
ae6c4806
DV		 2076 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2077
2078 if (!ppgtt) {
2079 seq_printf(m, " no ppgtt for context %d\n",
2080 ctx->user_handle);
2081 return 0;
2082 }
1c60fef5 2083
f83d6518
OM		 2084 if (i915_gem_context_is_default(ctx))
2085 seq_puts(m, " default context:\n");
2086 else
821d66dd 2087 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2088 ppgtt->debug_dump(ppgtt, m);
2089
2090 return 0;
2091}
2092
77df6772 2093static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2094{
3cf17fc5 2095 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2096 struct intel_engine_cs *ring;
77df6772
BW		 2097 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2098 int unused, i;
3cf17fc5 2099
77df6772
BW		 2100 if (!ppgtt)
2101 return;
2102
2103 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2104 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2105 for_each_ring(ring, dev_priv, unused) {
2106 seq_printf(m, "%s\n", ring->name);
2107 for (i = 0; i < 4; i++) {
2108 u32 offset = 0x270 + i * 8;
2109 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2110 pdp <<= 32;
2111 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2112 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2113 }
2114 }
2115}
2116
2117static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2118{
2119 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2120 struct intel_engine_cs *ring;
1c60fef5 2121 struct drm_file *file;
77df6772 2122 int i;
3cf17fc5 2123
3cf17fc5
DV		 2124 if (INTEL_INFO(dev)->gen == 6)
2125 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2126
a2c7f6fd 2127 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2128 seq_printf(m, "%s\n", ring->name);
2129 if (INTEL_INFO(dev)->gen == 7)
2130 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2131 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2132 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2133 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2134 }
2135 if (dev_priv->mm.aliasing_ppgtt) {
2136 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2137
267f0c90 2138 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 2139 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 2140
87d60b63 2141 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2142 }
1c60fef5
BW		 2143
2144 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2145 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2146
1c60fef5
BW		 2147 seq_printf(m, "proc: %s\n",
2148 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2149 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2150 }
2151 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2152}
2153
2154static int i915_ppgtt_info(struct seq_file *m, void *data)
2155{
9f25d007 2156 struct drm_info_node *node = m->private;
77df6772 2157 struct drm_device *dev = node->minor->dev;
c8c8fb33 2158 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2159
2160 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2161 if (ret)
2162 return ret;
c8c8fb33 2163 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2164
2165 if (INTEL_INFO(dev)->gen >= 8)
2166 gen8_ppgtt_info(m, dev);
2167 else if (INTEL_INFO(dev)->gen >= 6)
2168 gen6_ppgtt_info(m, dev);
2169
c8c8fb33 2170 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2171 mutex_unlock(&dev->struct_mutex);
2172
2173 return 0;
2174}
2175
63573eb7
BW		 2176static int i915_llc(struct seq_file *m, void *data)
2177{
9f25d007 2178 struct drm_info_node *node = m->private;
63573eb7
BW		 2179 struct drm_device *dev = node->minor->dev;
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181
2182 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2183 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2184 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2185
2186 return 0;
2187}
2188
e91fd8c6
RV		 2189static int i915_edp_psr_status(struct seq_file *m, void *data)
2190{
2191 struct drm_info_node *node = m->private;
2192 struct drm_device *dev = node->minor->dev;
2193 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2194 u32 psrperf = 0;
a6cbdb8e
RV		 2195 u32 stat[3];
2196 enum pipe pipe;
a031d709 2197 bool enabled = false;
e91fd8c6 2198
c8c8fb33
PZ		 2199 intel_runtime_pm_get(dev_priv);
2200
fa128fa6 2201 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2202 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2203 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2204 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2205 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2206 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2207 dev_priv->psr.busy_frontbuffer_bits);
2208 seq_printf(m, "Re-enable work scheduled: %s\n",
2209 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2210
a6cbdb8e
RV		 2211 if (HAS_PSR(dev)) {
2212 if (HAS_DDI(dev))
2213 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2214 else {
2215 for_each_pipe(dev_priv, pipe) {
2216 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2217 VLV_EDP_PSR_CURR_STATE_MASK;
2218 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2219 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2220 enabled = true;
2221 }
2222 }
2223 }
2224 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2225
2226 if (!HAS_DDI(dev))
2227 for_each_pipe(dev_priv, pipe) {
2228 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2229 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2230 seq_printf(m, " pipe %c", pipe_name(pipe));
2231 }
2232 seq_puts(m, "\n");
e91fd8c6 2233
fb495814
RV		 2234 seq_printf(m, "Link standby: %s\n",
2235 yesno((bool)dev_priv->psr.link_standby));
2236
a6cbdb8e
RV		 2237 /* CHV PSR has no kind of performance counter */
2238 if (HAS_PSR(dev) && HAS_DDI(dev)) {
a031d709
RV		 2239 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2240 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2241
2242 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2243 }
fa128fa6 2244 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2245
c8c8fb33 2246 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2247 return 0;
2248}
2249
d2e216d0
RV		 2250static int i915_sink_crc(struct seq_file *m, void *data)
2251{
2252 struct drm_info_node *node = m->private;
2253 struct drm_device *dev = node->minor->dev;
2254 struct intel_encoder *encoder;
2255 struct intel_connector *connector;
2256 struct intel_dp *intel_dp = NULL;
2257 int ret;
2258 u8 crc[6];
2259
2260 drm_modeset_lock_all(dev);
2261 list_for_each_entry(connector, &dev->mode_config.connector_list,
2262 base.head) {
2263
2264 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2265 continue;
2266
b6ae3c7c
PZ		 2267 if (!connector->base.encoder)
2268 continue;
2269
d2e216d0
RV		 2270 encoder = to_intel_encoder(connector->base.encoder);
2271 if (encoder->type != INTEL_OUTPUT_EDP)
2272 continue;
2273
2274 intel_dp = enc_to_intel_dp(&encoder->base);
2275
2276 ret = intel_dp_sink_crc(intel_dp, crc);
2277 if (ret)
2278 goto out;
2279
2280 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2281 crc[0], crc[1], crc[2],
2282 crc[3], crc[4], crc[5]);
2283 goto out;
2284 }
2285 ret = -ENODEV;
2286out:
2287 drm_modeset_unlock_all(dev);
2288 return ret;
2289}
2290
ec013e7f
JB		 2291static int i915_energy_uJ(struct seq_file *m, void *data)
2292{
2293 struct drm_info_node *node = m->private;
2294 struct drm_device *dev = node->minor->dev;
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 u64 power;
2297 u32 units;
2298
2299 if (INTEL_INFO(dev)->gen < 6)
2300 return -ENODEV;
2301
36623ef8
PZ		 2302 intel_runtime_pm_get(dev_priv);
2303
ec013e7f
JB		 2304 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2305 power = (power & 0x1f00) >> 8;
2306 units = 1000000 / (1 << power); /* convert to uJ */
2307 power = I915_READ(MCH_SECP_NRG_STTS);
2308 power *= units;
2309
36623ef8
PZ		 2310 intel_runtime_pm_put(dev_priv);
2311
ec013e7f 2312 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2313
2314 return 0;
2315}
2316
2317static int i915_pc8_status(struct seq_file *m, void *unused)
2318{
9f25d007 2319 struct drm_info_node *node = m->private;
371db66a
PZ		 2320 struct drm_device *dev = node->minor->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322
85b8d5c2 2323 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2324 seq_puts(m, "not supported\n");
2325 return 0;
2326 }
2327
86c4ec0d 2328 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2329 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2330 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2331
ec013e7f
JB		 2332 return 0;
2333}
2334
1da51581
ID		 2335static const char *power_domain_str(enum intel_display_power_domain domain)
2336{
2337 switch (domain) {
2338 case POWER_DOMAIN_PIPE_A:
2339 return "PIPE_A";
2340 case POWER_DOMAIN_PIPE_B:
2341 return "PIPE_B";
2342 case POWER_DOMAIN_PIPE_C:
2343 return "PIPE_C";
2344 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2345 return "PIPE_A_PANEL_FITTER";
2346 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2347 return "PIPE_B_PANEL_FITTER";
2348 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2349 return "PIPE_C_PANEL_FITTER";
2350 case POWER_DOMAIN_TRANSCODER_A:
2351 return "TRANSCODER_A";
2352 case POWER_DOMAIN_TRANSCODER_B:
2353 return "TRANSCODER_B";
2354 case POWER_DOMAIN_TRANSCODER_C:
2355 return "TRANSCODER_C";
2356 case POWER_DOMAIN_TRANSCODER_EDP:
2357 return "TRANSCODER_EDP";
319be8ae
ID		 2358 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2359 return "PORT_DDI_A_2_LANES";
2360 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2361 return "PORT_DDI_A_4_LANES";
2362 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2363 return "PORT_DDI_B_2_LANES";
2364 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2365 return "PORT_DDI_B_4_LANES";
2366 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2367 return "PORT_DDI_C_2_LANES";
2368 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2369 return "PORT_DDI_C_4_LANES";
2370 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2371 return "PORT_DDI_D_2_LANES";
2372 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2373 return "PORT_DDI_D_4_LANES";
2374 case POWER_DOMAIN_PORT_DSI:
2375 return "PORT_DSI";
2376 case POWER_DOMAIN_PORT_CRT:
2377 return "PORT_CRT";
2378 case POWER_DOMAIN_PORT_OTHER:
2379 return "PORT_OTHER";
1da51581
ID		 2380 case POWER_DOMAIN_VGA:
2381 return "VGA";
2382 case POWER_DOMAIN_AUDIO:
2383 return "AUDIO";
bd2bb1b9
PZ		 2384 case POWER_DOMAIN_PLLS:
2385 return "PLLS";
1407121a
S		 2386 case POWER_DOMAIN_AUX_A:
2387 return "AUX_A";
2388 case POWER_DOMAIN_AUX_B:
2389 return "AUX_B";
2390 case POWER_DOMAIN_AUX_C:
2391 return "AUX_C";
2392 case POWER_DOMAIN_AUX_D:
2393 return "AUX_D";
1da51581
ID		 2394 case POWER_DOMAIN_INIT:
2395 return "INIT";
2396 default:
5f77eeb0 2397 MISSING_CASE(domain);
1da51581
ID		 2398 return "?";
2399 }
2400}
2401
2402static int i915_power_domain_info(struct seq_file *m, void *unused)
2403{
9f25d007 2404 struct drm_info_node *node = m->private;
1da51581
ID		 2405 struct drm_device *dev = node->minor->dev;
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2407 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2408 int i;
2409
2410 mutex_lock(&power_domains->lock);
2411
2412 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2413 for (i = 0; i < power_domains->power_well_count; i++) {
2414 struct i915_power_well *power_well;
2415 enum intel_display_power_domain power_domain;
2416
2417 power_well = &power_domains->power_wells[i];
2418 seq_printf(m, "%-25s %d\n", power_well->name,
2419 power_well->count);
2420
2421 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2422 power_domain++) {
2423 if (!(BIT(power_domain) & power_well->domains))
2424 continue;
2425
2426 seq_printf(m, " %-23s %d\n",
2427 power_domain_str(power_domain),
2428 power_domains->domain_use_count[power_domain]);
2429 }
2430 }
2431
2432 mutex_unlock(&power_domains->lock);
2433
2434 return 0;
2435}
2436
53f5e3ca
JB		 2437static void intel_seq_print_mode(struct seq_file *m, int tabs,
2438 struct drm_display_mode *mode)
2439{
2440 int i;
2441
2442 for (i = 0; i < tabs; i++)
2443 seq_putc(m, '\t');
2444
2445 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2446 mode->base.id, mode->name,
2447 mode->vrefresh, mode->clock,
2448 mode->hdisplay, mode->hsync_start,
2449 mode->hsync_end, mode->htotal,
2450 mode->vdisplay, mode->vsync_start,
2451 mode->vsync_end, mode->vtotal,
2452 mode->type, mode->flags);
2453}
2454
2455static void intel_encoder_info(struct seq_file *m,
2456 struct intel_crtc *intel_crtc,
2457 struct intel_encoder *intel_encoder)
2458{
9f25d007 2459 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2460 struct drm_device *dev = node->minor->dev;
2461 struct drm_crtc *crtc = &intel_crtc->base;
2462 struct intel_connector *intel_connector;
2463 struct drm_encoder *encoder;
2464
2465 encoder = &intel_encoder->base;
2466 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2467 encoder->base.id, encoder->name);
53f5e3ca
JB		 2468 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2469 struct drm_connector *connector = &intel_connector->base;
2470 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2471 connector->base.id,
c23cc417 2472 connector->name,
53f5e3ca
JB		 2473 drm_get_connector_status_name(connector->status));
2474 if (connector->status == connector_status_connected) {
2475 struct drm_display_mode *mode = &crtc->mode;
2476 seq_printf(m, ", mode:\n");
2477 intel_seq_print_mode(m, 2, mode);
2478 } else {
2479 seq_putc(m, '\n');
2480 }
2481 }
2482}
2483
2484static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2485{
9f25d007 2486 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2487 struct drm_device *dev = node->minor->dev;
2488 struct drm_crtc *crtc = &intel_crtc->base;
2489 struct intel_encoder *intel_encoder;
2490
5aa8a937
MR		 2491 if (crtc->primary->fb)
2492 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2493 crtc->primary->fb->base.id, crtc->x, crtc->y,
2494 crtc->primary->fb->width, crtc->primary->fb->height);
2495 else
2496 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2497 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2498 intel_encoder_info(m, intel_crtc, intel_encoder);
2499}
2500
2501static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2502{
2503 struct drm_display_mode *mode = panel->fixed_mode;
2504
2505 seq_printf(m, "\tfixed mode:\n");
2506 intel_seq_print_mode(m, 2, mode);
2507}
2508
2509static void intel_dp_info(struct seq_file *m,
2510 struct intel_connector *intel_connector)
2511{
2512 struct intel_encoder *intel_encoder = intel_connector->encoder;
2513 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2514
2515 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2516 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2517 "no");
2518 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2519 intel_panel_info(m, &intel_connector->panel);
2520}
2521
2522static void intel_hdmi_info(struct seq_file *m,
2523 struct intel_connector *intel_connector)
2524{
2525 struct intel_encoder *intel_encoder = intel_connector->encoder;
2526 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2527
2528 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2529 "no");
2530}
2531
2532static void intel_lvds_info(struct seq_file *m,
2533 struct intel_connector *intel_connector)
2534{
2535 intel_panel_info(m, &intel_connector->panel);
2536}
2537
2538static void intel_connector_info(struct seq_file *m,
2539 struct drm_connector *connector)
2540{
2541 struct intel_connector *intel_connector = to_intel_connector(connector);
2542 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2543 struct drm_display_mode *mode;
53f5e3ca
JB		 2544
2545 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2546 connector->base.id, connector->name,
53f5e3ca
JB		 2547 drm_get_connector_status_name(connector->status));
2548 if (connector->status == connector_status_connected) {
2549 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2550 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2551 connector->display_info.width_mm,
2552 connector->display_info.height_mm);
2553 seq_printf(m, "\tsubpixel order: %s\n",
2554 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2555 seq_printf(m, "\tCEA rev: %d\n",
2556 connector->display_info.cea_rev);
2557 }
36cd7444
DA		 2558 if (intel_encoder) {
2559 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2560 intel_encoder->type == INTEL_OUTPUT_EDP)
2561 intel_dp_info(m, intel_connector);
2562 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2563 intel_hdmi_info(m, intel_connector);
2564 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2565 intel_lvds_info(m, intel_connector);
2566 }
53f5e3ca 2567
f103fc7d
JB		 2568 seq_printf(m, "\tmodes:\n");
2569 list_for_each_entry(mode, &connector->modes, head)
2570 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2571}
2572
065f2ec2
CW		 2573static bool cursor_active(struct drm_device *dev, int pipe)
2574{
2575 struct drm_i915_private *dev_priv = dev->dev_private;
2576 u32 state;
2577
2578 if (IS_845G(dev) || IS_I865G(dev))
2579 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2580 else
5efb3e28 2581 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2582
2583 return state;
2584}
2585
2586static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2587{
2588 struct drm_i915_private *dev_priv = dev->dev_private;
2589 u32 pos;
2590
5efb3e28 2591 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2592
2593 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2594 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2595 *x = -*x;
2596
2597 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2598 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2599 *y = -*y;
2600
2601 return cursor_active(dev, pipe);
2602}
2603
53f5e3ca
JB		 2604static int i915_display_info(struct seq_file *m, void *unused)
2605{
9f25d007 2606 struct drm_info_node *node = m->private;
53f5e3ca 2607 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2608 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2609 struct intel_crtc *crtc;
53f5e3ca
JB		 2610 struct drm_connector *connector;
2611
b0e5ddf3 2612 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2613 drm_modeset_lock_all(dev);
2614 seq_printf(m, "CRTC info\n");
2615 seq_printf(m, "---------\n");
d3fcc808 2616 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2617 bool active;
2618 int x, y;
53f5e3ca 2619
57127efa 2620 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2621 crtc->base.base.id, pipe_name(crtc->pipe),
6e3c9717
ACO		 2622 yesno(crtc->active), crtc->config->pipe_src_w,
2623 crtc->config->pipe_src_h);
a23dc658 2624 if (crtc->active) {
065f2ec2
CW		 2625 intel_crtc_info(m, crtc);
2626
a23dc658 2627 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2628 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2629 yesno(crtc->cursor_base),
57127efa
CW		 2630 x, y, crtc->cursor_width, crtc->cursor_height,
2631 crtc->cursor_addr, yesno(active));
a23dc658 2632 }
cace841c
DV		 2633
2634 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2635 yesno(!crtc->cpu_fifo_underrun_disabled),
2636 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2637 }
2638
2639 seq_printf(m, "\n");
2640 seq_printf(m, "Connector info\n");
2641 seq_printf(m, "--------------\n");
2642 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2643 intel_connector_info(m, connector);
2644 }
2645 drm_modeset_unlock_all(dev);
b0e5ddf3 2646 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2647
2648 return 0;
2649}
2650
e04934cf
BW		 2651static int i915_semaphore_status(struct seq_file *m, void *unused)
2652{
2653 struct drm_info_node *node = (struct drm_info_node *) m->private;
2654 struct drm_device *dev = node->minor->dev;
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 struct intel_engine_cs *ring;
2657 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2658 int i, j, ret;
2659
2660 if (!i915_semaphore_is_enabled(dev)) {
2661 seq_puts(m, "Semaphores are disabled\n");
2662 return 0;
2663 }
2664
2665 ret = mutex_lock_interruptible(&dev->struct_mutex);
2666 if (ret)
2667 return ret;
03872064 2668 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2669
2670 if (IS_BROADWELL(dev)) {
2671 struct page *page;
2672 uint64_t *seqno;
2673
2674 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2675
2676 seqno = (uint64_t *)kmap_atomic(page);
2677 for_each_ring(ring, dev_priv, i) {
2678 uint64_t offset;
2679
2680 seq_printf(m, "%s\n", ring->name);
2681
2682 seq_puts(m, " Last signal:");
2683 for (j = 0; j < num_rings; j++) {
2684 offset = i * I915_NUM_RINGS + j;
2685 seq_printf(m, "0x%08llx (0x%02llx) ",
2686 seqno[offset], offset * 8);
2687 }
2688 seq_putc(m, '\n');
2689
2690 seq_puts(m, " Last wait: ");
2691 for (j = 0; j < num_rings; j++) {
2692 offset = i + (j * I915_NUM_RINGS);
2693 seq_printf(m, "0x%08llx (0x%02llx) ",
2694 seqno[offset], offset * 8);
2695 }
2696 seq_putc(m, '\n');
2697
2698 }
2699 kunmap_atomic(seqno);
2700 } else {
2701 seq_puts(m, " Last signal:");
2702 for_each_ring(ring, dev_priv, i)
2703 for (j = 0; j < num_rings; j++)
2704 seq_printf(m, "0x%08x\n",
2705 I915_READ(ring->semaphore.mbox.signal[j]));
2706 seq_putc(m, '\n');
2707 }
2708
2709 seq_puts(m, "\nSync seqno:\n");
2710 for_each_ring(ring, dev_priv, i) {
2711 for (j = 0; j < num_rings; j++) {
2712 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2713 }
2714 seq_putc(m, '\n');
2715 }
2716 seq_putc(m, '\n');
2717
03872064 2718 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2719 mutex_unlock(&dev->struct_mutex);
2720 return 0;
2721}
2722
728e29d7
DV		 2723static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2724{
2725 struct drm_info_node *node = (struct drm_info_node *) m->private;
2726 struct drm_device *dev = node->minor->dev;
2727 struct drm_i915_private *dev_priv = dev->dev_private;
2728 int i;
2729
2730 drm_modeset_lock_all(dev);
2731 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2732 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2733
2734 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2735 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2736 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2737 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2738 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2739 seq_printf(m, " dpll_md: 0x%08x\n",
2740 pll->config.hw_state.dpll_md);
2741 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2742 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2743 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2744 }
2745 drm_modeset_unlock_all(dev);
2746
2747 return 0;
2748}
2749
1ed1ef9d 2750static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2751{
2752 int i;
2753 int ret;
2754 struct drm_info_node *node = (struct drm_info_node *) m->private;
2755 struct drm_device *dev = node->minor->dev;
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757
888b5995
AS		 2758 ret = mutex_lock_interruptible(&dev->struct_mutex);
2759 if (ret)
2760 return ret;
2761
2762 intel_runtime_pm_get(dev_priv);
2763
7225342a
MK		 2764 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2765 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2766 u32 addr, mask, value, read;
2767 bool ok;
888b5995 2768
7225342a
MK		 2769 addr = dev_priv->workarounds.reg[i].addr;
2770 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2771 value = dev_priv->workarounds.reg[i].value;
2772 read = I915_READ(addr);
2773 ok = (value & mask) == (read & mask);
2774 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2775 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2776 }
2777
2778 intel_runtime_pm_put(dev_priv);
2779 mutex_unlock(&dev->struct_mutex);
2780
2781 return 0;
2782}
2783
c5511e44
DL		 2784static int i915_ddb_info(struct seq_file *m, void *unused)
2785{
2786 struct drm_info_node *node = m->private;
2787 struct drm_device *dev = node->minor->dev;
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 struct skl_ddb_allocation *ddb;
2790 struct skl_ddb_entry *entry;
2791 enum pipe pipe;
2792 int plane;
2793
2fcffe19
DL		 2794 if (INTEL_INFO(dev)->gen < 9)
2795 return 0;
2796
c5511e44
DL		 2797 drm_modeset_lock_all(dev);
2798
2799 ddb = &dev_priv->wm.skl_hw.ddb;
2800
2801 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2802
2803 for_each_pipe(dev_priv, pipe) {
2804 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2805
2806 for_each_plane(pipe, plane) {
2807 entry = &ddb->plane[pipe][plane];
2808 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2809 entry->start, entry->end,
2810 skl_ddb_entry_size(entry));
2811 }
2812
2813 entry = &ddb->cursor[pipe];
2814 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2815 entry->end, skl_ddb_entry_size(entry));
2816 }
2817
2818 drm_modeset_unlock_all(dev);
2819
2820 return 0;
2821}
2822
07144428
DL		 2823struct pipe_crc_info {
2824 const char *name;
2825 struct drm_device *dev;
2826 enum pipe pipe;
2827};
2828
11bed958
DA		 2829static int i915_dp_mst_info(struct seq_file *m, void *unused)
2830{
2831 struct drm_info_node *node = (struct drm_info_node *) m->private;
2832 struct drm_device *dev = node->minor->dev;
2833 struct drm_encoder *encoder;
2834 struct intel_encoder *intel_encoder;
2835 struct intel_digital_port *intel_dig_port;
2836 drm_modeset_lock_all(dev);
2837 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2838 intel_encoder = to_intel_encoder(encoder);
2839 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2840 continue;
2841 intel_dig_port = enc_to_dig_port(encoder);
2842 if (!intel_dig_port->dp.can_mst)
2843 continue;
2844
2845 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2846 }
2847 drm_modeset_unlock_all(dev);
2848 return 0;
2849}
2850
07144428
DL		 2851static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2852{
be5c7a90
DL		 2853 struct pipe_crc_info *info = inode->i_private;
2854 struct drm_i915_private *dev_priv = info->dev->dev_private;
2855 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2856
7eb1c496
DV		 2857 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2858 return -ENODEV;
2859
d538bbdf
DL		 2860 spin_lock_irq(&pipe_crc->lock);
2861
2862 if (pipe_crc->opened) {
2863 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2864 return -EBUSY; /* already open */
2865 }
2866
d538bbdf 2867 pipe_crc->opened = true;
07144428
DL		 2868 filep->private_data = inode->i_private;
2869
d538bbdf
DL		 2870 spin_unlock_irq(&pipe_crc->lock);
2871
07144428
DL		 2872 return 0;
2873}
2874
2875static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2876{
be5c7a90
DL		 2877 struct pipe_crc_info *info = inode->i_private;
2878 struct drm_i915_private *dev_priv = info->dev->dev_private;
2879 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2880
d538bbdf
DL		 2881 spin_lock_irq(&pipe_crc->lock);
2882 pipe_crc->opened = false;
2883 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2884
07144428
DL		 2885 return 0;
2886}
2887
2888/* (6 fields, 8 chars each, space separated (5) + '\n') */
2889#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2890/* account for \'0' */
2891#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2892
2893static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2894{
d538bbdf
DL		 2895 assert_spin_locked(&pipe_crc->lock);
2896 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2897 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2898}
2899
2900static ssize_t
2901i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2902 loff_t *pos)
2903{
2904 struct pipe_crc_info *info = filep->private_data;
2905 struct drm_device *dev = info->dev;
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2908 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 2909 int n_entries;
07144428
DL		 2910 ssize_t bytes_read;
2911
2912 /*
2913 * Don't allow user space to provide buffers not big enough to hold
2914 * a line of data.
2915 */
2916 if (count < PIPE_CRC_LINE_LEN)
2917 return -EINVAL;
2918
2919 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2920 return 0;
07144428
DL		 2921
2922 /* nothing to read */
d538bbdf 2923 spin_lock_irq(&pipe_crc->lock);
07144428 2924 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2925 int ret;
2926
2927 if (filep->f_flags & O_NONBLOCK) {
2928 spin_unlock_irq(&pipe_crc->lock);
07144428 2929 return -EAGAIN;
d538bbdf 2930 }
07144428 2931
d538bbdf
DL		 2932 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2933 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2934 if (ret) {
2935 spin_unlock_irq(&pipe_crc->lock);
2936 return ret;
2937 }
8bf1e9f1
SH		 2938 }
2939
07144428 2940 /* We now have one or more entries to read */
9ad6d99f 2941 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 2942
07144428 2943 bytes_read = 0;
9ad6d99f
VS		 2944 while (n_entries > 0) {
2945 struct intel_pipe_crc_entry *entry =
2946 &pipe_crc->entries[pipe_crc->tail];
07144428 2947 int ret;
8bf1e9f1 2948
9ad6d99f
VS		 2949 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2950 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2951 break;
2952
2953 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2954 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2955
07144428
DL		 2956 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2957 "%8u %8x %8x %8x %8x %8x\n",
2958 entry->frame, entry->crc[0],
2959 entry->crc[1], entry->crc[2],
2960 entry->crc[3], entry->crc[4]);
2961
9ad6d99f
VS		 2962 spin_unlock_irq(&pipe_crc->lock);
2963
2964 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 2965 if (ret == PIPE_CRC_LINE_LEN)
2966 return -EFAULT;
b2c88f5b 2967
9ad6d99f
VS		 2968 user_buf += PIPE_CRC_LINE_LEN;
2969 n_entries--;
2970
2971 spin_lock_irq(&pipe_crc->lock);
2972 }
8bf1e9f1 2973
d538bbdf
DL		 2974 spin_unlock_irq(&pipe_crc->lock);
2975
07144428
DL		 2976 return bytes_read;
2977}
2978
2979static const struct file_operations i915_pipe_crc_fops = {
2980 .owner = THIS_MODULE,
2981 .open = i915_pipe_crc_open,
2982 .read = i915_pipe_crc_read,
2983 .release = i915_pipe_crc_release,
2984};
2985
2986static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2987 {
2988 .name = "i915_pipe_A_crc",
2989 .pipe = PIPE_A,
2990 },
2991 {
2992 .name = "i915_pipe_B_crc",
2993 .pipe = PIPE_B,
2994 },
2995 {
2996 .name = "i915_pipe_C_crc",
2997 .pipe = PIPE_C,
2998 },
2999};
3000
3001static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3002 enum pipe pipe)
3003{
3004 struct drm_device *dev = minor->dev;
3005 struct dentry *ent;
3006 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3007
3008 info->dev = dev;
3009 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3010 &i915_pipe_crc_fops);
f3c5fe97
WY		 3011 if (!ent)
3012 return -ENOMEM;
07144428
DL		 3013
3014 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3015}
3016
e8dfcf78 3017static const char * const pipe_crc_sources[] = {
926321d5
DV		 3018 "none",
3019 "plane1",
3020 "plane2",
3021 "pf",
5b3a856b 3022 "pipe",
3d099a05
DV		 3023 "TV",
3024 "DP-B",
3025 "DP-C",
3026 "DP-D",
46a19188 3027 "auto",
926321d5
DV		 3028};
3029
3030static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3031{
3032 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3033 return pipe_crc_sources[source];
3034}
3035
bd9db02f 3036static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3037{
3038 struct drm_device *dev = m->private;
3039 struct drm_i915_private *dev_priv = dev->dev_private;
3040 int i;
3041
3042 for (i = 0; i < I915_MAX_PIPES; i++)
3043 seq_printf(m, "%c %s\n", pipe_name(i),
3044 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3045
3046 return 0;
3047}
3048
bd9db02f 3049static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3050{
3051 struct drm_device *dev = inode->i_private;
3052
bd9db02f 3053 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3054}
3055
46a19188 3056static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3057 uint32_t *val)
3058{
46a19188
DV		 3059 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3060 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3061
3062 switch (*source) {
52f843f6
DV		 3063 case INTEL_PIPE_CRC_SOURCE_PIPE:
3064 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3065 break;
3066 case INTEL_PIPE_CRC_SOURCE_NONE:
3067 *val = 0;
3068 break;
3069 default:
3070 return -EINVAL;
3071 }
3072
3073 return 0;
3074}
3075
46a19188
DV		 3076static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3077 enum intel_pipe_crc_source *source)
3078{
3079 struct intel_encoder *encoder;
3080 struct intel_crtc *crtc;
26756809 3081 struct intel_digital_port *dig_port;
46a19188
DV		 3082 int ret = 0;
3083
3084 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3085
6e9f798d 3086 drm_modeset_lock_all(dev);
b2784e15 3087 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3088 if (!encoder->base.crtc)
3089 continue;
3090
3091 crtc = to_intel_crtc(encoder->base.crtc);
3092
3093 if (crtc->pipe != pipe)
3094 continue;
3095
3096 switch (encoder->type) {
3097 case INTEL_OUTPUT_TVOUT:
3098 *source = INTEL_PIPE_CRC_SOURCE_TV;
3099 break;
3100 case INTEL_OUTPUT_DISPLAYPORT:
3101 case INTEL_OUTPUT_EDP:
26756809
DV		 3102 dig_port = enc_to_dig_port(&encoder->base);
3103 switch (dig_port->port) {
3104 case PORT_B:
3105 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3106 break;
3107 case PORT_C:
3108 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3109 break;
3110 case PORT_D:
3111 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3112 break;
3113 default:
3114 WARN(1, "nonexisting DP port %c\n",
3115 port_name(dig_port->port));
3116 break;
3117 }
46a19188 3118 break;
6847d71b
PZ		 3119 default:
3120 break;
46a19188
DV		 3121 }
3122 }
6e9f798d 3123 drm_modeset_unlock_all(dev);
46a19188
DV		 3124
3125 return ret;
3126}
3127
3128static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3129 enum pipe pipe,
3130 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3131 uint32_t *val)
3132{
8d2f24ca
DV		 3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 bool need_stable_symbols = false;
3135
46a19188
DV		 3136 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3137 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3138 if (ret)
3139 return ret;
3140 }
3141
3142 switch (*source) {
7ac0129b
DV		 3143 case INTEL_PIPE_CRC_SOURCE_PIPE:
3144 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3145 break;
3146 case INTEL_PIPE_CRC_SOURCE_DP_B:
3147 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3148 need_stable_symbols = true;
7ac0129b
DV		 3149 break;
3150 case INTEL_PIPE_CRC_SOURCE_DP_C:
3151 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3152 need_stable_symbols = true;
7ac0129b 3153 break;
2be57922
VS		 3154 case INTEL_PIPE_CRC_SOURCE_DP_D:
3155 if (!IS_CHERRYVIEW(dev))
3156 return -EINVAL;
3157 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3158 need_stable_symbols = true;
3159 break;
7ac0129b
DV		 3160 case INTEL_PIPE_CRC_SOURCE_NONE:
3161 *val = 0;
3162 break;
3163 default:
3164 return -EINVAL;
3165 }
3166
8d2f24ca
DV		 3167 /*
3168 * When the pipe CRC tap point is after the transcoders we need
3169 * to tweak symbol-level features to produce a deterministic series of
3170 * symbols for a given frame. We need to reset those features only once
3171 * a frame (instead of every nth symbol):
3172 * - DC-balance: used to ensure a better clock recovery from the data
3173 * link (SDVO)
3174 * - DisplayPort scrambling: used for EMI reduction
3175 */
3176 if (need_stable_symbols) {
3177 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3178
8d2f24ca 3179 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3180 switch (pipe) {
3181 case PIPE_A:
8d2f24ca 3182 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3183 break;
3184 case PIPE_B:
8d2f24ca 3185 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3186 break;
3187 case PIPE_C:
3188 tmp |= PIPE_C_SCRAMBLE_RESET;
3189 break;
3190 default:
3191 return -EINVAL;
3192 }
8d2f24ca
DV		 3193 I915_WRITE(PORT_DFT2_G4X, tmp);
3194 }
3195
7ac0129b
DV		 3196 return 0;
3197}
3198
4b79ebf7 3199static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3200 enum pipe pipe,
3201 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3202 uint32_t *val)
3203{
84093603
DV		 3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 bool need_stable_symbols = false;
3206
46a19188
DV		 3207 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3208 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3209 if (ret)
3210 return ret;
3211 }
3212
3213 switch (*source) {
4b79ebf7
DV		 3214 case INTEL_PIPE_CRC_SOURCE_PIPE:
3215 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3216 break;
3217 case INTEL_PIPE_CRC_SOURCE_TV:
3218 if (!SUPPORTS_TV(dev))
3219 return -EINVAL;
3220 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3221 break;
3222 case INTEL_PIPE_CRC_SOURCE_DP_B:
3223 if (!IS_G4X(dev))
3224 return -EINVAL;
3225 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3226 need_stable_symbols = true;
4b79ebf7
DV		 3227 break;
3228 case INTEL_PIPE_CRC_SOURCE_DP_C:
3229 if (!IS_G4X(dev))
3230 return -EINVAL;
3231 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3232 need_stable_symbols = true;
4b79ebf7
DV		 3233 break;
3234 case INTEL_PIPE_CRC_SOURCE_DP_D:
3235 if (!IS_G4X(dev))
3236 return -EINVAL;
3237 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3238 need_stable_symbols = true;
4b79ebf7
DV		 3239 break;
3240 case INTEL_PIPE_CRC_SOURCE_NONE:
3241 *val = 0;
3242 break;
3243 default:
3244 return -EINVAL;
3245 }
3246
84093603
DV		 3247 /*
3248 * When the pipe CRC tap point is after the transcoders we need
3249 * to tweak symbol-level features to produce a deterministic series of
3250 * symbols for a given frame. We need to reset those features only once
3251 * a frame (instead of every nth symbol):
3252 * - DC-balance: used to ensure a better clock recovery from the data
3253 * link (SDVO)
3254 * - DisplayPort scrambling: used for EMI reduction
3255 */
3256 if (need_stable_symbols) {
3257 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3258
3259 WARN_ON(!IS_G4X(dev));
3260
3261 I915_WRITE(PORT_DFT_I9XX,
3262 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3263
3264 if (pipe == PIPE_A)
3265 tmp |= PIPE_A_SCRAMBLE_RESET;
3266 else
3267 tmp |= PIPE_B_SCRAMBLE_RESET;
3268
3269 I915_WRITE(PORT_DFT2_G4X, tmp);
3270 }
3271
4b79ebf7
DV		 3272 return 0;
3273}
3274
8d2f24ca
DV		 3275static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3276 enum pipe pipe)
3277{
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3280
eb736679
VS		 3281 switch (pipe) {
3282 case PIPE_A:
8d2f24ca 3283 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3284 break;
3285 case PIPE_B:
8d2f24ca 3286 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3287 break;
3288 case PIPE_C:
3289 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3290 break;
3291 default:
3292 return;
3293 }
8d2f24ca
DV		 3294 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3295 tmp &= ~DC_BALANCE_RESET_VLV;
3296 I915_WRITE(PORT_DFT2_G4X, tmp);
3297
3298}
3299
84093603
DV		 3300static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3301 enum pipe pipe)
3302{
3303 struct drm_i915_private *dev_priv = dev->dev_private;
3304 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3305
3306 if (pipe == PIPE_A)
3307 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3308 else
3309 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3310 I915_WRITE(PORT_DFT2_G4X, tmp);
3311
3312 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3313 I915_WRITE(PORT_DFT_I9XX,
3314 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3315 }
3316}
3317
46a19188 3318static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3319 uint32_t *val)
3320{
46a19188
DV		 3321 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3322 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3323
3324 switch (*source) {
5b3a856b
DV		 3325 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3326 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3327 break;
3328 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3329 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3330 break;
5b3a856b
DV		 3331 case INTEL_PIPE_CRC_SOURCE_PIPE:
3332 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3333 break;
3d099a05 3334 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3335 *val = 0;
3336 break;
3d099a05
DV		 3337 default:
3338 return -EINVAL;
5b3a856b
DV		 3339 }
3340
3341 return 0;
3342}
3343
fabf6e51
DV		 3344static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3345{
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_crtc *crtc =
3348 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3349
3350 drm_modeset_lock_all(dev);
3351 /*
3352 * If we use the eDP transcoder we need to make sure that we don't
3353 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3354 * relevant on hsw with pipe A when using the always-on power well
3355 * routing.
3356 */
6e3c9717
ACO		 3357 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3358 !crtc->config->pch_pfit.enabled) {
3359 crtc->config->pch_pfit.force_thru = true;
fabf6e51
DV		 3360
3361 intel_display_power_get(dev_priv,
3362 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3363
3364 dev_priv->display.crtc_disable(&crtc->base);
3365 dev_priv->display.crtc_enable(&crtc->base);
3366 }
3367 drm_modeset_unlock_all(dev);
3368}
3369
3370static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3371{
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 struct intel_crtc *crtc =
3374 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3375
3376 drm_modeset_lock_all(dev);
3377 /*
3378 * If we use the eDP transcoder we need to make sure that we don't
3379 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3380 * relevant on hsw with pipe A when using the always-on power well
3381 * routing.
3382 */
6e3c9717
ACO		 3383 if (crtc->config->pch_pfit.force_thru) {
3384 crtc->config->pch_pfit.force_thru = false;
fabf6e51
DV		 3385
3386 dev_priv->display.crtc_disable(&crtc->base);
3387 dev_priv->display.crtc_enable(&crtc->base);
3388
3389 intel_display_power_put(dev_priv,
3390 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3391 }
3392 drm_modeset_unlock_all(dev);
3393}
3394
3395static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3396 enum pipe pipe,
3397 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3398 uint32_t *val)
3399{
46a19188
DV		 3400 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3401 *source = INTEL_PIPE_CRC_SOURCE_PF;
3402
3403 switch (*source) {
5b3a856b
DV		 3404 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3405 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3406 break;
3407 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3408 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3409 break;
3410 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3411 if (IS_HASWELL(dev) && pipe == PIPE_A)
3412 hsw_trans_edp_pipe_A_crc_wa(dev);
3413
5b3a856b
DV		 3414 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3415 break;
3d099a05 3416 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3417 *val = 0;
3418 break;
3d099a05
DV		 3419 default:
3420 return -EINVAL;
5b3a856b
DV		 3421 }
3422
3423 return 0;
3424}
3425
926321d5
DV		 3426static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3427 enum intel_pipe_crc_source source)
3428{
3429 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3430 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3431 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3432 pipe));
432f3342 3433 u32 val = 0; /* shut up gcc */
5b3a856b 3434 int ret;
926321d5 3435
cc3da175
DL		 3436 if (pipe_crc->source == source)
3437 return 0;
3438
ae676fcd
DL		 3439 /* forbid changing the source without going back to 'none' */
3440 if (pipe_crc->source && source)
3441 return -EINVAL;
3442
9d8b0588
DV		 3443 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3444 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3445 return -EIO;
3446 }
3447
52f843f6 3448 if (IS_GEN2(dev))
46a19188 3449 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3450 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3451 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3452 else if (IS_VALLEYVIEW(dev))
fabf6e51 3453 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3454 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3455 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3456 else
fabf6e51 3457 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3458
3459 if (ret != 0)
3460 return ret;
3461
4b584369
DL		 3462 /* none -> real source transition */
3463 if (source) {
4252fbc3
VS		 3464 struct intel_pipe_crc_entry *entries;
3465
7cd6ccff
DL		 3466 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3467 pipe_name(pipe), pipe_crc_source_name(source));
3468
3cf54b34
VS		 3469 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3470 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3471 GFP_KERNEL);
3472 if (!entries)
e5f75aca
DL		 3473 return -ENOMEM;
3474
8c740dce
PZ		 3475 /*
3476 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3477 * enabled and disabled dynamically based on package C states,
3478 * user space can't make reliable use of the CRCs, so let's just
3479 * completely disable it.
3480 */
3481 hsw_disable_ips(crtc);
3482
d538bbdf 3483 spin_lock_irq(&pipe_crc->lock);
64387b61 3484 kfree(pipe_crc->entries);
4252fbc3 3485 pipe_crc->entries = entries;
d538bbdf
DL		 3486 pipe_crc->head = 0;
3487 pipe_crc->tail = 0;
3488 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3489 }
3490
cc3da175 3491 pipe_crc->source = source;
926321d5 3492
926321d5
DV		 3493 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3494 POSTING_READ(PIPE_CRC_CTL(pipe));
3495
e5f75aca
DL		 3496 /* real source -> none transition */
3497 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3498 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3499 struct intel_crtc *crtc =
3500 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3501
7cd6ccff
DL		 3502 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3503 pipe_name(pipe));
3504
a33d7105
DV		 3505 drm_modeset_lock(&crtc->base.mutex, NULL);
3506 if (crtc->active)
3507 intel_wait_for_vblank(dev, pipe);
3508 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3509
d538bbdf
DL		 3510 spin_lock_irq(&pipe_crc->lock);
3511 entries = pipe_crc->entries;
e5f75aca 3512 pipe_crc->entries = NULL;
9ad6d99f
VS		 3513 pipe_crc->head = 0;
3514 pipe_crc->tail = 0;
d538bbdf
DL		 3515 spin_unlock_irq(&pipe_crc->lock);
3516
3517 kfree(entries);
84093603
DV		 3518
3519 if (IS_G4X(dev))
3520 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3521 else if (IS_VALLEYVIEW(dev))
3522 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3523 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3524 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3525
3526 hsw_enable_ips(crtc);
e5f75aca
DL		 3527 }
3528
926321d5
DV		 3529 return 0;
3530}
3531
3532/*
3533 * Parse pipe CRC command strings:
b94dec87
DL		 3534 * command: wsp* object wsp+ name wsp+ source wsp*
3535 * object: 'pipe'
3536 * name: (A | B | C)
926321d5
DV		 3537 * source: (none | plane1 | plane2 | pf)
3538 * wsp: (#0x20 | #0x9 | #0xA)+
3539 *
3540 * eg.:
b94dec87
DL		 3541 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3542 * "pipe A none" -> Stop CRC
926321d5 3543 */
bd9db02f 3544static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3545{
3546 int n_words = 0;
3547
3548 while (*buf) {
3549 char *end;
3550
3551 /* skip leading white space */
3552 buf = skip_spaces(buf);
3553 if (!*buf)
3554 break; /* end of buffer */
3555
3556 /* find end of word */
3557 for (end = buf; *end && !isspace(*end); end++)
3558 ;
3559
3560 if (n_words == max_words) {
3561 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3562 max_words);
3563 return -EINVAL; /* ran out of words[] before bytes */
3564 }
3565
3566 if (*end)
3567 *end++ = '\0';
3568 words[n_words++] = buf;
3569 buf = end;
3570 }
3571
3572 return n_words;
3573}
3574
b94dec87
DL		 3575enum intel_pipe_crc_object {
3576 PIPE_CRC_OBJECT_PIPE,
3577};
3578
e8dfcf78 3579static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3580 "pipe",
3581};
3582
3583static int
bd9db02f 3584display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3585{
3586 int i;
3587
3588 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3589 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3590 *o = i;
b94dec87
DL		 3591 return 0;
3592 }
3593
3594 return -EINVAL;
3595}
3596
bd9db02f 3597static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3598{
3599 const char name = buf[0];
3600
3601 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3602 return -EINVAL;
3603
3604 *pipe = name - 'A';
3605
3606 return 0;
3607}
3608
3609static int
bd9db02f 3610display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3611{
3612 int i;
3613
3614 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3615 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3616 *s = i;
926321d5
DV		 3617 return 0;
3618 }
3619
3620 return -EINVAL;
3621}
3622
bd9db02f 3623static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3624{
b94dec87 3625#define N_WORDS 3
926321d5 3626 int n_words;
b94dec87 3627 char *words[N_WORDS];
926321d5 3628 enum pipe pipe;
b94dec87 3629 enum intel_pipe_crc_object object;
926321d5
DV		 3630 enum intel_pipe_crc_source source;
3631
bd9db02f 3632 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3633 if (n_words != N_WORDS) {
3634 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3635 N_WORDS);
3636 return -EINVAL;
3637 }
3638
bd9db02f 3639 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3640 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3641 return -EINVAL;
3642 }
3643
bd9db02f 3644 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3645 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3646 return -EINVAL;
3647 }
3648
bd9db02f 3649 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3650 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3651 return -EINVAL;
3652 }
3653
3654 return pipe_crc_set_source(dev, pipe, source);
3655}
3656
bd9db02f
DL		 3657static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3658 size_t len, loff_t *offp)
926321d5
DV		 3659{
3660 struct seq_file *m = file->private_data;
3661 struct drm_device *dev = m->private;
3662 char *tmpbuf;
3663 int ret;
3664
3665 if (len == 0)
3666 return 0;
3667
3668 if (len > PAGE_SIZE - 1) {
3669 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3670 PAGE_SIZE);
3671 return -E2BIG;
3672 }
3673
3674 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3675 if (!tmpbuf)
3676 return -ENOMEM;
3677
3678 if (copy_from_user(tmpbuf, ubuf, len)) {
3679 ret = -EFAULT;
3680 goto out;
3681 }
3682 tmpbuf[len] = '\0';
3683
bd9db02f 3684 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3685
3686out:
3687 kfree(tmpbuf);
3688 if (ret < 0)
3689 return ret;
3690
3691 *offp += len;
3692 return len;
3693}
3694
bd9db02f 3695static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3696 .owner = THIS_MODULE,
bd9db02f 3697 .open = display_crc_ctl_open,
926321d5
DV		 3698 .read = seq_read,
3699 .llseek = seq_lseek,
3700 .release = single_release,
bd9db02f 3701 .write = display_crc_ctl_write
926321d5
DV		 3702};
3703
97e94b22 3704static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3705{
3706 struct drm_device *dev = m->private;
546c81fd 3707 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3708 int level;
3709
3710 drm_modeset_lock_all(dev);
3711
3712 for (level = 0; level < num_levels; level++) {
3713 unsigned int latency = wm[level];
3714
97e94b22
DL		 3715 /*
3716 * - WM1+ latency values in 0.5us units
3717 * - latencies are in us on gen9
3718 */
3719 if (INTEL_INFO(dev)->gen >= 9)
3720 latency *= 10;
3721 else if (level > 0)
369a1342
VS		 3722 latency *= 5;
3723
3724 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3725 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3726 }
3727
3728 drm_modeset_unlock_all(dev);
3729}
3730
3731static int pri_wm_latency_show(struct seq_file *m, void *data)
3732{
3733 struct drm_device *dev = m->private;
97e94b22
DL		 3734 struct drm_i915_private *dev_priv = dev->dev_private;
3735 const uint16_t *latencies;
3736
3737 if (INTEL_INFO(dev)->gen >= 9)
3738 latencies = dev_priv->wm.skl_latency;
3739 else
3740 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3741
97e94b22 3742 wm_latency_show(m, latencies);
369a1342
VS		 3743
3744 return 0;
3745}
3746
3747static int spr_wm_latency_show(struct seq_file *m, void *data)
3748{
3749 struct drm_device *dev = m->private;
97e94b22
DL		 3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 const uint16_t *latencies;
3752
3753 if (INTEL_INFO(dev)->gen >= 9)
3754 latencies = dev_priv->wm.skl_latency;
3755 else
3756 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3757
97e94b22 3758 wm_latency_show(m, latencies);
369a1342
VS		 3759
3760 return 0;
3761}
3762
3763static int cur_wm_latency_show(struct seq_file *m, void *data)
3764{
3765 struct drm_device *dev = m->private;
97e94b22
DL		 3766 struct drm_i915_private *dev_priv = dev->dev_private;
3767 const uint16_t *latencies;
3768
3769 if (INTEL_INFO(dev)->gen >= 9)
3770 latencies = dev_priv->wm.skl_latency;
3771 else
3772 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3773
97e94b22 3774 wm_latency_show(m, latencies);
369a1342
VS		 3775
3776 return 0;
3777}
3778
3779static int pri_wm_latency_open(struct inode *inode, struct file *file)
3780{
3781 struct drm_device *dev = inode->i_private;
3782
9ad0257c 3783 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3784 return -ENODEV;
3785
3786 return single_open(file, pri_wm_latency_show, dev);
3787}
3788
3789static int spr_wm_latency_open(struct inode *inode, struct file *file)
3790{
3791 struct drm_device *dev = inode->i_private;
3792
9ad0257c 3793 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3794 return -ENODEV;
3795
3796 return single_open(file, spr_wm_latency_show, dev);
3797}
3798
3799static int cur_wm_latency_open(struct inode *inode, struct file *file)
3800{
3801 struct drm_device *dev = inode->i_private;
3802
9ad0257c 3803 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3804 return -ENODEV;
3805
3806 return single_open(file, cur_wm_latency_show, dev);
3807}
3808
3809static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 3810 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 3811{
3812 struct seq_file *m = file->private_data;
3813 struct drm_device *dev = m->private;
97e94b22 3814 uint16_t new[8] = { 0 };
546c81fd 3815 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3816 int level;
3817 int ret;
3818 char tmp[32];
3819
3820 if (len >= sizeof(tmp))
3821 return -EINVAL;
3822
3823 if (copy_from_user(tmp, ubuf, len))
3824 return -EFAULT;
3825
3826 tmp[len] = '\0';
3827
97e94b22
DL		 3828 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3829 &new[0], &new[1], &new[2], &new[3],
3830 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 3831 if (ret != num_levels)
3832 return -EINVAL;
3833
3834 drm_modeset_lock_all(dev);
3835
3836 for (level = 0; level < num_levels; level++)
3837 wm[level] = new[level];
3838
3839 drm_modeset_unlock_all(dev);
3840
3841 return len;
3842}
3843
3844
3845static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3846 size_t len, loff_t *offp)
3847{
3848 struct seq_file *m = file->private_data;
3849 struct drm_device *dev = m->private;
97e94b22
DL		 3850 struct drm_i915_private *dev_priv = dev->dev_private;
3851 uint16_t *latencies;
369a1342 3852
97e94b22
DL		 3853 if (INTEL_INFO(dev)->gen >= 9)
3854 latencies = dev_priv->wm.skl_latency;
3855 else
3856 latencies = to_i915(dev)->wm.pri_latency;
3857
3858 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3859}
3860
3861static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3862 size_t len, loff_t *offp)
3863{
3864 struct seq_file *m = file->private_data;
3865 struct drm_device *dev = m->private;
97e94b22
DL		 3866 struct drm_i915_private *dev_priv = dev->dev_private;
3867 uint16_t *latencies;
369a1342 3868
97e94b22
DL		 3869 if (INTEL_INFO(dev)->gen >= 9)
3870 latencies = dev_priv->wm.skl_latency;
3871 else
3872 latencies = to_i915(dev)->wm.spr_latency;
3873
3874 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3875}
3876
3877static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3878 size_t len, loff_t *offp)
3879{
3880 struct seq_file *m = file->private_data;
3881 struct drm_device *dev = m->private;
97e94b22
DL		 3882 struct drm_i915_private *dev_priv = dev->dev_private;
3883 uint16_t *latencies;
3884
3885 if (INTEL_INFO(dev)->gen >= 9)
3886 latencies = dev_priv->wm.skl_latency;
3887 else
3888 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3889
97e94b22 3890 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3891}
3892
3893static const struct file_operations i915_pri_wm_latency_fops = {
3894 .owner = THIS_MODULE,
3895 .open = pri_wm_latency_open,
3896 .read = seq_read,
3897 .llseek = seq_lseek,
3898 .release = single_release,
3899 .write = pri_wm_latency_write
3900};
3901
3902static const struct file_operations i915_spr_wm_latency_fops = {
3903 .owner = THIS_MODULE,
3904 .open = spr_wm_latency_open,
3905 .read = seq_read,
3906 .llseek = seq_lseek,
3907 .release = single_release,
3908 .write = spr_wm_latency_write
3909};
3910
3911static const struct file_operations i915_cur_wm_latency_fops = {
3912 .owner = THIS_MODULE,
3913 .open = cur_wm_latency_open,
3914 .read = seq_read,
3915 .llseek = seq_lseek,
3916 .release = single_release,
3917 .write = cur_wm_latency_write
3918};
3919
647416f9
KC		 3920static int
3921i915_wedged_get(void *data, u64 *val)
f3cd474b 3922{
647416f9 3923 struct drm_device *dev = data;
e277a1f8 3924 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3925
647416f9 3926 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3927
647416f9 3928 return 0;
f3cd474b
CW		 3929}
3930
647416f9
KC		 3931static int
3932i915_wedged_set(void *data, u64 val)
f3cd474b 3933{
647416f9 3934 struct drm_device *dev = data;
d46c0517
ID		 3935 struct drm_i915_private *dev_priv = dev->dev_private;
3936
3937 intel_runtime_pm_get(dev_priv);
f3cd474b 3938
58174462
MK		 3939 i915_handle_error(dev, val,
3940 "Manually setting wedged to %llu", val);
d46c0517
ID		 3941
3942 intel_runtime_pm_put(dev_priv);
3943
647416f9 3944 return 0;
f3cd474b
CW		 3945}
3946
647416f9
KC		 3947DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3948 i915_wedged_get, i915_wedged_set,
3a3b4f98 3949 "%llu\n");
f3cd474b 3950
647416f9
KC		 3951static int
3952i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3953{
647416f9 3954 struct drm_device *dev = data;
e277a1f8 3955 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3956
647416f9 3957 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3958
647416f9 3959 return 0;
e5eb3d63
DV		 3960}
3961
647416f9
KC		 3962static int
3963i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3964{
647416f9 3965 struct drm_device *dev = data;
e5eb3d63 3966 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3967 int ret;
e5eb3d63 3968
647416f9 3969 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3970
22bcfc6a
DV		 3971 ret = mutex_lock_interruptible(&dev->struct_mutex);
3972 if (ret)
3973 return ret;
3974
99584db3 3975 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3976 mutex_unlock(&dev->struct_mutex);
3977
647416f9 3978 return 0;
e5eb3d63
DV		 3979}
3980
647416f9
KC		 3981DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3982 i915_ring_stop_get, i915_ring_stop_set,
3983 "0x%08llx\n");
d5442303 3984
094f9a54
CW		 3985static int
3986i915_ring_missed_irq_get(void *data, u64 *val)
3987{
3988 struct drm_device *dev = data;
3989 struct drm_i915_private *dev_priv = dev->dev_private;
3990
3991 *val = dev_priv->gpu_error.missed_irq_rings;
3992 return 0;
3993}
3994
3995static int
3996i915_ring_missed_irq_set(void *data, u64 val)
3997{
3998 struct drm_device *dev = data;
3999 struct drm_i915_private *dev_priv = dev->dev_private;
4000 int ret;
4001
4002 /* Lock against concurrent debugfs callers */
4003 ret = mutex_lock_interruptible(&dev->struct_mutex);
4004 if (ret)
4005 return ret;
4006 dev_priv->gpu_error.missed_irq_rings = val;
4007 mutex_unlock(&dev->struct_mutex);
4008
4009 return 0;
4010}
4011
4012DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4013 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4014 "0x%08llx\n");
4015
4016static int
4017i915_ring_test_irq_get(void *data, u64 *val)
4018{
4019 struct drm_device *dev = data;
4020 struct drm_i915_private *dev_priv = dev->dev_private;
4021
4022 *val = dev_priv->gpu_error.test_irq_rings;
4023
4024 return 0;
4025}
4026
4027static int
4028i915_ring_test_irq_set(void *data, u64 val)
4029{
4030 struct drm_device *dev = data;
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4032 int ret;
4033
4034 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4035
4036 /* Lock against concurrent debugfs callers */
4037 ret = mutex_lock_interruptible(&dev->struct_mutex);
4038 if (ret)
4039 return ret;
4040
4041 dev_priv->gpu_error.test_irq_rings = val;
4042 mutex_unlock(&dev->struct_mutex);
4043
4044 return 0;
4045}
4046
4047DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4048 i915_ring_test_irq_get, i915_ring_test_irq_set,
4049 "0x%08llx\n");
4050
dd624afd
CW		 4051#define DROP_UNBOUND 0x1
4052#define DROP_BOUND 0x2
4053#define DROP_RETIRE 0x4
4054#define DROP_ACTIVE 0x8
4055#define DROP_ALL (DROP_UNBOUND | \
4056 DROP_BOUND | \
4057 DROP_RETIRE | \
4058 DROP_ACTIVE)
647416f9
KC		 4059static int
4060i915_drop_caches_get(void *data, u64 *val)
dd624afd 4061{
647416f9 4062 *val = DROP_ALL;
dd624afd 4063
647416f9 4064 return 0;
dd624afd
CW		 4065}
4066
647416f9
KC		 4067static int
4068i915_drop_caches_set(void *data, u64 val)
dd624afd 4069{
647416f9 4070 struct drm_device *dev = data;
dd624afd 4071 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4072 int ret;
dd624afd 4073
2f9fe5ff 4074 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4075
4076 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4077 * on ioctls on -EAGAIN. */
4078 ret = mutex_lock_interruptible(&dev->struct_mutex);
4079 if (ret)
4080 return ret;
4081
4082 if (val & DROP_ACTIVE) {
4083 ret = i915_gpu_idle(dev);
4084 if (ret)
4085 goto unlock;
4086 }
4087
4088 if (val & (DROP_RETIRE | DROP_ACTIVE))
4089 i915_gem_retire_requests(dev);
4090
21ab4e74
CW		 4091 if (val & DROP_BOUND)
4092 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4093
21ab4e74
CW		 4094 if (val & DROP_UNBOUND)
4095 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4096
4097unlock:
4098 mutex_unlock(&dev->struct_mutex);
4099
647416f9 4100 return ret;
dd624afd
CW		 4101}
4102
647416f9
KC		 4103DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4104 i915_drop_caches_get, i915_drop_caches_set,
4105 "0x%08llx\n");
dd624afd 4106
647416f9
KC		 4107static int
4108i915_max_freq_get(void *data, u64 *val)
358733e9 4109{
647416f9 4110 struct drm_device *dev = data;
e277a1f8 4111 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4112 int ret;
004777cb 4113
daa3afb2 4114 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4115 return -ENODEV;
4116
5c9669ce
TR		 4117 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4118
4fc688ce 4119 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4120 if (ret)
4121 return ret;
358733e9 4122
7c59a9c1 4123 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4124 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4125
647416f9 4126 return 0;
358733e9
JB		 4127}
4128
647416f9
KC		 4129static int
4130i915_max_freq_set(void *data, u64 val)
358733e9 4131{
647416f9 4132 struct drm_device *dev = data;
358733e9 4133 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4134 u32 rp_state_cap, hw_max, hw_min;
647416f9 4135 int ret;
004777cb 4136
daa3afb2 4137 if (INTEL_INFO(dev)->gen < 6)
004777cb 4138 return -ENODEV;
358733e9 4139
5c9669ce
TR		 4140 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4141
647416f9 4142 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4143
4fc688ce 4144 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4145 if (ret)
4146 return ret;
4147
358733e9
JB		 4148 /*
4149 * Turbo will still be enabled, but won't go above the set value.
4150 */
0a073b84 4151 if (IS_VALLEYVIEW(dev)) {
7c59a9c1 4152 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4153
03af2045
VS		 4154 hw_max = dev_priv->rps.max_freq;
4155 hw_min = dev_priv->rps.min_freq;
0a073b84 4156 } else {
7c59a9c1 4157 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 4158
4159 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4160 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4161 hw_min = (rp_state_cap >> 16) & 0xff;
4162 }
4163
b39fb297 4164 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4165 mutex_unlock(&dev_priv->rps.hw_lock);
4166 return -EINVAL;
0a073b84
JB		 4167 }
4168
b39fb297 4169 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 4170
4171 if (IS_VALLEYVIEW(dev))
4172 valleyview_set_rps(dev, val);
4173 else
4174 gen6_set_rps(dev, val);
4175
4fc688ce 4176 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4177
647416f9 4178 return 0;
358733e9
JB		 4179}
4180
647416f9
KC		 4181DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4182 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4183 "%llu\n");
358733e9 4184
647416f9
KC		 4185static int
4186i915_min_freq_get(void *data, u64 *val)
1523c310 4187{
647416f9 4188 struct drm_device *dev = data;
e277a1f8 4189 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4190 int ret;
004777cb 4191
daa3afb2 4192 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4193 return -ENODEV;
4194
5c9669ce
TR		 4195 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4196
4fc688ce 4197 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4198 if (ret)
4199 return ret;
1523c310 4200
7c59a9c1 4201 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4202 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4203
647416f9 4204 return 0;
1523c310
JB		 4205}
4206
647416f9
KC		 4207static int
4208i915_min_freq_set(void *data, u64 val)
1523c310 4209{
647416f9 4210 struct drm_device *dev = data;
1523c310 4211 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4212 u32 rp_state_cap, hw_max, hw_min;
647416f9 4213 int ret;
004777cb 4214
daa3afb2 4215 if (INTEL_INFO(dev)->gen < 6)
004777cb 4216 return -ENODEV;
1523c310 4217
5c9669ce
TR		 4218 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4219
647416f9 4220 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4221
4fc688ce 4222 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4223 if (ret)
4224 return ret;
4225
1523c310
JB		 4226 /*
4227 * Turbo will still be enabled, but won't go below the set value.
4228 */
0a073b84 4229 if (IS_VALLEYVIEW(dev)) {
7c59a9c1 4230 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4231
03af2045
VS		 4232 hw_max = dev_priv->rps.max_freq;
4233 hw_min = dev_priv->rps.min_freq;
0a073b84 4234 } else {
7c59a9c1 4235 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 4236
4237 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4238 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4239 hw_min = (rp_state_cap >> 16) & 0xff;
4240 }
4241
b39fb297 4242 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4243 mutex_unlock(&dev_priv->rps.hw_lock);
4244 return -EINVAL;
0a073b84 4245 }
dd0a1aa1 4246
b39fb297 4247 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 4248
4249 if (IS_VALLEYVIEW(dev))
4250 valleyview_set_rps(dev, val);
4251 else
4252 gen6_set_rps(dev, val);
4253
4fc688ce 4254 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4255
647416f9 4256 return 0;
1523c310
JB		 4257}
4258
647416f9
KC		 4259DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4260 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4261 "%llu\n");
1523c310 4262
647416f9
KC		 4263static int
4264i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4265{
647416f9 4266 struct drm_device *dev = data;
e277a1f8 4267 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4268 u32 snpcr;
647416f9 4269 int ret;
07b7ddd9 4270
004777cb
DV		 4271 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4272 return -ENODEV;
4273
22bcfc6a
DV		 4274 ret = mutex_lock_interruptible(&dev->struct_mutex);
4275 if (ret)
4276 return ret;
c8c8fb33 4277 intel_runtime_pm_get(dev_priv);
22bcfc6a 4278
07b7ddd9 4279 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4280
4281 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4282 mutex_unlock(&dev_priv->dev->struct_mutex);
4283
647416f9 4284 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4285
647416f9 4286 return 0;
07b7ddd9
JB		 4287}
4288
647416f9
KC		 4289static int
4290i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4291{
647416f9 4292 struct drm_device *dev = data;
07b7ddd9 4293 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4294 u32 snpcr;
07b7ddd9 4295
004777cb
DV		 4296 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4297 return -ENODEV;
4298
647416f9 4299 if (val > 3)
07b7ddd9
JB		 4300 return -EINVAL;
4301
c8c8fb33 4302 intel_runtime_pm_get(dev_priv);
647416f9 4303 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4304
4305 /* Update the cache sharing policy here as well */
4306 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4307 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4308 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4309 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4310
c8c8fb33 4311 intel_runtime_pm_put(dev_priv);
647416f9 4312 return 0;
07b7ddd9
JB		 4313}
4314
647416f9
KC		 4315DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4316 i915_cache_sharing_get, i915_cache_sharing_set,
4317 "%llu\n");
07b7ddd9 4318
6d794d42
BW		 4319static int i915_forcewake_open(struct inode *inode, struct file *file)
4320{
4321 struct drm_device *dev = inode->i_private;
4322 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4323
075edca4 4324 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4325 return 0;
4326
6daccb0b 4327 intel_runtime_pm_get(dev_priv);
59bad947 4328 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4329
4330 return 0;
4331}
4332
c43b5634 4333static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4334{
4335 struct drm_device *dev = inode->i_private;
4336 struct drm_i915_private *dev_priv = dev->dev_private;
4337
075edca4 4338 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4339 return 0;
4340
59bad947 4341 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 4342 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 4343
4344 return 0;
4345}
4346
4347static const struct file_operations i915_forcewake_fops = {
4348 .owner = THIS_MODULE,
4349 .open = i915_forcewake_open,
4350 .release = i915_forcewake_release,
4351};
4352
4353static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4354{
4355 struct drm_device *dev = minor->dev;
4356 struct dentry *ent;
4357
4358 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4359 S_IRUSR,
6d794d42
BW		 4360 root, dev,
4361 &i915_forcewake_fops);
f3c5fe97
WY		 4362 if (!ent)
4363 return -ENOMEM;
6d794d42 4364
8eb57294 4365 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4366}
4367
6a9c308d
DV		 4368static int i915_debugfs_create(struct dentry *root,
4369 struct drm_minor *minor,
4370 const char *name,
4371 const struct file_operations *fops)
07b7ddd9
JB		 4372{
4373 struct drm_device *dev = minor->dev;
4374 struct dentry *ent;
4375
6a9c308d 4376 ent = debugfs_create_file(name,
07b7ddd9
JB		 4377 S_IRUGO | S_IWUSR,
4378 root, dev,
6a9c308d 4379 fops);
f3c5fe97
WY		 4380 if (!ent)
4381 return -ENOMEM;
07b7ddd9 4382
6a9c308d 4383 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4384}
4385
06c5bf8c 4386static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4387 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4388 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4389 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4390 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4391 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4392 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4393 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4394 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4395 {"i915_gem_request", i915_gem_request_info, 0},
4396 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4397 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4398 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4399 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4400 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4401 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4402 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 4403 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 4404 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1 4405 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4406 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4407 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4408 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4409 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4410 {"i915_sr_status", i915_sr_status, 0},
44834a67 4411 {"i915_opregion", i915_opregion, 0},
37811fcc 4412 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4413 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4414 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4415 {"i915_execlists", i915_execlists, 0},
f65367b5 4416 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 4417 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4418 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4419 {"i915_llc", i915_llc, 0},
e91fd8c6 4420 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4421 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4422 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4423 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4424 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4425 {"i915_display_info", i915_display_info, 0},
e04934cf 4426 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4427 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4428 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4429 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4430 {"i915_ddb_info", i915_ddb_info, 0},
2017263e 4431};
27c202ad 4432#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4433
06c5bf8c 4434static const struct i915_debugfs_files {
34b9674c
DV		 4435 const char *name;
4436 const struct file_operations *fops;
4437} i915_debugfs_files[] = {
4438 {"i915_wedged", &i915_wedged_fops},
4439 {"i915_max_freq", &i915_max_freq_fops},
4440 {"i915_min_freq", &i915_min_freq_fops},
4441 {"i915_cache_sharing", &i915_cache_sharing_fops},
4442 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4443 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4444 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4445 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4446 {"i915_error_state", &i915_error_state_fops},
4447 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4448 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4449 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4450 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4451 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4452 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4453};
4454
07144428
DL		 4455void intel_display_crc_init(struct drm_device *dev)
4456{
4457 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4458 enum pipe pipe;
07144428 4459
055e393f 4460 for_each_pipe(dev_priv, pipe) {
b378360e 4461 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4462
d538bbdf
DL		 4463 pipe_crc->opened = false;
4464 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4465 init_waitqueue_head(&pipe_crc->wq);
4466 }
4467}
4468
27c202ad 4469int i915_debugfs_init(struct drm_minor *minor)
2017263e 4470{
34b9674c 4471 int ret, i;
f3cd474b 4472
6d794d42 4473 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4474 if (ret)
4475 return ret;
6a9c308d 4476
07144428
DL		 4477 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4478 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4479 if (ret)
4480 return ret;
4481 }
4482
34b9674c
DV		 4483 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4484 ret = i915_debugfs_create(minor->debugfs_root, minor,
4485 i915_debugfs_files[i].name,
4486 i915_debugfs_files[i].fops);
4487 if (ret)
4488 return ret;
4489 }
40633219 4490
27c202ad
BG		 4491 return drm_debugfs_create_files(i915_debugfs_list,
4492 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4493 minor->debugfs_root, minor);
4494}
4495
27c202ad 4496void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4497{
34b9674c
DV		 4498 int i;
4499
27c202ad
BG		 4500 drm_debugfs_remove_files(i915_debugfs_list,
4501 I915_DEBUGFS_ENTRIES, minor);
07144428 4502
6d794d42
BW		 4503 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4504 1, minor);
07144428 4505
e309a997 4506 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4507 struct drm_info_list *info_list =
4508 (struct drm_info_list *)&i915_pipe_crc_data[i];
4509
4510 drm_debugfs_remove_files(info_list, 1, minor);
4511 }
4512
34b9674c
DV		 4513 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4514 struct drm_info_list *info_list =
4515 (struct drm_info_list *) i915_debugfs_files[i].fops;
4516
4517 drm_debugfs_remove_files(info_list, 1, minor);
4518 }
2017263e 4519}
Linux kernel - Deliverables
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