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drm/i915: Define IS_BROXTON properly.
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
497666d8
DL		 49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
70d39fe4
CW		 75static int i915_capabilities(struct seq_file *m, void *data)
76{
9f25d007 77 struct drm_info_node *node = m->private;
70d39fe4
CW		 78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
70d39fe4
CW		 88
89 return 0;
90}
2017263e 91
05394f39 92static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 93{
baaa5cfb 94 if (obj->pin_display)
a6172a80
CW		 95 return "p";
96 else
97 return " ";
98}
99
05394f39 100static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 101{
0206e353
AJ		 102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
a6172a80
CW		 108}
109
1d693bcc
BW		 110static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111{
aff43766 112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 113}
114
ca1543be
TU		 115static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116{
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, vma_link) {
121 if (i915_is_ggtt(vma->vm) &&
122 drm_mm_node_allocated(&vma->node))
123 size += vma->node.size;
124 }
125
126 return size;
127}
128
37811fcc
CW		 129static void
130describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
131{
b4716185
CW		 132 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
133 struct intel_engine_cs *ring;
1d693bcc 134 struct i915_vma *vma;
d7f46fc4 135 int pin_count = 0;
b4716185 136 int i;
d7f46fc4 137
b4716185 138 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 139 &obj->base,
481a3d43 140 obj->active ? "*" : " ",
37811fcc
CW		 141 get_pin_flag(obj),
142 get_tiling_flag(obj),
1d693bcc 143 get_global_flag(obj),
a05a5862 144 obj->base.size / 1024,
37811fcc 145 obj->base.read_domains,
b4716185
CW		 146 obj->base.write_domain);
147 for_each_ring(ring, dev_priv, i)
148 seq_printf(m, "%x ",
149 i915_gem_request_get_seqno(obj->last_read_req[i]));
150 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 151 i915_gem_request_get_seqno(obj->last_write_req),
152 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 153 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 154 obj->dirty ? " dirty" : "",
155 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
156 if (obj->base.name)
157 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 159 if (vma->pin_count > 0)
160 pin_count++;
ba0635ff
DC		 161 }
162 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 163 if (obj->pin_display)
164 seq_printf(m, " (display)");
37811fcc
CW		 165 if (obj->fence_reg != I915_FENCE_REG_NONE)
166 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc 167 list_for_each_entry(vma, &obj->vma_list, vma_link) {
8d2fdc3f
TU		 168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma->vm) ? "g" : "pp",
170 vma->node.start, vma->node.size);
171 if (i915_is_ggtt(vma->vm))
172 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
1d693bcc 173 else
8d2fdc3f 174 seq_puts(m, ")");
1d693bcc 175 }
c1ad11fc 176 if (obj->stolen)
440fd528 177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 178 if (obj->pin_display || obj->fault_mappable) {
6299f992 179 char s[3], *t = s;
30154650 180 if (obj->pin_display)
6299f992
CW		 181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
b4716185 187 if (obj->last_write_req != NULL)
41c52415 188 seq_printf(m, " (%s)",
b4716185 189 i915_gem_request_get_ring(obj->last_write_req)->name);
d5a81ef1
DV		 190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 192}
193
273497e5 194static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 195{
ea0c76f8 196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199}
200
433e12f7 201static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 202{
9f25d007 203 struct drm_info_node *node = m->private;
433e12f7
BG		 204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
2017263e 206 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 207 struct drm_i915_private *dev_priv = dev->dev_private;
208 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 209 struct i915_vma *vma;
c44ef60e 210 u64 total_obj_size, total_gtt_size;
8f2480fb 211 int count, ret;
de227ef0
CW		 212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
2017263e 216
ca191b13 217 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 218 switch (list) {
219 case ACTIVE_LIST:
267f0c90 220 seq_puts(m, "Active:\n");
5cef07e1 221 head = &vm->active_list;
433e12f7
BG		 222 break;
223 case INACTIVE_LIST:
267f0c90 224 seq_puts(m, "Inactive:\n");
5cef07e1 225 head = &vm->inactive_list;
433e12f7 226 break;
433e12f7 227 default:
de227ef0
CW		 228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
2017263e 230 }
2017263e 231
8f2480fb 232 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 233 list_for_each_entry(vma, head, mm_list) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
8f2480fb 239 count++;
2017263e 240 }
de227ef0 241 mutex_unlock(&dev->struct_mutex);
5e118f41 242
c44ef60e 243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 244 count, total_obj_size, total_gtt_size);
2017263e
BG		 245 return 0;
246}
247
6d2b8885
CW		 248static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250{
251 struct drm_i915_gem_object *a =
b25cb2f8 252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 253 struct drm_i915_gem_object *b =
b25cb2f8 254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 255
2d05fa16
RV		 256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
6d2b8885
CW		 261}
262
263static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264{
9f25d007 265 struct drm_info_node *node = m->private;
6d2b8885
CW		 266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
c44ef60e 269 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
b25cb2f8 282 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 283
284 total_obj_size += obj->base.size;
ca1543be 285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
b25cb2f8 292 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
b25cb2f8 300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
b25cb2f8 304 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 305 }
306 mutex_unlock(&dev->struct_mutex);
307
c44ef60e 308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 309 count, total_obj_size, total_gtt_size);
310 return 0;
311}
312
6299f992
CW		 313#define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
ca1543be 315 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 316 ++count; \
317 if (obj->map_and_fenceable) { \
f343c5f6 318 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 319 ++mappable_count; \
320 } \
321 } \
0206e353 322} while (0)
6299f992 323
2db8e9d6 324struct file_stats {
6313c204 325 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
2db8e9d6
CW		 330};
331
332static int per_file_stats(int id, void *ptr, void *data)
333{
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
6313c204 336 struct i915_vma *vma;
2db8e9d6
CW		 337
338 stats->count++;
339 stats->total += obj->base.size;
340
c67a17e9
CW		 341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
6313c204
CW		 344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, vma_link) {
346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
351 if (i915_is_ggtt(vma->vm)) {
352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 357 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 358 continue;
359
41c52415 360 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
2db8e9d6 367 } else {
6313c204
CW		 368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
41c52415 370 if (obj->active)
6313c204
CW		 371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
2db8e9d6
CW		 376 }
377
6313c204
CW		 378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
2db8e9d6
CW		 381 return 0;
382}
383
b0da1b79
CW		 384#define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
c44ef60e 386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395} while (0)
493018dc
BV		 396
397static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399{
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
06fbca71 402 struct intel_engine_cs *ring;
8d9d5744 403 int i, j;
493018dc
BV		 404
405 memset(&stats, 0, sizeof(stats));
406
06fbca71 407 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 408 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &ring->batch_pool.cache_list[j],
411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
06fbca71 414 }
493018dc 415
b0da1b79 416 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 417}
418
ca191b13
BW		 419#define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
ca1543be 421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428} while (0)
429
430static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 431{
9f25d007 432 struct drm_info_node *node = m->private;
73aa808f
CW		 433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714 435 u32 count, mappable_count, purgeable_count;
c44ef60e 436 u64 size, mappable_size, purgeable_size;
6299f992 437 struct drm_i915_gem_object *obj;
5cef07e1 438 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 439 struct drm_file *file;
ca191b13 440 struct i915_vma *vma;
73aa808f
CW		 441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
6299f992
CW		 447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
35c20a60 452 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
ca191b13 457 count_vmas(&vm->active_list, mm_list);
c44ef60e 458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 459 count, mappable_count, size, mappable_size);
460
6299f992 461 size = count = mappable_size = mappable_count = 0;
ca191b13 462 count_vmas(&vm->inactive_list, mm_list);
c44ef60e 463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 464 count, mappable_count, size, mappable_size);
465
b7abb714 466 size = count = purgeable_size = purgeable_count = 0;
35c20a60 467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 468 size += obj->base.size, ++count;
b7abb714
CW		 469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
c44ef60e 472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 473
6299f992 474 size = count = mappable_size = mappable_count = 0;
35c20a60 475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 476 if (obj->fault_mappable) {
f343c5f6 477 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 478 ++count;
479 }
30154650 480 if (obj->pin_display) {
f343c5f6 481 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 482 ++mappable_count;
483 }
b7abb714
CW		 484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
6299f992 488 }
c44ef60e 489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 490 purgeable_count, purgeable_size);
c44ef60e 491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 492 mappable_count, mappable_size);
c44ef60e 493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992
CW		 494 count, size);
495
c44ef60e 496 seq_printf(m, "%llu [%llu] gtt total\n",
853ba5d2 497 dev_priv->gtt.base.total,
c44ef60e 498 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 499
493018dc
BV		 500 seq_putc(m, '\n');
501 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 502 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
503 struct file_stats stats;
3ec2f427 504 struct task_struct *task;
2db8e9d6
CW		 505
506 memset(&stats, 0, sizeof(stats));
6313c204 507 stats.file_priv = file->driver_priv;
5b5ffff0 508 spin_lock(&file->table_lock);
2db8e9d6 509 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 510 spin_unlock(&file->table_lock);
3ec2f427
TH		 511 /*
512 * Although we have a valid reference on file->pid, that does
513 * not guarantee that the task_struct who called get_pid() is
514 * still alive (e.g. get_pid(current) => fork() => exit()).
515 * Therefore, we need to protect this ->comm access using RCU.
516 */
517 rcu_read_lock();
518 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 519 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 520 rcu_read_unlock();
2db8e9d6
CW		 521 }
522
73aa808f
CW		 523 mutex_unlock(&dev->struct_mutex);
524
525 return 0;
526}
527
aee56cff 528static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 529{
9f25d007 530 struct drm_info_node *node = m->private;
08c18323 531 struct drm_device *dev = node->minor->dev;
1b50247a 532 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 533 struct drm_i915_private *dev_priv = dev->dev_private;
534 struct drm_i915_gem_object *obj;
c44ef60e 535 u64 total_obj_size, total_gtt_size;
08c18323
CW		 536 int count, ret;
537
538 ret = mutex_lock_interruptible(&dev->struct_mutex);
539 if (ret)
540 return ret;
541
542 total_obj_size = total_gtt_size = count = 0;
35c20a60 543 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 544 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 545 continue;
546
267f0c90 547 seq_puts(m, " ");
08c18323 548 describe_obj(m, obj);
267f0c90 549 seq_putc(m, '\n');
08c18323 550 total_obj_size += obj->base.size;
ca1543be 551 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 552 count++;
553 }
554
555 mutex_unlock(&dev->struct_mutex);
556
c44ef60e 557 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 558 count, total_obj_size, total_gtt_size);
559
560 return 0;
561}
562
4e5359cd
SF		 563static int i915_gem_pageflip_info(struct seq_file *m, void *data)
564{
9f25d007 565 struct drm_info_node *node = m->private;
4e5359cd 566 struct drm_device *dev = node->minor->dev;
d6bbafa1 567 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 568 struct intel_crtc *crtc;
8a270ebf
DV		 569 int ret;
570
571 ret = mutex_lock_interruptible(&dev->struct_mutex);
572 if (ret)
573 return ret;
4e5359cd 574
d3fcc808 575 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 576 const char pipe = pipe_name(crtc->pipe);
577 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 578 struct intel_unpin_work *work;
579
5e2d7afc 580 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 581 work = crtc->unpin_work;
582 if (work == NULL) {
9db4a9c7 583 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 584 pipe, plane);
585 } else {
d6bbafa1
CW		 586 u32 addr;
587
e7d841ca 588 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 589 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 590 pipe, plane);
591 } else {
9db4a9c7 592 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 593 pipe, plane);
594 }
3a8a946e
DV		 595 if (work->flip_queued_req) {
596 struct intel_engine_cs *ring =
597 i915_gem_request_get_ring(work->flip_queued_req);
598
20e28fba 599 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 600 ring->name,
f06cc1b9 601 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 602 dev_priv->next_seqno,
3a8a946e 603 ring->get_seqno(ring, true),
1b5a433a 604 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 605 } else
606 seq_printf(m, "Flip not associated with any ring\n");
607 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
608 work->flip_queued_vblank,
609 work->flip_ready_vblank,
1e3feefd 610 drm_crtc_vblank_count(&crtc->base));
4e5359cd 611 if (work->enable_stall_check)
267f0c90 612 seq_puts(m, "Stall check enabled, ");
4e5359cd 613 else
267f0c90 614 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 615 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 616
d6bbafa1
CW		 617 if (INTEL_INFO(dev)->gen >= 4)
618 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
619 else
620 addr = I915_READ(DSPADDR(crtc->plane));
621 seq_printf(m, "Current scanout address 0x%08x\n", addr);
622
4e5359cd 623 if (work->pending_flip_obj) {
d6bbafa1
CW		 624 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
625 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 626 }
627 }
5e2d7afc 628 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 629 }
630
8a270ebf
DV		 631 mutex_unlock(&dev->struct_mutex);
632
4e5359cd
SF		 633 return 0;
634}
635
493018dc
BV		 636static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
637{
638 struct drm_info_node *node = m->private;
639 struct drm_device *dev = node->minor->dev;
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 struct drm_i915_gem_object *obj;
06fbca71 642 struct intel_engine_cs *ring;
8d9d5744
CW		 643 int total = 0;
644 int ret, i, j;
493018dc
BV		 645
646 ret = mutex_lock_interruptible(&dev->struct_mutex);
647 if (ret)
648 return ret;
649
06fbca71 650 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 651 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
652 int count;
653
654 count = 0;
655 list_for_each_entry(obj,
656 &ring->batch_pool.cache_list[j],
657 batch_pool_link)
658 count++;
659 seq_printf(m, "%s cache[%d]: %d objects\n",
660 ring->name, j, count);
661
662 list_for_each_entry(obj,
663 &ring->batch_pool.cache_list[j],
664 batch_pool_link) {
665 seq_puts(m, " ");
666 describe_obj(m, obj);
667 seq_putc(m, '\n');
668 }
669
670 total += count;
06fbca71 671 }
493018dc
BV		 672 }
673
8d9d5744 674 seq_printf(m, "total: %d\n", total);
493018dc
BV		 675
676 mutex_unlock(&dev->struct_mutex);
677
678 return 0;
679}
680
2017263e
BG		 681static int i915_gem_request_info(struct seq_file *m, void *data)
682{
9f25d007 683 struct drm_info_node *node = m->private;
2017263e 684 struct drm_device *dev = node->minor->dev;
e277a1f8 685 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 686 struct intel_engine_cs *ring;
eed29a5b 687 struct drm_i915_gem_request *req;
2d1070b2 688 int ret, any, i;
de227ef0
CW		 689
690 ret = mutex_lock_interruptible(&dev->struct_mutex);
691 if (ret)
692 return ret;
2017263e 693
2d1070b2 694 any = 0;
a2c7f6fd 695 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 696 int count;
697
698 count = 0;
eed29a5b 699 list_for_each_entry(req, &ring->request_list, list)
2d1070b2
CW		 700 count++;
701 if (count == 0)
a2c7f6fd
CW		 702 continue;
703
2d1070b2 704 seq_printf(m, "%s requests: %d\n", ring->name, count);
eed29a5b 705 list_for_each_entry(req, &ring->request_list, list) {
2d1070b2
CW		 706 struct task_struct *task;
707
708 rcu_read_lock();
709 task = NULL;
eed29a5b
DV		 710 if (req->pid)
711 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 712 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 713 req->seqno,
714 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 715 task ? task->comm : "<unknown>",
716 task ? task->pid : -1);
717 rcu_read_unlock();
c2c347a9 718 }
2d1070b2
CW		 719
720 any++;
2017263e 721 }
de227ef0
CW		 722 mutex_unlock(&dev->struct_mutex);
723
2d1070b2 724 if (any == 0)
267f0c90 725 seq_puts(m, "No requests\n");
c2c347a9 726
2017263e
BG		 727 return 0;
728}
729
b2223497 730static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 731 struct intel_engine_cs *ring)
b2223497
CW		 732{
733 if (ring->get_seqno) {
20e28fba 734 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 735 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 736 }
737}
738
2017263e
BG		 739static int i915_gem_seqno_info(struct seq_file *m, void *data)
740{
9f25d007 741 struct drm_info_node *node = m->private;
2017263e 742 struct drm_device *dev = node->minor->dev;
e277a1f8 743 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 744 struct intel_engine_cs *ring;
1ec14ad3 745 int ret, i;
de227ef0
CW		 746
747 ret = mutex_lock_interruptible(&dev->struct_mutex);
748 if (ret)
749 return ret;
c8c8fb33 750 intel_runtime_pm_get(dev_priv);
2017263e 751
a2c7f6fd
CW		 752 for_each_ring(ring, dev_priv, i)
753 i915_ring_seqno_info(m, ring);
de227ef0 754
c8c8fb33 755 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 756 mutex_unlock(&dev->struct_mutex);
757
2017263e
BG		 758 return 0;
759}
760
761
762static int i915_interrupt_info(struct seq_file *m, void *data)
763{
9f25d007 764 struct drm_info_node *node = m->private;
2017263e 765 struct drm_device *dev = node->minor->dev;
e277a1f8 766 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 767 struct intel_engine_cs *ring;
9db4a9c7 768 int ret, i, pipe;
de227ef0
CW		 769
770 ret = mutex_lock_interruptible(&dev->struct_mutex);
771 if (ret)
772 return ret;
c8c8fb33 773 intel_runtime_pm_get(dev_priv);
2017263e 774
74e1ca8c 775 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 776 seq_printf(m, "Master Interrupt Control:\t%08x\n",
777 I915_READ(GEN8_MASTER_IRQ));
778
779 seq_printf(m, "Display IER:\t%08x\n",
780 I915_READ(VLV_IER));
781 seq_printf(m, "Display IIR:\t%08x\n",
782 I915_READ(VLV_IIR));
783 seq_printf(m, "Display IIR_RW:\t%08x\n",
784 I915_READ(VLV_IIR_RW));
785 seq_printf(m, "Display IMR:\t%08x\n",
786 I915_READ(VLV_IMR));
055e393f 787 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 788 seq_printf(m, "Pipe %c stat:\t%08x\n",
789 pipe_name(pipe),
790 I915_READ(PIPESTAT(pipe)));
791
792 seq_printf(m, "Port hotplug:\t%08x\n",
793 I915_READ(PORT_HOTPLUG_EN));
794 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
795 I915_READ(VLV_DPFLIPSTAT));
796 seq_printf(m, "DPINVGTT:\t%08x\n",
797 I915_READ(DPINVGTT));
798
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
806 }
807
808 seq_printf(m, "PCU interrupt mask:\t%08x\n",
809 I915_READ(GEN8_PCU_IMR));
810 seq_printf(m, "PCU interrupt identity:\t%08x\n",
811 I915_READ(GEN8_PCU_IIR));
812 seq_printf(m, "PCU interrupt enable:\t%08x\n",
813 I915_READ(GEN8_PCU_IER));
814 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 815 seq_printf(m, "Master Interrupt Control:\t%08x\n",
816 I915_READ(GEN8_MASTER_IRQ));
817
818 for (i = 0; i < 4; i++) {
819 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IMR(i)));
821 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IIR(i)));
823 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
824 i, I915_READ(GEN8_GT_IER(i)));
825 }
826
055e393f 827 for_each_pipe(dev_priv, pipe) {
f458ebbc 828 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 829 POWER_DOMAIN_PIPE(pipe))) {
830 seq_printf(m, "Pipe %c power disabled\n",
831 pipe_name(pipe));
832 continue;
833 }
a123f157 834 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 835 pipe_name(pipe),
836 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 837 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 838 pipe_name(pipe),
839 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 840 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 841 pipe_name(pipe),
842 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 843 }
844
845 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
846 I915_READ(GEN8_DE_PORT_IMR));
847 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IIR));
849 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IER));
851
852 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
853 I915_READ(GEN8_DE_MISC_IMR));
854 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IIR));
856 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IER));
858
859 seq_printf(m, "PCU interrupt mask:\t%08x\n",
860 I915_READ(GEN8_PCU_IMR));
861 seq_printf(m, "PCU interrupt identity:\t%08x\n",
862 I915_READ(GEN8_PCU_IIR));
863 seq_printf(m, "PCU interrupt enable:\t%08x\n",
864 I915_READ(GEN8_PCU_IER));
865 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 866 seq_printf(m, "Display IER:\t%08x\n",
867 I915_READ(VLV_IER));
868 seq_printf(m, "Display IIR:\t%08x\n",
869 I915_READ(VLV_IIR));
870 seq_printf(m, "Display IIR_RW:\t%08x\n",
871 I915_READ(VLV_IIR_RW));
872 seq_printf(m, "Display IMR:\t%08x\n",
873 I915_READ(VLV_IMR));
055e393f 874 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 875 seq_printf(m, "Pipe %c stat:\t%08x\n",
876 pipe_name(pipe),
877 I915_READ(PIPESTAT(pipe)));
878
879 seq_printf(m, "Master IER:\t%08x\n",
880 I915_READ(VLV_MASTER_IER));
881
882 seq_printf(m, "Render IER:\t%08x\n",
883 I915_READ(GTIER));
884 seq_printf(m, "Render IIR:\t%08x\n",
885 I915_READ(GTIIR));
886 seq_printf(m, "Render IMR:\t%08x\n",
887 I915_READ(GTIMR));
888
889 seq_printf(m, "PM IER:\t\t%08x\n",
890 I915_READ(GEN6_PMIER));
891 seq_printf(m, "PM IIR:\t\t%08x\n",
892 I915_READ(GEN6_PMIIR));
893 seq_printf(m, "PM IMR:\t\t%08x\n",
894 I915_READ(GEN6_PMIMR));
895
896 seq_printf(m, "Port hotplug:\t%08x\n",
897 I915_READ(PORT_HOTPLUG_EN));
898 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
899 I915_READ(VLV_DPFLIPSTAT));
900 seq_printf(m, "DPINVGTT:\t%08x\n",
901 I915_READ(DPINVGTT));
902
903 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 904 seq_printf(m, "Interrupt enable: %08x\n",
905 I915_READ(IER));
906 seq_printf(m, "Interrupt identity: %08x\n",
907 I915_READ(IIR));
908 seq_printf(m, "Interrupt mask: %08x\n",
909 I915_READ(IMR));
055e393f 910 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 911 seq_printf(m, "Pipe %c stat: %08x\n",
912 pipe_name(pipe),
913 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 914 } else {
915 seq_printf(m, "North Display Interrupt enable: %08x\n",
916 I915_READ(DEIER));
917 seq_printf(m, "North Display Interrupt identity: %08x\n",
918 I915_READ(DEIIR));
919 seq_printf(m, "North Display Interrupt mask: %08x\n",
920 I915_READ(DEIMR));
921 seq_printf(m, "South Display Interrupt enable: %08x\n",
922 I915_READ(SDEIER));
923 seq_printf(m, "South Display Interrupt identity: %08x\n",
924 I915_READ(SDEIIR));
925 seq_printf(m, "South Display Interrupt mask: %08x\n",
926 I915_READ(SDEIMR));
927 seq_printf(m, "Graphics Interrupt enable: %08x\n",
928 I915_READ(GTIER));
929 seq_printf(m, "Graphics Interrupt identity: %08x\n",
930 I915_READ(GTIIR));
931 seq_printf(m, "Graphics Interrupt mask: %08x\n",
932 I915_READ(GTIMR));
933 }
a2c7f6fd 934 for_each_ring(ring, dev_priv, i) {
a123f157 935 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 936 seq_printf(m,
937 "Graphics Interrupt mask (%s): %08x\n",
938 ring->name, I915_READ_IMR(ring));
9862e600 939 }
a2c7f6fd 940 i915_ring_seqno_info(m, ring);
9862e600 941 }
c8c8fb33 942 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 943 mutex_unlock(&dev->struct_mutex);
944
2017263e
BG		 945 return 0;
946}
947
a6172a80
CW		 948static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
949{
9f25d007 950 struct drm_info_node *node = m->private;
a6172a80 951 struct drm_device *dev = node->minor->dev;
e277a1f8 952 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 953 int i, ret;
954
955 ret = mutex_lock_interruptible(&dev->struct_mutex);
956 if (ret)
957 return ret;
a6172a80
CW		 958
959 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
960 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
961 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 962 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 963
6c085a72
CW		 964 seq_printf(m, "Fence %d, pin count = %d, object = ",
965 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 966 if (obj == NULL)
267f0c90 967 seq_puts(m, "unused");
c2c347a9 968 else
05394f39 969 describe_obj(m, obj);
267f0c90 970 seq_putc(m, '\n');
a6172a80
CW		 971 }
972
05394f39 973 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 974 return 0;
975}
976
2017263e
BG		 977static int i915_hws_info(struct seq_file *m, void *data)
978{
9f25d007 979 struct drm_info_node *node = m->private;
2017263e 980 struct drm_device *dev = node->minor->dev;
e277a1f8 981 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 982 struct intel_engine_cs *ring;
1a240d4d 983 const u32 *hws;
4066c0ae
CW		 984 int i;
985
1ec14ad3 986 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 987 hws = ring->status_page.page_addr;
2017263e
BG		 988 if (hws == NULL)
989 return 0;
990
991 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
992 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
993 i * 4,
994 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
995 }
996 return 0;
997}
998
d5442303
DV		 999static ssize_t
1000i915_error_state_write(struct file *filp,
1001 const char __user *ubuf,
1002 size_t cnt,
1003 loff_t *ppos)
1004{
edc3d884 1005 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1006 struct drm_device *dev = error_priv->dev;
22bcfc6a 1007 int ret;
d5442303
DV		 1008
1009 DRM_DEBUG_DRIVER("Resetting error state\n");
1010
22bcfc6a
DV		 1011 ret = mutex_lock_interruptible(&dev->struct_mutex);
1012 if (ret)
1013 return ret;
1014
d5442303
DV		 1015 i915_destroy_error_state(dev);
1016 mutex_unlock(&dev->struct_mutex);
1017
1018 return cnt;
1019}
1020
1021static int i915_error_state_open(struct inode *inode, struct file *file)
1022{
1023 struct drm_device *dev = inode->i_private;
d5442303 1024 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1025
1026 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1027 if (!error_priv)
1028 return -ENOMEM;
1029
1030 error_priv->dev = dev;
1031
95d5bfb3 1032 i915_error_state_get(dev, error_priv);
d5442303 1033
edc3d884
MK		 1034 file->private_data = error_priv;
1035
1036 return 0;
d5442303
DV		 1037}
1038
1039static int i915_error_state_release(struct inode *inode, struct file *file)
1040{
edc3d884 1041 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1042
95d5bfb3 1043 i915_error_state_put(error_priv);
d5442303
DV		 1044 kfree(error_priv);
1045
edc3d884
MK		 1046 return 0;
1047}
1048
4dc955f7
MK		 1049static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1050 size_t count, loff_t *pos)
1051{
1052 struct i915_error_state_file_priv *error_priv = file->private_data;
1053 struct drm_i915_error_state_buf error_str;
1054 loff_t tmp_pos = 0;
1055 ssize_t ret_count = 0;
1056 int ret;
1057
0a4cd7c8 1058 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1059 if (ret)
1060 return ret;
edc3d884 1061
fc16b48b 1062 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1063 if (ret)
1064 goto out;
1065
edc3d884
MK		 1066 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1067 error_str.buf,
1068 error_str.bytes);
1069
1070 if (ret_count < 0)
1071 ret = ret_count;
1072 else
1073 *pos = error_str.start + ret_count;
1074out:
4dc955f7 1075 i915_error_state_buf_release(&error_str);
edc3d884 1076 return ret ?: ret_count;
d5442303
DV		 1077}
1078
1079static const struct file_operations i915_error_state_fops = {
1080 .owner = THIS_MODULE,
1081 .open = i915_error_state_open,
edc3d884 1082 .read = i915_error_state_read,
d5442303
DV		 1083 .write = i915_error_state_write,
1084 .llseek = default_llseek,
1085 .release = i915_error_state_release,
1086};
1087
647416f9
KC		 1088static int
1089i915_next_seqno_get(void *data, u64 *val)
40633219 1090{
647416f9 1091 struct drm_device *dev = data;
e277a1f8 1092 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1093 int ret;
1094
1095 ret = mutex_lock_interruptible(&dev->struct_mutex);
1096 if (ret)
1097 return ret;
1098
647416f9 1099 *val = dev_priv->next_seqno;
40633219
MK		 1100 mutex_unlock(&dev->struct_mutex);
1101
647416f9 1102 return 0;
40633219
MK		 1103}
1104
647416f9
KC		 1105static int
1106i915_next_seqno_set(void *data, u64 val)
1107{
1108 struct drm_device *dev = data;
40633219
MK		 1109 int ret;
1110
40633219
MK		 1111 ret = mutex_lock_interruptible(&dev->struct_mutex);
1112 if (ret)
1113 return ret;
1114
e94fbaa8 1115 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1116 mutex_unlock(&dev->struct_mutex);
1117
647416f9 1118 return ret;
40633219
MK		 1119}
1120
647416f9
KC		 1121DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1122 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1123 "0x%llx\n");
40633219 1124
adb4bd12 1125static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1126{
9f25d007 1127 struct drm_info_node *node = m->private;
f97108d1 1128 struct drm_device *dev = node->minor->dev;
e277a1f8 1129 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1130 int ret = 0;
1131
1132 intel_runtime_pm_get(dev_priv);
3b8d8d91 1133
5c9669ce
TR		 1134 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1135
3b8d8d91
JB		 1136 if (IS_GEN5(dev)) {
1137 u16 rgvswctl = I915_READ16(MEMSWCTL);
1138 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1139
1140 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1141 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1142 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1143 MEMSTAT_VID_SHIFT);
1144 seq_printf(m, "Current P-state: %d\n",
1145 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2 1146 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
60260a5b 1147 IS_BROADWELL(dev) || IS_GEN9(dev)) {
35040562
BP		 1148 u32 rp_state_limits;
1149 u32 gt_perf_status;
1150 u32 rp_state_cap;
0d8f9491 1151 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1152 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1153 u32 rpupei, rpcurup, rpprevup;
1154 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1155 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1156 int max_freq;
1157
35040562
BP		 1158 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1159 if (IS_BROXTON(dev)) {
1160 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1161 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1162 } else {
1163 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1164 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1165 }
1166
3b8d8d91 1167 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1168 ret = mutex_lock_interruptible(&dev->struct_mutex);
1169 if (ret)
c8c8fb33 1170 goto out;
d1ebd816 1171
59bad947 1172 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1173
8e8c06cd 1174 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1175 if (IS_GEN9(dev))
1176 reqf >>= 23;
1177 else {
1178 reqf &= ~GEN6_TURBO_DISABLE;
1179 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1180 reqf >>= 24;
1181 else
1182 reqf >>= 25;
1183 }
7c59a9c1 1184 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1185
0d8f9491
CW		 1186 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1187 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1188 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1189
ccab5c82
JB		 1190 rpstat = I915_READ(GEN6_RPSTAT1);
1191 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1192 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1193 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1194 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1195 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1196 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1197 if (IS_GEN9(dev))
1198 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1199 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1200 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1201 else
1202 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1203 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1204
59bad947 1205 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1206 mutex_unlock(&dev->struct_mutex);
1207
9dd3c605
PZ		 1208 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1209 pm_ier = I915_READ(GEN6_PMIER);
1210 pm_imr = I915_READ(GEN6_PMIMR);
1211 pm_isr = I915_READ(GEN6_PMISR);
1212 pm_iir = I915_READ(GEN6_PMIIR);
1213 pm_mask = I915_READ(GEN6_PMINTRMSK);
1214 } else {
1215 pm_ier = I915_READ(GEN8_GT_IER(2));
1216 pm_imr = I915_READ(GEN8_GT_IMR(2));
1217 pm_isr = I915_READ(GEN8_GT_ISR(2));
1218 pm_iir = I915_READ(GEN8_GT_IIR(2));
1219 pm_mask = I915_READ(GEN6_PMINTRMSK);
1220 }
0d8f9491 1221 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1222 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1223 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1224 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1225 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1226 seq_printf(m, "Render p-state VID: %d\n",
1227 gt_perf_status & 0xff);
1228 seq_printf(m, "Render p-state limit: %d\n",
1229 rp_state_limits & 0xff);
0d8f9491
CW		 1230 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1231 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1232 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1233 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1234 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1235 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1236 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1237 GEN6_CURICONT_MASK);
1238 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1239 GEN6_CURBSYTAVG_MASK);
1240 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1241 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1242 seq_printf(m, "Up threshold: %d%%\n",
1243 dev_priv->rps.up_threshold);
1244
ccab5c82
JB		 1245 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1246 GEN6_CURIAVG_MASK);
1247 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1248 GEN6_CURBSYTAVG_MASK);
1249 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1250 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1251 seq_printf(m, "Down threshold: %d%%\n",
1252 dev_priv->rps.down_threshold);
3b8d8d91 1253
35040562
BP		 1254 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1255 rp_state_cap >> 16) & 0xff;
60260a5b 1256 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1257 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1258 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1259
1260 max_freq = (rp_state_cap & 0xff00) >> 8;
60260a5b 1261 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1262 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1263 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1264
35040562
BP		 1265 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1266 rp_state_cap >> 0) & 0xff;
60260a5b 1267 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1268 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1269 intel_gpu_freq(dev_priv, max_freq));
31c77388 1270 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1271 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1272
d86ed34a
CW		 1273 seq_printf(m, "Current freq: %d MHz\n",
1274 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1275 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1276 seq_printf(m, "Idle freq: %d MHz\n",
1277 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1278 seq_printf(m, "Min freq: %d MHz\n",
1279 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1280 seq_printf(m, "Max freq: %d MHz\n",
1281 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1282 seq_printf(m,
1283 "efficient (RPe) frequency: %d MHz\n",
1284 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84 1285 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1286 u32 freq_sts;
0a073b84 1287
259bd5d4 1288 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1289 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1290 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1291 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1292
d86ed34a
CW		 1293 seq_printf(m, "actual GPU freq: %d MHz\n",
1294 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1295
1296 seq_printf(m, "current GPU freq: %d MHz\n",
1297 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1298
0a073b84 1299 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1300 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1301
0a073b84 1302 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1303 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1304
aed242ff
CW		 1305 seq_printf(m, "idle GPU freq: %d MHz\n",
1306 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1307
7c59a9c1
VS		 1308 seq_printf(m,
1309 "efficient (RPe) frequency: %d MHz\n",
1310 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
259bd5d4 1311 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1312 } else {
267f0c90 1313 seq_puts(m, "no P-state info available\n");
3b8d8d91 1314 }
f97108d1 1315
1170f28c
MK		 1316 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1317 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1318 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1319
c8c8fb33
PZ		 1320out:
1321 intel_runtime_pm_put(dev_priv);
1322 return ret;
f97108d1
JB		 1323}
1324
f654449a
CW		 1325static int i915_hangcheck_info(struct seq_file *m, void *unused)
1326{
1327 struct drm_info_node *node = m->private;
ebbc7546
MK		 1328 struct drm_device *dev = node->minor->dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1330 struct intel_engine_cs *ring;
ebbc7546
MK		 1331 u64 acthd[I915_NUM_RINGS];
1332 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1333 int i;
1334
1335 if (!i915.enable_hangcheck) {
1336 seq_printf(m, "Hangcheck disabled\n");
1337 return 0;
1338 }
1339
ebbc7546
MK		 1340 intel_runtime_pm_get(dev_priv);
1341
1342 for_each_ring(ring, dev_priv, i) {
1343 seqno[i] = ring->get_seqno(ring, false);
1344 acthd[i] = intel_ring_get_active_head(ring);
1345 }
1346
1347 intel_runtime_pm_put(dev_priv);
1348
f654449a
CW		 1349 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1350 seq_printf(m, "Hangcheck active, fires in %dms\n",
1351 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1352 jiffies));
1353 } else
1354 seq_printf(m, "Hangcheck inactive\n");
1355
1356 for_each_ring(ring, dev_priv, i) {
1357 seq_printf(m, "%s:\n", ring->name);
1358 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1359 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1360 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1361 (long long)ring->hangcheck.acthd,
ebbc7546 1362 (long long)acthd[i]);
f654449a
CW		 1363 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1364 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1365 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1366 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1367 }
1368
1369 return 0;
1370}
1371
4d85529d 1372static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1373{
9f25d007 1374 struct drm_info_node *node = m->private;
f97108d1 1375 struct drm_device *dev = node->minor->dev;
e277a1f8 1376 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1377 u32 rgvmodectl, rstdbyctl;
1378 u16 crstandvid;
1379 int ret;
1380
1381 ret = mutex_lock_interruptible(&dev->struct_mutex);
1382 if (ret)
1383 return ret;
c8c8fb33 1384 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1385
1386 rgvmodectl = I915_READ(MEMMODECTL);
1387 rstdbyctl = I915_READ(RSTDBYCTL);
1388 crstandvid = I915_READ16(CRSTANDVID);
1389
c8c8fb33 1390 intel_runtime_pm_put(dev_priv);
616fdb5a 1391 mutex_unlock(&dev->struct_mutex);
f97108d1 1392
742f491d 1393 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1394 seq_printf(m, "Boost freq: %d\n",
1395 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1396 MEMMODE_BOOST_FREQ_SHIFT);
1397 seq_printf(m, "HW control enabled: %s\n",
742f491d 1398 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1399 seq_printf(m, "SW control enabled: %s\n",
742f491d 1400 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1401 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1402 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1403 seq_printf(m, "Starting frequency: P%d\n",
1404 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1405 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1406 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1407 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1408 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1409 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1410 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1411 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1412 seq_puts(m, "Current RS state: ");
88271da3
JB		 1413 switch (rstdbyctl & RSX_STATUS_MASK) {
1414 case RSX_STATUS_ON:
267f0c90 1415 seq_puts(m, "on\n");
88271da3
JB		 1416 break;
1417 case RSX_STATUS_RC1:
267f0c90 1418 seq_puts(m, "RC1\n");
88271da3
JB		 1419 break;
1420 case RSX_STATUS_RC1E:
267f0c90 1421 seq_puts(m, "RC1E\n");
88271da3
JB		 1422 break;
1423 case RSX_STATUS_RS1:
267f0c90 1424 seq_puts(m, "RS1\n");
88271da3
JB		 1425 break;
1426 case RSX_STATUS_RS2:
267f0c90 1427 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1428 break;
1429 case RSX_STATUS_RS3:
267f0c90 1430 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1431 break;
1432 default:
267f0c90 1433 seq_puts(m, "unknown\n");
88271da3
JB		 1434 break;
1435 }
f97108d1
JB		 1436
1437 return 0;
1438}
1439
f65367b5 1440static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1441{
b2cff0db
CW		 1442 struct drm_info_node *node = m->private;
1443 struct drm_device *dev = node->minor->dev;
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1446 int i;
1447
1448 spin_lock_irq(&dev_priv->uncore.lock);
1449 for_each_fw_domain(fw_domain, dev_priv, i) {
1450 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1451 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1452 fw_domain->wake_count);
1453 }
1454 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1455
b2cff0db
CW		 1456 return 0;
1457}
1458
1459static int vlv_drpc_info(struct seq_file *m)
1460{
9f25d007 1461 struct drm_info_node *node = m->private;
669ab5aa
D		 1462 struct drm_device *dev = node->minor->dev;
1463 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1464 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1465
d46c0517
ID		 1466 intel_runtime_pm_get(dev_priv);
1467
6b312cd3 1468 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1469 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1470 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1471
d46c0517
ID		 1472 intel_runtime_pm_put(dev_priv);
1473
669ab5aa
D		 1474 seq_printf(m, "Video Turbo Mode: %s\n",
1475 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1476 seq_printf(m, "Turbo enabled: %s\n",
1477 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1478 seq_printf(m, "HW control enabled: %s\n",
1479 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1480 seq_printf(m, "SW control enabled: %s\n",
1481 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1482 GEN6_RP_MEDIA_SW_MODE));
1483 seq_printf(m, "RC6 Enabled: %s\n",
1484 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1485 GEN6_RC_CTL_EI_MODE(1))));
1486 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1487 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1488 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1489 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1490
9cc19be5
ID		 1491 seq_printf(m, "Render RC6 residency since boot: %u\n",
1492 I915_READ(VLV_GT_RENDER_RC6));
1493 seq_printf(m, "Media RC6 residency since boot: %u\n",
1494 I915_READ(VLV_GT_MEDIA_RC6));
1495
f65367b5 1496 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1497}
1498
4d85529d
BW		 1499static int gen6_drpc_info(struct seq_file *m)
1500{
9f25d007 1501 struct drm_info_node *node = m->private;
4d85529d
BW		 1502 struct drm_device *dev = node->minor->dev;
1503 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1504 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1505 unsigned forcewake_count;
aee56cff 1506 int count = 0, ret;
4d85529d
BW		 1507
1508 ret = mutex_lock_interruptible(&dev->struct_mutex);
1509 if (ret)
1510 return ret;
c8c8fb33 1511 intel_runtime_pm_get(dev_priv);
4d85529d 1512
907b28c5 1513 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1514 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1515 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1516
1517 if (forcewake_count) {
267f0c90
DL		 1518 seq_puts(m, "RC information inaccurate because somebody "
1519 "holds a forcewake reference \n");
4d85529d
BW		 1520 } else {
1521 /* NB: we cannot use forcewake, else we read the wrong values */
1522 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1523 udelay(10);
1524 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1525 }
1526
75aa3f63 1527 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
ed71f1b4 1528 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1529
1530 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1531 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1532 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1533 mutex_lock(&dev_priv->rps.hw_lock);
1534 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1535 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1536
c8c8fb33
PZ		 1537 intel_runtime_pm_put(dev_priv);
1538
4d85529d
BW		 1539 seq_printf(m, "Video Turbo Mode: %s\n",
1540 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1541 seq_printf(m, "HW control enabled: %s\n",
1542 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1543 seq_printf(m, "SW control enabled: %s\n",
1544 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1545 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1546 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1547 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1548 seq_printf(m, "RC6 Enabled: %s\n",
1549 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1550 seq_printf(m, "Deep RC6 Enabled: %s\n",
1551 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1552 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1553 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1554 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1555 switch (gt_core_status & GEN6_RCn_MASK) {
1556 case GEN6_RC0:
1557 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1558 seq_puts(m, "Core Power Down\n");
4d85529d 1559 else
267f0c90 1560 seq_puts(m, "on\n");
4d85529d
BW		 1561 break;
1562 case GEN6_RC3:
267f0c90 1563 seq_puts(m, "RC3\n");
4d85529d
BW		 1564 break;
1565 case GEN6_RC6:
267f0c90 1566 seq_puts(m, "RC6\n");
4d85529d
BW		 1567 break;
1568 case GEN6_RC7:
267f0c90 1569 seq_puts(m, "RC7\n");
4d85529d
BW		 1570 break;
1571 default:
267f0c90 1572 seq_puts(m, "Unknown\n");
4d85529d
BW		 1573 break;
1574 }
1575
1576 seq_printf(m, "Core Power Down: %s\n",
1577 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1578
1579 /* Not exactly sure what this is */
1580 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1581 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1582 seq_printf(m, "RC6 residency since boot: %u\n",
1583 I915_READ(GEN6_GT_GFX_RC6));
1584 seq_printf(m, "RC6+ residency since boot: %u\n",
1585 I915_READ(GEN6_GT_GFX_RC6p));
1586 seq_printf(m, "RC6++ residency since boot: %u\n",
1587 I915_READ(GEN6_GT_GFX_RC6pp));
1588
ecd8faea
BW		 1589 seq_printf(m, "RC6 voltage: %dmV\n",
1590 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1591 seq_printf(m, "RC6+ voltage: %dmV\n",
1592 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1593 seq_printf(m, "RC6++ voltage: %dmV\n",
1594 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1595 return 0;
1596}
1597
1598static int i915_drpc_info(struct seq_file *m, void *unused)
1599{
9f25d007 1600 struct drm_info_node *node = m->private;
4d85529d
BW		 1601 struct drm_device *dev = node->minor->dev;
1602
669ab5aa
D		 1603 if (IS_VALLEYVIEW(dev))
1604 return vlv_drpc_info(m);
ac66cf4b 1605 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1606 return gen6_drpc_info(m);
1607 else
1608 return ironlake_drpc_info(m);
1609}
1610
9a851789
DV		 1611static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1612{
1613 struct drm_info_node *node = m->private;
1614 struct drm_device *dev = node->minor->dev;
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616
1617 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1618 dev_priv->fb_tracking.busy_bits);
1619
1620 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1621 dev_priv->fb_tracking.flip_bits);
1622
1623 return 0;
1624}
1625
b5e50c3f
JB		 1626static int i915_fbc_status(struct seq_file *m, void *unused)
1627{
9f25d007 1628 struct drm_info_node *node = m->private;
b5e50c3f 1629 struct drm_device *dev = node->minor->dev;
e277a1f8 1630 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1631
3a77c4c4 1632 if (!HAS_FBC(dev)) {
267f0c90 1633 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1634 return 0;
1635 }
1636
36623ef8 1637 intel_runtime_pm_get(dev_priv);
25ad93fd 1638 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1639
7733b49b 1640 if (intel_fbc_enabled(dev_priv))
267f0c90 1641 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1642 else
1643 seq_printf(m, "FBC disabled: %s\n",
1644 intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
36623ef8 1645
31b9df10
PZ		 1646 if (INTEL_INFO(dev_priv)->gen >= 7)
1647 seq_printf(m, "Compressing: %s\n",
1648 yesno(I915_READ(FBC_STATUS2) &
1649 FBC_COMPRESSION_MASK));
1650
25ad93fd 1651 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1652 intel_runtime_pm_put(dev_priv);
1653
b5e50c3f
JB		 1654 return 0;
1655}
1656
da46f936
RV		 1657static int i915_fbc_fc_get(void *data, u64 *val)
1658{
1659 struct drm_device *dev = data;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661
1662 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1663 return -ENODEV;
1664
da46f936 1665 *val = dev_priv->fbc.false_color;
da46f936
RV		 1666
1667 return 0;
1668}
1669
1670static int i915_fbc_fc_set(void *data, u64 val)
1671{
1672 struct drm_device *dev = data;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 u32 reg;
1675
1676 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1677 return -ENODEV;
1678
25ad93fd 1679 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1680
1681 reg = I915_READ(ILK_DPFC_CONTROL);
1682 dev_priv->fbc.false_color = val;
1683
1684 I915_WRITE(ILK_DPFC_CONTROL, val ?
1685 (reg | FBC_CTL_FALSE_COLOR) :
1686 (reg & ~FBC_CTL_FALSE_COLOR));
1687
25ad93fd 1688 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1689 return 0;
1690}
1691
1692DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1693 i915_fbc_fc_get, i915_fbc_fc_set,
1694 "%llu\n");
1695
92d44621
PZ		 1696static int i915_ips_status(struct seq_file *m, void *unused)
1697{
9f25d007 1698 struct drm_info_node *node = m->private;
92d44621
PZ		 1699 struct drm_device *dev = node->minor->dev;
1700 struct drm_i915_private *dev_priv = dev->dev_private;
1701
f5adf94e 1702 if (!HAS_IPS(dev)) {
92d44621
PZ		 1703 seq_puts(m, "not supported\n");
1704 return 0;
1705 }
1706
36623ef8
PZ		 1707 intel_runtime_pm_get(dev_priv);
1708
0eaa53f0
RV		 1709 seq_printf(m, "Enabled by kernel parameter: %s\n",
1710 yesno(i915.enable_ips));
1711
1712 if (INTEL_INFO(dev)->gen >= 8) {
1713 seq_puts(m, "Currently: unknown\n");
1714 } else {
1715 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1716 seq_puts(m, "Currently: enabled\n");
1717 else
1718 seq_puts(m, "Currently: disabled\n");
1719 }
92d44621 1720
36623ef8
PZ		 1721 intel_runtime_pm_put(dev_priv);
1722
92d44621
PZ		 1723 return 0;
1724}
1725
4a9bef37
JB		 1726static int i915_sr_status(struct seq_file *m, void *unused)
1727{
9f25d007 1728 struct drm_info_node *node = m->private;
4a9bef37 1729 struct drm_device *dev = node->minor->dev;
e277a1f8 1730 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1731 bool sr_enabled = false;
1732
36623ef8
PZ		 1733 intel_runtime_pm_get(dev_priv);
1734
1398261a 1735 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1736 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1737 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1738 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1739 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1740 else if (IS_I915GM(dev))
1741 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1742 else if (IS_PINEVIEW(dev))
1743 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
77b64555
ACO		 1744 else if (IS_VALLEYVIEW(dev))
1745 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1746
36623ef8
PZ		 1747 intel_runtime_pm_put(dev_priv);
1748
5ba2aaaa
CW		 1749 seq_printf(m, "self-refresh: %s\n",
1750 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1751
1752 return 0;
1753}
1754
7648fa99
JB		 1755static int i915_emon_status(struct seq_file *m, void *unused)
1756{
9f25d007 1757 struct drm_info_node *node = m->private;
7648fa99 1758 struct drm_device *dev = node->minor->dev;
e277a1f8 1759 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1760 unsigned long temp, chipset, gfx;
de227ef0
CW		 1761 int ret;
1762
582be6b4
CW		 1763 if (!IS_GEN5(dev))
1764 return -ENODEV;
1765
de227ef0
CW		 1766 ret = mutex_lock_interruptible(&dev->struct_mutex);
1767 if (ret)
1768 return ret;
7648fa99
JB		 1769
1770 temp = i915_mch_val(dev_priv);
1771 chipset = i915_chipset_val(dev_priv);
1772 gfx = i915_gfx_val(dev_priv);
de227ef0 1773 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1774
1775 seq_printf(m, "GMCH temp: %ld\n", temp);
1776 seq_printf(m, "Chipset power: %ld\n", chipset);
1777 seq_printf(m, "GFX power: %ld\n", gfx);
1778 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1779
1780 return 0;
1781}
1782
23b2f8bb
JB		 1783static int i915_ring_freq_table(struct seq_file *m, void *unused)
1784{
9f25d007 1785 struct drm_info_node *node = m->private;
23b2f8bb 1786 struct drm_device *dev = node->minor->dev;
e277a1f8 1787 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1788 int ret = 0;
23b2f8bb 1789 int gpu_freq, ia_freq;
f936ec34 1790 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1791
97d3308a 1792 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1793 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1794 return 0;
1795 }
1796
5bfa0199
PZ		 1797 intel_runtime_pm_get(dev_priv);
1798
5c9669ce
TR		 1799 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1800
4fc688ce 1801 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1802 if (ret)
5bfa0199 1803 goto out;
23b2f8bb 1804
f936ec34
AG		 1805 if (IS_SKYLAKE(dev)) {
1806 /* Convert GT frequency to 50 HZ units */
1807 min_gpu_freq =
1808 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1809 max_gpu_freq =
1810 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1811 } else {
1812 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1813 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1814 }
1815
267f0c90 1816 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1817
f936ec34 1818 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1819 ia_freq = gpu_freq;
1820 sandybridge_pcode_read(dev_priv,
1821 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1822 &ia_freq);
3ebecd07 1823 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34
AG		 1824 intel_gpu_freq(dev_priv, (gpu_freq *
1825 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1826 ((ia_freq >> 0) & 0xff) * 100,
1827 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1828 }
1829
4fc688ce 1830 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1831
5bfa0199
PZ		 1832out:
1833 intel_runtime_pm_put(dev_priv);
1834 return ret;
23b2f8bb
JB		 1835}
1836
44834a67
CW		 1837static int i915_opregion(struct seq_file *m, void *unused)
1838{
9f25d007 1839 struct drm_info_node *node = m->private;
44834a67 1840 struct drm_device *dev = node->minor->dev;
e277a1f8 1841 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1842 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1843 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1844 int ret;
1845
0d38f009
DV		 1846 if (data == NULL)
1847 return -ENOMEM;
1848
44834a67
CW		 1849 ret = mutex_lock_interruptible(&dev->struct_mutex);
1850 if (ret)
0d38f009 1851 goto out;
44834a67 1852
0d38f009 1853 if (opregion->header) {
115719fc 1854 memcpy(data, opregion->header, OPREGION_SIZE);
0d38f009
DV		 1855 seq_write(m, data, OPREGION_SIZE);
1856 }
44834a67
CW		 1857
1858 mutex_unlock(&dev->struct_mutex);
1859
0d38f009
DV		 1860out:
1861 kfree(data);
44834a67
CW		 1862 return 0;
1863}
1864
37811fcc
CW		 1865static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1866{
9f25d007 1867 struct drm_info_node *node = m->private;
37811fcc 1868 struct drm_device *dev = node->minor->dev;
4520f53a 1869 struct intel_fbdev *ifbdev = NULL;
37811fcc 1870 struct intel_framebuffer *fb;
3a58ee10 1871 struct drm_framebuffer *drm_fb;
37811fcc 1872
0695726e 1873#ifdef CONFIG_DRM_FBDEV_EMULATION
4520f53a 1874 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1875
1876 ifbdev = dev_priv->fbdev;
1877 fb = to_intel_framebuffer(ifbdev->helper.fb);
1878
c1ca506d 1879 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1880 fb->base.width,
1881 fb->base.height,
1882 fb->base.depth,
623f9783 1883 fb->base.bits_per_pixel,
c1ca506d 1884 fb->base.modifier[0],
623f9783 1885 atomic_read(&fb->base.refcount.refcount));
05394f39 1886 describe_obj(m, fb->obj);
267f0c90 1887 seq_putc(m, '\n');
4520f53a 1888#endif
37811fcc 1889
4b096ac1 1890 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10
DV		 1891 drm_for_each_fb(drm_fb, dev) {
1892 fb = to_intel_framebuffer(drm_fb);
131a56dc 1893 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1894 continue;
1895
c1ca506d 1896 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1897 fb->base.width,
1898 fb->base.height,
1899 fb->base.depth,
623f9783 1900 fb->base.bits_per_pixel,
c1ca506d 1901 fb->base.modifier[0],
623f9783 1902 atomic_read(&fb->base.refcount.refcount));
05394f39 1903 describe_obj(m, fb->obj);
267f0c90 1904 seq_putc(m, '\n');
37811fcc 1905 }
4b096ac1 1906 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1907
1908 return 0;
1909}
1910
c9fe99bd
OM		 1911static void describe_ctx_ringbuf(struct seq_file *m,
1912 struct intel_ringbuffer *ringbuf)
1913{
1914 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1915 ringbuf->space, ringbuf->head, ringbuf->tail,
1916 ringbuf->last_retired_head);
1917}
1918
e76d3630
BW		 1919static int i915_context_status(struct seq_file *m, void *unused)
1920{
9f25d007 1921 struct drm_info_node *node = m->private;
e76d3630 1922 struct drm_device *dev = node->minor->dev;
e277a1f8 1923 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1924 struct intel_engine_cs *ring;
273497e5 1925 struct intel_context *ctx;
a168c293 1926 int ret, i;
e76d3630 1927
f3d28878 1928 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1929 if (ret)
1930 return ret;
1931
a33afea5 1932 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1933 if (!i915.enable_execlists &&
1934 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1935 continue;
1936
a33afea5 1937 seq_puts(m, "HW context ");
3ccfd19d 1938 describe_ctx(m, ctx);
c9fe99bd 1939 for_each_ring(ring, dev_priv, i) {
a33afea5 1940 if (ring->default_context == ctx)
c9fe99bd
OM		 1941 seq_printf(m, "(default context %s) ",
1942 ring->name);
1943 }
1944
1945 if (i915.enable_execlists) {
1946 seq_putc(m, '\n');
1947 for_each_ring(ring, dev_priv, i) {
1948 struct drm_i915_gem_object *ctx_obj =
1949 ctx->engine[i].state;
1950 struct intel_ringbuffer *ringbuf =
1951 ctx->engine[i].ringbuf;
1952
1953 seq_printf(m, "%s: ", ring->name);
1954 if (ctx_obj)
1955 describe_obj(m, ctx_obj);
1956 if (ringbuf)
1957 describe_ctx_ringbuf(m, ringbuf);
1958 seq_putc(m, '\n');
1959 }
1960 } else {
1961 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1962 }
a33afea5 1963
a33afea5 1964 seq_putc(m, '\n');
a168c293
BW		 1965 }
1966
f3d28878 1967 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1968
1969 return 0;
1970}
1971
064ca1d2
TD		 1972static void i915_dump_lrc_obj(struct seq_file *m,
1973 struct intel_engine_cs *ring,
1974 struct drm_i915_gem_object *ctx_obj)
1975{
1976 struct page *page;
1977 uint32_t *reg_state;
1978 int j;
1979 unsigned long ggtt_offset = 0;
1980
1981 if (ctx_obj == NULL) {
1982 seq_printf(m, "Context on %s with no gem object\n",
1983 ring->name);
1984 return;
1985 }
1986
1987 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1988 intel_execlists_ctx_id(ctx_obj));
1989
1990 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1991 seq_puts(m, "\tNot bound in GGTT\n");
1992 else
1993 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1994
1995 if (i915_gem_object_get_pages(ctx_obj)) {
1996 seq_puts(m, "\tFailed to get pages for context object\n");
1997 return;
1998 }
1999
d1675198 2000 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
064ca1d2
TD		 2001 if (!WARN_ON(page == NULL)) {
2002 reg_state = kmap_atomic(page);
2003
2004 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2005 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2006 ggtt_offset + 4096 + (j * 4),
2007 reg_state[j], reg_state[j + 1],
2008 reg_state[j + 2], reg_state[j + 3]);
2009 }
2010 kunmap_atomic(reg_state);
2011 }
2012
2013 seq_putc(m, '\n');
2014}
2015
c0ab1ae9
BW		 2016static int i915_dump_lrc(struct seq_file *m, void *unused)
2017{
2018 struct drm_info_node *node = (struct drm_info_node *) m->private;
2019 struct drm_device *dev = node->minor->dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 struct intel_engine_cs *ring;
2022 struct intel_context *ctx;
2023 int ret, i;
2024
2025 if (!i915.enable_execlists) {
2026 seq_printf(m, "Logical Ring Contexts are disabled\n");
2027 return 0;
2028 }
2029
2030 ret = mutex_lock_interruptible(&dev->struct_mutex);
2031 if (ret)
2032 return ret;
2033
2034 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2035 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 2036 if (ring->default_context != ctx)
2037 i915_dump_lrc_obj(m, ring,
2038 ctx->engine[i].state);
c0ab1ae9
BW		 2039 }
2040 }
2041
2042 mutex_unlock(&dev->struct_mutex);
2043
2044 return 0;
2045}
2046
4ba70e44
OM		 2047static int i915_execlists(struct seq_file *m, void *data)
2048{
2049 struct drm_info_node *node = (struct drm_info_node *)m->private;
2050 struct drm_device *dev = node->minor->dev;
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 struct intel_engine_cs *ring;
2053 u32 status_pointer;
2054 u8 read_pointer;
2055 u8 write_pointer;
2056 u32 status;
2057 u32 ctx_id;
2058 struct list_head *cursor;
2059 int ring_id, i;
2060 int ret;
2061
2062 if (!i915.enable_execlists) {
2063 seq_puts(m, "Logical Ring Contexts are disabled\n");
2064 return 0;
2065 }
2066
2067 ret = mutex_lock_interruptible(&dev->struct_mutex);
2068 if (ret)
2069 return ret;
2070
fc0412ec
MT		 2071 intel_runtime_pm_get(dev_priv);
2072
4ba70e44 2073 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2074 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2075 int count = 0;
2076 unsigned long flags;
2077
2078 seq_printf(m, "%s\n", ring->name);
2079
83843d84
VS		 2080 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2081 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
4ba70e44
OM		 2082 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2083 status, ctx_id);
2084
2085 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2086 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2087
2088 read_pointer = ring->next_context_status_buffer;
2089 write_pointer = status_pointer & 0x07;
2090 if (read_pointer > write_pointer)
2091 write_pointer += 6;
2092 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2093 read_pointer, write_pointer);
2094
2095 for (i = 0; i < 6; i++) {
83843d84
VS		 2096 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2097 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
4ba70e44
OM		 2098
2099 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2100 i, status, ctx_id);
2101 }
2102
2103 spin_lock_irqsave(&ring->execlist_lock, flags);
2104 list_for_each(cursor, &ring->execlist_queue)
2105 count++;
2106 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2107 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2108 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2109
2110 seq_printf(m, "\t%d requests in queue\n", count);
2111 if (head_req) {
2112 struct drm_i915_gem_object *ctx_obj;
2113
6d3d8274 2114 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2115 seq_printf(m, "\tHead request id: %u\n",
2116 intel_execlists_ctx_id(ctx_obj));
2117 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2118 head_req->tail);
4ba70e44
OM		 2119 }
2120
2121 seq_putc(m, '\n');
2122 }
2123
fc0412ec 2124 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2125 mutex_unlock(&dev->struct_mutex);
2126
2127 return 0;
2128}
2129
ea16a3cd
DV		 2130static const char *swizzle_string(unsigned swizzle)
2131{
aee56cff 2132 switch (swizzle) {
ea16a3cd
DV		 2133 case I915_BIT_6_SWIZZLE_NONE:
2134 return "none";
2135 case I915_BIT_6_SWIZZLE_9:
2136 return "bit9";
2137 case I915_BIT_6_SWIZZLE_9_10:
2138 return "bit9/bit10";
2139 case I915_BIT_6_SWIZZLE_9_11:
2140 return "bit9/bit11";
2141 case I915_BIT_6_SWIZZLE_9_10_11:
2142 return "bit9/bit10/bit11";
2143 case I915_BIT_6_SWIZZLE_9_17:
2144 return "bit9/bit17";
2145 case I915_BIT_6_SWIZZLE_9_10_17:
2146 return "bit9/bit10/bit17";
2147 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2148 return "unknown";
ea16a3cd
DV		 2149 }
2150
2151 return "bug";
2152}
2153
2154static int i915_swizzle_info(struct seq_file *m, void *data)
2155{
9f25d007 2156 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2157 struct drm_device *dev = node->minor->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2159 int ret;
2160
2161 ret = mutex_lock_interruptible(&dev->struct_mutex);
2162 if (ret)
2163 return ret;
c8c8fb33 2164 intel_runtime_pm_get(dev_priv);
ea16a3cd 2165
ea16a3cd
DV		 2166 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2167 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2168 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2169 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2170
2171 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2172 seq_printf(m, "DDC = 0x%08x\n",
2173 I915_READ(DCC));
656bfa3a
DV		 2174 seq_printf(m, "DDC2 = 0x%08x\n",
2175 I915_READ(DCC2));
ea16a3cd
DV		 2176 seq_printf(m, "C0DRB3 = 0x%04x\n",
2177 I915_READ16(C0DRB3));
2178 seq_printf(m, "C1DRB3 = 0x%04x\n",
2179 I915_READ16(C1DRB3));
9d3203e1 2180 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2181 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2182 I915_READ(MAD_DIMM_C0));
2183 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2184 I915_READ(MAD_DIMM_C1));
2185 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2186 I915_READ(MAD_DIMM_C2));
2187 seq_printf(m, "TILECTL = 0x%08x\n",
2188 I915_READ(TILECTL));
5907f5fb 2189 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2190 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2191 I915_READ(GAMTARBMODE));
2192 else
2193 seq_printf(m, "ARB_MODE = 0x%08x\n",
2194 I915_READ(ARB_MODE));
3fa7d235
DV		 2195 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2196 I915_READ(DISP_ARB_CTL));
ea16a3cd 2197 }
656bfa3a
DV		 2198
2199 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2200 seq_puts(m, "L-shaped memory detected\n");
2201
c8c8fb33 2202 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2203 mutex_unlock(&dev->struct_mutex);
2204
2205 return 0;
2206}
2207
1c60fef5
BW		 2208static int per_file_ctx(int id, void *ptr, void *data)
2209{
273497e5 2210 struct intel_context *ctx = ptr;
1c60fef5 2211 struct seq_file *m = data;
ae6c4806
DV		 2212 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2213
2214 if (!ppgtt) {
2215 seq_printf(m, " no ppgtt for context %d\n",
2216 ctx->user_handle);
2217 return 0;
2218 }
1c60fef5 2219
f83d6518
OM		 2220 if (i915_gem_context_is_default(ctx))
2221 seq_puts(m, " default context:\n");
2222 else
821d66dd 2223 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2224 ppgtt->debug_dump(ppgtt, m);
2225
2226 return 0;
2227}
2228
77df6772 2229static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2230{
3cf17fc5 2231 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2232 struct intel_engine_cs *ring;
77df6772
BW		 2233 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2234 int unused, i;
3cf17fc5 2235
77df6772
BW		 2236 if (!ppgtt)
2237 return;
2238
77df6772
BW		 2239 for_each_ring(ring, dev_priv, unused) {
2240 seq_printf(m, "%s\n", ring->name);
2241 for (i = 0; i < 4; i++) {
d3a93cbe 2242 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
77df6772 2243 pdp <<= 32;
d3a93cbe 2244 pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
a2a5b15c 2245 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2246 }
2247 }
2248}
2249
2250static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2251{
2252 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2253 struct intel_engine_cs *ring;
77df6772 2254 int i;
3cf17fc5 2255
3cf17fc5
DV		 2256 if (INTEL_INFO(dev)->gen == 6)
2257 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2258
a2c7f6fd 2259 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2260 seq_printf(m, "%s\n", ring->name);
2261 if (INTEL_INFO(dev)->gen == 7)
2262 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2263 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2264 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2265 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2266 }
2267 if (dev_priv->mm.aliasing_ppgtt) {
2268 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2269
267f0c90 2270 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2271 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2272
87d60b63 2273 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2274 }
1c60fef5 2275
3cf17fc5 2276 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2277}
2278
2279static int i915_ppgtt_info(struct seq_file *m, void *data)
2280{
9f25d007 2281 struct drm_info_node *node = m->private;
77df6772 2282 struct drm_device *dev = node->minor->dev;
c8c8fb33 2283 struct drm_i915_private *dev_priv = dev->dev_private;
ea91e401 2284 struct drm_file *file;
77df6772
BW		 2285
2286 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2287 if (ret)
2288 return ret;
c8c8fb33 2289 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2290
2291 if (INTEL_INFO(dev)->gen >= 8)
2292 gen8_ppgtt_info(m, dev);
2293 else if (INTEL_INFO(dev)->gen >= 6)
2294 gen6_ppgtt_info(m, dev);
2295
ea91e401
MT		 2296 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2297 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2298 struct task_struct *task;
ea91e401 2299
7cb5dff8 2300 task = get_pid_task(file->pid, PIDTYPE_PID);
06812760
DC		 2301 if (!task) {
2302 ret = -ESRCH;
2303 goto out_put;
2304 }
7cb5dff8
GT		 2305 seq_printf(m, "\nproc: %s\n", task->comm);
2306 put_task_struct(task);
ea91e401
MT		 2307 idr_for_each(&file_priv->context_idr, per_file_ctx,
2308 (void *)(unsigned long)m);
2309 }
2310
06812760 2311out_put:
c8c8fb33 2312 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2313 mutex_unlock(&dev->struct_mutex);
2314
06812760 2315 return ret;
3cf17fc5
DV		 2316}
2317
f5a4c67d
CW		 2318static int count_irq_waiters(struct drm_i915_private *i915)
2319{
2320 struct intel_engine_cs *ring;
2321 int count = 0;
2322 int i;
2323
2324 for_each_ring(ring, i915, i)
2325 count += ring->irq_refcount;
2326
2327 return count;
2328}
2329
1854d5ca
CW		 2330static int i915_rps_boost_info(struct seq_file *m, void *data)
2331{
2332 struct drm_info_node *node = m->private;
2333 struct drm_device *dev = node->minor->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct drm_file *file;
1854d5ca 2336
f5a4c67d
CW		 2337 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2338 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2339 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2340 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2341 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2342 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2343 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2344 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2345 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2346 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2347 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2348 struct drm_i915_file_private *file_priv = file->driver_priv;
2349 struct task_struct *task;
2350
2351 rcu_read_lock();
2352 task = pid_task(file->pid, PIDTYPE_PID);
2353 seq_printf(m, "%s [%d]: %d boosts%s\n",
2354 task ? task->comm : "<unknown>",
2355 task ? task->pid : -1,
2e1b8730
CW		 2356 file_priv->rps.boosts,
2357 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2358 rcu_read_unlock();
2359 }
2e1b8730
CW		 2360 seq_printf(m, "Semaphore boosts: %d%s\n",
2361 dev_priv->rps.semaphores.boosts,
2362 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2363 seq_printf(m, "MMIO flip boosts: %d%s\n",
2364 dev_priv->rps.mmioflips.boosts,
2365 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2366 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2367 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2368
8d3afd7d 2369 return 0;
1854d5ca
CW		 2370}
2371
63573eb7
BW		 2372static int i915_llc(struct seq_file *m, void *data)
2373{
9f25d007 2374 struct drm_info_node *node = m->private;
63573eb7
BW		 2375 struct drm_device *dev = node->minor->dev;
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377
2378 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2379 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2380 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2381
2382 return 0;
2383}
2384
fdf5d357
AD		 2385static int i915_guc_load_status_info(struct seq_file *m, void *data)
2386{
2387 struct drm_info_node *node = m->private;
2388 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2389 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2390 u32 tmp, i;
2391
2392 if (!HAS_GUC_UCODE(dev_priv->dev))
2393 return 0;
2394
2395 seq_printf(m, "GuC firmware status:\n");
2396 seq_printf(m, "\tpath: %s\n",
2397 guc_fw->guc_fw_path);
2398 seq_printf(m, "\tfetch: %s\n",
2399 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2400 seq_printf(m, "\tload: %s\n",
2401 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2402 seq_printf(m, "\tversion wanted: %d.%d\n",
2403 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2404 seq_printf(m, "\tversion found: %d.%d\n",
2405 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
feda33ef
AD		 2406 seq_printf(m, "\theader: offset is %d; size = %d\n",
2407 guc_fw->header_offset, guc_fw->header_size);
2408 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2409 guc_fw->ucode_offset, guc_fw->ucode_size);
2410 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2411 guc_fw->rsa_offset, guc_fw->rsa_size);
fdf5d357
AD		 2412
2413 tmp = I915_READ(GUC_STATUS);
2414
2415 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2416 seq_printf(m, "\tBootrom status = 0x%x\n",
2417 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2418 seq_printf(m, "\tuKernel status = 0x%x\n",
2419 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2420 seq_printf(m, "\tMIA Core status = 0x%x\n",
2421 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2422 seq_puts(m, "\nScratch registers:\n");
2423 for (i = 0; i < 16; i++)
2424 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2425
2426 return 0;
2427}
2428
8b417c26
DG		 2429static void i915_guc_client_info(struct seq_file *m,
2430 struct drm_i915_private *dev_priv,
2431 struct i915_guc_client *client)
2432{
2433 struct intel_engine_cs *ring;
2434 uint64_t tot = 0;
2435 uint32_t i;
2436
2437 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2438 client->priority, client->ctx_index, client->proc_desc_offset);
2439 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2440 client->doorbell_id, client->doorbell_offset, client->cookie);
2441 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2442 client->wq_size, client->wq_offset, client->wq_tail);
2443
2444 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2445 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2446 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2447
2448 for_each_ring(ring, dev_priv, i) {
2449 seq_printf(m, "\tSubmissions: %llu %s\n",
2450 client->submissions[i],
2451 ring->name);
2452 tot += client->submissions[i];
2453 }
2454 seq_printf(m, "\tTotal: %llu\n", tot);
2455}
2456
2457static int i915_guc_info(struct seq_file *m, void *data)
2458{
2459 struct drm_info_node *node = m->private;
2460 struct drm_device *dev = node->minor->dev;
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2462 struct intel_guc guc;
0a0b457f 2463 struct i915_guc_client client = {};
8b417c26
DG		 2464 struct intel_engine_cs *ring;
2465 enum intel_ring_id i;
2466 u64 total = 0;
2467
2468 if (!HAS_GUC_SCHED(dev_priv->dev))
2469 return 0;
2470
2471 /* Take a local copy of the GuC data, so we can dump it at leisure */
2472 spin_lock(&dev_priv->guc.host2guc_lock);
2473 guc = dev_priv->guc;
2474 if (guc.execbuf_client) {
2475 spin_lock(&guc.execbuf_client->wq_lock);
2476 client = *guc.execbuf_client;
2477 spin_unlock(&guc.execbuf_client->wq_lock);
2478 }
2479 spin_unlock(&dev_priv->guc.host2guc_lock);
2480
2481 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2482 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2483 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2484 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2485 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2486
2487 seq_printf(m, "\nGuC submissions:\n");
2488 for_each_ring(ring, dev_priv, i) {
2489 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2490 ring->name, guc.submissions[i],
2491 guc.last_seqno[i], guc.last_seqno[i]);
2492 total += guc.submissions[i];
2493 }
2494 seq_printf(m, "\t%s: %llu\n", "Total", total);
2495
2496 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2497 i915_guc_client_info(m, dev_priv, &client);
2498
2499 /* Add more as required ... */
2500
2501 return 0;
2502}
2503
4c7e77fc
AD		 2504static int i915_guc_log_dump(struct seq_file *m, void *data)
2505{
2506 struct drm_info_node *node = m->private;
2507 struct drm_device *dev = node->minor->dev;
2508 struct drm_i915_private *dev_priv = dev->dev_private;
2509 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2510 u32 *log;
2511 int i = 0, pg;
2512
2513 if (!log_obj)
2514 return 0;
2515
2516 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2517 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2518
2519 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2520 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2521 *(log + i), *(log + i + 1),
2522 *(log + i + 2), *(log + i + 3));
2523
2524 kunmap_atomic(log);
2525 }
2526
2527 seq_putc(m, '\n');
2528
2529 return 0;
2530}
2531
e91fd8c6
RV		 2532static int i915_edp_psr_status(struct seq_file *m, void *data)
2533{
2534 struct drm_info_node *node = m->private;
2535 struct drm_device *dev = node->minor->dev;
2536 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2537 u32 psrperf = 0;
a6cbdb8e
RV		 2538 u32 stat[3];
2539 enum pipe pipe;
a031d709 2540 bool enabled = false;
e91fd8c6 2541
3553a8ea
DL		 2542 if (!HAS_PSR(dev)) {
2543 seq_puts(m, "PSR not supported\n");
2544 return 0;
2545 }
2546
c8c8fb33
PZ		 2547 intel_runtime_pm_get(dev_priv);
2548
fa128fa6 2549 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2550 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2551 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2552 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2553 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2554 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2555 dev_priv->psr.busy_frontbuffer_bits);
2556 seq_printf(m, "Re-enable work scheduled: %s\n",
2557 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2558
3553a8ea
DL		 2559 if (HAS_DDI(dev))
2560 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2561 else {
2562 for_each_pipe(dev_priv, pipe) {
2563 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2564 VLV_EDP_PSR_CURR_STATE_MASK;
2565 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2566 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2567 enabled = true;
a6cbdb8e
RV		 2568 }
2569 }
2570 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2571
2572 if (!HAS_DDI(dev))
2573 for_each_pipe(dev_priv, pipe) {
2574 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2575 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2576 seq_printf(m, " pipe %c", pipe_name(pipe));
2577 }
2578 seq_puts(m, "\n");
e91fd8c6 2579
a6cbdb8e 2580 /* CHV PSR has no kind of performance counter */
3553a8ea 2581 if (HAS_DDI(dev)) {
a031d709
RV		 2582 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2583 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2584
2585 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2586 }
fa128fa6 2587 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2588
c8c8fb33 2589 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2590 return 0;
2591}
2592
d2e216d0
RV		 2593static int i915_sink_crc(struct seq_file *m, void *data)
2594{
2595 struct drm_info_node *node = m->private;
2596 struct drm_device *dev = node->minor->dev;
2597 struct intel_encoder *encoder;
2598 struct intel_connector *connector;
2599 struct intel_dp *intel_dp = NULL;
2600 int ret;
2601 u8 crc[6];
2602
2603 drm_modeset_lock_all(dev);
aca5e361 2604 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2605
2606 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2607 continue;
2608
b6ae3c7c
PZ		 2609 if (!connector->base.encoder)
2610 continue;
2611
d2e216d0
RV		 2612 encoder = to_intel_encoder(connector->base.encoder);
2613 if (encoder->type != INTEL_OUTPUT_EDP)
2614 continue;
2615
2616 intel_dp = enc_to_intel_dp(&encoder->base);
2617
2618 ret = intel_dp_sink_crc(intel_dp, crc);
2619 if (ret)
2620 goto out;
2621
2622 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2623 crc[0], crc[1], crc[2],
2624 crc[3], crc[4], crc[5]);
2625 goto out;
2626 }
2627 ret = -ENODEV;
2628out:
2629 drm_modeset_unlock_all(dev);
2630 return ret;
2631}
2632
ec013e7f
JB		 2633static int i915_energy_uJ(struct seq_file *m, void *data)
2634{
2635 struct drm_info_node *node = m->private;
2636 struct drm_device *dev = node->minor->dev;
2637 struct drm_i915_private *dev_priv = dev->dev_private;
2638 u64 power;
2639 u32 units;
2640
2641 if (INTEL_INFO(dev)->gen < 6)
2642 return -ENODEV;
2643
36623ef8
PZ		 2644 intel_runtime_pm_get(dev_priv);
2645
ec013e7f
JB		 2646 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2647 power = (power & 0x1f00) >> 8;
2648 units = 1000000 / (1 << power); /* convert to uJ */
2649 power = I915_READ(MCH_SECP_NRG_STTS);
2650 power *= units;
2651
36623ef8
PZ		 2652 intel_runtime_pm_put(dev_priv);
2653
ec013e7f 2654 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2655
2656 return 0;
2657}
2658
6455c870 2659static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2660{
9f25d007 2661 struct drm_info_node *node = m->private;
371db66a
PZ		 2662 struct drm_device *dev = node->minor->dev;
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664
6455c870 2665 if (!HAS_RUNTIME_PM(dev)) {
371db66a
PZ		 2666 seq_puts(m, "not supported\n");
2667 return 0;
2668 }
2669
86c4ec0d 2670 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2671 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2672 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2673#ifdef CONFIG_PM
a6aaec8b
DL		 2674 seq_printf(m, "Usage count: %d\n",
2675 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2676#else
2677 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2678#endif
371db66a 2679
ec013e7f
JB		 2680 return 0;
2681}
2682
1da51581
ID		 2683static const char *power_domain_str(enum intel_display_power_domain domain)
2684{
2685 switch (domain) {
2686 case POWER_DOMAIN_PIPE_A:
2687 return "PIPE_A";
2688 case POWER_DOMAIN_PIPE_B:
2689 return "PIPE_B";
2690 case POWER_DOMAIN_PIPE_C:
2691 return "PIPE_C";
2692 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2693 return "PIPE_A_PANEL_FITTER";
2694 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2695 return "PIPE_B_PANEL_FITTER";
2696 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2697 return "PIPE_C_PANEL_FITTER";
2698 case POWER_DOMAIN_TRANSCODER_A:
2699 return "TRANSCODER_A";
2700 case POWER_DOMAIN_TRANSCODER_B:
2701 return "TRANSCODER_B";
2702 case POWER_DOMAIN_TRANSCODER_C:
2703 return "TRANSCODER_C";
2704 case POWER_DOMAIN_TRANSCODER_EDP:
2705 return "TRANSCODER_EDP";
319be8ae
ID		 2706 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2707 return "PORT_DDI_A_2_LANES";
2708 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2709 return "PORT_DDI_A_4_LANES";
2710 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2711 return "PORT_DDI_B_2_LANES";
2712 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2713 return "PORT_DDI_B_4_LANES";
2714 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2715 return "PORT_DDI_C_2_LANES";
2716 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2717 return "PORT_DDI_C_4_LANES";
2718 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2719 return "PORT_DDI_D_2_LANES";
2720 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2721 return "PORT_DDI_D_4_LANES";
d8e19f99
XZ		 2722 case POWER_DOMAIN_PORT_DDI_E_2_LANES:
2723 return "PORT_DDI_E_2_LANES";
319be8ae
ID		 2724 case POWER_DOMAIN_PORT_DSI:
2725 return "PORT_DSI";
2726 case POWER_DOMAIN_PORT_CRT:
2727 return "PORT_CRT";
2728 case POWER_DOMAIN_PORT_OTHER:
2729 return "PORT_OTHER";
1da51581
ID		 2730 case POWER_DOMAIN_VGA:
2731 return "VGA";
2732 case POWER_DOMAIN_AUDIO:
2733 return "AUDIO";
bd2bb1b9
PZ		 2734 case POWER_DOMAIN_PLLS:
2735 return "PLLS";
1407121a
S		 2736 case POWER_DOMAIN_AUX_A:
2737 return "AUX_A";
2738 case POWER_DOMAIN_AUX_B:
2739 return "AUX_B";
2740 case POWER_DOMAIN_AUX_C:
2741 return "AUX_C";
2742 case POWER_DOMAIN_AUX_D:
2743 return "AUX_D";
1da51581
ID		 2744 case POWER_DOMAIN_INIT:
2745 return "INIT";
2746 default:
5f77eeb0 2747 MISSING_CASE(domain);
1da51581
ID		 2748 return "?";
2749 }
2750}
2751
2752static int i915_power_domain_info(struct seq_file *m, void *unused)
2753{
9f25d007 2754 struct drm_info_node *node = m->private;
1da51581
ID		 2755 struct drm_device *dev = node->minor->dev;
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2758 int i;
2759
2760 mutex_lock(&power_domains->lock);
2761
2762 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2763 for (i = 0; i < power_domains->power_well_count; i++) {
2764 struct i915_power_well *power_well;
2765 enum intel_display_power_domain power_domain;
2766
2767 power_well = &power_domains->power_wells[i];
2768 seq_printf(m, "%-25s %d\n", power_well->name,
2769 power_well->count);
2770
2771 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2772 power_domain++) {
2773 if (!(BIT(power_domain) & power_well->domains))
2774 continue;
2775
2776 seq_printf(m, " %-23s %d\n",
2777 power_domain_str(power_domain),
2778 power_domains->domain_use_count[power_domain]);
2779 }
2780 }
2781
2782 mutex_unlock(&power_domains->lock);
2783
2784 return 0;
2785}
2786
53f5e3ca
JB		 2787static void intel_seq_print_mode(struct seq_file *m, int tabs,
2788 struct drm_display_mode *mode)
2789{
2790 int i;
2791
2792 for (i = 0; i < tabs; i++)
2793 seq_putc(m, '\t');
2794
2795 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2796 mode->base.id, mode->name,
2797 mode->vrefresh, mode->clock,
2798 mode->hdisplay, mode->hsync_start,
2799 mode->hsync_end, mode->htotal,
2800 mode->vdisplay, mode->vsync_start,
2801 mode->vsync_end, mode->vtotal,
2802 mode->type, mode->flags);
2803}
2804
2805static void intel_encoder_info(struct seq_file *m,
2806 struct intel_crtc *intel_crtc,
2807 struct intel_encoder *intel_encoder)
2808{
9f25d007 2809 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2810 struct drm_device *dev = node->minor->dev;
2811 struct drm_crtc *crtc = &intel_crtc->base;
2812 struct intel_connector *intel_connector;
2813 struct drm_encoder *encoder;
2814
2815 encoder = &intel_encoder->base;
2816 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2817 encoder->base.id, encoder->name);
53f5e3ca
JB		 2818 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2819 struct drm_connector *connector = &intel_connector->base;
2820 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2821 connector->base.id,
c23cc417 2822 connector->name,
53f5e3ca
JB		 2823 drm_get_connector_status_name(connector->status));
2824 if (connector->status == connector_status_connected) {
2825 struct drm_display_mode *mode = &crtc->mode;
2826 seq_printf(m, ", mode:\n");
2827 intel_seq_print_mode(m, 2, mode);
2828 } else {
2829 seq_putc(m, '\n');
2830 }
2831 }
2832}
2833
2834static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2835{
9f25d007 2836 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2837 struct drm_device *dev = node->minor->dev;
2838 struct drm_crtc *crtc = &intel_crtc->base;
2839 struct intel_encoder *intel_encoder;
23a48d53
ML		 2840 struct drm_plane_state *plane_state = crtc->primary->state;
2841 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2842
23a48d53 2843 if (fb)
5aa8a937 2844 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2845 fb->base.id, plane_state->src_x >> 16,
2846 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2847 else
2848 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2849 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2850 intel_encoder_info(m, intel_crtc, intel_encoder);
2851}
2852
2853static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2854{
2855 struct drm_display_mode *mode = panel->fixed_mode;
2856
2857 seq_printf(m, "\tfixed mode:\n");
2858 intel_seq_print_mode(m, 2, mode);
2859}
2860
2861static void intel_dp_info(struct seq_file *m,
2862 struct intel_connector *intel_connector)
2863{
2864 struct intel_encoder *intel_encoder = intel_connector->encoder;
2865 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2866
2867 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2868 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
53f5e3ca
JB		 2869 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2870 intel_panel_info(m, &intel_connector->panel);
2871}
2872
2873static void intel_hdmi_info(struct seq_file *m,
2874 struct intel_connector *intel_connector)
2875{
2876 struct intel_encoder *intel_encoder = intel_connector->encoder;
2877 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2878
742f491d 2879 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2880}
2881
2882static void intel_lvds_info(struct seq_file *m,
2883 struct intel_connector *intel_connector)
2884{
2885 intel_panel_info(m, &intel_connector->panel);
2886}
2887
2888static void intel_connector_info(struct seq_file *m,
2889 struct drm_connector *connector)
2890{
2891 struct intel_connector *intel_connector = to_intel_connector(connector);
2892 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2893 struct drm_display_mode *mode;
53f5e3ca
JB		 2894
2895 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2896 connector->base.id, connector->name,
53f5e3ca
JB		 2897 drm_get_connector_status_name(connector->status));
2898 if (connector->status == connector_status_connected) {
2899 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2900 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2901 connector->display_info.width_mm,
2902 connector->display_info.height_mm);
2903 seq_printf(m, "\tsubpixel order: %s\n",
2904 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2905 seq_printf(m, "\tCEA rev: %d\n",
2906 connector->display_info.cea_rev);
2907 }
36cd7444
DA		 2908 if (intel_encoder) {
2909 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2910 intel_encoder->type == INTEL_OUTPUT_EDP)
2911 intel_dp_info(m, intel_connector);
2912 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2913 intel_hdmi_info(m, intel_connector);
2914 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2915 intel_lvds_info(m, intel_connector);
2916 }
53f5e3ca 2917
f103fc7d
JB		 2918 seq_printf(m, "\tmodes:\n");
2919 list_for_each_entry(mode, &connector->modes, head)
2920 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2921}
2922
065f2ec2
CW		 2923static bool cursor_active(struct drm_device *dev, int pipe)
2924{
2925 struct drm_i915_private *dev_priv = dev->dev_private;
2926 u32 state;
2927
2928 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 2929 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
065f2ec2 2930 else
5efb3e28 2931 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2932
2933 return state;
2934}
2935
2936static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2937{
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 u32 pos;
2940
5efb3e28 2941 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2942
2943 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2944 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2945 *x = -*x;
2946
2947 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2948 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2949 *y = -*y;
2950
2951 return cursor_active(dev, pipe);
2952}
2953
53f5e3ca
JB		 2954static int i915_display_info(struct seq_file *m, void *unused)
2955{
9f25d007 2956 struct drm_info_node *node = m->private;
53f5e3ca 2957 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2958 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2959 struct intel_crtc *crtc;
53f5e3ca
JB		 2960 struct drm_connector *connector;
2961
b0e5ddf3 2962 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2963 drm_modeset_lock_all(dev);
2964 seq_printf(m, "CRTC info\n");
2965 seq_printf(m, "---------\n");
d3fcc808 2966 for_each_intel_crtc(dev, crtc) {
065f2ec2 2967 bool active;
f77076c9 2968 struct intel_crtc_state *pipe_config;
065f2ec2 2969 int x, y;
53f5e3ca 2970
f77076c9
ML		 2971 pipe_config = to_intel_crtc_state(crtc->base.state);
2972
57127efa 2973 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2974 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9
ML		 2975 yesno(pipe_config->base.active),
2976 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2977 if (pipe_config->base.active) {
065f2ec2
CW		 2978 intel_crtc_info(m, crtc);
2979
a23dc658 2980 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2981 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2982 yesno(crtc->cursor_base),
3dd512fb
MR		 2983 x, y, crtc->base.cursor->state->crtc_w,
2984 crtc->base.cursor->state->crtc_h,
57127efa 2985 crtc->cursor_addr, yesno(active));
a23dc658 2986 }
cace841c
DV		 2987
2988 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2989 yesno(!crtc->cpu_fifo_underrun_disabled),
2990 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2991 }
2992
2993 seq_printf(m, "\n");
2994 seq_printf(m, "Connector info\n");
2995 seq_printf(m, "--------------\n");
2996 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2997 intel_connector_info(m, connector);
2998 }
2999 drm_modeset_unlock_all(dev);
b0e5ddf3 3000 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 3001
3002 return 0;
3003}
3004
e04934cf
BW		 3005static int i915_semaphore_status(struct seq_file *m, void *unused)
3006{
3007 struct drm_info_node *node = (struct drm_info_node *) m->private;
3008 struct drm_device *dev = node->minor->dev;
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_engine_cs *ring;
3011 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3012 int i, j, ret;
3013
3014 if (!i915_semaphore_is_enabled(dev)) {
3015 seq_puts(m, "Semaphores are disabled\n");
3016 return 0;
3017 }
3018
3019 ret = mutex_lock_interruptible(&dev->struct_mutex);
3020 if (ret)
3021 return ret;
03872064 3022 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 3023
3024 if (IS_BROADWELL(dev)) {
3025 struct page *page;
3026 uint64_t *seqno;
3027
3028 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3029
3030 seqno = (uint64_t *)kmap_atomic(page);
3031 for_each_ring(ring, dev_priv, i) {
3032 uint64_t offset;
3033
3034 seq_printf(m, "%s\n", ring->name);
3035
3036 seq_puts(m, " Last signal:");
3037 for (j = 0; j < num_rings; j++) {
3038 offset = i * I915_NUM_RINGS + j;
3039 seq_printf(m, "0x%08llx (0x%02llx) ",
3040 seqno[offset], offset * 8);
3041 }
3042 seq_putc(m, '\n');
3043
3044 seq_puts(m, " Last wait: ");
3045 for (j = 0; j < num_rings; j++) {
3046 offset = i + (j * I915_NUM_RINGS);
3047 seq_printf(m, "0x%08llx (0x%02llx) ",
3048 seqno[offset], offset * 8);
3049 }
3050 seq_putc(m, '\n');
3051
3052 }
3053 kunmap_atomic(seqno);
3054 } else {
3055 seq_puts(m, " Last signal:");
3056 for_each_ring(ring, dev_priv, i)
3057 for (j = 0; j < num_rings; j++)
3058 seq_printf(m, "0x%08x\n",
3059 I915_READ(ring->semaphore.mbox.signal[j]));
3060 seq_putc(m, '\n');
3061 }
3062
3063 seq_puts(m, "\nSync seqno:\n");
3064 for_each_ring(ring, dev_priv, i) {
3065 for (j = 0; j < num_rings; j++) {
3066 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
3067 }
3068 seq_putc(m, '\n');
3069 }
3070 seq_putc(m, '\n');
3071
03872064 3072 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3073 mutex_unlock(&dev->struct_mutex);
3074 return 0;
3075}
3076
728e29d7
DV		 3077static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3078{
3079 struct drm_info_node *node = (struct drm_info_node *) m->private;
3080 struct drm_device *dev = node->minor->dev;
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 int i;
3083
3084 drm_modeset_lock_all(dev);
3085 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3086 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3087
3088 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 3089 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 3090 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 3091 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3092 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3093 seq_printf(m, " dpll_md: 0x%08x\n",
3094 pll->config.hw_state.dpll_md);
3095 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3096 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3097 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3098 }
3099 drm_modeset_unlock_all(dev);
3100
3101 return 0;
3102}
3103
1ed1ef9d 3104static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3105{
3106 int i;
3107 int ret;
3108 struct drm_info_node *node = (struct drm_info_node *) m->private;
3109 struct drm_device *dev = node->minor->dev;
3110 struct drm_i915_private *dev_priv = dev->dev_private;
3111
888b5995
AS		 3112 ret = mutex_lock_interruptible(&dev->struct_mutex);
3113 if (ret)
3114 return ret;
3115
3116 intel_runtime_pm_get(dev_priv);
3117
7225342a
MK		 3118 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3119 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 3120 u32 addr, mask, value, read;
3121 bool ok;
888b5995 3122
7225342a
MK		 3123 addr = dev_priv->workarounds.reg[i].addr;
3124 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 3125 value = dev_priv->workarounds.reg[i].value;
3126 read = I915_READ(addr);
3127 ok = (value & mask) == (read & mask);
3128 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3129 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3130 }
3131
3132 intel_runtime_pm_put(dev_priv);
3133 mutex_unlock(&dev->struct_mutex);
3134
3135 return 0;
3136}
3137
c5511e44
DL		 3138static int i915_ddb_info(struct seq_file *m, void *unused)
3139{
3140 struct drm_info_node *node = m->private;
3141 struct drm_device *dev = node->minor->dev;
3142 struct drm_i915_private *dev_priv = dev->dev_private;
3143 struct skl_ddb_allocation *ddb;
3144 struct skl_ddb_entry *entry;
3145 enum pipe pipe;
3146 int plane;
3147
2fcffe19
DL		 3148 if (INTEL_INFO(dev)->gen < 9)
3149 return 0;
3150
c5511e44
DL		 3151 drm_modeset_lock_all(dev);
3152
3153 ddb = &dev_priv->wm.skl_hw.ddb;
3154
3155 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3156
3157 for_each_pipe(dev_priv, pipe) {
3158 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3159
dd740780 3160 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3161 entry = &ddb->plane[pipe][plane];
3162 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3163 entry->start, entry->end,
3164 skl_ddb_entry_size(entry));
3165 }
3166
4969d33e 3167 entry = &ddb->plane[pipe][PLANE_CURSOR];
c5511e44
DL		 3168 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3169 entry->end, skl_ddb_entry_size(entry));
3170 }
3171
3172 drm_modeset_unlock_all(dev);
3173
3174 return 0;
3175}
3176
a54746e3
VK		 3177static void drrs_status_per_crtc(struct seq_file *m,
3178 struct drm_device *dev, struct intel_crtc *intel_crtc)
3179{
3180 struct intel_encoder *intel_encoder;
3181 struct drm_i915_private *dev_priv = dev->dev_private;
3182 struct i915_drrs *drrs = &dev_priv->drrs;
3183 int vrefresh = 0;
3184
3185 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3186 /* Encoder connected on this CRTC */
3187 switch (intel_encoder->type) {
3188 case INTEL_OUTPUT_EDP:
3189 seq_puts(m, "eDP:\n");
3190 break;
3191 case INTEL_OUTPUT_DSI:
3192 seq_puts(m, "DSI:\n");
3193 break;
3194 case INTEL_OUTPUT_HDMI:
3195 seq_puts(m, "HDMI:\n");
3196 break;
3197 case INTEL_OUTPUT_DISPLAYPORT:
3198 seq_puts(m, "DP:\n");
3199 break;
3200 default:
3201 seq_printf(m, "Other encoder (id=%d).\n",
3202 intel_encoder->type);
3203 return;
3204 }
3205 }
3206
3207 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3208 seq_puts(m, "\tVBT: DRRS_type: Static");
3209 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3210 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3211 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3212 seq_puts(m, "\tVBT: DRRS_type: None");
3213 else
3214 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3215
3216 seq_puts(m, "\n\n");
3217
f77076c9 3218 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3219 struct intel_panel *panel;
3220
3221 mutex_lock(&drrs->mutex);
3222 /* DRRS Supported */
3223 seq_puts(m, "\tDRRS Supported: Yes\n");
3224
3225 /* disable_drrs() will make drrs->dp NULL */
3226 if (!drrs->dp) {
3227 seq_puts(m, "Idleness DRRS: Disabled");
3228 mutex_unlock(&drrs->mutex);
3229 return;
3230 }
3231
3232 panel = &drrs->dp->attached_connector->panel;
3233 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3234 drrs->busy_frontbuffer_bits);
3235
3236 seq_puts(m, "\n\t\t");
3237 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3238 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3239 vrefresh = panel->fixed_mode->vrefresh;
3240 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3241 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3242 vrefresh = panel->downclock_mode->vrefresh;
3243 } else {
3244 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3245 drrs->refresh_rate_type);
3246 mutex_unlock(&drrs->mutex);
3247 return;
3248 }
3249 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3250
3251 seq_puts(m, "\n\t\t");
3252 mutex_unlock(&drrs->mutex);
3253 } else {
3254 /* DRRS not supported. Print the VBT parameter*/
3255 seq_puts(m, "\tDRRS Supported : No");
3256 }
3257 seq_puts(m, "\n");
3258}
3259
3260static int i915_drrs_status(struct seq_file *m, void *unused)
3261{
3262 struct drm_info_node *node = m->private;
3263 struct drm_device *dev = node->minor->dev;
3264 struct intel_crtc *intel_crtc;
3265 int active_crtc_cnt = 0;
3266
3267 for_each_intel_crtc(dev, intel_crtc) {
3268 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3269
f77076c9 3270 if (intel_crtc->base.state->active) {
a54746e3
VK		 3271 active_crtc_cnt++;
3272 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3273
3274 drrs_status_per_crtc(m, dev, intel_crtc);
3275 }
3276
3277 drm_modeset_unlock(&intel_crtc->base.mutex);
3278 }
3279
3280 if (!active_crtc_cnt)
3281 seq_puts(m, "No active crtc found\n");
3282
3283 return 0;
3284}
3285
07144428
DL		 3286struct pipe_crc_info {
3287 const char *name;
3288 struct drm_device *dev;
3289 enum pipe pipe;
3290};
3291
11bed958
DA		 3292static int i915_dp_mst_info(struct seq_file *m, void *unused)
3293{
3294 struct drm_info_node *node = (struct drm_info_node *) m->private;
3295 struct drm_device *dev = node->minor->dev;
3296 struct drm_encoder *encoder;
3297 struct intel_encoder *intel_encoder;
3298 struct intel_digital_port *intel_dig_port;
3299 drm_modeset_lock_all(dev);
3300 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3301 intel_encoder = to_intel_encoder(encoder);
3302 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3303 continue;
3304 intel_dig_port = enc_to_dig_port(encoder);
3305 if (!intel_dig_port->dp.can_mst)
3306 continue;
3307
3308 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3309 }
3310 drm_modeset_unlock_all(dev);
3311 return 0;
3312}
3313
07144428
DL		 3314static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3315{
be5c7a90
DL		 3316 struct pipe_crc_info *info = inode->i_private;
3317 struct drm_i915_private *dev_priv = info->dev->dev_private;
3318 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3319
7eb1c496
DV		 3320 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3321 return -ENODEV;
3322
d538bbdf
DL		 3323 spin_lock_irq(&pipe_crc->lock);
3324
3325 if (pipe_crc->opened) {
3326 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3327 return -EBUSY; /* already open */
3328 }
3329
d538bbdf 3330 pipe_crc->opened = true;
07144428
DL		 3331 filep->private_data = inode->i_private;
3332
d538bbdf
DL		 3333 spin_unlock_irq(&pipe_crc->lock);
3334
07144428
DL		 3335 return 0;
3336}
3337
3338static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3339{
be5c7a90
DL		 3340 struct pipe_crc_info *info = inode->i_private;
3341 struct drm_i915_private *dev_priv = info->dev->dev_private;
3342 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3343
d538bbdf
DL		 3344 spin_lock_irq(&pipe_crc->lock);
3345 pipe_crc->opened = false;
3346 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3347
07144428
DL		 3348 return 0;
3349}
3350
3351/* (6 fields, 8 chars each, space separated (5) + '\n') */
3352#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3353/* account for \'0' */
3354#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3355
3356static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3357{
d538bbdf
DL		 3358 assert_spin_locked(&pipe_crc->lock);
3359 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3360 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3361}
3362
3363static ssize_t
3364i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3365 loff_t *pos)
3366{
3367 struct pipe_crc_info *info = filep->private_data;
3368 struct drm_device *dev = info->dev;
3369 struct drm_i915_private *dev_priv = dev->dev_private;
3370 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3371 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3372 int n_entries;
07144428
DL		 3373 ssize_t bytes_read;
3374
3375 /*
3376 * Don't allow user space to provide buffers not big enough to hold
3377 * a line of data.
3378 */
3379 if (count < PIPE_CRC_LINE_LEN)
3380 return -EINVAL;
3381
3382 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3383 return 0;
07144428
DL		 3384
3385 /* nothing to read */
d538bbdf 3386 spin_lock_irq(&pipe_crc->lock);
07144428 3387 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3388 int ret;
3389
3390 if (filep->f_flags & O_NONBLOCK) {
3391 spin_unlock_irq(&pipe_crc->lock);
07144428 3392 return -EAGAIN;
d538bbdf 3393 }
07144428 3394
d538bbdf
DL		 3395 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3396 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3397 if (ret) {
3398 spin_unlock_irq(&pipe_crc->lock);
3399 return ret;
3400 }
8bf1e9f1
SH		 3401 }
3402
07144428 3403 /* We now have one or more entries to read */
9ad6d99f 3404 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3405
07144428 3406 bytes_read = 0;
9ad6d99f
VS		 3407 while (n_entries > 0) {
3408 struct intel_pipe_crc_entry *entry =
3409 &pipe_crc->entries[pipe_crc->tail];
07144428 3410 int ret;
8bf1e9f1 3411
9ad6d99f
VS		 3412 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3413 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3414 break;
3415
3416 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3417 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3418
07144428
DL		 3419 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3420 "%8u %8x %8x %8x %8x %8x\n",
3421 entry->frame, entry->crc[0],
3422 entry->crc[1], entry->crc[2],
3423 entry->crc[3], entry->crc[4]);
3424
9ad6d99f
VS		 3425 spin_unlock_irq(&pipe_crc->lock);
3426
3427 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3428 if (ret == PIPE_CRC_LINE_LEN)
3429 return -EFAULT;
b2c88f5b 3430
9ad6d99f
VS		 3431 user_buf += PIPE_CRC_LINE_LEN;
3432 n_entries--;
3433
3434 spin_lock_irq(&pipe_crc->lock);
3435 }
8bf1e9f1 3436
d538bbdf
DL		 3437 spin_unlock_irq(&pipe_crc->lock);
3438
07144428
DL		 3439 return bytes_read;
3440}
3441
3442static const struct file_operations i915_pipe_crc_fops = {
3443 .owner = THIS_MODULE,
3444 .open = i915_pipe_crc_open,
3445 .read = i915_pipe_crc_read,
3446 .release = i915_pipe_crc_release,
3447};
3448
3449static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3450 {
3451 .name = "i915_pipe_A_crc",
3452 .pipe = PIPE_A,
3453 },
3454 {
3455 .name = "i915_pipe_B_crc",
3456 .pipe = PIPE_B,
3457 },
3458 {
3459 .name = "i915_pipe_C_crc",
3460 .pipe = PIPE_C,
3461 },
3462};
3463
3464static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3465 enum pipe pipe)
3466{
3467 struct drm_device *dev = minor->dev;
3468 struct dentry *ent;
3469 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3470
3471 info->dev = dev;
3472 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3473 &i915_pipe_crc_fops);
f3c5fe97
WY		 3474 if (!ent)
3475 return -ENOMEM;
07144428
DL		 3476
3477 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3478}
3479
e8dfcf78 3480static const char * const pipe_crc_sources[] = {
926321d5
DV		 3481 "none",
3482 "plane1",
3483 "plane2",
3484 "pf",
5b3a856b 3485 "pipe",
3d099a05
DV		 3486 "TV",
3487 "DP-B",
3488 "DP-C",
3489 "DP-D",
46a19188 3490 "auto",
926321d5
DV		 3491};
3492
3493static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3494{
3495 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3496 return pipe_crc_sources[source];
3497}
3498
bd9db02f 3499static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3500{
3501 struct drm_device *dev = m->private;
3502 struct drm_i915_private *dev_priv = dev->dev_private;
3503 int i;
3504
3505 for (i = 0; i < I915_MAX_PIPES; i++)
3506 seq_printf(m, "%c %s\n", pipe_name(i),
3507 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3508
3509 return 0;
3510}
3511
bd9db02f 3512static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3513{
3514 struct drm_device *dev = inode->i_private;
3515
bd9db02f 3516 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3517}
3518
46a19188 3519static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3520 uint32_t *val)
3521{
46a19188
DV		 3522 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3523 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3524
3525 switch (*source) {
52f843f6
DV		 3526 case INTEL_PIPE_CRC_SOURCE_PIPE:
3527 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3528 break;
3529 case INTEL_PIPE_CRC_SOURCE_NONE:
3530 *val = 0;
3531 break;
3532 default:
3533 return -EINVAL;
3534 }
3535
3536 return 0;
3537}
3538
46a19188
DV		 3539static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3540 enum intel_pipe_crc_source *source)
3541{
3542 struct intel_encoder *encoder;
3543 struct intel_crtc *crtc;
26756809 3544 struct intel_digital_port *dig_port;
46a19188
DV		 3545 int ret = 0;
3546
3547 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3548
6e9f798d 3549 drm_modeset_lock_all(dev);
b2784e15 3550 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3551 if (!encoder->base.crtc)
3552 continue;
3553
3554 crtc = to_intel_crtc(encoder->base.crtc);
3555
3556 if (crtc->pipe != pipe)
3557 continue;
3558
3559 switch (encoder->type) {
3560 case INTEL_OUTPUT_TVOUT:
3561 *source = INTEL_PIPE_CRC_SOURCE_TV;
3562 break;
3563 case INTEL_OUTPUT_DISPLAYPORT:
3564 case INTEL_OUTPUT_EDP:
26756809
DV		 3565 dig_port = enc_to_dig_port(&encoder->base);
3566 switch (dig_port->port) {
3567 case PORT_B:
3568 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3569 break;
3570 case PORT_C:
3571 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3572 break;
3573 case PORT_D:
3574 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3575 break;
3576 default:
3577 WARN(1, "nonexisting DP port %c\n",
3578 port_name(dig_port->port));
3579 break;
3580 }
46a19188 3581 break;
6847d71b
PZ		 3582 default:
3583 break;
46a19188
DV		 3584 }
3585 }
6e9f798d 3586 drm_modeset_unlock_all(dev);
46a19188
DV		 3587
3588 return ret;
3589}
3590
3591static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3592 enum pipe pipe,
3593 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3594 uint32_t *val)
3595{
8d2f24ca
DV		 3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 bool need_stable_symbols = false;
3598
46a19188
DV		 3599 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3600 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3601 if (ret)
3602 return ret;
3603 }
3604
3605 switch (*source) {
7ac0129b
DV		 3606 case INTEL_PIPE_CRC_SOURCE_PIPE:
3607 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3608 break;
3609 case INTEL_PIPE_CRC_SOURCE_DP_B:
3610 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3611 need_stable_symbols = true;
7ac0129b
DV		 3612 break;
3613 case INTEL_PIPE_CRC_SOURCE_DP_C:
3614 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3615 need_stable_symbols = true;
7ac0129b 3616 break;
2be57922
VS		 3617 case INTEL_PIPE_CRC_SOURCE_DP_D:
3618 if (!IS_CHERRYVIEW(dev))
3619 return -EINVAL;
3620 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3621 need_stable_symbols = true;
3622 break;
7ac0129b
DV		 3623 case INTEL_PIPE_CRC_SOURCE_NONE:
3624 *val = 0;
3625 break;
3626 default:
3627 return -EINVAL;
3628 }
3629
8d2f24ca
DV		 3630 /*
3631 * When the pipe CRC tap point is after the transcoders we need
3632 * to tweak symbol-level features to produce a deterministic series of
3633 * symbols for a given frame. We need to reset those features only once
3634 * a frame (instead of every nth symbol):
3635 * - DC-balance: used to ensure a better clock recovery from the data
3636 * link (SDVO)
3637 * - DisplayPort scrambling: used for EMI reduction
3638 */
3639 if (need_stable_symbols) {
3640 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3641
8d2f24ca 3642 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3643 switch (pipe) {
3644 case PIPE_A:
8d2f24ca 3645 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3646 break;
3647 case PIPE_B:
8d2f24ca 3648 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3649 break;
3650 case PIPE_C:
3651 tmp |= PIPE_C_SCRAMBLE_RESET;
3652 break;
3653 default:
3654 return -EINVAL;
3655 }
8d2f24ca
DV		 3656 I915_WRITE(PORT_DFT2_G4X, tmp);
3657 }
3658
7ac0129b
DV		 3659 return 0;
3660}
3661
4b79ebf7 3662static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3663 enum pipe pipe,
3664 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3665 uint32_t *val)
3666{
84093603
DV		 3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 bool need_stable_symbols = false;
3669
46a19188
DV		 3670 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3671 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3672 if (ret)
3673 return ret;
3674 }
3675
3676 switch (*source) {
4b79ebf7
DV		 3677 case INTEL_PIPE_CRC_SOURCE_PIPE:
3678 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3679 break;
3680 case INTEL_PIPE_CRC_SOURCE_TV:
3681 if (!SUPPORTS_TV(dev))
3682 return -EINVAL;
3683 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3684 break;
3685 case INTEL_PIPE_CRC_SOURCE_DP_B:
3686 if (!IS_G4X(dev))
3687 return -EINVAL;
3688 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3689 need_stable_symbols = true;
4b79ebf7
DV		 3690 break;
3691 case INTEL_PIPE_CRC_SOURCE_DP_C:
3692 if (!IS_G4X(dev))
3693 return -EINVAL;
3694 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3695 need_stable_symbols = true;
4b79ebf7
DV		 3696 break;
3697 case INTEL_PIPE_CRC_SOURCE_DP_D:
3698 if (!IS_G4X(dev))
3699 return -EINVAL;
3700 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3701 need_stable_symbols = true;
4b79ebf7
DV		 3702 break;
3703 case INTEL_PIPE_CRC_SOURCE_NONE:
3704 *val = 0;
3705 break;
3706 default:
3707 return -EINVAL;
3708 }
3709
84093603
DV		 3710 /*
3711 * When the pipe CRC tap point is after the transcoders we need
3712 * to tweak symbol-level features to produce a deterministic series of
3713 * symbols for a given frame. We need to reset those features only once
3714 * a frame (instead of every nth symbol):
3715 * - DC-balance: used to ensure a better clock recovery from the data
3716 * link (SDVO)
3717 * - DisplayPort scrambling: used for EMI reduction
3718 */
3719 if (need_stable_symbols) {
3720 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3721
3722 WARN_ON(!IS_G4X(dev));
3723
3724 I915_WRITE(PORT_DFT_I9XX,
3725 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3726
3727 if (pipe == PIPE_A)
3728 tmp |= PIPE_A_SCRAMBLE_RESET;
3729 else
3730 tmp |= PIPE_B_SCRAMBLE_RESET;
3731
3732 I915_WRITE(PORT_DFT2_G4X, tmp);
3733 }
3734
4b79ebf7
DV		 3735 return 0;
3736}
3737
8d2f24ca
DV		 3738static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3739 enum pipe pipe)
3740{
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3743
eb736679
VS		 3744 switch (pipe) {
3745 case PIPE_A:
8d2f24ca 3746 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3747 break;
3748 case PIPE_B:
8d2f24ca 3749 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3750 break;
3751 case PIPE_C:
3752 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3753 break;
3754 default:
3755 return;
3756 }
8d2f24ca
DV		 3757 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3758 tmp &= ~DC_BALANCE_RESET_VLV;
3759 I915_WRITE(PORT_DFT2_G4X, tmp);
3760
3761}
3762
84093603
DV		 3763static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3764 enum pipe pipe)
3765{
3766 struct drm_i915_private *dev_priv = dev->dev_private;
3767 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3768
3769 if (pipe == PIPE_A)
3770 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3771 else
3772 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3773 I915_WRITE(PORT_DFT2_G4X, tmp);
3774
3775 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3776 I915_WRITE(PORT_DFT_I9XX,
3777 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3778 }
3779}
3780
46a19188 3781static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3782 uint32_t *val)
3783{
46a19188
DV		 3784 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3785 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3786
3787 switch (*source) {
5b3a856b
DV		 3788 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3789 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3790 break;
3791 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3792 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3793 break;
5b3a856b
DV		 3794 case INTEL_PIPE_CRC_SOURCE_PIPE:
3795 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3796 break;
3d099a05 3797 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3798 *val = 0;
3799 break;
3d099a05
DV		 3800 default:
3801 return -EINVAL;
5b3a856b
DV		 3802 }
3803
3804 return 0;
3805}
3806
c4e2d043 3807static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51
DV		 3808{
3809 struct drm_i915_private *dev_priv = dev->dev_private;
3810 struct intel_crtc *crtc =
3811 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3812 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3813 struct drm_atomic_state *state;
3814 int ret = 0;
fabf6e51
DV		 3815
3816 drm_modeset_lock_all(dev);
c4e2d043
ML		 3817 state = drm_atomic_state_alloc(dev);
3818 if (!state) {
3819 ret = -ENOMEM;
3820 goto out;
fabf6e51 3821 }
fabf6e51 3822
c4e2d043
ML		 3823 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3824 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3825 if (IS_ERR(pipe_config)) {
3826 ret = PTR_ERR(pipe_config);
3827 goto out;
3828 }
fabf6e51 3829
c4e2d043
ML		 3830 pipe_config->pch_pfit.force_thru = enable;
3831 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3832 pipe_config->pch_pfit.enabled != enable)
3833 pipe_config->base.connectors_changed = true;
1b509259 3834
c4e2d043
ML		 3835 ret = drm_atomic_commit(state);
3836out:
fabf6e51 3837 drm_modeset_unlock_all(dev);
c4e2d043
ML		 3838 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3839 if (ret)
3840 drm_atomic_state_free(state);
fabf6e51
DV		 3841}
3842
3843static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3844 enum pipe pipe,
3845 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3846 uint32_t *val)
3847{
46a19188
DV		 3848 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3849 *source = INTEL_PIPE_CRC_SOURCE_PF;
3850
3851 switch (*source) {
5b3a856b
DV		 3852 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3853 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3854 break;
3855 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3856 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3857 break;
3858 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 3859 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 3860 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 3861
5b3a856b
DV		 3862 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3863 break;
3d099a05 3864 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3865 *val = 0;
3866 break;
3d099a05
DV		 3867 default:
3868 return -EINVAL;
5b3a856b
DV		 3869 }
3870
3871 return 0;
3872}
3873
926321d5
DV		 3874static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3875 enum intel_pipe_crc_source source)
3876{
3877 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3878 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3879 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3880 pipe));
432f3342 3881 u32 val = 0; /* shut up gcc */
5b3a856b 3882 int ret;
926321d5 3883
cc3da175
DL		 3884 if (pipe_crc->source == source)
3885 return 0;
3886
ae676fcd
DL		 3887 /* forbid changing the source without going back to 'none' */
3888 if (pipe_crc->source && source)
3889 return -EINVAL;
3890
9d8b0588
DV		 3891 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3892 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3893 return -EIO;
3894 }
3895
52f843f6 3896 if (IS_GEN2(dev))
46a19188 3897 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3898 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3899 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3900 else if (IS_VALLEYVIEW(dev))
fabf6e51 3901 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3902 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3903 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3904 else
fabf6e51 3905 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3906
3907 if (ret != 0)
3908 return ret;
3909
4b584369
DL		 3910 /* none -> real source transition */
3911 if (source) {
4252fbc3
VS		 3912 struct intel_pipe_crc_entry *entries;
3913
7cd6ccff
DL		 3914 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3915 pipe_name(pipe), pipe_crc_source_name(source));
3916
3cf54b34
VS		 3917 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3918 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3919 GFP_KERNEL);
3920 if (!entries)
e5f75aca
DL		 3921 return -ENOMEM;
3922
8c740dce
PZ		 3923 /*
3924 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3925 * enabled and disabled dynamically based on package C states,
3926 * user space can't make reliable use of the CRCs, so let's just
3927 * completely disable it.
3928 */
3929 hsw_disable_ips(crtc);
3930
d538bbdf 3931 spin_lock_irq(&pipe_crc->lock);
64387b61 3932 kfree(pipe_crc->entries);
4252fbc3 3933 pipe_crc->entries = entries;
d538bbdf
DL		 3934 pipe_crc->head = 0;
3935 pipe_crc->tail = 0;
3936 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3937 }
3938
cc3da175 3939 pipe_crc->source = source;
926321d5 3940
926321d5
DV		 3941 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3942 POSTING_READ(PIPE_CRC_CTL(pipe));
3943
e5f75aca
DL		 3944 /* real source -> none transition */
3945 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3946 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3947 struct intel_crtc *crtc =
3948 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3949
7cd6ccff
DL		 3950 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3951 pipe_name(pipe));
3952
a33d7105 3953 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 3954 if (crtc->base.state->active)
a33d7105
DV		 3955 intel_wait_for_vblank(dev, pipe);
3956 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3957
d538bbdf
DL		 3958 spin_lock_irq(&pipe_crc->lock);
3959 entries = pipe_crc->entries;
e5f75aca 3960 pipe_crc->entries = NULL;
9ad6d99f
VS		 3961 pipe_crc->head = 0;
3962 pipe_crc->tail = 0;
d538bbdf
DL		 3963 spin_unlock_irq(&pipe_crc->lock);
3964
3965 kfree(entries);
84093603
DV		 3966
3967 if (IS_G4X(dev))
3968 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3969 else if (IS_VALLEYVIEW(dev))
3970 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 3971 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 3972 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 3973
3974 hsw_enable_ips(crtc);
e5f75aca
DL		 3975 }
3976
926321d5
DV		 3977 return 0;
3978}
3979
3980/*
3981 * Parse pipe CRC command strings:
b94dec87
DL		 3982 * command: wsp* object wsp+ name wsp+ source wsp*
3983 * object: 'pipe'
3984 * name: (A | B | C)
926321d5
DV		 3985 * source: (none | plane1 | plane2 | pf)
3986 * wsp: (#0x20 | #0x9 | #0xA)+
3987 *
3988 * eg.:
b94dec87
DL		 3989 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3990 * "pipe A none" -> Stop CRC
926321d5 3991 */
bd9db02f 3992static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3993{
3994 int n_words = 0;
3995
3996 while (*buf) {
3997 char *end;
3998
3999 /* skip leading white space */
4000 buf = skip_spaces(buf);
4001 if (!*buf)
4002 break; /* end of buffer */
4003
4004 /* find end of word */
4005 for (end = buf; *end && !isspace(*end); end++)
4006 ;
4007
4008 if (n_words == max_words) {
4009 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4010 max_words);
4011 return -EINVAL; /* ran out of words[] before bytes */
4012 }
4013
4014 if (*end)
4015 *end++ = '\0';
4016 words[n_words++] = buf;
4017 buf = end;
4018 }
4019
4020 return n_words;
4021}
4022
b94dec87
DL		 4023enum intel_pipe_crc_object {
4024 PIPE_CRC_OBJECT_PIPE,
4025};
4026
e8dfcf78 4027static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4028 "pipe",
4029};
4030
4031static int
bd9db02f 4032display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4033{
4034 int i;
4035
4036 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4037 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4038 *o = i;
b94dec87
DL		 4039 return 0;
4040 }
4041
4042 return -EINVAL;
4043}
4044
bd9db02f 4045static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4046{
4047 const char name = buf[0];
4048
4049 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4050 return -EINVAL;
4051
4052 *pipe = name - 'A';
4053
4054 return 0;
4055}
4056
4057static int
bd9db02f 4058display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4059{
4060 int i;
4061
4062 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4063 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4064 *s = i;
926321d5
DV		 4065 return 0;
4066 }
4067
4068 return -EINVAL;
4069}
4070
bd9db02f 4071static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 4072{
b94dec87 4073#define N_WORDS 3
926321d5 4074 int n_words;
b94dec87 4075 char *words[N_WORDS];
926321d5 4076 enum pipe pipe;
b94dec87 4077 enum intel_pipe_crc_object object;
926321d5
DV		 4078 enum intel_pipe_crc_source source;
4079
bd9db02f 4080 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4081 if (n_words != N_WORDS) {
4082 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4083 N_WORDS);
4084 return -EINVAL;
4085 }
4086
bd9db02f 4087 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4088 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4089 return -EINVAL;
4090 }
4091
bd9db02f 4092 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4093 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4094 return -EINVAL;
4095 }
4096
bd9db02f 4097 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4098 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4099 return -EINVAL;
4100 }
4101
4102 return pipe_crc_set_source(dev, pipe, source);
4103}
4104
bd9db02f
DL		 4105static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4106 size_t len, loff_t *offp)
926321d5
DV		 4107{
4108 struct seq_file *m = file->private_data;
4109 struct drm_device *dev = m->private;
4110 char *tmpbuf;
4111 int ret;
4112
4113 if (len == 0)
4114 return 0;
4115
4116 if (len > PAGE_SIZE - 1) {
4117 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4118 PAGE_SIZE);
4119 return -E2BIG;
4120 }
4121
4122 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4123 if (!tmpbuf)
4124 return -ENOMEM;
4125
4126 if (copy_from_user(tmpbuf, ubuf, len)) {
4127 ret = -EFAULT;
4128 goto out;
4129 }
4130 tmpbuf[len] = '\0';
4131
bd9db02f 4132 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4133
4134out:
4135 kfree(tmpbuf);
4136 if (ret < 0)
4137 return ret;
4138
4139 *offp += len;
4140 return len;
4141}
4142
bd9db02f 4143static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4144 .owner = THIS_MODULE,
bd9db02f 4145 .open = display_crc_ctl_open,
926321d5
DV		 4146 .read = seq_read,
4147 .llseek = seq_lseek,
4148 .release = single_release,
bd9db02f 4149 .write = display_crc_ctl_write
926321d5
DV		 4150};
4151
eb3394fa
TP		 4152static ssize_t i915_displayport_test_active_write(struct file *file,
4153 const char __user *ubuf,
4154 size_t len, loff_t *offp)
4155{
4156 char *input_buffer;
4157 int status = 0;
eb3394fa
TP		 4158 struct drm_device *dev;
4159 struct drm_connector *connector;
4160 struct list_head *connector_list;
4161 struct intel_dp *intel_dp;
4162 int val = 0;
4163
9aaffa34 4164 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4165
eb3394fa
TP		 4166 connector_list = &dev->mode_config.connector_list;
4167
4168 if (len == 0)
4169 return 0;
4170
4171 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4172 if (!input_buffer)
4173 return -ENOMEM;
4174
4175 if (copy_from_user(input_buffer, ubuf, len)) {
4176 status = -EFAULT;
4177 goto out;
4178 }
4179
4180 input_buffer[len] = '\0';
4181 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4182
4183 list_for_each_entry(connector, connector_list, head) {
4184
4185 if (connector->connector_type !=
4186 DRM_MODE_CONNECTOR_DisplayPort)
4187 continue;
4188
b8bb08ec 4189 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4190 connector->encoder != NULL) {
4191 intel_dp = enc_to_intel_dp(connector->encoder);
4192 status = kstrtoint(input_buffer, 10, &val);
4193 if (status < 0)
4194 goto out;
4195 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4196 /* To prevent erroneous activation of the compliance
4197 * testing code, only accept an actual value of 1 here
4198 */
4199 if (val == 1)
4200 intel_dp->compliance_test_active = 1;
4201 else
4202 intel_dp->compliance_test_active = 0;
4203 }
4204 }
4205out:
4206 kfree(input_buffer);
4207 if (status < 0)
4208 return status;
4209
4210 *offp += len;
4211 return len;
4212}
4213
4214static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4215{
4216 struct drm_device *dev = m->private;
4217 struct drm_connector *connector;
4218 struct list_head *connector_list = &dev->mode_config.connector_list;
4219 struct intel_dp *intel_dp;
4220
eb3394fa
TP		 4221 list_for_each_entry(connector, connector_list, head) {
4222
4223 if (connector->connector_type !=
4224 DRM_MODE_CONNECTOR_DisplayPort)
4225 continue;
4226
4227 if (connector->status == connector_status_connected &&
4228 connector->encoder != NULL) {
4229 intel_dp = enc_to_intel_dp(connector->encoder);
4230 if (intel_dp->compliance_test_active)
4231 seq_puts(m, "1");
4232 else
4233 seq_puts(m, "0");
4234 } else
4235 seq_puts(m, "0");
4236 }
4237
4238 return 0;
4239}
4240
4241static int i915_displayport_test_active_open(struct inode *inode,
4242 struct file *file)
4243{
4244 struct drm_device *dev = inode->i_private;
4245
4246 return single_open(file, i915_displayport_test_active_show, dev);
4247}
4248
4249static const struct file_operations i915_displayport_test_active_fops = {
4250 .owner = THIS_MODULE,
4251 .open = i915_displayport_test_active_open,
4252 .read = seq_read,
4253 .llseek = seq_lseek,
4254 .release = single_release,
4255 .write = i915_displayport_test_active_write
4256};
4257
4258static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4259{
4260 struct drm_device *dev = m->private;
4261 struct drm_connector *connector;
4262 struct list_head *connector_list = &dev->mode_config.connector_list;
4263 struct intel_dp *intel_dp;
4264
eb3394fa
TP		 4265 list_for_each_entry(connector, connector_list, head) {
4266
4267 if (connector->connector_type !=
4268 DRM_MODE_CONNECTOR_DisplayPort)
4269 continue;
4270
4271 if (connector->status == connector_status_connected &&
4272 connector->encoder != NULL) {
4273 intel_dp = enc_to_intel_dp(connector->encoder);
4274 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4275 } else
4276 seq_puts(m, "0");
4277 }
4278
4279 return 0;
4280}
4281static int i915_displayport_test_data_open(struct inode *inode,
4282 struct file *file)
4283{
4284 struct drm_device *dev = inode->i_private;
4285
4286 return single_open(file, i915_displayport_test_data_show, dev);
4287}
4288
4289static const struct file_operations i915_displayport_test_data_fops = {
4290 .owner = THIS_MODULE,
4291 .open = i915_displayport_test_data_open,
4292 .read = seq_read,
4293 .llseek = seq_lseek,
4294 .release = single_release
4295};
4296
4297static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4298{
4299 struct drm_device *dev = m->private;
4300 struct drm_connector *connector;
4301 struct list_head *connector_list = &dev->mode_config.connector_list;
4302 struct intel_dp *intel_dp;
4303
eb3394fa
TP		 4304 list_for_each_entry(connector, connector_list, head) {
4305
4306 if (connector->connector_type !=
4307 DRM_MODE_CONNECTOR_DisplayPort)
4308 continue;
4309
4310 if (connector->status == connector_status_connected &&
4311 connector->encoder != NULL) {
4312 intel_dp = enc_to_intel_dp(connector->encoder);
4313 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4314 } else
4315 seq_puts(m, "0");
4316 }
4317
4318 return 0;
4319}
4320
4321static int i915_displayport_test_type_open(struct inode *inode,
4322 struct file *file)
4323{
4324 struct drm_device *dev = inode->i_private;
4325
4326 return single_open(file, i915_displayport_test_type_show, dev);
4327}
4328
4329static const struct file_operations i915_displayport_test_type_fops = {
4330 .owner = THIS_MODULE,
4331 .open = i915_displayport_test_type_open,
4332 .read = seq_read,
4333 .llseek = seq_lseek,
4334 .release = single_release
4335};
4336
97e94b22 4337static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4338{
4339 struct drm_device *dev = m->private;
369a1342 4340 int level;
de38b95c
VS		 4341 int num_levels;
4342
4343 if (IS_CHERRYVIEW(dev))
4344 num_levels = 3;
4345 else if (IS_VALLEYVIEW(dev))
4346 num_levels = 1;
4347 else
4348 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4349
4350 drm_modeset_lock_all(dev);
4351
4352 for (level = 0; level < num_levels; level++) {
4353 unsigned int latency = wm[level];
4354
97e94b22
DL		 4355 /*
4356 * - WM1+ latency values in 0.5us units
de38b95c 4357 * - latencies are in us on gen9/vlv/chv
97e94b22 4358 */
de38b95c 4359 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
97e94b22
DL		 4360 latency *= 10;
4361 else if (level > 0)
369a1342
VS		 4362 latency *= 5;
4363
4364 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4365 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4366 }
4367
4368 drm_modeset_unlock_all(dev);
4369}
4370
4371static int pri_wm_latency_show(struct seq_file *m, void *data)
4372{
4373 struct drm_device *dev = m->private;
97e94b22
DL		 4374 struct drm_i915_private *dev_priv = dev->dev_private;
4375 const uint16_t *latencies;
4376
4377 if (INTEL_INFO(dev)->gen >= 9)
4378 latencies = dev_priv->wm.skl_latency;
4379 else
4380 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4381
97e94b22 4382 wm_latency_show(m, latencies);
369a1342
VS		 4383
4384 return 0;
4385}
4386
4387static int spr_wm_latency_show(struct seq_file *m, void *data)
4388{
4389 struct drm_device *dev = m->private;
97e94b22
DL		 4390 struct drm_i915_private *dev_priv = dev->dev_private;
4391 const uint16_t *latencies;
4392
4393 if (INTEL_INFO(dev)->gen >= 9)
4394 latencies = dev_priv->wm.skl_latency;
4395 else
4396 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4397
97e94b22 4398 wm_latency_show(m, latencies);
369a1342
VS		 4399
4400 return 0;
4401}
4402
4403static int cur_wm_latency_show(struct seq_file *m, void *data)
4404{
4405 struct drm_device *dev = m->private;
97e94b22
DL		 4406 struct drm_i915_private *dev_priv = dev->dev_private;
4407 const uint16_t *latencies;
4408
4409 if (INTEL_INFO(dev)->gen >= 9)
4410 latencies = dev_priv->wm.skl_latency;
4411 else
4412 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4413
97e94b22 4414 wm_latency_show(m, latencies);
369a1342
VS		 4415
4416 return 0;
4417}
4418
4419static int pri_wm_latency_open(struct inode *inode, struct file *file)
4420{
4421 struct drm_device *dev = inode->i_private;
4422
de38b95c 4423 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4424 return -ENODEV;
4425
4426 return single_open(file, pri_wm_latency_show, dev);
4427}
4428
4429static int spr_wm_latency_open(struct inode *inode, struct file *file)
4430{
4431 struct drm_device *dev = inode->i_private;
4432
9ad0257c 4433 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4434 return -ENODEV;
4435
4436 return single_open(file, spr_wm_latency_show, dev);
4437}
4438
4439static int cur_wm_latency_open(struct inode *inode, struct file *file)
4440{
4441 struct drm_device *dev = inode->i_private;
4442
9ad0257c 4443 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4444 return -ENODEV;
4445
4446 return single_open(file, cur_wm_latency_show, dev);
4447}
4448
4449static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4450 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4451{
4452 struct seq_file *m = file->private_data;
4453 struct drm_device *dev = m->private;
97e94b22 4454 uint16_t new[8] = { 0 };
de38b95c 4455 int num_levels;
369a1342
VS		 4456 int level;
4457 int ret;
4458 char tmp[32];
4459
de38b95c
VS		 4460 if (IS_CHERRYVIEW(dev))
4461 num_levels = 3;
4462 else if (IS_VALLEYVIEW(dev))
4463 num_levels = 1;
4464 else
4465 num_levels = ilk_wm_max_level(dev) + 1;
4466
369a1342
VS		 4467 if (len >= sizeof(tmp))
4468 return -EINVAL;
4469
4470 if (copy_from_user(tmp, ubuf, len))
4471 return -EFAULT;
4472
4473 tmp[len] = '\0';
4474
97e94b22
DL		 4475 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4476 &new[0], &new[1], &new[2], &new[3],
4477 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4478 if (ret != num_levels)
4479 return -EINVAL;
4480
4481 drm_modeset_lock_all(dev);
4482
4483 for (level = 0; level < num_levels; level++)
4484 wm[level] = new[level];
4485
4486 drm_modeset_unlock_all(dev);
4487
4488 return len;
4489}
4490
4491
4492static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4493 size_t len, loff_t *offp)
4494{
4495 struct seq_file *m = file->private_data;
4496 struct drm_device *dev = m->private;
97e94b22
DL		 4497 struct drm_i915_private *dev_priv = dev->dev_private;
4498 uint16_t *latencies;
369a1342 4499
97e94b22
DL		 4500 if (INTEL_INFO(dev)->gen >= 9)
4501 latencies = dev_priv->wm.skl_latency;
4502 else
4503 latencies = to_i915(dev)->wm.pri_latency;
4504
4505 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4506}
4507
4508static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4509 size_t len, loff_t *offp)
4510{
4511 struct seq_file *m = file->private_data;
4512 struct drm_device *dev = m->private;
97e94b22
DL		 4513 struct drm_i915_private *dev_priv = dev->dev_private;
4514 uint16_t *latencies;
369a1342 4515
97e94b22
DL		 4516 if (INTEL_INFO(dev)->gen >= 9)
4517 latencies = dev_priv->wm.skl_latency;
4518 else
4519 latencies = to_i915(dev)->wm.spr_latency;
4520
4521 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4522}
4523
4524static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4525 size_t len, loff_t *offp)
4526{
4527 struct seq_file *m = file->private_data;
4528 struct drm_device *dev = m->private;
97e94b22
DL		 4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 uint16_t *latencies;
4531
4532 if (INTEL_INFO(dev)->gen >= 9)
4533 latencies = dev_priv->wm.skl_latency;
4534 else
4535 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4536
97e94b22 4537 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4538}
4539
4540static const struct file_operations i915_pri_wm_latency_fops = {
4541 .owner = THIS_MODULE,
4542 .open = pri_wm_latency_open,
4543 .read = seq_read,
4544 .llseek = seq_lseek,
4545 .release = single_release,
4546 .write = pri_wm_latency_write
4547};
4548
4549static const struct file_operations i915_spr_wm_latency_fops = {
4550 .owner = THIS_MODULE,
4551 .open = spr_wm_latency_open,
4552 .read = seq_read,
4553 .llseek = seq_lseek,
4554 .release = single_release,
4555 .write = spr_wm_latency_write
4556};
4557
4558static const struct file_operations i915_cur_wm_latency_fops = {
4559 .owner = THIS_MODULE,
4560 .open = cur_wm_latency_open,
4561 .read = seq_read,
4562 .llseek = seq_lseek,
4563 .release = single_release,
4564 .write = cur_wm_latency_write
4565};
4566
647416f9
KC		 4567static int
4568i915_wedged_get(void *data, u64 *val)
f3cd474b 4569{
647416f9 4570 struct drm_device *dev = data;
e277a1f8 4571 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4572
647416f9 4573 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4574
647416f9 4575 return 0;
f3cd474b
CW		 4576}
4577
647416f9
KC		 4578static int
4579i915_wedged_set(void *data, u64 val)
f3cd474b 4580{
647416f9 4581 struct drm_device *dev = data;
d46c0517
ID		 4582 struct drm_i915_private *dev_priv = dev->dev_private;
4583
b8d24a06
MK		 4584 /*
4585 * There is no safeguard against this debugfs entry colliding
4586 * with the hangcheck calling same i915_handle_error() in
4587 * parallel, causing an explosion. For now we assume that the
4588 * test harness is responsible enough not to inject gpu hangs
4589 * while it is writing to 'i915_wedged'
4590 */
4591
4592 if (i915_reset_in_progress(&dev_priv->gpu_error))
4593 return -EAGAIN;
4594
d46c0517 4595 intel_runtime_pm_get(dev_priv);
f3cd474b 4596
58174462
MK		 4597 i915_handle_error(dev, val,
4598 "Manually setting wedged to %llu", val);
d46c0517
ID		 4599
4600 intel_runtime_pm_put(dev_priv);
4601
647416f9 4602 return 0;
f3cd474b
CW		 4603}
4604
647416f9
KC		 4605DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4606 i915_wedged_get, i915_wedged_set,
3a3b4f98 4607 "%llu\n");
f3cd474b 4608
647416f9
KC		 4609static int
4610i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4611{
647416f9 4612 struct drm_device *dev = data;
e277a1f8 4613 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4614
647416f9 4615 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4616
647416f9 4617 return 0;
e5eb3d63
DV		 4618}
4619
647416f9
KC		 4620static int
4621i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4622{
647416f9 4623 struct drm_device *dev = data;
e5eb3d63 4624 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4625 int ret;
e5eb3d63 4626
647416f9 4627 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4628
22bcfc6a
DV		 4629 ret = mutex_lock_interruptible(&dev->struct_mutex);
4630 if (ret)
4631 return ret;
4632
99584db3 4633 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4634 mutex_unlock(&dev->struct_mutex);
4635
647416f9 4636 return 0;
e5eb3d63
DV		 4637}
4638
647416f9
KC		 4639DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4640 i915_ring_stop_get, i915_ring_stop_set,
4641 "0x%08llx\n");
d5442303 4642
094f9a54
CW		 4643static int
4644i915_ring_missed_irq_get(void *data, u64 *val)
4645{
4646 struct drm_device *dev = data;
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648
4649 *val = dev_priv->gpu_error.missed_irq_rings;
4650 return 0;
4651}
4652
4653static int
4654i915_ring_missed_irq_set(void *data, u64 val)
4655{
4656 struct drm_device *dev = data;
4657 struct drm_i915_private *dev_priv = dev->dev_private;
4658 int ret;
4659
4660 /* Lock against concurrent debugfs callers */
4661 ret = mutex_lock_interruptible(&dev->struct_mutex);
4662 if (ret)
4663 return ret;
4664 dev_priv->gpu_error.missed_irq_rings = val;
4665 mutex_unlock(&dev->struct_mutex);
4666
4667 return 0;
4668}
4669
4670DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4671 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4672 "0x%08llx\n");
4673
4674static int
4675i915_ring_test_irq_get(void *data, u64 *val)
4676{
4677 struct drm_device *dev = data;
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4679
4680 *val = dev_priv->gpu_error.test_irq_rings;
4681
4682 return 0;
4683}
4684
4685static int
4686i915_ring_test_irq_set(void *data, u64 val)
4687{
4688 struct drm_device *dev = data;
4689 struct drm_i915_private *dev_priv = dev->dev_private;
4690 int ret;
4691
4692 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4693
4694 /* Lock against concurrent debugfs callers */
4695 ret = mutex_lock_interruptible(&dev->struct_mutex);
4696 if (ret)
4697 return ret;
4698
4699 dev_priv->gpu_error.test_irq_rings = val;
4700 mutex_unlock(&dev->struct_mutex);
4701
4702 return 0;
4703}
4704
4705DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4706 i915_ring_test_irq_get, i915_ring_test_irq_set,
4707 "0x%08llx\n");
4708
dd624afd
CW		 4709#define DROP_UNBOUND 0x1
4710#define DROP_BOUND 0x2
4711#define DROP_RETIRE 0x4
4712#define DROP_ACTIVE 0x8
4713#define DROP_ALL (DROP_UNBOUND | \
4714 DROP_BOUND | \
4715 DROP_RETIRE | \
4716 DROP_ACTIVE)
647416f9
KC		 4717static int
4718i915_drop_caches_get(void *data, u64 *val)
dd624afd 4719{
647416f9 4720 *val = DROP_ALL;
dd624afd 4721
647416f9 4722 return 0;
dd624afd
CW		 4723}
4724
647416f9
KC		 4725static int
4726i915_drop_caches_set(void *data, u64 val)
dd624afd 4727{
647416f9 4728 struct drm_device *dev = data;
dd624afd 4729 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4730 int ret;
dd624afd 4731
2f9fe5ff 4732 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4733
4734 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4735 * on ioctls on -EAGAIN. */
4736 ret = mutex_lock_interruptible(&dev->struct_mutex);
4737 if (ret)
4738 return ret;
4739
4740 if (val & DROP_ACTIVE) {
4741 ret = i915_gpu_idle(dev);
4742 if (ret)
4743 goto unlock;
4744 }
4745
4746 if (val & (DROP_RETIRE | DROP_ACTIVE))
4747 i915_gem_retire_requests(dev);
4748
21ab4e74
CW		 4749 if (val & DROP_BOUND)
4750 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4751
21ab4e74
CW		 4752 if (val & DROP_UNBOUND)
4753 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4754
4755unlock:
4756 mutex_unlock(&dev->struct_mutex);
4757
647416f9 4758 return ret;
dd624afd
CW		 4759}
4760
647416f9
KC		 4761DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4762 i915_drop_caches_get, i915_drop_caches_set,
4763 "0x%08llx\n");
dd624afd 4764
647416f9
KC		 4765static int
4766i915_max_freq_get(void *data, u64 *val)
358733e9 4767{
647416f9 4768 struct drm_device *dev = data;
e277a1f8 4769 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4770 int ret;
004777cb 4771
daa3afb2 4772 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4773 return -ENODEV;
4774
5c9669ce
TR		 4775 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4776
4fc688ce 4777 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4778 if (ret)
4779 return ret;
358733e9 4780
7c59a9c1 4781 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4782 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4783
647416f9 4784 return 0;
358733e9
JB		 4785}
4786
647416f9
KC		 4787static int
4788i915_max_freq_set(void *data, u64 val)
358733e9 4789{
647416f9 4790 struct drm_device *dev = data;
358733e9 4791 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4792 u32 hw_max, hw_min;
647416f9 4793 int ret;
004777cb 4794
daa3afb2 4795 if (INTEL_INFO(dev)->gen < 6)
004777cb 4796 return -ENODEV;
358733e9 4797
5c9669ce
TR		 4798 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4799
647416f9 4800 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4801
4fc688ce 4802 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4803 if (ret)
4804 return ret;
4805
358733e9
JB		 4806 /*
4807 * Turbo will still be enabled, but won't go above the set value.
4808 */
bc4d91f6 4809 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4810
bc4d91f6
AG		 4811 hw_max = dev_priv->rps.max_freq;
4812 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4813
b39fb297 4814 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4815 mutex_unlock(&dev_priv->rps.hw_lock);
4816 return -EINVAL;
0a073b84
JB		 4817 }
4818
b39fb297 4819 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4820
ffe02b40 4821 intel_set_rps(dev, val);
dd0a1aa1 4822
4fc688ce 4823 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4824
647416f9 4825 return 0;
358733e9
JB		 4826}
4827
647416f9
KC		 4828DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4829 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4830 "%llu\n");
358733e9 4831
647416f9
KC		 4832static int
4833i915_min_freq_get(void *data, u64 *val)
1523c310 4834{
647416f9 4835 struct drm_device *dev = data;
e277a1f8 4836 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4837 int ret;
004777cb 4838
daa3afb2 4839 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4840 return -ENODEV;
4841
5c9669ce
TR		 4842 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4843
4fc688ce 4844 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4845 if (ret)
4846 return ret;
1523c310 4847
7c59a9c1 4848 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4849 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4850
647416f9 4851 return 0;
1523c310
JB		 4852}
4853
647416f9
KC		 4854static int
4855i915_min_freq_set(void *data, u64 val)
1523c310 4856{
647416f9 4857 struct drm_device *dev = data;
1523c310 4858 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4859 u32 hw_max, hw_min;
647416f9 4860 int ret;
004777cb 4861
daa3afb2 4862 if (INTEL_INFO(dev)->gen < 6)
004777cb 4863 return -ENODEV;
1523c310 4864
5c9669ce
TR		 4865 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4866
647416f9 4867 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4868
4fc688ce 4869 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4870 if (ret)
4871 return ret;
4872
1523c310
JB		 4873 /*
4874 * Turbo will still be enabled, but won't go below the set value.
4875 */
bc4d91f6 4876 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4877
bc4d91f6
AG		 4878 hw_max = dev_priv->rps.max_freq;
4879 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4880
b39fb297 4881 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4882 mutex_unlock(&dev_priv->rps.hw_lock);
4883 return -EINVAL;
0a073b84 4884 }
dd0a1aa1 4885
b39fb297 4886 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4887
ffe02b40 4888 intel_set_rps(dev, val);
dd0a1aa1 4889
4fc688ce 4890 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4891
647416f9 4892 return 0;
1523c310
JB		 4893}
4894
647416f9
KC		 4895DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4896 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4897 "%llu\n");
1523c310 4898
647416f9
KC		 4899static int
4900i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4901{
647416f9 4902 struct drm_device *dev = data;
e277a1f8 4903 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4904 u32 snpcr;
647416f9 4905 int ret;
07b7ddd9 4906
004777cb
DV		 4907 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4908 return -ENODEV;
4909
22bcfc6a
DV		 4910 ret = mutex_lock_interruptible(&dev->struct_mutex);
4911 if (ret)
4912 return ret;
c8c8fb33 4913 intel_runtime_pm_get(dev_priv);
22bcfc6a 4914
07b7ddd9 4915 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4916
4917 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4918 mutex_unlock(&dev_priv->dev->struct_mutex);
4919
647416f9 4920 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4921
647416f9 4922 return 0;
07b7ddd9
JB		 4923}
4924
647416f9
KC		 4925static int
4926i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4927{
647416f9 4928 struct drm_device *dev = data;
07b7ddd9 4929 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4930 u32 snpcr;
07b7ddd9 4931
004777cb
DV		 4932 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4933 return -ENODEV;
4934
647416f9 4935 if (val > 3)
07b7ddd9
JB		 4936 return -EINVAL;
4937
c8c8fb33 4938 intel_runtime_pm_get(dev_priv);
647416f9 4939 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4940
4941 /* Update the cache sharing policy here as well */
4942 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4943 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4944 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4945 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4946
c8c8fb33 4947 intel_runtime_pm_put(dev_priv);
647416f9 4948 return 0;
07b7ddd9
JB		 4949}
4950
647416f9
KC		 4951DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4952 i915_cache_sharing_get, i915_cache_sharing_set,
4953 "%llu\n");
07b7ddd9 4954
5d39525a
JM		 4955struct sseu_dev_status {
4956 unsigned int slice_total;
4957 unsigned int subslice_total;
4958 unsigned int subslice_per_slice;
4959 unsigned int eu_total;
4960 unsigned int eu_per_subslice;
4961};
4962
4963static void cherryview_sseu_device_status(struct drm_device *dev,
4964 struct sseu_dev_status *stat)
4965{
4966 struct drm_i915_private *dev_priv = dev->dev_private;
0a0b457f 4967 int ss_max = 2;
5d39525a
JM		 4968 int ss;
4969 u32 sig1[ss_max], sig2[ss_max];
4970
4971 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4972 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4973 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4974 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4975
4976 for (ss = 0; ss < ss_max; ss++) {
4977 unsigned int eu_cnt;
4978
4979 if (sig1[ss] & CHV_SS_PG_ENABLE)
4980 /* skip disabled subslice */
4981 continue;
4982
4983 stat->slice_total = 1;
4984 stat->subslice_per_slice++;
4985 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4986 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4987 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4988 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4989 stat->eu_total += eu_cnt;
4990 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4991 }
4992 stat->subslice_total = stat->subslice_per_slice;
4993}
4994
4995static void gen9_sseu_device_status(struct drm_device *dev,
4996 struct sseu_dev_status *stat)
4997{
4998 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 4999 int s_max = 3, ss_max = 4;
5d39525a
JM		 5000 int s, ss;
5001 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5002
1c046bc1
JM		 5003 /* BXT has a single slice and at most 3 subslices. */
5004 if (IS_BROXTON(dev)) {
5005 s_max = 1;
5006 ss_max = 3;
5007 }
5008
5009 for (s = 0; s < s_max; s++) {
5010 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5011 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5012 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5013 }
5014
5d39525a
JM		 5015 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5016 GEN9_PGCTL_SSA_EU19_ACK |
5017 GEN9_PGCTL_SSA_EU210_ACK |
5018 GEN9_PGCTL_SSA_EU311_ACK;
5019 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5020 GEN9_PGCTL_SSB_EU19_ACK |
5021 GEN9_PGCTL_SSB_EU210_ACK |
5022 GEN9_PGCTL_SSB_EU311_ACK;
5023
5024 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 5025 unsigned int ss_cnt = 0;
5026
5d39525a
JM		 5027 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5028 /* skip disabled slice */
5029 continue;
5030
5031 stat->slice_total++;
1c046bc1
JM		 5032
5033 if (IS_SKYLAKE(dev))
5034 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5035
5d39525a
JM		 5036 for (ss = 0; ss < ss_max; ss++) {
5037 unsigned int eu_cnt;
5038
1c046bc1
JM		 5039 if (IS_BROXTON(dev) &&
5040 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5041 /* skip disabled subslice */
5042 continue;
5043
5044 if (IS_BROXTON(dev))
5045 ss_cnt++;
5046
5d39525a
JM		 5047 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5048 eu_mask[ss%2]);
5049 stat->eu_total += eu_cnt;
5050 stat->eu_per_subslice = max(stat->eu_per_subslice,
5051 eu_cnt);
5052 }
1c046bc1
JM		 5053
5054 stat->subslice_total += ss_cnt;
5055 stat->subslice_per_slice = max(stat->subslice_per_slice,
5056 ss_cnt);
5d39525a
JM		 5057 }
5058}
5059
91bedd34
ŁD		 5060static void broadwell_sseu_device_status(struct drm_device *dev,
5061 struct sseu_dev_status *stat)
5062{
5063 struct drm_i915_private *dev_priv = dev->dev_private;
5064 int s;
5065 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5066
5067 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5068
5069 if (stat->slice_total) {
5070 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5071 stat->subslice_total = stat->slice_total *
5072 stat->subslice_per_slice;
5073 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5074 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5075
5076 /* subtract fused off EU(s) from enabled slice(s) */
5077 for (s = 0; s < stat->slice_total; s++) {
5078 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5079
5080 stat->eu_total -= hweight8(subslice_7eu);
5081 }
5082 }
5083}
5084
3873218f
JM		 5085static int i915_sseu_status(struct seq_file *m, void *unused)
5086{
5087 struct drm_info_node *node = (struct drm_info_node *) m->private;
5088 struct drm_device *dev = node->minor->dev;
5d39525a 5089 struct sseu_dev_status stat;
3873218f 5090
91bedd34 5091 if (INTEL_INFO(dev)->gen < 8)
3873218f
JM		 5092 return -ENODEV;
5093
5094 seq_puts(m, "SSEU Device Info\n");
5095 seq_printf(m, " Available Slice Total: %u\n",
5096 INTEL_INFO(dev)->slice_total);
5097 seq_printf(m, " Available Subslice Total: %u\n",
5098 INTEL_INFO(dev)->subslice_total);
5099 seq_printf(m, " Available Subslice Per Slice: %u\n",
5100 INTEL_INFO(dev)->subslice_per_slice);
5101 seq_printf(m, " Available EU Total: %u\n",
5102 INTEL_INFO(dev)->eu_total);
5103 seq_printf(m, " Available EU Per Subslice: %u\n",
5104 INTEL_INFO(dev)->eu_per_subslice);
5105 seq_printf(m, " Has Slice Power Gating: %s\n",
5106 yesno(INTEL_INFO(dev)->has_slice_pg));
5107 seq_printf(m, " Has Subslice Power Gating: %s\n",
5108 yesno(INTEL_INFO(dev)->has_subslice_pg));
5109 seq_printf(m, " Has EU Power Gating: %s\n",
5110 yesno(INTEL_INFO(dev)->has_eu_pg));
5111
7f992aba 5112 seq_puts(m, "SSEU Device Status\n");
5d39525a 5113 memset(&stat, 0, sizeof(stat));
5575f03a 5114 if (IS_CHERRYVIEW(dev)) {
5d39525a 5115 cherryview_sseu_device_status(dev, &stat);
91bedd34
ŁD		 5116 } else if (IS_BROADWELL(dev)) {
5117 broadwell_sseu_device_status(dev, &stat);
1c046bc1 5118 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 5119 gen9_sseu_device_status(dev, &stat);
7f992aba 5120 }
5d39525a
JM		 5121 seq_printf(m, " Enabled Slice Total: %u\n",
5122 stat.slice_total);
5123 seq_printf(m, " Enabled Subslice Total: %u\n",
5124 stat.subslice_total);
5125 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5126 stat.subslice_per_slice);
5127 seq_printf(m, " Enabled EU Total: %u\n",
5128 stat.eu_total);
5129 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5130 stat.eu_per_subslice);
7f992aba 5131
3873218f
JM		 5132 return 0;
5133}
5134
6d794d42
BW		 5135static int i915_forcewake_open(struct inode *inode, struct file *file)
5136{
5137 struct drm_device *dev = inode->i_private;
5138 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 5139
075edca4 5140 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5141 return 0;
5142
6daccb0b 5143 intel_runtime_pm_get(dev_priv);
59bad947 5144 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5145
5146 return 0;
5147}
5148
c43b5634 5149static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5150{
5151 struct drm_device *dev = inode->i_private;
5152 struct drm_i915_private *dev_priv = dev->dev_private;
5153
075edca4 5154 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5155 return 0;
5156
59bad947 5157 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5158 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5159
5160 return 0;
5161}
5162
5163static const struct file_operations i915_forcewake_fops = {
5164 .owner = THIS_MODULE,
5165 .open = i915_forcewake_open,
5166 .release = i915_forcewake_release,
5167};
5168
5169static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5170{
5171 struct drm_device *dev = minor->dev;
5172 struct dentry *ent;
5173
5174 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5175 S_IRUSR,
6d794d42
BW		 5176 root, dev,
5177 &i915_forcewake_fops);
f3c5fe97
WY		 5178 if (!ent)
5179 return -ENOMEM;
6d794d42 5180
8eb57294 5181 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5182}
5183
6a9c308d
DV		 5184static int i915_debugfs_create(struct dentry *root,
5185 struct drm_minor *minor,
5186 const char *name,
5187 const struct file_operations *fops)
07b7ddd9
JB		 5188{
5189 struct drm_device *dev = minor->dev;
5190 struct dentry *ent;
5191
6a9c308d 5192 ent = debugfs_create_file(name,
07b7ddd9
JB		 5193 S_IRUGO | S_IWUSR,
5194 root, dev,
6a9c308d 5195 fops);
f3c5fe97
WY		 5196 if (!ent)
5197 return -ENOMEM;
07b7ddd9 5198
6a9c308d 5199 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5200}
5201
06c5bf8c 5202static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5203 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5204 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5205 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5206 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5207 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5208 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5209 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5210 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5211 {"i915_gem_request", i915_gem_request_info, 0},
5212 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5213 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5214 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5215 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5216 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5217 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5218 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5219 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5220 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5221 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5222 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5223 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5224 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5225 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5226 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5227 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5228 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5229 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5230 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5231 {"i915_sr_status", i915_sr_status, 0},
44834a67 5232 {"i915_opregion", i915_opregion, 0},
37811fcc 5233 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5234 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5235 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5236 {"i915_execlists", i915_execlists, 0},
f65367b5 5237 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5238 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5239 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5240 {"i915_llc", i915_llc, 0},
e91fd8c6 5241 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5242 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5243 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5244 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5245 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 5246 {"i915_display_info", i915_display_info, 0},
e04934cf 5247 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5248 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5249 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5250 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5251 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5252 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5253 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5254 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5255};
27c202ad 5256#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5257
06c5bf8c 5258static const struct i915_debugfs_files {
34b9674c
DV		 5259 const char *name;
5260 const struct file_operations *fops;
5261} i915_debugfs_files[] = {
5262 {"i915_wedged", &i915_wedged_fops},
5263 {"i915_max_freq", &i915_max_freq_fops},
5264 {"i915_min_freq", &i915_min_freq_fops},
5265 {"i915_cache_sharing", &i915_cache_sharing_fops},
5266 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5267 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5268 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5269 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5270 {"i915_error_state", &i915_error_state_fops},
5271 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5272 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5273 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5274 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5275 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5276 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5277 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5278 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5279 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5280};
5281
07144428
DL		 5282void intel_display_crc_init(struct drm_device *dev)
5283{
5284 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5285 enum pipe pipe;
07144428 5286
055e393f 5287 for_each_pipe(dev_priv, pipe) {
b378360e 5288 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5289
d538bbdf
DL		 5290 pipe_crc->opened = false;
5291 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5292 init_waitqueue_head(&pipe_crc->wq);
5293 }
5294}
5295
27c202ad 5296int i915_debugfs_init(struct drm_minor *minor)
2017263e 5297{
34b9674c 5298 int ret, i;
f3cd474b 5299
6d794d42 5300 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5301 if (ret)
5302 return ret;
6a9c308d 5303
07144428
DL		 5304 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5305 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5306 if (ret)
5307 return ret;
5308 }
5309
34b9674c
DV		 5310 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5311 ret = i915_debugfs_create(minor->debugfs_root, minor,
5312 i915_debugfs_files[i].name,
5313 i915_debugfs_files[i].fops);
5314 if (ret)
5315 return ret;
5316 }
40633219 5317
27c202ad
BG		 5318 return drm_debugfs_create_files(i915_debugfs_list,
5319 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5320 minor->debugfs_root, minor);
5321}
5322
27c202ad 5323void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5324{
34b9674c
DV		 5325 int i;
5326
27c202ad
BG		 5327 drm_debugfs_remove_files(i915_debugfs_list,
5328 I915_DEBUGFS_ENTRIES, minor);
07144428 5329
6d794d42
BW		 5330 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5331 1, minor);
07144428 5332
e309a997 5333 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5334 struct drm_info_list *info_list =
5335 (struct drm_info_list *)&i915_pipe_crc_data[i];
5336
5337 drm_debugfs_remove_files(info_list, 1, minor);
5338 }
5339
34b9674c
DV		 5340 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5341 struct drm_info_list *info_list =
5342 (struct drm_info_list *) i915_debugfs_files[i].fops;
5343
5344 drm_debugfs_remove_files(info_list, 1, minor);
5345 }
2017263e 5346}
aa7471d2
JN		 5347
5348struct dpcd_block {
5349 /* DPCD dump start address. */
5350 unsigned int offset;
5351 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5352 unsigned int end;
5353 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5354 size_t size;
5355 /* Only valid for eDP. */
5356 bool edp;
5357};
5358
5359static const struct dpcd_block i915_dpcd_debug[] = {
5360 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5361 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5362 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5363 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5364 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5365 { .offset = DP_SET_POWER },
5366 { .offset = DP_EDP_DPCD_REV },
5367 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5368 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5369 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5370};
5371
5372static int i915_dpcd_show(struct seq_file *m, void *data)
5373{
5374 struct drm_connector *connector = m->private;
5375 struct intel_dp *intel_dp =
5376 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5377 uint8_t buf[16];
5378 ssize_t err;
5379 int i;
5380
5c1a8875
MK		 5381 if (connector->status != connector_status_connected)
5382 return -ENODEV;
5383
aa7471d2
JN		 5384 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5385 const struct dpcd_block *b = &i915_dpcd_debug[i];
5386 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5387
5388 if (b->edp &&
5389 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5390 continue;
5391
5392 /* low tech for now */
5393 if (WARN_ON(size > sizeof(buf)))
5394 continue;
5395
5396 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5397 if (err <= 0) {
5398 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5399 size, b->offset, err);
5400 continue;
5401 }
5402
5403 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5404 }
aa7471d2
JN		 5405
5406 return 0;
5407}
5408
5409static int i915_dpcd_open(struct inode *inode, struct file *file)
5410{
5411 return single_open(file, i915_dpcd_show, inode->i_private);
5412}
5413
5414static const struct file_operations i915_dpcd_fops = {
5415 .owner = THIS_MODULE,
5416 .open = i915_dpcd_open,
5417 .read = seq_read,
5418 .llseek = seq_lseek,
5419 .release = single_release,
5420};
5421
5422/**
5423 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5424 * @connector: pointer to a registered drm_connector
5425 *
5426 * Cleanup will be done by drm_connector_unregister() through a call to
5427 * drm_debugfs_connector_remove().
5428 *
5429 * Returns 0 on success, negative error codes on error.
5430 */
5431int i915_debugfs_connector_add(struct drm_connector *connector)
5432{
5433 struct dentry *root = connector->debugfs_entry;
5434
5435 /* The connector must have been registered beforehands. */
5436 if (!root)
5437 return -ENODEV;
5438
5439 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5440 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5441 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5442 &i915_dpcd_fops);
5443
5444 return 0;
5445}
Linux kernel - Deliverables
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