Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
70d39fe4 CW |
49 | static const char *yesno(int v) |
50 | { | |
51 | return v ? "yes" : "no"; | |
52 | } | |
53 | ||
497666d8 DL |
54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
55 | * allocated we need to hook into the minor for release. */ | |
56 | static int | |
57 | drm_add_fake_info_node(struct drm_minor *minor, | |
58 | struct dentry *ent, | |
59 | const void *key) | |
60 | { | |
61 | struct drm_info_node *node; | |
62 | ||
63 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
64 | if (node == NULL) { | |
65 | debugfs_remove(ent); | |
66 | return -ENOMEM; | |
67 | } | |
68 | ||
69 | node->minor = minor; | |
70 | node->dent = ent; | |
71 | node->info_ent = (void *) key; | |
72 | ||
73 | mutex_lock(&minor->debugfs_lock); | |
74 | list_add(&node->list, &minor->debugfs_list); | |
75 | mutex_unlock(&minor->debugfs_lock); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
70d39fe4 CW |
80 | static int i915_capabilities(struct seq_file *m, void *data) |
81 | { | |
9f25d007 | 82 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
83 | struct drm_device *dev = node->minor->dev; |
84 | const struct intel_device_info *info = INTEL_INFO(dev); | |
85 | ||
86 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
89 | #define SEP_SEMICOLON ; | |
90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
91 | #undef PRINT_FLAG | |
92 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
93 | |
94 | return 0; | |
95 | } | |
2017263e | 96 | |
05394f39 | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 98 | { |
05394f39 | 99 | if (obj->user_pin_count > 0) |
a6172a80 | 100 | return "P"; |
d7f46fc4 | 101 | else if (i915_gem_obj_is_pinned(obj)) |
a6172a80 CW |
102 | return "p"; |
103 | else | |
104 | return " "; | |
105 | } | |
106 | ||
05394f39 | 107 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 108 | { |
0206e353 AJ |
109 | switch (obj->tiling_mode) { |
110 | default: | |
111 | case I915_TILING_NONE: return " "; | |
112 | case I915_TILING_X: return "X"; | |
113 | case I915_TILING_Y: return "Y"; | |
114 | } | |
a6172a80 CW |
115 | } |
116 | ||
1d693bcc BW |
117 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
118 | { | |
119 | return obj->has_global_gtt_mapping ? "g" : " "; | |
120 | } | |
121 | ||
37811fcc CW |
122 | static void |
123 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
124 | { | |
1d693bcc | 125 | struct i915_vma *vma; |
d7f46fc4 BW |
126 | int pin_count = 0; |
127 | ||
fb1ae911 | 128 | seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", |
37811fcc CW |
129 | &obj->base, |
130 | get_pin_flag(obj), | |
131 | get_tiling_flag(obj), | |
1d693bcc | 132 | get_global_flag(obj), |
a05a5862 | 133 | obj->base.size / 1024, |
37811fcc CW |
134 | obj->base.read_domains, |
135 | obj->base.write_domain, | |
0201f1ec CW |
136 | obj->last_read_seqno, |
137 | obj->last_write_seqno, | |
caea7476 | 138 | obj->last_fenced_seqno, |
84734a04 | 139 | i915_cache_level_str(obj->cache_level), |
37811fcc CW |
140 | obj->dirty ? " dirty" : "", |
141 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
142 | if (obj->base.name) | |
143 | seq_printf(m, " (name: %d)", obj->base.name); | |
d7f46fc4 BW |
144 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
145 | if (vma->pin_count > 0) | |
146 | pin_count++; | |
147 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
148 | if (obj->pin_display) |
149 | seq_printf(m, " (display)"); | |
37811fcc CW |
150 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
151 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc BW |
152 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
153 | if (!i915_is_ggtt(vma->vm)) | |
154 | seq_puts(m, " (pp"); | |
155 | else | |
156 | seq_puts(m, " (g"); | |
157 | seq_printf(m, "gtt offset: %08lx, size: %08lx)", | |
158 | vma->node.start, vma->node.size); | |
159 | } | |
c1ad11fc CW |
160 | if (obj->stolen) |
161 | seq_printf(m, " (stolen: %08lx)", obj->stolen->start); | |
6299f992 CW |
162 | if (obj->pin_mappable || obj->fault_mappable) { |
163 | char s[3], *t = s; | |
164 | if (obj->pin_mappable) | |
165 | *t++ = 'p'; | |
166 | if (obj->fault_mappable) | |
167 | *t++ = 'f'; | |
168 | *t = '\0'; | |
169 | seq_printf(m, " (%s mappable)", s); | |
170 | } | |
69dc4987 CW |
171 | if (obj->ring != NULL) |
172 | seq_printf(m, " (%s)", obj->ring->name); | |
37811fcc CW |
173 | } |
174 | ||
273497e5 | 175 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
3ccfd19d BW |
176 | { |
177 | seq_putc(m, ctx->is_initialized ? 'I' : 'i'); | |
178 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); | |
179 | seq_putc(m, ' '); | |
180 | } | |
181 | ||
433e12f7 | 182 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e | 183 | { |
9f25d007 | 184 | struct drm_info_node *node = m->private; |
433e12f7 BG |
185 | uintptr_t list = (uintptr_t) node->info_ent->data; |
186 | struct list_head *head; | |
2017263e | 187 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
188 | struct drm_i915_private *dev_priv = dev->dev_private; |
189 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 190 | struct i915_vma *vma; |
8f2480fb CW |
191 | size_t total_obj_size, total_gtt_size; |
192 | int count, ret; | |
de227ef0 CW |
193 | |
194 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
195 | if (ret) | |
196 | return ret; | |
2017263e | 197 | |
ca191b13 | 198 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
199 | switch (list) { |
200 | case ACTIVE_LIST: | |
267f0c90 | 201 | seq_puts(m, "Active:\n"); |
5cef07e1 | 202 | head = &vm->active_list; |
433e12f7 BG |
203 | break; |
204 | case INACTIVE_LIST: | |
267f0c90 | 205 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 206 | head = &vm->inactive_list; |
433e12f7 | 207 | break; |
433e12f7 | 208 | default: |
de227ef0 CW |
209 | mutex_unlock(&dev->struct_mutex); |
210 | return -EINVAL; | |
2017263e | 211 | } |
2017263e | 212 | |
8f2480fb | 213 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
214 | list_for_each_entry(vma, head, mm_list) { |
215 | seq_printf(m, " "); | |
216 | describe_obj(m, vma->obj); | |
217 | seq_printf(m, "\n"); | |
218 | total_obj_size += vma->obj->base.size; | |
219 | total_gtt_size += vma->node.size; | |
8f2480fb | 220 | count++; |
2017263e | 221 | } |
de227ef0 | 222 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 223 | |
8f2480fb CW |
224 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
225 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
226 | return 0; |
227 | } | |
228 | ||
6d2b8885 CW |
229 | static int obj_rank_by_stolen(void *priv, |
230 | struct list_head *A, struct list_head *B) | |
231 | { | |
232 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 233 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 234 | struct drm_i915_gem_object *b = |
b25cb2f8 | 235 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
236 | |
237 | return a->stolen->start - b->stolen->start; | |
238 | } | |
239 | ||
240 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
241 | { | |
9f25d007 | 242 | struct drm_info_node *node = m->private; |
6d2b8885 CW |
243 | struct drm_device *dev = node->minor->dev; |
244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
245 | struct drm_i915_gem_object *obj; | |
246 | size_t total_obj_size, total_gtt_size; | |
247 | LIST_HEAD(stolen); | |
248 | int count, ret; | |
249 | ||
250 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
251 | if (ret) | |
252 | return ret; | |
253 | ||
254 | total_obj_size = total_gtt_size = count = 0; | |
255 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
256 | if (obj->stolen == NULL) | |
257 | continue; | |
258 | ||
b25cb2f8 | 259 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
260 | |
261 | total_obj_size += obj->base.size; | |
262 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
263 | count++; | |
264 | } | |
265 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
266 | if (obj->stolen == NULL) | |
267 | continue; | |
268 | ||
b25cb2f8 | 269 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
270 | |
271 | total_obj_size += obj->base.size; | |
272 | count++; | |
273 | } | |
274 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
275 | seq_puts(m, "Stolen:\n"); | |
276 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 277 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
278 | seq_puts(m, " "); |
279 | describe_obj(m, obj); | |
280 | seq_putc(m, '\n'); | |
b25cb2f8 | 281 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
282 | } |
283 | mutex_unlock(&dev->struct_mutex); | |
284 | ||
285 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
286 | count, total_obj_size, total_gtt_size); | |
287 | return 0; | |
288 | } | |
289 | ||
6299f992 CW |
290 | #define count_objects(list, member) do { \ |
291 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 292 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
293 | ++count; \ |
294 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 295 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
296 | ++mappable_count; \ |
297 | } \ | |
298 | } \ | |
0206e353 | 299 | } while (0) |
6299f992 | 300 | |
2db8e9d6 | 301 | struct file_stats { |
6313c204 | 302 | struct drm_i915_file_private *file_priv; |
2db8e9d6 | 303 | int count; |
c67a17e9 CW |
304 | size_t total, unbound; |
305 | size_t global, shared; | |
306 | size_t active, inactive; | |
2db8e9d6 CW |
307 | }; |
308 | ||
309 | static int per_file_stats(int id, void *ptr, void *data) | |
310 | { | |
311 | struct drm_i915_gem_object *obj = ptr; | |
312 | struct file_stats *stats = data; | |
6313c204 | 313 | struct i915_vma *vma; |
2db8e9d6 CW |
314 | |
315 | stats->count++; | |
316 | stats->total += obj->base.size; | |
317 | ||
c67a17e9 CW |
318 | if (obj->base.name || obj->base.dma_buf) |
319 | stats->shared += obj->base.size; | |
320 | ||
6313c204 CW |
321 | if (USES_FULL_PPGTT(obj->base.dev)) { |
322 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
323 | struct i915_hw_ppgtt *ppgtt; | |
324 | ||
325 | if (!drm_mm_node_allocated(&vma->node)) | |
326 | continue; | |
327 | ||
328 | if (i915_is_ggtt(vma->vm)) { | |
329 | stats->global += obj->base.size; | |
330 | continue; | |
331 | } | |
332 | ||
333 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
334 | if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv) | |
335 | continue; | |
336 | ||
337 | if (obj->ring) /* XXX per-vma statistic */ | |
338 | stats->active += obj->base.size; | |
339 | else | |
340 | stats->inactive += obj->base.size; | |
341 | ||
342 | return 0; | |
343 | } | |
2db8e9d6 | 344 | } else { |
6313c204 CW |
345 | if (i915_gem_obj_ggtt_bound(obj)) { |
346 | stats->global += obj->base.size; | |
347 | if (obj->ring) | |
348 | stats->active += obj->base.size; | |
349 | else | |
350 | stats->inactive += obj->base.size; | |
351 | return 0; | |
352 | } | |
2db8e9d6 CW |
353 | } |
354 | ||
6313c204 CW |
355 | if (!list_empty(&obj->global_list)) |
356 | stats->unbound += obj->base.size; | |
357 | ||
2db8e9d6 CW |
358 | return 0; |
359 | } | |
360 | ||
ca191b13 BW |
361 | #define count_vmas(list, member) do { \ |
362 | list_for_each_entry(vma, list, member) { \ | |
363 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
364 | ++count; \ | |
365 | if (vma->obj->map_and_fenceable) { \ | |
366 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
367 | ++mappable_count; \ | |
368 | } \ | |
369 | } \ | |
370 | } while (0) | |
371 | ||
372 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 373 | { |
9f25d007 | 374 | struct drm_info_node *node = m->private; |
73aa808f CW |
375 | struct drm_device *dev = node->minor->dev; |
376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
377 | u32 count, mappable_count, purgeable_count; |
378 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 379 | struct drm_i915_gem_object *obj; |
5cef07e1 | 380 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 381 | struct drm_file *file; |
ca191b13 | 382 | struct i915_vma *vma; |
73aa808f CW |
383 | int ret; |
384 | ||
385 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
386 | if (ret) | |
387 | return ret; | |
388 | ||
6299f992 CW |
389 | seq_printf(m, "%u objects, %zu bytes\n", |
390 | dev_priv->mm.object_count, | |
391 | dev_priv->mm.object_memory); | |
392 | ||
393 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 394 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
395 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
396 | count, mappable_count, size, mappable_size); | |
397 | ||
398 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 399 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
400 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
401 | count, mappable_count, size, mappable_size); | |
402 | ||
6299f992 | 403 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 404 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
405 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
406 | count, mappable_count, size, mappable_size); | |
407 | ||
b7abb714 | 408 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 409 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 410 | size += obj->base.size, ++count; |
b7abb714 CW |
411 | if (obj->madv == I915_MADV_DONTNEED) |
412 | purgeable_size += obj->base.size, ++purgeable_count; | |
413 | } | |
6c085a72 CW |
414 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
415 | ||
6299f992 | 416 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 417 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 418 | if (obj->fault_mappable) { |
f343c5f6 | 419 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
420 | ++count; |
421 | } | |
422 | if (obj->pin_mappable) { | |
f343c5f6 | 423 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
424 | ++mappable_count; |
425 | } | |
b7abb714 CW |
426 | if (obj->madv == I915_MADV_DONTNEED) { |
427 | purgeable_size += obj->base.size; | |
428 | ++purgeable_count; | |
429 | } | |
6299f992 | 430 | } |
b7abb714 CW |
431 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
432 | purgeable_count, purgeable_size); | |
6299f992 CW |
433 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
434 | mappable_count, mappable_size); | |
435 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
436 | count, size); | |
437 | ||
93d18799 | 438 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
439 | dev_priv->gtt.base.total, |
440 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 441 | |
267f0c90 | 442 | seq_putc(m, '\n'); |
2db8e9d6 CW |
443 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
444 | struct file_stats stats; | |
3ec2f427 | 445 | struct task_struct *task; |
2db8e9d6 CW |
446 | |
447 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 448 | stats.file_priv = file->driver_priv; |
2db8e9d6 | 449 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
3ec2f427 TH |
450 | /* |
451 | * Although we have a valid reference on file->pid, that does | |
452 | * not guarantee that the task_struct who called get_pid() is | |
453 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
454 | * Therefore, we need to protect this ->comm access using RCU. | |
455 | */ | |
456 | rcu_read_lock(); | |
457 | task = pid_task(file->pid, PIDTYPE_PID); | |
c67a17e9 | 458 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", |
3ec2f427 | 459 | task ? task->comm : "<unknown>", |
2db8e9d6 CW |
460 | stats.count, |
461 | stats.total, | |
462 | stats.active, | |
463 | stats.inactive, | |
6313c204 | 464 | stats.global, |
c67a17e9 | 465 | stats.shared, |
2db8e9d6 | 466 | stats.unbound); |
3ec2f427 | 467 | rcu_read_unlock(); |
2db8e9d6 CW |
468 | } |
469 | ||
73aa808f CW |
470 | mutex_unlock(&dev->struct_mutex); |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
aee56cff | 475 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 476 | { |
9f25d007 | 477 | struct drm_info_node *node = m->private; |
08c18323 | 478 | struct drm_device *dev = node->minor->dev; |
1b50247a | 479 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
480 | struct drm_i915_private *dev_priv = dev->dev_private; |
481 | struct drm_i915_gem_object *obj; | |
482 | size_t total_obj_size, total_gtt_size; | |
483 | int count, ret; | |
484 | ||
485 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
486 | if (ret) | |
487 | return ret; | |
488 | ||
489 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 490 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 491 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
492 | continue; |
493 | ||
267f0c90 | 494 | seq_puts(m, " "); |
08c18323 | 495 | describe_obj(m, obj); |
267f0c90 | 496 | seq_putc(m, '\n'); |
08c18323 | 497 | total_obj_size += obj->base.size; |
f343c5f6 | 498 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
499 | count++; |
500 | } | |
501 | ||
502 | mutex_unlock(&dev->struct_mutex); | |
503 | ||
504 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
505 | count, total_obj_size, total_gtt_size); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
4e5359cd SF |
510 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
511 | { | |
9f25d007 | 512 | struct drm_info_node *node = m->private; |
4e5359cd SF |
513 | struct drm_device *dev = node->minor->dev; |
514 | unsigned long flags; | |
515 | struct intel_crtc *crtc; | |
516 | ||
d3fcc808 | 517 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
518 | const char pipe = pipe_name(crtc->pipe); |
519 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
520 | struct intel_unpin_work *work; |
521 | ||
522 | spin_lock_irqsave(&dev->event_lock, flags); | |
523 | work = crtc->unpin_work; | |
524 | if (work == NULL) { | |
9db4a9c7 | 525 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
526 | pipe, plane); |
527 | } else { | |
e7d841ca | 528 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 529 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
530 | pipe, plane); |
531 | } else { | |
9db4a9c7 | 532 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
533 | pipe, plane); |
534 | } | |
535 | if (work->enable_stall_check) | |
267f0c90 | 536 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 537 | else |
267f0c90 | 538 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 539 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd SF |
540 | |
541 | if (work->old_fb_obj) { | |
05394f39 CW |
542 | struct drm_i915_gem_object *obj = work->old_fb_obj; |
543 | if (obj) | |
f343c5f6 BW |
544 | seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n", |
545 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
546 | } |
547 | if (work->pending_flip_obj) { | |
05394f39 CW |
548 | struct drm_i915_gem_object *obj = work->pending_flip_obj; |
549 | if (obj) | |
f343c5f6 BW |
550 | seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n", |
551 | i915_gem_obj_ggtt_offset(obj)); | |
4e5359cd SF |
552 | } |
553 | } | |
554 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
555 | } | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
2017263e BG |
560 | static int i915_gem_request_info(struct seq_file *m, void *data) |
561 | { | |
9f25d007 | 562 | struct drm_info_node *node = m->private; |
2017263e | 563 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 564 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 565 | struct intel_engine_cs *ring; |
2017263e | 566 | struct drm_i915_gem_request *gem_request; |
a2c7f6fd | 567 | int ret, count, i; |
de227ef0 CW |
568 | |
569 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
570 | if (ret) | |
571 | return ret; | |
2017263e | 572 | |
c2c347a9 | 573 | count = 0; |
a2c7f6fd CW |
574 | for_each_ring(ring, dev_priv, i) { |
575 | if (list_empty(&ring->request_list)) | |
576 | continue; | |
577 | ||
578 | seq_printf(m, "%s requests:\n", ring->name); | |
c2c347a9 | 579 | list_for_each_entry(gem_request, |
a2c7f6fd | 580 | &ring->request_list, |
c2c347a9 CW |
581 | list) { |
582 | seq_printf(m, " %d @ %d\n", | |
583 | gem_request->seqno, | |
584 | (int) (jiffies - gem_request->emitted_jiffies)); | |
585 | } | |
586 | count++; | |
2017263e | 587 | } |
de227ef0 CW |
588 | mutex_unlock(&dev->struct_mutex); |
589 | ||
c2c347a9 | 590 | if (count == 0) |
267f0c90 | 591 | seq_puts(m, "No requests\n"); |
c2c347a9 | 592 | |
2017263e BG |
593 | return 0; |
594 | } | |
595 | ||
b2223497 | 596 | static void i915_ring_seqno_info(struct seq_file *m, |
a4872ba6 | 597 | struct intel_engine_cs *ring) |
b2223497 CW |
598 | { |
599 | if (ring->get_seqno) { | |
43a7b924 | 600 | seq_printf(m, "Current sequence (%s): %u\n", |
b2eadbc8 | 601 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
602 | } |
603 | } | |
604 | ||
2017263e BG |
605 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
606 | { | |
9f25d007 | 607 | struct drm_info_node *node = m->private; |
2017263e | 608 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 609 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 610 | struct intel_engine_cs *ring; |
1ec14ad3 | 611 | int ret, i; |
de227ef0 CW |
612 | |
613 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
614 | if (ret) | |
615 | return ret; | |
c8c8fb33 | 616 | intel_runtime_pm_get(dev_priv); |
2017263e | 617 | |
a2c7f6fd CW |
618 | for_each_ring(ring, dev_priv, i) |
619 | i915_ring_seqno_info(m, ring); | |
de227ef0 | 620 | |
c8c8fb33 | 621 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
622 | mutex_unlock(&dev->struct_mutex); |
623 | ||
2017263e BG |
624 | return 0; |
625 | } | |
626 | ||
627 | ||
628 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
629 | { | |
9f25d007 | 630 | struct drm_info_node *node = m->private; |
2017263e | 631 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 632 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 633 | struct intel_engine_cs *ring; |
9db4a9c7 | 634 | int ret, i, pipe; |
de227ef0 CW |
635 | |
636 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
637 | if (ret) | |
638 | return ret; | |
c8c8fb33 | 639 | intel_runtime_pm_get(dev_priv); |
2017263e | 640 | |
74e1ca8c VS |
641 | if (IS_CHERRYVIEW(dev)) { |
642 | int i; | |
643 | seq_printf(m, "Master Interrupt Control:\t%08x\n", | |
644 | I915_READ(GEN8_MASTER_IRQ)); | |
645 | ||
646 | seq_printf(m, "Display IER:\t%08x\n", | |
647 | I915_READ(VLV_IER)); | |
648 | seq_printf(m, "Display IIR:\t%08x\n", | |
649 | I915_READ(VLV_IIR)); | |
650 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
651 | I915_READ(VLV_IIR_RW)); | |
652 | seq_printf(m, "Display IMR:\t%08x\n", | |
653 | I915_READ(VLV_IMR)); | |
654 | for_each_pipe(pipe) | |
655 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
656 | pipe_name(pipe), | |
657 | I915_READ(PIPESTAT(pipe))); | |
658 | ||
659 | seq_printf(m, "Port hotplug:\t%08x\n", | |
660 | I915_READ(PORT_HOTPLUG_EN)); | |
661 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
662 | I915_READ(VLV_DPFLIPSTAT)); | |
663 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
664 | I915_READ(DPINVGTT)); | |
665 | ||
666 | for (i = 0; i < 4; i++) { | |
667 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
668 | i, I915_READ(GEN8_GT_IMR(i))); | |
669 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
670 | i, I915_READ(GEN8_GT_IIR(i))); | |
671 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
672 | i, I915_READ(GEN8_GT_IER(i))); | |
673 | } | |
674 | ||
675 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
676 | I915_READ(GEN8_PCU_IMR)); | |
677 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
678 | I915_READ(GEN8_PCU_IIR)); | |
679 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
680 | I915_READ(GEN8_PCU_IER)); | |
681 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
682 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
683 | I915_READ(GEN8_MASTER_IRQ)); | |
684 | ||
685 | for (i = 0; i < 4; i++) { | |
686 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
687 | i, I915_READ(GEN8_GT_IMR(i))); | |
688 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
689 | i, I915_READ(GEN8_GT_IIR(i))); | |
690 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
691 | i, I915_READ(GEN8_GT_IER(i))); | |
692 | } | |
693 | ||
07d27e20 | 694 | for_each_pipe(pipe) { |
a123f157 | 695 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
696 | pipe_name(pipe), |
697 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 698 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
699 | pipe_name(pipe), |
700 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 701 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
702 | pipe_name(pipe), |
703 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
a123f157 BW |
704 | } |
705 | ||
706 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
707 | I915_READ(GEN8_DE_PORT_IMR)); | |
708 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
709 | I915_READ(GEN8_DE_PORT_IIR)); | |
710 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
711 | I915_READ(GEN8_DE_PORT_IER)); | |
712 | ||
713 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
714 | I915_READ(GEN8_DE_MISC_IMR)); | |
715 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
716 | I915_READ(GEN8_DE_MISC_IIR)); | |
717 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
718 | I915_READ(GEN8_DE_MISC_IER)); | |
719 | ||
720 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
721 | I915_READ(GEN8_PCU_IMR)); | |
722 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
723 | I915_READ(GEN8_PCU_IIR)); | |
724 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
725 | I915_READ(GEN8_PCU_IER)); | |
726 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
727 | seq_printf(m, "Display IER:\t%08x\n", |
728 | I915_READ(VLV_IER)); | |
729 | seq_printf(m, "Display IIR:\t%08x\n", | |
730 | I915_READ(VLV_IIR)); | |
731 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
732 | I915_READ(VLV_IIR_RW)); | |
733 | seq_printf(m, "Display IMR:\t%08x\n", | |
734 | I915_READ(VLV_IMR)); | |
735 | for_each_pipe(pipe) | |
736 | seq_printf(m, "Pipe %c stat:\t%08x\n", | |
737 | pipe_name(pipe), | |
738 | I915_READ(PIPESTAT(pipe))); | |
739 | ||
740 | seq_printf(m, "Master IER:\t%08x\n", | |
741 | I915_READ(VLV_MASTER_IER)); | |
742 | ||
743 | seq_printf(m, "Render IER:\t%08x\n", | |
744 | I915_READ(GTIER)); | |
745 | seq_printf(m, "Render IIR:\t%08x\n", | |
746 | I915_READ(GTIIR)); | |
747 | seq_printf(m, "Render IMR:\t%08x\n", | |
748 | I915_READ(GTIMR)); | |
749 | ||
750 | seq_printf(m, "PM IER:\t\t%08x\n", | |
751 | I915_READ(GEN6_PMIER)); | |
752 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
753 | I915_READ(GEN6_PMIIR)); | |
754 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
755 | I915_READ(GEN6_PMIMR)); | |
756 | ||
757 | seq_printf(m, "Port hotplug:\t%08x\n", | |
758 | I915_READ(PORT_HOTPLUG_EN)); | |
759 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
760 | I915_READ(VLV_DPFLIPSTAT)); | |
761 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
762 | I915_READ(DPINVGTT)); | |
763 | ||
764 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
765 | seq_printf(m, "Interrupt enable: %08x\n", |
766 | I915_READ(IER)); | |
767 | seq_printf(m, "Interrupt identity: %08x\n", | |
768 | I915_READ(IIR)); | |
769 | seq_printf(m, "Interrupt mask: %08x\n", | |
770 | I915_READ(IMR)); | |
9db4a9c7 JB |
771 | for_each_pipe(pipe) |
772 | seq_printf(m, "Pipe %c stat: %08x\n", | |
773 | pipe_name(pipe), | |
774 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
775 | } else { |
776 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
777 | I915_READ(DEIER)); | |
778 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
779 | I915_READ(DEIIR)); | |
780 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
781 | I915_READ(DEIMR)); | |
782 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
783 | I915_READ(SDEIER)); | |
784 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
785 | I915_READ(SDEIIR)); | |
786 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
787 | I915_READ(SDEIMR)); | |
788 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
789 | I915_READ(GTIER)); | |
790 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
791 | I915_READ(GTIIR)); | |
792 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
793 | I915_READ(GTIMR)); | |
794 | } | |
a2c7f6fd | 795 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 796 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
797 | seq_printf(m, |
798 | "Graphics Interrupt mask (%s): %08x\n", | |
799 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 800 | } |
a2c7f6fd | 801 | i915_ring_seqno_info(m, ring); |
9862e600 | 802 | } |
c8c8fb33 | 803 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
804 | mutex_unlock(&dev->struct_mutex); |
805 | ||
2017263e BG |
806 | return 0; |
807 | } | |
808 | ||
a6172a80 CW |
809 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
810 | { | |
9f25d007 | 811 | struct drm_info_node *node = m->private; |
a6172a80 | 812 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 813 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
814 | int i, ret; |
815 | ||
816 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
817 | if (ret) | |
818 | return ret; | |
a6172a80 CW |
819 | |
820 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
821 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
822 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 823 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 824 | |
6c085a72 CW |
825 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
826 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 827 | if (obj == NULL) |
267f0c90 | 828 | seq_puts(m, "unused"); |
c2c347a9 | 829 | else |
05394f39 | 830 | describe_obj(m, obj); |
267f0c90 | 831 | seq_putc(m, '\n'); |
a6172a80 CW |
832 | } |
833 | ||
05394f39 | 834 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
835 | return 0; |
836 | } | |
837 | ||
2017263e BG |
838 | static int i915_hws_info(struct seq_file *m, void *data) |
839 | { | |
9f25d007 | 840 | struct drm_info_node *node = m->private; |
2017263e | 841 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 842 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 843 | struct intel_engine_cs *ring; |
1a240d4d | 844 | const u32 *hws; |
4066c0ae CW |
845 | int i; |
846 | ||
1ec14ad3 | 847 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 848 | hws = ring->status_page.page_addr; |
2017263e BG |
849 | if (hws == NULL) |
850 | return 0; | |
851 | ||
852 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
853 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
854 | i * 4, | |
855 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
856 | } | |
857 | return 0; | |
858 | } | |
859 | ||
d5442303 DV |
860 | static ssize_t |
861 | i915_error_state_write(struct file *filp, | |
862 | const char __user *ubuf, | |
863 | size_t cnt, | |
864 | loff_t *ppos) | |
865 | { | |
edc3d884 | 866 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 867 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 868 | int ret; |
d5442303 DV |
869 | |
870 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
871 | ||
22bcfc6a DV |
872 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
873 | if (ret) | |
874 | return ret; | |
875 | ||
d5442303 DV |
876 | i915_destroy_error_state(dev); |
877 | mutex_unlock(&dev->struct_mutex); | |
878 | ||
879 | return cnt; | |
880 | } | |
881 | ||
882 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
883 | { | |
884 | struct drm_device *dev = inode->i_private; | |
d5442303 | 885 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
886 | |
887 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
888 | if (!error_priv) | |
889 | return -ENOMEM; | |
890 | ||
891 | error_priv->dev = dev; | |
892 | ||
95d5bfb3 | 893 | i915_error_state_get(dev, error_priv); |
d5442303 | 894 | |
edc3d884 MK |
895 | file->private_data = error_priv; |
896 | ||
897 | return 0; | |
d5442303 DV |
898 | } |
899 | ||
900 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
901 | { | |
edc3d884 | 902 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 903 | |
95d5bfb3 | 904 | i915_error_state_put(error_priv); |
d5442303 DV |
905 | kfree(error_priv); |
906 | ||
edc3d884 MK |
907 | return 0; |
908 | } | |
909 | ||
4dc955f7 MK |
910 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
911 | size_t count, loff_t *pos) | |
912 | { | |
913 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
914 | struct drm_i915_error_state_buf error_str; | |
915 | loff_t tmp_pos = 0; | |
916 | ssize_t ret_count = 0; | |
917 | int ret; | |
918 | ||
919 | ret = i915_error_state_buf_init(&error_str, count, *pos); | |
920 | if (ret) | |
921 | return ret; | |
edc3d884 | 922 | |
fc16b48b | 923 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
924 | if (ret) |
925 | goto out; | |
926 | ||
edc3d884 MK |
927 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
928 | error_str.buf, | |
929 | error_str.bytes); | |
930 | ||
931 | if (ret_count < 0) | |
932 | ret = ret_count; | |
933 | else | |
934 | *pos = error_str.start + ret_count; | |
935 | out: | |
4dc955f7 | 936 | i915_error_state_buf_release(&error_str); |
edc3d884 | 937 | return ret ?: ret_count; |
d5442303 DV |
938 | } |
939 | ||
940 | static const struct file_operations i915_error_state_fops = { | |
941 | .owner = THIS_MODULE, | |
942 | .open = i915_error_state_open, | |
edc3d884 | 943 | .read = i915_error_state_read, |
d5442303 DV |
944 | .write = i915_error_state_write, |
945 | .llseek = default_llseek, | |
946 | .release = i915_error_state_release, | |
947 | }; | |
948 | ||
647416f9 KC |
949 | static int |
950 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 951 | { |
647416f9 | 952 | struct drm_device *dev = data; |
e277a1f8 | 953 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
954 | int ret; |
955 | ||
956 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
957 | if (ret) | |
958 | return ret; | |
959 | ||
647416f9 | 960 | *val = dev_priv->next_seqno; |
40633219 MK |
961 | mutex_unlock(&dev->struct_mutex); |
962 | ||
647416f9 | 963 | return 0; |
40633219 MK |
964 | } |
965 | ||
647416f9 KC |
966 | static int |
967 | i915_next_seqno_set(void *data, u64 val) | |
968 | { | |
969 | struct drm_device *dev = data; | |
40633219 MK |
970 | int ret; |
971 | ||
40633219 MK |
972 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
973 | if (ret) | |
974 | return ret; | |
975 | ||
e94fbaa8 | 976 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
977 | mutex_unlock(&dev->struct_mutex); |
978 | ||
647416f9 | 979 | return ret; |
40633219 MK |
980 | } |
981 | ||
647416f9 KC |
982 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
983 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 984 | "0x%llx\n"); |
40633219 | 985 | |
f97108d1 JB |
986 | static int i915_rstdby_delays(struct seq_file *m, void *unused) |
987 | { | |
9f25d007 | 988 | struct drm_info_node *node = m->private; |
f97108d1 | 989 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 990 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
991 | u16 crstanddelay; |
992 | int ret; | |
993 | ||
994 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
995 | if (ret) | |
996 | return ret; | |
c8c8fb33 | 997 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
998 | |
999 | crstanddelay = I915_READ16(CRSTANDVID); | |
1000 | ||
c8c8fb33 | 1001 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1002 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
1003 | |
1004 | seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f)); | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
adb4bd12 | 1009 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1010 | { |
9f25d007 | 1011 | struct drm_info_node *node = m->private; |
f97108d1 | 1012 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1013 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
1014 | int ret = 0; |
1015 | ||
1016 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1017 | |
5c9669ce TR |
1018 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1019 | ||
3b8d8d91 JB |
1020 | if (IS_GEN5(dev)) { |
1021 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1022 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1023 | ||
1024 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1025 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1026 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1027 | MEMSTAT_VID_SHIFT); | |
1028 | seq_printf(m, "Current P-state: %d\n", | |
1029 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
daa3afb2 TR |
1030 | } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) || |
1031 | IS_BROADWELL(dev)) { | |
3b8d8d91 JB |
1032 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
1033 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
1034 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
0d8f9491 | 1035 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1036 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1037 | u32 rpupei, rpcurup, rpprevup; |
1038 | u32 rpdownei, rpcurdown, rpprevdown; | |
3b8d8d91 JB |
1039 | int max_freq; |
1040 | ||
1041 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
1042 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1043 | if (ret) | |
c8c8fb33 | 1044 | goto out; |
d1ebd816 | 1045 | |
c8d9a590 | 1046 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1047 | |
8e8c06cd CW |
1048 | reqf = I915_READ(GEN6_RPNSWREQ); |
1049 | reqf &= ~GEN6_TURBO_DISABLE; | |
daa3afb2 | 1050 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
8e8c06cd CW |
1051 | reqf >>= 24; |
1052 | else | |
1053 | reqf >>= 25; | |
1054 | reqf *= GT_FREQUENCY_MULTIPLIER; | |
1055 | ||
0d8f9491 CW |
1056 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1057 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1058 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1059 | ||
ccab5c82 JB |
1060 | rpstat = I915_READ(GEN6_RPSTAT1); |
1061 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
1062 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
1063 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
1064 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
1065 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
1066 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
daa3afb2 | 1067 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
f82855d3 BW |
1068 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1069 | else | |
1070 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
1071 | cagf *= GT_FREQUENCY_MULTIPLIER; | |
ccab5c82 | 1072 | |
c8d9a590 | 1073 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1074 | mutex_unlock(&dev->struct_mutex); |
1075 | ||
0d8f9491 CW |
1076 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
1077 | I915_READ(GEN6_PMIER), | |
1078 | I915_READ(GEN6_PMIMR), | |
1079 | I915_READ(GEN6_PMISR), | |
1080 | I915_READ(GEN6_PMIIR), | |
1081 | I915_READ(GEN6_PMINTRMSK)); | |
3b8d8d91 | 1082 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 JB |
1083 | seq_printf(m, "Render p-state ratio: %d\n", |
1084 | (gt_perf_status & 0xff00) >> 8); | |
1085 | seq_printf(m, "Render p-state VID: %d\n", | |
1086 | gt_perf_status & 0xff); | |
1087 | seq_printf(m, "Render p-state limit: %d\n", | |
1088 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1089 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1090 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1091 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1092 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1093 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1094 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1095 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1096 | GEN6_CURICONT_MASK); | |
1097 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1098 | GEN6_CURBSYTAVG_MASK); | |
1099 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1100 | GEN6_CURBSYTAVG_MASK); | |
1101 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & | |
1102 | GEN6_CURIAVG_MASK); | |
1103 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1104 | GEN6_CURBSYTAVG_MASK); | |
1105 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1106 | GEN6_CURBSYTAVG_MASK); | |
3b8d8d91 JB |
1107 | |
1108 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
1109 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", | |
c8735b0c | 1110 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1111 | |
1112 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
1113 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", | |
c8735b0c | 1114 | max_freq * GT_FREQUENCY_MULTIPLIER); |
3b8d8d91 JB |
1115 | |
1116 | max_freq = rp_state_cap & 0xff; | |
1117 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", | |
c8735b0c | 1118 | max_freq * GT_FREQUENCY_MULTIPLIER); |
31c77388 BW |
1119 | |
1120 | seq_printf(m, "Max overclocked frequency: %dMHz\n", | |
b39fb297 | 1121 | dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER); |
0a073b84 JB |
1122 | } else if (IS_VALLEYVIEW(dev)) { |
1123 | u32 freq_sts, val; | |
1124 | ||
259bd5d4 | 1125 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1126 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1127 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1128 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1129 | ||
c5bd2bf6 | 1130 | val = valleyview_rps_max_freq(dev_priv); |
0a073b84 | 1131 | seq_printf(m, "max GPU freq: %d MHz\n", |
2ec3815f | 1132 | vlv_gpu_freq(dev_priv, val)); |
0a073b84 | 1133 | |
c5bd2bf6 | 1134 | val = valleyview_rps_min_freq(dev_priv); |
0a073b84 | 1135 | seq_printf(m, "min GPU freq: %d MHz\n", |
2ec3815f | 1136 | vlv_gpu_freq(dev_priv, val)); |
0a073b84 JB |
1137 | |
1138 | seq_printf(m, "current GPU freq: %d MHz\n", | |
2ec3815f | 1139 | vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); |
259bd5d4 | 1140 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1141 | } else { |
267f0c90 | 1142 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1143 | } |
f97108d1 | 1144 | |
c8c8fb33 PZ |
1145 | out: |
1146 | intel_runtime_pm_put(dev_priv); | |
1147 | return ret; | |
f97108d1 JB |
1148 | } |
1149 | ||
1150 | static int i915_delayfreq_table(struct seq_file *m, void *unused) | |
1151 | { | |
9f25d007 | 1152 | struct drm_info_node *node = m->private; |
f97108d1 | 1153 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1154 | struct drm_i915_private *dev_priv = dev->dev_private; |
f97108d1 | 1155 | u32 delayfreq; |
616fdb5a BW |
1156 | int ret, i; |
1157 | ||
1158 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1159 | if (ret) | |
1160 | return ret; | |
c8c8fb33 | 1161 | intel_runtime_pm_get(dev_priv); |
f97108d1 JB |
1162 | |
1163 | for (i = 0; i < 16; i++) { | |
1164 | delayfreq = I915_READ(PXVFREQ_BASE + i * 4); | |
7648fa99 JB |
1165 | seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq, |
1166 | (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT); | |
f97108d1 JB |
1167 | } |
1168 | ||
c8c8fb33 PZ |
1169 | intel_runtime_pm_put(dev_priv); |
1170 | ||
616fdb5a BW |
1171 | mutex_unlock(&dev->struct_mutex); |
1172 | ||
f97108d1 JB |
1173 | return 0; |
1174 | } | |
1175 | ||
1176 | static inline int MAP_TO_MV(int map) | |
1177 | { | |
1178 | return 1250 - (map * 25); | |
1179 | } | |
1180 | ||
1181 | static int i915_inttoext_table(struct seq_file *m, void *unused) | |
1182 | { | |
9f25d007 | 1183 | struct drm_info_node *node = m->private; |
f97108d1 | 1184 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1185 | struct drm_i915_private *dev_priv = dev->dev_private; |
f97108d1 | 1186 | u32 inttoext; |
616fdb5a BW |
1187 | int ret, i; |
1188 | ||
1189 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1190 | if (ret) | |
1191 | return ret; | |
c8c8fb33 | 1192 | intel_runtime_pm_get(dev_priv); |
f97108d1 JB |
1193 | |
1194 | for (i = 1; i <= 32; i++) { | |
1195 | inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4); | |
1196 | seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext); | |
1197 | } | |
1198 | ||
c8c8fb33 | 1199 | intel_runtime_pm_put(dev_priv); |
616fdb5a BW |
1200 | mutex_unlock(&dev->struct_mutex); |
1201 | ||
f97108d1 JB |
1202 | return 0; |
1203 | } | |
1204 | ||
4d85529d | 1205 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1206 | { |
9f25d007 | 1207 | struct drm_info_node *node = m->private; |
f97108d1 | 1208 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1209 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1210 | u32 rgvmodectl, rstdbyctl; |
1211 | u16 crstandvid; | |
1212 | int ret; | |
1213 | ||
1214 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1215 | if (ret) | |
1216 | return ret; | |
c8c8fb33 | 1217 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1218 | |
1219 | rgvmodectl = I915_READ(MEMMODECTL); | |
1220 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1221 | crstandvid = I915_READ16(CRSTANDVID); | |
1222 | ||
c8c8fb33 | 1223 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1224 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
1225 | |
1226 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1227 | "yes" : "no"); | |
1228 | seq_printf(m, "Boost freq: %d\n", | |
1229 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1230 | MEMMODE_BOOST_FREQ_SHIFT); | |
1231 | seq_printf(m, "HW control enabled: %s\n", | |
1232 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1233 | seq_printf(m, "SW control enabled: %s\n", | |
1234 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1235 | seq_printf(m, "Gated voltage change: %s\n", | |
1236 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1237 | seq_printf(m, "Starting frequency: P%d\n", | |
1238 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1239 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1240 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1241 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1242 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1243 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1244 | seq_printf(m, "Render standby enabled: %s\n", | |
1245 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1246 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1247 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1248 | case RSX_STATUS_ON: | |
267f0c90 | 1249 | seq_puts(m, "on\n"); |
88271da3 JB |
1250 | break; |
1251 | case RSX_STATUS_RC1: | |
267f0c90 | 1252 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1253 | break; |
1254 | case RSX_STATUS_RC1E: | |
267f0c90 | 1255 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1256 | break; |
1257 | case RSX_STATUS_RS1: | |
267f0c90 | 1258 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1259 | break; |
1260 | case RSX_STATUS_RS2: | |
267f0c90 | 1261 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1262 | break; |
1263 | case RSX_STATUS_RS3: | |
267f0c90 | 1264 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1265 | break; |
1266 | default: | |
267f0c90 | 1267 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1268 | break; |
1269 | } | |
f97108d1 JB |
1270 | |
1271 | return 0; | |
1272 | } | |
1273 | ||
669ab5aa D |
1274 | static int vlv_drpc_info(struct seq_file *m) |
1275 | { | |
1276 | ||
9f25d007 | 1277 | struct drm_info_node *node = m->private; |
669ab5aa D |
1278 | struct drm_device *dev = node->minor->dev; |
1279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1280 | u32 rpmodectl1, rcctl1; | |
1281 | unsigned fw_rendercount = 0, fw_mediacount = 0; | |
1282 | ||
d46c0517 ID |
1283 | intel_runtime_pm_get(dev_priv); |
1284 | ||
669ab5aa D |
1285 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1286 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1287 | ||
d46c0517 ID |
1288 | intel_runtime_pm_put(dev_priv); |
1289 | ||
669ab5aa D |
1290 | seq_printf(m, "Video Turbo Mode: %s\n", |
1291 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1292 | seq_printf(m, "Turbo enabled: %s\n", | |
1293 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1294 | seq_printf(m, "HW control enabled: %s\n", | |
1295 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1296 | seq_printf(m, "SW control enabled: %s\n", | |
1297 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1298 | GEN6_RP_MEDIA_SW_MODE)); | |
1299 | seq_printf(m, "RC6 Enabled: %s\n", | |
1300 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1301 | GEN6_RC_CTL_EI_MODE(1)))); | |
1302 | seq_printf(m, "Render Power Well: %s\n", | |
1303 | (I915_READ(VLV_GTLC_PW_STATUS) & | |
1304 | VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); | |
1305 | seq_printf(m, "Media Power Well: %s\n", | |
1306 | (I915_READ(VLV_GTLC_PW_STATUS) & | |
1307 | VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); | |
1308 | ||
9cc19be5 ID |
1309 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1310 | I915_READ(VLV_GT_RENDER_RC6)); | |
1311 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1312 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1313 | ||
669ab5aa D |
1314 | spin_lock_irq(&dev_priv->uncore.lock); |
1315 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1316 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1317 | spin_unlock_irq(&dev_priv->uncore.lock); | |
1318 | ||
1319 | seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount); | |
1320 | seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount); | |
1321 | ||
1322 | ||
1323 | return 0; | |
1324 | } | |
1325 | ||
1326 | ||
4d85529d BW |
1327 | static int gen6_drpc_info(struct seq_file *m) |
1328 | { | |
1329 | ||
9f25d007 | 1330 | struct drm_info_node *node = m->private; |
4d85529d BW |
1331 | struct drm_device *dev = node->minor->dev; |
1332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1333 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1334 | unsigned forcewake_count; |
aee56cff | 1335 | int count = 0, ret; |
4d85529d BW |
1336 | |
1337 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1338 | if (ret) | |
1339 | return ret; | |
c8c8fb33 | 1340 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1341 | |
907b28c5 CW |
1342 | spin_lock_irq(&dev_priv->uncore.lock); |
1343 | forcewake_count = dev_priv->uncore.forcewake_count; | |
1344 | spin_unlock_irq(&dev_priv->uncore.lock); | |
93b525dc DV |
1345 | |
1346 | if (forcewake_count) { | |
267f0c90 DL |
1347 | seq_puts(m, "RC information inaccurate because somebody " |
1348 | "holds a forcewake reference \n"); | |
4d85529d BW |
1349 | } else { |
1350 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1351 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1352 | udelay(10); | |
1353 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1354 | } | |
1355 | ||
1356 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1357 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1358 | |
1359 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1360 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1361 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1362 | mutex_lock(&dev_priv->rps.hw_lock); |
1363 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1364 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1365 | |
c8c8fb33 PZ |
1366 | intel_runtime_pm_put(dev_priv); |
1367 | ||
4d85529d BW |
1368 | seq_printf(m, "Video Turbo Mode: %s\n", |
1369 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1370 | seq_printf(m, "HW control enabled: %s\n", | |
1371 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1372 | seq_printf(m, "SW control enabled: %s\n", | |
1373 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1374 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1375 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1376 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1377 | seq_printf(m, "RC6 Enabled: %s\n", | |
1378 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1379 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1380 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1381 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1382 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1383 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1384 | switch (gt_core_status & GEN6_RCn_MASK) { |
1385 | case GEN6_RC0: | |
1386 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1387 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1388 | else |
267f0c90 | 1389 | seq_puts(m, "on\n"); |
4d85529d BW |
1390 | break; |
1391 | case GEN6_RC3: | |
267f0c90 | 1392 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1393 | break; |
1394 | case GEN6_RC6: | |
267f0c90 | 1395 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1396 | break; |
1397 | case GEN6_RC7: | |
267f0c90 | 1398 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1399 | break; |
1400 | default: | |
267f0c90 | 1401 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1402 | break; |
1403 | } | |
1404 | ||
1405 | seq_printf(m, "Core Power Down: %s\n", | |
1406 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1407 | |
1408 | /* Not exactly sure what this is */ | |
1409 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1410 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1411 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1412 | I915_READ(GEN6_GT_GFX_RC6)); | |
1413 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1414 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1415 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1416 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1417 | ||
ecd8faea BW |
1418 | seq_printf(m, "RC6 voltage: %dmV\n", |
1419 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1420 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1421 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1422 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1423 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1424 | return 0; |
1425 | } | |
1426 | ||
1427 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1428 | { | |
9f25d007 | 1429 | struct drm_info_node *node = m->private; |
4d85529d BW |
1430 | struct drm_device *dev = node->minor->dev; |
1431 | ||
669ab5aa D |
1432 | if (IS_VALLEYVIEW(dev)) |
1433 | return vlv_drpc_info(m); | |
1434 | else if (IS_GEN6(dev) || IS_GEN7(dev)) | |
4d85529d BW |
1435 | return gen6_drpc_info(m); |
1436 | else | |
1437 | return ironlake_drpc_info(m); | |
1438 | } | |
1439 | ||
b5e50c3f JB |
1440 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1441 | { | |
9f25d007 | 1442 | struct drm_info_node *node = m->private; |
b5e50c3f | 1443 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1444 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1445 | |
3a77c4c4 | 1446 | if (!HAS_FBC(dev)) { |
267f0c90 | 1447 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1448 | return 0; |
1449 | } | |
1450 | ||
36623ef8 PZ |
1451 | intel_runtime_pm_get(dev_priv); |
1452 | ||
ee5382ae | 1453 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1454 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1455 | } else { |
267f0c90 | 1456 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1457 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1458 | case FBC_OK: |
1459 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1460 | break; | |
1461 | case FBC_UNSUPPORTED: | |
1462 | seq_puts(m, "unsupported by this chipset"); | |
1463 | break; | |
bed4a673 | 1464 | case FBC_NO_OUTPUT: |
267f0c90 | 1465 | seq_puts(m, "no outputs"); |
bed4a673 | 1466 | break; |
b5e50c3f | 1467 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1468 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1469 | break; |
1470 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1471 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1472 | break; |
1473 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1474 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1475 | break; |
1476 | case FBC_BAD_PLANE: | |
267f0c90 | 1477 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1478 | break; |
1479 | case FBC_NOT_TILED: | |
267f0c90 | 1480 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1481 | break; |
9c928d16 | 1482 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1483 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1484 | break; |
c1a9f047 | 1485 | case FBC_MODULE_PARAM: |
267f0c90 | 1486 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1487 | break; |
8a5729a3 | 1488 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1489 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1490 | break; |
b5e50c3f | 1491 | default: |
267f0c90 | 1492 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1493 | } |
267f0c90 | 1494 | seq_putc(m, '\n'); |
b5e50c3f | 1495 | } |
36623ef8 PZ |
1496 | |
1497 | intel_runtime_pm_put(dev_priv); | |
1498 | ||
b5e50c3f JB |
1499 | return 0; |
1500 | } | |
1501 | ||
92d44621 PZ |
1502 | static int i915_ips_status(struct seq_file *m, void *unused) |
1503 | { | |
9f25d007 | 1504 | struct drm_info_node *node = m->private; |
92d44621 PZ |
1505 | struct drm_device *dev = node->minor->dev; |
1506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1507 | ||
f5adf94e | 1508 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1509 | seq_puts(m, "not supported\n"); |
1510 | return 0; | |
1511 | } | |
1512 | ||
36623ef8 PZ |
1513 | intel_runtime_pm_get(dev_priv); |
1514 | ||
e59150dc | 1515 | if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE) |
92d44621 PZ |
1516 | seq_puts(m, "enabled\n"); |
1517 | else | |
1518 | seq_puts(m, "disabled\n"); | |
1519 | ||
36623ef8 PZ |
1520 | intel_runtime_pm_put(dev_priv); |
1521 | ||
92d44621 PZ |
1522 | return 0; |
1523 | } | |
1524 | ||
4a9bef37 JB |
1525 | static int i915_sr_status(struct seq_file *m, void *unused) |
1526 | { | |
9f25d007 | 1527 | struct drm_info_node *node = m->private; |
4a9bef37 | 1528 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1529 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1530 | bool sr_enabled = false; |
1531 | ||
36623ef8 PZ |
1532 | intel_runtime_pm_get(dev_priv); |
1533 | ||
1398261a | 1534 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1535 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1536 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1537 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1538 | else if (IS_I915GM(dev)) | |
1539 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1540 | else if (IS_PINEVIEW(dev)) | |
1541 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1542 | ||
36623ef8 PZ |
1543 | intel_runtime_pm_put(dev_priv); |
1544 | ||
5ba2aaaa CW |
1545 | seq_printf(m, "self-refresh: %s\n", |
1546 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1547 | |
1548 | return 0; | |
1549 | } | |
1550 | ||
7648fa99 JB |
1551 | static int i915_emon_status(struct seq_file *m, void *unused) |
1552 | { | |
9f25d007 | 1553 | struct drm_info_node *node = m->private; |
7648fa99 | 1554 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1555 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1556 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1557 | int ret; |
1558 | ||
582be6b4 CW |
1559 | if (!IS_GEN5(dev)) |
1560 | return -ENODEV; | |
1561 | ||
de227ef0 CW |
1562 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1563 | if (ret) | |
1564 | return ret; | |
7648fa99 JB |
1565 | |
1566 | temp = i915_mch_val(dev_priv); | |
1567 | chipset = i915_chipset_val(dev_priv); | |
1568 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1569 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1570 | |
1571 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1572 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1573 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1574 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1575 | ||
1576 | return 0; | |
1577 | } | |
1578 | ||
23b2f8bb JB |
1579 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1580 | { | |
9f25d007 | 1581 | struct drm_info_node *node = m->private; |
23b2f8bb | 1582 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1583 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1584 | int ret = 0; |
23b2f8bb JB |
1585 | int gpu_freq, ia_freq; |
1586 | ||
1c70c0ce | 1587 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1588 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1589 | return 0; |
1590 | } | |
1591 | ||
5bfa0199 PZ |
1592 | intel_runtime_pm_get(dev_priv); |
1593 | ||
5c9669ce TR |
1594 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1595 | ||
4fc688ce | 1596 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1597 | if (ret) |
5bfa0199 | 1598 | goto out; |
23b2f8bb | 1599 | |
267f0c90 | 1600 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1601 | |
b39fb297 BW |
1602 | for (gpu_freq = dev_priv->rps.min_freq_softlimit; |
1603 | gpu_freq <= dev_priv->rps.max_freq_softlimit; | |
23b2f8bb | 1604 | gpu_freq++) { |
42c0526c BW |
1605 | ia_freq = gpu_freq; |
1606 | sandybridge_pcode_read(dev_priv, | |
1607 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1608 | &ia_freq); | |
3ebecd07 CW |
1609 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
1610 | gpu_freq * GT_FREQUENCY_MULTIPLIER, | |
1611 | ((ia_freq >> 0) & 0xff) * 100, | |
1612 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1613 | } |
1614 | ||
4fc688ce | 1615 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1616 | |
5bfa0199 PZ |
1617 | out: |
1618 | intel_runtime_pm_put(dev_priv); | |
1619 | return ret; | |
23b2f8bb JB |
1620 | } |
1621 | ||
7648fa99 JB |
1622 | static int i915_gfxec(struct seq_file *m, void *unused) |
1623 | { | |
9f25d007 | 1624 | struct drm_info_node *node = m->private; |
7648fa99 | 1625 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1626 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1627 | int ret; |
1628 | ||
1629 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1630 | if (ret) | |
1631 | return ret; | |
c8c8fb33 | 1632 | intel_runtime_pm_get(dev_priv); |
7648fa99 JB |
1633 | |
1634 | seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4)); | |
c8c8fb33 | 1635 | intel_runtime_pm_put(dev_priv); |
7648fa99 | 1636 | |
616fdb5a BW |
1637 | mutex_unlock(&dev->struct_mutex); |
1638 | ||
7648fa99 JB |
1639 | return 0; |
1640 | } | |
1641 | ||
44834a67 CW |
1642 | static int i915_opregion(struct seq_file *m, void *unused) |
1643 | { | |
9f25d007 | 1644 | struct drm_info_node *node = m->private; |
44834a67 | 1645 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1646 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 | 1647 | struct intel_opregion *opregion = &dev_priv->opregion; |
0d38f009 | 1648 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1649 | int ret; |
1650 | ||
0d38f009 DV |
1651 | if (data == NULL) |
1652 | return -ENOMEM; | |
1653 | ||
44834a67 CW |
1654 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1655 | if (ret) | |
0d38f009 | 1656 | goto out; |
44834a67 | 1657 | |
0d38f009 DV |
1658 | if (opregion->header) { |
1659 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1660 | seq_write(m, data, OPREGION_SIZE); | |
1661 | } | |
44834a67 CW |
1662 | |
1663 | mutex_unlock(&dev->struct_mutex); | |
1664 | ||
0d38f009 DV |
1665 | out: |
1666 | kfree(data); | |
44834a67 CW |
1667 | return 0; |
1668 | } | |
1669 | ||
37811fcc CW |
1670 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1671 | { | |
9f25d007 | 1672 | struct drm_info_node *node = m->private; |
37811fcc | 1673 | struct drm_device *dev = node->minor->dev; |
4520f53a | 1674 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1675 | struct intel_framebuffer *fb; |
37811fcc | 1676 | |
4520f53a DV |
1677 | #ifdef CONFIG_DRM_I915_FBDEV |
1678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
37811fcc CW |
1679 | |
1680 | ifbdev = dev_priv->fbdev; | |
1681 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1682 | ||
623f9783 | 1683 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1684 | fb->base.width, |
1685 | fb->base.height, | |
1686 | fb->base.depth, | |
623f9783 DV |
1687 | fb->base.bits_per_pixel, |
1688 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1689 | describe_obj(m, fb->obj); |
267f0c90 | 1690 | seq_putc(m, '\n'); |
4520f53a | 1691 | #endif |
37811fcc | 1692 | |
4b096ac1 | 1693 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc | 1694 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
131a56dc | 1695 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
37811fcc CW |
1696 | continue; |
1697 | ||
623f9783 | 1698 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ", |
37811fcc CW |
1699 | fb->base.width, |
1700 | fb->base.height, | |
1701 | fb->base.depth, | |
623f9783 DV |
1702 | fb->base.bits_per_pixel, |
1703 | atomic_read(&fb->base.refcount.refcount)); | |
05394f39 | 1704 | describe_obj(m, fb->obj); |
267f0c90 | 1705 | seq_putc(m, '\n'); |
37811fcc | 1706 | } |
4b096ac1 | 1707 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1708 | |
1709 | return 0; | |
1710 | } | |
1711 | ||
e76d3630 BW |
1712 | static int i915_context_status(struct seq_file *m, void *unused) |
1713 | { | |
9f25d007 | 1714 | struct drm_info_node *node = m->private; |
e76d3630 | 1715 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1716 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1717 | struct intel_engine_cs *ring; |
273497e5 | 1718 | struct intel_context *ctx; |
a168c293 | 1719 | int ret, i; |
e76d3630 | 1720 | |
f3d28878 | 1721 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1722 | if (ret) |
1723 | return ret; | |
1724 | ||
3e373948 | 1725 | if (dev_priv->ips.pwrctx) { |
267f0c90 | 1726 | seq_puts(m, "power context "); |
3e373948 | 1727 | describe_obj(m, dev_priv->ips.pwrctx); |
267f0c90 | 1728 | seq_putc(m, '\n'); |
dc501fbc | 1729 | } |
e76d3630 | 1730 | |
3e373948 | 1731 | if (dev_priv->ips.renderctx) { |
267f0c90 | 1732 | seq_puts(m, "render context "); |
3e373948 | 1733 | describe_obj(m, dev_priv->ips.renderctx); |
267f0c90 | 1734 | seq_putc(m, '\n'); |
dc501fbc | 1735 | } |
e76d3630 | 1736 | |
a33afea5 | 1737 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
b77f6997 CW |
1738 | if (ctx->obj == NULL) |
1739 | continue; | |
1740 | ||
a33afea5 | 1741 | seq_puts(m, "HW context "); |
3ccfd19d | 1742 | describe_ctx(m, ctx); |
a33afea5 BW |
1743 | for_each_ring(ring, dev_priv, i) |
1744 | if (ring->default_context == ctx) | |
1745 | seq_printf(m, "(default context %s) ", ring->name); | |
1746 | ||
1747 | describe_obj(m, ctx->obj); | |
1748 | seq_putc(m, '\n'); | |
a168c293 BW |
1749 | } |
1750 | ||
f3d28878 | 1751 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1752 | |
1753 | return 0; | |
1754 | } | |
1755 | ||
6d794d42 BW |
1756 | static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) |
1757 | { | |
9f25d007 | 1758 | struct drm_info_node *node = m->private; |
6d794d42 BW |
1759 | struct drm_device *dev = node->minor->dev; |
1760 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43709ba0 | 1761 | unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0; |
6d794d42 | 1762 | |
907b28c5 | 1763 | spin_lock_irq(&dev_priv->uncore.lock); |
43709ba0 D |
1764 | if (IS_VALLEYVIEW(dev)) { |
1765 | fw_rendercount = dev_priv->uncore.fw_rendercount; | |
1766 | fw_mediacount = dev_priv->uncore.fw_mediacount; | |
1767 | } else | |
1768 | forcewake_count = dev_priv->uncore.forcewake_count; | |
907b28c5 | 1769 | spin_unlock_irq(&dev_priv->uncore.lock); |
6d794d42 | 1770 | |
43709ba0 D |
1771 | if (IS_VALLEYVIEW(dev)) { |
1772 | seq_printf(m, "fw_rendercount = %u\n", fw_rendercount); | |
1773 | seq_printf(m, "fw_mediacount = %u\n", fw_mediacount); | |
1774 | } else | |
1775 | seq_printf(m, "forcewake count = %u\n", forcewake_count); | |
6d794d42 BW |
1776 | |
1777 | return 0; | |
1778 | } | |
1779 | ||
ea16a3cd DV |
1780 | static const char *swizzle_string(unsigned swizzle) |
1781 | { | |
aee56cff | 1782 | switch (swizzle) { |
ea16a3cd DV |
1783 | case I915_BIT_6_SWIZZLE_NONE: |
1784 | return "none"; | |
1785 | case I915_BIT_6_SWIZZLE_9: | |
1786 | return "bit9"; | |
1787 | case I915_BIT_6_SWIZZLE_9_10: | |
1788 | return "bit9/bit10"; | |
1789 | case I915_BIT_6_SWIZZLE_9_11: | |
1790 | return "bit9/bit11"; | |
1791 | case I915_BIT_6_SWIZZLE_9_10_11: | |
1792 | return "bit9/bit10/bit11"; | |
1793 | case I915_BIT_6_SWIZZLE_9_17: | |
1794 | return "bit9/bit17"; | |
1795 | case I915_BIT_6_SWIZZLE_9_10_17: | |
1796 | return "bit9/bit10/bit17"; | |
1797 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 1798 | return "unknown"; |
ea16a3cd DV |
1799 | } |
1800 | ||
1801 | return "bug"; | |
1802 | } | |
1803 | ||
1804 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
1805 | { | |
9f25d007 | 1806 | struct drm_info_node *node = m->private; |
ea16a3cd DV |
1807 | struct drm_device *dev = node->minor->dev; |
1808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
1809 | int ret; |
1810 | ||
1811 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1812 | if (ret) | |
1813 | return ret; | |
c8c8fb33 | 1814 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 1815 | |
ea16a3cd DV |
1816 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
1817 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
1818 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
1819 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
1820 | ||
1821 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
1822 | seq_printf(m, "DDC = 0x%08x\n", | |
1823 | I915_READ(DCC)); | |
1824 | seq_printf(m, "C0DRB3 = 0x%04x\n", | |
1825 | I915_READ16(C0DRB3)); | |
1826 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
1827 | I915_READ16(C1DRB3)); | |
9d3203e1 | 1828 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
1829 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
1830 | I915_READ(MAD_DIMM_C0)); | |
1831 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
1832 | I915_READ(MAD_DIMM_C1)); | |
1833 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
1834 | I915_READ(MAD_DIMM_C2)); | |
1835 | seq_printf(m, "TILECTL = 0x%08x\n", | |
1836 | I915_READ(TILECTL)); | |
9d3203e1 BW |
1837 | if (IS_GEN8(dev)) |
1838 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", | |
1839 | I915_READ(GAMTARBMODE)); | |
1840 | else | |
1841 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
1842 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
1843 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
1844 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 1845 | } |
c8c8fb33 | 1846 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
1847 | mutex_unlock(&dev->struct_mutex); |
1848 | ||
1849 | return 0; | |
1850 | } | |
1851 | ||
1c60fef5 BW |
1852 | static int per_file_ctx(int id, void *ptr, void *data) |
1853 | { | |
273497e5 | 1854 | struct intel_context *ctx = ptr; |
1c60fef5 BW |
1855 | struct seq_file *m = data; |
1856 | struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx); | |
1857 | ||
f83d6518 OM |
1858 | if (i915_gem_context_is_default(ctx)) |
1859 | seq_puts(m, " default context:\n"); | |
1860 | else | |
1861 | seq_printf(m, " context %d:\n", ctx->id); | |
1c60fef5 BW |
1862 | ppgtt->debug_dump(ppgtt, m); |
1863 | ||
1864 | return 0; | |
1865 | } | |
1866 | ||
77df6772 | 1867 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 1868 | { |
3cf17fc5 | 1869 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1870 | struct intel_engine_cs *ring; |
77df6772 BW |
1871 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1872 | int unused, i; | |
3cf17fc5 | 1873 | |
77df6772 BW |
1874 | if (!ppgtt) |
1875 | return; | |
1876 | ||
1877 | seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); | |
5abbcca3 | 1878 | seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); |
77df6772 BW |
1879 | for_each_ring(ring, dev_priv, unused) { |
1880 | seq_printf(m, "%s\n", ring->name); | |
1881 | for (i = 0; i < 4; i++) { | |
1882 | u32 offset = 0x270 + i * 8; | |
1883 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); | |
1884 | pdp <<= 32; | |
1885 | pdp |= I915_READ(ring->mmio_base + offset); | |
a2a5b15c | 1886 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
1887 | } |
1888 | } | |
1889 | } | |
1890 | ||
1891 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
1892 | { | |
1893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1894 | struct intel_engine_cs *ring; |
1c60fef5 | 1895 | struct drm_file *file; |
77df6772 | 1896 | int i; |
3cf17fc5 | 1897 | |
3cf17fc5 DV |
1898 | if (INTEL_INFO(dev)->gen == 6) |
1899 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
1900 | ||
a2c7f6fd | 1901 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
1902 | seq_printf(m, "%s\n", ring->name); |
1903 | if (INTEL_INFO(dev)->gen == 7) | |
1904 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
1905 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
1906 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
1907 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
1908 | } | |
1909 | if (dev_priv->mm.aliasing_ppgtt) { | |
1910 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1911 | ||
267f0c90 | 1912 | seq_puts(m, "aliasing PPGTT:\n"); |
3cf17fc5 | 1913 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset); |
1c60fef5 | 1914 | |
87d60b63 | 1915 | ppgtt->debug_dump(ppgtt, m); |
1c60fef5 BW |
1916 | } else |
1917 | return; | |
1918 | ||
1919 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { | |
1920 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1c60fef5 | 1921 | |
1c60fef5 BW |
1922 | seq_printf(m, "proc: %s\n", |
1923 | get_pid_task(file->pid, PIDTYPE_PID)->comm); | |
1c60fef5 | 1924 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); |
3cf17fc5 DV |
1925 | } |
1926 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
77df6772 BW |
1927 | } |
1928 | ||
1929 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
1930 | { | |
9f25d007 | 1931 | struct drm_info_node *node = m->private; |
77df6772 | 1932 | struct drm_device *dev = node->minor->dev; |
c8c8fb33 | 1933 | struct drm_i915_private *dev_priv = dev->dev_private; |
77df6772 BW |
1934 | |
1935 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1936 | if (ret) | |
1937 | return ret; | |
c8c8fb33 | 1938 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
1939 | |
1940 | if (INTEL_INFO(dev)->gen >= 8) | |
1941 | gen8_ppgtt_info(m, dev); | |
1942 | else if (INTEL_INFO(dev)->gen >= 6) | |
1943 | gen6_ppgtt_info(m, dev); | |
1944 | ||
c8c8fb33 | 1945 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
1946 | mutex_unlock(&dev->struct_mutex); |
1947 | ||
1948 | return 0; | |
1949 | } | |
1950 | ||
63573eb7 BW |
1951 | static int i915_llc(struct seq_file *m, void *data) |
1952 | { | |
9f25d007 | 1953 | struct drm_info_node *node = m->private; |
63573eb7 BW |
1954 | struct drm_device *dev = node->minor->dev; |
1955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1956 | ||
1957 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
1958 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
1959 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
1960 | ||
1961 | return 0; | |
1962 | } | |
1963 | ||
e91fd8c6 RV |
1964 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
1965 | { | |
1966 | struct drm_info_node *node = m->private; | |
1967 | struct drm_device *dev = node->minor->dev; | |
1968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 RV |
1969 | u32 psrperf = 0; |
1970 | bool enabled = false; | |
e91fd8c6 | 1971 | |
c8c8fb33 PZ |
1972 | intel_runtime_pm_get(dev_priv); |
1973 | ||
a031d709 RV |
1974 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
1975 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
e91fd8c6 | 1976 | |
a031d709 RV |
1977 | enabled = HAS_PSR(dev) && |
1978 | I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
1979 | seq_printf(m, "Enabled: %s\n", yesno(enabled)); | |
e91fd8c6 | 1980 | |
a031d709 RV |
1981 | if (HAS_PSR(dev)) |
1982 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & | |
1983 | EDP_PSR_PERF_CNT_MASK; | |
1984 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
e91fd8c6 | 1985 | |
c8c8fb33 | 1986 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
1987 | return 0; |
1988 | } | |
1989 | ||
d2e216d0 RV |
1990 | static int i915_sink_crc(struct seq_file *m, void *data) |
1991 | { | |
1992 | struct drm_info_node *node = m->private; | |
1993 | struct drm_device *dev = node->minor->dev; | |
1994 | struct intel_encoder *encoder; | |
1995 | struct intel_connector *connector; | |
1996 | struct intel_dp *intel_dp = NULL; | |
1997 | int ret; | |
1998 | u8 crc[6]; | |
1999 | ||
2000 | drm_modeset_lock_all(dev); | |
2001 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
2002 | base.head) { | |
2003 | ||
2004 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
2005 | continue; | |
2006 | ||
b6ae3c7c PZ |
2007 | if (!connector->base.encoder) |
2008 | continue; | |
2009 | ||
d2e216d0 RV |
2010 | encoder = to_intel_encoder(connector->base.encoder); |
2011 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2012 | continue; | |
2013 | ||
2014 | intel_dp = enc_to_intel_dp(&encoder->base); | |
2015 | ||
2016 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2017 | if (ret) | |
2018 | goto out; | |
2019 | ||
2020 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2021 | crc[0], crc[1], crc[2], | |
2022 | crc[3], crc[4], crc[5]); | |
2023 | goto out; | |
2024 | } | |
2025 | ret = -ENODEV; | |
2026 | out: | |
2027 | drm_modeset_unlock_all(dev); | |
2028 | return ret; | |
2029 | } | |
2030 | ||
ec013e7f JB |
2031 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2032 | { | |
2033 | struct drm_info_node *node = m->private; | |
2034 | struct drm_device *dev = node->minor->dev; | |
2035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2036 | u64 power; | |
2037 | u32 units; | |
2038 | ||
2039 | if (INTEL_INFO(dev)->gen < 6) | |
2040 | return -ENODEV; | |
2041 | ||
36623ef8 PZ |
2042 | intel_runtime_pm_get(dev_priv); |
2043 | ||
ec013e7f JB |
2044 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2045 | power = (power & 0x1f00) >> 8; | |
2046 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2047 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2048 | power *= units; | |
2049 | ||
36623ef8 PZ |
2050 | intel_runtime_pm_put(dev_priv); |
2051 | ||
ec013e7f | 2052 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2053 | |
2054 | return 0; | |
2055 | } | |
2056 | ||
2057 | static int i915_pc8_status(struct seq_file *m, void *unused) | |
2058 | { | |
9f25d007 | 2059 | struct drm_info_node *node = m->private; |
371db66a PZ |
2060 | struct drm_device *dev = node->minor->dev; |
2061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2062 | ||
85b8d5c2 | 2063 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { |
371db66a PZ |
2064 | seq_puts(m, "not supported\n"); |
2065 | return 0; | |
2066 | } | |
2067 | ||
86c4ec0d | 2068 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2069 | seq_printf(m, "IRQs disabled: %s\n", |
5d584b2e | 2070 | yesno(dev_priv->pm.irqs_disabled)); |
371db66a | 2071 | |
ec013e7f JB |
2072 | return 0; |
2073 | } | |
2074 | ||
1da51581 ID |
2075 | static const char *power_domain_str(enum intel_display_power_domain domain) |
2076 | { | |
2077 | switch (domain) { | |
2078 | case POWER_DOMAIN_PIPE_A: | |
2079 | return "PIPE_A"; | |
2080 | case POWER_DOMAIN_PIPE_B: | |
2081 | return "PIPE_B"; | |
2082 | case POWER_DOMAIN_PIPE_C: | |
2083 | return "PIPE_C"; | |
2084 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
2085 | return "PIPE_A_PANEL_FITTER"; | |
2086 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
2087 | return "PIPE_B_PANEL_FITTER"; | |
2088 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
2089 | return "PIPE_C_PANEL_FITTER"; | |
2090 | case POWER_DOMAIN_TRANSCODER_A: | |
2091 | return "TRANSCODER_A"; | |
2092 | case POWER_DOMAIN_TRANSCODER_B: | |
2093 | return "TRANSCODER_B"; | |
2094 | case POWER_DOMAIN_TRANSCODER_C: | |
2095 | return "TRANSCODER_C"; | |
2096 | case POWER_DOMAIN_TRANSCODER_EDP: | |
2097 | return "TRANSCODER_EDP"; | |
319be8ae ID |
2098 | case POWER_DOMAIN_PORT_DDI_A_2_LANES: |
2099 | return "PORT_DDI_A_2_LANES"; | |
2100 | case POWER_DOMAIN_PORT_DDI_A_4_LANES: | |
2101 | return "PORT_DDI_A_4_LANES"; | |
2102 | case POWER_DOMAIN_PORT_DDI_B_2_LANES: | |
2103 | return "PORT_DDI_B_2_LANES"; | |
2104 | case POWER_DOMAIN_PORT_DDI_B_4_LANES: | |
2105 | return "PORT_DDI_B_4_LANES"; | |
2106 | case POWER_DOMAIN_PORT_DDI_C_2_LANES: | |
2107 | return "PORT_DDI_C_2_LANES"; | |
2108 | case POWER_DOMAIN_PORT_DDI_C_4_LANES: | |
2109 | return "PORT_DDI_C_4_LANES"; | |
2110 | case POWER_DOMAIN_PORT_DDI_D_2_LANES: | |
2111 | return "PORT_DDI_D_2_LANES"; | |
2112 | case POWER_DOMAIN_PORT_DDI_D_4_LANES: | |
2113 | return "PORT_DDI_D_4_LANES"; | |
2114 | case POWER_DOMAIN_PORT_DSI: | |
2115 | return "PORT_DSI"; | |
2116 | case POWER_DOMAIN_PORT_CRT: | |
2117 | return "PORT_CRT"; | |
2118 | case POWER_DOMAIN_PORT_OTHER: | |
2119 | return "PORT_OTHER"; | |
1da51581 ID |
2120 | case POWER_DOMAIN_VGA: |
2121 | return "VGA"; | |
2122 | case POWER_DOMAIN_AUDIO: | |
2123 | return "AUDIO"; | |
2124 | case POWER_DOMAIN_INIT: | |
2125 | return "INIT"; | |
2126 | default: | |
2127 | WARN_ON(1); | |
2128 | return "?"; | |
2129 | } | |
2130 | } | |
2131 | ||
2132 | static int i915_power_domain_info(struct seq_file *m, void *unused) | |
2133 | { | |
9f25d007 | 2134 | struct drm_info_node *node = m->private; |
1da51581 ID |
2135 | struct drm_device *dev = node->minor->dev; |
2136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2137 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2138 | int i; | |
2139 | ||
2140 | mutex_lock(&power_domains->lock); | |
2141 | ||
2142 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2143 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2144 | struct i915_power_well *power_well; | |
2145 | enum intel_display_power_domain power_domain; | |
2146 | ||
2147 | power_well = &power_domains->power_wells[i]; | |
2148 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2149 | power_well->count); | |
2150 | ||
2151 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2152 | power_domain++) { | |
2153 | if (!(BIT(power_domain) & power_well->domains)) | |
2154 | continue; | |
2155 | ||
2156 | seq_printf(m, " %-23s %d\n", | |
2157 | power_domain_str(power_domain), | |
2158 | power_domains->domain_use_count[power_domain]); | |
2159 | } | |
2160 | } | |
2161 | ||
2162 | mutex_unlock(&power_domains->lock); | |
2163 | ||
2164 | return 0; | |
2165 | } | |
2166 | ||
53f5e3ca JB |
2167 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2168 | struct drm_display_mode *mode) | |
2169 | { | |
2170 | int i; | |
2171 | ||
2172 | for (i = 0; i < tabs; i++) | |
2173 | seq_putc(m, '\t'); | |
2174 | ||
2175 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2176 | mode->base.id, mode->name, | |
2177 | mode->vrefresh, mode->clock, | |
2178 | mode->hdisplay, mode->hsync_start, | |
2179 | mode->hsync_end, mode->htotal, | |
2180 | mode->vdisplay, mode->vsync_start, | |
2181 | mode->vsync_end, mode->vtotal, | |
2182 | mode->type, mode->flags); | |
2183 | } | |
2184 | ||
2185 | static void intel_encoder_info(struct seq_file *m, | |
2186 | struct intel_crtc *intel_crtc, | |
2187 | struct intel_encoder *intel_encoder) | |
2188 | { | |
9f25d007 | 2189 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2190 | struct drm_device *dev = node->minor->dev; |
2191 | struct drm_crtc *crtc = &intel_crtc->base; | |
2192 | struct intel_connector *intel_connector; | |
2193 | struct drm_encoder *encoder; | |
2194 | ||
2195 | encoder = &intel_encoder->base; | |
2196 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2197 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2198 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2199 | struct drm_connector *connector = &intel_connector->base; | |
2200 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2201 | connector->base.id, | |
c23cc417 | 2202 | connector->name, |
53f5e3ca JB |
2203 | drm_get_connector_status_name(connector->status)); |
2204 | if (connector->status == connector_status_connected) { | |
2205 | struct drm_display_mode *mode = &crtc->mode; | |
2206 | seq_printf(m, ", mode:\n"); | |
2207 | intel_seq_print_mode(m, 2, mode); | |
2208 | } else { | |
2209 | seq_putc(m, '\n'); | |
2210 | } | |
2211 | } | |
2212 | } | |
2213 | ||
2214 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2215 | { | |
9f25d007 | 2216 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2217 | struct drm_device *dev = node->minor->dev; |
2218 | struct drm_crtc *crtc = &intel_crtc->base; | |
2219 | struct intel_encoder *intel_encoder; | |
2220 | ||
2221 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", | |
f4510a27 MR |
2222 | crtc->primary->fb->base.id, crtc->x, crtc->y, |
2223 | crtc->primary->fb->width, crtc->primary->fb->height); | |
53f5e3ca JB |
2224 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2225 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2226 | } | |
2227 | ||
2228 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2229 | { | |
2230 | struct drm_display_mode *mode = panel->fixed_mode; | |
2231 | ||
2232 | seq_printf(m, "\tfixed mode:\n"); | |
2233 | intel_seq_print_mode(m, 2, mode); | |
2234 | } | |
2235 | ||
2236 | static void intel_dp_info(struct seq_file *m, | |
2237 | struct intel_connector *intel_connector) | |
2238 | { | |
2239 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2240 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2241 | ||
2242 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
2243 | seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : | |
2244 | "no"); | |
2245 | if (intel_encoder->type == INTEL_OUTPUT_EDP) | |
2246 | intel_panel_info(m, &intel_connector->panel); | |
2247 | } | |
2248 | ||
2249 | static void intel_hdmi_info(struct seq_file *m, | |
2250 | struct intel_connector *intel_connector) | |
2251 | { | |
2252 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2253 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2254 | ||
2255 | seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : | |
2256 | "no"); | |
2257 | } | |
2258 | ||
2259 | static void intel_lvds_info(struct seq_file *m, | |
2260 | struct intel_connector *intel_connector) | |
2261 | { | |
2262 | intel_panel_info(m, &intel_connector->panel); | |
2263 | } | |
2264 | ||
2265 | static void intel_connector_info(struct seq_file *m, | |
2266 | struct drm_connector *connector) | |
2267 | { | |
2268 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2269 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2270 | struct drm_display_mode *mode; |
53f5e3ca JB |
2271 | |
2272 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2273 | connector->base.id, connector->name, |
53f5e3ca JB |
2274 | drm_get_connector_status_name(connector->status)); |
2275 | if (connector->status == connector_status_connected) { | |
2276 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2277 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2278 | connector->display_info.width_mm, | |
2279 | connector->display_info.height_mm); | |
2280 | seq_printf(m, "\tsubpixel order: %s\n", | |
2281 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2282 | seq_printf(m, "\tCEA rev: %d\n", | |
2283 | connector->display_info.cea_rev); | |
2284 | } | |
2285 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2286 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2287 | intel_dp_info(m, intel_connector); | |
2288 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2289 | intel_hdmi_info(m, intel_connector); | |
2290 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2291 | intel_lvds_info(m, intel_connector); | |
2292 | ||
f103fc7d JB |
2293 | seq_printf(m, "\tmodes:\n"); |
2294 | list_for_each_entry(mode, &connector->modes, head) | |
2295 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2296 | } |
2297 | ||
065f2ec2 CW |
2298 | static bool cursor_active(struct drm_device *dev, int pipe) |
2299 | { | |
2300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2301 | u32 state; | |
2302 | ||
2303 | if (IS_845G(dev) || IS_I865G(dev)) | |
2304 | state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
065f2ec2 | 2305 | else |
5efb3e28 | 2306 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2307 | |
2308 | return state; | |
2309 | } | |
2310 | ||
2311 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2312 | { | |
2313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2314 | u32 pos; | |
2315 | ||
5efb3e28 | 2316 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2317 | |
2318 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2319 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2320 | *x = -*x; | |
2321 | ||
2322 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2323 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2324 | *y = -*y; | |
2325 | ||
2326 | return cursor_active(dev, pipe); | |
2327 | } | |
2328 | ||
53f5e3ca JB |
2329 | static int i915_display_info(struct seq_file *m, void *unused) |
2330 | { | |
9f25d007 | 2331 | struct drm_info_node *node = m->private; |
53f5e3ca | 2332 | struct drm_device *dev = node->minor->dev; |
b0e5ddf3 | 2333 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 2334 | struct intel_crtc *crtc; |
53f5e3ca JB |
2335 | struct drm_connector *connector; |
2336 | ||
b0e5ddf3 | 2337 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
2338 | drm_modeset_lock_all(dev); |
2339 | seq_printf(m, "CRTC info\n"); | |
2340 | seq_printf(m, "---------\n"); | |
d3fcc808 | 2341 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 CW |
2342 | bool active; |
2343 | int x, y; | |
53f5e3ca JB |
2344 | |
2345 | seq_printf(m, "CRTC %d: pipe: %c, active: %s\n", | |
065f2ec2 CW |
2346 | crtc->base.base.id, pipe_name(crtc->pipe), |
2347 | yesno(crtc->active)); | |
a23dc658 | 2348 | if (crtc->active) { |
065f2ec2 CW |
2349 | intel_crtc_info(m, crtc); |
2350 | ||
a23dc658 PZ |
2351 | active = cursor_position(dev, crtc->pipe, &x, &y); |
2352 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n", | |
4b0e333e | 2353 | yesno(crtc->cursor_base), |
a23dc658 PZ |
2354 | x, y, crtc->cursor_addr, |
2355 | yesno(active)); | |
2356 | } | |
cace841c DV |
2357 | |
2358 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
2359 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
2360 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
2361 | } |
2362 | ||
2363 | seq_printf(m, "\n"); | |
2364 | seq_printf(m, "Connector info\n"); | |
2365 | seq_printf(m, "--------------\n"); | |
2366 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2367 | intel_connector_info(m, connector); | |
2368 | } | |
2369 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 2370 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
2371 | |
2372 | return 0; | |
2373 | } | |
2374 | ||
07144428 DL |
2375 | struct pipe_crc_info { |
2376 | const char *name; | |
2377 | struct drm_device *dev; | |
2378 | enum pipe pipe; | |
2379 | }; | |
2380 | ||
2381 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) | |
2382 | { | |
be5c7a90 DL |
2383 | struct pipe_crc_info *info = inode->i_private; |
2384 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2385 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2386 | ||
7eb1c496 DV |
2387 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
2388 | return -ENODEV; | |
2389 | ||
d538bbdf DL |
2390 | spin_lock_irq(&pipe_crc->lock); |
2391 | ||
2392 | if (pipe_crc->opened) { | |
2393 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
2394 | return -EBUSY; /* already open */ |
2395 | } | |
2396 | ||
d538bbdf | 2397 | pipe_crc->opened = true; |
07144428 DL |
2398 | filep->private_data = inode->i_private; |
2399 | ||
d538bbdf DL |
2400 | spin_unlock_irq(&pipe_crc->lock); |
2401 | ||
07144428 DL |
2402 | return 0; |
2403 | } | |
2404 | ||
2405 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
2406 | { | |
be5c7a90 DL |
2407 | struct pipe_crc_info *info = inode->i_private; |
2408 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
2409 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2410 | ||
d538bbdf DL |
2411 | spin_lock_irq(&pipe_crc->lock); |
2412 | pipe_crc->opened = false; | |
2413 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 2414 | |
07144428 DL |
2415 | return 0; |
2416 | } | |
2417 | ||
2418 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
2419 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
2420 | /* account for \'0' */ | |
2421 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
2422 | ||
2423 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 2424 | { |
d538bbdf DL |
2425 | assert_spin_locked(&pipe_crc->lock); |
2426 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
2427 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
2428 | } |
2429 | ||
2430 | static ssize_t | |
2431 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
2432 | loff_t *pos) | |
2433 | { | |
2434 | struct pipe_crc_info *info = filep->private_data; | |
2435 | struct drm_device *dev = info->dev; | |
2436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2437 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
2438 | char buf[PIPE_CRC_BUFFER_LEN]; | |
2439 | int head, tail, n_entries, n; | |
2440 | ssize_t bytes_read; | |
2441 | ||
2442 | /* | |
2443 | * Don't allow user space to provide buffers not big enough to hold | |
2444 | * a line of data. | |
2445 | */ | |
2446 | if (count < PIPE_CRC_LINE_LEN) | |
2447 | return -EINVAL; | |
2448 | ||
2449 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 2450 | return 0; |
07144428 DL |
2451 | |
2452 | /* nothing to read */ | |
d538bbdf | 2453 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 2454 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
2455 | int ret; |
2456 | ||
2457 | if (filep->f_flags & O_NONBLOCK) { | |
2458 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 2459 | return -EAGAIN; |
d538bbdf | 2460 | } |
07144428 | 2461 | |
d538bbdf DL |
2462 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
2463 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
2464 | if (ret) { | |
2465 | spin_unlock_irq(&pipe_crc->lock); | |
2466 | return ret; | |
2467 | } | |
8bf1e9f1 SH |
2468 | } |
2469 | ||
07144428 | 2470 | /* We now have one or more entries to read */ |
d538bbdf DL |
2471 | head = pipe_crc->head; |
2472 | tail = pipe_crc->tail; | |
07144428 DL |
2473 | n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR), |
2474 | count / PIPE_CRC_LINE_LEN); | |
d538bbdf DL |
2475 | spin_unlock_irq(&pipe_crc->lock); |
2476 | ||
07144428 DL |
2477 | bytes_read = 0; |
2478 | n = 0; | |
2479 | do { | |
b2c88f5b | 2480 | struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail]; |
07144428 | 2481 | int ret; |
8bf1e9f1 | 2482 | |
07144428 DL |
2483 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
2484 | "%8u %8x %8x %8x %8x %8x\n", | |
2485 | entry->frame, entry->crc[0], | |
2486 | entry->crc[1], entry->crc[2], | |
2487 | entry->crc[3], entry->crc[4]); | |
2488 | ||
2489 | ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN, | |
2490 | buf, PIPE_CRC_LINE_LEN); | |
2491 | if (ret == PIPE_CRC_LINE_LEN) | |
2492 | return -EFAULT; | |
b2c88f5b DL |
2493 | |
2494 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
2495 | tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
07144428 DL |
2496 | n++; |
2497 | } while (--n_entries); | |
8bf1e9f1 | 2498 | |
d538bbdf DL |
2499 | spin_lock_irq(&pipe_crc->lock); |
2500 | pipe_crc->tail = tail; | |
2501 | spin_unlock_irq(&pipe_crc->lock); | |
2502 | ||
07144428 DL |
2503 | return bytes_read; |
2504 | } | |
2505 | ||
2506 | static const struct file_operations i915_pipe_crc_fops = { | |
2507 | .owner = THIS_MODULE, | |
2508 | .open = i915_pipe_crc_open, | |
2509 | .read = i915_pipe_crc_read, | |
2510 | .release = i915_pipe_crc_release, | |
2511 | }; | |
2512 | ||
2513 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
2514 | { | |
2515 | .name = "i915_pipe_A_crc", | |
2516 | .pipe = PIPE_A, | |
2517 | }, | |
2518 | { | |
2519 | .name = "i915_pipe_B_crc", | |
2520 | .pipe = PIPE_B, | |
2521 | }, | |
2522 | { | |
2523 | .name = "i915_pipe_C_crc", | |
2524 | .pipe = PIPE_C, | |
2525 | }, | |
2526 | }; | |
2527 | ||
2528 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
2529 | enum pipe pipe) | |
2530 | { | |
2531 | struct drm_device *dev = minor->dev; | |
2532 | struct dentry *ent; | |
2533 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
2534 | ||
2535 | info->dev = dev; | |
2536 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
2537 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
2538 | if (!ent) |
2539 | return -ENOMEM; | |
07144428 DL |
2540 | |
2541 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
2542 | } |
2543 | ||
e8dfcf78 | 2544 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
2545 | "none", |
2546 | "plane1", | |
2547 | "plane2", | |
2548 | "pf", | |
5b3a856b | 2549 | "pipe", |
3d099a05 DV |
2550 | "TV", |
2551 | "DP-B", | |
2552 | "DP-C", | |
2553 | "DP-D", | |
46a19188 | 2554 | "auto", |
926321d5 DV |
2555 | }; |
2556 | ||
2557 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
2558 | { | |
2559 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
2560 | return pipe_crc_sources[source]; | |
2561 | } | |
2562 | ||
bd9db02f | 2563 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
2564 | { |
2565 | struct drm_device *dev = m->private; | |
2566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2567 | int i; | |
2568 | ||
2569 | for (i = 0; i < I915_MAX_PIPES; i++) | |
2570 | seq_printf(m, "%c %s\n", pipe_name(i), | |
2571 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
2572 | ||
2573 | return 0; | |
2574 | } | |
2575 | ||
bd9db02f | 2576 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
2577 | { |
2578 | struct drm_device *dev = inode->i_private; | |
2579 | ||
bd9db02f | 2580 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
2581 | } |
2582 | ||
46a19188 | 2583 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
2584 | uint32_t *val) |
2585 | { | |
46a19188 DV |
2586 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2587 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2588 | ||
2589 | switch (*source) { | |
52f843f6 DV |
2590 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2591 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
2592 | break; | |
2593 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2594 | *val = 0; | |
2595 | break; | |
2596 | default: | |
2597 | return -EINVAL; | |
2598 | } | |
2599 | ||
2600 | return 0; | |
2601 | } | |
2602 | ||
46a19188 DV |
2603 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
2604 | enum intel_pipe_crc_source *source) | |
2605 | { | |
2606 | struct intel_encoder *encoder; | |
2607 | struct intel_crtc *crtc; | |
26756809 | 2608 | struct intel_digital_port *dig_port; |
46a19188 DV |
2609 | int ret = 0; |
2610 | ||
2611 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2612 | ||
6e9f798d | 2613 | drm_modeset_lock_all(dev); |
46a19188 DV |
2614 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
2615 | base.head) { | |
2616 | if (!encoder->base.crtc) | |
2617 | continue; | |
2618 | ||
2619 | crtc = to_intel_crtc(encoder->base.crtc); | |
2620 | ||
2621 | if (crtc->pipe != pipe) | |
2622 | continue; | |
2623 | ||
2624 | switch (encoder->type) { | |
2625 | case INTEL_OUTPUT_TVOUT: | |
2626 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
2627 | break; | |
2628 | case INTEL_OUTPUT_DISPLAYPORT: | |
2629 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
2630 | dig_port = enc_to_dig_port(&encoder->base); |
2631 | switch (dig_port->port) { | |
2632 | case PORT_B: | |
2633 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
2634 | break; | |
2635 | case PORT_C: | |
2636 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
2637 | break; | |
2638 | case PORT_D: | |
2639 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
2640 | break; | |
2641 | default: | |
2642 | WARN(1, "nonexisting DP port %c\n", | |
2643 | port_name(dig_port->port)); | |
2644 | break; | |
2645 | } | |
46a19188 DV |
2646 | break; |
2647 | } | |
2648 | } | |
6e9f798d | 2649 | drm_modeset_unlock_all(dev); |
46a19188 DV |
2650 | |
2651 | return ret; | |
2652 | } | |
2653 | ||
2654 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
2655 | enum pipe pipe, | |
2656 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
2657 | uint32_t *val) |
2658 | { | |
8d2f24ca DV |
2659 | struct drm_i915_private *dev_priv = dev->dev_private; |
2660 | bool need_stable_symbols = false; | |
2661 | ||
46a19188 DV |
2662 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2663 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2664 | if (ret) | |
2665 | return ret; | |
2666 | } | |
2667 | ||
2668 | switch (*source) { | |
7ac0129b DV |
2669 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2670 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
2671 | break; | |
2672 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2673 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 2674 | need_stable_symbols = true; |
7ac0129b DV |
2675 | break; |
2676 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2677 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 2678 | need_stable_symbols = true; |
7ac0129b DV |
2679 | break; |
2680 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2681 | *val = 0; | |
2682 | break; | |
2683 | default: | |
2684 | return -EINVAL; | |
2685 | } | |
2686 | ||
8d2f24ca DV |
2687 | /* |
2688 | * When the pipe CRC tap point is after the transcoders we need | |
2689 | * to tweak symbol-level features to produce a deterministic series of | |
2690 | * symbols for a given frame. We need to reset those features only once | |
2691 | * a frame (instead of every nth symbol): | |
2692 | * - DC-balance: used to ensure a better clock recovery from the data | |
2693 | * link (SDVO) | |
2694 | * - DisplayPort scrambling: used for EMI reduction | |
2695 | */ | |
2696 | if (need_stable_symbols) { | |
2697 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2698 | ||
8d2f24ca DV |
2699 | tmp |= DC_BALANCE_RESET_VLV; |
2700 | if (pipe == PIPE_A) | |
2701 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2702 | else | |
2703 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2704 | ||
2705 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2706 | } | |
2707 | ||
7ac0129b DV |
2708 | return 0; |
2709 | } | |
2710 | ||
4b79ebf7 | 2711 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
2712 | enum pipe pipe, |
2713 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
2714 | uint32_t *val) |
2715 | { | |
84093603 DV |
2716 | struct drm_i915_private *dev_priv = dev->dev_private; |
2717 | bool need_stable_symbols = false; | |
2718 | ||
46a19188 DV |
2719 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
2720 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
2721 | if (ret) | |
2722 | return ret; | |
2723 | } | |
2724 | ||
2725 | switch (*source) { | |
4b79ebf7 DV |
2726 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2727 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
2728 | break; | |
2729 | case INTEL_PIPE_CRC_SOURCE_TV: | |
2730 | if (!SUPPORTS_TV(dev)) | |
2731 | return -EINVAL; | |
2732 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
2733 | break; | |
2734 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
2735 | if (!IS_G4X(dev)) | |
2736 | return -EINVAL; | |
2737 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 2738 | need_stable_symbols = true; |
4b79ebf7 DV |
2739 | break; |
2740 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
2741 | if (!IS_G4X(dev)) | |
2742 | return -EINVAL; | |
2743 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 2744 | need_stable_symbols = true; |
4b79ebf7 DV |
2745 | break; |
2746 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
2747 | if (!IS_G4X(dev)) | |
2748 | return -EINVAL; | |
2749 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 2750 | need_stable_symbols = true; |
4b79ebf7 DV |
2751 | break; |
2752 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
2753 | *val = 0; | |
2754 | break; | |
2755 | default: | |
2756 | return -EINVAL; | |
2757 | } | |
2758 | ||
84093603 DV |
2759 | /* |
2760 | * When the pipe CRC tap point is after the transcoders we need | |
2761 | * to tweak symbol-level features to produce a deterministic series of | |
2762 | * symbols for a given frame. We need to reset those features only once | |
2763 | * a frame (instead of every nth symbol): | |
2764 | * - DC-balance: used to ensure a better clock recovery from the data | |
2765 | * link (SDVO) | |
2766 | * - DisplayPort scrambling: used for EMI reduction | |
2767 | */ | |
2768 | if (need_stable_symbols) { | |
2769 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2770 | ||
2771 | WARN_ON(!IS_G4X(dev)); | |
2772 | ||
2773 | I915_WRITE(PORT_DFT_I9XX, | |
2774 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
2775 | ||
2776 | if (pipe == PIPE_A) | |
2777 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
2778 | else | |
2779 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
2780 | ||
2781 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2782 | } | |
2783 | ||
4b79ebf7 DV |
2784 | return 0; |
2785 | } | |
2786 | ||
8d2f24ca DV |
2787 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
2788 | enum pipe pipe) | |
2789 | { | |
2790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2791 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2792 | ||
2793 | if (pipe == PIPE_A) | |
2794 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2795 | else | |
2796 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2797 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) | |
2798 | tmp &= ~DC_BALANCE_RESET_VLV; | |
2799 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2800 | ||
2801 | } | |
2802 | ||
84093603 DV |
2803 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
2804 | enum pipe pipe) | |
2805 | { | |
2806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2807 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
2808 | ||
2809 | if (pipe == PIPE_A) | |
2810 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
2811 | else | |
2812 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
2813 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
2814 | ||
2815 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
2816 | I915_WRITE(PORT_DFT_I9XX, | |
2817 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
2818 | } | |
2819 | } | |
2820 | ||
46a19188 | 2821 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2822 | uint32_t *val) |
2823 | { | |
46a19188 DV |
2824 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2825 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
2826 | ||
2827 | switch (*source) { | |
5b3a856b DV |
2828 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2829 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
2830 | break; | |
2831 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2832 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
2833 | break; | |
5b3a856b DV |
2834 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
2835 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
2836 | break; | |
3d099a05 | 2837 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2838 | *val = 0; |
2839 | break; | |
3d099a05 DV |
2840 | default: |
2841 | return -EINVAL; | |
5b3a856b DV |
2842 | } |
2843 | ||
2844 | return 0; | |
2845 | } | |
2846 | ||
46a19188 | 2847 | static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
2848 | uint32_t *val) |
2849 | { | |
46a19188 DV |
2850 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
2851 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
2852 | ||
2853 | switch (*source) { | |
5b3a856b DV |
2854 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
2855 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
2856 | break; | |
2857 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
2858 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
2859 | break; | |
2860 | case INTEL_PIPE_CRC_SOURCE_PF: | |
2861 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; | |
2862 | break; | |
3d099a05 | 2863 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
2864 | *val = 0; |
2865 | break; | |
3d099a05 DV |
2866 | default: |
2867 | return -EINVAL; | |
5b3a856b DV |
2868 | } |
2869 | ||
2870 | return 0; | |
2871 | } | |
2872 | ||
926321d5 DV |
2873 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
2874 | enum intel_pipe_crc_source source) | |
2875 | { | |
2876 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 2877 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
432f3342 | 2878 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 2879 | int ret; |
926321d5 | 2880 | |
cc3da175 DL |
2881 | if (pipe_crc->source == source) |
2882 | return 0; | |
2883 | ||
ae676fcd DL |
2884 | /* forbid changing the source without going back to 'none' */ |
2885 | if (pipe_crc->source && source) | |
2886 | return -EINVAL; | |
2887 | ||
52f843f6 | 2888 | if (IS_GEN2(dev)) |
46a19188 | 2889 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 2890 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 2891 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
7ac0129b | 2892 | else if (IS_VALLEYVIEW(dev)) |
46a19188 | 2893 | ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val); |
4b79ebf7 | 2894 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 2895 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 2896 | else |
46a19188 | 2897 | ret = ivb_pipe_crc_ctl_reg(&source, &val); |
5b3a856b DV |
2898 | |
2899 | if (ret != 0) | |
2900 | return ret; | |
2901 | ||
4b584369 DL |
2902 | /* none -> real source transition */ |
2903 | if (source) { | |
7cd6ccff DL |
2904 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
2905 | pipe_name(pipe), pipe_crc_source_name(source)); | |
2906 | ||
e5f75aca DL |
2907 | pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) * |
2908 | INTEL_PIPE_CRC_ENTRIES_NR, | |
2909 | GFP_KERNEL); | |
2910 | if (!pipe_crc->entries) | |
2911 | return -ENOMEM; | |
2912 | ||
d538bbdf DL |
2913 | spin_lock_irq(&pipe_crc->lock); |
2914 | pipe_crc->head = 0; | |
2915 | pipe_crc->tail = 0; | |
2916 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
2917 | } |
2918 | ||
cc3da175 | 2919 | pipe_crc->source = source; |
926321d5 | 2920 | |
926321d5 DV |
2921 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
2922 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
2923 | ||
e5f75aca DL |
2924 | /* real source -> none transition */ |
2925 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 2926 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
2927 | struct intel_crtc *crtc = |
2928 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 2929 | |
7cd6ccff DL |
2930 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
2931 | pipe_name(pipe)); | |
2932 | ||
a33d7105 DV |
2933 | drm_modeset_lock(&crtc->base.mutex, NULL); |
2934 | if (crtc->active) | |
2935 | intel_wait_for_vblank(dev, pipe); | |
2936 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 2937 | |
d538bbdf DL |
2938 | spin_lock_irq(&pipe_crc->lock); |
2939 | entries = pipe_crc->entries; | |
e5f75aca | 2940 | pipe_crc->entries = NULL; |
d538bbdf DL |
2941 | spin_unlock_irq(&pipe_crc->lock); |
2942 | ||
2943 | kfree(entries); | |
84093603 DV |
2944 | |
2945 | if (IS_G4X(dev)) | |
2946 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
8d2f24ca DV |
2947 | else if (IS_VALLEYVIEW(dev)) |
2948 | vlv_undo_pipe_scramble_reset(dev, pipe); | |
e5f75aca DL |
2949 | } |
2950 | ||
926321d5 DV |
2951 | return 0; |
2952 | } | |
2953 | ||
2954 | /* | |
2955 | * Parse pipe CRC command strings: | |
b94dec87 DL |
2956 | * command: wsp* object wsp+ name wsp+ source wsp* |
2957 | * object: 'pipe' | |
2958 | * name: (A | B | C) | |
926321d5 DV |
2959 | * source: (none | plane1 | plane2 | pf) |
2960 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
2961 | * | |
2962 | * eg.: | |
b94dec87 DL |
2963 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
2964 | * "pipe A none" -> Stop CRC | |
926321d5 | 2965 | */ |
bd9db02f | 2966 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
2967 | { |
2968 | int n_words = 0; | |
2969 | ||
2970 | while (*buf) { | |
2971 | char *end; | |
2972 | ||
2973 | /* skip leading white space */ | |
2974 | buf = skip_spaces(buf); | |
2975 | if (!*buf) | |
2976 | break; /* end of buffer */ | |
2977 | ||
2978 | /* find end of word */ | |
2979 | for (end = buf; *end && !isspace(*end); end++) | |
2980 | ; | |
2981 | ||
2982 | if (n_words == max_words) { | |
2983 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
2984 | max_words); | |
2985 | return -EINVAL; /* ran out of words[] before bytes */ | |
2986 | } | |
2987 | ||
2988 | if (*end) | |
2989 | *end++ = '\0'; | |
2990 | words[n_words++] = buf; | |
2991 | buf = end; | |
2992 | } | |
2993 | ||
2994 | return n_words; | |
2995 | } | |
2996 | ||
b94dec87 DL |
2997 | enum intel_pipe_crc_object { |
2998 | PIPE_CRC_OBJECT_PIPE, | |
2999 | }; | |
3000 | ||
e8dfcf78 | 3001 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
3002 | "pipe", |
3003 | }; | |
3004 | ||
3005 | static int | |
bd9db02f | 3006 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
3007 | { |
3008 | int i; | |
3009 | ||
3010 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
3011 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 3012 | *o = i; |
b94dec87 DL |
3013 | return 0; |
3014 | } | |
3015 | ||
3016 | return -EINVAL; | |
3017 | } | |
3018 | ||
bd9db02f | 3019 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
3020 | { |
3021 | const char name = buf[0]; | |
3022 | ||
3023 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
3024 | return -EINVAL; | |
3025 | ||
3026 | *pipe = name - 'A'; | |
3027 | ||
3028 | return 0; | |
3029 | } | |
3030 | ||
3031 | static int | |
bd9db02f | 3032 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
3033 | { |
3034 | int i; | |
3035 | ||
3036 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
3037 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 3038 | *s = i; |
926321d5 DV |
3039 | return 0; |
3040 | } | |
3041 | ||
3042 | return -EINVAL; | |
3043 | } | |
3044 | ||
bd9db02f | 3045 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 3046 | { |
b94dec87 | 3047 | #define N_WORDS 3 |
926321d5 | 3048 | int n_words; |
b94dec87 | 3049 | char *words[N_WORDS]; |
926321d5 | 3050 | enum pipe pipe; |
b94dec87 | 3051 | enum intel_pipe_crc_object object; |
926321d5 DV |
3052 | enum intel_pipe_crc_source source; |
3053 | ||
bd9db02f | 3054 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
3055 | if (n_words != N_WORDS) { |
3056 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
3057 | N_WORDS); | |
3058 | return -EINVAL; | |
3059 | } | |
3060 | ||
bd9db02f | 3061 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 3062 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
3063 | return -EINVAL; |
3064 | } | |
3065 | ||
bd9db02f | 3066 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 3067 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
3068 | return -EINVAL; |
3069 | } | |
3070 | ||
bd9db02f | 3071 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 3072 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
3073 | return -EINVAL; |
3074 | } | |
3075 | ||
3076 | return pipe_crc_set_source(dev, pipe, source); | |
3077 | } | |
3078 | ||
bd9db02f DL |
3079 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
3080 | size_t len, loff_t *offp) | |
926321d5 DV |
3081 | { |
3082 | struct seq_file *m = file->private_data; | |
3083 | struct drm_device *dev = m->private; | |
3084 | char *tmpbuf; | |
3085 | int ret; | |
3086 | ||
3087 | if (len == 0) | |
3088 | return 0; | |
3089 | ||
3090 | if (len > PAGE_SIZE - 1) { | |
3091 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
3092 | PAGE_SIZE); | |
3093 | return -E2BIG; | |
3094 | } | |
3095 | ||
3096 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
3097 | if (!tmpbuf) | |
3098 | return -ENOMEM; | |
3099 | ||
3100 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
3101 | ret = -EFAULT; | |
3102 | goto out; | |
3103 | } | |
3104 | tmpbuf[len] = '\0'; | |
3105 | ||
bd9db02f | 3106 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
3107 | |
3108 | out: | |
3109 | kfree(tmpbuf); | |
3110 | if (ret < 0) | |
3111 | return ret; | |
3112 | ||
3113 | *offp += len; | |
3114 | return len; | |
3115 | } | |
3116 | ||
bd9db02f | 3117 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 3118 | .owner = THIS_MODULE, |
bd9db02f | 3119 | .open = display_crc_ctl_open, |
926321d5 DV |
3120 | .read = seq_read, |
3121 | .llseek = seq_lseek, | |
3122 | .release = single_release, | |
bd9db02f | 3123 | .write = display_crc_ctl_write |
926321d5 DV |
3124 | }; |
3125 | ||
369a1342 VS |
3126 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[5]) |
3127 | { | |
3128 | struct drm_device *dev = m->private; | |
546c81fd | 3129 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
3130 | int level; |
3131 | ||
3132 | drm_modeset_lock_all(dev); | |
3133 | ||
3134 | for (level = 0; level < num_levels; level++) { | |
3135 | unsigned int latency = wm[level]; | |
3136 | ||
3137 | /* WM1+ latency values in 0.5us units */ | |
3138 | if (level > 0) | |
3139 | latency *= 5; | |
3140 | ||
3141 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
3142 | level, wm[level], | |
3143 | latency / 10, latency % 10); | |
3144 | } | |
3145 | ||
3146 | drm_modeset_unlock_all(dev); | |
3147 | } | |
3148 | ||
3149 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
3150 | { | |
3151 | struct drm_device *dev = m->private; | |
3152 | ||
3153 | wm_latency_show(m, to_i915(dev)->wm.pri_latency); | |
3154 | ||
3155 | return 0; | |
3156 | } | |
3157 | ||
3158 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
3159 | { | |
3160 | struct drm_device *dev = m->private; | |
3161 | ||
3162 | wm_latency_show(m, to_i915(dev)->wm.spr_latency); | |
3163 | ||
3164 | return 0; | |
3165 | } | |
3166 | ||
3167 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
3168 | { | |
3169 | struct drm_device *dev = m->private; | |
3170 | ||
3171 | wm_latency_show(m, to_i915(dev)->wm.cur_latency); | |
3172 | ||
3173 | return 0; | |
3174 | } | |
3175 | ||
3176 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
3177 | { | |
3178 | struct drm_device *dev = inode->i_private; | |
3179 | ||
3180 | if (!HAS_PCH_SPLIT(dev)) | |
3181 | return -ENODEV; | |
3182 | ||
3183 | return single_open(file, pri_wm_latency_show, dev); | |
3184 | } | |
3185 | ||
3186 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
3187 | { | |
3188 | struct drm_device *dev = inode->i_private; | |
3189 | ||
3190 | if (!HAS_PCH_SPLIT(dev)) | |
3191 | return -ENODEV; | |
3192 | ||
3193 | return single_open(file, spr_wm_latency_show, dev); | |
3194 | } | |
3195 | ||
3196 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
3197 | { | |
3198 | struct drm_device *dev = inode->i_private; | |
3199 | ||
3200 | if (!HAS_PCH_SPLIT(dev)) | |
3201 | return -ENODEV; | |
3202 | ||
3203 | return single_open(file, cur_wm_latency_show, dev); | |
3204 | } | |
3205 | ||
3206 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
3207 | size_t len, loff_t *offp, uint16_t wm[5]) | |
3208 | { | |
3209 | struct seq_file *m = file->private_data; | |
3210 | struct drm_device *dev = m->private; | |
3211 | uint16_t new[5] = { 0 }; | |
546c81fd | 3212 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
3213 | int level; |
3214 | int ret; | |
3215 | char tmp[32]; | |
3216 | ||
3217 | if (len >= sizeof(tmp)) | |
3218 | return -EINVAL; | |
3219 | ||
3220 | if (copy_from_user(tmp, ubuf, len)) | |
3221 | return -EFAULT; | |
3222 | ||
3223 | tmp[len] = '\0'; | |
3224 | ||
3225 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]); | |
3226 | if (ret != num_levels) | |
3227 | return -EINVAL; | |
3228 | ||
3229 | drm_modeset_lock_all(dev); | |
3230 | ||
3231 | for (level = 0; level < num_levels; level++) | |
3232 | wm[level] = new[level]; | |
3233 | ||
3234 | drm_modeset_unlock_all(dev); | |
3235 | ||
3236 | return len; | |
3237 | } | |
3238 | ||
3239 | ||
3240 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
3241 | size_t len, loff_t *offp) | |
3242 | { | |
3243 | struct seq_file *m = file->private_data; | |
3244 | struct drm_device *dev = m->private; | |
3245 | ||
3246 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency); | |
3247 | } | |
3248 | ||
3249 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
3250 | size_t len, loff_t *offp) | |
3251 | { | |
3252 | struct seq_file *m = file->private_data; | |
3253 | struct drm_device *dev = m->private; | |
3254 | ||
3255 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency); | |
3256 | } | |
3257 | ||
3258 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
3259 | size_t len, loff_t *offp) | |
3260 | { | |
3261 | struct seq_file *m = file->private_data; | |
3262 | struct drm_device *dev = m->private; | |
3263 | ||
3264 | return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency); | |
3265 | } | |
3266 | ||
3267 | static const struct file_operations i915_pri_wm_latency_fops = { | |
3268 | .owner = THIS_MODULE, | |
3269 | .open = pri_wm_latency_open, | |
3270 | .read = seq_read, | |
3271 | .llseek = seq_lseek, | |
3272 | .release = single_release, | |
3273 | .write = pri_wm_latency_write | |
3274 | }; | |
3275 | ||
3276 | static const struct file_operations i915_spr_wm_latency_fops = { | |
3277 | .owner = THIS_MODULE, | |
3278 | .open = spr_wm_latency_open, | |
3279 | .read = seq_read, | |
3280 | .llseek = seq_lseek, | |
3281 | .release = single_release, | |
3282 | .write = spr_wm_latency_write | |
3283 | }; | |
3284 | ||
3285 | static const struct file_operations i915_cur_wm_latency_fops = { | |
3286 | .owner = THIS_MODULE, | |
3287 | .open = cur_wm_latency_open, | |
3288 | .read = seq_read, | |
3289 | .llseek = seq_lseek, | |
3290 | .release = single_release, | |
3291 | .write = cur_wm_latency_write | |
3292 | }; | |
3293 | ||
647416f9 KC |
3294 | static int |
3295 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 3296 | { |
647416f9 | 3297 | struct drm_device *dev = data; |
e277a1f8 | 3298 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 3299 | |
647416f9 | 3300 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 3301 | |
647416f9 | 3302 | return 0; |
f3cd474b CW |
3303 | } |
3304 | ||
647416f9 KC |
3305 | static int |
3306 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 3307 | { |
647416f9 | 3308 | struct drm_device *dev = data; |
d46c0517 ID |
3309 | struct drm_i915_private *dev_priv = dev->dev_private; |
3310 | ||
3311 | intel_runtime_pm_get(dev_priv); | |
f3cd474b | 3312 | |
58174462 MK |
3313 | i915_handle_error(dev, val, |
3314 | "Manually setting wedged to %llu", val); | |
d46c0517 ID |
3315 | |
3316 | intel_runtime_pm_put(dev_priv); | |
3317 | ||
647416f9 | 3318 | return 0; |
f3cd474b CW |
3319 | } |
3320 | ||
647416f9 KC |
3321 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
3322 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 3323 | "%llu\n"); |
f3cd474b | 3324 | |
647416f9 KC |
3325 | static int |
3326 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 3327 | { |
647416f9 | 3328 | struct drm_device *dev = data; |
e277a1f8 | 3329 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 3330 | |
647416f9 | 3331 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 3332 | |
647416f9 | 3333 | return 0; |
e5eb3d63 DV |
3334 | } |
3335 | ||
647416f9 KC |
3336 | static int |
3337 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 3338 | { |
647416f9 | 3339 | struct drm_device *dev = data; |
e5eb3d63 | 3340 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3341 | int ret; |
e5eb3d63 | 3342 | |
647416f9 | 3343 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 3344 | |
22bcfc6a DV |
3345 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3346 | if (ret) | |
3347 | return ret; | |
3348 | ||
99584db3 | 3349 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
3350 | mutex_unlock(&dev->struct_mutex); |
3351 | ||
647416f9 | 3352 | return 0; |
e5eb3d63 DV |
3353 | } |
3354 | ||
647416f9 KC |
3355 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
3356 | i915_ring_stop_get, i915_ring_stop_set, | |
3357 | "0x%08llx\n"); | |
d5442303 | 3358 | |
094f9a54 CW |
3359 | static int |
3360 | i915_ring_missed_irq_get(void *data, u64 *val) | |
3361 | { | |
3362 | struct drm_device *dev = data; | |
3363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3364 | ||
3365 | *val = dev_priv->gpu_error.missed_irq_rings; | |
3366 | return 0; | |
3367 | } | |
3368 | ||
3369 | static int | |
3370 | i915_ring_missed_irq_set(void *data, u64 val) | |
3371 | { | |
3372 | struct drm_device *dev = data; | |
3373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3374 | int ret; | |
3375 | ||
3376 | /* Lock against concurrent debugfs callers */ | |
3377 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3378 | if (ret) | |
3379 | return ret; | |
3380 | dev_priv->gpu_error.missed_irq_rings = val; | |
3381 | mutex_unlock(&dev->struct_mutex); | |
3382 | ||
3383 | return 0; | |
3384 | } | |
3385 | ||
3386 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
3387 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
3388 | "0x%08llx\n"); | |
3389 | ||
3390 | static int | |
3391 | i915_ring_test_irq_get(void *data, u64 *val) | |
3392 | { | |
3393 | struct drm_device *dev = data; | |
3394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3395 | ||
3396 | *val = dev_priv->gpu_error.test_irq_rings; | |
3397 | ||
3398 | return 0; | |
3399 | } | |
3400 | ||
3401 | static int | |
3402 | i915_ring_test_irq_set(void *data, u64 val) | |
3403 | { | |
3404 | struct drm_device *dev = data; | |
3405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3406 | int ret; | |
3407 | ||
3408 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
3409 | ||
3410 | /* Lock against concurrent debugfs callers */ | |
3411 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3412 | if (ret) | |
3413 | return ret; | |
3414 | ||
3415 | dev_priv->gpu_error.test_irq_rings = val; | |
3416 | mutex_unlock(&dev->struct_mutex); | |
3417 | ||
3418 | return 0; | |
3419 | } | |
3420 | ||
3421 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
3422 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
3423 | "0x%08llx\n"); | |
3424 | ||
dd624afd CW |
3425 | #define DROP_UNBOUND 0x1 |
3426 | #define DROP_BOUND 0x2 | |
3427 | #define DROP_RETIRE 0x4 | |
3428 | #define DROP_ACTIVE 0x8 | |
3429 | #define DROP_ALL (DROP_UNBOUND | \ | |
3430 | DROP_BOUND | \ | |
3431 | DROP_RETIRE | \ | |
3432 | DROP_ACTIVE) | |
647416f9 KC |
3433 | static int |
3434 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 3435 | { |
647416f9 | 3436 | *val = DROP_ALL; |
dd624afd | 3437 | |
647416f9 | 3438 | return 0; |
dd624afd CW |
3439 | } |
3440 | ||
647416f9 KC |
3441 | static int |
3442 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 3443 | { |
647416f9 | 3444 | struct drm_device *dev = data; |
dd624afd CW |
3445 | struct drm_i915_private *dev_priv = dev->dev_private; |
3446 | struct drm_i915_gem_object *obj, *next; | |
ca191b13 BW |
3447 | struct i915_address_space *vm; |
3448 | struct i915_vma *vma, *x; | |
647416f9 | 3449 | int ret; |
dd624afd | 3450 | |
2f9fe5ff | 3451 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
3452 | |
3453 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
3454 | * on ioctls on -EAGAIN. */ | |
3455 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3456 | if (ret) | |
3457 | return ret; | |
3458 | ||
3459 | if (val & DROP_ACTIVE) { | |
3460 | ret = i915_gpu_idle(dev); | |
3461 | if (ret) | |
3462 | goto unlock; | |
3463 | } | |
3464 | ||
3465 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
3466 | i915_gem_retire_requests(dev); | |
3467 | ||
3468 | if (val & DROP_BOUND) { | |
ca191b13 BW |
3469 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3470 | list_for_each_entry_safe(vma, x, &vm->inactive_list, | |
3471 | mm_list) { | |
d7f46fc4 | 3472 | if (vma->pin_count) |
ca191b13 BW |
3473 | continue; |
3474 | ||
3475 | ret = i915_vma_unbind(vma); | |
3476 | if (ret) | |
3477 | goto unlock; | |
3478 | } | |
31a46c9c | 3479 | } |
dd624afd CW |
3480 | } |
3481 | ||
3482 | if (val & DROP_UNBOUND) { | |
35c20a60 BW |
3483 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
3484 | global_list) | |
dd624afd CW |
3485 | if (obj->pages_pin_count == 0) { |
3486 | ret = i915_gem_object_put_pages(obj); | |
3487 | if (ret) | |
3488 | goto unlock; | |
3489 | } | |
3490 | } | |
3491 | ||
3492 | unlock: | |
3493 | mutex_unlock(&dev->struct_mutex); | |
3494 | ||
647416f9 | 3495 | return ret; |
dd624afd CW |
3496 | } |
3497 | ||
647416f9 KC |
3498 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
3499 | i915_drop_caches_get, i915_drop_caches_set, | |
3500 | "0x%08llx\n"); | |
dd624afd | 3501 | |
647416f9 KC |
3502 | static int |
3503 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 3504 | { |
647416f9 | 3505 | struct drm_device *dev = data; |
e277a1f8 | 3506 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3507 | int ret; |
004777cb | 3508 | |
daa3afb2 | 3509 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
3510 | return -ENODEV; |
3511 | ||
5c9669ce TR |
3512 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3513 | ||
4fc688ce | 3514 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3515 | if (ret) |
3516 | return ret; | |
358733e9 | 3517 | |
0a073b84 | 3518 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 3519 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
0a073b84 | 3520 | else |
b39fb297 | 3521 | *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
4fc688ce | 3522 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 3523 | |
647416f9 | 3524 | return 0; |
358733e9 JB |
3525 | } |
3526 | ||
647416f9 KC |
3527 | static int |
3528 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 3529 | { |
647416f9 | 3530 | struct drm_device *dev = data; |
358733e9 | 3531 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 3532 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 3533 | int ret; |
004777cb | 3534 | |
daa3afb2 | 3535 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 3536 | return -ENODEV; |
358733e9 | 3537 | |
5c9669ce TR |
3538 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3539 | ||
647416f9 | 3540 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 3541 | |
4fc688ce | 3542 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3543 | if (ret) |
3544 | return ret; | |
3545 | ||
358733e9 JB |
3546 | /* |
3547 | * Turbo will still be enabled, but won't go above the set value. | |
3548 | */ | |
0a073b84 | 3549 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 3550 | val = vlv_freq_opcode(dev_priv, val); |
dd0a1aa1 JM |
3551 | |
3552 | hw_max = valleyview_rps_max_freq(dev_priv); | |
3553 | hw_min = valleyview_rps_min_freq(dev_priv); | |
0a073b84 JB |
3554 | } else { |
3555 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
dd0a1aa1 JM |
3556 | |
3557 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
b39fb297 | 3558 | hw_max = dev_priv->rps.max_freq; |
dd0a1aa1 JM |
3559 | hw_min = (rp_state_cap >> 16) & 0xff; |
3560 | } | |
3561 | ||
b39fb297 | 3562 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
3563 | mutex_unlock(&dev_priv->rps.hw_lock); |
3564 | return -EINVAL; | |
0a073b84 JB |
3565 | } |
3566 | ||
b39fb297 | 3567 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 JM |
3568 | |
3569 | if (IS_VALLEYVIEW(dev)) | |
3570 | valleyview_set_rps(dev, val); | |
3571 | else | |
3572 | gen6_set_rps(dev, val); | |
3573 | ||
4fc688ce | 3574 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 3575 | |
647416f9 | 3576 | return 0; |
358733e9 JB |
3577 | } |
3578 | ||
647416f9 KC |
3579 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
3580 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 3581 | "%llu\n"); |
358733e9 | 3582 | |
647416f9 KC |
3583 | static int |
3584 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 3585 | { |
647416f9 | 3586 | struct drm_device *dev = data; |
e277a1f8 | 3587 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 3588 | int ret; |
004777cb | 3589 | |
daa3afb2 | 3590 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
3591 | return -ENODEV; |
3592 | ||
5c9669ce TR |
3593 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3594 | ||
4fc688ce | 3595 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3596 | if (ret) |
3597 | return ret; | |
1523c310 | 3598 | |
0a073b84 | 3599 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 3600 | *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
0a073b84 | 3601 | else |
b39fb297 | 3602 | *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER; |
4fc688ce | 3603 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3604 | |
647416f9 | 3605 | return 0; |
1523c310 JB |
3606 | } |
3607 | ||
647416f9 KC |
3608 | static int |
3609 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 3610 | { |
647416f9 | 3611 | struct drm_device *dev = data; |
1523c310 | 3612 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd0a1aa1 | 3613 | u32 rp_state_cap, hw_max, hw_min; |
647416f9 | 3614 | int ret; |
004777cb | 3615 | |
daa3afb2 | 3616 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 3617 | return -ENODEV; |
1523c310 | 3618 | |
5c9669ce TR |
3619 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
3620 | ||
647416f9 | 3621 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 3622 | |
4fc688ce | 3623 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
3624 | if (ret) |
3625 | return ret; | |
3626 | ||
1523c310 JB |
3627 | /* |
3628 | * Turbo will still be enabled, but won't go below the set value. | |
3629 | */ | |
0a073b84 | 3630 | if (IS_VALLEYVIEW(dev)) { |
2ec3815f | 3631 | val = vlv_freq_opcode(dev_priv, val); |
dd0a1aa1 JM |
3632 | |
3633 | hw_max = valleyview_rps_max_freq(dev_priv); | |
3634 | hw_min = valleyview_rps_min_freq(dev_priv); | |
0a073b84 JB |
3635 | } else { |
3636 | do_div(val, GT_FREQUENCY_MULTIPLIER); | |
dd0a1aa1 JM |
3637 | |
3638 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
b39fb297 | 3639 | hw_max = dev_priv->rps.max_freq; |
dd0a1aa1 JM |
3640 | hw_min = (rp_state_cap >> 16) & 0xff; |
3641 | } | |
3642 | ||
b39fb297 | 3643 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
3644 | mutex_unlock(&dev_priv->rps.hw_lock); |
3645 | return -EINVAL; | |
0a073b84 | 3646 | } |
dd0a1aa1 | 3647 | |
b39fb297 | 3648 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 JM |
3649 | |
3650 | if (IS_VALLEYVIEW(dev)) | |
3651 | valleyview_set_rps(dev, val); | |
3652 | else | |
3653 | gen6_set_rps(dev, val); | |
3654 | ||
4fc688ce | 3655 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 3656 | |
647416f9 | 3657 | return 0; |
1523c310 JB |
3658 | } |
3659 | ||
647416f9 KC |
3660 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
3661 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 3662 | "%llu\n"); |
1523c310 | 3663 | |
647416f9 KC |
3664 | static int |
3665 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 3666 | { |
647416f9 | 3667 | struct drm_device *dev = data; |
e277a1f8 | 3668 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 3669 | u32 snpcr; |
647416f9 | 3670 | int ret; |
07b7ddd9 | 3671 | |
004777cb DV |
3672 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3673 | return -ENODEV; | |
3674 | ||
22bcfc6a DV |
3675 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3676 | if (ret) | |
3677 | return ret; | |
c8c8fb33 | 3678 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 3679 | |
07b7ddd9 | 3680 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
3681 | |
3682 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
3683 | mutex_unlock(&dev_priv->dev->struct_mutex); |
3684 | ||
647416f9 | 3685 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 3686 | |
647416f9 | 3687 | return 0; |
07b7ddd9 JB |
3688 | } |
3689 | ||
647416f9 KC |
3690 | static int |
3691 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 3692 | { |
647416f9 | 3693 | struct drm_device *dev = data; |
07b7ddd9 | 3694 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 3695 | u32 snpcr; |
07b7ddd9 | 3696 | |
004777cb DV |
3697 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
3698 | return -ENODEV; | |
3699 | ||
647416f9 | 3700 | if (val > 3) |
07b7ddd9 JB |
3701 | return -EINVAL; |
3702 | ||
c8c8fb33 | 3703 | intel_runtime_pm_get(dev_priv); |
647416f9 | 3704 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
3705 | |
3706 | /* Update the cache sharing policy here as well */ | |
3707 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
3708 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
3709 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
3710 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3711 | ||
c8c8fb33 | 3712 | intel_runtime_pm_put(dev_priv); |
647416f9 | 3713 | return 0; |
07b7ddd9 JB |
3714 | } |
3715 | ||
647416f9 KC |
3716 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
3717 | i915_cache_sharing_get, i915_cache_sharing_set, | |
3718 | "%llu\n"); | |
07b7ddd9 | 3719 | |
6d794d42 BW |
3720 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
3721 | { | |
3722 | struct drm_device *dev = inode->i_private; | |
3723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 3724 | |
075edca4 | 3725 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3726 | return 0; |
3727 | ||
c8d9a590 | 3728 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3729 | |
3730 | return 0; | |
3731 | } | |
3732 | ||
c43b5634 | 3733 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
3734 | { |
3735 | struct drm_device *dev = inode->i_private; | |
3736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3737 | ||
075edca4 | 3738 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
3739 | return 0; |
3740 | ||
c8d9a590 | 3741 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
3742 | |
3743 | return 0; | |
3744 | } | |
3745 | ||
3746 | static const struct file_operations i915_forcewake_fops = { | |
3747 | .owner = THIS_MODULE, | |
3748 | .open = i915_forcewake_open, | |
3749 | .release = i915_forcewake_release, | |
3750 | }; | |
3751 | ||
3752 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
3753 | { | |
3754 | struct drm_device *dev = minor->dev; | |
3755 | struct dentry *ent; | |
3756 | ||
3757 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 3758 | S_IRUSR, |
6d794d42 BW |
3759 | root, dev, |
3760 | &i915_forcewake_fops); | |
f3c5fe97 WY |
3761 | if (!ent) |
3762 | return -ENOMEM; | |
6d794d42 | 3763 | |
8eb57294 | 3764 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
3765 | } |
3766 | ||
6a9c308d DV |
3767 | static int i915_debugfs_create(struct dentry *root, |
3768 | struct drm_minor *minor, | |
3769 | const char *name, | |
3770 | const struct file_operations *fops) | |
07b7ddd9 JB |
3771 | { |
3772 | struct drm_device *dev = minor->dev; | |
3773 | struct dentry *ent; | |
3774 | ||
6a9c308d | 3775 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
3776 | S_IRUGO | S_IWUSR, |
3777 | root, dev, | |
6a9c308d | 3778 | fops); |
f3c5fe97 WY |
3779 | if (!ent) |
3780 | return -ENOMEM; | |
07b7ddd9 | 3781 | |
6a9c308d | 3782 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
3783 | } |
3784 | ||
06c5bf8c | 3785 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 3786 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 3787 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 3788 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 3789 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 3790 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 3791 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 3792 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 3793 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
3794 | {"i915_gem_request", i915_gem_request_info, 0}, |
3795 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 3796 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 3797 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
3798 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
3799 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
3800 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 3801 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
f97108d1 | 3802 | {"i915_rstdby_delays", i915_rstdby_delays, 0}, |
adb4bd12 | 3803 | {"i915_frequency_info", i915_frequency_info, 0}, |
f97108d1 JB |
3804 | {"i915_delayfreq_table", i915_delayfreq_table, 0}, |
3805 | {"i915_inttoext_table", i915_inttoext_table, 0}, | |
3806 | {"i915_drpc_info", i915_drpc_info, 0}, | |
7648fa99 | 3807 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 3808 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
7648fa99 | 3809 | {"i915_gfxec", i915_gfxec, 0}, |
b5e50c3f | 3810 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 3811 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 3812 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 3813 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 3814 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 3815 | {"i915_context_status", i915_context_status, 0}, |
6d794d42 | 3816 | {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, |
ea16a3cd | 3817 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 3818 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 3819 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 3820 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 3821 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 3822 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
371db66a | 3823 | {"i915_pc8_status", i915_pc8_status, 0}, |
1da51581 | 3824 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
53f5e3ca | 3825 | {"i915_display_info", i915_display_info, 0}, |
2017263e | 3826 | }; |
27c202ad | 3827 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 3828 | |
06c5bf8c | 3829 | static const struct i915_debugfs_files { |
34b9674c DV |
3830 | const char *name; |
3831 | const struct file_operations *fops; | |
3832 | } i915_debugfs_files[] = { | |
3833 | {"i915_wedged", &i915_wedged_fops}, | |
3834 | {"i915_max_freq", &i915_max_freq_fops}, | |
3835 | {"i915_min_freq", &i915_min_freq_fops}, | |
3836 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
3837 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
3838 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
3839 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
3840 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
3841 | {"i915_error_state", &i915_error_state_fops}, | |
3842 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 3843 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
3844 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
3845 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
3846 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
34b9674c DV |
3847 | }; |
3848 | ||
07144428 DL |
3849 | void intel_display_crc_init(struct drm_device *dev) |
3850 | { | |
3851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 3852 | enum pipe pipe; |
07144428 | 3853 | |
b378360e DV |
3854 | for_each_pipe(pipe) { |
3855 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
07144428 | 3856 | |
d538bbdf DL |
3857 | pipe_crc->opened = false; |
3858 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
3859 | init_waitqueue_head(&pipe_crc->wq); |
3860 | } | |
3861 | } | |
3862 | ||
27c202ad | 3863 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 3864 | { |
34b9674c | 3865 | int ret, i; |
f3cd474b | 3866 | |
6d794d42 | 3867 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
3868 | if (ret) |
3869 | return ret; | |
6a9c308d | 3870 | |
07144428 DL |
3871 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
3872 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
3873 | if (ret) | |
3874 | return ret; | |
3875 | } | |
3876 | ||
34b9674c DV |
3877 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3878 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
3879 | i915_debugfs_files[i].name, | |
3880 | i915_debugfs_files[i].fops); | |
3881 | if (ret) | |
3882 | return ret; | |
3883 | } | |
40633219 | 3884 | |
27c202ad BG |
3885 | return drm_debugfs_create_files(i915_debugfs_list, |
3886 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
3887 | minor->debugfs_root, minor); |
3888 | } | |
3889 | ||
27c202ad | 3890 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 3891 | { |
34b9674c DV |
3892 | int i; |
3893 | ||
27c202ad BG |
3894 | drm_debugfs_remove_files(i915_debugfs_list, |
3895 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 3896 | |
6d794d42 BW |
3897 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
3898 | 1, minor); | |
07144428 | 3899 | |
e309a997 | 3900 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
3901 | struct drm_info_list *info_list = |
3902 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
3903 | ||
3904 | drm_debugfs_remove_files(info_list, 1, minor); | |
3905 | } | |
3906 | ||
34b9674c DV |
3907 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
3908 | struct drm_info_list *info_list = | |
3909 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
3910 | ||
3911 | drm_debugfs_remove_files(info_list, 1, minor); | |
3912 | } | |
2017263e | 3913 | } |