Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
497666d8 DL |
49 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
50 | * allocated we need to hook into the minor for release. */ | |
51 | static int | |
52 | drm_add_fake_info_node(struct drm_minor *minor, | |
53 | struct dentry *ent, | |
54 | const void *key) | |
55 | { | |
56 | struct drm_info_node *node; | |
57 | ||
58 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
59 | if (node == NULL) { | |
60 | debugfs_remove(ent); | |
61 | return -ENOMEM; | |
62 | } | |
63 | ||
64 | node->minor = minor; | |
65 | node->dent = ent; | |
66 | node->info_ent = (void *) key; | |
67 | ||
68 | mutex_lock(&minor->debugfs_lock); | |
69 | list_add(&node->list, &minor->debugfs_list); | |
70 | mutex_unlock(&minor->debugfs_lock); | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
70d39fe4 CW |
75 | static int i915_capabilities(struct seq_file *m, void *data) |
76 | { | |
9f25d007 | 77 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
78 | struct drm_device *dev = node->minor->dev; |
79 | const struct intel_device_info *info = INTEL_INFO(dev); | |
80 | ||
81 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 82 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
83 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
84 | #define SEP_SEMICOLON ; | |
85 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
86 | #undef PRINT_FLAG | |
87 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
88 | |
89 | return 0; | |
90 | } | |
2017263e | 91 | |
05394f39 | 92 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 93 | { |
baaa5cfb | 94 | if (obj->pin_display) |
a6172a80 CW |
95 | return "p"; |
96 | else | |
97 | return " "; | |
98 | } | |
99 | ||
05394f39 | 100 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 101 | { |
0206e353 AJ |
102 | switch (obj->tiling_mode) { |
103 | default: | |
104 | case I915_TILING_NONE: return " "; | |
105 | case I915_TILING_X: return "X"; | |
106 | case I915_TILING_Y: return "Y"; | |
107 | } | |
a6172a80 CW |
108 | } |
109 | ||
1d693bcc BW |
110 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
111 | { | |
aff43766 | 112 | return i915_gem_obj_to_ggtt(obj) ? "g" : " "; |
1d693bcc BW |
113 | } |
114 | ||
ca1543be TU |
115 | static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) |
116 | { | |
117 | u64 size = 0; | |
118 | struct i915_vma *vma; | |
119 | ||
120 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
121 | if (i915_is_ggtt(vma->vm) && | |
122 | drm_mm_node_allocated(&vma->node)) | |
123 | size += vma->node.size; | |
124 | } | |
125 | ||
126 | return size; | |
127 | } | |
128 | ||
37811fcc CW |
129 | static void |
130 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
131 | { | |
b4716185 CW |
132 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
133 | struct intel_engine_cs *ring; | |
1d693bcc | 134 | struct i915_vma *vma; |
d7f46fc4 | 135 | int pin_count = 0; |
b4716185 | 136 | int i; |
d7f46fc4 | 137 | |
b4716185 | 138 | seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ", |
37811fcc | 139 | &obj->base, |
481a3d43 | 140 | obj->active ? "*" : " ", |
37811fcc CW |
141 | get_pin_flag(obj), |
142 | get_tiling_flag(obj), | |
1d693bcc | 143 | get_global_flag(obj), |
a05a5862 | 144 | obj->base.size / 1024, |
37811fcc | 145 | obj->base.read_domains, |
b4716185 CW |
146 | obj->base.write_domain); |
147 | for_each_ring(ring, dev_priv, i) | |
148 | seq_printf(m, "%x ", | |
149 | i915_gem_request_get_seqno(obj->last_read_req[i])); | |
150 | seq_printf(m, "] %x %x%s%s%s", | |
97b2a6a1 JH |
151 | i915_gem_request_get_seqno(obj->last_write_req), |
152 | i915_gem_request_get_seqno(obj->last_fenced_req), | |
0a4cd7c8 | 153 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
37811fcc CW |
154 | obj->dirty ? " dirty" : "", |
155 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
156 | if (obj->base.name) | |
157 | seq_printf(m, " (name: %d)", obj->base.name); | |
ba0635ff | 158 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
159 | if (vma->pin_count > 0) |
160 | pin_count++; | |
ba0635ff DC |
161 | } |
162 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
163 | if (obj->pin_display) |
164 | seq_printf(m, " (display)"); | |
37811fcc CW |
165 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
166 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc | 167 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
8d2fdc3f TU |
168 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
169 | i915_is_ggtt(vma->vm) ? "g" : "pp", | |
170 | vma->node.start, vma->node.size); | |
171 | if (i915_is_ggtt(vma->vm)) | |
172 | seq_printf(m, ", type: %u)", vma->ggtt_view.type); | |
1d693bcc | 173 | else |
8d2fdc3f | 174 | seq_puts(m, ")"); |
1d693bcc | 175 | } |
c1ad11fc | 176 | if (obj->stolen) |
440fd528 | 177 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
30154650 | 178 | if (obj->pin_display || obj->fault_mappable) { |
6299f992 | 179 | char s[3], *t = s; |
30154650 | 180 | if (obj->pin_display) |
6299f992 CW |
181 | *t++ = 'p'; |
182 | if (obj->fault_mappable) | |
183 | *t++ = 'f'; | |
184 | *t = '\0'; | |
185 | seq_printf(m, " (%s mappable)", s); | |
186 | } | |
b4716185 | 187 | if (obj->last_write_req != NULL) |
41c52415 | 188 | seq_printf(m, " (%s)", |
b4716185 | 189 | i915_gem_request_get_ring(obj->last_write_req)->name); |
d5a81ef1 DV |
190 | if (obj->frontbuffer_bits) |
191 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); | |
37811fcc CW |
192 | } |
193 | ||
273497e5 | 194 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
3ccfd19d | 195 | { |
ea0c76f8 | 196 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
3ccfd19d BW |
197 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
198 | seq_putc(m, ' '); | |
199 | } | |
200 | ||
433e12f7 | 201 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e | 202 | { |
9f25d007 | 203 | struct drm_info_node *node = m->private; |
433e12f7 BG |
204 | uintptr_t list = (uintptr_t) node->info_ent->data; |
205 | struct list_head *head; | |
2017263e | 206 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
207 | struct drm_i915_private *dev_priv = dev->dev_private; |
208 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 209 | struct i915_vma *vma; |
c44ef60e | 210 | u64 total_obj_size, total_gtt_size; |
8f2480fb | 211 | int count, ret; |
de227ef0 CW |
212 | |
213 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
214 | if (ret) | |
215 | return ret; | |
2017263e | 216 | |
ca191b13 | 217 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
218 | switch (list) { |
219 | case ACTIVE_LIST: | |
267f0c90 | 220 | seq_puts(m, "Active:\n"); |
5cef07e1 | 221 | head = &vm->active_list; |
433e12f7 BG |
222 | break; |
223 | case INACTIVE_LIST: | |
267f0c90 | 224 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 225 | head = &vm->inactive_list; |
433e12f7 | 226 | break; |
433e12f7 | 227 | default: |
de227ef0 CW |
228 | mutex_unlock(&dev->struct_mutex); |
229 | return -EINVAL; | |
2017263e | 230 | } |
2017263e | 231 | |
8f2480fb | 232 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
233 | list_for_each_entry(vma, head, mm_list) { |
234 | seq_printf(m, " "); | |
235 | describe_obj(m, vma->obj); | |
236 | seq_printf(m, "\n"); | |
237 | total_obj_size += vma->obj->base.size; | |
238 | total_gtt_size += vma->node.size; | |
8f2480fb | 239 | count++; |
2017263e | 240 | } |
de227ef0 | 241 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 242 | |
c44ef60e | 243 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
8f2480fb | 244 | count, total_obj_size, total_gtt_size); |
2017263e BG |
245 | return 0; |
246 | } | |
247 | ||
6d2b8885 CW |
248 | static int obj_rank_by_stolen(void *priv, |
249 | struct list_head *A, struct list_head *B) | |
250 | { | |
251 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 252 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 253 | struct drm_i915_gem_object *b = |
b25cb2f8 | 254 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 255 | |
2d05fa16 RV |
256 | if (a->stolen->start < b->stolen->start) |
257 | return -1; | |
258 | if (a->stolen->start > b->stolen->start) | |
259 | return 1; | |
260 | return 0; | |
6d2b8885 CW |
261 | } |
262 | ||
263 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
264 | { | |
9f25d007 | 265 | struct drm_info_node *node = m->private; |
6d2b8885 CW |
266 | struct drm_device *dev = node->minor->dev; |
267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
268 | struct drm_i915_gem_object *obj; | |
c44ef60e | 269 | u64 total_obj_size, total_gtt_size; |
6d2b8885 CW |
270 | LIST_HEAD(stolen); |
271 | int count, ret; | |
272 | ||
273 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
274 | if (ret) | |
275 | return ret; | |
276 | ||
277 | total_obj_size = total_gtt_size = count = 0; | |
278 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
279 | if (obj->stolen == NULL) | |
280 | continue; | |
281 | ||
b25cb2f8 | 282 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
283 | |
284 | total_obj_size += obj->base.size; | |
ca1543be | 285 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
6d2b8885 CW |
286 | count++; |
287 | } | |
288 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
289 | if (obj->stolen == NULL) | |
290 | continue; | |
291 | ||
b25cb2f8 | 292 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
293 | |
294 | total_obj_size += obj->base.size; | |
295 | count++; | |
296 | } | |
297 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
298 | seq_puts(m, "Stolen:\n"); | |
299 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 300 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
301 | seq_puts(m, " "); |
302 | describe_obj(m, obj); | |
303 | seq_putc(m, '\n'); | |
b25cb2f8 | 304 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
305 | } |
306 | mutex_unlock(&dev->struct_mutex); | |
307 | ||
c44ef60e | 308 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
6d2b8885 CW |
309 | count, total_obj_size, total_gtt_size); |
310 | return 0; | |
311 | } | |
312 | ||
6299f992 CW |
313 | #define count_objects(list, member) do { \ |
314 | list_for_each_entry(obj, list, member) { \ | |
ca1543be | 315 | size += i915_gem_obj_total_ggtt_size(obj); \ |
6299f992 CW |
316 | ++count; \ |
317 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 318 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
319 | ++mappable_count; \ |
320 | } \ | |
321 | } \ | |
0206e353 | 322 | } while (0) |
6299f992 | 323 | |
2db8e9d6 | 324 | struct file_stats { |
6313c204 | 325 | struct drm_i915_file_private *file_priv; |
c44ef60e MK |
326 | unsigned long count; |
327 | u64 total, unbound; | |
328 | u64 global, shared; | |
329 | u64 active, inactive; | |
2db8e9d6 CW |
330 | }; |
331 | ||
332 | static int per_file_stats(int id, void *ptr, void *data) | |
333 | { | |
334 | struct drm_i915_gem_object *obj = ptr; | |
335 | struct file_stats *stats = data; | |
6313c204 | 336 | struct i915_vma *vma; |
2db8e9d6 CW |
337 | |
338 | stats->count++; | |
339 | stats->total += obj->base.size; | |
340 | ||
c67a17e9 CW |
341 | if (obj->base.name || obj->base.dma_buf) |
342 | stats->shared += obj->base.size; | |
343 | ||
6313c204 CW |
344 | if (USES_FULL_PPGTT(obj->base.dev)) { |
345 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
346 | struct i915_hw_ppgtt *ppgtt; | |
347 | ||
348 | if (!drm_mm_node_allocated(&vma->node)) | |
349 | continue; | |
350 | ||
351 | if (i915_is_ggtt(vma->vm)) { | |
352 | stats->global += obj->base.size; | |
353 | continue; | |
354 | } | |
355 | ||
356 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
4d884705 | 357 | if (ppgtt->file_priv != stats->file_priv) |
6313c204 CW |
358 | continue; |
359 | ||
41c52415 | 360 | if (obj->active) /* XXX per-vma statistic */ |
6313c204 CW |
361 | stats->active += obj->base.size; |
362 | else | |
363 | stats->inactive += obj->base.size; | |
364 | ||
365 | return 0; | |
366 | } | |
2db8e9d6 | 367 | } else { |
6313c204 CW |
368 | if (i915_gem_obj_ggtt_bound(obj)) { |
369 | stats->global += obj->base.size; | |
41c52415 | 370 | if (obj->active) |
6313c204 CW |
371 | stats->active += obj->base.size; |
372 | else | |
373 | stats->inactive += obj->base.size; | |
374 | return 0; | |
375 | } | |
2db8e9d6 CW |
376 | } |
377 | ||
6313c204 CW |
378 | if (!list_empty(&obj->global_list)) |
379 | stats->unbound += obj->base.size; | |
380 | ||
2db8e9d6 CW |
381 | return 0; |
382 | } | |
383 | ||
b0da1b79 CW |
384 | #define print_file_stats(m, name, stats) do { \ |
385 | if (stats.count) \ | |
c44ef60e | 386 | seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ |
b0da1b79 CW |
387 | name, \ |
388 | stats.count, \ | |
389 | stats.total, \ | |
390 | stats.active, \ | |
391 | stats.inactive, \ | |
392 | stats.global, \ | |
393 | stats.shared, \ | |
394 | stats.unbound); \ | |
395 | } while (0) | |
493018dc BV |
396 | |
397 | static void print_batch_pool_stats(struct seq_file *m, | |
398 | struct drm_i915_private *dev_priv) | |
399 | { | |
400 | struct drm_i915_gem_object *obj; | |
401 | struct file_stats stats; | |
06fbca71 | 402 | struct intel_engine_cs *ring; |
8d9d5744 | 403 | int i, j; |
493018dc BV |
404 | |
405 | memset(&stats, 0, sizeof(stats)); | |
406 | ||
06fbca71 | 407 | for_each_ring(ring, dev_priv, i) { |
8d9d5744 CW |
408 | for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) { |
409 | list_for_each_entry(obj, | |
410 | &ring->batch_pool.cache_list[j], | |
411 | batch_pool_link) | |
412 | per_file_stats(0, obj, &stats); | |
413 | } | |
06fbca71 | 414 | } |
493018dc | 415 | |
b0da1b79 | 416 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
417 | } |
418 | ||
ca191b13 BW |
419 | #define count_vmas(list, member) do { \ |
420 | list_for_each_entry(vma, list, member) { \ | |
ca1543be | 421 | size += i915_gem_obj_total_ggtt_size(vma->obj); \ |
ca191b13 BW |
422 | ++count; \ |
423 | if (vma->obj->map_and_fenceable) { \ | |
424 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
425 | ++mappable_count; \ | |
426 | } \ | |
427 | } \ | |
428 | } while (0) | |
429 | ||
430 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 431 | { |
9f25d007 | 432 | struct drm_info_node *node = m->private; |
73aa808f CW |
433 | struct drm_device *dev = node->minor->dev; |
434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 | 435 | u32 count, mappable_count, purgeable_count; |
c44ef60e | 436 | u64 size, mappable_size, purgeable_size; |
6299f992 | 437 | struct drm_i915_gem_object *obj; |
5cef07e1 | 438 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 439 | struct drm_file *file; |
ca191b13 | 440 | struct i915_vma *vma; |
73aa808f CW |
441 | int ret; |
442 | ||
443 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
444 | if (ret) | |
445 | return ret; | |
446 | ||
6299f992 CW |
447 | seq_printf(m, "%u objects, %zu bytes\n", |
448 | dev_priv->mm.object_count, | |
449 | dev_priv->mm.object_memory); | |
450 | ||
451 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 452 | count_objects(&dev_priv->mm.bound_list, global_list); |
c44ef60e | 453 | seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n", |
6299f992 CW |
454 | count, mappable_count, size, mappable_size); |
455 | ||
456 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 457 | count_vmas(&vm->active_list, mm_list); |
c44ef60e | 458 | seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n", |
6299f992 CW |
459 | count, mappable_count, size, mappable_size); |
460 | ||
6299f992 | 461 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 462 | count_vmas(&vm->inactive_list, mm_list); |
c44ef60e | 463 | seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n", |
6299f992 CW |
464 | count, mappable_count, size, mappable_size); |
465 | ||
b7abb714 | 466 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 467 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 468 | size += obj->base.size, ++count; |
b7abb714 CW |
469 | if (obj->madv == I915_MADV_DONTNEED) |
470 | purgeable_size += obj->base.size, ++purgeable_count; | |
471 | } | |
c44ef60e | 472 | seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); |
6c085a72 | 473 | |
6299f992 | 474 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 475 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 476 | if (obj->fault_mappable) { |
f343c5f6 | 477 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
478 | ++count; |
479 | } | |
30154650 | 480 | if (obj->pin_display) { |
f343c5f6 | 481 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
482 | ++mappable_count; |
483 | } | |
b7abb714 CW |
484 | if (obj->madv == I915_MADV_DONTNEED) { |
485 | purgeable_size += obj->base.size; | |
486 | ++purgeable_count; | |
487 | } | |
6299f992 | 488 | } |
c44ef60e | 489 | seq_printf(m, "%u purgeable objects, %llu bytes\n", |
b7abb714 | 490 | purgeable_count, purgeable_size); |
c44ef60e | 491 | seq_printf(m, "%u pinned mappable objects, %llu bytes\n", |
6299f992 | 492 | mappable_count, mappable_size); |
c44ef60e | 493 | seq_printf(m, "%u fault mappable objects, %llu bytes\n", |
6299f992 CW |
494 | count, size); |
495 | ||
c44ef60e | 496 | seq_printf(m, "%llu [%llu] gtt total\n", |
853ba5d2 | 497 | dev_priv->gtt.base.total, |
c44ef60e | 498 | (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); |
73aa808f | 499 | |
493018dc BV |
500 | seq_putc(m, '\n'); |
501 | print_batch_pool_stats(m, dev_priv); | |
2db8e9d6 CW |
502 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
503 | struct file_stats stats; | |
3ec2f427 | 504 | struct task_struct *task; |
2db8e9d6 CW |
505 | |
506 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 507 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 508 | spin_lock(&file->table_lock); |
2db8e9d6 | 509 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 510 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
511 | /* |
512 | * Although we have a valid reference on file->pid, that does | |
513 | * not guarantee that the task_struct who called get_pid() is | |
514 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
515 | * Therefore, we need to protect this ->comm access using RCU. | |
516 | */ | |
517 | rcu_read_lock(); | |
518 | task = pid_task(file->pid, PIDTYPE_PID); | |
493018dc | 519 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 520 | rcu_read_unlock(); |
2db8e9d6 CW |
521 | } |
522 | ||
73aa808f CW |
523 | mutex_unlock(&dev->struct_mutex); |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
aee56cff | 528 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 529 | { |
9f25d007 | 530 | struct drm_info_node *node = m->private; |
08c18323 | 531 | struct drm_device *dev = node->minor->dev; |
1b50247a | 532 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
533 | struct drm_i915_private *dev_priv = dev->dev_private; |
534 | struct drm_i915_gem_object *obj; | |
c44ef60e | 535 | u64 total_obj_size, total_gtt_size; |
08c18323 CW |
536 | int count, ret; |
537 | ||
538 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
539 | if (ret) | |
540 | return ret; | |
541 | ||
542 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 543 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 544 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
545 | continue; |
546 | ||
267f0c90 | 547 | seq_puts(m, " "); |
08c18323 | 548 | describe_obj(m, obj); |
267f0c90 | 549 | seq_putc(m, '\n'); |
08c18323 | 550 | total_obj_size += obj->base.size; |
ca1543be | 551 | total_gtt_size += i915_gem_obj_total_ggtt_size(obj); |
08c18323 CW |
552 | count++; |
553 | } | |
554 | ||
555 | mutex_unlock(&dev->struct_mutex); | |
556 | ||
c44ef60e | 557 | seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", |
08c18323 CW |
558 | count, total_obj_size, total_gtt_size); |
559 | ||
560 | return 0; | |
561 | } | |
562 | ||
4e5359cd SF |
563 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
564 | { | |
9f25d007 | 565 | struct drm_info_node *node = m->private; |
4e5359cd | 566 | struct drm_device *dev = node->minor->dev; |
d6bbafa1 | 567 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd | 568 | struct intel_crtc *crtc; |
8a270ebf DV |
569 | int ret; |
570 | ||
571 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
572 | if (ret) | |
573 | return ret; | |
4e5359cd | 574 | |
d3fcc808 | 575 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
576 | const char pipe = pipe_name(crtc->pipe); |
577 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
578 | struct intel_unpin_work *work; |
579 | ||
5e2d7afc | 580 | spin_lock_irq(&dev->event_lock); |
4e5359cd SF |
581 | work = crtc->unpin_work; |
582 | if (work == NULL) { | |
9db4a9c7 | 583 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
584 | pipe, plane); |
585 | } else { | |
d6bbafa1 CW |
586 | u32 addr; |
587 | ||
e7d841ca | 588 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 589 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
590 | pipe, plane); |
591 | } else { | |
9db4a9c7 | 592 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
593 | pipe, plane); |
594 | } | |
3a8a946e DV |
595 | if (work->flip_queued_req) { |
596 | struct intel_engine_cs *ring = | |
597 | i915_gem_request_get_ring(work->flip_queued_req); | |
598 | ||
20e28fba | 599 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", |
3a8a946e | 600 | ring->name, |
f06cc1b9 | 601 | i915_gem_request_get_seqno(work->flip_queued_req), |
d6bbafa1 | 602 | dev_priv->next_seqno, |
3a8a946e | 603 | ring->get_seqno(ring, true), |
1b5a433a | 604 | i915_gem_request_completed(work->flip_queued_req, true)); |
d6bbafa1 CW |
605 | } else |
606 | seq_printf(m, "Flip not associated with any ring\n"); | |
607 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
608 | work->flip_queued_vblank, | |
609 | work->flip_ready_vblank, | |
1e3feefd | 610 | drm_crtc_vblank_count(&crtc->base)); |
4e5359cd | 611 | if (work->enable_stall_check) |
267f0c90 | 612 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 613 | else |
267f0c90 | 614 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 615 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd | 616 | |
d6bbafa1 CW |
617 | if (INTEL_INFO(dev)->gen >= 4) |
618 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); | |
619 | else | |
620 | addr = I915_READ(DSPADDR(crtc->plane)); | |
621 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
622 | ||
4e5359cd | 623 | if (work->pending_flip_obj) { |
d6bbafa1 CW |
624 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); |
625 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
626 | } |
627 | } | |
5e2d7afc | 628 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
629 | } |
630 | ||
8a270ebf DV |
631 | mutex_unlock(&dev->struct_mutex); |
632 | ||
4e5359cd SF |
633 | return 0; |
634 | } | |
635 | ||
493018dc BV |
636 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
637 | { | |
638 | struct drm_info_node *node = m->private; | |
639 | struct drm_device *dev = node->minor->dev; | |
640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
641 | struct drm_i915_gem_object *obj; | |
06fbca71 | 642 | struct intel_engine_cs *ring; |
8d9d5744 CW |
643 | int total = 0; |
644 | int ret, i, j; | |
493018dc BV |
645 | |
646 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
647 | if (ret) | |
648 | return ret; | |
649 | ||
06fbca71 | 650 | for_each_ring(ring, dev_priv, i) { |
8d9d5744 CW |
651 | for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) { |
652 | int count; | |
653 | ||
654 | count = 0; | |
655 | list_for_each_entry(obj, | |
656 | &ring->batch_pool.cache_list[j], | |
657 | batch_pool_link) | |
658 | count++; | |
659 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
660 | ring->name, j, count); | |
661 | ||
662 | list_for_each_entry(obj, | |
663 | &ring->batch_pool.cache_list[j], | |
664 | batch_pool_link) { | |
665 | seq_puts(m, " "); | |
666 | describe_obj(m, obj); | |
667 | seq_putc(m, '\n'); | |
668 | } | |
669 | ||
670 | total += count; | |
06fbca71 | 671 | } |
493018dc BV |
672 | } |
673 | ||
8d9d5744 | 674 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
675 | |
676 | mutex_unlock(&dev->struct_mutex); | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
2017263e BG |
681 | static int i915_gem_request_info(struct seq_file *m, void *data) |
682 | { | |
9f25d007 | 683 | struct drm_info_node *node = m->private; |
2017263e | 684 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 685 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 686 | struct intel_engine_cs *ring; |
eed29a5b | 687 | struct drm_i915_gem_request *req; |
2d1070b2 | 688 | int ret, any, i; |
de227ef0 CW |
689 | |
690 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
691 | if (ret) | |
692 | return ret; | |
2017263e | 693 | |
2d1070b2 | 694 | any = 0; |
a2c7f6fd | 695 | for_each_ring(ring, dev_priv, i) { |
2d1070b2 CW |
696 | int count; |
697 | ||
698 | count = 0; | |
eed29a5b | 699 | list_for_each_entry(req, &ring->request_list, list) |
2d1070b2 CW |
700 | count++; |
701 | if (count == 0) | |
a2c7f6fd CW |
702 | continue; |
703 | ||
2d1070b2 | 704 | seq_printf(m, "%s requests: %d\n", ring->name, count); |
eed29a5b | 705 | list_for_each_entry(req, &ring->request_list, list) { |
2d1070b2 CW |
706 | struct task_struct *task; |
707 | ||
708 | rcu_read_lock(); | |
709 | task = NULL; | |
eed29a5b DV |
710 | if (req->pid) |
711 | task = pid_task(req->pid, PIDTYPE_PID); | |
2d1070b2 | 712 | seq_printf(m, " %x @ %d: %s [%d]\n", |
eed29a5b DV |
713 | req->seqno, |
714 | (int) (jiffies - req->emitted_jiffies), | |
2d1070b2 CW |
715 | task ? task->comm : "<unknown>", |
716 | task ? task->pid : -1); | |
717 | rcu_read_unlock(); | |
c2c347a9 | 718 | } |
2d1070b2 CW |
719 | |
720 | any++; | |
2017263e | 721 | } |
de227ef0 CW |
722 | mutex_unlock(&dev->struct_mutex); |
723 | ||
2d1070b2 | 724 | if (any == 0) |
267f0c90 | 725 | seq_puts(m, "No requests\n"); |
c2c347a9 | 726 | |
2017263e BG |
727 | return 0; |
728 | } | |
729 | ||
b2223497 | 730 | static void i915_ring_seqno_info(struct seq_file *m, |
a4872ba6 | 731 | struct intel_engine_cs *ring) |
b2223497 CW |
732 | { |
733 | if (ring->get_seqno) { | |
20e28fba | 734 | seq_printf(m, "Current sequence (%s): %x\n", |
b2eadbc8 | 735 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
736 | } |
737 | } | |
738 | ||
2017263e BG |
739 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
740 | { | |
9f25d007 | 741 | struct drm_info_node *node = m->private; |
2017263e | 742 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 743 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 744 | struct intel_engine_cs *ring; |
1ec14ad3 | 745 | int ret, i; |
de227ef0 CW |
746 | |
747 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
748 | if (ret) | |
749 | return ret; | |
c8c8fb33 | 750 | intel_runtime_pm_get(dev_priv); |
2017263e | 751 | |
a2c7f6fd CW |
752 | for_each_ring(ring, dev_priv, i) |
753 | i915_ring_seqno_info(m, ring); | |
de227ef0 | 754 | |
c8c8fb33 | 755 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
756 | mutex_unlock(&dev->struct_mutex); |
757 | ||
2017263e BG |
758 | return 0; |
759 | } | |
760 | ||
761 | ||
762 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
763 | { | |
9f25d007 | 764 | struct drm_info_node *node = m->private; |
2017263e | 765 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 766 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 767 | struct intel_engine_cs *ring; |
9db4a9c7 | 768 | int ret, i, pipe; |
de227ef0 CW |
769 | |
770 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
771 | if (ret) | |
772 | return ret; | |
c8c8fb33 | 773 | intel_runtime_pm_get(dev_priv); |
2017263e | 774 | |
74e1ca8c | 775 | if (IS_CHERRYVIEW(dev)) { |
74e1ca8c VS |
776 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
777 | I915_READ(GEN8_MASTER_IRQ)); | |
778 | ||
779 | seq_printf(m, "Display IER:\t%08x\n", | |
780 | I915_READ(VLV_IER)); | |
781 | seq_printf(m, "Display IIR:\t%08x\n", | |
782 | I915_READ(VLV_IIR)); | |
783 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
784 | I915_READ(VLV_IIR_RW)); | |
785 | seq_printf(m, "Display IMR:\t%08x\n", | |
786 | I915_READ(VLV_IMR)); | |
055e393f | 787 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
788 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
789 | pipe_name(pipe), | |
790 | I915_READ(PIPESTAT(pipe))); | |
791 | ||
792 | seq_printf(m, "Port hotplug:\t%08x\n", | |
793 | I915_READ(PORT_HOTPLUG_EN)); | |
794 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
795 | I915_READ(VLV_DPFLIPSTAT)); | |
796 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
797 | I915_READ(DPINVGTT)); | |
798 | ||
799 | for (i = 0; i < 4; i++) { | |
800 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
801 | i, I915_READ(GEN8_GT_IMR(i))); | |
802 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
803 | i, I915_READ(GEN8_GT_IIR(i))); | |
804 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
805 | i, I915_READ(GEN8_GT_IER(i))); | |
806 | } | |
807 | ||
808 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
809 | I915_READ(GEN8_PCU_IMR)); | |
810 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
811 | I915_READ(GEN8_PCU_IIR)); | |
812 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
813 | I915_READ(GEN8_PCU_IER)); | |
814 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
815 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
816 | I915_READ(GEN8_MASTER_IRQ)); | |
817 | ||
818 | for (i = 0; i < 4; i++) { | |
819 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
820 | i, I915_READ(GEN8_GT_IMR(i))); | |
821 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
822 | i, I915_READ(GEN8_GT_IIR(i))); | |
823 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
824 | i, I915_READ(GEN8_GT_IER(i))); | |
825 | } | |
826 | ||
055e393f | 827 | for_each_pipe(dev_priv, pipe) { |
f458ebbc | 828 | if (!intel_display_power_is_enabled(dev_priv, |
22c59960 PZ |
829 | POWER_DOMAIN_PIPE(pipe))) { |
830 | seq_printf(m, "Pipe %c power disabled\n", | |
831 | pipe_name(pipe)); | |
832 | continue; | |
833 | } | |
a123f157 | 834 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
835 | pipe_name(pipe), |
836 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 837 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
838 | pipe_name(pipe), |
839 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 840 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
841 | pipe_name(pipe), |
842 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
a123f157 BW |
843 | } |
844 | ||
845 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
846 | I915_READ(GEN8_DE_PORT_IMR)); | |
847 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
848 | I915_READ(GEN8_DE_PORT_IIR)); | |
849 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
850 | I915_READ(GEN8_DE_PORT_IER)); | |
851 | ||
852 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
853 | I915_READ(GEN8_DE_MISC_IMR)); | |
854 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
855 | I915_READ(GEN8_DE_MISC_IIR)); | |
856 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
857 | I915_READ(GEN8_DE_MISC_IER)); | |
858 | ||
859 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
860 | I915_READ(GEN8_PCU_IMR)); | |
861 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
862 | I915_READ(GEN8_PCU_IIR)); | |
863 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
864 | I915_READ(GEN8_PCU_IER)); | |
865 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
866 | seq_printf(m, "Display IER:\t%08x\n", |
867 | I915_READ(VLV_IER)); | |
868 | seq_printf(m, "Display IIR:\t%08x\n", | |
869 | I915_READ(VLV_IIR)); | |
870 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
871 | I915_READ(VLV_IIR_RW)); | |
872 | seq_printf(m, "Display IMR:\t%08x\n", | |
873 | I915_READ(VLV_IMR)); | |
055e393f | 874 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
875 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
876 | pipe_name(pipe), | |
877 | I915_READ(PIPESTAT(pipe))); | |
878 | ||
879 | seq_printf(m, "Master IER:\t%08x\n", | |
880 | I915_READ(VLV_MASTER_IER)); | |
881 | ||
882 | seq_printf(m, "Render IER:\t%08x\n", | |
883 | I915_READ(GTIER)); | |
884 | seq_printf(m, "Render IIR:\t%08x\n", | |
885 | I915_READ(GTIIR)); | |
886 | seq_printf(m, "Render IMR:\t%08x\n", | |
887 | I915_READ(GTIMR)); | |
888 | ||
889 | seq_printf(m, "PM IER:\t\t%08x\n", | |
890 | I915_READ(GEN6_PMIER)); | |
891 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
892 | I915_READ(GEN6_PMIIR)); | |
893 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
894 | I915_READ(GEN6_PMIMR)); | |
895 | ||
896 | seq_printf(m, "Port hotplug:\t%08x\n", | |
897 | I915_READ(PORT_HOTPLUG_EN)); | |
898 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
899 | I915_READ(VLV_DPFLIPSTAT)); | |
900 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
901 | I915_READ(DPINVGTT)); | |
902 | ||
903 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
904 | seq_printf(m, "Interrupt enable: %08x\n", |
905 | I915_READ(IER)); | |
906 | seq_printf(m, "Interrupt identity: %08x\n", | |
907 | I915_READ(IIR)); | |
908 | seq_printf(m, "Interrupt mask: %08x\n", | |
909 | I915_READ(IMR)); | |
055e393f | 910 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
911 | seq_printf(m, "Pipe %c stat: %08x\n", |
912 | pipe_name(pipe), | |
913 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
914 | } else { |
915 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
916 | I915_READ(DEIER)); | |
917 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
918 | I915_READ(DEIIR)); | |
919 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
920 | I915_READ(DEIMR)); | |
921 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
922 | I915_READ(SDEIER)); | |
923 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
924 | I915_READ(SDEIIR)); | |
925 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
926 | I915_READ(SDEIMR)); | |
927 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
928 | I915_READ(GTIER)); | |
929 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
930 | I915_READ(GTIIR)); | |
931 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
932 | I915_READ(GTIMR)); | |
933 | } | |
a2c7f6fd | 934 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 935 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
936 | seq_printf(m, |
937 | "Graphics Interrupt mask (%s): %08x\n", | |
938 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 939 | } |
a2c7f6fd | 940 | i915_ring_seqno_info(m, ring); |
9862e600 | 941 | } |
c8c8fb33 | 942 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
943 | mutex_unlock(&dev->struct_mutex); |
944 | ||
2017263e BG |
945 | return 0; |
946 | } | |
947 | ||
a6172a80 CW |
948 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
949 | { | |
9f25d007 | 950 | struct drm_info_node *node = m->private; |
a6172a80 | 951 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 952 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
953 | int i, ret; |
954 | ||
955 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
956 | if (ret) | |
957 | return ret; | |
a6172a80 | 958 | |
a6172a80 CW |
959 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); |
960 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 961 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 962 | |
6c085a72 CW |
963 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
964 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 965 | if (obj == NULL) |
267f0c90 | 966 | seq_puts(m, "unused"); |
c2c347a9 | 967 | else |
05394f39 | 968 | describe_obj(m, obj); |
267f0c90 | 969 | seq_putc(m, '\n'); |
a6172a80 CW |
970 | } |
971 | ||
05394f39 | 972 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
973 | return 0; |
974 | } | |
975 | ||
2017263e BG |
976 | static int i915_hws_info(struct seq_file *m, void *data) |
977 | { | |
9f25d007 | 978 | struct drm_info_node *node = m->private; |
2017263e | 979 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 980 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 981 | struct intel_engine_cs *ring; |
1a240d4d | 982 | const u32 *hws; |
4066c0ae CW |
983 | int i; |
984 | ||
1ec14ad3 | 985 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 986 | hws = ring->status_page.page_addr; |
2017263e BG |
987 | if (hws == NULL) |
988 | return 0; | |
989 | ||
990 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
991 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
992 | i * 4, | |
993 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
994 | } | |
995 | return 0; | |
996 | } | |
997 | ||
d5442303 DV |
998 | static ssize_t |
999 | i915_error_state_write(struct file *filp, | |
1000 | const char __user *ubuf, | |
1001 | size_t cnt, | |
1002 | loff_t *ppos) | |
1003 | { | |
edc3d884 | 1004 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 1005 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 1006 | int ret; |
d5442303 DV |
1007 | |
1008 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
1009 | ||
22bcfc6a DV |
1010 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1011 | if (ret) | |
1012 | return ret; | |
1013 | ||
d5442303 DV |
1014 | i915_destroy_error_state(dev); |
1015 | mutex_unlock(&dev->struct_mutex); | |
1016 | ||
1017 | return cnt; | |
1018 | } | |
1019 | ||
1020 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
1021 | { | |
1022 | struct drm_device *dev = inode->i_private; | |
d5442303 | 1023 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
1024 | |
1025 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
1026 | if (!error_priv) | |
1027 | return -ENOMEM; | |
1028 | ||
1029 | error_priv->dev = dev; | |
1030 | ||
95d5bfb3 | 1031 | i915_error_state_get(dev, error_priv); |
d5442303 | 1032 | |
edc3d884 MK |
1033 | file->private_data = error_priv; |
1034 | ||
1035 | return 0; | |
d5442303 DV |
1036 | } |
1037 | ||
1038 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
1039 | { | |
edc3d884 | 1040 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 1041 | |
95d5bfb3 | 1042 | i915_error_state_put(error_priv); |
d5442303 DV |
1043 | kfree(error_priv); |
1044 | ||
edc3d884 MK |
1045 | return 0; |
1046 | } | |
1047 | ||
4dc955f7 MK |
1048 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1049 | size_t count, loff_t *pos) | |
1050 | { | |
1051 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1052 | struct drm_i915_error_state_buf error_str; | |
1053 | loff_t tmp_pos = 0; | |
1054 | ssize_t ret_count = 0; | |
1055 | int ret; | |
1056 | ||
0a4cd7c8 | 1057 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
4dc955f7 MK |
1058 | if (ret) |
1059 | return ret; | |
edc3d884 | 1060 | |
fc16b48b | 1061 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1062 | if (ret) |
1063 | goto out; | |
1064 | ||
edc3d884 MK |
1065 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1066 | error_str.buf, | |
1067 | error_str.bytes); | |
1068 | ||
1069 | if (ret_count < 0) | |
1070 | ret = ret_count; | |
1071 | else | |
1072 | *pos = error_str.start + ret_count; | |
1073 | out: | |
4dc955f7 | 1074 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1075 | return ret ?: ret_count; |
d5442303 DV |
1076 | } |
1077 | ||
1078 | static const struct file_operations i915_error_state_fops = { | |
1079 | .owner = THIS_MODULE, | |
1080 | .open = i915_error_state_open, | |
edc3d884 | 1081 | .read = i915_error_state_read, |
d5442303 DV |
1082 | .write = i915_error_state_write, |
1083 | .llseek = default_llseek, | |
1084 | .release = i915_error_state_release, | |
1085 | }; | |
1086 | ||
647416f9 KC |
1087 | static int |
1088 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1089 | { |
647416f9 | 1090 | struct drm_device *dev = data; |
e277a1f8 | 1091 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
1092 | int ret; |
1093 | ||
1094 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1095 | if (ret) | |
1096 | return ret; | |
1097 | ||
647416f9 | 1098 | *val = dev_priv->next_seqno; |
40633219 MK |
1099 | mutex_unlock(&dev->struct_mutex); |
1100 | ||
647416f9 | 1101 | return 0; |
40633219 MK |
1102 | } |
1103 | ||
647416f9 KC |
1104 | static int |
1105 | i915_next_seqno_set(void *data, u64 val) | |
1106 | { | |
1107 | struct drm_device *dev = data; | |
40633219 MK |
1108 | int ret; |
1109 | ||
40633219 MK |
1110 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1111 | if (ret) | |
1112 | return ret; | |
1113 | ||
e94fbaa8 | 1114 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1115 | mutex_unlock(&dev->struct_mutex); |
1116 | ||
647416f9 | 1117 | return ret; |
40633219 MK |
1118 | } |
1119 | ||
647416f9 KC |
1120 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1121 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1122 | "0x%llx\n"); |
40633219 | 1123 | |
adb4bd12 | 1124 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1125 | { |
9f25d007 | 1126 | struct drm_info_node *node = m->private; |
f97108d1 | 1127 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1128 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
1129 | int ret = 0; |
1130 | ||
1131 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1132 | |
5c9669ce TR |
1133 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1134 | ||
3b8d8d91 JB |
1135 | if (IS_GEN5(dev)) { |
1136 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1137 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1138 | ||
1139 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1140 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1141 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1142 | MEMSTAT_VID_SHIFT); | |
1143 | seq_printf(m, "Current P-state: %d\n", | |
1144 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
666a4537 WB |
1145 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
1146 | u32 freq_sts; | |
1147 | ||
1148 | mutex_lock(&dev_priv->rps.hw_lock); | |
1149 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
1150 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); | |
1151 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1152 | ||
1153 | seq_printf(m, "actual GPU freq: %d MHz\n", | |
1154 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1155 | ||
1156 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1157 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1158 | ||
1159 | seq_printf(m, "max GPU freq: %d MHz\n", | |
1160 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1161 | ||
1162 | seq_printf(m, "min GPU freq: %d MHz\n", | |
1163 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1164 | ||
1165 | seq_printf(m, "idle GPU freq: %d MHz\n", | |
1166 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1167 | ||
1168 | seq_printf(m, | |
1169 | "efficient (RPe) frequency: %d MHz\n", | |
1170 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
1171 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1172 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
35040562 BP |
1173 | u32 rp_state_limits; |
1174 | u32 gt_perf_status; | |
1175 | u32 rp_state_cap; | |
0d8f9491 | 1176 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1177 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1178 | u32 rpupei, rpcurup, rpprevup; |
1179 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1180 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1181 | int max_freq; |
1182 | ||
35040562 BP |
1183 | rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); |
1184 | if (IS_BROXTON(dev)) { | |
1185 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); | |
1186 | gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); | |
1187 | } else { | |
1188 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
1189 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
1190 | } | |
1191 | ||
3b8d8d91 | 1192 | /* RPSTAT1 is in the GT power well */ |
d1ebd816 BW |
1193 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1194 | if (ret) | |
c8c8fb33 | 1195 | goto out; |
d1ebd816 | 1196 | |
59bad947 | 1197 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1198 | |
8e8c06cd | 1199 | reqf = I915_READ(GEN6_RPNSWREQ); |
60260a5b AG |
1200 | if (IS_GEN9(dev)) |
1201 | reqf >>= 23; | |
1202 | else { | |
1203 | reqf &= ~GEN6_TURBO_DISABLE; | |
1204 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
1205 | reqf >>= 24; | |
1206 | else | |
1207 | reqf >>= 25; | |
1208 | } | |
7c59a9c1 | 1209 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1210 | |
0d8f9491 CW |
1211 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1212 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1213 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1214 | ||
ccab5c82 JB |
1215 | rpstat = I915_READ(GEN6_RPSTAT1); |
1216 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
1217 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
1218 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
1219 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
1220 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
1221 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
60260a5b AG |
1222 | if (IS_GEN9(dev)) |
1223 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
1224 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
f82855d3 BW |
1225 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1226 | else | |
1227 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1228 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1229 | |
59bad947 | 1230 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1231 | mutex_unlock(&dev->struct_mutex); |
1232 | ||
9dd3c605 PZ |
1233 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1234 | pm_ier = I915_READ(GEN6_PMIER); | |
1235 | pm_imr = I915_READ(GEN6_PMIMR); | |
1236 | pm_isr = I915_READ(GEN6_PMISR); | |
1237 | pm_iir = I915_READ(GEN6_PMIIR); | |
1238 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1239 | } else { | |
1240 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1241 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1242 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1243 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1244 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1245 | } | |
0d8f9491 | 1246 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1247 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
3b8d8d91 | 1248 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1249 | seq_printf(m, "Render p-state ratio: %d\n", |
60260a5b | 1250 | (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1251 | seq_printf(m, "Render p-state VID: %d\n", |
1252 | gt_perf_status & 0xff); | |
1253 | seq_printf(m, "Render p-state limit: %d\n", | |
1254 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1255 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1256 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1257 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1258 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1259 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1260 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1261 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1262 | GEN6_CURICONT_MASK); | |
1263 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1264 | GEN6_CURBSYTAVG_MASK); | |
1265 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1266 | GEN6_CURBSYTAVG_MASK); | |
d86ed34a CW |
1267 | seq_printf(m, "Up threshold: %d%%\n", |
1268 | dev_priv->rps.up_threshold); | |
1269 | ||
ccab5c82 JB |
1270 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & |
1271 | GEN6_CURIAVG_MASK); | |
1272 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1273 | GEN6_CURBSYTAVG_MASK); | |
1274 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1275 | GEN6_CURBSYTAVG_MASK); | |
d86ed34a CW |
1276 | seq_printf(m, "Down threshold: %d%%\n", |
1277 | dev_priv->rps.down_threshold); | |
3b8d8d91 | 1278 | |
35040562 BP |
1279 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : |
1280 | rp_state_cap >> 16) & 0xff; | |
ef11bdb3 RV |
1281 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1282 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1283 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1284 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1285 | |
1286 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
ef11bdb3 RV |
1287 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1288 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1289 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1290 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 | 1291 | |
35040562 BP |
1292 | max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : |
1293 | rp_state_cap >> 0) & 0xff; | |
ef11bdb3 RV |
1294 | max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1295 | GEN9_FREQ_SCALER : 1); | |
3b8d8d91 | 1296 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1297 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1298 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1299 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1300 | |
d86ed34a CW |
1301 | seq_printf(m, "Current freq: %d MHz\n", |
1302 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1303 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1304 | seq_printf(m, "Idle freq: %d MHz\n", |
1305 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1306 | seq_printf(m, "Min freq: %d MHz\n", |
1307 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1308 | seq_printf(m, "Max freq: %d MHz\n", | |
1309 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1310 | seq_printf(m, | |
1311 | "efficient (RPe) frequency: %d MHz\n", | |
1312 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
3b8d8d91 | 1313 | } else { |
267f0c90 | 1314 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1315 | } |
f97108d1 | 1316 | |
1170f28c MK |
1317 | seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); |
1318 | seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); | |
1319 | seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); | |
1320 | ||
c8c8fb33 PZ |
1321 | out: |
1322 | intel_runtime_pm_put(dev_priv); | |
1323 | return ret; | |
f97108d1 JB |
1324 | } |
1325 | ||
f654449a CW |
1326 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1327 | { | |
1328 | struct drm_info_node *node = m->private; | |
ebbc7546 MK |
1329 | struct drm_device *dev = node->minor->dev; |
1330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f654449a | 1331 | struct intel_engine_cs *ring; |
ebbc7546 MK |
1332 | u64 acthd[I915_NUM_RINGS]; |
1333 | u32 seqno[I915_NUM_RINGS]; | |
f654449a CW |
1334 | int i; |
1335 | ||
1336 | if (!i915.enable_hangcheck) { | |
1337 | seq_printf(m, "Hangcheck disabled\n"); | |
1338 | return 0; | |
1339 | } | |
1340 | ||
ebbc7546 MK |
1341 | intel_runtime_pm_get(dev_priv); |
1342 | ||
1343 | for_each_ring(ring, dev_priv, i) { | |
1344 | seqno[i] = ring->get_seqno(ring, false); | |
1345 | acthd[i] = intel_ring_get_active_head(ring); | |
1346 | } | |
1347 | ||
1348 | intel_runtime_pm_put(dev_priv); | |
1349 | ||
f654449a CW |
1350 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1351 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1352 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1353 | jiffies)); | |
1354 | } else | |
1355 | seq_printf(m, "Hangcheck inactive\n"); | |
1356 | ||
1357 | for_each_ring(ring, dev_priv, i) { | |
1358 | seq_printf(m, "%s:\n", ring->name); | |
1359 | seq_printf(m, "\tseqno = %x [current %x]\n", | |
ebbc7546 | 1360 | ring->hangcheck.seqno, seqno[i]); |
f654449a CW |
1361 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
1362 | (long long)ring->hangcheck.acthd, | |
ebbc7546 | 1363 | (long long)acthd[i]); |
f654449a CW |
1364 | seq_printf(m, "\tmax ACTHD = 0x%08llx\n", |
1365 | (long long)ring->hangcheck.max_acthd); | |
ebbc7546 MK |
1366 | seq_printf(m, "\tscore = %d\n", ring->hangcheck.score); |
1367 | seq_printf(m, "\taction = %d\n", ring->hangcheck.action); | |
f654449a CW |
1368 | } |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
4d85529d | 1373 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1374 | { |
9f25d007 | 1375 | struct drm_info_node *node = m->private; |
f97108d1 | 1376 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1377 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1378 | u32 rgvmodectl, rstdbyctl; |
1379 | u16 crstandvid; | |
1380 | int ret; | |
1381 | ||
1382 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1383 | if (ret) | |
1384 | return ret; | |
c8c8fb33 | 1385 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1386 | |
1387 | rgvmodectl = I915_READ(MEMMODECTL); | |
1388 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1389 | crstandvid = I915_READ16(CRSTANDVID); | |
1390 | ||
c8c8fb33 | 1391 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1392 | mutex_unlock(&dev->struct_mutex); |
f97108d1 | 1393 | |
742f491d | 1394 | seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); |
f97108d1 JB |
1395 | seq_printf(m, "Boost freq: %d\n", |
1396 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1397 | MEMMODE_BOOST_FREQ_SHIFT); | |
1398 | seq_printf(m, "HW control enabled: %s\n", | |
742f491d | 1399 | yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); |
f97108d1 | 1400 | seq_printf(m, "SW control enabled: %s\n", |
742f491d | 1401 | yesno(rgvmodectl & MEMMODE_SWMODE_EN)); |
f97108d1 | 1402 | seq_printf(m, "Gated voltage change: %s\n", |
742f491d | 1403 | yesno(rgvmodectl & MEMMODE_RCLK_GATE)); |
f97108d1 JB |
1404 | seq_printf(m, "Starting frequency: P%d\n", |
1405 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1406 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1407 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1408 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1409 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1410 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1411 | seq_printf(m, "Render standby enabled: %s\n", | |
742f491d | 1412 | yesno(!(rstdbyctl & RCX_SW_EXIT))); |
267f0c90 | 1413 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1414 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1415 | case RSX_STATUS_ON: | |
267f0c90 | 1416 | seq_puts(m, "on\n"); |
88271da3 JB |
1417 | break; |
1418 | case RSX_STATUS_RC1: | |
267f0c90 | 1419 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1420 | break; |
1421 | case RSX_STATUS_RC1E: | |
267f0c90 | 1422 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1423 | break; |
1424 | case RSX_STATUS_RS1: | |
267f0c90 | 1425 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1426 | break; |
1427 | case RSX_STATUS_RS2: | |
267f0c90 | 1428 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1429 | break; |
1430 | case RSX_STATUS_RS3: | |
267f0c90 | 1431 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1432 | break; |
1433 | default: | |
267f0c90 | 1434 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1435 | break; |
1436 | } | |
f97108d1 JB |
1437 | |
1438 | return 0; | |
1439 | } | |
1440 | ||
f65367b5 | 1441 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1442 | { |
b2cff0db CW |
1443 | struct drm_info_node *node = m->private; |
1444 | struct drm_device *dev = node->minor->dev; | |
1445 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1446 | struct intel_uncore_forcewake_domain *fw_domain; | |
b2cff0db CW |
1447 | int i; |
1448 | ||
1449 | spin_lock_irq(&dev_priv->uncore.lock); | |
1450 | for_each_fw_domain(fw_domain, dev_priv, i) { | |
1451 | seq_printf(m, "%s.wake_count = %u\n", | |
05a2fb15 | 1452 | intel_uncore_forcewake_domain_to_str(i), |
b2cff0db CW |
1453 | fw_domain->wake_count); |
1454 | } | |
1455 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1456 | |
b2cff0db CW |
1457 | return 0; |
1458 | } | |
1459 | ||
1460 | static int vlv_drpc_info(struct seq_file *m) | |
1461 | { | |
9f25d007 | 1462 | struct drm_info_node *node = m->private; |
669ab5aa D |
1463 | struct drm_device *dev = node->minor->dev; |
1464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6b312cd3 | 1465 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1466 | |
d46c0517 ID |
1467 | intel_runtime_pm_get(dev_priv); |
1468 | ||
6b312cd3 | 1469 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1470 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1471 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1472 | ||
d46c0517 ID |
1473 | intel_runtime_pm_put(dev_priv); |
1474 | ||
669ab5aa D |
1475 | seq_printf(m, "Video Turbo Mode: %s\n", |
1476 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1477 | seq_printf(m, "Turbo enabled: %s\n", | |
1478 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1479 | seq_printf(m, "HW control enabled: %s\n", | |
1480 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1481 | seq_printf(m, "SW control enabled: %s\n", | |
1482 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1483 | GEN6_RP_MEDIA_SW_MODE)); | |
1484 | seq_printf(m, "RC6 Enabled: %s\n", | |
1485 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1486 | GEN6_RC_CTL_EI_MODE(1)))); | |
1487 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1488 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1489 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1490 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1491 | |
9cc19be5 ID |
1492 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1493 | I915_READ(VLV_GT_RENDER_RC6)); | |
1494 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1495 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1496 | ||
f65367b5 | 1497 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1498 | } |
1499 | ||
4d85529d BW |
1500 | static int gen6_drpc_info(struct seq_file *m) |
1501 | { | |
9f25d007 | 1502 | struct drm_info_node *node = m->private; |
4d85529d BW |
1503 | struct drm_device *dev = node->minor->dev; |
1504 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1505 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1506 | unsigned forcewake_count; |
aee56cff | 1507 | int count = 0, ret; |
4d85529d BW |
1508 | |
1509 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1510 | if (ret) | |
1511 | return ret; | |
c8c8fb33 | 1512 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1513 | |
907b28c5 | 1514 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1515 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1516 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1517 | |
1518 | if (forcewake_count) { | |
267f0c90 DL |
1519 | seq_puts(m, "RC information inaccurate because somebody " |
1520 | "holds a forcewake reference \n"); | |
4d85529d BW |
1521 | } else { |
1522 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1523 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1524 | udelay(10); | |
1525 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1526 | } | |
1527 | ||
75aa3f63 | 1528 | gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); |
ed71f1b4 | 1529 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1530 | |
1531 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1532 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1533 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1534 | mutex_lock(&dev_priv->rps.hw_lock); |
1535 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1536 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1537 | |
c8c8fb33 PZ |
1538 | intel_runtime_pm_put(dev_priv); |
1539 | ||
4d85529d BW |
1540 | seq_printf(m, "Video Turbo Mode: %s\n", |
1541 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1542 | seq_printf(m, "HW control enabled: %s\n", | |
1543 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1544 | seq_printf(m, "SW control enabled: %s\n", | |
1545 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1546 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1547 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1548 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1549 | seq_printf(m, "RC6 Enabled: %s\n", | |
1550 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1551 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1552 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1553 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1554 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1555 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1556 | switch (gt_core_status & GEN6_RCn_MASK) { |
1557 | case GEN6_RC0: | |
1558 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1559 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1560 | else |
267f0c90 | 1561 | seq_puts(m, "on\n"); |
4d85529d BW |
1562 | break; |
1563 | case GEN6_RC3: | |
267f0c90 | 1564 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1565 | break; |
1566 | case GEN6_RC6: | |
267f0c90 | 1567 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1568 | break; |
1569 | case GEN6_RC7: | |
267f0c90 | 1570 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1571 | break; |
1572 | default: | |
267f0c90 | 1573 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1574 | break; |
1575 | } | |
1576 | ||
1577 | seq_printf(m, "Core Power Down: %s\n", | |
1578 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1579 | |
1580 | /* Not exactly sure what this is */ | |
1581 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1582 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1583 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1584 | I915_READ(GEN6_GT_GFX_RC6)); | |
1585 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1586 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1587 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1588 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1589 | ||
ecd8faea BW |
1590 | seq_printf(m, "RC6 voltage: %dmV\n", |
1591 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1592 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1593 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1594 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1595 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1596 | return 0; |
1597 | } | |
1598 | ||
1599 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1600 | { | |
9f25d007 | 1601 | struct drm_info_node *node = m->private; |
4d85529d BW |
1602 | struct drm_device *dev = node->minor->dev; |
1603 | ||
666a4537 | 1604 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
669ab5aa | 1605 | return vlv_drpc_info(m); |
ac66cf4b | 1606 | else if (INTEL_INFO(dev)->gen >= 6) |
4d85529d BW |
1607 | return gen6_drpc_info(m); |
1608 | else | |
1609 | return ironlake_drpc_info(m); | |
1610 | } | |
1611 | ||
9a851789 DV |
1612 | static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) |
1613 | { | |
1614 | struct drm_info_node *node = m->private; | |
1615 | struct drm_device *dev = node->minor->dev; | |
1616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1617 | ||
1618 | seq_printf(m, "FB tracking busy bits: 0x%08x\n", | |
1619 | dev_priv->fb_tracking.busy_bits); | |
1620 | ||
1621 | seq_printf(m, "FB tracking flip bits: 0x%08x\n", | |
1622 | dev_priv->fb_tracking.flip_bits); | |
1623 | ||
1624 | return 0; | |
1625 | } | |
1626 | ||
b5e50c3f JB |
1627 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1628 | { | |
9f25d007 | 1629 | struct drm_info_node *node = m->private; |
b5e50c3f | 1630 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1631 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1632 | |
3a77c4c4 | 1633 | if (!HAS_FBC(dev)) { |
267f0c90 | 1634 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1635 | return 0; |
1636 | } | |
1637 | ||
36623ef8 | 1638 | intel_runtime_pm_get(dev_priv); |
25ad93fd | 1639 | mutex_lock(&dev_priv->fbc.lock); |
36623ef8 | 1640 | |
0e631adc | 1641 | if (intel_fbc_is_active(dev_priv)) |
267f0c90 | 1642 | seq_puts(m, "FBC enabled\n"); |
2e8144a5 PZ |
1643 | else |
1644 | seq_printf(m, "FBC disabled: %s\n", | |
bf6189c6 | 1645 | dev_priv->fbc.no_fbc_reason); |
36623ef8 | 1646 | |
31b9df10 PZ |
1647 | if (INTEL_INFO(dev_priv)->gen >= 7) |
1648 | seq_printf(m, "Compressing: %s\n", | |
1649 | yesno(I915_READ(FBC_STATUS2) & | |
1650 | FBC_COMPRESSION_MASK)); | |
1651 | ||
25ad93fd | 1652 | mutex_unlock(&dev_priv->fbc.lock); |
36623ef8 PZ |
1653 | intel_runtime_pm_put(dev_priv); |
1654 | ||
b5e50c3f JB |
1655 | return 0; |
1656 | } | |
1657 | ||
da46f936 RV |
1658 | static int i915_fbc_fc_get(void *data, u64 *val) |
1659 | { | |
1660 | struct drm_device *dev = data; | |
1661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1662 | ||
1663 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1664 | return -ENODEV; | |
1665 | ||
da46f936 | 1666 | *val = dev_priv->fbc.false_color; |
da46f936 RV |
1667 | |
1668 | return 0; | |
1669 | } | |
1670 | ||
1671 | static int i915_fbc_fc_set(void *data, u64 val) | |
1672 | { | |
1673 | struct drm_device *dev = data; | |
1674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1675 | u32 reg; | |
1676 | ||
1677 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1678 | return -ENODEV; | |
1679 | ||
25ad93fd | 1680 | mutex_lock(&dev_priv->fbc.lock); |
da46f936 RV |
1681 | |
1682 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1683 | dev_priv->fbc.false_color = val; | |
1684 | ||
1685 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1686 | (reg | FBC_CTL_FALSE_COLOR) : | |
1687 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1688 | ||
25ad93fd | 1689 | mutex_unlock(&dev_priv->fbc.lock); |
da46f936 RV |
1690 | return 0; |
1691 | } | |
1692 | ||
1693 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1694 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1695 | "%llu\n"); | |
1696 | ||
92d44621 PZ |
1697 | static int i915_ips_status(struct seq_file *m, void *unused) |
1698 | { | |
9f25d007 | 1699 | struct drm_info_node *node = m->private; |
92d44621 PZ |
1700 | struct drm_device *dev = node->minor->dev; |
1701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1702 | ||
f5adf94e | 1703 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1704 | seq_puts(m, "not supported\n"); |
1705 | return 0; | |
1706 | } | |
1707 | ||
36623ef8 PZ |
1708 | intel_runtime_pm_get(dev_priv); |
1709 | ||
0eaa53f0 RV |
1710 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1711 | yesno(i915.enable_ips)); | |
1712 | ||
1713 | if (INTEL_INFO(dev)->gen >= 8) { | |
1714 | seq_puts(m, "Currently: unknown\n"); | |
1715 | } else { | |
1716 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1717 | seq_puts(m, "Currently: enabled\n"); | |
1718 | else | |
1719 | seq_puts(m, "Currently: disabled\n"); | |
1720 | } | |
92d44621 | 1721 | |
36623ef8 PZ |
1722 | intel_runtime_pm_put(dev_priv); |
1723 | ||
92d44621 PZ |
1724 | return 0; |
1725 | } | |
1726 | ||
4a9bef37 JB |
1727 | static int i915_sr_status(struct seq_file *m, void *unused) |
1728 | { | |
9f25d007 | 1729 | struct drm_info_node *node = m->private; |
4a9bef37 | 1730 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1731 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1732 | bool sr_enabled = false; |
1733 | ||
36623ef8 PZ |
1734 | intel_runtime_pm_get(dev_priv); |
1735 | ||
1398261a | 1736 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1737 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
77b64555 ACO |
1738 | else if (IS_CRESTLINE(dev) || IS_G4X(dev) || |
1739 | IS_I945G(dev) || IS_I945GM(dev)) | |
4a9bef37 JB |
1740 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1741 | else if (IS_I915GM(dev)) | |
1742 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1743 | else if (IS_PINEVIEW(dev)) | |
1744 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
666a4537 | 1745 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
77b64555 | 1746 | sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4a9bef37 | 1747 | |
36623ef8 PZ |
1748 | intel_runtime_pm_put(dev_priv); |
1749 | ||
5ba2aaaa CW |
1750 | seq_printf(m, "self-refresh: %s\n", |
1751 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1752 | |
1753 | return 0; | |
1754 | } | |
1755 | ||
7648fa99 JB |
1756 | static int i915_emon_status(struct seq_file *m, void *unused) |
1757 | { | |
9f25d007 | 1758 | struct drm_info_node *node = m->private; |
7648fa99 | 1759 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1760 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1761 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1762 | int ret; |
1763 | ||
582be6b4 CW |
1764 | if (!IS_GEN5(dev)) |
1765 | return -ENODEV; | |
1766 | ||
de227ef0 CW |
1767 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1768 | if (ret) | |
1769 | return ret; | |
7648fa99 JB |
1770 | |
1771 | temp = i915_mch_val(dev_priv); | |
1772 | chipset = i915_chipset_val(dev_priv); | |
1773 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1774 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1775 | |
1776 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1777 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1778 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1779 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1780 | ||
1781 | return 0; | |
1782 | } | |
1783 | ||
23b2f8bb JB |
1784 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1785 | { | |
9f25d007 | 1786 | struct drm_info_node *node = m->private; |
23b2f8bb | 1787 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1788 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1789 | int ret = 0; |
23b2f8bb | 1790 | int gpu_freq, ia_freq; |
f936ec34 | 1791 | unsigned int max_gpu_freq, min_gpu_freq; |
23b2f8bb | 1792 | |
97d3308a | 1793 | if (!HAS_CORE_RING_FREQ(dev)) { |
267f0c90 | 1794 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1795 | return 0; |
1796 | } | |
1797 | ||
5bfa0199 PZ |
1798 | intel_runtime_pm_get(dev_priv); |
1799 | ||
5c9669ce TR |
1800 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1801 | ||
4fc688ce | 1802 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1803 | if (ret) |
5bfa0199 | 1804 | goto out; |
23b2f8bb | 1805 | |
ef11bdb3 | 1806 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
f936ec34 AG |
1807 | /* Convert GT frequency to 50 HZ units */ |
1808 | min_gpu_freq = | |
1809 | dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; | |
1810 | max_gpu_freq = | |
1811 | dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; | |
1812 | } else { | |
1813 | min_gpu_freq = dev_priv->rps.min_freq_softlimit; | |
1814 | max_gpu_freq = dev_priv->rps.max_freq_softlimit; | |
1815 | } | |
1816 | ||
267f0c90 | 1817 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1818 | |
f936ec34 | 1819 | for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { |
42c0526c BW |
1820 | ia_freq = gpu_freq; |
1821 | sandybridge_pcode_read(dev_priv, | |
1822 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1823 | &ia_freq); | |
3ebecd07 | 1824 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
f936ec34 | 1825 | intel_gpu_freq(dev_priv, (gpu_freq * |
ef11bdb3 RV |
1826 | (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? |
1827 | GEN9_FREQ_SCALER : 1))), | |
3ebecd07 CW |
1828 | ((ia_freq >> 0) & 0xff) * 100, |
1829 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1830 | } |
1831 | ||
4fc688ce | 1832 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1833 | |
5bfa0199 PZ |
1834 | out: |
1835 | intel_runtime_pm_put(dev_priv); | |
1836 | return ret; | |
23b2f8bb JB |
1837 | } |
1838 | ||
44834a67 CW |
1839 | static int i915_opregion(struct seq_file *m, void *unused) |
1840 | { | |
9f25d007 | 1841 | struct drm_info_node *node = m->private; |
44834a67 | 1842 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1843 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 | 1844 | struct intel_opregion *opregion = &dev_priv->opregion; |
0d38f009 | 1845 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1846 | int ret; |
1847 | ||
0d38f009 DV |
1848 | if (data == NULL) |
1849 | return -ENOMEM; | |
1850 | ||
44834a67 CW |
1851 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1852 | if (ret) | |
0d38f009 | 1853 | goto out; |
44834a67 | 1854 | |
0d38f009 | 1855 | if (opregion->header) { |
115719fc | 1856 | memcpy(data, opregion->header, OPREGION_SIZE); |
0d38f009 DV |
1857 | seq_write(m, data, OPREGION_SIZE); |
1858 | } | |
44834a67 CW |
1859 | |
1860 | mutex_unlock(&dev->struct_mutex); | |
1861 | ||
0d38f009 DV |
1862 | out: |
1863 | kfree(data); | |
44834a67 CW |
1864 | return 0; |
1865 | } | |
1866 | ||
37811fcc CW |
1867 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1868 | { | |
9f25d007 | 1869 | struct drm_info_node *node = m->private; |
37811fcc | 1870 | struct drm_device *dev = node->minor->dev; |
b13b8402 | 1871 | struct intel_framebuffer *fbdev_fb = NULL; |
3a58ee10 | 1872 | struct drm_framebuffer *drm_fb; |
37811fcc | 1873 | |
0695726e | 1874 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
b13b8402 NS |
1875 | if (to_i915(dev)->fbdev) { |
1876 | fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb); | |
1877 | ||
1878 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", | |
1879 | fbdev_fb->base.width, | |
1880 | fbdev_fb->base.height, | |
1881 | fbdev_fb->base.depth, | |
1882 | fbdev_fb->base.bits_per_pixel, | |
1883 | fbdev_fb->base.modifier[0], | |
1884 | atomic_read(&fbdev_fb->base.refcount.refcount)); | |
1885 | describe_obj(m, fbdev_fb->obj); | |
1886 | seq_putc(m, '\n'); | |
1887 | } | |
4520f53a | 1888 | #endif |
37811fcc | 1889 | |
4b096ac1 | 1890 | mutex_lock(&dev->mode_config.fb_lock); |
3a58ee10 | 1891 | drm_for_each_fb(drm_fb, dev) { |
b13b8402 NS |
1892 | struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); |
1893 | if (fb == fbdev_fb) | |
37811fcc CW |
1894 | continue; |
1895 | ||
c1ca506d | 1896 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1897 | fb->base.width, |
1898 | fb->base.height, | |
1899 | fb->base.depth, | |
623f9783 | 1900 | fb->base.bits_per_pixel, |
c1ca506d | 1901 | fb->base.modifier[0], |
623f9783 | 1902 | atomic_read(&fb->base.refcount.refcount)); |
05394f39 | 1903 | describe_obj(m, fb->obj); |
267f0c90 | 1904 | seq_putc(m, '\n'); |
37811fcc | 1905 | } |
4b096ac1 | 1906 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1907 | |
1908 | return 0; | |
1909 | } | |
1910 | ||
c9fe99bd OM |
1911 | static void describe_ctx_ringbuf(struct seq_file *m, |
1912 | struct intel_ringbuffer *ringbuf) | |
1913 | { | |
1914 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
1915 | ringbuf->space, ringbuf->head, ringbuf->tail, | |
1916 | ringbuf->last_retired_head); | |
1917 | } | |
1918 | ||
e76d3630 BW |
1919 | static int i915_context_status(struct seq_file *m, void *unused) |
1920 | { | |
9f25d007 | 1921 | struct drm_info_node *node = m->private; |
e76d3630 | 1922 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1923 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1924 | struct intel_engine_cs *ring; |
273497e5 | 1925 | struct intel_context *ctx; |
a168c293 | 1926 | int ret, i; |
e76d3630 | 1927 | |
f3d28878 | 1928 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1929 | if (ret) |
1930 | return ret; | |
1931 | ||
a33afea5 | 1932 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
c9fe99bd OM |
1933 | if (!i915.enable_execlists && |
1934 | ctx->legacy_hw_ctx.rcs_state == NULL) | |
b77f6997 CW |
1935 | continue; |
1936 | ||
a33afea5 | 1937 | seq_puts(m, "HW context "); |
3ccfd19d | 1938 | describe_ctx(m, ctx); |
c9fe99bd | 1939 | for_each_ring(ring, dev_priv, i) { |
a33afea5 | 1940 | if (ring->default_context == ctx) |
c9fe99bd OM |
1941 | seq_printf(m, "(default context %s) ", |
1942 | ring->name); | |
1943 | } | |
1944 | ||
1945 | if (i915.enable_execlists) { | |
1946 | seq_putc(m, '\n'); | |
1947 | for_each_ring(ring, dev_priv, i) { | |
1948 | struct drm_i915_gem_object *ctx_obj = | |
1949 | ctx->engine[i].state; | |
1950 | struct intel_ringbuffer *ringbuf = | |
1951 | ctx->engine[i].ringbuf; | |
1952 | ||
1953 | seq_printf(m, "%s: ", ring->name); | |
1954 | if (ctx_obj) | |
1955 | describe_obj(m, ctx_obj); | |
1956 | if (ringbuf) | |
1957 | describe_ctx_ringbuf(m, ringbuf); | |
1958 | seq_putc(m, '\n'); | |
1959 | } | |
1960 | } else { | |
1961 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); | |
1962 | } | |
a33afea5 | 1963 | |
a33afea5 | 1964 | seq_putc(m, '\n'); |
a168c293 BW |
1965 | } |
1966 | ||
f3d28878 | 1967 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1968 | |
1969 | return 0; | |
1970 | } | |
1971 | ||
064ca1d2 TD |
1972 | static void i915_dump_lrc_obj(struct seq_file *m, |
1973 | struct intel_engine_cs *ring, | |
1974 | struct drm_i915_gem_object *ctx_obj) | |
1975 | { | |
1976 | struct page *page; | |
1977 | uint32_t *reg_state; | |
1978 | int j; | |
1979 | unsigned long ggtt_offset = 0; | |
1980 | ||
1981 | if (ctx_obj == NULL) { | |
1982 | seq_printf(m, "Context on %s with no gem object\n", | |
1983 | ring->name); | |
1984 | return; | |
1985 | } | |
1986 | ||
1987 | seq_printf(m, "CONTEXT: %s %u\n", ring->name, | |
1988 | intel_execlists_ctx_id(ctx_obj)); | |
1989 | ||
1990 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) | |
1991 | seq_puts(m, "\tNot bound in GGTT\n"); | |
1992 | else | |
1993 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); | |
1994 | ||
1995 | if (i915_gem_object_get_pages(ctx_obj)) { | |
1996 | seq_puts(m, "\tFailed to get pages for context object\n"); | |
1997 | return; | |
1998 | } | |
1999 | ||
d1675198 | 2000 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
064ca1d2 TD |
2001 | if (!WARN_ON(page == NULL)) { |
2002 | reg_state = kmap_atomic(page); | |
2003 | ||
2004 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
2005 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2006 | ggtt_offset + 4096 + (j * 4), | |
2007 | reg_state[j], reg_state[j + 1], | |
2008 | reg_state[j + 2], reg_state[j + 3]); | |
2009 | } | |
2010 | kunmap_atomic(reg_state); | |
2011 | } | |
2012 | ||
2013 | seq_putc(m, '\n'); | |
2014 | } | |
2015 | ||
c0ab1ae9 BW |
2016 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2017 | { | |
2018 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2019 | struct drm_device *dev = node->minor->dev; | |
2020 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2021 | struct intel_engine_cs *ring; | |
2022 | struct intel_context *ctx; | |
2023 | int ret, i; | |
2024 | ||
2025 | if (!i915.enable_execlists) { | |
2026 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2027 | return 0; | |
2028 | } | |
2029 | ||
2030 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2031 | if (ret) | |
2032 | return ret; | |
2033 | ||
2034 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
2035 | for_each_ring(ring, dev_priv, i) { | |
064ca1d2 TD |
2036 | if (ring->default_context != ctx) |
2037 | i915_dump_lrc_obj(m, ring, | |
2038 | ctx->engine[i].state); | |
c0ab1ae9 BW |
2039 | } |
2040 | } | |
2041 | ||
2042 | mutex_unlock(&dev->struct_mutex); | |
2043 | ||
2044 | return 0; | |
2045 | } | |
2046 | ||
4ba70e44 OM |
2047 | static int i915_execlists(struct seq_file *m, void *data) |
2048 | { | |
2049 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
2050 | struct drm_device *dev = node->minor->dev; | |
2051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2052 | struct intel_engine_cs *ring; | |
2053 | u32 status_pointer; | |
2054 | u8 read_pointer; | |
2055 | u8 write_pointer; | |
2056 | u32 status; | |
2057 | u32 ctx_id; | |
2058 | struct list_head *cursor; | |
2059 | int ring_id, i; | |
2060 | int ret; | |
2061 | ||
2062 | if (!i915.enable_execlists) { | |
2063 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
2064 | return 0; | |
2065 | } | |
2066 | ||
2067 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2068 | if (ret) | |
2069 | return ret; | |
2070 | ||
fc0412ec MT |
2071 | intel_runtime_pm_get(dev_priv); |
2072 | ||
4ba70e44 | 2073 | for_each_ring(ring, dev_priv, ring_id) { |
6d3d8274 | 2074 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 OM |
2075 | int count = 0; |
2076 | unsigned long flags; | |
2077 | ||
2078 | seq_printf(m, "%s\n", ring->name); | |
2079 | ||
83843d84 VS |
2080 | status = I915_READ(RING_EXECLIST_STATUS_LO(ring)); |
2081 | ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring)); | |
4ba70e44 OM |
2082 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", |
2083 | status, ctx_id); | |
2084 | ||
2085 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
2086 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); | |
2087 | ||
2088 | read_pointer = ring->next_context_status_buffer; | |
2089 | write_pointer = status_pointer & 0x07; | |
2090 | if (read_pointer > write_pointer) | |
2091 | write_pointer += 6; | |
2092 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", | |
2093 | read_pointer, write_pointer); | |
2094 | ||
2095 | for (i = 0; i < 6; i++) { | |
83843d84 VS |
2096 | status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i)); |
2097 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i)); | |
4ba70e44 OM |
2098 | |
2099 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
2100 | i, status, ctx_id); | |
2101 | } | |
2102 | ||
2103 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2104 | list_for_each(cursor, &ring->execlist_queue) | |
2105 | count++; | |
2106 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
6d3d8274 | 2107 | struct drm_i915_gem_request, execlist_link); |
4ba70e44 OM |
2108 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
2109 | ||
2110 | seq_printf(m, "\t%d requests in queue\n", count); | |
2111 | if (head_req) { | |
2112 | struct drm_i915_gem_object *ctx_obj; | |
2113 | ||
6d3d8274 | 2114 | ctx_obj = head_req->ctx->engine[ring_id].state; |
4ba70e44 OM |
2115 | seq_printf(m, "\tHead request id: %u\n", |
2116 | intel_execlists_ctx_id(ctx_obj)); | |
2117 | seq_printf(m, "\tHead request tail: %u\n", | |
6d3d8274 | 2118 | head_req->tail); |
4ba70e44 OM |
2119 | } |
2120 | ||
2121 | seq_putc(m, '\n'); | |
2122 | } | |
2123 | ||
fc0412ec | 2124 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2125 | mutex_unlock(&dev->struct_mutex); |
2126 | ||
2127 | return 0; | |
2128 | } | |
2129 | ||
ea16a3cd DV |
2130 | static const char *swizzle_string(unsigned swizzle) |
2131 | { | |
aee56cff | 2132 | switch (swizzle) { |
ea16a3cd DV |
2133 | case I915_BIT_6_SWIZZLE_NONE: |
2134 | return "none"; | |
2135 | case I915_BIT_6_SWIZZLE_9: | |
2136 | return "bit9"; | |
2137 | case I915_BIT_6_SWIZZLE_9_10: | |
2138 | return "bit9/bit10"; | |
2139 | case I915_BIT_6_SWIZZLE_9_11: | |
2140 | return "bit9/bit11"; | |
2141 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2142 | return "bit9/bit10/bit11"; | |
2143 | case I915_BIT_6_SWIZZLE_9_17: | |
2144 | return "bit9/bit17"; | |
2145 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2146 | return "bit9/bit10/bit17"; | |
2147 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2148 | return "unknown"; |
ea16a3cd DV |
2149 | } |
2150 | ||
2151 | return "bug"; | |
2152 | } | |
2153 | ||
2154 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2155 | { | |
9f25d007 | 2156 | struct drm_info_node *node = m->private; |
ea16a3cd DV |
2157 | struct drm_device *dev = node->minor->dev; |
2158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
2159 | int ret; |
2160 | ||
2161 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2162 | if (ret) | |
2163 | return ret; | |
c8c8fb33 | 2164 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2165 | |
ea16a3cd DV |
2166 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2167 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2168 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2169 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2170 | ||
2171 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
2172 | seq_printf(m, "DDC = 0x%08x\n", | |
2173 | I915_READ(DCC)); | |
656bfa3a DV |
2174 | seq_printf(m, "DDC2 = 0x%08x\n", |
2175 | I915_READ(DCC2)); | |
ea16a3cd DV |
2176 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2177 | I915_READ16(C0DRB3)); | |
2178 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2179 | I915_READ16(C1DRB3)); | |
9d3203e1 | 2180 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
2181 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2182 | I915_READ(MAD_DIMM_C0)); | |
2183 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2184 | I915_READ(MAD_DIMM_C1)); | |
2185 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2186 | I915_READ(MAD_DIMM_C2)); | |
2187 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2188 | I915_READ(TILECTL)); | |
5907f5fb | 2189 | if (INTEL_INFO(dev)->gen >= 8) |
9d3203e1 BW |
2190 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2191 | I915_READ(GAMTARBMODE)); | |
2192 | else | |
2193 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2194 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2195 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2196 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2197 | } |
656bfa3a DV |
2198 | |
2199 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2200 | seq_puts(m, "L-shaped memory detected\n"); | |
2201 | ||
c8c8fb33 | 2202 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2203 | mutex_unlock(&dev->struct_mutex); |
2204 | ||
2205 | return 0; | |
2206 | } | |
2207 | ||
1c60fef5 BW |
2208 | static int per_file_ctx(int id, void *ptr, void *data) |
2209 | { | |
273497e5 | 2210 | struct intel_context *ctx = ptr; |
1c60fef5 | 2211 | struct seq_file *m = data; |
ae6c4806 DV |
2212 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2213 | ||
2214 | if (!ppgtt) { | |
2215 | seq_printf(m, " no ppgtt for context %d\n", | |
2216 | ctx->user_handle); | |
2217 | return 0; | |
2218 | } | |
1c60fef5 | 2219 | |
f83d6518 OM |
2220 | if (i915_gem_context_is_default(ctx)) |
2221 | seq_puts(m, " default context:\n"); | |
2222 | else | |
821d66dd | 2223 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2224 | ppgtt->debug_dump(ppgtt, m); |
2225 | ||
2226 | return 0; | |
2227 | } | |
2228 | ||
77df6772 | 2229 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 2230 | { |
3cf17fc5 | 2231 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2232 | struct intel_engine_cs *ring; |
77df6772 BW |
2233 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
2234 | int unused, i; | |
3cf17fc5 | 2235 | |
77df6772 BW |
2236 | if (!ppgtt) |
2237 | return; | |
2238 | ||
77df6772 BW |
2239 | for_each_ring(ring, dev_priv, unused) { |
2240 | seq_printf(m, "%s\n", ring->name); | |
2241 | for (i = 0; i < 4; i++) { | |
d3a93cbe | 2242 | u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i)); |
77df6772 | 2243 | pdp <<= 32; |
d3a93cbe | 2244 | pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i)); |
a2a5b15c | 2245 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2246 | } |
2247 | } | |
2248 | } | |
2249 | ||
2250 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
2251 | { | |
2252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2253 | struct intel_engine_cs *ring; |
77df6772 | 2254 | int i; |
3cf17fc5 | 2255 | |
3cf17fc5 DV |
2256 | if (INTEL_INFO(dev)->gen == 6) |
2257 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
2258 | ||
a2c7f6fd | 2259 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
2260 | seq_printf(m, "%s\n", ring->name); |
2261 | if (INTEL_INFO(dev)->gen == 7) | |
2262 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
2263 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
2264 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
2265 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
2266 | } | |
2267 | if (dev_priv->mm.aliasing_ppgtt) { | |
2268 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2269 | ||
267f0c90 | 2270 | seq_puts(m, "aliasing PPGTT:\n"); |
44159ddb | 2271 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); |
1c60fef5 | 2272 | |
87d60b63 | 2273 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2274 | } |
1c60fef5 | 2275 | |
3cf17fc5 | 2276 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); |
77df6772 BW |
2277 | } |
2278 | ||
2279 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2280 | { | |
9f25d007 | 2281 | struct drm_info_node *node = m->private; |
77df6772 | 2282 | struct drm_device *dev = node->minor->dev; |
c8c8fb33 | 2283 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea91e401 | 2284 | struct drm_file *file; |
77df6772 BW |
2285 | |
2286 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2287 | if (ret) | |
2288 | return ret; | |
c8c8fb33 | 2289 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
2290 | |
2291 | if (INTEL_INFO(dev)->gen >= 8) | |
2292 | gen8_ppgtt_info(m, dev); | |
2293 | else if (INTEL_INFO(dev)->gen >= 6) | |
2294 | gen6_ppgtt_info(m, dev); | |
2295 | ||
ea91e401 MT |
2296 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2297 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
7cb5dff8 | 2298 | struct task_struct *task; |
ea91e401 | 2299 | |
7cb5dff8 | 2300 | task = get_pid_task(file->pid, PIDTYPE_PID); |
06812760 DC |
2301 | if (!task) { |
2302 | ret = -ESRCH; | |
2303 | goto out_put; | |
2304 | } | |
7cb5dff8 GT |
2305 | seq_printf(m, "\nproc: %s\n", task->comm); |
2306 | put_task_struct(task); | |
ea91e401 MT |
2307 | idr_for_each(&file_priv->context_idr, per_file_ctx, |
2308 | (void *)(unsigned long)m); | |
2309 | } | |
2310 | ||
06812760 | 2311 | out_put: |
c8c8fb33 | 2312 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
2313 | mutex_unlock(&dev->struct_mutex); |
2314 | ||
06812760 | 2315 | return ret; |
3cf17fc5 DV |
2316 | } |
2317 | ||
f5a4c67d CW |
2318 | static int count_irq_waiters(struct drm_i915_private *i915) |
2319 | { | |
2320 | struct intel_engine_cs *ring; | |
2321 | int count = 0; | |
2322 | int i; | |
2323 | ||
2324 | for_each_ring(ring, i915, i) | |
2325 | count += ring->irq_refcount; | |
2326 | ||
2327 | return count; | |
2328 | } | |
2329 | ||
1854d5ca CW |
2330 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2331 | { | |
2332 | struct drm_info_node *node = m->private; | |
2333 | struct drm_device *dev = node->minor->dev; | |
2334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2335 | struct drm_file *file; | |
1854d5ca | 2336 | |
f5a4c67d CW |
2337 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
2338 | seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); | |
2339 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); | |
2340 | seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
2341 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
2342 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
2343 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2344 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2345 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
8d3afd7d | 2346 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2347 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2348 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2349 | struct task_struct *task; | |
2350 | ||
2351 | rcu_read_lock(); | |
2352 | task = pid_task(file->pid, PIDTYPE_PID); | |
2353 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2354 | task ? task->comm : "<unknown>", | |
2355 | task ? task->pid : -1, | |
2e1b8730 CW |
2356 | file_priv->rps.boosts, |
2357 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2358 | rcu_read_unlock(); |
2359 | } | |
2e1b8730 CW |
2360 | seq_printf(m, "Semaphore boosts: %d%s\n", |
2361 | dev_priv->rps.semaphores.boosts, | |
2362 | list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active"); | |
2363 | seq_printf(m, "MMIO flip boosts: %d%s\n", | |
2364 | dev_priv->rps.mmioflips.boosts, | |
2365 | list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); | |
1854d5ca | 2366 | seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2367 | spin_unlock(&dev_priv->rps.client_lock); |
1854d5ca | 2368 | |
8d3afd7d | 2369 | return 0; |
1854d5ca CW |
2370 | } |
2371 | ||
63573eb7 BW |
2372 | static int i915_llc(struct seq_file *m, void *data) |
2373 | { | |
9f25d007 | 2374 | struct drm_info_node *node = m->private; |
63573eb7 BW |
2375 | struct drm_device *dev = node->minor->dev; |
2376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2377 | ||
2378 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
2379 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
2380 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
2381 | ||
2382 | return 0; | |
2383 | } | |
2384 | ||
fdf5d357 AD |
2385 | static int i915_guc_load_status_info(struct seq_file *m, void *data) |
2386 | { | |
2387 | struct drm_info_node *node = m->private; | |
2388 | struct drm_i915_private *dev_priv = node->minor->dev->dev_private; | |
2389 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
2390 | u32 tmp, i; | |
2391 | ||
2392 | if (!HAS_GUC_UCODE(dev_priv->dev)) | |
2393 | return 0; | |
2394 | ||
2395 | seq_printf(m, "GuC firmware status:\n"); | |
2396 | seq_printf(m, "\tpath: %s\n", | |
2397 | guc_fw->guc_fw_path); | |
2398 | seq_printf(m, "\tfetch: %s\n", | |
2399 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
2400 | seq_printf(m, "\tload: %s\n", | |
2401 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
2402 | seq_printf(m, "\tversion wanted: %d.%d\n", | |
2403 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
2404 | seq_printf(m, "\tversion found: %d.%d\n", | |
2405 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); | |
feda33ef AD |
2406 | seq_printf(m, "\theader: offset is %d; size = %d\n", |
2407 | guc_fw->header_offset, guc_fw->header_size); | |
2408 | seq_printf(m, "\tuCode: offset is %d; size = %d\n", | |
2409 | guc_fw->ucode_offset, guc_fw->ucode_size); | |
2410 | seq_printf(m, "\tRSA: offset is %d; size = %d\n", | |
2411 | guc_fw->rsa_offset, guc_fw->rsa_size); | |
fdf5d357 AD |
2412 | |
2413 | tmp = I915_READ(GUC_STATUS); | |
2414 | ||
2415 | seq_printf(m, "\nGuC status 0x%08x:\n", tmp); | |
2416 | seq_printf(m, "\tBootrom status = 0x%x\n", | |
2417 | (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); | |
2418 | seq_printf(m, "\tuKernel status = 0x%x\n", | |
2419 | (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); | |
2420 | seq_printf(m, "\tMIA Core status = 0x%x\n", | |
2421 | (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); | |
2422 | seq_puts(m, "\nScratch registers:\n"); | |
2423 | for (i = 0; i < 16; i++) | |
2424 | seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); | |
2425 | ||
2426 | return 0; | |
2427 | } | |
2428 | ||
8b417c26 DG |
2429 | static void i915_guc_client_info(struct seq_file *m, |
2430 | struct drm_i915_private *dev_priv, | |
2431 | struct i915_guc_client *client) | |
2432 | { | |
2433 | struct intel_engine_cs *ring; | |
2434 | uint64_t tot = 0; | |
2435 | uint32_t i; | |
2436 | ||
2437 | seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", | |
2438 | client->priority, client->ctx_index, client->proc_desc_offset); | |
2439 | seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", | |
2440 | client->doorbell_id, client->doorbell_offset, client->cookie); | |
2441 | seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", | |
2442 | client->wq_size, client->wq_offset, client->wq_tail); | |
2443 | ||
2444 | seq_printf(m, "\tFailed to queue: %u\n", client->q_fail); | |
2445 | seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); | |
2446 | seq_printf(m, "\tLast submission result: %d\n", client->retcode); | |
2447 | ||
2448 | for_each_ring(ring, dev_priv, i) { | |
2449 | seq_printf(m, "\tSubmissions: %llu %s\n", | |
2450 | client->submissions[i], | |
2451 | ring->name); | |
2452 | tot += client->submissions[i]; | |
2453 | } | |
2454 | seq_printf(m, "\tTotal: %llu\n", tot); | |
2455 | } | |
2456 | ||
2457 | static int i915_guc_info(struct seq_file *m, void *data) | |
2458 | { | |
2459 | struct drm_info_node *node = m->private; | |
2460 | struct drm_device *dev = node->minor->dev; | |
2461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2462 | struct intel_guc guc; | |
0a0b457f | 2463 | struct i915_guc_client client = {}; |
8b417c26 DG |
2464 | struct intel_engine_cs *ring; |
2465 | enum intel_ring_id i; | |
2466 | u64 total = 0; | |
2467 | ||
2468 | if (!HAS_GUC_SCHED(dev_priv->dev)) | |
2469 | return 0; | |
2470 | ||
5a843307 AD |
2471 | if (mutex_lock_interruptible(&dev->struct_mutex)) |
2472 | return 0; | |
2473 | ||
8b417c26 | 2474 | /* Take a local copy of the GuC data, so we can dump it at leisure */ |
8b417c26 | 2475 | guc = dev_priv->guc; |
5a843307 | 2476 | if (guc.execbuf_client) |
8b417c26 | 2477 | client = *guc.execbuf_client; |
5a843307 AD |
2478 | |
2479 | mutex_unlock(&dev->struct_mutex); | |
8b417c26 DG |
2480 | |
2481 | seq_printf(m, "GuC total action count: %llu\n", guc.action_count); | |
2482 | seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); | |
2483 | seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); | |
2484 | seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); | |
2485 | seq_printf(m, "GuC last action error code: %d\n", guc.action_err); | |
2486 | ||
2487 | seq_printf(m, "\nGuC submissions:\n"); | |
2488 | for_each_ring(ring, dev_priv, i) { | |
2489 | seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n", | |
2490 | ring->name, guc.submissions[i], | |
2491 | guc.last_seqno[i], guc.last_seqno[i]); | |
2492 | total += guc.submissions[i]; | |
2493 | } | |
2494 | seq_printf(m, "\t%s: %llu\n", "Total", total); | |
2495 | ||
2496 | seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); | |
2497 | i915_guc_client_info(m, dev_priv, &client); | |
2498 | ||
2499 | /* Add more as required ... */ | |
2500 | ||
2501 | return 0; | |
2502 | } | |
2503 | ||
4c7e77fc AD |
2504 | static int i915_guc_log_dump(struct seq_file *m, void *data) |
2505 | { | |
2506 | struct drm_info_node *node = m->private; | |
2507 | struct drm_device *dev = node->minor->dev; | |
2508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2509 | struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj; | |
2510 | u32 *log; | |
2511 | int i = 0, pg; | |
2512 | ||
2513 | if (!log_obj) | |
2514 | return 0; | |
2515 | ||
2516 | for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) { | |
2517 | log = kmap_atomic(i915_gem_object_get_page(log_obj, pg)); | |
2518 | ||
2519 | for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) | |
2520 | seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", | |
2521 | *(log + i), *(log + i + 1), | |
2522 | *(log + i + 2), *(log + i + 3)); | |
2523 | ||
2524 | kunmap_atomic(log); | |
2525 | } | |
2526 | ||
2527 | seq_putc(m, '\n'); | |
2528 | ||
2529 | return 0; | |
2530 | } | |
2531 | ||
e91fd8c6 RV |
2532 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2533 | { | |
2534 | struct drm_info_node *node = m->private; | |
2535 | struct drm_device *dev = node->minor->dev; | |
2536 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 | 2537 | u32 psrperf = 0; |
a6cbdb8e RV |
2538 | u32 stat[3]; |
2539 | enum pipe pipe; | |
a031d709 | 2540 | bool enabled = false; |
e91fd8c6 | 2541 | |
3553a8ea DL |
2542 | if (!HAS_PSR(dev)) { |
2543 | seq_puts(m, "PSR not supported\n"); | |
2544 | return 0; | |
2545 | } | |
2546 | ||
c8c8fb33 PZ |
2547 | intel_runtime_pm_get(dev_priv); |
2548 | ||
fa128fa6 | 2549 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2550 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2551 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2552 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2553 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2554 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2555 | dev_priv->psr.busy_frontbuffer_bits); | |
2556 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2557 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2558 | |
3553a8ea | 2559 | if (HAS_DDI(dev)) |
443a389f | 2560 | enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; |
3553a8ea DL |
2561 | else { |
2562 | for_each_pipe(dev_priv, pipe) { | |
2563 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2564 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2565 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2566 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2567 | enabled = true; | |
a6cbdb8e RV |
2568 | } |
2569 | } | |
2570 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); | |
2571 | ||
2572 | if (!HAS_DDI(dev)) | |
2573 | for_each_pipe(dev_priv, pipe) { | |
2574 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2575 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2576 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2577 | } | |
2578 | seq_puts(m, "\n"); | |
e91fd8c6 | 2579 | |
05eec3c2 RV |
2580 | /* |
2581 | * VLV/CHV PSR has no kind of performance counter | |
2582 | * SKL+ Perf counter is reset to 0 everytime DC state is entered | |
2583 | */ | |
2584 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
443a389f | 2585 | psrperf = I915_READ(EDP_PSR_PERF_CNT) & |
a031d709 | 2586 | EDP_PSR_PERF_CNT_MASK; |
a6cbdb8e RV |
2587 | |
2588 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2589 | } | |
fa128fa6 | 2590 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2591 | |
c8c8fb33 | 2592 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2593 | return 0; |
2594 | } | |
2595 | ||
d2e216d0 RV |
2596 | static int i915_sink_crc(struct seq_file *m, void *data) |
2597 | { | |
2598 | struct drm_info_node *node = m->private; | |
2599 | struct drm_device *dev = node->minor->dev; | |
2600 | struct intel_encoder *encoder; | |
2601 | struct intel_connector *connector; | |
2602 | struct intel_dp *intel_dp = NULL; | |
2603 | int ret; | |
2604 | u8 crc[6]; | |
2605 | ||
2606 | drm_modeset_lock_all(dev); | |
aca5e361 | 2607 | for_each_intel_connector(dev, connector) { |
d2e216d0 RV |
2608 | |
2609 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
2610 | continue; | |
2611 | ||
b6ae3c7c PZ |
2612 | if (!connector->base.encoder) |
2613 | continue; | |
2614 | ||
d2e216d0 RV |
2615 | encoder = to_intel_encoder(connector->base.encoder); |
2616 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2617 | continue; | |
2618 | ||
2619 | intel_dp = enc_to_intel_dp(&encoder->base); | |
2620 | ||
2621 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2622 | if (ret) | |
2623 | goto out; | |
2624 | ||
2625 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2626 | crc[0], crc[1], crc[2], | |
2627 | crc[3], crc[4], crc[5]); | |
2628 | goto out; | |
2629 | } | |
2630 | ret = -ENODEV; | |
2631 | out: | |
2632 | drm_modeset_unlock_all(dev); | |
2633 | return ret; | |
2634 | } | |
2635 | ||
ec013e7f JB |
2636 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2637 | { | |
2638 | struct drm_info_node *node = m->private; | |
2639 | struct drm_device *dev = node->minor->dev; | |
2640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2641 | u64 power; | |
2642 | u32 units; | |
2643 | ||
2644 | if (INTEL_INFO(dev)->gen < 6) | |
2645 | return -ENODEV; | |
2646 | ||
36623ef8 PZ |
2647 | intel_runtime_pm_get(dev_priv); |
2648 | ||
ec013e7f JB |
2649 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2650 | power = (power & 0x1f00) >> 8; | |
2651 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2652 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2653 | power *= units; | |
2654 | ||
36623ef8 PZ |
2655 | intel_runtime_pm_put(dev_priv); |
2656 | ||
ec013e7f | 2657 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2658 | |
2659 | return 0; | |
2660 | } | |
2661 | ||
6455c870 | 2662 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2663 | { |
9f25d007 | 2664 | struct drm_info_node *node = m->private; |
371db66a PZ |
2665 | struct drm_device *dev = node->minor->dev; |
2666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2667 | ||
6455c870 | 2668 | if (!HAS_RUNTIME_PM(dev)) { |
371db66a PZ |
2669 | seq_puts(m, "not supported\n"); |
2670 | return 0; | |
2671 | } | |
2672 | ||
86c4ec0d | 2673 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2674 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2675 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2676 | #ifdef CONFIG_PM |
a6aaec8b DL |
2677 | seq_printf(m, "Usage count: %d\n", |
2678 | atomic_read(&dev->dev->power.usage_count)); | |
0d804184 CW |
2679 | #else |
2680 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2681 | #endif | |
371db66a | 2682 | |
ec013e7f JB |
2683 | return 0; |
2684 | } | |
2685 | ||
1da51581 ID |
2686 | static int i915_power_domain_info(struct seq_file *m, void *unused) |
2687 | { | |
9f25d007 | 2688 | struct drm_info_node *node = m->private; |
1da51581 ID |
2689 | struct drm_device *dev = node->minor->dev; |
2690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2691 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2692 | int i; | |
2693 | ||
2694 | mutex_lock(&power_domains->lock); | |
2695 | ||
2696 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2697 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2698 | struct i915_power_well *power_well; | |
2699 | enum intel_display_power_domain power_domain; | |
2700 | ||
2701 | power_well = &power_domains->power_wells[i]; | |
2702 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2703 | power_well->count); | |
2704 | ||
2705 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2706 | power_domain++) { | |
2707 | if (!(BIT(power_domain) & power_well->domains)) | |
2708 | continue; | |
2709 | ||
2710 | seq_printf(m, " %-23s %d\n", | |
9895ad03 | 2711 | intel_display_power_domain_str(power_domain), |
1da51581 ID |
2712 | power_domains->domain_use_count[power_domain]); |
2713 | } | |
2714 | } | |
2715 | ||
2716 | mutex_unlock(&power_domains->lock); | |
2717 | ||
2718 | return 0; | |
2719 | } | |
2720 | ||
b7cec66d DL |
2721 | static int i915_dmc_info(struct seq_file *m, void *unused) |
2722 | { | |
2723 | struct drm_info_node *node = m->private; | |
2724 | struct drm_device *dev = node->minor->dev; | |
2725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2726 | struct intel_csr *csr; | |
2727 | ||
2728 | if (!HAS_CSR(dev)) { | |
2729 | seq_puts(m, "not supported\n"); | |
2730 | return 0; | |
2731 | } | |
2732 | ||
2733 | csr = &dev_priv->csr; | |
2734 | ||
6fb403de MK |
2735 | intel_runtime_pm_get(dev_priv); |
2736 | ||
b7cec66d DL |
2737 | seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); |
2738 | seq_printf(m, "path: %s\n", csr->fw_path); | |
2739 | ||
2740 | if (!csr->dmc_payload) | |
6fb403de | 2741 | goto out; |
b7cec66d DL |
2742 | |
2743 | seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), | |
2744 | CSR_VERSION_MINOR(csr->version)); | |
2745 | ||
8337206d DL |
2746 | if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { |
2747 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2748 | I915_READ(SKL_CSR_DC3_DC5_COUNT)); | |
2749 | seq_printf(m, "DC5 -> DC6 count: %d\n", | |
2750 | I915_READ(SKL_CSR_DC5_DC6_COUNT)); | |
16e11b99 MK |
2751 | } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) { |
2752 | seq_printf(m, "DC3 -> DC5 count: %d\n", | |
2753 | I915_READ(BXT_CSR_DC3_DC5_COUNT)); | |
8337206d DL |
2754 | } |
2755 | ||
6fb403de MK |
2756 | out: |
2757 | seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); | |
2758 | seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); | |
2759 | seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); | |
2760 | ||
8337206d DL |
2761 | intel_runtime_pm_put(dev_priv); |
2762 | ||
b7cec66d DL |
2763 | return 0; |
2764 | } | |
2765 | ||
53f5e3ca JB |
2766 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2767 | struct drm_display_mode *mode) | |
2768 | { | |
2769 | int i; | |
2770 | ||
2771 | for (i = 0; i < tabs; i++) | |
2772 | seq_putc(m, '\t'); | |
2773 | ||
2774 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2775 | mode->base.id, mode->name, | |
2776 | mode->vrefresh, mode->clock, | |
2777 | mode->hdisplay, mode->hsync_start, | |
2778 | mode->hsync_end, mode->htotal, | |
2779 | mode->vdisplay, mode->vsync_start, | |
2780 | mode->vsync_end, mode->vtotal, | |
2781 | mode->type, mode->flags); | |
2782 | } | |
2783 | ||
2784 | static void intel_encoder_info(struct seq_file *m, | |
2785 | struct intel_crtc *intel_crtc, | |
2786 | struct intel_encoder *intel_encoder) | |
2787 | { | |
9f25d007 | 2788 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2789 | struct drm_device *dev = node->minor->dev; |
2790 | struct drm_crtc *crtc = &intel_crtc->base; | |
2791 | struct intel_connector *intel_connector; | |
2792 | struct drm_encoder *encoder; | |
2793 | ||
2794 | encoder = &intel_encoder->base; | |
2795 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2796 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2797 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2798 | struct drm_connector *connector = &intel_connector->base; | |
2799 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2800 | connector->base.id, | |
c23cc417 | 2801 | connector->name, |
53f5e3ca JB |
2802 | drm_get_connector_status_name(connector->status)); |
2803 | if (connector->status == connector_status_connected) { | |
2804 | struct drm_display_mode *mode = &crtc->mode; | |
2805 | seq_printf(m, ", mode:\n"); | |
2806 | intel_seq_print_mode(m, 2, mode); | |
2807 | } else { | |
2808 | seq_putc(m, '\n'); | |
2809 | } | |
2810 | } | |
2811 | } | |
2812 | ||
2813 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2814 | { | |
9f25d007 | 2815 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2816 | struct drm_device *dev = node->minor->dev; |
2817 | struct drm_crtc *crtc = &intel_crtc->base; | |
2818 | struct intel_encoder *intel_encoder; | |
23a48d53 ML |
2819 | struct drm_plane_state *plane_state = crtc->primary->state; |
2820 | struct drm_framebuffer *fb = plane_state->fb; | |
53f5e3ca | 2821 | |
23a48d53 | 2822 | if (fb) |
5aa8a937 | 2823 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", |
23a48d53 ML |
2824 | fb->base.id, plane_state->src_x >> 16, |
2825 | plane_state->src_y >> 16, fb->width, fb->height); | |
5aa8a937 MR |
2826 | else |
2827 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2828 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2829 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2830 | } | |
2831 | ||
2832 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2833 | { | |
2834 | struct drm_display_mode *mode = panel->fixed_mode; | |
2835 | ||
2836 | seq_printf(m, "\tfixed mode:\n"); | |
2837 | intel_seq_print_mode(m, 2, mode); | |
2838 | } | |
2839 | ||
2840 | static void intel_dp_info(struct seq_file *m, | |
2841 | struct intel_connector *intel_connector) | |
2842 | { | |
2843 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2844 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2845 | ||
2846 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
742f491d | 2847 | seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); |
53f5e3ca JB |
2848 | if (intel_encoder->type == INTEL_OUTPUT_EDP) |
2849 | intel_panel_info(m, &intel_connector->panel); | |
2850 | } | |
2851 | ||
3d52ccf5 LY |
2852 | static void intel_dp_mst_info(struct seq_file *m, |
2853 | struct intel_connector *intel_connector) | |
2854 | { | |
2855 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2856 | struct intel_dp_mst_encoder *intel_mst = | |
2857 | enc_to_mst(&intel_encoder->base); | |
2858 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
2859 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2860 | bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, | |
2861 | intel_connector->port); | |
2862 | ||
2863 | seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); | |
2864 | } | |
2865 | ||
53f5e3ca JB |
2866 | static void intel_hdmi_info(struct seq_file *m, |
2867 | struct intel_connector *intel_connector) | |
2868 | { | |
2869 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2870 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2871 | ||
742f491d | 2872 | seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); |
53f5e3ca JB |
2873 | } |
2874 | ||
2875 | static void intel_lvds_info(struct seq_file *m, | |
2876 | struct intel_connector *intel_connector) | |
2877 | { | |
2878 | intel_panel_info(m, &intel_connector->panel); | |
2879 | } | |
2880 | ||
2881 | static void intel_connector_info(struct seq_file *m, | |
2882 | struct drm_connector *connector) | |
2883 | { | |
2884 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2885 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2886 | struct drm_display_mode *mode; |
53f5e3ca JB |
2887 | |
2888 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2889 | connector->base.id, connector->name, |
53f5e3ca JB |
2890 | drm_get_connector_status_name(connector->status)); |
2891 | if (connector->status == connector_status_connected) { | |
2892 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2893 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2894 | connector->display_info.width_mm, | |
2895 | connector->display_info.height_mm); | |
2896 | seq_printf(m, "\tsubpixel order: %s\n", | |
2897 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2898 | seq_printf(m, "\tCEA rev: %d\n", | |
2899 | connector->display_info.cea_rev); | |
2900 | } | |
36cd7444 DA |
2901 | if (intel_encoder) { |
2902 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2903 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2904 | intel_dp_info(m, intel_connector); | |
2905 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2906 | intel_hdmi_info(m, intel_connector); | |
2907 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2908 | intel_lvds_info(m, intel_connector); | |
3d52ccf5 LY |
2909 | else if (intel_encoder->type == INTEL_OUTPUT_DP_MST) |
2910 | intel_dp_mst_info(m, intel_connector); | |
36cd7444 | 2911 | } |
53f5e3ca | 2912 | |
f103fc7d JB |
2913 | seq_printf(m, "\tmodes:\n"); |
2914 | list_for_each_entry(mode, &connector->modes, head) | |
2915 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2916 | } |
2917 | ||
065f2ec2 CW |
2918 | static bool cursor_active(struct drm_device *dev, int pipe) |
2919 | { | |
2920 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2921 | u32 state; | |
2922 | ||
2923 | if (IS_845G(dev) || IS_I865G(dev)) | |
0b87c24e | 2924 | state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
065f2ec2 | 2925 | else |
5efb3e28 | 2926 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2927 | |
2928 | return state; | |
2929 | } | |
2930 | ||
2931 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2932 | { | |
2933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2934 | u32 pos; | |
2935 | ||
5efb3e28 | 2936 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2937 | |
2938 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2939 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2940 | *x = -*x; | |
2941 | ||
2942 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2943 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2944 | *y = -*y; | |
2945 | ||
2946 | return cursor_active(dev, pipe); | |
2947 | } | |
2948 | ||
3abc4e09 RF |
2949 | static const char *plane_type(enum drm_plane_type type) |
2950 | { | |
2951 | switch (type) { | |
2952 | case DRM_PLANE_TYPE_OVERLAY: | |
2953 | return "OVL"; | |
2954 | case DRM_PLANE_TYPE_PRIMARY: | |
2955 | return "PRI"; | |
2956 | case DRM_PLANE_TYPE_CURSOR: | |
2957 | return "CUR"; | |
2958 | /* | |
2959 | * Deliberately omitting default: to generate compiler warnings | |
2960 | * when a new drm_plane_type gets added. | |
2961 | */ | |
2962 | } | |
2963 | ||
2964 | return "unknown"; | |
2965 | } | |
2966 | ||
2967 | static const char *plane_rotation(unsigned int rotation) | |
2968 | { | |
2969 | static char buf[48]; | |
2970 | /* | |
2971 | * According to doc only one DRM_ROTATE_ is allowed but this | |
2972 | * will print them all to visualize if the values are misused | |
2973 | */ | |
2974 | snprintf(buf, sizeof(buf), | |
2975 | "%s%s%s%s%s%s(0x%08x)", | |
2976 | (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "", | |
2977 | (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "", | |
2978 | (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "", | |
2979 | (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "", | |
2980 | (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "", | |
2981 | (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "", | |
2982 | rotation); | |
2983 | ||
2984 | return buf; | |
2985 | } | |
2986 | ||
2987 | static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2988 | { | |
2989 | struct drm_info_node *node = m->private; | |
2990 | struct drm_device *dev = node->minor->dev; | |
2991 | struct intel_plane *intel_plane; | |
2992 | ||
2993 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
2994 | struct drm_plane_state *state; | |
2995 | struct drm_plane *plane = &intel_plane->base; | |
2996 | ||
2997 | if (!plane->state) { | |
2998 | seq_puts(m, "plane->state is NULL!\n"); | |
2999 | continue; | |
3000 | } | |
3001 | ||
3002 | state = plane->state; | |
3003 | ||
3004 | seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", | |
3005 | plane->base.id, | |
3006 | plane_type(intel_plane->base.type), | |
3007 | state->crtc_x, state->crtc_y, | |
3008 | state->crtc_w, state->crtc_h, | |
3009 | (state->src_x >> 16), | |
3010 | ((state->src_x & 0xffff) * 15625) >> 10, | |
3011 | (state->src_y >> 16), | |
3012 | ((state->src_y & 0xffff) * 15625) >> 10, | |
3013 | (state->src_w >> 16), | |
3014 | ((state->src_w & 0xffff) * 15625) >> 10, | |
3015 | (state->src_h >> 16), | |
3016 | ((state->src_h & 0xffff) * 15625) >> 10, | |
3017 | state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A", | |
3018 | plane_rotation(state->rotation)); | |
3019 | } | |
3020 | } | |
3021 | ||
3022 | static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
3023 | { | |
3024 | struct intel_crtc_state *pipe_config; | |
3025 | int num_scalers = intel_crtc->num_scalers; | |
3026 | int i; | |
3027 | ||
3028 | pipe_config = to_intel_crtc_state(intel_crtc->base.state); | |
3029 | ||
3030 | /* Not all platformas have a scaler */ | |
3031 | if (num_scalers) { | |
3032 | seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", | |
3033 | num_scalers, | |
3034 | pipe_config->scaler_state.scaler_users, | |
3035 | pipe_config->scaler_state.scaler_id); | |
3036 | ||
3037 | for (i = 0; i < SKL_NUM_SCALERS; i++) { | |
3038 | struct intel_scaler *sc = | |
3039 | &pipe_config->scaler_state.scalers[i]; | |
3040 | ||
3041 | seq_printf(m, ", scalers[%d]: use=%s, mode=%x", | |
3042 | i, yesno(sc->in_use), sc->mode); | |
3043 | } | |
3044 | seq_puts(m, "\n"); | |
3045 | } else { | |
3046 | seq_puts(m, "\tNo scalers available on this platform\n"); | |
3047 | } | |
3048 | } | |
3049 | ||
53f5e3ca JB |
3050 | static int i915_display_info(struct seq_file *m, void *unused) |
3051 | { | |
9f25d007 | 3052 | struct drm_info_node *node = m->private; |
53f5e3ca | 3053 | struct drm_device *dev = node->minor->dev; |
b0e5ddf3 | 3054 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 3055 | struct intel_crtc *crtc; |
53f5e3ca JB |
3056 | struct drm_connector *connector; |
3057 | ||
b0e5ddf3 | 3058 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
3059 | drm_modeset_lock_all(dev); |
3060 | seq_printf(m, "CRTC info\n"); | |
3061 | seq_printf(m, "---------\n"); | |
d3fcc808 | 3062 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 3063 | bool active; |
f77076c9 | 3064 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 3065 | int x, y; |
53f5e3ca | 3066 | |
f77076c9 ML |
3067 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3068 | ||
3abc4e09 | 3069 | seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", |
065f2ec2 | 3070 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 | 3071 | yesno(pipe_config->base.active), |
3abc4e09 RF |
3072 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
3073 | yesno(pipe_config->dither), pipe_config->pipe_bpp); | |
3074 | ||
f77076c9 | 3075 | if (pipe_config->base.active) { |
065f2ec2 CW |
3076 | intel_crtc_info(m, crtc); |
3077 | ||
a23dc658 | 3078 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 3079 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 3080 | yesno(crtc->cursor_base), |
3dd512fb MR |
3081 | x, y, crtc->base.cursor->state->crtc_w, |
3082 | crtc->base.cursor->state->crtc_h, | |
57127efa | 3083 | crtc->cursor_addr, yesno(active)); |
3abc4e09 RF |
3084 | intel_scaler_info(m, crtc); |
3085 | intel_plane_info(m, crtc); | |
a23dc658 | 3086 | } |
cace841c DV |
3087 | |
3088 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
3089 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
3090 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
3091 | } |
3092 | ||
3093 | seq_printf(m, "\n"); | |
3094 | seq_printf(m, "Connector info\n"); | |
3095 | seq_printf(m, "--------------\n"); | |
3096 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3097 | intel_connector_info(m, connector); | |
3098 | } | |
3099 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 3100 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
3101 | |
3102 | return 0; | |
3103 | } | |
3104 | ||
e04934cf BW |
3105 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
3106 | { | |
3107 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3108 | struct drm_device *dev = node->minor->dev; | |
3109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3110 | struct intel_engine_cs *ring; | |
3111 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
3112 | int i, j, ret; | |
3113 | ||
3114 | if (!i915_semaphore_is_enabled(dev)) { | |
3115 | seq_puts(m, "Semaphores are disabled\n"); | |
3116 | return 0; | |
3117 | } | |
3118 | ||
3119 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
3120 | if (ret) | |
3121 | return ret; | |
03872064 | 3122 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
3123 | |
3124 | if (IS_BROADWELL(dev)) { | |
3125 | struct page *page; | |
3126 | uint64_t *seqno; | |
3127 | ||
3128 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
3129 | ||
3130 | seqno = (uint64_t *)kmap_atomic(page); | |
3131 | for_each_ring(ring, dev_priv, i) { | |
3132 | uint64_t offset; | |
3133 | ||
3134 | seq_printf(m, "%s\n", ring->name); | |
3135 | ||
3136 | seq_puts(m, " Last signal:"); | |
3137 | for (j = 0; j < num_rings; j++) { | |
3138 | offset = i * I915_NUM_RINGS + j; | |
3139 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
3140 | seqno[offset], offset * 8); | |
3141 | } | |
3142 | seq_putc(m, '\n'); | |
3143 | ||
3144 | seq_puts(m, " Last wait: "); | |
3145 | for (j = 0; j < num_rings; j++) { | |
3146 | offset = i + (j * I915_NUM_RINGS); | |
3147 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
3148 | seqno[offset], offset * 8); | |
3149 | } | |
3150 | seq_putc(m, '\n'); | |
3151 | ||
3152 | } | |
3153 | kunmap_atomic(seqno); | |
3154 | } else { | |
3155 | seq_puts(m, " Last signal:"); | |
3156 | for_each_ring(ring, dev_priv, i) | |
3157 | for (j = 0; j < num_rings; j++) | |
3158 | seq_printf(m, "0x%08x\n", | |
3159 | I915_READ(ring->semaphore.mbox.signal[j])); | |
3160 | seq_putc(m, '\n'); | |
3161 | } | |
3162 | ||
3163 | seq_puts(m, "\nSync seqno:\n"); | |
3164 | for_each_ring(ring, dev_priv, i) { | |
3165 | for (j = 0; j < num_rings; j++) { | |
3166 | seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); | |
3167 | } | |
3168 | seq_putc(m, '\n'); | |
3169 | } | |
3170 | seq_putc(m, '\n'); | |
3171 | ||
03872064 | 3172 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
3173 | mutex_unlock(&dev->struct_mutex); |
3174 | return 0; | |
3175 | } | |
3176 | ||
728e29d7 DV |
3177 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
3178 | { | |
3179 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3180 | struct drm_device *dev = node->minor->dev; | |
3181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3182 | int i; | |
3183 | ||
3184 | drm_modeset_lock_all(dev); | |
3185 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3186 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
3187 | ||
3188 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
1e6f2ddc | 3189 | seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n", |
3e369b76 | 3190 | pll->config.crtc_mask, pll->active, yesno(pll->on)); |
728e29d7 | 3191 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
3192 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
3193 | seq_printf(m, " dpll_md: 0x%08x\n", | |
3194 | pll->config.hw_state.dpll_md); | |
3195 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
3196 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
3197 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
3198 | } |
3199 | drm_modeset_unlock_all(dev); | |
3200 | ||
3201 | return 0; | |
3202 | } | |
3203 | ||
1ed1ef9d | 3204 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
3205 | { |
3206 | int i; | |
3207 | int ret; | |
3208 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3209 | struct drm_device *dev = node->minor->dev; | |
3210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3211 | ||
888b5995 AS |
3212 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
3213 | if (ret) | |
3214 | return ret; | |
3215 | ||
3216 | intel_runtime_pm_get(dev_priv); | |
3217 | ||
7225342a MK |
3218 | seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count); |
3219 | for (i = 0; i < dev_priv->workarounds.count; ++i) { | |
f0f59a00 VS |
3220 | i915_reg_t addr; |
3221 | u32 mask, value, read; | |
2fa60f6d | 3222 | bool ok; |
888b5995 | 3223 | |
7225342a MK |
3224 | addr = dev_priv->workarounds.reg[i].addr; |
3225 | mask = dev_priv->workarounds.reg[i].mask; | |
2fa60f6d MK |
3226 | value = dev_priv->workarounds.reg[i].value; |
3227 | read = I915_READ(addr); | |
3228 | ok = (value & mask) == (read & mask); | |
3229 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
f0f59a00 | 3230 | i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); |
888b5995 AS |
3231 | } |
3232 | ||
3233 | intel_runtime_pm_put(dev_priv); | |
3234 | mutex_unlock(&dev->struct_mutex); | |
3235 | ||
3236 | return 0; | |
3237 | } | |
3238 | ||
c5511e44 DL |
3239 | static int i915_ddb_info(struct seq_file *m, void *unused) |
3240 | { | |
3241 | struct drm_info_node *node = m->private; | |
3242 | struct drm_device *dev = node->minor->dev; | |
3243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3244 | struct skl_ddb_allocation *ddb; | |
3245 | struct skl_ddb_entry *entry; | |
3246 | enum pipe pipe; | |
3247 | int plane; | |
3248 | ||
2fcffe19 DL |
3249 | if (INTEL_INFO(dev)->gen < 9) |
3250 | return 0; | |
3251 | ||
c5511e44 DL |
3252 | drm_modeset_lock_all(dev); |
3253 | ||
3254 | ddb = &dev_priv->wm.skl_hw.ddb; | |
3255 | ||
3256 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
3257 | ||
3258 | for_each_pipe(dev_priv, pipe) { | |
3259 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
3260 | ||
dd740780 | 3261 | for_each_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
3262 | entry = &ddb->plane[pipe][plane]; |
3263 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
3264 | entry->start, entry->end, | |
3265 | skl_ddb_entry_size(entry)); | |
3266 | } | |
3267 | ||
4969d33e | 3268 | entry = &ddb->plane[pipe][PLANE_CURSOR]; |
c5511e44 DL |
3269 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, |
3270 | entry->end, skl_ddb_entry_size(entry)); | |
3271 | } | |
3272 | ||
3273 | drm_modeset_unlock_all(dev); | |
3274 | ||
3275 | return 0; | |
3276 | } | |
3277 | ||
a54746e3 VK |
3278 | static void drrs_status_per_crtc(struct seq_file *m, |
3279 | struct drm_device *dev, struct intel_crtc *intel_crtc) | |
3280 | { | |
3281 | struct intel_encoder *intel_encoder; | |
3282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3283 | struct i915_drrs *drrs = &dev_priv->drrs; | |
3284 | int vrefresh = 0; | |
3285 | ||
3286 | for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { | |
3287 | /* Encoder connected on this CRTC */ | |
3288 | switch (intel_encoder->type) { | |
3289 | case INTEL_OUTPUT_EDP: | |
3290 | seq_puts(m, "eDP:\n"); | |
3291 | break; | |
3292 | case INTEL_OUTPUT_DSI: | |
3293 | seq_puts(m, "DSI:\n"); | |
3294 | break; | |
3295 | case INTEL_OUTPUT_HDMI: | |
3296 | seq_puts(m, "HDMI:\n"); | |
3297 | break; | |
3298 | case INTEL_OUTPUT_DISPLAYPORT: | |
3299 | seq_puts(m, "DP:\n"); | |
3300 | break; | |
3301 | default: | |
3302 | seq_printf(m, "Other encoder (id=%d).\n", | |
3303 | intel_encoder->type); | |
3304 | return; | |
3305 | } | |
3306 | } | |
3307 | ||
3308 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3309 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3310 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3311 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3312 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3313 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3314 | else | |
3315 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3316 | ||
3317 | seq_puts(m, "\n\n"); | |
3318 | ||
f77076c9 | 3319 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3320 | struct intel_panel *panel; |
3321 | ||
3322 | mutex_lock(&drrs->mutex); | |
3323 | /* DRRS Supported */ | |
3324 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3325 | ||
3326 | /* disable_drrs() will make drrs->dp NULL */ | |
3327 | if (!drrs->dp) { | |
3328 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3329 | mutex_unlock(&drrs->mutex); | |
3330 | return; | |
3331 | } | |
3332 | ||
3333 | panel = &drrs->dp->attached_connector->panel; | |
3334 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3335 | drrs->busy_frontbuffer_bits); | |
3336 | ||
3337 | seq_puts(m, "\n\t\t"); | |
3338 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3339 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3340 | vrefresh = panel->fixed_mode->vrefresh; | |
3341 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3342 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3343 | vrefresh = panel->downclock_mode->vrefresh; | |
3344 | } else { | |
3345 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3346 | drrs->refresh_rate_type); | |
3347 | mutex_unlock(&drrs->mutex); | |
3348 | return; | |
3349 | } | |
3350 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3351 | ||
3352 | seq_puts(m, "\n\t\t"); | |
3353 | mutex_unlock(&drrs->mutex); | |
3354 | } else { | |
3355 | /* DRRS not supported. Print the VBT parameter*/ | |
3356 | seq_puts(m, "\tDRRS Supported : No"); | |
3357 | } | |
3358 | seq_puts(m, "\n"); | |
3359 | } | |
3360 | ||
3361 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3362 | { | |
3363 | struct drm_info_node *node = m->private; | |
3364 | struct drm_device *dev = node->minor->dev; | |
3365 | struct intel_crtc *intel_crtc; | |
3366 | int active_crtc_cnt = 0; | |
3367 | ||
3368 | for_each_intel_crtc(dev, intel_crtc) { | |
3369 | drm_modeset_lock(&intel_crtc->base.mutex, NULL); | |
3370 | ||
f77076c9 | 3371 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3372 | active_crtc_cnt++; |
3373 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3374 | ||
3375 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3376 | } | |
3377 | ||
3378 | drm_modeset_unlock(&intel_crtc->base.mutex); | |
3379 | } | |
3380 | ||
3381 | if (!active_crtc_cnt) | |
3382 | seq_puts(m, "No active crtc found\n"); | |
3383 | ||
3384 | return 0; | |
3385 | } | |
3386 | ||
07144428 DL |
3387 | struct pipe_crc_info { |
3388 | const char *name; | |
3389 | struct drm_device *dev; | |
3390 | enum pipe pipe; | |
3391 | }; | |
3392 | ||
11bed958 DA |
3393 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3394 | { | |
3395 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3396 | struct drm_device *dev = node->minor->dev; | |
3397 | struct drm_encoder *encoder; | |
3398 | struct intel_encoder *intel_encoder; | |
3399 | struct intel_digital_port *intel_dig_port; | |
3400 | drm_modeset_lock_all(dev); | |
3401 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
3402 | intel_encoder = to_intel_encoder(encoder); | |
3403 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) | |
3404 | continue; | |
3405 | intel_dig_port = enc_to_dig_port(encoder); | |
3406 | if (!intel_dig_port->dp.can_mst) | |
3407 | continue; | |
3408 | ||
3409 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); | |
3410 | } | |
3411 | drm_modeset_unlock_all(dev); | |
3412 | return 0; | |
3413 | } | |
3414 | ||
07144428 DL |
3415 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3416 | { | |
be5c7a90 DL |
3417 | struct pipe_crc_info *info = inode->i_private; |
3418 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3419 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3420 | ||
7eb1c496 DV |
3421 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
3422 | return -ENODEV; | |
3423 | ||
d538bbdf DL |
3424 | spin_lock_irq(&pipe_crc->lock); |
3425 | ||
3426 | if (pipe_crc->opened) { | |
3427 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3428 | return -EBUSY; /* already open */ |
3429 | } | |
3430 | ||
d538bbdf | 3431 | pipe_crc->opened = true; |
07144428 DL |
3432 | filep->private_data = inode->i_private; |
3433 | ||
d538bbdf DL |
3434 | spin_unlock_irq(&pipe_crc->lock); |
3435 | ||
07144428 DL |
3436 | return 0; |
3437 | } | |
3438 | ||
3439 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3440 | { | |
be5c7a90 DL |
3441 | struct pipe_crc_info *info = inode->i_private; |
3442 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3443 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3444 | ||
d538bbdf DL |
3445 | spin_lock_irq(&pipe_crc->lock); |
3446 | pipe_crc->opened = false; | |
3447 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3448 | |
07144428 DL |
3449 | return 0; |
3450 | } | |
3451 | ||
3452 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3453 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3454 | /* account for \'0' */ | |
3455 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3456 | ||
3457 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3458 | { |
d538bbdf DL |
3459 | assert_spin_locked(&pipe_crc->lock); |
3460 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3461 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3462 | } |
3463 | ||
3464 | static ssize_t | |
3465 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3466 | loff_t *pos) | |
3467 | { | |
3468 | struct pipe_crc_info *info = filep->private_data; | |
3469 | struct drm_device *dev = info->dev; | |
3470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3471 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3472 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3473 | int n_entries; |
07144428 DL |
3474 | ssize_t bytes_read; |
3475 | ||
3476 | /* | |
3477 | * Don't allow user space to provide buffers not big enough to hold | |
3478 | * a line of data. | |
3479 | */ | |
3480 | if (count < PIPE_CRC_LINE_LEN) | |
3481 | return -EINVAL; | |
3482 | ||
3483 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3484 | return 0; |
07144428 DL |
3485 | |
3486 | /* nothing to read */ | |
d538bbdf | 3487 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3488 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3489 | int ret; |
3490 | ||
3491 | if (filep->f_flags & O_NONBLOCK) { | |
3492 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3493 | return -EAGAIN; |
d538bbdf | 3494 | } |
07144428 | 3495 | |
d538bbdf DL |
3496 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3497 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3498 | if (ret) { | |
3499 | spin_unlock_irq(&pipe_crc->lock); | |
3500 | return ret; | |
3501 | } | |
8bf1e9f1 SH |
3502 | } |
3503 | ||
07144428 | 3504 | /* We now have one or more entries to read */ |
9ad6d99f | 3505 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3506 | |
07144428 | 3507 | bytes_read = 0; |
9ad6d99f VS |
3508 | while (n_entries > 0) { |
3509 | struct intel_pipe_crc_entry *entry = | |
3510 | &pipe_crc->entries[pipe_crc->tail]; | |
07144428 | 3511 | int ret; |
8bf1e9f1 | 3512 | |
9ad6d99f VS |
3513 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3514 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3515 | break; | |
3516 | ||
3517 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3518 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3519 | ||
07144428 DL |
3520 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3521 | "%8u %8x %8x %8x %8x %8x\n", | |
3522 | entry->frame, entry->crc[0], | |
3523 | entry->crc[1], entry->crc[2], | |
3524 | entry->crc[3], entry->crc[4]); | |
3525 | ||
9ad6d99f VS |
3526 | spin_unlock_irq(&pipe_crc->lock); |
3527 | ||
3528 | ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); | |
07144428 DL |
3529 | if (ret == PIPE_CRC_LINE_LEN) |
3530 | return -EFAULT; | |
b2c88f5b | 3531 | |
9ad6d99f VS |
3532 | user_buf += PIPE_CRC_LINE_LEN; |
3533 | n_entries--; | |
3534 | ||
3535 | spin_lock_irq(&pipe_crc->lock); | |
3536 | } | |
8bf1e9f1 | 3537 | |
d538bbdf DL |
3538 | spin_unlock_irq(&pipe_crc->lock); |
3539 | ||
07144428 DL |
3540 | return bytes_read; |
3541 | } | |
3542 | ||
3543 | static const struct file_operations i915_pipe_crc_fops = { | |
3544 | .owner = THIS_MODULE, | |
3545 | .open = i915_pipe_crc_open, | |
3546 | .read = i915_pipe_crc_read, | |
3547 | .release = i915_pipe_crc_release, | |
3548 | }; | |
3549 | ||
3550 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3551 | { | |
3552 | .name = "i915_pipe_A_crc", | |
3553 | .pipe = PIPE_A, | |
3554 | }, | |
3555 | { | |
3556 | .name = "i915_pipe_B_crc", | |
3557 | .pipe = PIPE_B, | |
3558 | }, | |
3559 | { | |
3560 | .name = "i915_pipe_C_crc", | |
3561 | .pipe = PIPE_C, | |
3562 | }, | |
3563 | }; | |
3564 | ||
3565 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3566 | enum pipe pipe) | |
3567 | { | |
3568 | struct drm_device *dev = minor->dev; | |
3569 | struct dentry *ent; | |
3570 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3571 | ||
3572 | info->dev = dev; | |
3573 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
3574 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3575 | if (!ent) |
3576 | return -ENOMEM; | |
07144428 DL |
3577 | |
3578 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3579 | } |
3580 | ||
e8dfcf78 | 3581 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3582 | "none", |
3583 | "plane1", | |
3584 | "plane2", | |
3585 | "pf", | |
5b3a856b | 3586 | "pipe", |
3d099a05 DV |
3587 | "TV", |
3588 | "DP-B", | |
3589 | "DP-C", | |
3590 | "DP-D", | |
46a19188 | 3591 | "auto", |
926321d5 DV |
3592 | }; |
3593 | ||
3594 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3595 | { | |
3596 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3597 | return pipe_crc_sources[source]; | |
3598 | } | |
3599 | ||
bd9db02f | 3600 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
3601 | { |
3602 | struct drm_device *dev = m->private; | |
3603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3604 | int i; | |
3605 | ||
3606 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3607 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3608 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3609 | ||
3610 | return 0; | |
3611 | } | |
3612 | ||
bd9db02f | 3613 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
3614 | { |
3615 | struct drm_device *dev = inode->i_private; | |
3616 | ||
bd9db02f | 3617 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
3618 | } |
3619 | ||
46a19188 | 3620 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3621 | uint32_t *val) |
3622 | { | |
46a19188 DV |
3623 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3624 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3625 | ||
3626 | switch (*source) { | |
52f843f6 DV |
3627 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3628 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3629 | break; | |
3630 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3631 | *val = 0; | |
3632 | break; | |
3633 | default: | |
3634 | return -EINVAL; | |
3635 | } | |
3636 | ||
3637 | return 0; | |
3638 | } | |
3639 | ||
46a19188 DV |
3640 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
3641 | enum intel_pipe_crc_source *source) | |
3642 | { | |
3643 | struct intel_encoder *encoder; | |
3644 | struct intel_crtc *crtc; | |
26756809 | 3645 | struct intel_digital_port *dig_port; |
46a19188 DV |
3646 | int ret = 0; |
3647 | ||
3648 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3649 | ||
6e9f798d | 3650 | drm_modeset_lock_all(dev); |
b2784e15 | 3651 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3652 | if (!encoder->base.crtc) |
3653 | continue; | |
3654 | ||
3655 | crtc = to_intel_crtc(encoder->base.crtc); | |
3656 | ||
3657 | if (crtc->pipe != pipe) | |
3658 | continue; | |
3659 | ||
3660 | switch (encoder->type) { | |
3661 | case INTEL_OUTPUT_TVOUT: | |
3662 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3663 | break; | |
3664 | case INTEL_OUTPUT_DISPLAYPORT: | |
3665 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
3666 | dig_port = enc_to_dig_port(&encoder->base); |
3667 | switch (dig_port->port) { | |
3668 | case PORT_B: | |
3669 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3670 | break; | |
3671 | case PORT_C: | |
3672 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3673 | break; | |
3674 | case PORT_D: | |
3675 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3676 | break; | |
3677 | default: | |
3678 | WARN(1, "nonexisting DP port %c\n", | |
3679 | port_name(dig_port->port)); | |
3680 | break; | |
3681 | } | |
46a19188 | 3682 | break; |
6847d71b PZ |
3683 | default: |
3684 | break; | |
46a19188 DV |
3685 | } |
3686 | } | |
6e9f798d | 3687 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3688 | |
3689 | return ret; | |
3690 | } | |
3691 | ||
3692 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
3693 | enum pipe pipe, | |
3694 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3695 | uint32_t *val) |
3696 | { | |
8d2f24ca DV |
3697 | struct drm_i915_private *dev_priv = dev->dev_private; |
3698 | bool need_stable_symbols = false; | |
3699 | ||
46a19188 DV |
3700 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3701 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3702 | if (ret) | |
3703 | return ret; | |
3704 | } | |
3705 | ||
3706 | switch (*source) { | |
7ac0129b DV |
3707 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3708 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3709 | break; | |
3710 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3711 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3712 | need_stable_symbols = true; |
7ac0129b DV |
3713 | break; |
3714 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3715 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3716 | need_stable_symbols = true; |
7ac0129b | 3717 | break; |
2be57922 VS |
3718 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
3719 | if (!IS_CHERRYVIEW(dev)) | |
3720 | return -EINVAL; | |
3721 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3722 | need_stable_symbols = true; | |
3723 | break; | |
7ac0129b DV |
3724 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3725 | *val = 0; | |
3726 | break; | |
3727 | default: | |
3728 | return -EINVAL; | |
3729 | } | |
3730 | ||
8d2f24ca DV |
3731 | /* |
3732 | * When the pipe CRC tap point is after the transcoders we need | |
3733 | * to tweak symbol-level features to produce a deterministic series of | |
3734 | * symbols for a given frame. We need to reset those features only once | |
3735 | * a frame (instead of every nth symbol): | |
3736 | * - DC-balance: used to ensure a better clock recovery from the data | |
3737 | * link (SDVO) | |
3738 | * - DisplayPort scrambling: used for EMI reduction | |
3739 | */ | |
3740 | if (need_stable_symbols) { | |
3741 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3742 | ||
8d2f24ca | 3743 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3744 | switch (pipe) { |
3745 | case PIPE_A: | |
8d2f24ca | 3746 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3747 | break; |
3748 | case PIPE_B: | |
8d2f24ca | 3749 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3750 | break; |
3751 | case PIPE_C: | |
3752 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3753 | break; | |
3754 | default: | |
3755 | return -EINVAL; | |
3756 | } | |
8d2f24ca DV |
3757 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3758 | } | |
3759 | ||
7ac0129b DV |
3760 | return 0; |
3761 | } | |
3762 | ||
4b79ebf7 | 3763 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
3764 | enum pipe pipe, |
3765 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3766 | uint32_t *val) |
3767 | { | |
84093603 DV |
3768 | struct drm_i915_private *dev_priv = dev->dev_private; |
3769 | bool need_stable_symbols = false; | |
3770 | ||
46a19188 DV |
3771 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3772 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3773 | if (ret) | |
3774 | return ret; | |
3775 | } | |
3776 | ||
3777 | switch (*source) { | |
4b79ebf7 DV |
3778 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3779 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3780 | break; | |
3781 | case INTEL_PIPE_CRC_SOURCE_TV: | |
3782 | if (!SUPPORTS_TV(dev)) | |
3783 | return -EINVAL; | |
3784 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3785 | break; | |
3786 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3787 | if (!IS_G4X(dev)) | |
3788 | return -EINVAL; | |
3789 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3790 | need_stable_symbols = true; |
4b79ebf7 DV |
3791 | break; |
3792 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3793 | if (!IS_G4X(dev)) | |
3794 | return -EINVAL; | |
3795 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3796 | need_stable_symbols = true; |
4b79ebf7 DV |
3797 | break; |
3798 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
3799 | if (!IS_G4X(dev)) | |
3800 | return -EINVAL; | |
3801 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3802 | need_stable_symbols = true; |
4b79ebf7 DV |
3803 | break; |
3804 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3805 | *val = 0; | |
3806 | break; | |
3807 | default: | |
3808 | return -EINVAL; | |
3809 | } | |
3810 | ||
84093603 DV |
3811 | /* |
3812 | * When the pipe CRC tap point is after the transcoders we need | |
3813 | * to tweak symbol-level features to produce a deterministic series of | |
3814 | * symbols for a given frame. We need to reset those features only once | |
3815 | * a frame (instead of every nth symbol): | |
3816 | * - DC-balance: used to ensure a better clock recovery from the data | |
3817 | * link (SDVO) | |
3818 | * - DisplayPort scrambling: used for EMI reduction | |
3819 | */ | |
3820 | if (need_stable_symbols) { | |
3821 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3822 | ||
3823 | WARN_ON(!IS_G4X(dev)); | |
3824 | ||
3825 | I915_WRITE(PORT_DFT_I9XX, | |
3826 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3827 | ||
3828 | if (pipe == PIPE_A) | |
3829 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3830 | else | |
3831 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3832 | ||
3833 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3834 | } | |
3835 | ||
4b79ebf7 DV |
3836 | return 0; |
3837 | } | |
3838 | ||
8d2f24ca DV |
3839 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
3840 | enum pipe pipe) | |
3841 | { | |
3842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3843 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3844 | ||
eb736679 VS |
3845 | switch (pipe) { |
3846 | case PIPE_A: | |
8d2f24ca | 3847 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3848 | break; |
3849 | case PIPE_B: | |
8d2f24ca | 3850 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3851 | break; |
3852 | case PIPE_C: | |
3853 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3854 | break; | |
3855 | default: | |
3856 | return; | |
3857 | } | |
8d2f24ca DV |
3858 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3859 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3860 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3861 | ||
3862 | } | |
3863 | ||
84093603 DV |
3864 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
3865 | enum pipe pipe) | |
3866 | { | |
3867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3868 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3869 | ||
3870 | if (pipe == PIPE_A) | |
3871 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3872 | else | |
3873 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3874 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3875 | ||
3876 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3877 | I915_WRITE(PORT_DFT_I9XX, | |
3878 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3879 | } | |
3880 | } | |
3881 | ||
46a19188 | 3882 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3883 | uint32_t *val) |
3884 | { | |
46a19188 DV |
3885 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3886 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3887 | ||
3888 | switch (*source) { | |
5b3a856b DV |
3889 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3890 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
3891 | break; | |
3892 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3893 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
3894 | break; | |
5b3a856b DV |
3895 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3896 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
3897 | break; | |
3d099a05 | 3898 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3899 | *val = 0; |
3900 | break; | |
3d099a05 DV |
3901 | default: |
3902 | return -EINVAL; | |
5b3a856b DV |
3903 | } |
3904 | ||
3905 | return 0; | |
3906 | } | |
3907 | ||
c4e2d043 | 3908 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable) |
fabf6e51 DV |
3909 | { |
3910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3911 | struct intel_crtc *crtc = | |
3912 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 3913 | struct intel_crtc_state *pipe_config; |
c4e2d043 ML |
3914 | struct drm_atomic_state *state; |
3915 | int ret = 0; | |
fabf6e51 DV |
3916 | |
3917 | drm_modeset_lock_all(dev); | |
c4e2d043 ML |
3918 | state = drm_atomic_state_alloc(dev); |
3919 | if (!state) { | |
3920 | ret = -ENOMEM; | |
3921 | goto out; | |
fabf6e51 | 3922 | } |
fabf6e51 | 3923 | |
c4e2d043 ML |
3924 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); |
3925 | pipe_config = intel_atomic_get_crtc_state(state, crtc); | |
3926 | if (IS_ERR(pipe_config)) { | |
3927 | ret = PTR_ERR(pipe_config); | |
3928 | goto out; | |
3929 | } | |
fabf6e51 | 3930 | |
c4e2d043 ML |
3931 | pipe_config->pch_pfit.force_thru = enable; |
3932 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
3933 | pipe_config->pch_pfit.enabled != enable) | |
3934 | pipe_config->base.connectors_changed = true; | |
1b509259 | 3935 | |
c4e2d043 ML |
3936 | ret = drm_atomic_commit(state); |
3937 | out: | |
fabf6e51 | 3938 | drm_modeset_unlock_all(dev); |
c4e2d043 ML |
3939 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
3940 | if (ret) | |
3941 | drm_atomic_state_free(state); | |
fabf6e51 DV |
3942 | } |
3943 | ||
3944 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
3945 | enum pipe pipe, | |
3946 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
3947 | uint32_t *val) |
3948 | { | |
46a19188 DV |
3949 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3950 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
3951 | ||
3952 | switch (*source) { | |
5b3a856b DV |
3953 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3954 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
3955 | break; | |
3956 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3957 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
3958 | break; | |
3959 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 | 3960 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 3961 | hsw_trans_edp_pipe_A_crc_wa(dev, true); |
fabf6e51 | 3962 | |
5b3a856b DV |
3963 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
3964 | break; | |
3d099a05 | 3965 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3966 | *val = 0; |
3967 | break; | |
3d099a05 DV |
3968 | default: |
3969 | return -EINVAL; | |
5b3a856b DV |
3970 | } |
3971 | ||
3972 | return 0; | |
3973 | } | |
3974 | ||
926321d5 DV |
3975 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
3976 | enum intel_pipe_crc_source source) | |
3977 | { | |
3978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 3979 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
8c740dce PZ |
3980 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
3981 | pipe)); | |
432f3342 | 3982 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 3983 | int ret; |
926321d5 | 3984 | |
cc3da175 DL |
3985 | if (pipe_crc->source == source) |
3986 | return 0; | |
3987 | ||
ae676fcd DL |
3988 | /* forbid changing the source without going back to 'none' */ |
3989 | if (pipe_crc->source && source) | |
3990 | return -EINVAL; | |
3991 | ||
9d8b0588 DV |
3992 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) { |
3993 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); | |
3994 | return -EIO; | |
3995 | } | |
3996 | ||
52f843f6 | 3997 | if (IS_GEN2(dev)) |
46a19188 | 3998 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 3999 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 4000 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
666a4537 | 4001 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
fabf6e51 | 4002 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 4003 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 4004 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 4005 | else |
fabf6e51 | 4006 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
4007 | |
4008 | if (ret != 0) | |
4009 | return ret; | |
4010 | ||
4b584369 DL |
4011 | /* none -> real source transition */ |
4012 | if (source) { | |
4252fbc3 VS |
4013 | struct intel_pipe_crc_entry *entries; |
4014 | ||
7cd6ccff DL |
4015 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
4016 | pipe_name(pipe), pipe_crc_source_name(source)); | |
4017 | ||
3cf54b34 VS |
4018 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
4019 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 VS |
4020 | GFP_KERNEL); |
4021 | if (!entries) | |
e5f75aca DL |
4022 | return -ENOMEM; |
4023 | ||
8c740dce PZ |
4024 | /* |
4025 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
4026 | * enabled and disabled dynamically based on package C states, | |
4027 | * user space can't make reliable use of the CRCs, so let's just | |
4028 | * completely disable it. | |
4029 | */ | |
4030 | hsw_disable_ips(crtc); | |
4031 | ||
d538bbdf | 4032 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 4033 | kfree(pipe_crc->entries); |
4252fbc3 | 4034 | pipe_crc->entries = entries; |
d538bbdf DL |
4035 | pipe_crc->head = 0; |
4036 | pipe_crc->tail = 0; | |
4037 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
4038 | } |
4039 | ||
cc3da175 | 4040 | pipe_crc->source = source; |
926321d5 | 4041 | |
926321d5 DV |
4042 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
4043 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
4044 | ||
e5f75aca DL |
4045 | /* real source -> none transition */ |
4046 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 4047 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
4048 | struct intel_crtc *crtc = |
4049 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 4050 | |
7cd6ccff DL |
4051 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
4052 | pipe_name(pipe)); | |
4053 | ||
a33d7105 | 4054 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 4055 | if (crtc->base.state->active) |
a33d7105 DV |
4056 | intel_wait_for_vblank(dev, pipe); |
4057 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 4058 | |
d538bbdf DL |
4059 | spin_lock_irq(&pipe_crc->lock); |
4060 | entries = pipe_crc->entries; | |
e5f75aca | 4061 | pipe_crc->entries = NULL; |
9ad6d99f VS |
4062 | pipe_crc->head = 0; |
4063 | pipe_crc->tail = 0; | |
d538bbdf DL |
4064 | spin_unlock_irq(&pipe_crc->lock); |
4065 | ||
4066 | kfree(entries); | |
84093603 DV |
4067 | |
4068 | if (IS_G4X(dev)) | |
4069 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
666a4537 | 4070 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
8d2f24ca | 4071 | vlv_undo_pipe_scramble_reset(dev, pipe); |
fabf6e51 | 4072 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
c4e2d043 | 4073 | hsw_trans_edp_pipe_A_crc_wa(dev, false); |
8c740dce PZ |
4074 | |
4075 | hsw_enable_ips(crtc); | |
e5f75aca DL |
4076 | } |
4077 | ||
926321d5 DV |
4078 | return 0; |
4079 | } | |
4080 | ||
4081 | /* | |
4082 | * Parse pipe CRC command strings: | |
b94dec87 DL |
4083 | * command: wsp* object wsp+ name wsp+ source wsp* |
4084 | * object: 'pipe' | |
4085 | * name: (A | B | C) | |
926321d5 DV |
4086 | * source: (none | plane1 | plane2 | pf) |
4087 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
4088 | * | |
4089 | * eg.: | |
b94dec87 DL |
4090 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
4091 | * "pipe A none" -> Stop CRC | |
926321d5 | 4092 | */ |
bd9db02f | 4093 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
4094 | { |
4095 | int n_words = 0; | |
4096 | ||
4097 | while (*buf) { | |
4098 | char *end; | |
4099 | ||
4100 | /* skip leading white space */ | |
4101 | buf = skip_spaces(buf); | |
4102 | if (!*buf) | |
4103 | break; /* end of buffer */ | |
4104 | ||
4105 | /* find end of word */ | |
4106 | for (end = buf; *end && !isspace(*end); end++) | |
4107 | ; | |
4108 | ||
4109 | if (n_words == max_words) { | |
4110 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
4111 | max_words); | |
4112 | return -EINVAL; /* ran out of words[] before bytes */ | |
4113 | } | |
4114 | ||
4115 | if (*end) | |
4116 | *end++ = '\0'; | |
4117 | words[n_words++] = buf; | |
4118 | buf = end; | |
4119 | } | |
4120 | ||
4121 | return n_words; | |
4122 | } | |
4123 | ||
b94dec87 DL |
4124 | enum intel_pipe_crc_object { |
4125 | PIPE_CRC_OBJECT_PIPE, | |
4126 | }; | |
4127 | ||
e8dfcf78 | 4128 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
4129 | "pipe", |
4130 | }; | |
4131 | ||
4132 | static int | |
bd9db02f | 4133 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
4134 | { |
4135 | int i; | |
4136 | ||
4137 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
4138 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 4139 | *o = i; |
b94dec87 DL |
4140 | return 0; |
4141 | } | |
4142 | ||
4143 | return -EINVAL; | |
4144 | } | |
4145 | ||
bd9db02f | 4146 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
4147 | { |
4148 | const char name = buf[0]; | |
4149 | ||
4150 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
4151 | return -EINVAL; | |
4152 | ||
4153 | *pipe = name - 'A'; | |
4154 | ||
4155 | return 0; | |
4156 | } | |
4157 | ||
4158 | static int | |
bd9db02f | 4159 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
4160 | { |
4161 | int i; | |
4162 | ||
4163 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
4164 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 4165 | *s = i; |
926321d5 DV |
4166 | return 0; |
4167 | } | |
4168 | ||
4169 | return -EINVAL; | |
4170 | } | |
4171 | ||
bd9db02f | 4172 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 4173 | { |
b94dec87 | 4174 | #define N_WORDS 3 |
926321d5 | 4175 | int n_words; |
b94dec87 | 4176 | char *words[N_WORDS]; |
926321d5 | 4177 | enum pipe pipe; |
b94dec87 | 4178 | enum intel_pipe_crc_object object; |
926321d5 DV |
4179 | enum intel_pipe_crc_source source; |
4180 | ||
bd9db02f | 4181 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
4182 | if (n_words != N_WORDS) { |
4183 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
4184 | N_WORDS); | |
4185 | return -EINVAL; | |
4186 | } | |
4187 | ||
bd9db02f | 4188 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 4189 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
4190 | return -EINVAL; |
4191 | } | |
4192 | ||
bd9db02f | 4193 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 4194 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
4195 | return -EINVAL; |
4196 | } | |
4197 | ||
bd9db02f | 4198 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 4199 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
4200 | return -EINVAL; |
4201 | } | |
4202 | ||
4203 | return pipe_crc_set_source(dev, pipe, source); | |
4204 | } | |
4205 | ||
bd9db02f DL |
4206 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
4207 | size_t len, loff_t *offp) | |
926321d5 DV |
4208 | { |
4209 | struct seq_file *m = file->private_data; | |
4210 | struct drm_device *dev = m->private; | |
4211 | char *tmpbuf; | |
4212 | int ret; | |
4213 | ||
4214 | if (len == 0) | |
4215 | return 0; | |
4216 | ||
4217 | if (len > PAGE_SIZE - 1) { | |
4218 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
4219 | PAGE_SIZE); | |
4220 | return -E2BIG; | |
4221 | } | |
4222 | ||
4223 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
4224 | if (!tmpbuf) | |
4225 | return -ENOMEM; | |
4226 | ||
4227 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
4228 | ret = -EFAULT; | |
4229 | goto out; | |
4230 | } | |
4231 | tmpbuf[len] = '\0'; | |
4232 | ||
bd9db02f | 4233 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
4234 | |
4235 | out: | |
4236 | kfree(tmpbuf); | |
4237 | if (ret < 0) | |
4238 | return ret; | |
4239 | ||
4240 | *offp += len; | |
4241 | return len; | |
4242 | } | |
4243 | ||
bd9db02f | 4244 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4245 | .owner = THIS_MODULE, |
bd9db02f | 4246 | .open = display_crc_ctl_open, |
926321d5 DV |
4247 | .read = seq_read, |
4248 | .llseek = seq_lseek, | |
4249 | .release = single_release, | |
bd9db02f | 4250 | .write = display_crc_ctl_write |
926321d5 DV |
4251 | }; |
4252 | ||
eb3394fa TP |
4253 | static ssize_t i915_displayport_test_active_write(struct file *file, |
4254 | const char __user *ubuf, | |
4255 | size_t len, loff_t *offp) | |
4256 | { | |
4257 | char *input_buffer; | |
4258 | int status = 0; | |
eb3394fa TP |
4259 | struct drm_device *dev; |
4260 | struct drm_connector *connector; | |
4261 | struct list_head *connector_list; | |
4262 | struct intel_dp *intel_dp; | |
4263 | int val = 0; | |
4264 | ||
9aaffa34 | 4265 | dev = ((struct seq_file *)file->private_data)->private; |
eb3394fa | 4266 | |
eb3394fa TP |
4267 | connector_list = &dev->mode_config.connector_list; |
4268 | ||
4269 | if (len == 0) | |
4270 | return 0; | |
4271 | ||
4272 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4273 | if (!input_buffer) | |
4274 | return -ENOMEM; | |
4275 | ||
4276 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4277 | status = -EFAULT; | |
4278 | goto out; | |
4279 | } | |
4280 | ||
4281 | input_buffer[len] = '\0'; | |
4282 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4283 | ||
4284 | list_for_each_entry(connector, connector_list, head) { | |
4285 | ||
4286 | if (connector->connector_type != | |
4287 | DRM_MODE_CONNECTOR_DisplayPort) | |
4288 | continue; | |
4289 | ||
b8bb08ec | 4290 | if (connector->status == connector_status_connected && |
eb3394fa TP |
4291 | connector->encoder != NULL) { |
4292 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4293 | status = kstrtoint(input_buffer, 10, &val); | |
4294 | if (status < 0) | |
4295 | goto out; | |
4296 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4297 | /* To prevent erroneous activation of the compliance | |
4298 | * testing code, only accept an actual value of 1 here | |
4299 | */ | |
4300 | if (val == 1) | |
4301 | intel_dp->compliance_test_active = 1; | |
4302 | else | |
4303 | intel_dp->compliance_test_active = 0; | |
4304 | } | |
4305 | } | |
4306 | out: | |
4307 | kfree(input_buffer); | |
4308 | if (status < 0) | |
4309 | return status; | |
4310 | ||
4311 | *offp += len; | |
4312 | return len; | |
4313 | } | |
4314 | ||
4315 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4316 | { | |
4317 | struct drm_device *dev = m->private; | |
4318 | struct drm_connector *connector; | |
4319 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4320 | struct intel_dp *intel_dp; | |
4321 | ||
eb3394fa TP |
4322 | list_for_each_entry(connector, connector_list, head) { |
4323 | ||
4324 | if (connector->connector_type != | |
4325 | DRM_MODE_CONNECTOR_DisplayPort) | |
4326 | continue; | |
4327 | ||
4328 | if (connector->status == connector_status_connected && | |
4329 | connector->encoder != NULL) { | |
4330 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4331 | if (intel_dp->compliance_test_active) | |
4332 | seq_puts(m, "1"); | |
4333 | else | |
4334 | seq_puts(m, "0"); | |
4335 | } else | |
4336 | seq_puts(m, "0"); | |
4337 | } | |
4338 | ||
4339 | return 0; | |
4340 | } | |
4341 | ||
4342 | static int i915_displayport_test_active_open(struct inode *inode, | |
4343 | struct file *file) | |
4344 | { | |
4345 | struct drm_device *dev = inode->i_private; | |
4346 | ||
4347 | return single_open(file, i915_displayport_test_active_show, dev); | |
4348 | } | |
4349 | ||
4350 | static const struct file_operations i915_displayport_test_active_fops = { | |
4351 | .owner = THIS_MODULE, | |
4352 | .open = i915_displayport_test_active_open, | |
4353 | .read = seq_read, | |
4354 | .llseek = seq_lseek, | |
4355 | .release = single_release, | |
4356 | .write = i915_displayport_test_active_write | |
4357 | }; | |
4358 | ||
4359 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4360 | { | |
4361 | struct drm_device *dev = m->private; | |
4362 | struct drm_connector *connector; | |
4363 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4364 | struct intel_dp *intel_dp; | |
4365 | ||
eb3394fa TP |
4366 | list_for_each_entry(connector, connector_list, head) { |
4367 | ||
4368 | if (connector->connector_type != | |
4369 | DRM_MODE_CONNECTOR_DisplayPort) | |
4370 | continue; | |
4371 | ||
4372 | if (connector->status == connector_status_connected && | |
4373 | connector->encoder != NULL) { | |
4374 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4375 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4376 | } else | |
4377 | seq_puts(m, "0"); | |
4378 | } | |
4379 | ||
4380 | return 0; | |
4381 | } | |
4382 | static int i915_displayport_test_data_open(struct inode *inode, | |
4383 | struct file *file) | |
4384 | { | |
4385 | struct drm_device *dev = inode->i_private; | |
4386 | ||
4387 | return single_open(file, i915_displayport_test_data_show, dev); | |
4388 | } | |
4389 | ||
4390 | static const struct file_operations i915_displayport_test_data_fops = { | |
4391 | .owner = THIS_MODULE, | |
4392 | .open = i915_displayport_test_data_open, | |
4393 | .read = seq_read, | |
4394 | .llseek = seq_lseek, | |
4395 | .release = single_release | |
4396 | }; | |
4397 | ||
4398 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4399 | { | |
4400 | struct drm_device *dev = m->private; | |
4401 | struct drm_connector *connector; | |
4402 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4403 | struct intel_dp *intel_dp; | |
4404 | ||
eb3394fa TP |
4405 | list_for_each_entry(connector, connector_list, head) { |
4406 | ||
4407 | if (connector->connector_type != | |
4408 | DRM_MODE_CONNECTOR_DisplayPort) | |
4409 | continue; | |
4410 | ||
4411 | if (connector->status == connector_status_connected && | |
4412 | connector->encoder != NULL) { | |
4413 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4414 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4415 | } else | |
4416 | seq_puts(m, "0"); | |
4417 | } | |
4418 | ||
4419 | return 0; | |
4420 | } | |
4421 | ||
4422 | static int i915_displayport_test_type_open(struct inode *inode, | |
4423 | struct file *file) | |
4424 | { | |
4425 | struct drm_device *dev = inode->i_private; | |
4426 | ||
4427 | return single_open(file, i915_displayport_test_type_show, dev); | |
4428 | } | |
4429 | ||
4430 | static const struct file_operations i915_displayport_test_type_fops = { | |
4431 | .owner = THIS_MODULE, | |
4432 | .open = i915_displayport_test_type_open, | |
4433 | .read = seq_read, | |
4434 | .llseek = seq_lseek, | |
4435 | .release = single_release | |
4436 | }; | |
4437 | ||
97e94b22 | 4438 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 VS |
4439 | { |
4440 | struct drm_device *dev = m->private; | |
369a1342 | 4441 | int level; |
de38b95c VS |
4442 | int num_levels; |
4443 | ||
4444 | if (IS_CHERRYVIEW(dev)) | |
4445 | num_levels = 3; | |
4446 | else if (IS_VALLEYVIEW(dev)) | |
4447 | num_levels = 1; | |
4448 | else | |
4449 | num_levels = ilk_wm_max_level(dev) + 1; | |
369a1342 VS |
4450 | |
4451 | drm_modeset_lock_all(dev); | |
4452 | ||
4453 | for (level = 0; level < num_levels; level++) { | |
4454 | unsigned int latency = wm[level]; | |
4455 | ||
97e94b22 DL |
4456 | /* |
4457 | * - WM1+ latency values in 0.5us units | |
de38b95c | 4458 | * - latencies are in us on gen9/vlv/chv |
97e94b22 | 4459 | */ |
666a4537 WB |
4460 | if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) || |
4461 | IS_CHERRYVIEW(dev)) | |
97e94b22 DL |
4462 | latency *= 10; |
4463 | else if (level > 0) | |
369a1342 VS |
4464 | latency *= 5; |
4465 | ||
4466 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4467 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4468 | } |
4469 | ||
4470 | drm_modeset_unlock_all(dev); | |
4471 | } | |
4472 | ||
4473 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4474 | { | |
4475 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4476 | struct drm_i915_private *dev_priv = dev->dev_private; |
4477 | const uint16_t *latencies; | |
4478 | ||
4479 | if (INTEL_INFO(dev)->gen >= 9) | |
4480 | latencies = dev_priv->wm.skl_latency; | |
4481 | else | |
4482 | latencies = to_i915(dev)->wm.pri_latency; | |
369a1342 | 4483 | |
97e94b22 | 4484 | wm_latency_show(m, latencies); |
369a1342 VS |
4485 | |
4486 | return 0; | |
4487 | } | |
4488 | ||
4489 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4490 | { | |
4491 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4492 | struct drm_i915_private *dev_priv = dev->dev_private; |
4493 | const uint16_t *latencies; | |
4494 | ||
4495 | if (INTEL_INFO(dev)->gen >= 9) | |
4496 | latencies = dev_priv->wm.skl_latency; | |
4497 | else | |
4498 | latencies = to_i915(dev)->wm.spr_latency; | |
369a1342 | 4499 | |
97e94b22 | 4500 | wm_latency_show(m, latencies); |
369a1342 VS |
4501 | |
4502 | return 0; | |
4503 | } | |
4504 | ||
4505 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4506 | { | |
4507 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4508 | struct drm_i915_private *dev_priv = dev->dev_private; |
4509 | const uint16_t *latencies; | |
4510 | ||
4511 | if (INTEL_INFO(dev)->gen >= 9) | |
4512 | latencies = dev_priv->wm.skl_latency; | |
4513 | else | |
4514 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4515 | |
97e94b22 | 4516 | wm_latency_show(m, latencies); |
369a1342 VS |
4517 | |
4518 | return 0; | |
4519 | } | |
4520 | ||
4521 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4522 | { | |
4523 | struct drm_device *dev = inode->i_private; | |
4524 | ||
de38b95c | 4525 | if (INTEL_INFO(dev)->gen < 5) |
369a1342 VS |
4526 | return -ENODEV; |
4527 | ||
4528 | return single_open(file, pri_wm_latency_show, dev); | |
4529 | } | |
4530 | ||
4531 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4532 | { | |
4533 | struct drm_device *dev = inode->i_private; | |
4534 | ||
9ad0257c | 4535 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4536 | return -ENODEV; |
4537 | ||
4538 | return single_open(file, spr_wm_latency_show, dev); | |
4539 | } | |
4540 | ||
4541 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4542 | { | |
4543 | struct drm_device *dev = inode->i_private; | |
4544 | ||
9ad0257c | 4545 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4546 | return -ENODEV; |
4547 | ||
4548 | return single_open(file, cur_wm_latency_show, dev); | |
4549 | } | |
4550 | ||
4551 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4552 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4553 | { |
4554 | struct seq_file *m = file->private_data; | |
4555 | struct drm_device *dev = m->private; | |
97e94b22 | 4556 | uint16_t new[8] = { 0 }; |
de38b95c | 4557 | int num_levels; |
369a1342 VS |
4558 | int level; |
4559 | int ret; | |
4560 | char tmp[32]; | |
4561 | ||
de38b95c VS |
4562 | if (IS_CHERRYVIEW(dev)) |
4563 | num_levels = 3; | |
4564 | else if (IS_VALLEYVIEW(dev)) | |
4565 | num_levels = 1; | |
4566 | else | |
4567 | num_levels = ilk_wm_max_level(dev) + 1; | |
4568 | ||
369a1342 VS |
4569 | if (len >= sizeof(tmp)) |
4570 | return -EINVAL; | |
4571 | ||
4572 | if (copy_from_user(tmp, ubuf, len)) | |
4573 | return -EFAULT; | |
4574 | ||
4575 | tmp[len] = '\0'; | |
4576 | ||
97e94b22 DL |
4577 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4578 | &new[0], &new[1], &new[2], &new[3], | |
4579 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4580 | if (ret != num_levels) |
4581 | return -EINVAL; | |
4582 | ||
4583 | drm_modeset_lock_all(dev); | |
4584 | ||
4585 | for (level = 0; level < num_levels; level++) | |
4586 | wm[level] = new[level]; | |
4587 | ||
4588 | drm_modeset_unlock_all(dev); | |
4589 | ||
4590 | return len; | |
4591 | } | |
4592 | ||
4593 | ||
4594 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4595 | size_t len, loff_t *offp) | |
4596 | { | |
4597 | struct seq_file *m = file->private_data; | |
4598 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4599 | struct drm_i915_private *dev_priv = dev->dev_private; |
4600 | uint16_t *latencies; | |
369a1342 | 4601 | |
97e94b22 DL |
4602 | if (INTEL_INFO(dev)->gen >= 9) |
4603 | latencies = dev_priv->wm.skl_latency; | |
4604 | else | |
4605 | latencies = to_i915(dev)->wm.pri_latency; | |
4606 | ||
4607 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4608 | } |
4609 | ||
4610 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4611 | size_t len, loff_t *offp) | |
4612 | { | |
4613 | struct seq_file *m = file->private_data; | |
4614 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4615 | struct drm_i915_private *dev_priv = dev->dev_private; |
4616 | uint16_t *latencies; | |
369a1342 | 4617 | |
97e94b22 DL |
4618 | if (INTEL_INFO(dev)->gen >= 9) |
4619 | latencies = dev_priv->wm.skl_latency; | |
4620 | else | |
4621 | latencies = to_i915(dev)->wm.spr_latency; | |
4622 | ||
4623 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4624 | } |
4625 | ||
4626 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4627 | size_t len, loff_t *offp) | |
4628 | { | |
4629 | struct seq_file *m = file->private_data; | |
4630 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4631 | struct drm_i915_private *dev_priv = dev->dev_private; |
4632 | uint16_t *latencies; | |
4633 | ||
4634 | if (INTEL_INFO(dev)->gen >= 9) | |
4635 | latencies = dev_priv->wm.skl_latency; | |
4636 | else | |
4637 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4638 | |
97e94b22 | 4639 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4640 | } |
4641 | ||
4642 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4643 | .owner = THIS_MODULE, | |
4644 | .open = pri_wm_latency_open, | |
4645 | .read = seq_read, | |
4646 | .llseek = seq_lseek, | |
4647 | .release = single_release, | |
4648 | .write = pri_wm_latency_write | |
4649 | }; | |
4650 | ||
4651 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4652 | .owner = THIS_MODULE, | |
4653 | .open = spr_wm_latency_open, | |
4654 | .read = seq_read, | |
4655 | .llseek = seq_lseek, | |
4656 | .release = single_release, | |
4657 | .write = spr_wm_latency_write | |
4658 | }; | |
4659 | ||
4660 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4661 | .owner = THIS_MODULE, | |
4662 | .open = cur_wm_latency_open, | |
4663 | .read = seq_read, | |
4664 | .llseek = seq_lseek, | |
4665 | .release = single_release, | |
4666 | .write = cur_wm_latency_write | |
4667 | }; | |
4668 | ||
647416f9 KC |
4669 | static int |
4670 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4671 | { |
647416f9 | 4672 | struct drm_device *dev = data; |
e277a1f8 | 4673 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 4674 | |
647416f9 | 4675 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 4676 | |
647416f9 | 4677 | return 0; |
f3cd474b CW |
4678 | } |
4679 | ||
647416f9 KC |
4680 | static int |
4681 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4682 | { |
647416f9 | 4683 | struct drm_device *dev = data; |
d46c0517 ID |
4684 | struct drm_i915_private *dev_priv = dev->dev_private; |
4685 | ||
b8d24a06 MK |
4686 | /* |
4687 | * There is no safeguard against this debugfs entry colliding | |
4688 | * with the hangcheck calling same i915_handle_error() in | |
4689 | * parallel, causing an explosion. For now we assume that the | |
4690 | * test harness is responsible enough not to inject gpu hangs | |
4691 | * while it is writing to 'i915_wedged' | |
4692 | */ | |
4693 | ||
4694 | if (i915_reset_in_progress(&dev_priv->gpu_error)) | |
4695 | return -EAGAIN; | |
4696 | ||
d46c0517 | 4697 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 4698 | |
58174462 MK |
4699 | i915_handle_error(dev, val, |
4700 | "Manually setting wedged to %llu", val); | |
d46c0517 ID |
4701 | |
4702 | intel_runtime_pm_put(dev_priv); | |
4703 | ||
647416f9 | 4704 | return 0; |
f3cd474b CW |
4705 | } |
4706 | ||
647416f9 KC |
4707 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4708 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4709 | "%llu\n"); |
f3cd474b | 4710 | |
647416f9 KC |
4711 | static int |
4712 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 4713 | { |
647416f9 | 4714 | struct drm_device *dev = data; |
e277a1f8 | 4715 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 4716 | |
647416f9 | 4717 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 4718 | |
647416f9 | 4719 | return 0; |
e5eb3d63 DV |
4720 | } |
4721 | ||
647416f9 KC |
4722 | static int |
4723 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 4724 | { |
647416f9 | 4725 | struct drm_device *dev = data; |
e5eb3d63 | 4726 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4727 | int ret; |
e5eb3d63 | 4728 | |
647416f9 | 4729 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 4730 | |
22bcfc6a DV |
4731 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4732 | if (ret) | |
4733 | return ret; | |
4734 | ||
99584db3 | 4735 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
4736 | mutex_unlock(&dev->struct_mutex); |
4737 | ||
647416f9 | 4738 | return 0; |
e5eb3d63 DV |
4739 | } |
4740 | ||
647416f9 KC |
4741 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
4742 | i915_ring_stop_get, i915_ring_stop_set, | |
4743 | "0x%08llx\n"); | |
d5442303 | 4744 | |
094f9a54 CW |
4745 | static int |
4746 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4747 | { | |
4748 | struct drm_device *dev = data; | |
4749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4750 | ||
4751 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4752 | return 0; | |
4753 | } | |
4754 | ||
4755 | static int | |
4756 | i915_ring_missed_irq_set(void *data, u64 val) | |
4757 | { | |
4758 | struct drm_device *dev = data; | |
4759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4760 | int ret; | |
4761 | ||
4762 | /* Lock against concurrent debugfs callers */ | |
4763 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4764 | if (ret) | |
4765 | return ret; | |
4766 | dev_priv->gpu_error.missed_irq_rings = val; | |
4767 | mutex_unlock(&dev->struct_mutex); | |
4768 | ||
4769 | return 0; | |
4770 | } | |
4771 | ||
4772 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4773 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4774 | "0x%08llx\n"); | |
4775 | ||
4776 | static int | |
4777 | i915_ring_test_irq_get(void *data, u64 *val) | |
4778 | { | |
4779 | struct drm_device *dev = data; | |
4780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4781 | ||
4782 | *val = dev_priv->gpu_error.test_irq_rings; | |
4783 | ||
4784 | return 0; | |
4785 | } | |
4786 | ||
4787 | static int | |
4788 | i915_ring_test_irq_set(void *data, u64 val) | |
4789 | { | |
4790 | struct drm_device *dev = data; | |
4791 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4792 | int ret; | |
4793 | ||
4794 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
4795 | ||
4796 | /* Lock against concurrent debugfs callers */ | |
4797 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4798 | if (ret) | |
4799 | return ret; | |
4800 | ||
4801 | dev_priv->gpu_error.test_irq_rings = val; | |
4802 | mutex_unlock(&dev->struct_mutex); | |
4803 | ||
4804 | return 0; | |
4805 | } | |
4806 | ||
4807 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4808 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4809 | "0x%08llx\n"); | |
4810 | ||
dd624afd CW |
4811 | #define DROP_UNBOUND 0x1 |
4812 | #define DROP_BOUND 0x2 | |
4813 | #define DROP_RETIRE 0x4 | |
4814 | #define DROP_ACTIVE 0x8 | |
4815 | #define DROP_ALL (DROP_UNBOUND | \ | |
4816 | DROP_BOUND | \ | |
4817 | DROP_RETIRE | \ | |
4818 | DROP_ACTIVE) | |
647416f9 KC |
4819 | static int |
4820 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4821 | { |
647416f9 | 4822 | *val = DROP_ALL; |
dd624afd | 4823 | |
647416f9 | 4824 | return 0; |
dd624afd CW |
4825 | } |
4826 | ||
647416f9 KC |
4827 | static int |
4828 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4829 | { |
647416f9 | 4830 | struct drm_device *dev = data; |
dd624afd | 4831 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4832 | int ret; |
dd624afd | 4833 | |
2f9fe5ff | 4834 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4835 | |
4836 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4837 | * on ioctls on -EAGAIN. */ | |
4838 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4839 | if (ret) | |
4840 | return ret; | |
4841 | ||
4842 | if (val & DROP_ACTIVE) { | |
4843 | ret = i915_gpu_idle(dev); | |
4844 | if (ret) | |
4845 | goto unlock; | |
4846 | } | |
4847 | ||
4848 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
4849 | i915_gem_retire_requests(dev); | |
4850 | ||
21ab4e74 CW |
4851 | if (val & DROP_BOUND) |
4852 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4853 | |
21ab4e74 CW |
4854 | if (val & DROP_UNBOUND) |
4855 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4856 | |
4857 | unlock: | |
4858 | mutex_unlock(&dev->struct_mutex); | |
4859 | ||
647416f9 | 4860 | return ret; |
dd624afd CW |
4861 | } |
4862 | ||
647416f9 KC |
4863 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4864 | i915_drop_caches_get, i915_drop_caches_set, | |
4865 | "0x%08llx\n"); | |
dd624afd | 4866 | |
647416f9 KC |
4867 | static int |
4868 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4869 | { |
647416f9 | 4870 | struct drm_device *dev = data; |
e277a1f8 | 4871 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4872 | int ret; |
004777cb | 4873 | |
daa3afb2 | 4874 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4875 | return -ENODEV; |
4876 | ||
5c9669ce TR |
4877 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4878 | ||
4fc688ce | 4879 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4880 | if (ret) |
4881 | return ret; | |
358733e9 | 4882 | |
7c59a9c1 | 4883 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
4fc688ce | 4884 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4885 | |
647416f9 | 4886 | return 0; |
358733e9 JB |
4887 | } |
4888 | ||
647416f9 KC |
4889 | static int |
4890 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4891 | { |
647416f9 | 4892 | struct drm_device *dev = data; |
358733e9 | 4893 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 4894 | u32 hw_max, hw_min; |
647416f9 | 4895 | int ret; |
004777cb | 4896 | |
daa3afb2 | 4897 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4898 | return -ENODEV; |
358733e9 | 4899 | |
5c9669ce TR |
4900 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4901 | ||
647416f9 | 4902 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4903 | |
4fc688ce | 4904 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4905 | if (ret) |
4906 | return ret; | |
4907 | ||
358733e9 JB |
4908 | /* |
4909 | * Turbo will still be enabled, but won't go above the set value. | |
4910 | */ | |
bc4d91f6 | 4911 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4912 | |
bc4d91f6 AG |
4913 | hw_max = dev_priv->rps.max_freq; |
4914 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4915 | |
b39fb297 | 4916 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4917 | mutex_unlock(&dev_priv->rps.hw_lock); |
4918 | return -EINVAL; | |
0a073b84 JB |
4919 | } |
4920 | ||
b39fb297 | 4921 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4922 | |
ffe02b40 | 4923 | intel_set_rps(dev, val); |
dd0a1aa1 | 4924 | |
4fc688ce | 4925 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4926 | |
647416f9 | 4927 | return 0; |
358733e9 JB |
4928 | } |
4929 | ||
647416f9 KC |
4930 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4931 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4932 | "%llu\n"); |
358733e9 | 4933 | |
647416f9 KC |
4934 | static int |
4935 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4936 | { |
647416f9 | 4937 | struct drm_device *dev = data; |
e277a1f8 | 4938 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4939 | int ret; |
004777cb | 4940 | |
daa3afb2 | 4941 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4942 | return -ENODEV; |
4943 | ||
5c9669ce TR |
4944 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4945 | ||
4fc688ce | 4946 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4947 | if (ret) |
4948 | return ret; | |
1523c310 | 4949 | |
7c59a9c1 | 4950 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
4fc688ce | 4951 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4952 | |
647416f9 | 4953 | return 0; |
1523c310 JB |
4954 | } |
4955 | ||
647416f9 KC |
4956 | static int |
4957 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4958 | { |
647416f9 | 4959 | struct drm_device *dev = data; |
1523c310 | 4960 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 4961 | u32 hw_max, hw_min; |
647416f9 | 4962 | int ret; |
004777cb | 4963 | |
daa3afb2 | 4964 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4965 | return -ENODEV; |
1523c310 | 4966 | |
5c9669ce TR |
4967 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4968 | ||
647416f9 | 4969 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4970 | |
4fc688ce | 4971 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4972 | if (ret) |
4973 | return ret; | |
4974 | ||
1523c310 JB |
4975 | /* |
4976 | * Turbo will still be enabled, but won't go below the set value. | |
4977 | */ | |
bc4d91f6 | 4978 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4979 | |
bc4d91f6 AG |
4980 | hw_max = dev_priv->rps.max_freq; |
4981 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4982 | |
b39fb297 | 4983 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
4984 | mutex_unlock(&dev_priv->rps.hw_lock); |
4985 | return -EINVAL; | |
0a073b84 | 4986 | } |
dd0a1aa1 | 4987 | |
b39fb297 | 4988 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4989 | |
ffe02b40 | 4990 | intel_set_rps(dev, val); |
dd0a1aa1 | 4991 | |
4fc688ce | 4992 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4993 | |
647416f9 | 4994 | return 0; |
1523c310 JB |
4995 | } |
4996 | ||
647416f9 KC |
4997 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4998 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4999 | "%llu\n"); |
1523c310 | 5000 | |
647416f9 KC |
5001 | static int |
5002 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 5003 | { |
647416f9 | 5004 | struct drm_device *dev = data; |
e277a1f8 | 5005 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 5006 | u32 snpcr; |
647416f9 | 5007 | int ret; |
07b7ddd9 | 5008 | |
004777cb DV |
5009 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5010 | return -ENODEV; | |
5011 | ||
22bcfc6a DV |
5012 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
5013 | if (ret) | |
5014 | return ret; | |
c8c8fb33 | 5015 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 5016 | |
07b7ddd9 | 5017 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
5018 | |
5019 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
5020 | mutex_unlock(&dev_priv->dev->struct_mutex); |
5021 | ||
647416f9 | 5022 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 5023 | |
647416f9 | 5024 | return 0; |
07b7ddd9 JB |
5025 | } |
5026 | ||
647416f9 KC |
5027 | static int |
5028 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 5029 | { |
647416f9 | 5030 | struct drm_device *dev = data; |
07b7ddd9 | 5031 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 5032 | u32 snpcr; |
07b7ddd9 | 5033 | |
004777cb DV |
5034 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
5035 | return -ENODEV; | |
5036 | ||
647416f9 | 5037 | if (val > 3) |
07b7ddd9 JB |
5038 | return -EINVAL; |
5039 | ||
c8c8fb33 | 5040 | intel_runtime_pm_get(dev_priv); |
647416f9 | 5041 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
5042 | |
5043 | /* Update the cache sharing policy here as well */ | |
5044 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
5045 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5046 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
5047 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
5048 | ||
c8c8fb33 | 5049 | intel_runtime_pm_put(dev_priv); |
647416f9 | 5050 | return 0; |
07b7ddd9 JB |
5051 | } |
5052 | ||
647416f9 KC |
5053 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
5054 | i915_cache_sharing_get, i915_cache_sharing_set, | |
5055 | "%llu\n"); | |
07b7ddd9 | 5056 | |
5d39525a JM |
5057 | struct sseu_dev_status { |
5058 | unsigned int slice_total; | |
5059 | unsigned int subslice_total; | |
5060 | unsigned int subslice_per_slice; | |
5061 | unsigned int eu_total; | |
5062 | unsigned int eu_per_subslice; | |
5063 | }; | |
5064 | ||
5065 | static void cherryview_sseu_device_status(struct drm_device *dev, | |
5066 | struct sseu_dev_status *stat) | |
5067 | { | |
5068 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0a0b457f | 5069 | int ss_max = 2; |
5d39525a JM |
5070 | int ss; |
5071 | u32 sig1[ss_max], sig2[ss_max]; | |
5072 | ||
5073 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
5074 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
5075 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
5076 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
5077 | ||
5078 | for (ss = 0; ss < ss_max; ss++) { | |
5079 | unsigned int eu_cnt; | |
5080 | ||
5081 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
5082 | /* skip disabled subslice */ | |
5083 | continue; | |
5084 | ||
5085 | stat->slice_total = 1; | |
5086 | stat->subslice_per_slice++; | |
5087 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + | |
5088 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
5089 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
5090 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
5091 | stat->eu_total += eu_cnt; | |
5092 | stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); | |
5093 | } | |
5094 | stat->subslice_total = stat->subslice_per_slice; | |
5095 | } | |
5096 | ||
5097 | static void gen9_sseu_device_status(struct drm_device *dev, | |
5098 | struct sseu_dev_status *stat) | |
5099 | { | |
5100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1c046bc1 | 5101 | int s_max = 3, ss_max = 4; |
5d39525a JM |
5102 | int s, ss; |
5103 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
5104 | ||
1c046bc1 JM |
5105 | /* BXT has a single slice and at most 3 subslices. */ |
5106 | if (IS_BROXTON(dev)) { | |
5107 | s_max = 1; | |
5108 | ss_max = 3; | |
5109 | } | |
5110 | ||
5111 | for (s = 0; s < s_max; s++) { | |
5112 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
5113 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
5114 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
5115 | } | |
5116 | ||
5d39525a JM |
5117 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
5118 | GEN9_PGCTL_SSA_EU19_ACK | | |
5119 | GEN9_PGCTL_SSA_EU210_ACK | | |
5120 | GEN9_PGCTL_SSA_EU311_ACK; | |
5121 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
5122 | GEN9_PGCTL_SSB_EU19_ACK | | |
5123 | GEN9_PGCTL_SSB_EU210_ACK | | |
5124 | GEN9_PGCTL_SSB_EU311_ACK; | |
5125 | ||
5126 | for (s = 0; s < s_max; s++) { | |
1c046bc1 JM |
5127 | unsigned int ss_cnt = 0; |
5128 | ||
5d39525a JM |
5129 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) |
5130 | /* skip disabled slice */ | |
5131 | continue; | |
5132 | ||
5133 | stat->slice_total++; | |
1c046bc1 | 5134 | |
ef11bdb3 | 5135 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1c046bc1 JM |
5136 | ss_cnt = INTEL_INFO(dev)->subslice_per_slice; |
5137 | ||
5d39525a JM |
5138 | for (ss = 0; ss < ss_max; ss++) { |
5139 | unsigned int eu_cnt; | |
5140 | ||
1c046bc1 JM |
5141 | if (IS_BROXTON(dev) && |
5142 | !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
5143 | /* skip disabled subslice */ | |
5144 | continue; | |
5145 | ||
5146 | if (IS_BROXTON(dev)) | |
5147 | ss_cnt++; | |
5148 | ||
5d39525a JM |
5149 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
5150 | eu_mask[ss%2]); | |
5151 | stat->eu_total += eu_cnt; | |
5152 | stat->eu_per_subslice = max(stat->eu_per_subslice, | |
5153 | eu_cnt); | |
5154 | } | |
1c046bc1 JM |
5155 | |
5156 | stat->subslice_total += ss_cnt; | |
5157 | stat->subslice_per_slice = max(stat->subslice_per_slice, | |
5158 | ss_cnt); | |
5d39525a JM |
5159 | } |
5160 | } | |
5161 | ||
91bedd34 ŁD |
5162 | static void broadwell_sseu_device_status(struct drm_device *dev, |
5163 | struct sseu_dev_status *stat) | |
5164 | { | |
5165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5166 | int s; | |
5167 | u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); | |
5168 | ||
5169 | stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); | |
5170 | ||
5171 | if (stat->slice_total) { | |
5172 | stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; | |
5173 | stat->subslice_total = stat->slice_total * | |
5174 | stat->subslice_per_slice; | |
5175 | stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice; | |
5176 | stat->eu_total = stat->eu_per_subslice * stat->subslice_total; | |
5177 | ||
5178 | /* subtract fused off EU(s) from enabled slice(s) */ | |
5179 | for (s = 0; s < stat->slice_total; s++) { | |
5180 | u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s]; | |
5181 | ||
5182 | stat->eu_total -= hweight8(subslice_7eu); | |
5183 | } | |
5184 | } | |
5185 | } | |
5186 | ||
3873218f JM |
5187 | static int i915_sseu_status(struct seq_file *m, void *unused) |
5188 | { | |
5189 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
5190 | struct drm_device *dev = node->minor->dev; | |
5d39525a | 5191 | struct sseu_dev_status stat; |
3873218f | 5192 | |
91bedd34 | 5193 | if (INTEL_INFO(dev)->gen < 8) |
3873218f JM |
5194 | return -ENODEV; |
5195 | ||
5196 | seq_puts(m, "SSEU Device Info\n"); | |
5197 | seq_printf(m, " Available Slice Total: %u\n", | |
5198 | INTEL_INFO(dev)->slice_total); | |
5199 | seq_printf(m, " Available Subslice Total: %u\n", | |
5200 | INTEL_INFO(dev)->subslice_total); | |
5201 | seq_printf(m, " Available Subslice Per Slice: %u\n", | |
5202 | INTEL_INFO(dev)->subslice_per_slice); | |
5203 | seq_printf(m, " Available EU Total: %u\n", | |
5204 | INTEL_INFO(dev)->eu_total); | |
5205 | seq_printf(m, " Available EU Per Subslice: %u\n", | |
5206 | INTEL_INFO(dev)->eu_per_subslice); | |
5207 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
5208 | yesno(INTEL_INFO(dev)->has_slice_pg)); | |
5209 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
5210 | yesno(INTEL_INFO(dev)->has_subslice_pg)); | |
5211 | seq_printf(m, " Has EU Power Gating: %s\n", | |
5212 | yesno(INTEL_INFO(dev)->has_eu_pg)); | |
5213 | ||
7f992aba | 5214 | seq_puts(m, "SSEU Device Status\n"); |
5d39525a | 5215 | memset(&stat, 0, sizeof(stat)); |
5575f03a | 5216 | if (IS_CHERRYVIEW(dev)) { |
5d39525a | 5217 | cherryview_sseu_device_status(dev, &stat); |
91bedd34 ŁD |
5218 | } else if (IS_BROADWELL(dev)) { |
5219 | broadwell_sseu_device_status(dev, &stat); | |
1c046bc1 | 5220 | } else if (INTEL_INFO(dev)->gen >= 9) { |
5d39525a | 5221 | gen9_sseu_device_status(dev, &stat); |
7f992aba | 5222 | } |
5d39525a JM |
5223 | seq_printf(m, " Enabled Slice Total: %u\n", |
5224 | stat.slice_total); | |
5225 | seq_printf(m, " Enabled Subslice Total: %u\n", | |
5226 | stat.subslice_total); | |
5227 | seq_printf(m, " Enabled Subslice Per Slice: %u\n", | |
5228 | stat.subslice_per_slice); | |
5229 | seq_printf(m, " Enabled EU Total: %u\n", | |
5230 | stat.eu_total); | |
5231 | seq_printf(m, " Enabled EU Per Subslice: %u\n", | |
5232 | stat.eu_per_subslice); | |
7f992aba | 5233 | |
3873218f JM |
5234 | return 0; |
5235 | } | |
5236 | ||
6d794d42 BW |
5237 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
5238 | { | |
5239 | struct drm_device *dev = inode->i_private; | |
5240 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 5241 | |
075edca4 | 5242 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5243 | return 0; |
5244 | ||
6daccb0b | 5245 | intel_runtime_pm_get(dev_priv); |
59bad947 | 5246 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
5247 | |
5248 | return 0; | |
5249 | } | |
5250 | ||
c43b5634 | 5251 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
5252 | { |
5253 | struct drm_device *dev = inode->i_private; | |
5254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5255 | ||
075edca4 | 5256 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
5257 | return 0; |
5258 | ||
59bad947 | 5259 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 5260 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
5261 | |
5262 | return 0; | |
5263 | } | |
5264 | ||
5265 | static const struct file_operations i915_forcewake_fops = { | |
5266 | .owner = THIS_MODULE, | |
5267 | .open = i915_forcewake_open, | |
5268 | .release = i915_forcewake_release, | |
5269 | }; | |
5270 | ||
5271 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5272 | { | |
5273 | struct drm_device *dev = minor->dev; | |
5274 | struct dentry *ent; | |
5275 | ||
5276 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5277 | S_IRUSR, |
6d794d42 BW |
5278 | root, dev, |
5279 | &i915_forcewake_fops); | |
f3c5fe97 WY |
5280 | if (!ent) |
5281 | return -ENOMEM; | |
6d794d42 | 5282 | |
8eb57294 | 5283 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5284 | } |
5285 | ||
6a9c308d DV |
5286 | static int i915_debugfs_create(struct dentry *root, |
5287 | struct drm_minor *minor, | |
5288 | const char *name, | |
5289 | const struct file_operations *fops) | |
07b7ddd9 JB |
5290 | { |
5291 | struct drm_device *dev = minor->dev; | |
5292 | struct dentry *ent; | |
5293 | ||
6a9c308d | 5294 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
5295 | S_IRUGO | S_IWUSR, |
5296 | root, dev, | |
6a9c308d | 5297 | fops); |
f3c5fe97 WY |
5298 | if (!ent) |
5299 | return -ENOMEM; | |
07b7ddd9 | 5300 | |
6a9c308d | 5301 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5302 | } |
5303 | ||
06c5bf8c | 5304 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5305 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5306 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5307 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 5308 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 5309 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 5310 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 5311 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5312 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5313 | {"i915_gem_request", i915_gem_request_info, 0}, |
5314 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5315 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5316 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5317 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5318 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5319 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5320 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5321 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
8b417c26 | 5322 | {"i915_guc_info", i915_guc_info, 0}, |
fdf5d357 | 5323 | {"i915_guc_load_status", i915_guc_load_status_info, 0}, |
4c7e77fc | 5324 | {"i915_guc_log_dump", i915_guc_log_dump, 0}, |
adb4bd12 | 5325 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5326 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5327 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5328 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5329 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
9a851789 | 5330 | {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, |
b5e50c3f | 5331 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5332 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5333 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5334 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 5335 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5336 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5337 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 5338 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 5339 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5340 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5341 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5342 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5343 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5344 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5345 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5346 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5347 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
b7cec66d | 5348 | {"i915_dmc_info", i915_dmc_info, 0}, |
53f5e3ca | 5349 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 5350 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5351 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5352 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5353 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5354 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5355 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5356 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5357 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5358 | }; |
27c202ad | 5359 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5360 | |
06c5bf8c | 5361 | static const struct i915_debugfs_files { |
34b9674c DV |
5362 | const char *name; |
5363 | const struct file_operations *fops; | |
5364 | } i915_debugfs_files[] = { | |
5365 | {"i915_wedged", &i915_wedged_fops}, | |
5366 | {"i915_max_freq", &i915_max_freq_fops}, | |
5367 | {"i915_min_freq", &i915_min_freq_fops}, | |
5368 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
5369 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
5370 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5371 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
5372 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
5373 | {"i915_error_state", &i915_error_state_fops}, | |
5374 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 5375 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5376 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5377 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5378 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5379 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5380 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5381 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
5382 | {"i915_dp_test_active", &i915_displayport_test_active_fops} | |
34b9674c DV |
5383 | }; |
5384 | ||
07144428 DL |
5385 | void intel_display_crc_init(struct drm_device *dev) |
5386 | { | |
5387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 5388 | enum pipe pipe; |
07144428 | 5389 | |
055e393f | 5390 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5391 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5392 | |
d538bbdf DL |
5393 | pipe_crc->opened = false; |
5394 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5395 | init_waitqueue_head(&pipe_crc->wq); |
5396 | } | |
5397 | } | |
5398 | ||
27c202ad | 5399 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 5400 | { |
34b9674c | 5401 | int ret, i; |
f3cd474b | 5402 | |
6d794d42 | 5403 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5404 | if (ret) |
5405 | return ret; | |
6a9c308d | 5406 | |
07144428 DL |
5407 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5408 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5409 | if (ret) | |
5410 | return ret; | |
5411 | } | |
5412 | ||
34b9674c DV |
5413 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5414 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5415 | i915_debugfs_files[i].name, | |
5416 | i915_debugfs_files[i].fops); | |
5417 | if (ret) | |
5418 | return ret; | |
5419 | } | |
40633219 | 5420 | |
27c202ad BG |
5421 | return drm_debugfs_create_files(i915_debugfs_list, |
5422 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5423 | minor->debugfs_root, minor); |
5424 | } | |
5425 | ||
27c202ad | 5426 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 5427 | { |
34b9674c DV |
5428 | int i; |
5429 | ||
27c202ad BG |
5430 | drm_debugfs_remove_files(i915_debugfs_list, |
5431 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5432 | |
6d794d42 BW |
5433 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
5434 | 1, minor); | |
07144428 | 5435 | |
e309a997 | 5436 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5437 | struct drm_info_list *info_list = |
5438 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5439 | ||
5440 | drm_debugfs_remove_files(info_list, 1, minor); | |
5441 | } | |
5442 | ||
34b9674c DV |
5443 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5444 | struct drm_info_list *info_list = | |
5445 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
5446 | ||
5447 | drm_debugfs_remove_files(info_list, 1, minor); | |
5448 | } | |
2017263e | 5449 | } |
aa7471d2 JN |
5450 | |
5451 | struct dpcd_block { | |
5452 | /* DPCD dump start address. */ | |
5453 | unsigned int offset; | |
5454 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5455 | unsigned int end; | |
5456 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5457 | size_t size; | |
5458 | /* Only valid for eDP. */ | |
5459 | bool edp; | |
5460 | }; | |
5461 | ||
5462 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5463 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5464 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5465 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5466 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5467 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5468 | { .offset = DP_SET_POWER }, | |
5469 | { .offset = DP_EDP_DPCD_REV }, | |
5470 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5471 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5472 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5473 | }; | |
5474 | ||
5475 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5476 | { | |
5477 | struct drm_connector *connector = m->private; | |
5478 | struct intel_dp *intel_dp = | |
5479 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5480 | uint8_t buf[16]; | |
5481 | ssize_t err; | |
5482 | int i; | |
5483 | ||
5c1a8875 MK |
5484 | if (connector->status != connector_status_connected) |
5485 | return -ENODEV; | |
5486 | ||
aa7471d2 JN |
5487 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5488 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5489 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5490 | ||
5491 | if (b->edp && | |
5492 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5493 | continue; | |
5494 | ||
5495 | /* low tech for now */ | |
5496 | if (WARN_ON(size > sizeof(buf))) | |
5497 | continue; | |
5498 | ||
5499 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5500 | if (err <= 0) { | |
5501 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5502 | size, b->offset, err); | |
5503 | continue; | |
5504 | } | |
5505 | ||
5506 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5507 | } |
aa7471d2 JN |
5508 | |
5509 | return 0; | |
5510 | } | |
5511 | ||
5512 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5513 | { | |
5514 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5515 | } | |
5516 | ||
5517 | static const struct file_operations i915_dpcd_fops = { | |
5518 | .owner = THIS_MODULE, | |
5519 | .open = i915_dpcd_open, | |
5520 | .read = seq_read, | |
5521 | .llseek = seq_lseek, | |
5522 | .release = single_release, | |
5523 | }; | |
5524 | ||
5525 | /** | |
5526 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5527 | * @connector: pointer to a registered drm_connector | |
5528 | * | |
5529 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5530 | * drm_debugfs_connector_remove(). | |
5531 | * | |
5532 | * Returns 0 on success, negative error codes on error. | |
5533 | */ | |
5534 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5535 | { | |
5536 | struct dentry *root = connector->debugfs_entry; | |
5537 | ||
5538 | /* The connector must have been registered beforehands. */ | |
5539 | if (!root) | |
5540 | return -ENODEV; | |
5541 | ||
5542 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5543 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5544 | debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, | |
5545 | &i915_dpcd_fops); | |
5546 | ||
5547 | return 0; | |
5548 | } |