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drm/i915/skl: Expose DC5/DC6 entry counts
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
497666d8
DL		 49/* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
51static int
52drm_add_fake_info_node(struct drm_minor *minor,
53 struct dentry *ent,
54 const void *key)
55{
56 struct drm_info_node *node;
57
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
59 if (node == NULL) {
60 debugfs_remove(ent);
61 return -ENOMEM;
62 }
63
64 node->minor = minor;
65 node->dent = ent;
66 node->info_ent = (void *) key;
67
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
71
72 return 0;
73}
74
70d39fe4
CW		 75static int i915_capabilities(struct seq_file *m, void *data)
76{
9f25d007 77 struct drm_info_node *node = m->private;
70d39fe4
CW		 78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
80
81 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 83#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84#define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
86#undef PRINT_FLAG
87#undef SEP_SEMICOLON
70d39fe4
CW		 88
89 return 0;
90}
2017263e 91
05394f39 92static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 93{
baaa5cfb 94 if (obj->pin_display)
a6172a80
CW		 95 return "p";
96 else
97 return " ";
98}
99
05394f39 100static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 101{
0206e353
AJ		 102 switch (obj->tiling_mode) {
103 default:
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
107 }
a6172a80
CW		 108}
109
1d693bcc
BW		 110static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
111{
aff43766 112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 113}
114
ca1543be
TU		 115static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
116{
117 u64 size = 0;
118 struct i915_vma *vma;
119
120 list_for_each_entry(vma, &obj->vma_list, vma_link) {
121 if (i915_is_ggtt(vma->vm) &&
122 drm_mm_node_allocated(&vma->node))
123 size += vma->node.size;
124 }
125
126 return size;
127}
128
37811fcc
CW		 129static void
130describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
131{
b4716185
CW		 132 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
133 struct intel_engine_cs *ring;
1d693bcc 134 struct i915_vma *vma;
d7f46fc4 135 int pin_count = 0;
b4716185 136 int i;
d7f46fc4 137
b4716185 138 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 139 &obj->base,
481a3d43 140 obj->active ? "*" : " ",
37811fcc
CW		 141 get_pin_flag(obj),
142 get_tiling_flag(obj),
1d693bcc 143 get_global_flag(obj),
a05a5862 144 obj->base.size / 1024,
37811fcc 145 obj->base.read_domains,
b4716185
CW		 146 obj->base.write_domain);
147 for_each_ring(ring, dev_priv, i)
148 seq_printf(m, "%x ",
149 i915_gem_request_get_seqno(obj->last_read_req[i]));
150 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 151 i915_gem_request_get_seqno(obj->last_write_req),
152 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 153 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 154 obj->dirty ? " dirty" : "",
155 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
156 if (obj->base.name)
157 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 158 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 159 if (vma->pin_count > 0)
160 pin_count++;
ba0635ff
DC		 161 }
162 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 163 if (obj->pin_display)
164 seq_printf(m, " (display)");
37811fcc
CW		 165 if (obj->fence_reg != I915_FENCE_REG_NONE)
166 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc 167 list_for_each_entry(vma, &obj->vma_list, vma_link) {
8d2fdc3f
TU		 168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
169 i915_is_ggtt(vma->vm) ? "g" : "pp",
170 vma->node.start, vma->node.size);
171 if (i915_is_ggtt(vma->vm))
172 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
1d693bcc 173 else
8d2fdc3f 174 seq_puts(m, ")");
1d693bcc 175 }
c1ad11fc 176 if (obj->stolen)
440fd528 177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 178 if (obj->pin_display || obj->fault_mappable) {
6299f992 179 char s[3], *t = s;
30154650 180 if (obj->pin_display)
6299f992
CW		 181 *t++ = 'p';
182 if (obj->fault_mappable)
183 *t++ = 'f';
184 *t = '\0';
185 seq_printf(m, " (%s mappable)", s);
186 }
b4716185 187 if (obj->last_write_req != NULL)
41c52415 188 seq_printf(m, " (%s)",
b4716185 189 i915_gem_request_get_ring(obj->last_write_req)->name);
d5a81ef1
DV		 190 if (obj->frontbuffer_bits)
191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 192}
193
273497e5 194static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 195{
ea0c76f8 196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 197 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
198 seq_putc(m, ' ');
199}
200
433e12f7 201static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 202{
9f25d007 203 struct drm_info_node *node = m->private;
433e12f7
BG		 204 uintptr_t list = (uintptr_t) node->info_ent->data;
205 struct list_head *head;
2017263e 206 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 207 struct drm_i915_private *dev_priv = dev->dev_private;
208 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 209 struct i915_vma *vma;
c44ef60e 210 u64 total_obj_size, total_gtt_size;
8f2480fb 211 int count, ret;
de227ef0
CW		 212
213 ret = mutex_lock_interruptible(&dev->struct_mutex);
214 if (ret)
215 return ret;
2017263e 216
ca191b13 217 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 218 switch (list) {
219 case ACTIVE_LIST:
267f0c90 220 seq_puts(m, "Active:\n");
5cef07e1 221 head = &vm->active_list;
433e12f7
BG		 222 break;
223 case INACTIVE_LIST:
267f0c90 224 seq_puts(m, "Inactive:\n");
5cef07e1 225 head = &vm->inactive_list;
433e12f7 226 break;
433e12f7 227 default:
de227ef0
CW		 228 mutex_unlock(&dev->struct_mutex);
229 return -EINVAL;
2017263e 230 }
2017263e 231
8f2480fb 232 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 233 list_for_each_entry(vma, head, mm_list) {
234 seq_printf(m, " ");
235 describe_obj(m, vma->obj);
236 seq_printf(m, "\n");
237 total_obj_size += vma->obj->base.size;
238 total_gtt_size += vma->node.size;
8f2480fb 239 count++;
2017263e 240 }
de227ef0 241 mutex_unlock(&dev->struct_mutex);
5e118f41 242
c44ef60e 243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 244 count, total_obj_size, total_gtt_size);
2017263e
BG		 245 return 0;
246}
247
6d2b8885
CW		 248static int obj_rank_by_stolen(void *priv,
249 struct list_head *A, struct list_head *B)
250{
251 struct drm_i915_gem_object *a =
b25cb2f8 252 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 253 struct drm_i915_gem_object *b =
b25cb2f8 254 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 255
2d05fa16
RV		 256 if (a->stolen->start < b->stolen->start)
257 return -1;
258 if (a->stolen->start > b->stolen->start)
259 return 1;
260 return 0;
6d2b8885
CW		 261}
262
263static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
264{
9f25d007 265 struct drm_info_node *node = m->private;
6d2b8885
CW		 266 struct drm_device *dev = node->minor->dev;
267 struct drm_i915_private *dev_priv = dev->dev_private;
268 struct drm_i915_gem_object *obj;
c44ef60e 269 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 270 LIST_HEAD(stolen);
271 int count, ret;
272
273 ret = mutex_lock_interruptible(&dev->struct_mutex);
274 if (ret)
275 return ret;
276
277 total_obj_size = total_gtt_size = count = 0;
278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
279 if (obj->stolen == NULL)
280 continue;
281
b25cb2f8 282 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 283
284 total_obj_size += obj->base.size;
ca1543be 285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 286 count++;
287 }
288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
289 if (obj->stolen == NULL)
290 continue;
291
b25cb2f8 292 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 293
294 total_obj_size += obj->base.size;
295 count++;
296 }
297 list_sort(NULL, &stolen, obj_rank_by_stolen);
298 seq_puts(m, "Stolen:\n");
299 while (!list_empty(&stolen)) {
b25cb2f8 300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 301 seq_puts(m, " ");
302 describe_obj(m, obj);
303 seq_putc(m, '\n');
b25cb2f8 304 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 305 }
306 mutex_unlock(&dev->struct_mutex);
307
c44ef60e 308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 309 count, total_obj_size, total_gtt_size);
310 return 0;
311}
312
6299f992
CW		 313#define count_objects(list, member) do { \
314 list_for_each_entry(obj, list, member) { \
ca1543be 315 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 316 ++count; \
317 if (obj->map_and_fenceable) { \
f343c5f6 318 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 319 ++mappable_count; \
320 } \
321 } \
0206e353 322} while (0)
6299f992 323
2db8e9d6 324struct file_stats {
6313c204 325 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 326 unsigned long count;
327 u64 total, unbound;
328 u64 global, shared;
329 u64 active, inactive;
2db8e9d6
CW		 330};
331
332static int per_file_stats(int id, void *ptr, void *data)
333{
334 struct drm_i915_gem_object *obj = ptr;
335 struct file_stats *stats = data;
6313c204 336 struct i915_vma *vma;
2db8e9d6
CW		 337
338 stats->count++;
339 stats->total += obj->base.size;
340
c67a17e9
CW		 341 if (obj->base.name || obj->base.dma_buf)
342 stats->shared += obj->base.size;
343
6313c204
CW		 344 if (USES_FULL_PPGTT(obj->base.dev)) {
345 list_for_each_entry(vma, &obj->vma_list, vma_link) {
346 struct i915_hw_ppgtt *ppgtt;
347
348 if (!drm_mm_node_allocated(&vma->node))
349 continue;
350
351 if (i915_is_ggtt(vma->vm)) {
352 stats->global += obj->base.size;
353 continue;
354 }
355
356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 357 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 358 continue;
359
41c52415 360 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 361 stats->active += obj->base.size;
362 else
363 stats->inactive += obj->base.size;
364
365 return 0;
366 }
2db8e9d6 367 } else {
6313c204
CW		 368 if (i915_gem_obj_ggtt_bound(obj)) {
369 stats->global += obj->base.size;
41c52415 370 if (obj->active)
6313c204
CW		 371 stats->active += obj->base.size;
372 else
373 stats->inactive += obj->base.size;
374 return 0;
375 }
2db8e9d6
CW		 376 }
377
6313c204
CW		 378 if (!list_empty(&obj->global_list))
379 stats->unbound += obj->base.size;
380
2db8e9d6
CW		 381 return 0;
382}
383
b0da1b79
CW		 384#define print_file_stats(m, name, stats) do { \
385 if (stats.count) \
c44ef60e 386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 387 name, \
388 stats.count, \
389 stats.total, \
390 stats.active, \
391 stats.inactive, \
392 stats.global, \
393 stats.shared, \
394 stats.unbound); \
395} while (0)
493018dc
BV		 396
397static void print_batch_pool_stats(struct seq_file *m,
398 struct drm_i915_private *dev_priv)
399{
400 struct drm_i915_gem_object *obj;
401 struct file_stats stats;
06fbca71 402 struct intel_engine_cs *ring;
8d9d5744 403 int i, j;
493018dc
BV		 404
405 memset(&stats, 0, sizeof(stats));
406
06fbca71 407 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 408 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
409 list_for_each_entry(obj,
410 &ring->batch_pool.cache_list[j],
411 batch_pool_link)
412 per_file_stats(0, obj, &stats);
413 }
06fbca71 414 }
493018dc 415
b0da1b79 416 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 417}
418
ca191b13
BW		 419#define count_vmas(list, member) do { \
420 list_for_each_entry(vma, list, member) { \
ca1543be 421 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 422 ++count; \
423 if (vma->obj->map_and_fenceable) { \
424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
425 ++mappable_count; \
426 } \
427 } \
428} while (0)
429
430static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 431{
9f25d007 432 struct drm_info_node *node = m->private;
73aa808f
CW		 433 struct drm_device *dev = node->minor->dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714 435 u32 count, mappable_count, purgeable_count;
c44ef60e 436 u64 size, mappable_size, purgeable_size;
6299f992 437 struct drm_i915_gem_object *obj;
5cef07e1 438 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 439 struct drm_file *file;
ca191b13 440 struct i915_vma *vma;
73aa808f
CW		 441 int ret;
442
443 ret = mutex_lock_interruptible(&dev->struct_mutex);
444 if (ret)
445 return ret;
446
6299f992
CW		 447 seq_printf(m, "%u objects, %zu bytes\n",
448 dev_priv->mm.object_count,
449 dev_priv->mm.object_memory);
450
451 size = count = mappable_size = mappable_count = 0;
35c20a60 452 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 454 count, mappable_count, size, mappable_size);
455
456 size = count = mappable_size = mappable_count = 0;
ca191b13 457 count_vmas(&vm->active_list, mm_list);
c44ef60e 458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 459 count, mappable_count, size, mappable_size);
460
6299f992 461 size = count = mappable_size = mappable_count = 0;
ca191b13 462 count_vmas(&vm->inactive_list, mm_list);
c44ef60e 463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 464 count, mappable_count, size, mappable_size);
465
b7abb714 466 size = count = purgeable_size = purgeable_count = 0;
35c20a60 467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 468 size += obj->base.size, ++count;
b7abb714
CW		 469 if (obj->madv == I915_MADV_DONTNEED)
470 purgeable_size += obj->base.size, ++purgeable_count;
471 }
c44ef60e 472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 473
6299f992 474 size = count = mappable_size = mappable_count = 0;
35c20a60 475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 476 if (obj->fault_mappable) {
f343c5f6 477 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 478 ++count;
479 }
30154650 480 if (obj->pin_display) {
f343c5f6 481 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 482 ++mappable_count;
483 }
b7abb714
CW		 484 if (obj->madv == I915_MADV_DONTNEED) {
485 purgeable_size += obj->base.size;
486 ++purgeable_count;
487 }
6299f992 488 }
c44ef60e 489 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 490 purgeable_count, purgeable_size);
c44ef60e 491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 492 mappable_count, mappable_size);
c44ef60e 493 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992
CW		 494 count, size);
495
c44ef60e 496 seq_printf(m, "%llu [%llu] gtt total\n",
853ba5d2 497 dev_priv->gtt.base.total,
c44ef60e 498 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 499
493018dc
BV		 500 seq_putc(m, '\n');
501 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 502 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
503 struct file_stats stats;
3ec2f427 504 struct task_struct *task;
2db8e9d6
CW		 505
506 memset(&stats, 0, sizeof(stats));
6313c204 507 stats.file_priv = file->driver_priv;
5b5ffff0 508 spin_lock(&file->table_lock);
2db8e9d6 509 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 510 spin_unlock(&file->table_lock);
3ec2f427
TH		 511 /*
512 * Although we have a valid reference on file->pid, that does
513 * not guarantee that the task_struct who called get_pid() is
514 * still alive (e.g. get_pid(current) => fork() => exit()).
515 * Therefore, we need to protect this ->comm access using RCU.
516 */
517 rcu_read_lock();
518 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 519 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 520 rcu_read_unlock();
2db8e9d6
CW		 521 }
522
73aa808f
CW		 523 mutex_unlock(&dev->struct_mutex);
524
525 return 0;
526}
527
aee56cff 528static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 529{
9f25d007 530 struct drm_info_node *node = m->private;
08c18323 531 struct drm_device *dev = node->minor->dev;
1b50247a 532 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 533 struct drm_i915_private *dev_priv = dev->dev_private;
534 struct drm_i915_gem_object *obj;
c44ef60e 535 u64 total_obj_size, total_gtt_size;
08c18323
CW		 536 int count, ret;
537
538 ret = mutex_lock_interruptible(&dev->struct_mutex);
539 if (ret)
540 return ret;
541
542 total_obj_size = total_gtt_size = count = 0;
35c20a60 543 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 544 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 545 continue;
546
267f0c90 547 seq_puts(m, " ");
08c18323 548 describe_obj(m, obj);
267f0c90 549 seq_putc(m, '\n');
08c18323 550 total_obj_size += obj->base.size;
ca1543be 551 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 552 count++;
553 }
554
555 mutex_unlock(&dev->struct_mutex);
556
c44ef60e 557 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 558 count, total_obj_size, total_gtt_size);
559
560 return 0;
561}
562
4e5359cd
SF		 563static int i915_gem_pageflip_info(struct seq_file *m, void *data)
564{
9f25d007 565 struct drm_info_node *node = m->private;
4e5359cd 566 struct drm_device *dev = node->minor->dev;
d6bbafa1 567 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 568 struct intel_crtc *crtc;
8a270ebf
DV		 569 int ret;
570
571 ret = mutex_lock_interruptible(&dev->struct_mutex);
572 if (ret)
573 return ret;
4e5359cd 574
d3fcc808 575 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 576 const char pipe = pipe_name(crtc->pipe);
577 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 578 struct intel_unpin_work *work;
579
5e2d7afc 580 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 581 work = crtc->unpin_work;
582 if (work == NULL) {
9db4a9c7 583 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 584 pipe, plane);
585 } else {
d6bbafa1
CW		 586 u32 addr;
587
e7d841ca 588 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 589 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 590 pipe, plane);
591 } else {
9db4a9c7 592 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 593 pipe, plane);
594 }
3a8a946e
DV		 595 if (work->flip_queued_req) {
596 struct intel_engine_cs *ring =
597 i915_gem_request_get_ring(work->flip_queued_req);
598
20e28fba 599 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 600 ring->name,
f06cc1b9 601 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 602 dev_priv->next_seqno,
3a8a946e 603 ring->get_seqno(ring, true),
1b5a433a 604 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 605 } else
606 seq_printf(m, "Flip not associated with any ring\n");
607 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
608 work->flip_queued_vblank,
609 work->flip_ready_vblank,
1e3feefd 610 drm_crtc_vblank_count(&crtc->base));
4e5359cd 611 if (work->enable_stall_check)
267f0c90 612 seq_puts(m, "Stall check enabled, ");
4e5359cd 613 else
267f0c90 614 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 615 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 616
d6bbafa1
CW		 617 if (INTEL_INFO(dev)->gen >= 4)
618 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
619 else
620 addr = I915_READ(DSPADDR(crtc->plane));
621 seq_printf(m, "Current scanout address 0x%08x\n", addr);
622
4e5359cd 623 if (work->pending_flip_obj) {
d6bbafa1
CW		 624 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
625 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 626 }
627 }
5e2d7afc 628 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 629 }
630
8a270ebf
DV		 631 mutex_unlock(&dev->struct_mutex);
632
4e5359cd
SF		 633 return 0;
634}
635
493018dc
BV		 636static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
637{
638 struct drm_info_node *node = m->private;
639 struct drm_device *dev = node->minor->dev;
640 struct drm_i915_private *dev_priv = dev->dev_private;
641 struct drm_i915_gem_object *obj;
06fbca71 642 struct intel_engine_cs *ring;
8d9d5744
CW		 643 int total = 0;
644 int ret, i, j;
493018dc
BV		 645
646 ret = mutex_lock_interruptible(&dev->struct_mutex);
647 if (ret)
648 return ret;
649
06fbca71 650 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 651 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
652 int count;
653
654 count = 0;
655 list_for_each_entry(obj,
656 &ring->batch_pool.cache_list[j],
657 batch_pool_link)
658 count++;
659 seq_printf(m, "%s cache[%d]: %d objects\n",
660 ring->name, j, count);
661
662 list_for_each_entry(obj,
663 &ring->batch_pool.cache_list[j],
664 batch_pool_link) {
665 seq_puts(m, " ");
666 describe_obj(m, obj);
667 seq_putc(m, '\n');
668 }
669
670 total += count;
06fbca71 671 }
493018dc
BV		 672 }
673
8d9d5744 674 seq_printf(m, "total: %d\n", total);
493018dc
BV		 675
676 mutex_unlock(&dev->struct_mutex);
677
678 return 0;
679}
680
2017263e
BG		 681static int i915_gem_request_info(struct seq_file *m, void *data)
682{
9f25d007 683 struct drm_info_node *node = m->private;
2017263e 684 struct drm_device *dev = node->minor->dev;
e277a1f8 685 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 686 struct intel_engine_cs *ring;
eed29a5b 687 struct drm_i915_gem_request *req;
2d1070b2 688 int ret, any, i;
de227ef0
CW		 689
690 ret = mutex_lock_interruptible(&dev->struct_mutex);
691 if (ret)
692 return ret;
2017263e 693
2d1070b2 694 any = 0;
a2c7f6fd 695 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 696 int count;
697
698 count = 0;
eed29a5b 699 list_for_each_entry(req, &ring->request_list, list)
2d1070b2
CW		 700 count++;
701 if (count == 0)
a2c7f6fd
CW		 702 continue;
703
2d1070b2 704 seq_printf(m, "%s requests: %d\n", ring->name, count);
eed29a5b 705 list_for_each_entry(req, &ring->request_list, list) {
2d1070b2
CW		 706 struct task_struct *task;
707
708 rcu_read_lock();
709 task = NULL;
eed29a5b
DV		 710 if (req->pid)
711 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 712 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 713 req->seqno,
714 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 715 task ? task->comm : "<unknown>",
716 task ? task->pid : -1);
717 rcu_read_unlock();
c2c347a9 718 }
2d1070b2
CW		 719
720 any++;
2017263e 721 }
de227ef0
CW		 722 mutex_unlock(&dev->struct_mutex);
723
2d1070b2 724 if (any == 0)
267f0c90 725 seq_puts(m, "No requests\n");
c2c347a9 726
2017263e
BG		 727 return 0;
728}
729
b2223497 730static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 731 struct intel_engine_cs *ring)
b2223497
CW		 732{
733 if (ring->get_seqno) {
20e28fba 734 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 735 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 736 }
737}
738
2017263e
BG		 739static int i915_gem_seqno_info(struct seq_file *m, void *data)
740{
9f25d007 741 struct drm_info_node *node = m->private;
2017263e 742 struct drm_device *dev = node->minor->dev;
e277a1f8 743 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 744 struct intel_engine_cs *ring;
1ec14ad3 745 int ret, i;
de227ef0
CW		 746
747 ret = mutex_lock_interruptible(&dev->struct_mutex);
748 if (ret)
749 return ret;
c8c8fb33 750 intel_runtime_pm_get(dev_priv);
2017263e 751
a2c7f6fd
CW		 752 for_each_ring(ring, dev_priv, i)
753 i915_ring_seqno_info(m, ring);
de227ef0 754
c8c8fb33 755 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 756 mutex_unlock(&dev->struct_mutex);
757
2017263e
BG		 758 return 0;
759}
760
761
762static int i915_interrupt_info(struct seq_file *m, void *data)
763{
9f25d007 764 struct drm_info_node *node = m->private;
2017263e 765 struct drm_device *dev = node->minor->dev;
e277a1f8 766 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 767 struct intel_engine_cs *ring;
9db4a9c7 768 int ret, i, pipe;
de227ef0
CW		 769
770 ret = mutex_lock_interruptible(&dev->struct_mutex);
771 if (ret)
772 return ret;
c8c8fb33 773 intel_runtime_pm_get(dev_priv);
2017263e 774
74e1ca8c 775 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 776 seq_printf(m, "Master Interrupt Control:\t%08x\n",
777 I915_READ(GEN8_MASTER_IRQ));
778
779 seq_printf(m, "Display IER:\t%08x\n",
780 I915_READ(VLV_IER));
781 seq_printf(m, "Display IIR:\t%08x\n",
782 I915_READ(VLV_IIR));
783 seq_printf(m, "Display IIR_RW:\t%08x\n",
784 I915_READ(VLV_IIR_RW));
785 seq_printf(m, "Display IMR:\t%08x\n",
786 I915_READ(VLV_IMR));
055e393f 787 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 788 seq_printf(m, "Pipe %c stat:\t%08x\n",
789 pipe_name(pipe),
790 I915_READ(PIPESTAT(pipe)));
791
792 seq_printf(m, "Port hotplug:\t%08x\n",
793 I915_READ(PORT_HOTPLUG_EN));
794 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
795 I915_READ(VLV_DPFLIPSTAT));
796 seq_printf(m, "DPINVGTT:\t%08x\n",
797 I915_READ(DPINVGTT));
798
799 for (i = 0; i < 4; i++) {
800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IMR(i)));
802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IIR(i)));
804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
805 i, I915_READ(GEN8_GT_IER(i)));
806 }
807
808 seq_printf(m, "PCU interrupt mask:\t%08x\n",
809 I915_READ(GEN8_PCU_IMR));
810 seq_printf(m, "PCU interrupt identity:\t%08x\n",
811 I915_READ(GEN8_PCU_IIR));
812 seq_printf(m, "PCU interrupt enable:\t%08x\n",
813 I915_READ(GEN8_PCU_IER));
814 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 815 seq_printf(m, "Master Interrupt Control:\t%08x\n",
816 I915_READ(GEN8_MASTER_IRQ));
817
818 for (i = 0; i < 4; i++) {
819 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IMR(i)));
821 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IIR(i)));
823 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
824 i, I915_READ(GEN8_GT_IER(i)));
825 }
826
055e393f 827 for_each_pipe(dev_priv, pipe) {
f458ebbc 828 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 829 POWER_DOMAIN_PIPE(pipe))) {
830 seq_printf(m, "Pipe %c power disabled\n",
831 pipe_name(pipe));
832 continue;
833 }
a123f157 834 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 835 pipe_name(pipe),
836 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 837 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 838 pipe_name(pipe),
839 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 840 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 841 pipe_name(pipe),
842 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 843 }
844
845 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
846 I915_READ(GEN8_DE_PORT_IMR));
847 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
848 I915_READ(GEN8_DE_PORT_IIR));
849 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
850 I915_READ(GEN8_DE_PORT_IER));
851
852 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
853 I915_READ(GEN8_DE_MISC_IMR));
854 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
855 I915_READ(GEN8_DE_MISC_IIR));
856 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
857 I915_READ(GEN8_DE_MISC_IER));
858
859 seq_printf(m, "PCU interrupt mask:\t%08x\n",
860 I915_READ(GEN8_PCU_IMR));
861 seq_printf(m, "PCU interrupt identity:\t%08x\n",
862 I915_READ(GEN8_PCU_IIR));
863 seq_printf(m, "PCU interrupt enable:\t%08x\n",
864 I915_READ(GEN8_PCU_IER));
865 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 866 seq_printf(m, "Display IER:\t%08x\n",
867 I915_READ(VLV_IER));
868 seq_printf(m, "Display IIR:\t%08x\n",
869 I915_READ(VLV_IIR));
870 seq_printf(m, "Display IIR_RW:\t%08x\n",
871 I915_READ(VLV_IIR_RW));
872 seq_printf(m, "Display IMR:\t%08x\n",
873 I915_READ(VLV_IMR));
055e393f 874 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 875 seq_printf(m, "Pipe %c stat:\t%08x\n",
876 pipe_name(pipe),
877 I915_READ(PIPESTAT(pipe)));
878
879 seq_printf(m, "Master IER:\t%08x\n",
880 I915_READ(VLV_MASTER_IER));
881
882 seq_printf(m, "Render IER:\t%08x\n",
883 I915_READ(GTIER));
884 seq_printf(m, "Render IIR:\t%08x\n",
885 I915_READ(GTIIR));
886 seq_printf(m, "Render IMR:\t%08x\n",
887 I915_READ(GTIMR));
888
889 seq_printf(m, "PM IER:\t\t%08x\n",
890 I915_READ(GEN6_PMIER));
891 seq_printf(m, "PM IIR:\t\t%08x\n",
892 I915_READ(GEN6_PMIIR));
893 seq_printf(m, "PM IMR:\t\t%08x\n",
894 I915_READ(GEN6_PMIMR));
895
896 seq_printf(m, "Port hotplug:\t%08x\n",
897 I915_READ(PORT_HOTPLUG_EN));
898 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
899 I915_READ(VLV_DPFLIPSTAT));
900 seq_printf(m, "DPINVGTT:\t%08x\n",
901 I915_READ(DPINVGTT));
902
903 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 904 seq_printf(m, "Interrupt enable: %08x\n",
905 I915_READ(IER));
906 seq_printf(m, "Interrupt identity: %08x\n",
907 I915_READ(IIR));
908 seq_printf(m, "Interrupt mask: %08x\n",
909 I915_READ(IMR));
055e393f 910 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 911 seq_printf(m, "Pipe %c stat: %08x\n",
912 pipe_name(pipe),
913 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 914 } else {
915 seq_printf(m, "North Display Interrupt enable: %08x\n",
916 I915_READ(DEIER));
917 seq_printf(m, "North Display Interrupt identity: %08x\n",
918 I915_READ(DEIIR));
919 seq_printf(m, "North Display Interrupt mask: %08x\n",
920 I915_READ(DEIMR));
921 seq_printf(m, "South Display Interrupt enable: %08x\n",
922 I915_READ(SDEIER));
923 seq_printf(m, "South Display Interrupt identity: %08x\n",
924 I915_READ(SDEIIR));
925 seq_printf(m, "South Display Interrupt mask: %08x\n",
926 I915_READ(SDEIMR));
927 seq_printf(m, "Graphics Interrupt enable: %08x\n",
928 I915_READ(GTIER));
929 seq_printf(m, "Graphics Interrupt identity: %08x\n",
930 I915_READ(GTIIR));
931 seq_printf(m, "Graphics Interrupt mask: %08x\n",
932 I915_READ(GTIMR));
933 }
a2c7f6fd 934 for_each_ring(ring, dev_priv, i) {
a123f157 935 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 936 seq_printf(m,
937 "Graphics Interrupt mask (%s): %08x\n",
938 ring->name, I915_READ_IMR(ring));
9862e600 939 }
a2c7f6fd 940 i915_ring_seqno_info(m, ring);
9862e600 941 }
c8c8fb33 942 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 943 mutex_unlock(&dev->struct_mutex);
944
2017263e
BG		 945 return 0;
946}
947
a6172a80
CW		 948static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
949{
9f25d007 950 struct drm_info_node *node = m->private;
a6172a80 951 struct drm_device *dev = node->minor->dev;
e277a1f8 952 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 953 int i, ret;
954
955 ret = mutex_lock_interruptible(&dev->struct_mutex);
956 if (ret)
957 return ret;
a6172a80
CW		 958
959 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
960 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
961 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 962 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 963
6c085a72
CW		 964 seq_printf(m, "Fence %d, pin count = %d, object = ",
965 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 966 if (obj == NULL)
267f0c90 967 seq_puts(m, "unused");
c2c347a9 968 else
05394f39 969 describe_obj(m, obj);
267f0c90 970 seq_putc(m, '\n');
a6172a80
CW		 971 }
972
05394f39 973 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 974 return 0;
975}
976
2017263e
BG		 977static int i915_hws_info(struct seq_file *m, void *data)
978{
9f25d007 979 struct drm_info_node *node = m->private;
2017263e 980 struct drm_device *dev = node->minor->dev;
e277a1f8 981 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 982 struct intel_engine_cs *ring;
1a240d4d 983 const u32 *hws;
4066c0ae
CW		 984 int i;
985
1ec14ad3 986 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 987 hws = ring->status_page.page_addr;
2017263e
BG		 988 if (hws == NULL)
989 return 0;
990
991 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
992 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
993 i * 4,
994 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
995 }
996 return 0;
997}
998
d5442303
DV		 999static ssize_t
1000i915_error_state_write(struct file *filp,
1001 const char __user *ubuf,
1002 size_t cnt,
1003 loff_t *ppos)
1004{
edc3d884 1005 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1006 struct drm_device *dev = error_priv->dev;
22bcfc6a 1007 int ret;
d5442303
DV		 1008
1009 DRM_DEBUG_DRIVER("Resetting error state\n");
1010
22bcfc6a
DV		 1011 ret = mutex_lock_interruptible(&dev->struct_mutex);
1012 if (ret)
1013 return ret;
1014
d5442303
DV		 1015 i915_destroy_error_state(dev);
1016 mutex_unlock(&dev->struct_mutex);
1017
1018 return cnt;
1019}
1020
1021static int i915_error_state_open(struct inode *inode, struct file *file)
1022{
1023 struct drm_device *dev = inode->i_private;
d5442303 1024 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1025
1026 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1027 if (!error_priv)
1028 return -ENOMEM;
1029
1030 error_priv->dev = dev;
1031
95d5bfb3 1032 i915_error_state_get(dev, error_priv);
d5442303 1033
edc3d884
MK		 1034 file->private_data = error_priv;
1035
1036 return 0;
d5442303
DV		 1037}
1038
1039static int i915_error_state_release(struct inode *inode, struct file *file)
1040{
edc3d884 1041 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1042
95d5bfb3 1043 i915_error_state_put(error_priv);
d5442303
DV		 1044 kfree(error_priv);
1045
edc3d884
MK		 1046 return 0;
1047}
1048
4dc955f7
MK		 1049static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1050 size_t count, loff_t *pos)
1051{
1052 struct i915_error_state_file_priv *error_priv = file->private_data;
1053 struct drm_i915_error_state_buf error_str;
1054 loff_t tmp_pos = 0;
1055 ssize_t ret_count = 0;
1056 int ret;
1057
0a4cd7c8 1058 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1059 if (ret)
1060 return ret;
edc3d884 1061
fc16b48b 1062 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1063 if (ret)
1064 goto out;
1065
edc3d884
MK		 1066 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1067 error_str.buf,
1068 error_str.bytes);
1069
1070 if (ret_count < 0)
1071 ret = ret_count;
1072 else
1073 *pos = error_str.start + ret_count;
1074out:
4dc955f7 1075 i915_error_state_buf_release(&error_str);
edc3d884 1076 return ret ?: ret_count;
d5442303
DV		 1077}
1078
1079static const struct file_operations i915_error_state_fops = {
1080 .owner = THIS_MODULE,
1081 .open = i915_error_state_open,
edc3d884 1082 .read = i915_error_state_read,
d5442303
DV		 1083 .write = i915_error_state_write,
1084 .llseek = default_llseek,
1085 .release = i915_error_state_release,
1086};
1087
647416f9
KC		 1088static int
1089i915_next_seqno_get(void *data, u64 *val)
40633219 1090{
647416f9 1091 struct drm_device *dev = data;
e277a1f8 1092 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1093 int ret;
1094
1095 ret = mutex_lock_interruptible(&dev->struct_mutex);
1096 if (ret)
1097 return ret;
1098
647416f9 1099 *val = dev_priv->next_seqno;
40633219
MK		 1100 mutex_unlock(&dev->struct_mutex);
1101
647416f9 1102 return 0;
40633219
MK		 1103}
1104
647416f9
KC		 1105static int
1106i915_next_seqno_set(void *data, u64 val)
1107{
1108 struct drm_device *dev = data;
40633219
MK		 1109 int ret;
1110
40633219
MK		 1111 ret = mutex_lock_interruptible(&dev->struct_mutex);
1112 if (ret)
1113 return ret;
1114
e94fbaa8 1115 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1116 mutex_unlock(&dev->struct_mutex);
1117
647416f9 1118 return ret;
40633219
MK		 1119}
1120
647416f9
KC		 1121DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1122 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1123 "0x%llx\n");
40633219 1124
adb4bd12 1125static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1126{
9f25d007 1127 struct drm_info_node *node = m->private;
f97108d1 1128 struct drm_device *dev = node->minor->dev;
e277a1f8 1129 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1130 int ret = 0;
1131
1132 intel_runtime_pm_get(dev_priv);
3b8d8d91 1133
5c9669ce
TR		 1134 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1135
3b8d8d91
JB		 1136 if (IS_GEN5(dev)) {
1137 u16 rgvswctl = I915_READ16(MEMSWCTL);
1138 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1139
1140 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1141 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1142 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1143 MEMSTAT_VID_SHIFT);
1144 seq_printf(m, "Current P-state: %d\n",
1145 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2 1146 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
60260a5b 1147 IS_BROADWELL(dev) || IS_GEN9(dev)) {
35040562
BP		 1148 u32 rp_state_limits;
1149 u32 gt_perf_status;
1150 u32 rp_state_cap;
0d8f9491 1151 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1152 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1153 u32 rpupei, rpcurup, rpprevup;
1154 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1155 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1156 int max_freq;
1157
35040562
BP		 1158 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1159 if (IS_BROXTON(dev)) {
1160 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1161 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1162 } else {
1163 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1164 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1165 }
1166
3b8d8d91 1167 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1168 ret = mutex_lock_interruptible(&dev->struct_mutex);
1169 if (ret)
c8c8fb33 1170 goto out;
d1ebd816 1171
59bad947 1172 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1173
8e8c06cd 1174 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1175 if (IS_GEN9(dev))
1176 reqf >>= 23;
1177 else {
1178 reqf &= ~GEN6_TURBO_DISABLE;
1179 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1180 reqf >>= 24;
1181 else
1182 reqf >>= 25;
1183 }
7c59a9c1 1184 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1185
0d8f9491
CW		 1186 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1187 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1188 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1189
ccab5c82
JB		 1190 rpstat = I915_READ(GEN6_RPSTAT1);
1191 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1192 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1193 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1194 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1195 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1196 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1197 if (IS_GEN9(dev))
1198 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1199 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1200 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1201 else
1202 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1203 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1204
59bad947 1205 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1206 mutex_unlock(&dev->struct_mutex);
1207
9dd3c605
PZ		 1208 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1209 pm_ier = I915_READ(GEN6_PMIER);
1210 pm_imr = I915_READ(GEN6_PMIMR);
1211 pm_isr = I915_READ(GEN6_PMISR);
1212 pm_iir = I915_READ(GEN6_PMIIR);
1213 pm_mask = I915_READ(GEN6_PMINTRMSK);
1214 } else {
1215 pm_ier = I915_READ(GEN8_GT_IER(2));
1216 pm_imr = I915_READ(GEN8_GT_IMR(2));
1217 pm_isr = I915_READ(GEN8_GT_ISR(2));
1218 pm_iir = I915_READ(GEN8_GT_IIR(2));
1219 pm_mask = I915_READ(GEN6_PMINTRMSK);
1220 }
0d8f9491 1221 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1222 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1223 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1224 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1225 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1226 seq_printf(m, "Render p-state VID: %d\n",
1227 gt_perf_status & 0xff);
1228 seq_printf(m, "Render p-state limit: %d\n",
1229 rp_state_limits & 0xff);
0d8f9491
CW		 1230 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1231 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1232 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1233 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1234 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1235 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1236 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1237 GEN6_CURICONT_MASK);
1238 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1239 GEN6_CURBSYTAVG_MASK);
1240 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1241 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1242 seq_printf(m, "Up threshold: %d%%\n",
1243 dev_priv->rps.up_threshold);
1244
ccab5c82
JB		 1245 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1246 GEN6_CURIAVG_MASK);
1247 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1248 GEN6_CURBSYTAVG_MASK);
1249 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1250 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1251 seq_printf(m, "Down threshold: %d%%\n",
1252 dev_priv->rps.down_threshold);
3b8d8d91 1253
35040562
BP		 1254 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1255 rp_state_cap >> 16) & 0xff;
ef11bdb3
RV		 1256 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1257 GEN9_FREQ_SCALER : 1);
3b8d8d91 1258 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1259 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1260
1261 max_freq = (rp_state_cap & 0xff00) >> 8;
ef11bdb3
RV		 1262 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1263 GEN9_FREQ_SCALER : 1);
3b8d8d91 1264 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1265 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1266
35040562
BP		 1267 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1268 rp_state_cap >> 0) & 0xff;
ef11bdb3
RV		 1269 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1270 GEN9_FREQ_SCALER : 1);
3b8d8d91 1271 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1272 intel_gpu_freq(dev_priv, max_freq));
31c77388 1273 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1274 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1275
d86ed34a
CW		 1276 seq_printf(m, "Current freq: %d MHz\n",
1277 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1278 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1279 seq_printf(m, "Idle freq: %d MHz\n",
1280 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1281 seq_printf(m, "Min freq: %d MHz\n",
1282 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1283 seq_printf(m, "Max freq: %d MHz\n",
1284 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1285 seq_printf(m,
1286 "efficient (RPe) frequency: %d MHz\n",
1287 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84 1288 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1289 u32 freq_sts;
0a073b84 1290
259bd5d4 1291 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1292 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1293 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1294 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1295
d86ed34a
CW		 1296 seq_printf(m, "actual GPU freq: %d MHz\n",
1297 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1298
1299 seq_printf(m, "current GPU freq: %d MHz\n",
1300 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1301
0a073b84 1302 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1303 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1304
0a073b84 1305 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1306 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1307
aed242ff
CW		 1308 seq_printf(m, "idle GPU freq: %d MHz\n",
1309 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1310
7c59a9c1
VS		 1311 seq_printf(m,
1312 "efficient (RPe) frequency: %d MHz\n",
1313 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
259bd5d4 1314 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1315 } else {
267f0c90 1316 seq_puts(m, "no P-state info available\n");
3b8d8d91 1317 }
f97108d1 1318
1170f28c
MK		 1319 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1320 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1321 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1322
c8c8fb33
PZ		 1323out:
1324 intel_runtime_pm_put(dev_priv);
1325 return ret;
f97108d1
JB		 1326}
1327
f654449a
CW		 1328static int i915_hangcheck_info(struct seq_file *m, void *unused)
1329{
1330 struct drm_info_node *node = m->private;
ebbc7546
MK		 1331 struct drm_device *dev = node->minor->dev;
1332 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1333 struct intel_engine_cs *ring;
ebbc7546
MK		 1334 u64 acthd[I915_NUM_RINGS];
1335 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1336 int i;
1337
1338 if (!i915.enable_hangcheck) {
1339 seq_printf(m, "Hangcheck disabled\n");
1340 return 0;
1341 }
1342
ebbc7546
MK		 1343 intel_runtime_pm_get(dev_priv);
1344
1345 for_each_ring(ring, dev_priv, i) {
1346 seqno[i] = ring->get_seqno(ring, false);
1347 acthd[i] = intel_ring_get_active_head(ring);
1348 }
1349
1350 intel_runtime_pm_put(dev_priv);
1351
f654449a
CW		 1352 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1353 seq_printf(m, "Hangcheck active, fires in %dms\n",
1354 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1355 jiffies));
1356 } else
1357 seq_printf(m, "Hangcheck inactive\n");
1358
1359 for_each_ring(ring, dev_priv, i) {
1360 seq_printf(m, "%s:\n", ring->name);
1361 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1362 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1363 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1364 (long long)ring->hangcheck.acthd,
ebbc7546 1365 (long long)acthd[i]);
f654449a
CW		 1366 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1367 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1368 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1369 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1370 }
1371
1372 return 0;
1373}
1374
4d85529d 1375static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1376{
9f25d007 1377 struct drm_info_node *node = m->private;
f97108d1 1378 struct drm_device *dev = node->minor->dev;
e277a1f8 1379 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1380 u32 rgvmodectl, rstdbyctl;
1381 u16 crstandvid;
1382 int ret;
1383
1384 ret = mutex_lock_interruptible(&dev->struct_mutex);
1385 if (ret)
1386 return ret;
c8c8fb33 1387 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1388
1389 rgvmodectl = I915_READ(MEMMODECTL);
1390 rstdbyctl = I915_READ(RSTDBYCTL);
1391 crstandvid = I915_READ16(CRSTANDVID);
1392
c8c8fb33 1393 intel_runtime_pm_put(dev_priv);
616fdb5a 1394 mutex_unlock(&dev->struct_mutex);
f97108d1 1395
742f491d 1396 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
f97108d1
JB		 1397 seq_printf(m, "Boost freq: %d\n",
1398 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1399 MEMMODE_BOOST_FREQ_SHIFT);
1400 seq_printf(m, "HW control enabled: %s\n",
742f491d 1401 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
f97108d1 1402 seq_printf(m, "SW control enabled: %s\n",
742f491d 1403 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
f97108d1 1404 seq_printf(m, "Gated voltage change: %s\n",
742f491d 1405 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
f97108d1
JB		 1406 seq_printf(m, "Starting frequency: P%d\n",
1407 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1408 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1409 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1410 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1411 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1412 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1413 seq_printf(m, "Render standby enabled: %s\n",
742f491d 1414 yesno(!(rstdbyctl & RCX_SW_EXIT)));
267f0c90 1415 seq_puts(m, "Current RS state: ");
88271da3
JB		 1416 switch (rstdbyctl & RSX_STATUS_MASK) {
1417 case RSX_STATUS_ON:
267f0c90 1418 seq_puts(m, "on\n");
88271da3
JB		 1419 break;
1420 case RSX_STATUS_RC1:
267f0c90 1421 seq_puts(m, "RC1\n");
88271da3
JB		 1422 break;
1423 case RSX_STATUS_RC1E:
267f0c90 1424 seq_puts(m, "RC1E\n");
88271da3
JB		 1425 break;
1426 case RSX_STATUS_RS1:
267f0c90 1427 seq_puts(m, "RS1\n");
88271da3
JB		 1428 break;
1429 case RSX_STATUS_RS2:
267f0c90 1430 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1431 break;
1432 case RSX_STATUS_RS3:
267f0c90 1433 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1434 break;
1435 default:
267f0c90 1436 seq_puts(m, "unknown\n");
88271da3
JB		 1437 break;
1438 }
f97108d1
JB		 1439
1440 return 0;
1441}
1442
f65367b5 1443static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1444{
b2cff0db
CW		 1445 struct drm_info_node *node = m->private;
1446 struct drm_device *dev = node->minor->dev;
1447 struct drm_i915_private *dev_priv = dev->dev_private;
1448 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1449 int i;
1450
1451 spin_lock_irq(&dev_priv->uncore.lock);
1452 for_each_fw_domain(fw_domain, dev_priv, i) {
1453 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1454 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1455 fw_domain->wake_count);
1456 }
1457 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1458
b2cff0db
CW		 1459 return 0;
1460}
1461
1462static int vlv_drpc_info(struct seq_file *m)
1463{
9f25d007 1464 struct drm_info_node *node = m->private;
669ab5aa
D		 1465 struct drm_device *dev = node->minor->dev;
1466 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1467 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1468
d46c0517
ID		 1469 intel_runtime_pm_get(dev_priv);
1470
6b312cd3 1471 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1472 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1473 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1474
d46c0517
ID		 1475 intel_runtime_pm_put(dev_priv);
1476
669ab5aa
D		 1477 seq_printf(m, "Video Turbo Mode: %s\n",
1478 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1479 seq_printf(m, "Turbo enabled: %s\n",
1480 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1481 seq_printf(m, "HW control enabled: %s\n",
1482 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1483 seq_printf(m, "SW control enabled: %s\n",
1484 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1485 GEN6_RP_MEDIA_SW_MODE));
1486 seq_printf(m, "RC6 Enabled: %s\n",
1487 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1488 GEN6_RC_CTL_EI_MODE(1))));
1489 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1490 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1491 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1492 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1493
9cc19be5
ID		 1494 seq_printf(m, "Render RC6 residency since boot: %u\n",
1495 I915_READ(VLV_GT_RENDER_RC6));
1496 seq_printf(m, "Media RC6 residency since boot: %u\n",
1497 I915_READ(VLV_GT_MEDIA_RC6));
1498
f65367b5 1499 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1500}
1501
4d85529d
BW		 1502static int gen6_drpc_info(struct seq_file *m)
1503{
9f25d007 1504 struct drm_info_node *node = m->private;
4d85529d
BW		 1505 struct drm_device *dev = node->minor->dev;
1506 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1507 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1508 unsigned forcewake_count;
aee56cff 1509 int count = 0, ret;
4d85529d
BW		 1510
1511 ret = mutex_lock_interruptible(&dev->struct_mutex);
1512 if (ret)
1513 return ret;
c8c8fb33 1514 intel_runtime_pm_get(dev_priv);
4d85529d 1515
907b28c5 1516 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1517 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1518 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1519
1520 if (forcewake_count) {
267f0c90
DL		 1521 seq_puts(m, "RC information inaccurate because somebody "
1522 "holds a forcewake reference \n");
4d85529d
BW		 1523 } else {
1524 /* NB: we cannot use forcewake, else we read the wrong values */
1525 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1526 udelay(10);
1527 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1528 }
1529
75aa3f63 1530 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
ed71f1b4 1531 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1532
1533 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1534 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1535 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1536 mutex_lock(&dev_priv->rps.hw_lock);
1537 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1538 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1539
c8c8fb33
PZ		 1540 intel_runtime_pm_put(dev_priv);
1541
4d85529d
BW		 1542 seq_printf(m, "Video Turbo Mode: %s\n",
1543 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1544 seq_printf(m, "HW control enabled: %s\n",
1545 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1546 seq_printf(m, "SW control enabled: %s\n",
1547 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1548 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1549 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1550 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1551 seq_printf(m, "RC6 Enabled: %s\n",
1552 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1553 seq_printf(m, "Deep RC6 Enabled: %s\n",
1554 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1555 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1556 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1557 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1558 switch (gt_core_status & GEN6_RCn_MASK) {
1559 case GEN6_RC0:
1560 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1561 seq_puts(m, "Core Power Down\n");
4d85529d 1562 else
267f0c90 1563 seq_puts(m, "on\n");
4d85529d
BW		 1564 break;
1565 case GEN6_RC3:
267f0c90 1566 seq_puts(m, "RC3\n");
4d85529d
BW		 1567 break;
1568 case GEN6_RC6:
267f0c90 1569 seq_puts(m, "RC6\n");
4d85529d
BW		 1570 break;
1571 case GEN6_RC7:
267f0c90 1572 seq_puts(m, "RC7\n");
4d85529d
BW		 1573 break;
1574 default:
267f0c90 1575 seq_puts(m, "Unknown\n");
4d85529d
BW		 1576 break;
1577 }
1578
1579 seq_printf(m, "Core Power Down: %s\n",
1580 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1581
1582 /* Not exactly sure what this is */
1583 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1584 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1585 seq_printf(m, "RC6 residency since boot: %u\n",
1586 I915_READ(GEN6_GT_GFX_RC6));
1587 seq_printf(m, "RC6+ residency since boot: %u\n",
1588 I915_READ(GEN6_GT_GFX_RC6p));
1589 seq_printf(m, "RC6++ residency since boot: %u\n",
1590 I915_READ(GEN6_GT_GFX_RC6pp));
1591
ecd8faea
BW		 1592 seq_printf(m, "RC6 voltage: %dmV\n",
1593 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1594 seq_printf(m, "RC6+ voltage: %dmV\n",
1595 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1596 seq_printf(m, "RC6++ voltage: %dmV\n",
1597 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1598 return 0;
1599}
1600
1601static int i915_drpc_info(struct seq_file *m, void *unused)
1602{
9f25d007 1603 struct drm_info_node *node = m->private;
4d85529d
BW		 1604 struct drm_device *dev = node->minor->dev;
1605
669ab5aa
D		 1606 if (IS_VALLEYVIEW(dev))
1607 return vlv_drpc_info(m);
ac66cf4b 1608 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1609 return gen6_drpc_info(m);
1610 else
1611 return ironlake_drpc_info(m);
1612}
1613
9a851789
DV		 1614static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1615{
1616 struct drm_info_node *node = m->private;
1617 struct drm_device *dev = node->minor->dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619
1620 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1621 dev_priv->fb_tracking.busy_bits);
1622
1623 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1624 dev_priv->fb_tracking.flip_bits);
1625
1626 return 0;
1627}
1628
b5e50c3f
JB		 1629static int i915_fbc_status(struct seq_file *m, void *unused)
1630{
9f25d007 1631 struct drm_info_node *node = m->private;
b5e50c3f 1632 struct drm_device *dev = node->minor->dev;
e277a1f8 1633 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1634
3a77c4c4 1635 if (!HAS_FBC(dev)) {
267f0c90 1636 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1637 return 0;
1638 }
1639
36623ef8 1640 intel_runtime_pm_get(dev_priv);
25ad93fd 1641 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1642
7733b49b 1643 if (intel_fbc_enabled(dev_priv))
267f0c90 1644 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1645 else
1646 seq_printf(m, "FBC disabled: %s\n",
bf6189c6 1647 dev_priv->fbc.no_fbc_reason);
36623ef8 1648
31b9df10
PZ		 1649 if (INTEL_INFO(dev_priv)->gen >= 7)
1650 seq_printf(m, "Compressing: %s\n",
1651 yesno(I915_READ(FBC_STATUS2) &
1652 FBC_COMPRESSION_MASK));
1653
25ad93fd 1654 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1655 intel_runtime_pm_put(dev_priv);
1656
b5e50c3f
JB		 1657 return 0;
1658}
1659
da46f936
RV		 1660static int i915_fbc_fc_get(void *data, u64 *val)
1661{
1662 struct drm_device *dev = data;
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1666 return -ENODEV;
1667
da46f936 1668 *val = dev_priv->fbc.false_color;
da46f936
RV		 1669
1670 return 0;
1671}
1672
1673static int i915_fbc_fc_set(void *data, u64 val)
1674{
1675 struct drm_device *dev = data;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 u32 reg;
1678
1679 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1680 return -ENODEV;
1681
25ad93fd 1682 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1683
1684 reg = I915_READ(ILK_DPFC_CONTROL);
1685 dev_priv->fbc.false_color = val;
1686
1687 I915_WRITE(ILK_DPFC_CONTROL, val ?
1688 (reg | FBC_CTL_FALSE_COLOR) :
1689 (reg & ~FBC_CTL_FALSE_COLOR));
1690
25ad93fd 1691 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1692 return 0;
1693}
1694
1695DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1696 i915_fbc_fc_get, i915_fbc_fc_set,
1697 "%llu\n");
1698
92d44621
PZ		 1699static int i915_ips_status(struct seq_file *m, void *unused)
1700{
9f25d007 1701 struct drm_info_node *node = m->private;
92d44621
PZ		 1702 struct drm_device *dev = node->minor->dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704
f5adf94e 1705 if (!HAS_IPS(dev)) {
92d44621
PZ		 1706 seq_puts(m, "not supported\n");
1707 return 0;
1708 }
1709
36623ef8
PZ		 1710 intel_runtime_pm_get(dev_priv);
1711
0eaa53f0
RV		 1712 seq_printf(m, "Enabled by kernel parameter: %s\n",
1713 yesno(i915.enable_ips));
1714
1715 if (INTEL_INFO(dev)->gen >= 8) {
1716 seq_puts(m, "Currently: unknown\n");
1717 } else {
1718 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1719 seq_puts(m, "Currently: enabled\n");
1720 else
1721 seq_puts(m, "Currently: disabled\n");
1722 }
92d44621 1723
36623ef8
PZ		 1724 intel_runtime_pm_put(dev_priv);
1725
92d44621
PZ		 1726 return 0;
1727}
1728
4a9bef37
JB		 1729static int i915_sr_status(struct seq_file *m, void *unused)
1730{
9f25d007 1731 struct drm_info_node *node = m->private;
4a9bef37 1732 struct drm_device *dev = node->minor->dev;
e277a1f8 1733 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1734 bool sr_enabled = false;
1735
36623ef8
PZ		 1736 intel_runtime_pm_get(dev_priv);
1737
1398261a 1738 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1739 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1740 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1741 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1742 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1743 else if (IS_I915GM(dev))
1744 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1745 else if (IS_PINEVIEW(dev))
1746 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
77b64555
ACO		 1747 else if (IS_VALLEYVIEW(dev))
1748 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1749
36623ef8
PZ		 1750 intel_runtime_pm_put(dev_priv);
1751
5ba2aaaa
CW		 1752 seq_printf(m, "self-refresh: %s\n",
1753 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1754
1755 return 0;
1756}
1757
7648fa99
JB		 1758static int i915_emon_status(struct seq_file *m, void *unused)
1759{
9f25d007 1760 struct drm_info_node *node = m->private;
7648fa99 1761 struct drm_device *dev = node->minor->dev;
e277a1f8 1762 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1763 unsigned long temp, chipset, gfx;
de227ef0
CW		 1764 int ret;
1765
582be6b4
CW		 1766 if (!IS_GEN5(dev))
1767 return -ENODEV;
1768
de227ef0
CW		 1769 ret = mutex_lock_interruptible(&dev->struct_mutex);
1770 if (ret)
1771 return ret;
7648fa99
JB		 1772
1773 temp = i915_mch_val(dev_priv);
1774 chipset = i915_chipset_val(dev_priv);
1775 gfx = i915_gfx_val(dev_priv);
de227ef0 1776 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1777
1778 seq_printf(m, "GMCH temp: %ld\n", temp);
1779 seq_printf(m, "Chipset power: %ld\n", chipset);
1780 seq_printf(m, "GFX power: %ld\n", gfx);
1781 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1782
1783 return 0;
1784}
1785
23b2f8bb
JB		 1786static int i915_ring_freq_table(struct seq_file *m, void *unused)
1787{
9f25d007 1788 struct drm_info_node *node = m->private;
23b2f8bb 1789 struct drm_device *dev = node->minor->dev;
e277a1f8 1790 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1791 int ret = 0;
23b2f8bb 1792 int gpu_freq, ia_freq;
f936ec34 1793 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1794
97d3308a 1795 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1796 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1797 return 0;
1798 }
1799
5bfa0199
PZ		 1800 intel_runtime_pm_get(dev_priv);
1801
5c9669ce
TR		 1802 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1803
4fc688ce 1804 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1805 if (ret)
5bfa0199 1806 goto out;
23b2f8bb 1807
ef11bdb3 1808 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
f936ec34
AG		 1809 /* Convert GT frequency to 50 HZ units */
1810 min_gpu_freq =
1811 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1812 max_gpu_freq =
1813 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1814 } else {
1815 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1816 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1817 }
1818
267f0c90 1819 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1820
f936ec34 1821 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1822 ia_freq = gpu_freq;
1823 sandybridge_pcode_read(dev_priv,
1824 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1825 &ia_freq);
3ebecd07 1826 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34 1827 intel_gpu_freq(dev_priv, (gpu_freq *
ef11bdb3
RV		 1828 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1829 GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1830 ((ia_freq >> 0) & 0xff) * 100,
1831 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1832 }
1833
4fc688ce 1834 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1835
5bfa0199
PZ		 1836out:
1837 intel_runtime_pm_put(dev_priv);
1838 return ret;
23b2f8bb
JB		 1839}
1840
44834a67
CW		 1841static int i915_opregion(struct seq_file *m, void *unused)
1842{
9f25d007 1843 struct drm_info_node *node = m->private;
44834a67 1844 struct drm_device *dev = node->minor->dev;
e277a1f8 1845 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1846 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1847 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1848 int ret;
1849
0d38f009
DV		 1850 if (data == NULL)
1851 return -ENOMEM;
1852
44834a67
CW		 1853 ret = mutex_lock_interruptible(&dev->struct_mutex);
1854 if (ret)
0d38f009 1855 goto out;
44834a67 1856
0d38f009 1857 if (opregion->header) {
115719fc 1858 memcpy(data, opregion->header, OPREGION_SIZE);
0d38f009
DV		 1859 seq_write(m, data, OPREGION_SIZE);
1860 }
44834a67
CW		 1861
1862 mutex_unlock(&dev->struct_mutex);
1863
0d38f009
DV		 1864out:
1865 kfree(data);
44834a67
CW		 1866 return 0;
1867}
1868
37811fcc
CW		 1869static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1870{
9f25d007 1871 struct drm_info_node *node = m->private;
37811fcc 1872 struct drm_device *dev = node->minor->dev;
4520f53a 1873 struct intel_fbdev *ifbdev = NULL;
37811fcc 1874 struct intel_framebuffer *fb;
3a58ee10 1875 struct drm_framebuffer *drm_fb;
37811fcc 1876
0695726e 1877#ifdef CONFIG_DRM_FBDEV_EMULATION
4520f53a 1878 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1879
1880 ifbdev = dev_priv->fbdev;
1881 fb = to_intel_framebuffer(ifbdev->helper.fb);
1882
c1ca506d 1883 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1884 fb->base.width,
1885 fb->base.height,
1886 fb->base.depth,
623f9783 1887 fb->base.bits_per_pixel,
c1ca506d 1888 fb->base.modifier[0],
623f9783 1889 atomic_read(&fb->base.refcount.refcount));
05394f39 1890 describe_obj(m, fb->obj);
267f0c90 1891 seq_putc(m, '\n');
4520f53a 1892#endif
37811fcc 1893
4b096ac1 1894 mutex_lock(&dev->mode_config.fb_lock);
3a58ee10
DV		 1895 drm_for_each_fb(drm_fb, dev) {
1896 fb = to_intel_framebuffer(drm_fb);
131a56dc 1897 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1898 continue;
1899
c1ca506d 1900 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1901 fb->base.width,
1902 fb->base.height,
1903 fb->base.depth,
623f9783 1904 fb->base.bits_per_pixel,
c1ca506d 1905 fb->base.modifier[0],
623f9783 1906 atomic_read(&fb->base.refcount.refcount));
05394f39 1907 describe_obj(m, fb->obj);
267f0c90 1908 seq_putc(m, '\n');
37811fcc 1909 }
4b096ac1 1910 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1911
1912 return 0;
1913}
1914
c9fe99bd
OM		 1915static void describe_ctx_ringbuf(struct seq_file *m,
1916 struct intel_ringbuffer *ringbuf)
1917{
1918 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1919 ringbuf->space, ringbuf->head, ringbuf->tail,
1920 ringbuf->last_retired_head);
1921}
1922
e76d3630
BW		 1923static int i915_context_status(struct seq_file *m, void *unused)
1924{
9f25d007 1925 struct drm_info_node *node = m->private;
e76d3630 1926 struct drm_device *dev = node->minor->dev;
e277a1f8 1927 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1928 struct intel_engine_cs *ring;
273497e5 1929 struct intel_context *ctx;
a168c293 1930 int ret, i;
e76d3630 1931
f3d28878 1932 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1933 if (ret)
1934 return ret;
1935
a33afea5 1936 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1937 if (!i915.enable_execlists &&
1938 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1939 continue;
1940
a33afea5 1941 seq_puts(m, "HW context ");
3ccfd19d 1942 describe_ctx(m, ctx);
c9fe99bd 1943 for_each_ring(ring, dev_priv, i) {
a33afea5 1944 if (ring->default_context == ctx)
c9fe99bd
OM		 1945 seq_printf(m, "(default context %s) ",
1946 ring->name);
1947 }
1948
1949 if (i915.enable_execlists) {
1950 seq_putc(m, '\n');
1951 for_each_ring(ring, dev_priv, i) {
1952 struct drm_i915_gem_object *ctx_obj =
1953 ctx->engine[i].state;
1954 struct intel_ringbuffer *ringbuf =
1955 ctx->engine[i].ringbuf;
1956
1957 seq_printf(m, "%s: ", ring->name);
1958 if (ctx_obj)
1959 describe_obj(m, ctx_obj);
1960 if (ringbuf)
1961 describe_ctx_ringbuf(m, ringbuf);
1962 seq_putc(m, '\n');
1963 }
1964 } else {
1965 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1966 }
a33afea5 1967
a33afea5 1968 seq_putc(m, '\n');
a168c293
BW		 1969 }
1970
f3d28878 1971 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1972
1973 return 0;
1974}
1975
064ca1d2
TD		 1976static void i915_dump_lrc_obj(struct seq_file *m,
1977 struct intel_engine_cs *ring,
1978 struct drm_i915_gem_object *ctx_obj)
1979{
1980 struct page *page;
1981 uint32_t *reg_state;
1982 int j;
1983 unsigned long ggtt_offset = 0;
1984
1985 if (ctx_obj == NULL) {
1986 seq_printf(m, "Context on %s with no gem object\n",
1987 ring->name);
1988 return;
1989 }
1990
1991 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1992 intel_execlists_ctx_id(ctx_obj));
1993
1994 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1995 seq_puts(m, "\tNot bound in GGTT\n");
1996 else
1997 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1998
1999 if (i915_gem_object_get_pages(ctx_obj)) {
2000 seq_puts(m, "\tFailed to get pages for context object\n");
2001 return;
2002 }
2003
d1675198 2004 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
064ca1d2
TD		 2005 if (!WARN_ON(page == NULL)) {
2006 reg_state = kmap_atomic(page);
2007
2008 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2009 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2010 ggtt_offset + 4096 + (j * 4),
2011 reg_state[j], reg_state[j + 1],
2012 reg_state[j + 2], reg_state[j + 3]);
2013 }
2014 kunmap_atomic(reg_state);
2015 }
2016
2017 seq_putc(m, '\n');
2018}
2019
c0ab1ae9
BW		 2020static int i915_dump_lrc(struct seq_file *m, void *unused)
2021{
2022 struct drm_info_node *node = (struct drm_info_node *) m->private;
2023 struct drm_device *dev = node->minor->dev;
2024 struct drm_i915_private *dev_priv = dev->dev_private;
2025 struct intel_engine_cs *ring;
2026 struct intel_context *ctx;
2027 int ret, i;
2028
2029 if (!i915.enable_execlists) {
2030 seq_printf(m, "Logical Ring Contexts are disabled\n");
2031 return 0;
2032 }
2033
2034 ret = mutex_lock_interruptible(&dev->struct_mutex);
2035 if (ret)
2036 return ret;
2037
2038 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2039 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 2040 if (ring->default_context != ctx)
2041 i915_dump_lrc_obj(m, ring,
2042 ctx->engine[i].state);
c0ab1ae9
BW		 2043 }
2044 }
2045
2046 mutex_unlock(&dev->struct_mutex);
2047
2048 return 0;
2049}
2050
4ba70e44
OM		 2051static int i915_execlists(struct seq_file *m, void *data)
2052{
2053 struct drm_info_node *node = (struct drm_info_node *)m->private;
2054 struct drm_device *dev = node->minor->dev;
2055 struct drm_i915_private *dev_priv = dev->dev_private;
2056 struct intel_engine_cs *ring;
2057 u32 status_pointer;
2058 u8 read_pointer;
2059 u8 write_pointer;
2060 u32 status;
2061 u32 ctx_id;
2062 struct list_head *cursor;
2063 int ring_id, i;
2064 int ret;
2065
2066 if (!i915.enable_execlists) {
2067 seq_puts(m, "Logical Ring Contexts are disabled\n");
2068 return 0;
2069 }
2070
2071 ret = mutex_lock_interruptible(&dev->struct_mutex);
2072 if (ret)
2073 return ret;
2074
fc0412ec
MT		 2075 intel_runtime_pm_get(dev_priv);
2076
4ba70e44 2077 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2078 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2079 int count = 0;
2080 unsigned long flags;
2081
2082 seq_printf(m, "%s\n", ring->name);
2083
83843d84
VS		 2084 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2085 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
4ba70e44
OM		 2086 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2087 status, ctx_id);
2088
2089 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2090 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2091
2092 read_pointer = ring->next_context_status_buffer;
2093 write_pointer = status_pointer & 0x07;
2094 if (read_pointer > write_pointer)
2095 write_pointer += 6;
2096 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2097 read_pointer, write_pointer);
2098
2099 for (i = 0; i < 6; i++) {
83843d84
VS		 2100 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2101 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
4ba70e44
OM		 2102
2103 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2104 i, status, ctx_id);
2105 }
2106
2107 spin_lock_irqsave(&ring->execlist_lock, flags);
2108 list_for_each(cursor, &ring->execlist_queue)
2109 count++;
2110 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2111 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2112 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2113
2114 seq_printf(m, "\t%d requests in queue\n", count);
2115 if (head_req) {
2116 struct drm_i915_gem_object *ctx_obj;
2117
6d3d8274 2118 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2119 seq_printf(m, "\tHead request id: %u\n",
2120 intel_execlists_ctx_id(ctx_obj));
2121 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2122 head_req->tail);
4ba70e44
OM		 2123 }
2124
2125 seq_putc(m, '\n');
2126 }
2127
fc0412ec 2128 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2129 mutex_unlock(&dev->struct_mutex);
2130
2131 return 0;
2132}
2133
ea16a3cd
DV		 2134static const char *swizzle_string(unsigned swizzle)
2135{
aee56cff 2136 switch (swizzle) {
ea16a3cd
DV		 2137 case I915_BIT_6_SWIZZLE_NONE:
2138 return "none";
2139 case I915_BIT_6_SWIZZLE_9:
2140 return "bit9";
2141 case I915_BIT_6_SWIZZLE_9_10:
2142 return "bit9/bit10";
2143 case I915_BIT_6_SWIZZLE_9_11:
2144 return "bit9/bit11";
2145 case I915_BIT_6_SWIZZLE_9_10_11:
2146 return "bit9/bit10/bit11";
2147 case I915_BIT_6_SWIZZLE_9_17:
2148 return "bit9/bit17";
2149 case I915_BIT_6_SWIZZLE_9_10_17:
2150 return "bit9/bit10/bit17";
2151 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2152 return "unknown";
ea16a3cd
DV		 2153 }
2154
2155 return "bug";
2156}
2157
2158static int i915_swizzle_info(struct seq_file *m, void *data)
2159{
9f25d007 2160 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2161 struct drm_device *dev = node->minor->dev;
2162 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2163 int ret;
2164
2165 ret = mutex_lock_interruptible(&dev->struct_mutex);
2166 if (ret)
2167 return ret;
c8c8fb33 2168 intel_runtime_pm_get(dev_priv);
ea16a3cd 2169
ea16a3cd
DV		 2170 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2171 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2172 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2173 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2174
2175 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2176 seq_printf(m, "DDC = 0x%08x\n",
2177 I915_READ(DCC));
656bfa3a
DV		 2178 seq_printf(m, "DDC2 = 0x%08x\n",
2179 I915_READ(DCC2));
ea16a3cd
DV		 2180 seq_printf(m, "C0DRB3 = 0x%04x\n",
2181 I915_READ16(C0DRB3));
2182 seq_printf(m, "C1DRB3 = 0x%04x\n",
2183 I915_READ16(C1DRB3));
9d3203e1 2184 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2185 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2186 I915_READ(MAD_DIMM_C0));
2187 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2188 I915_READ(MAD_DIMM_C1));
2189 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2190 I915_READ(MAD_DIMM_C2));
2191 seq_printf(m, "TILECTL = 0x%08x\n",
2192 I915_READ(TILECTL));
5907f5fb 2193 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2194 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2195 I915_READ(GAMTARBMODE));
2196 else
2197 seq_printf(m, "ARB_MODE = 0x%08x\n",
2198 I915_READ(ARB_MODE));
3fa7d235
DV		 2199 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2200 I915_READ(DISP_ARB_CTL));
ea16a3cd 2201 }
656bfa3a
DV		 2202
2203 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2204 seq_puts(m, "L-shaped memory detected\n");
2205
c8c8fb33 2206 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2207 mutex_unlock(&dev->struct_mutex);
2208
2209 return 0;
2210}
2211
1c60fef5
BW		 2212static int per_file_ctx(int id, void *ptr, void *data)
2213{
273497e5 2214 struct intel_context *ctx = ptr;
1c60fef5 2215 struct seq_file *m = data;
ae6c4806
DV		 2216 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2217
2218 if (!ppgtt) {
2219 seq_printf(m, " no ppgtt for context %d\n",
2220 ctx->user_handle);
2221 return 0;
2222 }
1c60fef5 2223
f83d6518
OM		 2224 if (i915_gem_context_is_default(ctx))
2225 seq_puts(m, " default context:\n");
2226 else
821d66dd 2227 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2228 ppgtt->debug_dump(ppgtt, m);
2229
2230 return 0;
2231}
2232
77df6772 2233static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2234{
3cf17fc5 2235 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2236 struct intel_engine_cs *ring;
77df6772
BW		 2237 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2238 int unused, i;
3cf17fc5 2239
77df6772
BW		 2240 if (!ppgtt)
2241 return;
2242
77df6772
BW		 2243 for_each_ring(ring, dev_priv, unused) {
2244 seq_printf(m, "%s\n", ring->name);
2245 for (i = 0; i < 4; i++) {
d3a93cbe 2246 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
77df6772 2247 pdp <<= 32;
d3a93cbe 2248 pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
a2a5b15c 2249 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2250 }
2251 }
2252}
2253
2254static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2255{
2256 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2257 struct intel_engine_cs *ring;
77df6772 2258 int i;
3cf17fc5 2259
3cf17fc5
DV		 2260 if (INTEL_INFO(dev)->gen == 6)
2261 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2262
a2c7f6fd 2263 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2264 seq_printf(m, "%s\n", ring->name);
2265 if (INTEL_INFO(dev)->gen == 7)
2266 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2267 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2268 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2269 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2270 }
2271 if (dev_priv->mm.aliasing_ppgtt) {
2272 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2273
267f0c90 2274 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2275 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2276
87d60b63 2277 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2278 }
1c60fef5 2279
3cf17fc5 2280 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2281}
2282
2283static int i915_ppgtt_info(struct seq_file *m, void *data)
2284{
9f25d007 2285 struct drm_info_node *node = m->private;
77df6772 2286 struct drm_device *dev = node->minor->dev;
c8c8fb33 2287 struct drm_i915_private *dev_priv = dev->dev_private;
ea91e401 2288 struct drm_file *file;
77df6772
BW		 2289
2290 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2291 if (ret)
2292 return ret;
c8c8fb33 2293 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2294
2295 if (INTEL_INFO(dev)->gen >= 8)
2296 gen8_ppgtt_info(m, dev);
2297 else if (INTEL_INFO(dev)->gen >= 6)
2298 gen6_ppgtt_info(m, dev);
2299
ea91e401
MT		 2300 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2301 struct drm_i915_file_private *file_priv = file->driver_priv;
7cb5dff8 2302 struct task_struct *task;
ea91e401 2303
7cb5dff8 2304 task = get_pid_task(file->pid, PIDTYPE_PID);
06812760
DC		 2305 if (!task) {
2306 ret = -ESRCH;
2307 goto out_put;
2308 }
7cb5dff8
GT		 2309 seq_printf(m, "\nproc: %s\n", task->comm);
2310 put_task_struct(task);
ea91e401
MT		 2311 idr_for_each(&file_priv->context_idr, per_file_ctx,
2312 (void *)(unsigned long)m);
2313 }
2314
06812760 2315out_put:
c8c8fb33 2316 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2317 mutex_unlock(&dev->struct_mutex);
2318
06812760 2319 return ret;
3cf17fc5
DV		 2320}
2321
f5a4c67d
CW		 2322static int count_irq_waiters(struct drm_i915_private *i915)
2323{
2324 struct intel_engine_cs *ring;
2325 int count = 0;
2326 int i;
2327
2328 for_each_ring(ring, i915, i)
2329 count += ring->irq_refcount;
2330
2331 return count;
2332}
2333
1854d5ca
CW		 2334static int i915_rps_boost_info(struct seq_file *m, void *data)
2335{
2336 struct drm_info_node *node = m->private;
2337 struct drm_device *dev = node->minor->dev;
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 struct drm_file *file;
1854d5ca 2340
f5a4c67d
CW		 2341 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2342 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2343 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2344 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2345 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2346 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2347 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2348 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2349 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2350 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2351 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2352 struct drm_i915_file_private *file_priv = file->driver_priv;
2353 struct task_struct *task;
2354
2355 rcu_read_lock();
2356 task = pid_task(file->pid, PIDTYPE_PID);
2357 seq_printf(m, "%s [%d]: %d boosts%s\n",
2358 task ? task->comm : "<unknown>",
2359 task ? task->pid : -1,
2e1b8730
CW		 2360 file_priv->rps.boosts,
2361 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2362 rcu_read_unlock();
2363 }
2e1b8730
CW		 2364 seq_printf(m, "Semaphore boosts: %d%s\n",
2365 dev_priv->rps.semaphores.boosts,
2366 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2367 seq_printf(m, "MMIO flip boosts: %d%s\n",
2368 dev_priv->rps.mmioflips.boosts,
2369 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2370 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2371 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2372
8d3afd7d 2373 return 0;
1854d5ca
CW		 2374}
2375
63573eb7
BW		 2376static int i915_llc(struct seq_file *m, void *data)
2377{
9f25d007 2378 struct drm_info_node *node = m->private;
63573eb7
BW		 2379 struct drm_device *dev = node->minor->dev;
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381
2382 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2383 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2384 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2385
2386 return 0;
2387}
2388
fdf5d357
AD		 2389static int i915_guc_load_status_info(struct seq_file *m, void *data)
2390{
2391 struct drm_info_node *node = m->private;
2392 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2393 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2394 u32 tmp, i;
2395
2396 if (!HAS_GUC_UCODE(dev_priv->dev))
2397 return 0;
2398
2399 seq_printf(m, "GuC firmware status:\n");
2400 seq_printf(m, "\tpath: %s\n",
2401 guc_fw->guc_fw_path);
2402 seq_printf(m, "\tfetch: %s\n",
2403 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2404 seq_printf(m, "\tload: %s\n",
2405 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2406 seq_printf(m, "\tversion wanted: %d.%d\n",
2407 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2408 seq_printf(m, "\tversion found: %d.%d\n",
2409 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
feda33ef
AD		 2410 seq_printf(m, "\theader: offset is %d; size = %d\n",
2411 guc_fw->header_offset, guc_fw->header_size);
2412 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2413 guc_fw->ucode_offset, guc_fw->ucode_size);
2414 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2415 guc_fw->rsa_offset, guc_fw->rsa_size);
fdf5d357
AD		 2416
2417 tmp = I915_READ(GUC_STATUS);
2418
2419 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2420 seq_printf(m, "\tBootrom status = 0x%x\n",
2421 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2422 seq_printf(m, "\tuKernel status = 0x%x\n",
2423 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2424 seq_printf(m, "\tMIA Core status = 0x%x\n",
2425 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2426 seq_puts(m, "\nScratch registers:\n");
2427 for (i = 0; i < 16; i++)
2428 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2429
2430 return 0;
2431}
2432
8b417c26
DG		 2433static void i915_guc_client_info(struct seq_file *m,
2434 struct drm_i915_private *dev_priv,
2435 struct i915_guc_client *client)
2436{
2437 struct intel_engine_cs *ring;
2438 uint64_t tot = 0;
2439 uint32_t i;
2440
2441 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2442 client->priority, client->ctx_index, client->proc_desc_offset);
2443 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2444 client->doorbell_id, client->doorbell_offset, client->cookie);
2445 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2446 client->wq_size, client->wq_offset, client->wq_tail);
2447
2448 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2449 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2450 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2451
2452 for_each_ring(ring, dev_priv, i) {
2453 seq_printf(m, "\tSubmissions: %llu %s\n",
2454 client->submissions[i],
2455 ring->name);
2456 tot += client->submissions[i];
2457 }
2458 seq_printf(m, "\tTotal: %llu\n", tot);
2459}
2460
2461static int i915_guc_info(struct seq_file *m, void *data)
2462{
2463 struct drm_info_node *node = m->private;
2464 struct drm_device *dev = node->minor->dev;
2465 struct drm_i915_private *dev_priv = dev->dev_private;
2466 struct intel_guc guc;
0a0b457f 2467 struct i915_guc_client client = {};
8b417c26
DG		 2468 struct intel_engine_cs *ring;
2469 enum intel_ring_id i;
2470 u64 total = 0;
2471
2472 if (!HAS_GUC_SCHED(dev_priv->dev))
2473 return 0;
2474
2475 /* Take a local copy of the GuC data, so we can dump it at leisure */
2476 spin_lock(&dev_priv->guc.host2guc_lock);
2477 guc = dev_priv->guc;
2478 if (guc.execbuf_client) {
2479 spin_lock(&guc.execbuf_client->wq_lock);
2480 client = *guc.execbuf_client;
2481 spin_unlock(&guc.execbuf_client->wq_lock);
2482 }
2483 spin_unlock(&dev_priv->guc.host2guc_lock);
2484
2485 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2486 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2487 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2488 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2489 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2490
2491 seq_printf(m, "\nGuC submissions:\n");
2492 for_each_ring(ring, dev_priv, i) {
2493 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2494 ring->name, guc.submissions[i],
2495 guc.last_seqno[i], guc.last_seqno[i]);
2496 total += guc.submissions[i];
2497 }
2498 seq_printf(m, "\t%s: %llu\n", "Total", total);
2499
2500 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2501 i915_guc_client_info(m, dev_priv, &client);
2502
2503 /* Add more as required ... */
2504
2505 return 0;
2506}
2507
4c7e77fc
AD		 2508static int i915_guc_log_dump(struct seq_file *m, void *data)
2509{
2510 struct drm_info_node *node = m->private;
2511 struct drm_device *dev = node->minor->dev;
2512 struct drm_i915_private *dev_priv = dev->dev_private;
2513 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2514 u32 *log;
2515 int i = 0, pg;
2516
2517 if (!log_obj)
2518 return 0;
2519
2520 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2521 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2522
2523 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2524 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2525 *(log + i), *(log + i + 1),
2526 *(log + i + 2), *(log + i + 3));
2527
2528 kunmap_atomic(log);
2529 }
2530
2531 seq_putc(m, '\n');
2532
2533 return 0;
2534}
2535
e91fd8c6
RV		 2536static int i915_edp_psr_status(struct seq_file *m, void *data)
2537{
2538 struct drm_info_node *node = m->private;
2539 struct drm_device *dev = node->minor->dev;
2540 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2541 u32 psrperf = 0;
a6cbdb8e
RV		 2542 u32 stat[3];
2543 enum pipe pipe;
a031d709 2544 bool enabled = false;
e91fd8c6 2545
3553a8ea
DL		 2546 if (!HAS_PSR(dev)) {
2547 seq_puts(m, "PSR not supported\n");
2548 return 0;
2549 }
2550
c8c8fb33
PZ		 2551 intel_runtime_pm_get(dev_priv);
2552
fa128fa6 2553 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2554 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2555 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2556 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2557 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2558 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2559 dev_priv->psr.busy_frontbuffer_bits);
2560 seq_printf(m, "Re-enable work scheduled: %s\n",
2561 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2562
3553a8ea
DL		 2563 if (HAS_DDI(dev))
2564 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2565 else {
2566 for_each_pipe(dev_priv, pipe) {
2567 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2568 VLV_EDP_PSR_CURR_STATE_MASK;
2569 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2570 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2571 enabled = true;
a6cbdb8e
RV		 2572 }
2573 }
2574 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2575
2576 if (!HAS_DDI(dev))
2577 for_each_pipe(dev_priv, pipe) {
2578 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2579 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2580 seq_printf(m, " pipe %c", pipe_name(pipe));
2581 }
2582 seq_puts(m, "\n");
e91fd8c6 2583
a6cbdb8e 2584 /* CHV PSR has no kind of performance counter */
3553a8ea 2585 if (HAS_DDI(dev)) {
a031d709
RV		 2586 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2587 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2588
2589 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2590 }
fa128fa6 2591 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2592
c8c8fb33 2593 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2594 return 0;
2595}
2596
d2e216d0
RV		 2597static int i915_sink_crc(struct seq_file *m, void *data)
2598{
2599 struct drm_info_node *node = m->private;
2600 struct drm_device *dev = node->minor->dev;
2601 struct intel_encoder *encoder;
2602 struct intel_connector *connector;
2603 struct intel_dp *intel_dp = NULL;
2604 int ret;
2605 u8 crc[6];
2606
2607 drm_modeset_lock_all(dev);
aca5e361 2608 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2609
2610 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2611 continue;
2612
b6ae3c7c
PZ		 2613 if (!connector->base.encoder)
2614 continue;
2615
d2e216d0
RV		 2616 encoder = to_intel_encoder(connector->base.encoder);
2617 if (encoder->type != INTEL_OUTPUT_EDP)
2618 continue;
2619
2620 intel_dp = enc_to_intel_dp(&encoder->base);
2621
2622 ret = intel_dp_sink_crc(intel_dp, crc);
2623 if (ret)
2624 goto out;
2625
2626 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2627 crc[0], crc[1], crc[2],
2628 crc[3], crc[4], crc[5]);
2629 goto out;
2630 }
2631 ret = -ENODEV;
2632out:
2633 drm_modeset_unlock_all(dev);
2634 return ret;
2635}
2636
ec013e7f
JB		 2637static int i915_energy_uJ(struct seq_file *m, void *data)
2638{
2639 struct drm_info_node *node = m->private;
2640 struct drm_device *dev = node->minor->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 u64 power;
2643 u32 units;
2644
2645 if (INTEL_INFO(dev)->gen < 6)
2646 return -ENODEV;
2647
36623ef8
PZ		 2648 intel_runtime_pm_get(dev_priv);
2649
ec013e7f
JB		 2650 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2651 power = (power & 0x1f00) >> 8;
2652 units = 1000000 / (1 << power); /* convert to uJ */
2653 power = I915_READ(MCH_SECP_NRG_STTS);
2654 power *= units;
2655
36623ef8
PZ		 2656 intel_runtime_pm_put(dev_priv);
2657
ec013e7f 2658 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2659
2660 return 0;
2661}
2662
6455c870 2663static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2664{
9f25d007 2665 struct drm_info_node *node = m->private;
371db66a
PZ		 2666 struct drm_device *dev = node->minor->dev;
2667 struct drm_i915_private *dev_priv = dev->dev_private;
2668
6455c870 2669 if (!HAS_RUNTIME_PM(dev)) {
371db66a
PZ		 2670 seq_puts(m, "not supported\n");
2671 return 0;
2672 }
2673
86c4ec0d 2674 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2675 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2676 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2677#ifdef CONFIG_PM
a6aaec8b
DL		 2678 seq_printf(m, "Usage count: %d\n",
2679 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2680#else
2681 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2682#endif
371db66a 2683
ec013e7f
JB		 2684 return 0;
2685}
2686
1da51581
ID		 2687static const char *power_domain_str(enum intel_display_power_domain domain)
2688{
2689 switch (domain) {
2690 case POWER_DOMAIN_PIPE_A:
2691 return "PIPE_A";
2692 case POWER_DOMAIN_PIPE_B:
2693 return "PIPE_B";
2694 case POWER_DOMAIN_PIPE_C:
2695 return "PIPE_C";
2696 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2697 return "PIPE_A_PANEL_FITTER";
2698 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2699 return "PIPE_B_PANEL_FITTER";
2700 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2701 return "PIPE_C_PANEL_FITTER";
2702 case POWER_DOMAIN_TRANSCODER_A:
2703 return "TRANSCODER_A";
2704 case POWER_DOMAIN_TRANSCODER_B:
2705 return "TRANSCODER_B";
2706 case POWER_DOMAIN_TRANSCODER_C:
2707 return "TRANSCODER_C";
2708 case POWER_DOMAIN_TRANSCODER_EDP:
2709 return "TRANSCODER_EDP";
319be8ae
ID		 2710 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2711 return "PORT_DDI_A_2_LANES";
2712 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2713 return "PORT_DDI_A_4_LANES";
2714 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2715 return "PORT_DDI_B_2_LANES";
2716 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2717 return "PORT_DDI_B_4_LANES";
2718 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2719 return "PORT_DDI_C_2_LANES";
2720 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2721 return "PORT_DDI_C_4_LANES";
2722 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2723 return "PORT_DDI_D_2_LANES";
2724 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2725 return "PORT_DDI_D_4_LANES";
d8e19f99
XZ		 2726 case POWER_DOMAIN_PORT_DDI_E_2_LANES:
2727 return "PORT_DDI_E_2_LANES";
319be8ae
ID		 2728 case POWER_DOMAIN_PORT_DSI:
2729 return "PORT_DSI";
2730 case POWER_DOMAIN_PORT_CRT:
2731 return "PORT_CRT";
2732 case POWER_DOMAIN_PORT_OTHER:
2733 return "PORT_OTHER";
1da51581
ID		 2734 case POWER_DOMAIN_VGA:
2735 return "VGA";
2736 case POWER_DOMAIN_AUDIO:
2737 return "AUDIO";
bd2bb1b9
PZ		 2738 case POWER_DOMAIN_PLLS:
2739 return "PLLS";
1407121a
S		 2740 case POWER_DOMAIN_AUX_A:
2741 return "AUX_A";
2742 case POWER_DOMAIN_AUX_B:
2743 return "AUX_B";
2744 case POWER_DOMAIN_AUX_C:
2745 return "AUX_C";
2746 case POWER_DOMAIN_AUX_D:
2747 return "AUX_D";
1da51581
ID		 2748 case POWER_DOMAIN_INIT:
2749 return "INIT";
2750 default:
5f77eeb0 2751 MISSING_CASE(domain);
1da51581
ID		 2752 return "?";
2753 }
2754}
2755
2756static int i915_power_domain_info(struct seq_file *m, void *unused)
2757{
9f25d007 2758 struct drm_info_node *node = m->private;
1da51581
ID		 2759 struct drm_device *dev = node->minor->dev;
2760 struct drm_i915_private *dev_priv = dev->dev_private;
2761 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2762 int i;
2763
2764 mutex_lock(&power_domains->lock);
2765
2766 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2767 for (i = 0; i < power_domains->power_well_count; i++) {
2768 struct i915_power_well *power_well;
2769 enum intel_display_power_domain power_domain;
2770
2771 power_well = &power_domains->power_wells[i];
2772 seq_printf(m, "%-25s %d\n", power_well->name,
2773 power_well->count);
2774
2775 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2776 power_domain++) {
2777 if (!(BIT(power_domain) & power_well->domains))
2778 continue;
2779
2780 seq_printf(m, " %-23s %d\n",
2781 power_domain_str(power_domain),
2782 power_domains->domain_use_count[power_domain]);
2783 }
2784 }
2785
2786 mutex_unlock(&power_domains->lock);
2787
2788 return 0;
2789}
2790
b7cec66d
DL		 2791static int i915_dmc_info(struct seq_file *m, void *unused)
2792{
2793 struct drm_info_node *node = m->private;
2794 struct drm_device *dev = node->minor->dev;
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796 struct intel_csr *csr;
2797
2798 if (!HAS_CSR(dev)) {
2799 seq_puts(m, "not supported\n");
2800 return 0;
2801 }
2802
2803 csr = &dev_priv->csr;
2804
2805 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2806 seq_printf(m, "path: %s\n", csr->fw_path);
2807
2808 if (!csr->dmc_payload)
2809 return 0;
2810
2811 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2812 CSR_VERSION_MINOR(csr->version));
2813
8337206d
DL		 2814 intel_runtime_pm_get(dev_priv);
2815
2816 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2817 seq_printf(m, "DC3 -> DC5 count: %d\n",
2818 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2819 seq_printf(m, "DC5 -> DC6 count: %d\n",
2820 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2821 }
2822
2823 intel_runtime_pm_put(dev_priv);
2824
b7cec66d
DL		 2825 return 0;
2826}
2827
53f5e3ca
JB		 2828static void intel_seq_print_mode(struct seq_file *m, int tabs,
2829 struct drm_display_mode *mode)
2830{
2831 int i;
2832
2833 for (i = 0; i < tabs; i++)
2834 seq_putc(m, '\t');
2835
2836 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2837 mode->base.id, mode->name,
2838 mode->vrefresh, mode->clock,
2839 mode->hdisplay, mode->hsync_start,
2840 mode->hsync_end, mode->htotal,
2841 mode->vdisplay, mode->vsync_start,
2842 mode->vsync_end, mode->vtotal,
2843 mode->type, mode->flags);
2844}
2845
2846static void intel_encoder_info(struct seq_file *m,
2847 struct intel_crtc *intel_crtc,
2848 struct intel_encoder *intel_encoder)
2849{
9f25d007 2850 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2851 struct drm_device *dev = node->minor->dev;
2852 struct drm_crtc *crtc = &intel_crtc->base;
2853 struct intel_connector *intel_connector;
2854 struct drm_encoder *encoder;
2855
2856 encoder = &intel_encoder->base;
2857 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2858 encoder->base.id, encoder->name);
53f5e3ca
JB		 2859 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2860 struct drm_connector *connector = &intel_connector->base;
2861 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2862 connector->base.id,
c23cc417 2863 connector->name,
53f5e3ca
JB		 2864 drm_get_connector_status_name(connector->status));
2865 if (connector->status == connector_status_connected) {
2866 struct drm_display_mode *mode = &crtc->mode;
2867 seq_printf(m, ", mode:\n");
2868 intel_seq_print_mode(m, 2, mode);
2869 } else {
2870 seq_putc(m, '\n');
2871 }
2872 }
2873}
2874
2875static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2876{
9f25d007 2877 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2878 struct drm_device *dev = node->minor->dev;
2879 struct drm_crtc *crtc = &intel_crtc->base;
2880 struct intel_encoder *intel_encoder;
23a48d53
ML		 2881 struct drm_plane_state *plane_state = crtc->primary->state;
2882 struct drm_framebuffer *fb = plane_state->fb;
53f5e3ca 2883
23a48d53 2884 if (fb)
5aa8a937 2885 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
23a48d53
ML		 2886 fb->base.id, plane_state->src_x >> 16,
2887 plane_state->src_y >> 16, fb->width, fb->height);
5aa8a937
MR		 2888 else
2889 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2890 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2891 intel_encoder_info(m, intel_crtc, intel_encoder);
2892}
2893
2894static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2895{
2896 struct drm_display_mode *mode = panel->fixed_mode;
2897
2898 seq_printf(m, "\tfixed mode:\n");
2899 intel_seq_print_mode(m, 2, mode);
2900}
2901
2902static void intel_dp_info(struct seq_file *m,
2903 struct intel_connector *intel_connector)
2904{
2905 struct intel_encoder *intel_encoder = intel_connector->encoder;
2906 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2907
2908 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
742f491d 2909 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
53f5e3ca
JB		 2910 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2911 intel_panel_info(m, &intel_connector->panel);
2912}
2913
2914static void intel_hdmi_info(struct seq_file *m,
2915 struct intel_connector *intel_connector)
2916{
2917 struct intel_encoder *intel_encoder = intel_connector->encoder;
2918 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2919
742f491d 2920 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
53f5e3ca
JB		 2921}
2922
2923static void intel_lvds_info(struct seq_file *m,
2924 struct intel_connector *intel_connector)
2925{
2926 intel_panel_info(m, &intel_connector->panel);
2927}
2928
2929static void intel_connector_info(struct seq_file *m,
2930 struct drm_connector *connector)
2931{
2932 struct intel_connector *intel_connector = to_intel_connector(connector);
2933 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2934 struct drm_display_mode *mode;
53f5e3ca
JB		 2935
2936 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2937 connector->base.id, connector->name,
53f5e3ca
JB		 2938 drm_get_connector_status_name(connector->status));
2939 if (connector->status == connector_status_connected) {
2940 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2941 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2942 connector->display_info.width_mm,
2943 connector->display_info.height_mm);
2944 seq_printf(m, "\tsubpixel order: %s\n",
2945 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2946 seq_printf(m, "\tCEA rev: %d\n",
2947 connector->display_info.cea_rev);
2948 }
36cd7444
DA		 2949 if (intel_encoder) {
2950 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2951 intel_encoder->type == INTEL_OUTPUT_EDP)
2952 intel_dp_info(m, intel_connector);
2953 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2954 intel_hdmi_info(m, intel_connector);
2955 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2956 intel_lvds_info(m, intel_connector);
2957 }
53f5e3ca 2958
f103fc7d
JB		 2959 seq_printf(m, "\tmodes:\n");
2960 list_for_each_entry(mode, &connector->modes, head)
2961 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2962}
2963
065f2ec2
CW		 2964static bool cursor_active(struct drm_device *dev, int pipe)
2965{
2966 struct drm_i915_private *dev_priv = dev->dev_private;
2967 u32 state;
2968
2969 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 2970 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
065f2ec2 2971 else
5efb3e28 2972 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2973
2974 return state;
2975}
2976
2977static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2978{
2979 struct drm_i915_private *dev_priv = dev->dev_private;
2980 u32 pos;
2981
5efb3e28 2982 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2983
2984 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2985 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2986 *x = -*x;
2987
2988 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2989 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2990 *y = -*y;
2991
2992 return cursor_active(dev, pipe);
2993}
2994
3abc4e09
RF		 2995static const char *plane_type(enum drm_plane_type type)
2996{
2997 switch (type) {
2998 case DRM_PLANE_TYPE_OVERLAY:
2999 return "OVL";
3000 case DRM_PLANE_TYPE_PRIMARY:
3001 return "PRI";
3002 case DRM_PLANE_TYPE_CURSOR:
3003 return "CUR";
3004 /*
3005 * Deliberately omitting default: to generate compiler warnings
3006 * when a new drm_plane_type gets added.
3007 */
3008 }
3009
3010 return "unknown";
3011}
3012
3013static const char *plane_rotation(unsigned int rotation)
3014{
3015 static char buf[48];
3016 /*
3017 * According to doc only one DRM_ROTATE_ is allowed but this
3018 * will print them all to visualize if the values are misused
3019 */
3020 snprintf(buf, sizeof(buf),
3021 "%s%s%s%s%s%s(0x%08x)",
3022 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3023 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3024 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3025 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3026 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3027 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3028 rotation);
3029
3030 return buf;
3031}
3032
3033static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3034{
3035 struct drm_info_node *node = m->private;
3036 struct drm_device *dev = node->minor->dev;
3037 struct intel_plane *intel_plane;
3038
3039 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3040 struct drm_plane_state *state;
3041 struct drm_plane *plane = &intel_plane->base;
3042
3043 if (!plane->state) {
3044 seq_puts(m, "plane->state is NULL!\n");
3045 continue;
3046 }
3047
3048 state = plane->state;
3049
3050 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3051 plane->base.id,
3052 plane_type(intel_plane->base.type),
3053 state->crtc_x, state->crtc_y,
3054 state->crtc_w, state->crtc_h,
3055 (state->src_x >> 16),
3056 ((state->src_x & 0xffff) * 15625) >> 10,
3057 (state->src_y >> 16),
3058 ((state->src_y & 0xffff) * 15625) >> 10,
3059 (state->src_w >> 16),
3060 ((state->src_w & 0xffff) * 15625) >> 10,
3061 (state->src_h >> 16),
3062 ((state->src_h & 0xffff) * 15625) >> 10,
3063 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3064 plane_rotation(state->rotation));
3065 }
3066}
3067
3068static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3069{
3070 struct intel_crtc_state *pipe_config;
3071 int num_scalers = intel_crtc->num_scalers;
3072 int i;
3073
3074 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3075
3076 /* Not all platformas have a scaler */
3077 if (num_scalers) {
3078 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3079 num_scalers,
3080 pipe_config->scaler_state.scaler_users,
3081 pipe_config->scaler_state.scaler_id);
3082
3083 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3084 struct intel_scaler *sc =
3085 &pipe_config->scaler_state.scalers[i];
3086
3087 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3088 i, yesno(sc->in_use), sc->mode);
3089 }
3090 seq_puts(m, "\n");
3091 } else {
3092 seq_puts(m, "\tNo scalers available on this platform\n");
3093 }
3094}
3095
53f5e3ca
JB		 3096static int i915_display_info(struct seq_file *m, void *unused)
3097{
9f25d007 3098 struct drm_info_node *node = m->private;
53f5e3ca 3099 struct drm_device *dev = node->minor->dev;
b0e5ddf3 3100 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 3101 struct intel_crtc *crtc;
53f5e3ca
JB		 3102 struct drm_connector *connector;
3103
b0e5ddf3 3104 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 3105 drm_modeset_lock_all(dev);
3106 seq_printf(m, "CRTC info\n");
3107 seq_printf(m, "---------\n");
d3fcc808 3108 for_each_intel_crtc(dev, crtc) {
065f2ec2 3109 bool active;
f77076c9 3110 struct intel_crtc_state *pipe_config;
065f2ec2 3111 int x, y;
53f5e3ca 3112
f77076c9
ML		 3113 pipe_config = to_intel_crtc_state(crtc->base.state);
3114
3abc4e09 3115 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
065f2ec2 3116 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9 3117 yesno(pipe_config->base.active),
3abc4e09
RF		 3118 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3119 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3120
f77076c9 3121 if (pipe_config->base.active) {
065f2ec2
CW		 3122 intel_crtc_info(m, crtc);
3123
a23dc658 3124 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 3125 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 3126 yesno(crtc->cursor_base),
3dd512fb
MR		 3127 x, y, crtc->base.cursor->state->crtc_w,
3128 crtc->base.cursor->state->crtc_h,
57127efa 3129 crtc->cursor_addr, yesno(active));
3abc4e09
RF		 3130 intel_scaler_info(m, crtc);
3131 intel_plane_info(m, crtc);
a23dc658 3132 }
cace841c
DV		 3133
3134 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3135 yesno(!crtc->cpu_fifo_underrun_disabled),
3136 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 3137 }
3138
3139 seq_printf(m, "\n");
3140 seq_printf(m, "Connector info\n");
3141 seq_printf(m, "--------------\n");
3142 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3143 intel_connector_info(m, connector);
3144 }
3145 drm_modeset_unlock_all(dev);
b0e5ddf3 3146 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 3147
3148 return 0;
3149}
3150
e04934cf
BW		 3151static int i915_semaphore_status(struct seq_file *m, void *unused)
3152{
3153 struct drm_info_node *node = (struct drm_info_node *) m->private;
3154 struct drm_device *dev = node->minor->dev;
3155 struct drm_i915_private *dev_priv = dev->dev_private;
3156 struct intel_engine_cs *ring;
3157 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3158 int i, j, ret;
3159
3160 if (!i915_semaphore_is_enabled(dev)) {
3161 seq_puts(m, "Semaphores are disabled\n");
3162 return 0;
3163 }
3164
3165 ret = mutex_lock_interruptible(&dev->struct_mutex);
3166 if (ret)
3167 return ret;
03872064 3168 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 3169
3170 if (IS_BROADWELL(dev)) {
3171 struct page *page;
3172 uint64_t *seqno;
3173
3174 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3175
3176 seqno = (uint64_t *)kmap_atomic(page);
3177 for_each_ring(ring, dev_priv, i) {
3178 uint64_t offset;
3179
3180 seq_printf(m, "%s\n", ring->name);
3181
3182 seq_puts(m, " Last signal:");
3183 for (j = 0; j < num_rings; j++) {
3184 offset = i * I915_NUM_RINGS + j;
3185 seq_printf(m, "0x%08llx (0x%02llx) ",
3186 seqno[offset], offset * 8);
3187 }
3188 seq_putc(m, '\n');
3189
3190 seq_puts(m, " Last wait: ");
3191 for (j = 0; j < num_rings; j++) {
3192 offset = i + (j * I915_NUM_RINGS);
3193 seq_printf(m, "0x%08llx (0x%02llx) ",
3194 seqno[offset], offset * 8);
3195 }
3196 seq_putc(m, '\n');
3197
3198 }
3199 kunmap_atomic(seqno);
3200 } else {
3201 seq_puts(m, " Last signal:");
3202 for_each_ring(ring, dev_priv, i)
3203 for (j = 0; j < num_rings; j++)
3204 seq_printf(m, "0x%08x\n",
3205 I915_READ(ring->semaphore.mbox.signal[j]));
3206 seq_putc(m, '\n');
3207 }
3208
3209 seq_puts(m, "\nSync seqno:\n");
3210 for_each_ring(ring, dev_priv, i) {
3211 for (j = 0; j < num_rings; j++) {
3212 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
3213 }
3214 seq_putc(m, '\n');
3215 }
3216 seq_putc(m, '\n');
3217
03872064 3218 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 3219 mutex_unlock(&dev->struct_mutex);
3220 return 0;
3221}
3222
728e29d7
DV		 3223static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3224{
3225 struct drm_info_node *node = (struct drm_info_node *) m->private;
3226 struct drm_device *dev = node->minor->dev;
3227 struct drm_i915_private *dev_priv = dev->dev_private;
3228 int i;
3229
3230 drm_modeset_lock_all(dev);
3231 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3232 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3233
3234 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 3235 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 3236 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 3237 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 3238 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3239 seq_printf(m, " dpll_md: 0x%08x\n",
3240 pll->config.hw_state.dpll_md);
3241 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3242 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3243 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 3244 }
3245 drm_modeset_unlock_all(dev);
3246
3247 return 0;
3248}
3249
1ed1ef9d 3250static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 3251{
3252 int i;
3253 int ret;
3254 struct drm_info_node *node = (struct drm_info_node *) m->private;
3255 struct drm_device *dev = node->minor->dev;
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257
888b5995
AS		 3258 ret = mutex_lock_interruptible(&dev->struct_mutex);
3259 if (ret)
3260 return ret;
3261
3262 intel_runtime_pm_get(dev_priv);
3263
7225342a
MK		 3264 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3265 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 3266 u32 addr, mask, value, read;
3267 bool ok;
888b5995 3268
7225342a
MK		 3269 addr = dev_priv->workarounds.reg[i].addr;
3270 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 3271 value = dev_priv->workarounds.reg[i].value;
3272 read = I915_READ(addr);
3273 ok = (value & mask) == (read & mask);
3274 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3275 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 3276 }
3277
3278 intel_runtime_pm_put(dev_priv);
3279 mutex_unlock(&dev->struct_mutex);
3280
3281 return 0;
3282}
3283
c5511e44
DL		 3284static int i915_ddb_info(struct seq_file *m, void *unused)
3285{
3286 struct drm_info_node *node = m->private;
3287 struct drm_device *dev = node->minor->dev;
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 struct skl_ddb_allocation *ddb;
3290 struct skl_ddb_entry *entry;
3291 enum pipe pipe;
3292 int plane;
3293
2fcffe19
DL		 3294 if (INTEL_INFO(dev)->gen < 9)
3295 return 0;
3296
c5511e44
DL		 3297 drm_modeset_lock_all(dev);
3298
3299 ddb = &dev_priv->wm.skl_hw.ddb;
3300
3301 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3302
3303 for_each_pipe(dev_priv, pipe) {
3304 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3305
dd740780 3306 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3307 entry = &ddb->plane[pipe][plane];
3308 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3309 entry->start, entry->end,
3310 skl_ddb_entry_size(entry));
3311 }
3312
4969d33e 3313 entry = &ddb->plane[pipe][PLANE_CURSOR];
c5511e44
DL		 3314 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3315 entry->end, skl_ddb_entry_size(entry));
3316 }
3317
3318 drm_modeset_unlock_all(dev);
3319
3320 return 0;
3321}
3322
a54746e3
VK		 3323static void drrs_status_per_crtc(struct seq_file *m,
3324 struct drm_device *dev, struct intel_crtc *intel_crtc)
3325{
3326 struct intel_encoder *intel_encoder;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct i915_drrs *drrs = &dev_priv->drrs;
3329 int vrefresh = 0;
3330
3331 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3332 /* Encoder connected on this CRTC */
3333 switch (intel_encoder->type) {
3334 case INTEL_OUTPUT_EDP:
3335 seq_puts(m, "eDP:\n");
3336 break;
3337 case INTEL_OUTPUT_DSI:
3338 seq_puts(m, "DSI:\n");
3339 break;
3340 case INTEL_OUTPUT_HDMI:
3341 seq_puts(m, "HDMI:\n");
3342 break;
3343 case INTEL_OUTPUT_DISPLAYPORT:
3344 seq_puts(m, "DP:\n");
3345 break;
3346 default:
3347 seq_printf(m, "Other encoder (id=%d).\n",
3348 intel_encoder->type);
3349 return;
3350 }
3351 }
3352
3353 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3354 seq_puts(m, "\tVBT: DRRS_type: Static");
3355 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3356 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3357 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3358 seq_puts(m, "\tVBT: DRRS_type: None");
3359 else
3360 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3361
3362 seq_puts(m, "\n\n");
3363
f77076c9 3364 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3365 struct intel_panel *panel;
3366
3367 mutex_lock(&drrs->mutex);
3368 /* DRRS Supported */
3369 seq_puts(m, "\tDRRS Supported: Yes\n");
3370
3371 /* disable_drrs() will make drrs->dp NULL */
3372 if (!drrs->dp) {
3373 seq_puts(m, "Idleness DRRS: Disabled");
3374 mutex_unlock(&drrs->mutex);
3375 return;
3376 }
3377
3378 panel = &drrs->dp->attached_connector->panel;
3379 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3380 drrs->busy_frontbuffer_bits);
3381
3382 seq_puts(m, "\n\t\t");
3383 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3384 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3385 vrefresh = panel->fixed_mode->vrefresh;
3386 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3387 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3388 vrefresh = panel->downclock_mode->vrefresh;
3389 } else {
3390 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3391 drrs->refresh_rate_type);
3392 mutex_unlock(&drrs->mutex);
3393 return;
3394 }
3395 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3396
3397 seq_puts(m, "\n\t\t");
3398 mutex_unlock(&drrs->mutex);
3399 } else {
3400 /* DRRS not supported. Print the VBT parameter*/
3401 seq_puts(m, "\tDRRS Supported : No");
3402 }
3403 seq_puts(m, "\n");
3404}
3405
3406static int i915_drrs_status(struct seq_file *m, void *unused)
3407{
3408 struct drm_info_node *node = m->private;
3409 struct drm_device *dev = node->minor->dev;
3410 struct intel_crtc *intel_crtc;
3411 int active_crtc_cnt = 0;
3412
3413 for_each_intel_crtc(dev, intel_crtc) {
3414 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3415
f77076c9 3416 if (intel_crtc->base.state->active) {
a54746e3
VK		 3417 active_crtc_cnt++;
3418 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3419
3420 drrs_status_per_crtc(m, dev, intel_crtc);
3421 }
3422
3423 drm_modeset_unlock(&intel_crtc->base.mutex);
3424 }
3425
3426 if (!active_crtc_cnt)
3427 seq_puts(m, "No active crtc found\n");
3428
3429 return 0;
3430}
3431
07144428
DL		 3432struct pipe_crc_info {
3433 const char *name;
3434 struct drm_device *dev;
3435 enum pipe pipe;
3436};
3437
11bed958
DA		 3438static int i915_dp_mst_info(struct seq_file *m, void *unused)
3439{
3440 struct drm_info_node *node = (struct drm_info_node *) m->private;
3441 struct drm_device *dev = node->minor->dev;
3442 struct drm_encoder *encoder;
3443 struct intel_encoder *intel_encoder;
3444 struct intel_digital_port *intel_dig_port;
3445 drm_modeset_lock_all(dev);
3446 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3447 intel_encoder = to_intel_encoder(encoder);
3448 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3449 continue;
3450 intel_dig_port = enc_to_dig_port(encoder);
3451 if (!intel_dig_port->dp.can_mst)
3452 continue;
3453
3454 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3455 }
3456 drm_modeset_unlock_all(dev);
3457 return 0;
3458}
3459
07144428
DL		 3460static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3461{
be5c7a90
DL		 3462 struct pipe_crc_info *info = inode->i_private;
3463 struct drm_i915_private *dev_priv = info->dev->dev_private;
3464 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3465
7eb1c496
DV		 3466 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3467 return -ENODEV;
3468
d538bbdf
DL		 3469 spin_lock_irq(&pipe_crc->lock);
3470
3471 if (pipe_crc->opened) {
3472 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3473 return -EBUSY; /* already open */
3474 }
3475
d538bbdf 3476 pipe_crc->opened = true;
07144428
DL		 3477 filep->private_data = inode->i_private;
3478
d538bbdf
DL		 3479 spin_unlock_irq(&pipe_crc->lock);
3480
07144428
DL		 3481 return 0;
3482}
3483
3484static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3485{
be5c7a90
DL		 3486 struct pipe_crc_info *info = inode->i_private;
3487 struct drm_i915_private *dev_priv = info->dev->dev_private;
3488 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3489
d538bbdf
DL		 3490 spin_lock_irq(&pipe_crc->lock);
3491 pipe_crc->opened = false;
3492 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3493
07144428
DL		 3494 return 0;
3495}
3496
3497/* (6 fields, 8 chars each, space separated (5) + '\n') */
3498#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3499/* account for \'0' */
3500#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3501
3502static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3503{
d538bbdf
DL		 3504 assert_spin_locked(&pipe_crc->lock);
3505 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3506 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3507}
3508
3509static ssize_t
3510i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3511 loff_t *pos)
3512{
3513 struct pipe_crc_info *info = filep->private_data;
3514 struct drm_device *dev = info->dev;
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3517 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3518 int n_entries;
07144428
DL		 3519 ssize_t bytes_read;
3520
3521 /*
3522 * Don't allow user space to provide buffers not big enough to hold
3523 * a line of data.
3524 */
3525 if (count < PIPE_CRC_LINE_LEN)
3526 return -EINVAL;
3527
3528 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3529 return 0;
07144428
DL		 3530
3531 /* nothing to read */
d538bbdf 3532 spin_lock_irq(&pipe_crc->lock);
07144428 3533 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3534 int ret;
3535
3536 if (filep->f_flags & O_NONBLOCK) {
3537 spin_unlock_irq(&pipe_crc->lock);
07144428 3538 return -EAGAIN;
d538bbdf 3539 }
07144428 3540
d538bbdf
DL		 3541 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3542 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3543 if (ret) {
3544 spin_unlock_irq(&pipe_crc->lock);
3545 return ret;
3546 }
8bf1e9f1
SH		 3547 }
3548
07144428 3549 /* We now have one or more entries to read */
9ad6d99f 3550 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3551
07144428 3552 bytes_read = 0;
9ad6d99f
VS		 3553 while (n_entries > 0) {
3554 struct intel_pipe_crc_entry *entry =
3555 &pipe_crc->entries[pipe_crc->tail];
07144428 3556 int ret;
8bf1e9f1 3557
9ad6d99f
VS		 3558 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3559 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3560 break;
3561
3562 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3563 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3564
07144428
DL		 3565 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3566 "%8u %8x %8x %8x %8x %8x\n",
3567 entry->frame, entry->crc[0],
3568 entry->crc[1], entry->crc[2],
3569 entry->crc[3], entry->crc[4]);
3570
9ad6d99f
VS		 3571 spin_unlock_irq(&pipe_crc->lock);
3572
3573 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3574 if (ret == PIPE_CRC_LINE_LEN)
3575 return -EFAULT;
b2c88f5b 3576
9ad6d99f
VS		 3577 user_buf += PIPE_CRC_LINE_LEN;
3578 n_entries--;
3579
3580 spin_lock_irq(&pipe_crc->lock);
3581 }
8bf1e9f1 3582
d538bbdf
DL		 3583 spin_unlock_irq(&pipe_crc->lock);
3584
07144428
DL		 3585 return bytes_read;
3586}
3587
3588static const struct file_operations i915_pipe_crc_fops = {
3589 .owner = THIS_MODULE,
3590 .open = i915_pipe_crc_open,
3591 .read = i915_pipe_crc_read,
3592 .release = i915_pipe_crc_release,
3593};
3594
3595static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3596 {
3597 .name = "i915_pipe_A_crc",
3598 .pipe = PIPE_A,
3599 },
3600 {
3601 .name = "i915_pipe_B_crc",
3602 .pipe = PIPE_B,
3603 },
3604 {
3605 .name = "i915_pipe_C_crc",
3606 .pipe = PIPE_C,
3607 },
3608};
3609
3610static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3611 enum pipe pipe)
3612{
3613 struct drm_device *dev = minor->dev;
3614 struct dentry *ent;
3615 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3616
3617 info->dev = dev;
3618 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3619 &i915_pipe_crc_fops);
f3c5fe97
WY		 3620 if (!ent)
3621 return -ENOMEM;
07144428
DL		 3622
3623 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3624}
3625
e8dfcf78 3626static const char * const pipe_crc_sources[] = {
926321d5
DV		 3627 "none",
3628 "plane1",
3629 "plane2",
3630 "pf",
5b3a856b 3631 "pipe",
3d099a05
DV		 3632 "TV",
3633 "DP-B",
3634 "DP-C",
3635 "DP-D",
46a19188 3636 "auto",
926321d5
DV		 3637};
3638
3639static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3640{
3641 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3642 return pipe_crc_sources[source];
3643}
3644
bd9db02f 3645static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3646{
3647 struct drm_device *dev = m->private;
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 int i;
3650
3651 for (i = 0; i < I915_MAX_PIPES; i++)
3652 seq_printf(m, "%c %s\n", pipe_name(i),
3653 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3654
3655 return 0;
3656}
3657
bd9db02f 3658static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3659{
3660 struct drm_device *dev = inode->i_private;
3661
bd9db02f 3662 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3663}
3664
46a19188 3665static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3666 uint32_t *val)
3667{
46a19188
DV		 3668 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3669 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3670
3671 switch (*source) {
52f843f6
DV		 3672 case INTEL_PIPE_CRC_SOURCE_PIPE:
3673 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3674 break;
3675 case INTEL_PIPE_CRC_SOURCE_NONE:
3676 *val = 0;
3677 break;
3678 default:
3679 return -EINVAL;
3680 }
3681
3682 return 0;
3683}
3684
46a19188
DV		 3685static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3686 enum intel_pipe_crc_source *source)
3687{
3688 struct intel_encoder *encoder;
3689 struct intel_crtc *crtc;
26756809 3690 struct intel_digital_port *dig_port;
46a19188
DV		 3691 int ret = 0;
3692
3693 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3694
6e9f798d 3695 drm_modeset_lock_all(dev);
b2784e15 3696 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3697 if (!encoder->base.crtc)
3698 continue;
3699
3700 crtc = to_intel_crtc(encoder->base.crtc);
3701
3702 if (crtc->pipe != pipe)
3703 continue;
3704
3705 switch (encoder->type) {
3706 case INTEL_OUTPUT_TVOUT:
3707 *source = INTEL_PIPE_CRC_SOURCE_TV;
3708 break;
3709 case INTEL_OUTPUT_DISPLAYPORT:
3710 case INTEL_OUTPUT_EDP:
26756809
DV		 3711 dig_port = enc_to_dig_port(&encoder->base);
3712 switch (dig_port->port) {
3713 case PORT_B:
3714 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3715 break;
3716 case PORT_C:
3717 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3718 break;
3719 case PORT_D:
3720 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3721 break;
3722 default:
3723 WARN(1, "nonexisting DP port %c\n",
3724 port_name(dig_port->port));
3725 break;
3726 }
46a19188 3727 break;
6847d71b
PZ		 3728 default:
3729 break;
46a19188
DV		 3730 }
3731 }
6e9f798d 3732 drm_modeset_unlock_all(dev);
46a19188
DV		 3733
3734 return ret;
3735}
3736
3737static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3738 enum pipe pipe,
3739 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3740 uint32_t *val)
3741{
8d2f24ca
DV		 3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 bool need_stable_symbols = false;
3744
46a19188
DV		 3745 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3746 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3747 if (ret)
3748 return ret;
3749 }
3750
3751 switch (*source) {
7ac0129b
DV		 3752 case INTEL_PIPE_CRC_SOURCE_PIPE:
3753 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3754 break;
3755 case INTEL_PIPE_CRC_SOURCE_DP_B:
3756 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3757 need_stable_symbols = true;
7ac0129b
DV		 3758 break;
3759 case INTEL_PIPE_CRC_SOURCE_DP_C:
3760 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3761 need_stable_symbols = true;
7ac0129b 3762 break;
2be57922
VS		 3763 case INTEL_PIPE_CRC_SOURCE_DP_D:
3764 if (!IS_CHERRYVIEW(dev))
3765 return -EINVAL;
3766 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3767 need_stable_symbols = true;
3768 break;
7ac0129b
DV		 3769 case INTEL_PIPE_CRC_SOURCE_NONE:
3770 *val = 0;
3771 break;
3772 default:
3773 return -EINVAL;
3774 }
3775
8d2f24ca
DV		 3776 /*
3777 * When the pipe CRC tap point is after the transcoders we need
3778 * to tweak symbol-level features to produce a deterministic series of
3779 * symbols for a given frame. We need to reset those features only once
3780 * a frame (instead of every nth symbol):
3781 * - DC-balance: used to ensure a better clock recovery from the data
3782 * link (SDVO)
3783 * - DisplayPort scrambling: used for EMI reduction
3784 */
3785 if (need_stable_symbols) {
3786 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3787
8d2f24ca 3788 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3789 switch (pipe) {
3790 case PIPE_A:
8d2f24ca 3791 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3792 break;
3793 case PIPE_B:
8d2f24ca 3794 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3795 break;
3796 case PIPE_C:
3797 tmp |= PIPE_C_SCRAMBLE_RESET;
3798 break;
3799 default:
3800 return -EINVAL;
3801 }
8d2f24ca
DV		 3802 I915_WRITE(PORT_DFT2_G4X, tmp);
3803 }
3804
7ac0129b
DV		 3805 return 0;
3806}
3807
4b79ebf7 3808static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3809 enum pipe pipe,
3810 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3811 uint32_t *val)
3812{
84093603
DV		 3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 bool need_stable_symbols = false;
3815
46a19188
DV		 3816 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3817 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3818 if (ret)
3819 return ret;
3820 }
3821
3822 switch (*source) {
4b79ebf7
DV		 3823 case INTEL_PIPE_CRC_SOURCE_PIPE:
3824 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3825 break;
3826 case INTEL_PIPE_CRC_SOURCE_TV:
3827 if (!SUPPORTS_TV(dev))
3828 return -EINVAL;
3829 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3830 break;
3831 case INTEL_PIPE_CRC_SOURCE_DP_B:
3832 if (!IS_G4X(dev))
3833 return -EINVAL;
3834 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3835 need_stable_symbols = true;
4b79ebf7
DV		 3836 break;
3837 case INTEL_PIPE_CRC_SOURCE_DP_C:
3838 if (!IS_G4X(dev))
3839 return -EINVAL;
3840 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3841 need_stable_symbols = true;
4b79ebf7
DV		 3842 break;
3843 case INTEL_PIPE_CRC_SOURCE_DP_D:
3844 if (!IS_G4X(dev))
3845 return -EINVAL;
3846 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3847 need_stable_symbols = true;
4b79ebf7
DV		 3848 break;
3849 case INTEL_PIPE_CRC_SOURCE_NONE:
3850 *val = 0;
3851 break;
3852 default:
3853 return -EINVAL;
3854 }
3855
84093603
DV		 3856 /*
3857 * When the pipe CRC tap point is after the transcoders we need
3858 * to tweak symbol-level features to produce a deterministic series of
3859 * symbols for a given frame. We need to reset those features only once
3860 * a frame (instead of every nth symbol):
3861 * - DC-balance: used to ensure a better clock recovery from the data
3862 * link (SDVO)
3863 * - DisplayPort scrambling: used for EMI reduction
3864 */
3865 if (need_stable_symbols) {
3866 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3867
3868 WARN_ON(!IS_G4X(dev));
3869
3870 I915_WRITE(PORT_DFT_I9XX,
3871 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3872
3873 if (pipe == PIPE_A)
3874 tmp |= PIPE_A_SCRAMBLE_RESET;
3875 else
3876 tmp |= PIPE_B_SCRAMBLE_RESET;
3877
3878 I915_WRITE(PORT_DFT2_G4X, tmp);
3879 }
3880
4b79ebf7
DV		 3881 return 0;
3882}
3883
8d2f24ca
DV		 3884static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3885 enum pipe pipe)
3886{
3887 struct drm_i915_private *dev_priv = dev->dev_private;
3888 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3889
eb736679
VS		 3890 switch (pipe) {
3891 case PIPE_A:
8d2f24ca 3892 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3893 break;
3894 case PIPE_B:
8d2f24ca 3895 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3896 break;
3897 case PIPE_C:
3898 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3899 break;
3900 default:
3901 return;
3902 }
8d2f24ca
DV		 3903 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3904 tmp &= ~DC_BALANCE_RESET_VLV;
3905 I915_WRITE(PORT_DFT2_G4X, tmp);
3906
3907}
3908
84093603
DV		 3909static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3910 enum pipe pipe)
3911{
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3914
3915 if (pipe == PIPE_A)
3916 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3917 else
3918 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3919 I915_WRITE(PORT_DFT2_G4X, tmp);
3920
3921 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3922 I915_WRITE(PORT_DFT_I9XX,
3923 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3924 }
3925}
3926
46a19188 3927static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3928 uint32_t *val)
3929{
46a19188
DV		 3930 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3931 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3932
3933 switch (*source) {
5b3a856b
DV		 3934 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3935 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3936 break;
3937 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3938 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3939 break;
5b3a856b
DV		 3940 case INTEL_PIPE_CRC_SOURCE_PIPE:
3941 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3942 break;
3d099a05 3943 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3944 *val = 0;
3945 break;
3d099a05
DV		 3946 default:
3947 return -EINVAL;
5b3a856b
DV		 3948 }
3949
3950 return 0;
3951}
3952
c4e2d043 3953static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
fabf6e51
DV		 3954{
3955 struct drm_i915_private *dev_priv = dev->dev_private;
3956 struct intel_crtc *crtc =
3957 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3958 struct intel_crtc_state *pipe_config;
c4e2d043
ML		 3959 struct drm_atomic_state *state;
3960 int ret = 0;
fabf6e51
DV		 3961
3962 drm_modeset_lock_all(dev);
c4e2d043
ML		 3963 state = drm_atomic_state_alloc(dev);
3964 if (!state) {
3965 ret = -ENOMEM;
3966 goto out;
fabf6e51 3967 }
fabf6e51 3968
c4e2d043
ML		 3969 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3970 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3971 if (IS_ERR(pipe_config)) {
3972 ret = PTR_ERR(pipe_config);
3973 goto out;
3974 }
fabf6e51 3975
c4e2d043
ML		 3976 pipe_config->pch_pfit.force_thru = enable;
3977 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3978 pipe_config->pch_pfit.enabled != enable)
3979 pipe_config->base.connectors_changed = true;
1b509259 3980
c4e2d043
ML		 3981 ret = drm_atomic_commit(state);
3982out:
fabf6e51 3983 drm_modeset_unlock_all(dev);
c4e2d043
ML		 3984 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3985 if (ret)
3986 drm_atomic_state_free(state);
fabf6e51
DV		 3987}
3988
3989static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3990 enum pipe pipe,
3991 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3992 uint32_t *val)
3993{
46a19188
DV		 3994 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3995 *source = INTEL_PIPE_CRC_SOURCE_PF;
3996
3997 switch (*source) {
5b3a856b
DV		 3998 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3999 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4000 break;
4001 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4002 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4003 break;
4004 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51 4005 if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4006 hsw_trans_edp_pipe_A_crc_wa(dev, true);
fabf6e51 4007
5b3a856b
DV		 4008 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4009 break;
3d099a05 4010 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 4011 *val = 0;
4012 break;
3d099a05
DV		 4013 default:
4014 return -EINVAL;
5b3a856b
DV		 4015 }
4016
4017 return 0;
4018}
4019
926321d5
DV		 4020static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4021 enum intel_pipe_crc_source source)
4022{
4023 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 4024 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 4025 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4026 pipe));
432f3342 4027 u32 val = 0; /* shut up gcc */
5b3a856b 4028 int ret;
926321d5 4029
cc3da175
DL		 4030 if (pipe_crc->source == source)
4031 return 0;
4032
ae676fcd
DL		 4033 /* forbid changing the source without going back to 'none' */
4034 if (pipe_crc->source && source)
4035 return -EINVAL;
4036
9d8b0588
DV		 4037 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
4038 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4039 return -EIO;
4040 }
4041
52f843f6 4042 if (IS_GEN2(dev))
46a19188 4043 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 4044 else if (INTEL_INFO(dev)->gen < 5)
46a19188 4045 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 4046 else if (IS_VALLEYVIEW(dev))
fabf6e51 4047 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 4048 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 4049 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 4050 else
fabf6e51 4051 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 4052
4053 if (ret != 0)
4054 return ret;
4055
4b584369
DL		 4056 /* none -> real source transition */
4057 if (source) {
4252fbc3
VS		 4058 struct intel_pipe_crc_entry *entries;
4059
7cd6ccff
DL		 4060 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4061 pipe_name(pipe), pipe_crc_source_name(source));
4062
3cf54b34
VS		 4063 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4064 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 4065 GFP_KERNEL);
4066 if (!entries)
e5f75aca
DL		 4067 return -ENOMEM;
4068
8c740dce
PZ		 4069 /*
4070 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4071 * enabled and disabled dynamically based on package C states,
4072 * user space can't make reliable use of the CRCs, so let's just
4073 * completely disable it.
4074 */
4075 hsw_disable_ips(crtc);
4076
d538bbdf 4077 spin_lock_irq(&pipe_crc->lock);
64387b61 4078 kfree(pipe_crc->entries);
4252fbc3 4079 pipe_crc->entries = entries;
d538bbdf
DL		 4080 pipe_crc->head = 0;
4081 pipe_crc->tail = 0;
4082 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 4083 }
4084
cc3da175 4085 pipe_crc->source = source;
926321d5 4086
926321d5
DV		 4087 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4088 POSTING_READ(PIPE_CRC_CTL(pipe));
4089
e5f75aca
DL		 4090 /* real source -> none transition */
4091 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 4092 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 4093 struct intel_crtc *crtc =
4094 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 4095
7cd6ccff
DL		 4096 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4097 pipe_name(pipe));
4098
a33d7105 4099 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 4100 if (crtc->base.state->active)
a33d7105
DV		 4101 intel_wait_for_vblank(dev, pipe);
4102 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 4103
d538bbdf
DL		 4104 spin_lock_irq(&pipe_crc->lock);
4105 entries = pipe_crc->entries;
e5f75aca 4106 pipe_crc->entries = NULL;
9ad6d99f
VS		 4107 pipe_crc->head = 0;
4108 pipe_crc->tail = 0;
d538bbdf
DL		 4109 spin_unlock_irq(&pipe_crc->lock);
4110
4111 kfree(entries);
84093603
DV		 4112
4113 if (IS_G4X(dev))
4114 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 4115 else if (IS_VALLEYVIEW(dev))
4116 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51 4117 else if (IS_HASWELL(dev) && pipe == PIPE_A)
c4e2d043 4118 hsw_trans_edp_pipe_A_crc_wa(dev, false);
8c740dce
PZ		 4119
4120 hsw_enable_ips(crtc);
e5f75aca
DL		 4121 }
4122
926321d5
DV		 4123 return 0;
4124}
4125
4126/*
4127 * Parse pipe CRC command strings:
b94dec87
DL		 4128 * command: wsp* object wsp+ name wsp+ source wsp*
4129 * object: 'pipe'
4130 * name: (A | B | C)
926321d5
DV		 4131 * source: (none | plane1 | plane2 | pf)
4132 * wsp: (#0x20 | #0x9 | #0xA)+
4133 *
4134 * eg.:
b94dec87
DL		 4135 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4136 * "pipe A none" -> Stop CRC
926321d5 4137 */
bd9db02f 4138static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 4139{
4140 int n_words = 0;
4141
4142 while (*buf) {
4143 char *end;
4144
4145 /* skip leading white space */
4146 buf = skip_spaces(buf);
4147 if (!*buf)
4148 break; /* end of buffer */
4149
4150 /* find end of word */
4151 for (end = buf; *end && !isspace(*end); end++)
4152 ;
4153
4154 if (n_words == max_words) {
4155 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4156 max_words);
4157 return -EINVAL; /* ran out of words[] before bytes */
4158 }
4159
4160 if (*end)
4161 *end++ = '\0';
4162 words[n_words++] = buf;
4163 buf = end;
4164 }
4165
4166 return n_words;
4167}
4168
b94dec87
DL		 4169enum intel_pipe_crc_object {
4170 PIPE_CRC_OBJECT_PIPE,
4171};
4172
e8dfcf78 4173static const char * const pipe_crc_objects[] = {
b94dec87
DL		 4174 "pipe",
4175};
4176
4177static int
bd9db02f 4178display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 4179{
4180 int i;
4181
4182 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4183 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 4184 *o = i;
b94dec87
DL		 4185 return 0;
4186 }
4187
4188 return -EINVAL;
4189}
4190
bd9db02f 4191static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 4192{
4193 const char name = buf[0];
4194
4195 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4196 return -EINVAL;
4197
4198 *pipe = name - 'A';
4199
4200 return 0;
4201}
4202
4203static int
bd9db02f 4204display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 4205{
4206 int i;
4207
4208 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4209 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 4210 *s = i;
926321d5
DV		 4211 return 0;
4212 }
4213
4214 return -EINVAL;
4215}
4216
bd9db02f 4217static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 4218{
b94dec87 4219#define N_WORDS 3
926321d5 4220 int n_words;
b94dec87 4221 char *words[N_WORDS];
926321d5 4222 enum pipe pipe;
b94dec87 4223 enum intel_pipe_crc_object object;
926321d5
DV		 4224 enum intel_pipe_crc_source source;
4225
bd9db02f 4226 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 4227 if (n_words != N_WORDS) {
4228 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4229 N_WORDS);
4230 return -EINVAL;
4231 }
4232
bd9db02f 4233 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 4234 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 4235 return -EINVAL;
4236 }
4237
bd9db02f 4238 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 4239 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 4240 return -EINVAL;
4241 }
4242
bd9db02f 4243 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 4244 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 4245 return -EINVAL;
4246 }
4247
4248 return pipe_crc_set_source(dev, pipe, source);
4249}
4250
bd9db02f
DL		 4251static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4252 size_t len, loff_t *offp)
926321d5
DV		 4253{
4254 struct seq_file *m = file->private_data;
4255 struct drm_device *dev = m->private;
4256 char *tmpbuf;
4257 int ret;
4258
4259 if (len == 0)
4260 return 0;
4261
4262 if (len > PAGE_SIZE - 1) {
4263 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4264 PAGE_SIZE);
4265 return -E2BIG;
4266 }
4267
4268 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4269 if (!tmpbuf)
4270 return -ENOMEM;
4271
4272 if (copy_from_user(tmpbuf, ubuf, len)) {
4273 ret = -EFAULT;
4274 goto out;
4275 }
4276 tmpbuf[len] = '\0';
4277
bd9db02f 4278 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4279
4280out:
4281 kfree(tmpbuf);
4282 if (ret < 0)
4283 return ret;
4284
4285 *offp += len;
4286 return len;
4287}
4288
bd9db02f 4289static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4290 .owner = THIS_MODULE,
bd9db02f 4291 .open = display_crc_ctl_open,
926321d5
DV		 4292 .read = seq_read,
4293 .llseek = seq_lseek,
4294 .release = single_release,
bd9db02f 4295 .write = display_crc_ctl_write
926321d5
DV		 4296};
4297
eb3394fa
TP		 4298static ssize_t i915_displayport_test_active_write(struct file *file,
4299 const char __user *ubuf,
4300 size_t len, loff_t *offp)
4301{
4302 char *input_buffer;
4303 int status = 0;
eb3394fa
TP		 4304 struct drm_device *dev;
4305 struct drm_connector *connector;
4306 struct list_head *connector_list;
4307 struct intel_dp *intel_dp;
4308 int val = 0;
4309
9aaffa34 4310 dev = ((struct seq_file *)file->private_data)->private;
eb3394fa 4311
eb3394fa
TP		 4312 connector_list = &dev->mode_config.connector_list;
4313
4314 if (len == 0)
4315 return 0;
4316
4317 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4318 if (!input_buffer)
4319 return -ENOMEM;
4320
4321 if (copy_from_user(input_buffer, ubuf, len)) {
4322 status = -EFAULT;
4323 goto out;
4324 }
4325
4326 input_buffer[len] = '\0';
4327 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4328
4329 list_for_each_entry(connector, connector_list, head) {
4330
4331 if (connector->connector_type !=
4332 DRM_MODE_CONNECTOR_DisplayPort)
4333 continue;
4334
b8bb08ec 4335 if (connector->status == connector_status_connected &&
eb3394fa
TP		 4336 connector->encoder != NULL) {
4337 intel_dp = enc_to_intel_dp(connector->encoder);
4338 status = kstrtoint(input_buffer, 10, &val);
4339 if (status < 0)
4340 goto out;
4341 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4342 /* To prevent erroneous activation of the compliance
4343 * testing code, only accept an actual value of 1 here
4344 */
4345 if (val == 1)
4346 intel_dp->compliance_test_active = 1;
4347 else
4348 intel_dp->compliance_test_active = 0;
4349 }
4350 }
4351out:
4352 kfree(input_buffer);
4353 if (status < 0)
4354 return status;
4355
4356 *offp += len;
4357 return len;
4358}
4359
4360static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4361{
4362 struct drm_device *dev = m->private;
4363 struct drm_connector *connector;
4364 struct list_head *connector_list = &dev->mode_config.connector_list;
4365 struct intel_dp *intel_dp;
4366
eb3394fa
TP		 4367 list_for_each_entry(connector, connector_list, head) {
4368
4369 if (connector->connector_type !=
4370 DRM_MODE_CONNECTOR_DisplayPort)
4371 continue;
4372
4373 if (connector->status == connector_status_connected &&
4374 connector->encoder != NULL) {
4375 intel_dp = enc_to_intel_dp(connector->encoder);
4376 if (intel_dp->compliance_test_active)
4377 seq_puts(m, "1");
4378 else
4379 seq_puts(m, "0");
4380 } else
4381 seq_puts(m, "0");
4382 }
4383
4384 return 0;
4385}
4386
4387static int i915_displayport_test_active_open(struct inode *inode,
4388 struct file *file)
4389{
4390 struct drm_device *dev = inode->i_private;
4391
4392 return single_open(file, i915_displayport_test_active_show, dev);
4393}
4394
4395static const struct file_operations i915_displayport_test_active_fops = {
4396 .owner = THIS_MODULE,
4397 .open = i915_displayport_test_active_open,
4398 .read = seq_read,
4399 .llseek = seq_lseek,
4400 .release = single_release,
4401 .write = i915_displayport_test_active_write
4402};
4403
4404static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4405{
4406 struct drm_device *dev = m->private;
4407 struct drm_connector *connector;
4408 struct list_head *connector_list = &dev->mode_config.connector_list;
4409 struct intel_dp *intel_dp;
4410
eb3394fa
TP		 4411 list_for_each_entry(connector, connector_list, head) {
4412
4413 if (connector->connector_type !=
4414 DRM_MODE_CONNECTOR_DisplayPort)
4415 continue;
4416
4417 if (connector->status == connector_status_connected &&
4418 connector->encoder != NULL) {
4419 intel_dp = enc_to_intel_dp(connector->encoder);
4420 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4421 } else
4422 seq_puts(m, "0");
4423 }
4424
4425 return 0;
4426}
4427static int i915_displayport_test_data_open(struct inode *inode,
4428 struct file *file)
4429{
4430 struct drm_device *dev = inode->i_private;
4431
4432 return single_open(file, i915_displayport_test_data_show, dev);
4433}
4434
4435static const struct file_operations i915_displayport_test_data_fops = {
4436 .owner = THIS_MODULE,
4437 .open = i915_displayport_test_data_open,
4438 .read = seq_read,
4439 .llseek = seq_lseek,
4440 .release = single_release
4441};
4442
4443static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4444{
4445 struct drm_device *dev = m->private;
4446 struct drm_connector *connector;
4447 struct list_head *connector_list = &dev->mode_config.connector_list;
4448 struct intel_dp *intel_dp;
4449
eb3394fa
TP		 4450 list_for_each_entry(connector, connector_list, head) {
4451
4452 if (connector->connector_type !=
4453 DRM_MODE_CONNECTOR_DisplayPort)
4454 continue;
4455
4456 if (connector->status == connector_status_connected &&
4457 connector->encoder != NULL) {
4458 intel_dp = enc_to_intel_dp(connector->encoder);
4459 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4460 } else
4461 seq_puts(m, "0");
4462 }
4463
4464 return 0;
4465}
4466
4467static int i915_displayport_test_type_open(struct inode *inode,
4468 struct file *file)
4469{
4470 struct drm_device *dev = inode->i_private;
4471
4472 return single_open(file, i915_displayport_test_type_show, dev);
4473}
4474
4475static const struct file_operations i915_displayport_test_type_fops = {
4476 .owner = THIS_MODULE,
4477 .open = i915_displayport_test_type_open,
4478 .read = seq_read,
4479 .llseek = seq_lseek,
4480 .release = single_release
4481};
4482
97e94b22 4483static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4484{
4485 struct drm_device *dev = m->private;
369a1342 4486 int level;
de38b95c
VS		 4487 int num_levels;
4488
4489 if (IS_CHERRYVIEW(dev))
4490 num_levels = 3;
4491 else if (IS_VALLEYVIEW(dev))
4492 num_levels = 1;
4493 else
4494 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4495
4496 drm_modeset_lock_all(dev);
4497
4498 for (level = 0; level < num_levels; level++) {
4499 unsigned int latency = wm[level];
4500
97e94b22
DL		 4501 /*
4502 * - WM1+ latency values in 0.5us units
de38b95c 4503 * - latencies are in us on gen9/vlv/chv
97e94b22 4504 */
de38b95c 4505 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
97e94b22
DL		 4506 latency *= 10;
4507 else if (level > 0)
369a1342
VS		 4508 latency *= 5;
4509
4510 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4511 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4512 }
4513
4514 drm_modeset_unlock_all(dev);
4515}
4516
4517static int pri_wm_latency_show(struct seq_file *m, void *data)
4518{
4519 struct drm_device *dev = m->private;
97e94b22
DL		 4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521 const uint16_t *latencies;
4522
4523 if (INTEL_INFO(dev)->gen >= 9)
4524 latencies = dev_priv->wm.skl_latency;
4525 else
4526 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4527
97e94b22 4528 wm_latency_show(m, latencies);
369a1342
VS		 4529
4530 return 0;
4531}
4532
4533static int spr_wm_latency_show(struct seq_file *m, void *data)
4534{
4535 struct drm_device *dev = m->private;
97e94b22
DL		 4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 const uint16_t *latencies;
4538
4539 if (INTEL_INFO(dev)->gen >= 9)
4540 latencies = dev_priv->wm.skl_latency;
4541 else
4542 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4543
97e94b22 4544 wm_latency_show(m, latencies);
369a1342
VS		 4545
4546 return 0;
4547}
4548
4549static int cur_wm_latency_show(struct seq_file *m, void *data)
4550{
4551 struct drm_device *dev = m->private;
97e94b22
DL		 4552 struct drm_i915_private *dev_priv = dev->dev_private;
4553 const uint16_t *latencies;
4554
4555 if (INTEL_INFO(dev)->gen >= 9)
4556 latencies = dev_priv->wm.skl_latency;
4557 else
4558 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4559
97e94b22 4560 wm_latency_show(m, latencies);
369a1342
VS		 4561
4562 return 0;
4563}
4564
4565static int pri_wm_latency_open(struct inode *inode, struct file *file)
4566{
4567 struct drm_device *dev = inode->i_private;
4568
de38b95c 4569 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4570 return -ENODEV;
4571
4572 return single_open(file, pri_wm_latency_show, dev);
4573}
4574
4575static int spr_wm_latency_open(struct inode *inode, struct file *file)
4576{
4577 struct drm_device *dev = inode->i_private;
4578
9ad0257c 4579 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4580 return -ENODEV;
4581
4582 return single_open(file, spr_wm_latency_show, dev);
4583}
4584
4585static int cur_wm_latency_open(struct inode *inode, struct file *file)
4586{
4587 struct drm_device *dev = inode->i_private;
4588
9ad0257c 4589 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4590 return -ENODEV;
4591
4592 return single_open(file, cur_wm_latency_show, dev);
4593}
4594
4595static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4596 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4597{
4598 struct seq_file *m = file->private_data;
4599 struct drm_device *dev = m->private;
97e94b22 4600 uint16_t new[8] = { 0 };
de38b95c 4601 int num_levels;
369a1342
VS		 4602 int level;
4603 int ret;
4604 char tmp[32];
4605
de38b95c
VS		 4606 if (IS_CHERRYVIEW(dev))
4607 num_levels = 3;
4608 else if (IS_VALLEYVIEW(dev))
4609 num_levels = 1;
4610 else
4611 num_levels = ilk_wm_max_level(dev) + 1;
4612
369a1342
VS		 4613 if (len >= sizeof(tmp))
4614 return -EINVAL;
4615
4616 if (copy_from_user(tmp, ubuf, len))
4617 return -EFAULT;
4618
4619 tmp[len] = '\0';
4620
97e94b22
DL		 4621 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4622 &new[0], &new[1], &new[2], &new[3],
4623 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4624 if (ret != num_levels)
4625 return -EINVAL;
4626
4627 drm_modeset_lock_all(dev);
4628
4629 for (level = 0; level < num_levels; level++)
4630 wm[level] = new[level];
4631
4632 drm_modeset_unlock_all(dev);
4633
4634 return len;
4635}
4636
4637
4638static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4639 size_t len, loff_t *offp)
4640{
4641 struct seq_file *m = file->private_data;
4642 struct drm_device *dev = m->private;
97e94b22
DL		 4643 struct drm_i915_private *dev_priv = dev->dev_private;
4644 uint16_t *latencies;
369a1342 4645
97e94b22
DL		 4646 if (INTEL_INFO(dev)->gen >= 9)
4647 latencies = dev_priv->wm.skl_latency;
4648 else
4649 latencies = to_i915(dev)->wm.pri_latency;
4650
4651 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4652}
4653
4654static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4655 size_t len, loff_t *offp)
4656{
4657 struct seq_file *m = file->private_data;
4658 struct drm_device *dev = m->private;
97e94b22
DL		 4659 struct drm_i915_private *dev_priv = dev->dev_private;
4660 uint16_t *latencies;
369a1342 4661
97e94b22
DL		 4662 if (INTEL_INFO(dev)->gen >= 9)
4663 latencies = dev_priv->wm.skl_latency;
4664 else
4665 latencies = to_i915(dev)->wm.spr_latency;
4666
4667 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4668}
4669
4670static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4671 size_t len, loff_t *offp)
4672{
4673 struct seq_file *m = file->private_data;
4674 struct drm_device *dev = m->private;
97e94b22
DL		 4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 uint16_t *latencies;
4677
4678 if (INTEL_INFO(dev)->gen >= 9)
4679 latencies = dev_priv->wm.skl_latency;
4680 else
4681 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4682
97e94b22 4683 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4684}
4685
4686static const struct file_operations i915_pri_wm_latency_fops = {
4687 .owner = THIS_MODULE,
4688 .open = pri_wm_latency_open,
4689 .read = seq_read,
4690 .llseek = seq_lseek,
4691 .release = single_release,
4692 .write = pri_wm_latency_write
4693};
4694
4695static const struct file_operations i915_spr_wm_latency_fops = {
4696 .owner = THIS_MODULE,
4697 .open = spr_wm_latency_open,
4698 .read = seq_read,
4699 .llseek = seq_lseek,
4700 .release = single_release,
4701 .write = spr_wm_latency_write
4702};
4703
4704static const struct file_operations i915_cur_wm_latency_fops = {
4705 .owner = THIS_MODULE,
4706 .open = cur_wm_latency_open,
4707 .read = seq_read,
4708 .llseek = seq_lseek,
4709 .release = single_release,
4710 .write = cur_wm_latency_write
4711};
4712
647416f9
KC		 4713static int
4714i915_wedged_get(void *data, u64 *val)
f3cd474b 4715{
647416f9 4716 struct drm_device *dev = data;
e277a1f8 4717 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4718
647416f9 4719 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4720
647416f9 4721 return 0;
f3cd474b
CW		 4722}
4723
647416f9
KC		 4724static int
4725i915_wedged_set(void *data, u64 val)
f3cd474b 4726{
647416f9 4727 struct drm_device *dev = data;
d46c0517
ID		 4728 struct drm_i915_private *dev_priv = dev->dev_private;
4729
b8d24a06
MK		 4730 /*
4731 * There is no safeguard against this debugfs entry colliding
4732 * with the hangcheck calling same i915_handle_error() in
4733 * parallel, causing an explosion. For now we assume that the
4734 * test harness is responsible enough not to inject gpu hangs
4735 * while it is writing to 'i915_wedged'
4736 */
4737
4738 if (i915_reset_in_progress(&dev_priv->gpu_error))
4739 return -EAGAIN;
4740
d46c0517 4741 intel_runtime_pm_get(dev_priv);
f3cd474b 4742
58174462
MK		 4743 i915_handle_error(dev, val,
4744 "Manually setting wedged to %llu", val);
d46c0517
ID		 4745
4746 intel_runtime_pm_put(dev_priv);
4747
647416f9 4748 return 0;
f3cd474b
CW		 4749}
4750
647416f9
KC		 4751DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4752 i915_wedged_get, i915_wedged_set,
3a3b4f98 4753 "%llu\n");
f3cd474b 4754
647416f9
KC		 4755static int
4756i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4757{
647416f9 4758 struct drm_device *dev = data;
e277a1f8 4759 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4760
647416f9 4761 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4762
647416f9 4763 return 0;
e5eb3d63
DV		 4764}
4765
647416f9
KC		 4766static int
4767i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4768{
647416f9 4769 struct drm_device *dev = data;
e5eb3d63 4770 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4771 int ret;
e5eb3d63 4772
647416f9 4773 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4774
22bcfc6a
DV		 4775 ret = mutex_lock_interruptible(&dev->struct_mutex);
4776 if (ret)
4777 return ret;
4778
99584db3 4779 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4780 mutex_unlock(&dev->struct_mutex);
4781
647416f9 4782 return 0;
e5eb3d63
DV		 4783}
4784
647416f9
KC		 4785DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4786 i915_ring_stop_get, i915_ring_stop_set,
4787 "0x%08llx\n");
d5442303 4788
094f9a54
CW		 4789static int
4790i915_ring_missed_irq_get(void *data, u64 *val)
4791{
4792 struct drm_device *dev = data;
4793 struct drm_i915_private *dev_priv = dev->dev_private;
4794
4795 *val = dev_priv->gpu_error.missed_irq_rings;
4796 return 0;
4797}
4798
4799static int
4800i915_ring_missed_irq_set(void *data, u64 val)
4801{
4802 struct drm_device *dev = data;
4803 struct drm_i915_private *dev_priv = dev->dev_private;
4804 int ret;
4805
4806 /* Lock against concurrent debugfs callers */
4807 ret = mutex_lock_interruptible(&dev->struct_mutex);
4808 if (ret)
4809 return ret;
4810 dev_priv->gpu_error.missed_irq_rings = val;
4811 mutex_unlock(&dev->struct_mutex);
4812
4813 return 0;
4814}
4815
4816DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4817 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4818 "0x%08llx\n");
4819
4820static int
4821i915_ring_test_irq_get(void *data, u64 *val)
4822{
4823 struct drm_device *dev = data;
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4825
4826 *val = dev_priv->gpu_error.test_irq_rings;
4827
4828 return 0;
4829}
4830
4831static int
4832i915_ring_test_irq_set(void *data, u64 val)
4833{
4834 struct drm_device *dev = data;
4835 struct drm_i915_private *dev_priv = dev->dev_private;
4836 int ret;
4837
4838 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4839
4840 /* Lock against concurrent debugfs callers */
4841 ret = mutex_lock_interruptible(&dev->struct_mutex);
4842 if (ret)
4843 return ret;
4844
4845 dev_priv->gpu_error.test_irq_rings = val;
4846 mutex_unlock(&dev->struct_mutex);
4847
4848 return 0;
4849}
4850
4851DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4852 i915_ring_test_irq_get, i915_ring_test_irq_set,
4853 "0x%08llx\n");
4854
dd624afd
CW		 4855#define DROP_UNBOUND 0x1
4856#define DROP_BOUND 0x2
4857#define DROP_RETIRE 0x4
4858#define DROP_ACTIVE 0x8
4859#define DROP_ALL (DROP_UNBOUND | \
4860 DROP_BOUND | \
4861 DROP_RETIRE | \
4862 DROP_ACTIVE)
647416f9
KC		 4863static int
4864i915_drop_caches_get(void *data, u64 *val)
dd624afd 4865{
647416f9 4866 *val = DROP_ALL;
dd624afd 4867
647416f9 4868 return 0;
dd624afd
CW		 4869}
4870
647416f9
KC		 4871static int
4872i915_drop_caches_set(void *data, u64 val)
dd624afd 4873{
647416f9 4874 struct drm_device *dev = data;
dd624afd 4875 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4876 int ret;
dd624afd 4877
2f9fe5ff 4878 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4879
4880 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4881 * on ioctls on -EAGAIN. */
4882 ret = mutex_lock_interruptible(&dev->struct_mutex);
4883 if (ret)
4884 return ret;
4885
4886 if (val & DROP_ACTIVE) {
4887 ret = i915_gpu_idle(dev);
4888 if (ret)
4889 goto unlock;
4890 }
4891
4892 if (val & (DROP_RETIRE | DROP_ACTIVE))
4893 i915_gem_retire_requests(dev);
4894
21ab4e74
CW		 4895 if (val & DROP_BOUND)
4896 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4897
21ab4e74
CW		 4898 if (val & DROP_UNBOUND)
4899 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4900
4901unlock:
4902 mutex_unlock(&dev->struct_mutex);
4903
647416f9 4904 return ret;
dd624afd
CW		 4905}
4906
647416f9
KC		 4907DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4908 i915_drop_caches_get, i915_drop_caches_set,
4909 "0x%08llx\n");
dd624afd 4910
647416f9
KC		 4911static int
4912i915_max_freq_get(void *data, u64 *val)
358733e9 4913{
647416f9 4914 struct drm_device *dev = data;
e277a1f8 4915 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4916 int ret;
004777cb 4917
daa3afb2 4918 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4919 return -ENODEV;
4920
5c9669ce
TR		 4921 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4922
4fc688ce 4923 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4924 if (ret)
4925 return ret;
358733e9 4926
7c59a9c1 4927 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4928 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4929
647416f9 4930 return 0;
358733e9
JB		 4931}
4932
647416f9
KC		 4933static int
4934i915_max_freq_set(void *data, u64 val)
358733e9 4935{
647416f9 4936 struct drm_device *dev = data;
358733e9 4937 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4938 u32 hw_max, hw_min;
647416f9 4939 int ret;
004777cb 4940
daa3afb2 4941 if (INTEL_INFO(dev)->gen < 6)
004777cb 4942 return -ENODEV;
358733e9 4943
5c9669ce
TR		 4944 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4945
647416f9 4946 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4947
4fc688ce 4948 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4949 if (ret)
4950 return ret;
4951
358733e9
JB		 4952 /*
4953 * Turbo will still be enabled, but won't go above the set value.
4954 */
bc4d91f6 4955 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4956
bc4d91f6
AG		 4957 hw_max = dev_priv->rps.max_freq;
4958 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4959
b39fb297 4960 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4961 mutex_unlock(&dev_priv->rps.hw_lock);
4962 return -EINVAL;
0a073b84
JB		 4963 }
4964
b39fb297 4965 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4966
ffe02b40 4967 intel_set_rps(dev, val);
dd0a1aa1 4968
4fc688ce 4969 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4970
647416f9 4971 return 0;
358733e9
JB		 4972}
4973
647416f9
KC		 4974DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4975 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4976 "%llu\n");
358733e9 4977
647416f9
KC		 4978static int
4979i915_min_freq_get(void *data, u64 *val)
1523c310 4980{
647416f9 4981 struct drm_device *dev = data;
e277a1f8 4982 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4983 int ret;
004777cb 4984
daa3afb2 4985 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4986 return -ENODEV;
4987
5c9669ce
TR		 4988 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4989
4fc688ce 4990 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4991 if (ret)
4992 return ret;
1523c310 4993
7c59a9c1 4994 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4995 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4996
647416f9 4997 return 0;
1523c310
JB		 4998}
4999
647416f9
KC		 5000static int
5001i915_min_freq_set(void *data, u64 val)
1523c310 5002{
647416f9 5003 struct drm_device *dev = data;
1523c310 5004 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 5005 u32 hw_max, hw_min;
647416f9 5006 int ret;
004777cb 5007
daa3afb2 5008 if (INTEL_INFO(dev)->gen < 6)
004777cb 5009 return -ENODEV;
1523c310 5010
5c9669ce
TR		 5011 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5012
647416f9 5013 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 5014
4fc688ce 5015 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 5016 if (ret)
5017 return ret;
5018
1523c310
JB		 5019 /*
5020 * Turbo will still be enabled, but won't go below the set value.
5021 */
bc4d91f6 5022 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 5023
bc4d91f6
AG		 5024 hw_max = dev_priv->rps.max_freq;
5025 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 5026
b39fb297 5027 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 5028 mutex_unlock(&dev_priv->rps.hw_lock);
5029 return -EINVAL;
0a073b84 5030 }
dd0a1aa1 5031
b39fb297 5032 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 5033
ffe02b40 5034 intel_set_rps(dev, val);
dd0a1aa1 5035
4fc688ce 5036 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 5037
647416f9 5038 return 0;
1523c310
JB		 5039}
5040
647416f9
KC		 5041DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5042 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 5043 "%llu\n");
1523c310 5044
647416f9
KC		 5045static int
5046i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 5047{
647416f9 5048 struct drm_device *dev = data;
e277a1f8 5049 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5050 u32 snpcr;
647416f9 5051 int ret;
07b7ddd9 5052
004777cb
DV		 5053 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5054 return -ENODEV;
5055
22bcfc6a
DV		 5056 ret = mutex_lock_interruptible(&dev->struct_mutex);
5057 if (ret)
5058 return ret;
c8c8fb33 5059 intel_runtime_pm_get(dev_priv);
22bcfc6a 5060
07b7ddd9 5061 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 5062
5063 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 5064 mutex_unlock(&dev_priv->dev->struct_mutex);
5065
647416f9 5066 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 5067
647416f9 5068 return 0;
07b7ddd9
JB		 5069}
5070
647416f9
KC		 5071static int
5072i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 5073{
647416f9 5074 struct drm_device *dev = data;
07b7ddd9 5075 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 5076 u32 snpcr;
07b7ddd9 5077
004777cb
DV		 5078 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5079 return -ENODEV;
5080
647416f9 5081 if (val > 3)
07b7ddd9
JB		 5082 return -EINVAL;
5083
c8c8fb33 5084 intel_runtime_pm_get(dev_priv);
647416f9 5085 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 5086
5087 /* Update the cache sharing policy here as well */
5088 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5089 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5090 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5091 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5092
c8c8fb33 5093 intel_runtime_pm_put(dev_priv);
647416f9 5094 return 0;
07b7ddd9
JB		 5095}
5096
647416f9
KC		 5097DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5098 i915_cache_sharing_get, i915_cache_sharing_set,
5099 "%llu\n");
07b7ddd9 5100
5d39525a
JM		 5101struct sseu_dev_status {
5102 unsigned int slice_total;
5103 unsigned int subslice_total;
5104 unsigned int subslice_per_slice;
5105 unsigned int eu_total;
5106 unsigned int eu_per_subslice;
5107};
5108
5109static void cherryview_sseu_device_status(struct drm_device *dev,
5110 struct sseu_dev_status *stat)
5111{
5112 struct drm_i915_private *dev_priv = dev->dev_private;
0a0b457f 5113 int ss_max = 2;
5d39525a
JM		 5114 int ss;
5115 u32 sig1[ss_max], sig2[ss_max];
5116
5117 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5118 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5119 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5120 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5121
5122 for (ss = 0; ss < ss_max; ss++) {
5123 unsigned int eu_cnt;
5124
5125 if (sig1[ss] & CHV_SS_PG_ENABLE)
5126 /* skip disabled subslice */
5127 continue;
5128
5129 stat->slice_total = 1;
5130 stat->subslice_per_slice++;
5131 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5132 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5133 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5134 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5135 stat->eu_total += eu_cnt;
5136 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5137 }
5138 stat->subslice_total = stat->subslice_per_slice;
5139}
5140
5141static void gen9_sseu_device_status(struct drm_device *dev,
5142 struct sseu_dev_status *stat)
5143{
5144 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 5145 int s_max = 3, ss_max = 4;
5d39525a
JM		 5146 int s, ss;
5147 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5148
1c046bc1
JM		 5149 /* BXT has a single slice and at most 3 subslices. */
5150 if (IS_BROXTON(dev)) {
5151 s_max = 1;
5152 ss_max = 3;
5153 }
5154
5155 for (s = 0; s < s_max; s++) {
5156 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5157 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5158 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5159 }
5160
5d39525a
JM		 5161 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5162 GEN9_PGCTL_SSA_EU19_ACK |
5163 GEN9_PGCTL_SSA_EU210_ACK |
5164 GEN9_PGCTL_SSA_EU311_ACK;
5165 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5166 GEN9_PGCTL_SSB_EU19_ACK |
5167 GEN9_PGCTL_SSB_EU210_ACK |
5168 GEN9_PGCTL_SSB_EU311_ACK;
5169
5170 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 5171 unsigned int ss_cnt = 0;
5172
5d39525a
JM		 5173 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5174 /* skip disabled slice */
5175 continue;
5176
5177 stat->slice_total++;
1c046bc1 5178
ef11bdb3 5179 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1c046bc1
JM		 5180 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5181
5d39525a
JM		 5182 for (ss = 0; ss < ss_max; ss++) {
5183 unsigned int eu_cnt;
5184
1c046bc1
JM		 5185 if (IS_BROXTON(dev) &&
5186 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5187 /* skip disabled subslice */
5188 continue;
5189
5190 if (IS_BROXTON(dev))
5191 ss_cnt++;
5192
5d39525a
JM		 5193 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5194 eu_mask[ss%2]);
5195 stat->eu_total += eu_cnt;
5196 stat->eu_per_subslice = max(stat->eu_per_subslice,
5197 eu_cnt);
5198 }
1c046bc1
JM		 5199
5200 stat->subslice_total += ss_cnt;
5201 stat->subslice_per_slice = max(stat->subslice_per_slice,
5202 ss_cnt);
5d39525a
JM		 5203 }
5204}
5205
91bedd34
ŁD		 5206static void broadwell_sseu_device_status(struct drm_device *dev,
5207 struct sseu_dev_status *stat)
5208{
5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210 int s;
5211 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5212
5213 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5214
5215 if (stat->slice_total) {
5216 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5217 stat->subslice_total = stat->slice_total *
5218 stat->subslice_per_slice;
5219 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5220 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5221
5222 /* subtract fused off EU(s) from enabled slice(s) */
5223 for (s = 0; s < stat->slice_total; s++) {
5224 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5225
5226 stat->eu_total -= hweight8(subslice_7eu);
5227 }
5228 }
5229}
5230
3873218f
JM		 5231static int i915_sseu_status(struct seq_file *m, void *unused)
5232{
5233 struct drm_info_node *node = (struct drm_info_node *) m->private;
5234 struct drm_device *dev = node->minor->dev;
5d39525a 5235 struct sseu_dev_status stat;
3873218f 5236
91bedd34 5237 if (INTEL_INFO(dev)->gen < 8)
3873218f
JM		 5238 return -ENODEV;
5239
5240 seq_puts(m, "SSEU Device Info\n");
5241 seq_printf(m, " Available Slice Total: %u\n",
5242 INTEL_INFO(dev)->slice_total);
5243 seq_printf(m, " Available Subslice Total: %u\n",
5244 INTEL_INFO(dev)->subslice_total);
5245 seq_printf(m, " Available Subslice Per Slice: %u\n",
5246 INTEL_INFO(dev)->subslice_per_slice);
5247 seq_printf(m, " Available EU Total: %u\n",
5248 INTEL_INFO(dev)->eu_total);
5249 seq_printf(m, " Available EU Per Subslice: %u\n",
5250 INTEL_INFO(dev)->eu_per_subslice);
5251 seq_printf(m, " Has Slice Power Gating: %s\n",
5252 yesno(INTEL_INFO(dev)->has_slice_pg));
5253 seq_printf(m, " Has Subslice Power Gating: %s\n",
5254 yesno(INTEL_INFO(dev)->has_subslice_pg));
5255 seq_printf(m, " Has EU Power Gating: %s\n",
5256 yesno(INTEL_INFO(dev)->has_eu_pg));
5257
7f992aba 5258 seq_puts(m, "SSEU Device Status\n");
5d39525a 5259 memset(&stat, 0, sizeof(stat));
5575f03a 5260 if (IS_CHERRYVIEW(dev)) {
5d39525a 5261 cherryview_sseu_device_status(dev, &stat);
91bedd34
ŁD		 5262 } else if (IS_BROADWELL(dev)) {
5263 broadwell_sseu_device_status(dev, &stat);
1c046bc1 5264 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 5265 gen9_sseu_device_status(dev, &stat);
7f992aba 5266 }
5d39525a
JM		 5267 seq_printf(m, " Enabled Slice Total: %u\n",
5268 stat.slice_total);
5269 seq_printf(m, " Enabled Subslice Total: %u\n",
5270 stat.subslice_total);
5271 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5272 stat.subslice_per_slice);
5273 seq_printf(m, " Enabled EU Total: %u\n",
5274 stat.eu_total);
5275 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5276 stat.eu_per_subslice);
7f992aba 5277
3873218f
JM		 5278 return 0;
5279}
5280
6d794d42
BW		 5281static int i915_forcewake_open(struct inode *inode, struct file *file)
5282{
5283 struct drm_device *dev = inode->i_private;
5284 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 5285
075edca4 5286 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5287 return 0;
5288
6daccb0b 5289 intel_runtime_pm_get(dev_priv);
59bad947 5290 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5291
5292 return 0;
5293}
5294
c43b5634 5295static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5296{
5297 struct drm_device *dev = inode->i_private;
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299
075edca4 5300 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5301 return 0;
5302
59bad947 5303 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5304 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5305
5306 return 0;
5307}
5308
5309static const struct file_operations i915_forcewake_fops = {
5310 .owner = THIS_MODULE,
5311 .open = i915_forcewake_open,
5312 .release = i915_forcewake_release,
5313};
5314
5315static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5316{
5317 struct drm_device *dev = minor->dev;
5318 struct dentry *ent;
5319
5320 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5321 S_IRUSR,
6d794d42
BW		 5322 root, dev,
5323 &i915_forcewake_fops);
f3c5fe97
WY		 5324 if (!ent)
5325 return -ENOMEM;
6d794d42 5326
8eb57294 5327 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5328}
5329
6a9c308d
DV		 5330static int i915_debugfs_create(struct dentry *root,
5331 struct drm_minor *minor,
5332 const char *name,
5333 const struct file_operations *fops)
07b7ddd9
JB		 5334{
5335 struct drm_device *dev = minor->dev;
5336 struct dentry *ent;
5337
6a9c308d 5338 ent = debugfs_create_file(name,
07b7ddd9
JB		 5339 S_IRUGO | S_IWUSR,
5340 root, dev,
6a9c308d 5341 fops);
f3c5fe97
WY		 5342 if (!ent)
5343 return -ENOMEM;
07b7ddd9 5344
6a9c308d 5345 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5346}
5347
06c5bf8c 5348static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5349 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5350 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5351 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5352 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5353 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5354 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5355 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5356 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5357 {"i915_gem_request", i915_gem_request_info, 0},
5358 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5359 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5360 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5361 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5362 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5363 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5364 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5365 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
8b417c26 5366 {"i915_guc_info", i915_guc_info, 0},
fdf5d357 5367 {"i915_guc_load_status", i915_guc_load_status_info, 0},
4c7e77fc 5368 {"i915_guc_log_dump", i915_guc_log_dump, 0},
adb4bd12 5369 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5370 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5371 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5372 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5373 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5374 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5375 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5376 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5377 {"i915_sr_status", i915_sr_status, 0},
44834a67 5378 {"i915_opregion", i915_opregion, 0},
37811fcc 5379 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5380 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5381 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5382 {"i915_execlists", i915_execlists, 0},
f65367b5 5383 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5384 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5385 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5386 {"i915_llc", i915_llc, 0},
e91fd8c6 5387 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5388 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5389 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5390 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5391 {"i915_power_domain_info", i915_power_domain_info, 0},
b7cec66d 5392 {"i915_dmc_info", i915_dmc_info, 0},
53f5e3ca 5393 {"i915_display_info", i915_display_info, 0},
e04934cf 5394 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5395 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5396 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5397 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5398 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5399 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5400 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5401 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5402};
27c202ad 5403#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5404
06c5bf8c 5405static const struct i915_debugfs_files {
34b9674c
DV		 5406 const char *name;
5407 const struct file_operations *fops;
5408} i915_debugfs_files[] = {
5409 {"i915_wedged", &i915_wedged_fops},
5410 {"i915_max_freq", &i915_max_freq_fops},
5411 {"i915_min_freq", &i915_min_freq_fops},
5412 {"i915_cache_sharing", &i915_cache_sharing_fops},
5413 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5414 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5415 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5416 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5417 {"i915_error_state", &i915_error_state_fops},
5418 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5419 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5420 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5421 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5422 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5423 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5424 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5425 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5426 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5427};
5428
07144428
DL		 5429void intel_display_crc_init(struct drm_device *dev)
5430{
5431 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5432 enum pipe pipe;
07144428 5433
055e393f 5434 for_each_pipe(dev_priv, pipe) {
b378360e 5435 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5436
d538bbdf
DL		 5437 pipe_crc->opened = false;
5438 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5439 init_waitqueue_head(&pipe_crc->wq);
5440 }
5441}
5442
27c202ad 5443int i915_debugfs_init(struct drm_minor *minor)
2017263e 5444{
34b9674c 5445 int ret, i;
f3cd474b 5446
6d794d42 5447 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5448 if (ret)
5449 return ret;
6a9c308d 5450
07144428
DL		 5451 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5452 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5453 if (ret)
5454 return ret;
5455 }
5456
34b9674c
DV		 5457 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5458 ret = i915_debugfs_create(minor->debugfs_root, minor,
5459 i915_debugfs_files[i].name,
5460 i915_debugfs_files[i].fops);
5461 if (ret)
5462 return ret;
5463 }
40633219 5464
27c202ad
BG		 5465 return drm_debugfs_create_files(i915_debugfs_list,
5466 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5467 minor->debugfs_root, minor);
5468}
5469
27c202ad 5470void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5471{
34b9674c
DV		 5472 int i;
5473
27c202ad
BG		 5474 drm_debugfs_remove_files(i915_debugfs_list,
5475 I915_DEBUGFS_ENTRIES, minor);
07144428 5476
6d794d42
BW		 5477 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5478 1, minor);
07144428 5479
e309a997 5480 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5481 struct drm_info_list *info_list =
5482 (struct drm_info_list *)&i915_pipe_crc_data[i];
5483
5484 drm_debugfs_remove_files(info_list, 1, minor);
5485 }
5486
34b9674c
DV		 5487 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5488 struct drm_info_list *info_list =
5489 (struct drm_info_list *) i915_debugfs_files[i].fops;
5490
5491 drm_debugfs_remove_files(info_list, 1, minor);
5492 }
2017263e 5493}
aa7471d2
JN		 5494
5495struct dpcd_block {
5496 /* DPCD dump start address. */
5497 unsigned int offset;
5498 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5499 unsigned int end;
5500 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5501 size_t size;
5502 /* Only valid for eDP. */
5503 bool edp;
5504};
5505
5506static const struct dpcd_block i915_dpcd_debug[] = {
5507 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5508 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5509 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5510 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5511 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5512 { .offset = DP_SET_POWER },
5513 { .offset = DP_EDP_DPCD_REV },
5514 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5515 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5516 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5517};
5518
5519static int i915_dpcd_show(struct seq_file *m, void *data)
5520{
5521 struct drm_connector *connector = m->private;
5522 struct intel_dp *intel_dp =
5523 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5524 uint8_t buf[16];
5525 ssize_t err;
5526 int i;
5527
5c1a8875
MK		 5528 if (connector->status != connector_status_connected)
5529 return -ENODEV;
5530
aa7471d2
JN		 5531 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5532 const struct dpcd_block *b = &i915_dpcd_debug[i];
5533 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5534
5535 if (b->edp &&
5536 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5537 continue;
5538
5539 /* low tech for now */
5540 if (WARN_ON(size > sizeof(buf)))
5541 continue;
5542
5543 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5544 if (err <= 0) {
5545 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5546 size, b->offset, err);
5547 continue;
5548 }
5549
5550 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5551 }
aa7471d2
JN		 5552
5553 return 0;
5554}
5555
5556static int i915_dpcd_open(struct inode *inode, struct file *file)
5557{
5558 return single_open(file, i915_dpcd_show, inode->i_private);
5559}
5560
5561static const struct file_operations i915_dpcd_fops = {
5562 .owner = THIS_MODULE,
5563 .open = i915_dpcd_open,
5564 .read = seq_read,
5565 .llseek = seq_lseek,
5566 .release = single_release,
5567};
5568
5569/**
5570 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5571 * @connector: pointer to a registered drm_connector
5572 *
5573 * Cleanup will be done by drm_connector_unregister() through a call to
5574 * drm_debugfs_connector_remove().
5575 *
5576 * Returns 0 on success, negative error codes on error.
5577 */
5578int i915_debugfs_connector_add(struct drm_connector *connector)
5579{
5580 struct dentry *root = connector->debugfs_entry;
5581
5582 /* The connector must have been registered beforehands. */
5583 if (!root)
5584 return -ENODEV;
5585
5586 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5587 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5588 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5589 &i915_dpcd_fops);
5590
5591 return 0;
5592}
Linux kernel - Deliverables
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