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drm/i915: Add provision to extend Golden context batch
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
baaa5cfb 99 if (obj->pin_display)
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
ca1543be
TU		 120static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
121{
122 u64 size = 0;
123 struct i915_vma *vma;
124
125 list_for_each_entry(vma, &obj->vma_list, vma_link) {
126 if (i915_is_ggtt(vma->vm) &&
127 drm_mm_node_allocated(&vma->node))
128 size += vma->node.size;
129 }
130
131 return size;
132}
133
37811fcc
CW		 134static void
135describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
136{
b4716185
CW		 137 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
138 struct intel_engine_cs *ring;
1d693bcc 139 struct i915_vma *vma;
d7f46fc4 140 int pin_count = 0;
b4716185 141 int i;
d7f46fc4 142
b4716185 143 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
37811fcc 144 &obj->base,
481a3d43 145 obj->active ? "*" : " ",
37811fcc
CW		 146 get_pin_flag(obj),
147 get_tiling_flag(obj),
1d693bcc 148 get_global_flag(obj),
a05a5862 149 obj->base.size / 1024,
37811fcc 150 obj->base.read_domains,
b4716185
CW		 151 obj->base.write_domain);
152 for_each_ring(ring, dev_priv, i)
153 seq_printf(m, "%x ",
154 i915_gem_request_get_seqno(obj->last_read_req[i]));
155 seq_printf(m, "] %x %x%s%s%s",
97b2a6a1
JH		 156 i915_gem_request_get_seqno(obj->last_write_req),
157 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 158 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 159 obj->dirty ? " dirty" : "",
160 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
161 if (obj->base.name)
162 seq_printf(m, " (name: %d)", obj->base.name);
ba0635ff 163 list_for_each_entry(vma, &obj->vma_list, vma_link) {
d7f46fc4
BW		 164 if (vma->pin_count > 0)
165 pin_count++;
ba0635ff
DC		 166 }
167 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 168 if (obj->pin_display)
169 seq_printf(m, " (display)");
37811fcc
CW		 170 if (obj->fence_reg != I915_FENCE_REG_NONE)
171 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc 172 list_for_each_entry(vma, &obj->vma_list, vma_link) {
8d2fdc3f
TU		 173 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
174 i915_is_ggtt(vma->vm) ? "g" : "pp",
175 vma->node.start, vma->node.size);
176 if (i915_is_ggtt(vma->vm))
177 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
1d693bcc 178 else
8d2fdc3f 179 seq_puts(m, ")");
1d693bcc 180 }
c1ad11fc 181 if (obj->stolen)
440fd528 182 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
30154650 183 if (obj->pin_display || obj->fault_mappable) {
6299f992 184 char s[3], *t = s;
30154650 185 if (obj->pin_display)
6299f992
CW		 186 *t++ = 'p';
187 if (obj->fault_mappable)
188 *t++ = 'f';
189 *t = '\0';
190 seq_printf(m, " (%s mappable)", s);
191 }
b4716185 192 if (obj->last_write_req != NULL)
41c52415 193 seq_printf(m, " (%s)",
b4716185 194 i915_gem_request_get_ring(obj->last_write_req)->name);
d5a81ef1
DV		 195 if (obj->frontbuffer_bits)
196 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 197}
198
273497e5 199static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 200{
ea0c76f8 201 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 202 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
203 seq_putc(m, ' ');
204}
205
433e12f7 206static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 207{
9f25d007 208 struct drm_info_node *node = m->private;
433e12f7
BG		 209 uintptr_t list = (uintptr_t) node->info_ent->data;
210 struct list_head *head;
2017263e 211 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 212 struct drm_i915_private *dev_priv = dev->dev_private;
213 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 214 struct i915_vma *vma;
c44ef60e 215 u64 total_obj_size, total_gtt_size;
8f2480fb 216 int count, ret;
de227ef0
CW		 217
218 ret = mutex_lock_interruptible(&dev->struct_mutex);
219 if (ret)
220 return ret;
2017263e 221
ca191b13 222 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 223 switch (list) {
224 case ACTIVE_LIST:
267f0c90 225 seq_puts(m, "Active:\n");
5cef07e1 226 head = &vm->active_list;
433e12f7
BG		 227 break;
228 case INACTIVE_LIST:
267f0c90 229 seq_puts(m, "Inactive:\n");
5cef07e1 230 head = &vm->inactive_list;
433e12f7 231 break;
433e12f7 232 default:
de227ef0
CW		 233 mutex_unlock(&dev->struct_mutex);
234 return -EINVAL;
2017263e 235 }
2017263e 236
8f2480fb 237 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 238 list_for_each_entry(vma, head, mm_list) {
239 seq_printf(m, " ");
240 describe_obj(m, vma->obj);
241 seq_printf(m, "\n");
242 total_obj_size += vma->obj->base.size;
243 total_gtt_size += vma->node.size;
8f2480fb 244 count++;
2017263e 245 }
de227ef0 246 mutex_unlock(&dev->struct_mutex);
5e118f41 247
c44ef60e 248 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
8f2480fb 249 count, total_obj_size, total_gtt_size);
2017263e
BG		 250 return 0;
251}
252
6d2b8885
CW		 253static int obj_rank_by_stolen(void *priv,
254 struct list_head *A, struct list_head *B)
255{
256 struct drm_i915_gem_object *a =
b25cb2f8 257 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 258 struct drm_i915_gem_object *b =
b25cb2f8 259 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 260
261 return a->stolen->start - b->stolen->start;
262}
263
264static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
265{
9f25d007 266 struct drm_info_node *node = m->private;
6d2b8885
CW		 267 struct drm_device *dev = node->minor->dev;
268 struct drm_i915_private *dev_priv = dev->dev_private;
269 struct drm_i915_gem_object *obj;
c44ef60e 270 u64 total_obj_size, total_gtt_size;
6d2b8885
CW		 271 LIST_HEAD(stolen);
272 int count, ret;
273
274 ret = mutex_lock_interruptible(&dev->struct_mutex);
275 if (ret)
276 return ret;
277
278 total_obj_size = total_gtt_size = count = 0;
279 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
280 if (obj->stolen == NULL)
281 continue;
282
b25cb2f8 283 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 284
285 total_obj_size += obj->base.size;
ca1543be 286 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
6d2b8885
CW		 287 count++;
288 }
289 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
290 if (obj->stolen == NULL)
291 continue;
292
b25cb2f8 293 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 294
295 total_obj_size += obj->base.size;
296 count++;
297 }
298 list_sort(NULL, &stolen, obj_rank_by_stolen);
299 seq_puts(m, "Stolen:\n");
300 while (!list_empty(&stolen)) {
b25cb2f8 301 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 302 seq_puts(m, " ");
303 describe_obj(m, obj);
304 seq_putc(m, '\n');
b25cb2f8 305 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 306 }
307 mutex_unlock(&dev->struct_mutex);
308
c44ef60e 309 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
6d2b8885
CW		 310 count, total_obj_size, total_gtt_size);
311 return 0;
312}
313
6299f992
CW		 314#define count_objects(list, member) do { \
315 list_for_each_entry(obj, list, member) { \
ca1543be 316 size += i915_gem_obj_total_ggtt_size(obj); \
6299f992
CW		 317 ++count; \
318 if (obj->map_and_fenceable) { \
f343c5f6 319 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 320 ++mappable_count; \
321 } \
322 } \
0206e353 323} while (0)
6299f992 324
2db8e9d6 325struct file_stats {
6313c204 326 struct drm_i915_file_private *file_priv;
c44ef60e
MK		 327 unsigned long count;
328 u64 total, unbound;
329 u64 global, shared;
330 u64 active, inactive;
2db8e9d6
CW		 331};
332
333static int per_file_stats(int id, void *ptr, void *data)
334{
335 struct drm_i915_gem_object *obj = ptr;
336 struct file_stats *stats = data;
6313c204 337 struct i915_vma *vma;
2db8e9d6
CW		 338
339 stats->count++;
340 stats->total += obj->base.size;
341
c67a17e9
CW		 342 if (obj->base.name || obj->base.dma_buf)
343 stats->shared += obj->base.size;
344
6313c204
CW		 345 if (USES_FULL_PPGTT(obj->base.dev)) {
346 list_for_each_entry(vma, &obj->vma_list, vma_link) {
347 struct i915_hw_ppgtt *ppgtt;
348
349 if (!drm_mm_node_allocated(&vma->node))
350 continue;
351
352 if (i915_is_ggtt(vma->vm)) {
353 stats->global += obj->base.size;
354 continue;
355 }
356
357 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 358 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 359 continue;
360
41c52415 361 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 362 stats->active += obj->base.size;
363 else
364 stats->inactive += obj->base.size;
365
366 return 0;
367 }
2db8e9d6 368 } else {
6313c204
CW		 369 if (i915_gem_obj_ggtt_bound(obj)) {
370 stats->global += obj->base.size;
41c52415 371 if (obj->active)
6313c204
CW		 372 stats->active += obj->base.size;
373 else
374 stats->inactive += obj->base.size;
375 return 0;
376 }
2db8e9d6
CW		 377 }
378
6313c204
CW		 379 if (!list_empty(&obj->global_list))
380 stats->unbound += obj->base.size;
381
2db8e9d6
CW		 382 return 0;
383}
384
b0da1b79
CW		 385#define print_file_stats(m, name, stats) do { \
386 if (stats.count) \
c44ef60e 387 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
b0da1b79
CW		 388 name, \
389 stats.count, \
390 stats.total, \
391 stats.active, \
392 stats.inactive, \
393 stats.global, \
394 stats.shared, \
395 stats.unbound); \
396} while (0)
493018dc
BV		 397
398static void print_batch_pool_stats(struct seq_file *m,
399 struct drm_i915_private *dev_priv)
400{
401 struct drm_i915_gem_object *obj;
402 struct file_stats stats;
06fbca71 403 struct intel_engine_cs *ring;
8d9d5744 404 int i, j;
493018dc
BV		 405
406 memset(&stats, 0, sizeof(stats));
407
06fbca71 408 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 409 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
410 list_for_each_entry(obj,
411 &ring->batch_pool.cache_list[j],
412 batch_pool_link)
413 per_file_stats(0, obj, &stats);
414 }
06fbca71 415 }
493018dc 416
b0da1b79 417 print_file_stats(m, "[k]batch pool", stats);
493018dc
BV		 418}
419
ca191b13
BW		 420#define count_vmas(list, member) do { \
421 list_for_each_entry(vma, list, member) { \
ca1543be 422 size += i915_gem_obj_total_ggtt_size(vma->obj); \
ca191b13
BW		 423 ++count; \
424 if (vma->obj->map_and_fenceable) { \
425 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
426 ++mappable_count; \
427 } \
428 } \
429} while (0)
430
431static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 432{
9f25d007 433 struct drm_info_node *node = m->private;
73aa808f
CW		 434 struct drm_device *dev = node->minor->dev;
435 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714 436 u32 count, mappable_count, purgeable_count;
c44ef60e 437 u64 size, mappable_size, purgeable_size;
6299f992 438 struct drm_i915_gem_object *obj;
5cef07e1 439 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 440 struct drm_file *file;
ca191b13 441 struct i915_vma *vma;
73aa808f
CW		 442 int ret;
443
444 ret = mutex_lock_interruptible(&dev->struct_mutex);
445 if (ret)
446 return ret;
447
6299f992
CW		 448 seq_printf(m, "%u objects, %zu bytes\n",
449 dev_priv->mm.object_count,
450 dev_priv->mm.object_memory);
451
452 size = count = mappable_size = mappable_count = 0;
35c20a60 453 count_objects(&dev_priv->mm.bound_list, global_list);
c44ef60e 454 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
6299f992
CW		 455 count, mappable_count, size, mappable_size);
456
457 size = count = mappable_size = mappable_count = 0;
ca191b13 458 count_vmas(&vm->active_list, mm_list);
c44ef60e 459 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
6299f992
CW		 460 count, mappable_count, size, mappable_size);
461
6299f992 462 size = count = mappable_size = mappable_count = 0;
ca191b13 463 count_vmas(&vm->inactive_list, mm_list);
c44ef60e 464 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
6299f992
CW		 465 count, mappable_count, size, mappable_size);
466
b7abb714 467 size = count = purgeable_size = purgeable_count = 0;
35c20a60 468 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 469 size += obj->base.size, ++count;
b7abb714
CW		 470 if (obj->madv == I915_MADV_DONTNEED)
471 purgeable_size += obj->base.size, ++purgeable_count;
472 }
c44ef60e 473 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
6c085a72 474
6299f992 475 size = count = mappable_size = mappable_count = 0;
35c20a60 476 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 477 if (obj->fault_mappable) {
f343c5f6 478 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 479 ++count;
480 }
30154650 481 if (obj->pin_display) {
f343c5f6 482 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 483 ++mappable_count;
484 }
b7abb714
CW		 485 if (obj->madv == I915_MADV_DONTNEED) {
486 purgeable_size += obj->base.size;
487 ++purgeable_count;
488 }
6299f992 489 }
c44ef60e 490 seq_printf(m, "%u purgeable objects, %llu bytes\n",
b7abb714 491 purgeable_count, purgeable_size);
c44ef60e 492 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
6299f992 493 mappable_count, mappable_size);
c44ef60e 494 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
6299f992
CW		 495 count, size);
496
c44ef60e 497 seq_printf(m, "%llu [%llu] gtt total\n",
853ba5d2 498 dev_priv->gtt.base.total,
c44ef60e 499 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 500
493018dc
BV		 501 seq_putc(m, '\n');
502 print_batch_pool_stats(m, dev_priv);
2db8e9d6
CW		 503 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
504 struct file_stats stats;
3ec2f427 505 struct task_struct *task;
2db8e9d6
CW		 506
507 memset(&stats, 0, sizeof(stats));
6313c204 508 stats.file_priv = file->driver_priv;
5b5ffff0 509 spin_lock(&file->table_lock);
2db8e9d6 510 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 511 spin_unlock(&file->table_lock);
3ec2f427
TH		 512 /*
513 * Although we have a valid reference on file->pid, that does
514 * not guarantee that the task_struct who called get_pid() is
515 * still alive (e.g. get_pid(current) => fork() => exit()).
516 * Therefore, we need to protect this ->comm access using RCU.
517 */
518 rcu_read_lock();
519 task = pid_task(file->pid, PIDTYPE_PID);
493018dc 520 print_file_stats(m, task ? task->comm : "<unknown>", stats);
3ec2f427 521 rcu_read_unlock();
2db8e9d6
CW		 522 }
523
73aa808f
CW		 524 mutex_unlock(&dev->struct_mutex);
525
526 return 0;
527}
528
aee56cff 529static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 530{
9f25d007 531 struct drm_info_node *node = m->private;
08c18323 532 struct drm_device *dev = node->minor->dev;
1b50247a 533 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 534 struct drm_i915_private *dev_priv = dev->dev_private;
535 struct drm_i915_gem_object *obj;
c44ef60e 536 u64 total_obj_size, total_gtt_size;
08c18323
CW		 537 int count, ret;
538
539 ret = mutex_lock_interruptible(&dev->struct_mutex);
540 if (ret)
541 return ret;
542
543 total_obj_size = total_gtt_size = count = 0;
35c20a60 544 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 545 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 546 continue;
547
267f0c90 548 seq_puts(m, " ");
08c18323 549 describe_obj(m, obj);
267f0c90 550 seq_putc(m, '\n');
08c18323 551 total_obj_size += obj->base.size;
ca1543be 552 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
08c18323
CW		 553 count++;
554 }
555
556 mutex_unlock(&dev->struct_mutex);
557
c44ef60e 558 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
08c18323
CW		 559 count, total_obj_size, total_gtt_size);
560
561 return 0;
562}
563
4e5359cd
SF		 564static int i915_gem_pageflip_info(struct seq_file *m, void *data)
565{
9f25d007 566 struct drm_info_node *node = m->private;
4e5359cd 567 struct drm_device *dev = node->minor->dev;
d6bbafa1 568 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 569 struct intel_crtc *crtc;
8a270ebf
DV		 570 int ret;
571
572 ret = mutex_lock_interruptible(&dev->struct_mutex);
573 if (ret)
574 return ret;
4e5359cd 575
d3fcc808 576 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 577 const char pipe = pipe_name(crtc->pipe);
578 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 579 struct intel_unpin_work *work;
580
5e2d7afc 581 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 582 work = crtc->unpin_work;
583 if (work == NULL) {
9db4a9c7 584 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 585 pipe, plane);
586 } else {
d6bbafa1
CW		 587 u32 addr;
588
e7d841ca 589 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 590 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 591 pipe, plane);
592 } else {
9db4a9c7 593 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 594 pipe, plane);
595 }
3a8a946e
DV		 596 if (work->flip_queued_req) {
597 struct intel_engine_cs *ring =
598 i915_gem_request_get_ring(work->flip_queued_req);
599
20e28fba 600 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
3a8a946e 601 ring->name,
f06cc1b9 602 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 603 dev_priv->next_seqno,
3a8a946e 604 ring->get_seqno(ring, true),
1b5a433a 605 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 606 } else
607 seq_printf(m, "Flip not associated with any ring\n");
608 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
609 work->flip_queued_vblank,
610 work->flip_ready_vblank,
1e3feefd 611 drm_crtc_vblank_count(&crtc->base));
4e5359cd 612 if (work->enable_stall_check)
267f0c90 613 seq_puts(m, "Stall check enabled, ");
4e5359cd 614 else
267f0c90 615 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 616 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 617
d6bbafa1
CW		 618 if (INTEL_INFO(dev)->gen >= 4)
619 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
620 else
621 addr = I915_READ(DSPADDR(crtc->plane));
622 seq_printf(m, "Current scanout address 0x%08x\n", addr);
623
4e5359cd 624 if (work->pending_flip_obj) {
d6bbafa1
CW		 625 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
626 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 627 }
628 }
5e2d7afc 629 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 630 }
631
8a270ebf
DV		 632 mutex_unlock(&dev->struct_mutex);
633
4e5359cd
SF		 634 return 0;
635}
636
493018dc
BV		 637static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
638{
639 struct drm_info_node *node = m->private;
640 struct drm_device *dev = node->minor->dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642 struct drm_i915_gem_object *obj;
06fbca71 643 struct intel_engine_cs *ring;
8d9d5744
CW		 644 int total = 0;
645 int ret, i, j;
493018dc
BV		 646
647 ret = mutex_lock_interruptible(&dev->struct_mutex);
648 if (ret)
649 return ret;
650
06fbca71 651 for_each_ring(ring, dev_priv, i) {
8d9d5744
CW		 652 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
653 int count;
654
655 count = 0;
656 list_for_each_entry(obj,
657 &ring->batch_pool.cache_list[j],
658 batch_pool_link)
659 count++;
660 seq_printf(m, "%s cache[%d]: %d objects\n",
661 ring->name, j, count);
662
663 list_for_each_entry(obj,
664 &ring->batch_pool.cache_list[j],
665 batch_pool_link) {
666 seq_puts(m, " ");
667 describe_obj(m, obj);
668 seq_putc(m, '\n');
669 }
670
671 total += count;
06fbca71 672 }
493018dc
BV		 673 }
674
8d9d5744 675 seq_printf(m, "total: %d\n", total);
493018dc
BV		 676
677 mutex_unlock(&dev->struct_mutex);
678
679 return 0;
680}
681
2017263e
BG		 682static int i915_gem_request_info(struct seq_file *m, void *data)
683{
9f25d007 684 struct drm_info_node *node = m->private;
2017263e 685 struct drm_device *dev = node->minor->dev;
e277a1f8 686 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 687 struct intel_engine_cs *ring;
eed29a5b 688 struct drm_i915_gem_request *req;
2d1070b2 689 int ret, any, i;
de227ef0
CW		 690
691 ret = mutex_lock_interruptible(&dev->struct_mutex);
692 if (ret)
693 return ret;
2017263e 694
2d1070b2 695 any = 0;
a2c7f6fd 696 for_each_ring(ring, dev_priv, i) {
2d1070b2
CW		 697 int count;
698
699 count = 0;
eed29a5b 700 list_for_each_entry(req, &ring->request_list, list)
2d1070b2
CW		 701 count++;
702 if (count == 0)
a2c7f6fd
CW		 703 continue;
704
2d1070b2 705 seq_printf(m, "%s requests: %d\n", ring->name, count);
eed29a5b 706 list_for_each_entry(req, &ring->request_list, list) {
2d1070b2
CW		 707 struct task_struct *task;
708
709 rcu_read_lock();
710 task = NULL;
eed29a5b
DV		 711 if (req->pid)
712 task = pid_task(req->pid, PIDTYPE_PID);
2d1070b2 713 seq_printf(m, " %x @ %d: %s [%d]\n",
eed29a5b
DV		 714 req->seqno,
715 (int) (jiffies - req->emitted_jiffies),
2d1070b2
CW		 716 task ? task->comm : "<unknown>",
717 task ? task->pid : -1);
718 rcu_read_unlock();
c2c347a9 719 }
2d1070b2
CW		 720
721 any++;
2017263e 722 }
de227ef0
CW		 723 mutex_unlock(&dev->struct_mutex);
724
2d1070b2 725 if (any == 0)
267f0c90 726 seq_puts(m, "No requests\n");
c2c347a9 727
2017263e
BG		 728 return 0;
729}
730
b2223497 731static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 732 struct intel_engine_cs *ring)
b2223497
CW		 733{
734 if (ring->get_seqno) {
20e28fba 735 seq_printf(m, "Current sequence (%s): %x\n",
b2eadbc8 736 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 737 }
738}
739
2017263e
BG		 740static int i915_gem_seqno_info(struct seq_file *m, void *data)
741{
9f25d007 742 struct drm_info_node *node = m->private;
2017263e 743 struct drm_device *dev = node->minor->dev;
e277a1f8 744 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 745 struct intel_engine_cs *ring;
1ec14ad3 746 int ret, i;
de227ef0
CW		 747
748 ret = mutex_lock_interruptible(&dev->struct_mutex);
749 if (ret)
750 return ret;
c8c8fb33 751 intel_runtime_pm_get(dev_priv);
2017263e 752
a2c7f6fd
CW		 753 for_each_ring(ring, dev_priv, i)
754 i915_ring_seqno_info(m, ring);
de227ef0 755
c8c8fb33 756 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 757 mutex_unlock(&dev->struct_mutex);
758
2017263e
BG		 759 return 0;
760}
761
762
763static int i915_interrupt_info(struct seq_file *m, void *data)
764{
9f25d007 765 struct drm_info_node *node = m->private;
2017263e 766 struct drm_device *dev = node->minor->dev;
e277a1f8 767 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 768 struct intel_engine_cs *ring;
9db4a9c7 769 int ret, i, pipe;
de227ef0
CW		 770
771 ret = mutex_lock_interruptible(&dev->struct_mutex);
772 if (ret)
773 return ret;
c8c8fb33 774 intel_runtime_pm_get(dev_priv);
2017263e 775
74e1ca8c 776 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 777 seq_printf(m, "Master Interrupt Control:\t%08x\n",
778 I915_READ(GEN8_MASTER_IRQ));
779
780 seq_printf(m, "Display IER:\t%08x\n",
781 I915_READ(VLV_IER));
782 seq_printf(m, "Display IIR:\t%08x\n",
783 I915_READ(VLV_IIR));
784 seq_printf(m, "Display IIR_RW:\t%08x\n",
785 I915_READ(VLV_IIR_RW));
786 seq_printf(m, "Display IMR:\t%08x\n",
787 I915_READ(VLV_IMR));
055e393f 788 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 789 seq_printf(m, "Pipe %c stat:\t%08x\n",
790 pipe_name(pipe),
791 I915_READ(PIPESTAT(pipe)));
792
793 seq_printf(m, "Port hotplug:\t%08x\n",
794 I915_READ(PORT_HOTPLUG_EN));
795 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
796 I915_READ(VLV_DPFLIPSTAT));
797 seq_printf(m, "DPINVGTT:\t%08x\n",
798 I915_READ(DPINVGTT));
799
800 for (i = 0; i < 4; i++) {
801 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
802 i, I915_READ(GEN8_GT_IMR(i)));
803 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
804 i, I915_READ(GEN8_GT_IIR(i)));
805 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
806 i, I915_READ(GEN8_GT_IER(i)));
807 }
808
809 seq_printf(m, "PCU interrupt mask:\t%08x\n",
810 I915_READ(GEN8_PCU_IMR));
811 seq_printf(m, "PCU interrupt identity:\t%08x\n",
812 I915_READ(GEN8_PCU_IIR));
813 seq_printf(m, "PCU interrupt enable:\t%08x\n",
814 I915_READ(GEN8_PCU_IER));
815 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 816 seq_printf(m, "Master Interrupt Control:\t%08x\n",
817 I915_READ(GEN8_MASTER_IRQ));
818
819 for (i = 0; i < 4; i++) {
820 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
821 i, I915_READ(GEN8_GT_IMR(i)));
822 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
823 i, I915_READ(GEN8_GT_IIR(i)));
824 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
825 i, I915_READ(GEN8_GT_IER(i)));
826 }
827
055e393f 828 for_each_pipe(dev_priv, pipe) {
f458ebbc 829 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 830 POWER_DOMAIN_PIPE(pipe))) {
831 seq_printf(m, "Pipe %c power disabled\n",
832 pipe_name(pipe));
833 continue;
834 }
a123f157 835 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 836 pipe_name(pipe),
837 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 838 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 839 pipe_name(pipe),
840 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 841 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 842 pipe_name(pipe),
843 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 844 }
845
846 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
847 I915_READ(GEN8_DE_PORT_IMR));
848 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IIR));
850 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IER));
852
853 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
854 I915_READ(GEN8_DE_MISC_IMR));
855 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IIR));
857 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IER));
859
860 seq_printf(m, "PCU interrupt mask:\t%08x\n",
861 I915_READ(GEN8_PCU_IMR));
862 seq_printf(m, "PCU interrupt identity:\t%08x\n",
863 I915_READ(GEN8_PCU_IIR));
864 seq_printf(m, "PCU interrupt enable:\t%08x\n",
865 I915_READ(GEN8_PCU_IER));
866 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 867 seq_printf(m, "Display IER:\t%08x\n",
868 I915_READ(VLV_IER));
869 seq_printf(m, "Display IIR:\t%08x\n",
870 I915_READ(VLV_IIR));
871 seq_printf(m, "Display IIR_RW:\t%08x\n",
872 I915_READ(VLV_IIR_RW));
873 seq_printf(m, "Display IMR:\t%08x\n",
874 I915_READ(VLV_IMR));
055e393f 875 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 876 seq_printf(m, "Pipe %c stat:\t%08x\n",
877 pipe_name(pipe),
878 I915_READ(PIPESTAT(pipe)));
879
880 seq_printf(m, "Master IER:\t%08x\n",
881 I915_READ(VLV_MASTER_IER));
882
883 seq_printf(m, "Render IER:\t%08x\n",
884 I915_READ(GTIER));
885 seq_printf(m, "Render IIR:\t%08x\n",
886 I915_READ(GTIIR));
887 seq_printf(m, "Render IMR:\t%08x\n",
888 I915_READ(GTIMR));
889
890 seq_printf(m, "PM IER:\t\t%08x\n",
891 I915_READ(GEN6_PMIER));
892 seq_printf(m, "PM IIR:\t\t%08x\n",
893 I915_READ(GEN6_PMIIR));
894 seq_printf(m, "PM IMR:\t\t%08x\n",
895 I915_READ(GEN6_PMIMR));
896
897 seq_printf(m, "Port hotplug:\t%08x\n",
898 I915_READ(PORT_HOTPLUG_EN));
899 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
900 I915_READ(VLV_DPFLIPSTAT));
901 seq_printf(m, "DPINVGTT:\t%08x\n",
902 I915_READ(DPINVGTT));
903
904 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 905 seq_printf(m, "Interrupt enable: %08x\n",
906 I915_READ(IER));
907 seq_printf(m, "Interrupt identity: %08x\n",
908 I915_READ(IIR));
909 seq_printf(m, "Interrupt mask: %08x\n",
910 I915_READ(IMR));
055e393f 911 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 912 seq_printf(m, "Pipe %c stat: %08x\n",
913 pipe_name(pipe),
914 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 915 } else {
916 seq_printf(m, "North Display Interrupt enable: %08x\n",
917 I915_READ(DEIER));
918 seq_printf(m, "North Display Interrupt identity: %08x\n",
919 I915_READ(DEIIR));
920 seq_printf(m, "North Display Interrupt mask: %08x\n",
921 I915_READ(DEIMR));
922 seq_printf(m, "South Display Interrupt enable: %08x\n",
923 I915_READ(SDEIER));
924 seq_printf(m, "South Display Interrupt identity: %08x\n",
925 I915_READ(SDEIIR));
926 seq_printf(m, "South Display Interrupt mask: %08x\n",
927 I915_READ(SDEIMR));
928 seq_printf(m, "Graphics Interrupt enable: %08x\n",
929 I915_READ(GTIER));
930 seq_printf(m, "Graphics Interrupt identity: %08x\n",
931 I915_READ(GTIIR));
932 seq_printf(m, "Graphics Interrupt mask: %08x\n",
933 I915_READ(GTIMR));
934 }
a2c7f6fd 935 for_each_ring(ring, dev_priv, i) {
a123f157 936 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 937 seq_printf(m,
938 "Graphics Interrupt mask (%s): %08x\n",
939 ring->name, I915_READ_IMR(ring));
9862e600 940 }
a2c7f6fd 941 i915_ring_seqno_info(m, ring);
9862e600 942 }
c8c8fb33 943 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 944 mutex_unlock(&dev->struct_mutex);
945
2017263e
BG		 946 return 0;
947}
948
a6172a80
CW		 949static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
950{
9f25d007 951 struct drm_info_node *node = m->private;
a6172a80 952 struct drm_device *dev = node->minor->dev;
e277a1f8 953 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 954 int i, ret;
955
956 ret = mutex_lock_interruptible(&dev->struct_mutex);
957 if (ret)
958 return ret;
a6172a80
CW		 959
960 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
961 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
962 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 963 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 964
6c085a72
CW		 965 seq_printf(m, "Fence %d, pin count = %d, object = ",
966 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 967 if (obj == NULL)
267f0c90 968 seq_puts(m, "unused");
c2c347a9 969 else
05394f39 970 describe_obj(m, obj);
267f0c90 971 seq_putc(m, '\n');
a6172a80
CW		 972 }
973
05394f39 974 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 975 return 0;
976}
977
2017263e
BG		 978static int i915_hws_info(struct seq_file *m, void *data)
979{
9f25d007 980 struct drm_info_node *node = m->private;
2017263e 981 struct drm_device *dev = node->minor->dev;
e277a1f8 982 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 983 struct intel_engine_cs *ring;
1a240d4d 984 const u32 *hws;
4066c0ae
CW		 985 int i;
986
1ec14ad3 987 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 988 hws = ring->status_page.page_addr;
2017263e
BG		 989 if (hws == NULL)
990 return 0;
991
992 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
993 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
994 i * 4,
995 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
996 }
997 return 0;
998}
999
d5442303
DV		 1000static ssize_t
1001i915_error_state_write(struct file *filp,
1002 const char __user *ubuf,
1003 size_t cnt,
1004 loff_t *ppos)
1005{
edc3d884 1006 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 1007 struct drm_device *dev = error_priv->dev;
22bcfc6a 1008 int ret;
d5442303
DV		 1009
1010 DRM_DEBUG_DRIVER("Resetting error state\n");
1011
22bcfc6a
DV		 1012 ret = mutex_lock_interruptible(&dev->struct_mutex);
1013 if (ret)
1014 return ret;
1015
d5442303
DV		 1016 i915_destroy_error_state(dev);
1017 mutex_unlock(&dev->struct_mutex);
1018
1019 return cnt;
1020}
1021
1022static int i915_error_state_open(struct inode *inode, struct file *file)
1023{
1024 struct drm_device *dev = inode->i_private;
d5442303 1025 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 1026
1027 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1028 if (!error_priv)
1029 return -ENOMEM;
1030
1031 error_priv->dev = dev;
1032
95d5bfb3 1033 i915_error_state_get(dev, error_priv);
d5442303 1034
edc3d884
MK		 1035 file->private_data = error_priv;
1036
1037 return 0;
d5442303
DV		 1038}
1039
1040static int i915_error_state_release(struct inode *inode, struct file *file)
1041{
edc3d884 1042 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 1043
95d5bfb3 1044 i915_error_state_put(error_priv);
d5442303
DV		 1045 kfree(error_priv);
1046
edc3d884
MK		 1047 return 0;
1048}
1049
4dc955f7
MK		 1050static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1051 size_t count, loff_t *pos)
1052{
1053 struct i915_error_state_file_priv *error_priv = file->private_data;
1054 struct drm_i915_error_state_buf error_str;
1055 loff_t tmp_pos = 0;
1056 ssize_t ret_count = 0;
1057 int ret;
1058
0a4cd7c8 1059 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 1060 if (ret)
1061 return ret;
edc3d884 1062
fc16b48b 1063 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 1064 if (ret)
1065 goto out;
1066
edc3d884
MK		 1067 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1068 error_str.buf,
1069 error_str.bytes);
1070
1071 if (ret_count < 0)
1072 ret = ret_count;
1073 else
1074 *pos = error_str.start + ret_count;
1075out:
4dc955f7 1076 i915_error_state_buf_release(&error_str);
edc3d884 1077 return ret ?: ret_count;
d5442303
DV		 1078}
1079
1080static const struct file_operations i915_error_state_fops = {
1081 .owner = THIS_MODULE,
1082 .open = i915_error_state_open,
edc3d884 1083 .read = i915_error_state_read,
d5442303
DV		 1084 .write = i915_error_state_write,
1085 .llseek = default_llseek,
1086 .release = i915_error_state_release,
1087};
1088
647416f9
KC		 1089static int
1090i915_next_seqno_get(void *data, u64 *val)
40633219 1091{
647416f9 1092 struct drm_device *dev = data;
e277a1f8 1093 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 1094 int ret;
1095
1096 ret = mutex_lock_interruptible(&dev->struct_mutex);
1097 if (ret)
1098 return ret;
1099
647416f9 1100 *val = dev_priv->next_seqno;
40633219
MK		 1101 mutex_unlock(&dev->struct_mutex);
1102
647416f9 1103 return 0;
40633219
MK		 1104}
1105
647416f9
KC		 1106static int
1107i915_next_seqno_set(void *data, u64 val)
1108{
1109 struct drm_device *dev = data;
40633219
MK		 1110 int ret;
1111
40633219
MK		 1112 ret = mutex_lock_interruptible(&dev->struct_mutex);
1113 if (ret)
1114 return ret;
1115
e94fbaa8 1116 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1117 mutex_unlock(&dev->struct_mutex);
1118
647416f9 1119 return ret;
40633219
MK		 1120}
1121
647416f9
KC		 1122DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1123 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1124 "0x%llx\n");
40633219 1125
adb4bd12 1126static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1127{
9f25d007 1128 struct drm_info_node *node = m->private;
f97108d1 1129 struct drm_device *dev = node->minor->dev;
e277a1f8 1130 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1131 int ret = 0;
1132
1133 intel_runtime_pm_get(dev_priv);
3b8d8d91 1134
5c9669ce
TR		 1135 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1136
3b8d8d91
JB		 1137 if (IS_GEN5(dev)) {
1138 u16 rgvswctl = I915_READ16(MEMSWCTL);
1139 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1140
1141 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1142 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1143 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1144 MEMSTAT_VID_SHIFT);
1145 seq_printf(m, "Current P-state: %d\n",
1146 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2 1147 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
60260a5b 1148 IS_BROADWELL(dev) || IS_GEN9(dev)) {
35040562
BP		 1149 u32 rp_state_limits;
1150 u32 gt_perf_status;
1151 u32 rp_state_cap;
0d8f9491 1152 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1153 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1154 u32 rpupei, rpcurup, rpprevup;
1155 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1156 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1157 int max_freq;
1158
35040562
BP		 1159 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1160 if (IS_BROXTON(dev)) {
1161 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1162 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1163 } else {
1164 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1165 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1166 }
1167
3b8d8d91 1168 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1169 ret = mutex_lock_interruptible(&dev->struct_mutex);
1170 if (ret)
c8c8fb33 1171 goto out;
d1ebd816 1172
59bad947 1173 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1174
8e8c06cd 1175 reqf = I915_READ(GEN6_RPNSWREQ);
60260a5b
AG		 1176 if (IS_GEN9(dev))
1177 reqf >>= 23;
1178 else {
1179 reqf &= ~GEN6_TURBO_DISABLE;
1180 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1181 reqf >>= 24;
1182 else
1183 reqf >>= 25;
1184 }
7c59a9c1 1185 reqf = intel_gpu_freq(dev_priv, reqf);
8e8c06cd 1186
0d8f9491
CW		 1187 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1188 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1189 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1190
ccab5c82
JB		 1191 rpstat = I915_READ(GEN6_RPSTAT1);
1192 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1193 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1194 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1195 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1196 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1197 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
60260a5b
AG		 1198 if (IS_GEN9(dev))
1199 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1200 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1201 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1202 else
1203 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
7c59a9c1 1204 cagf = intel_gpu_freq(dev_priv, cagf);
ccab5c82 1205
59bad947 1206 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1207 mutex_unlock(&dev->struct_mutex);
1208
9dd3c605
PZ		 1209 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1210 pm_ier = I915_READ(GEN6_PMIER);
1211 pm_imr = I915_READ(GEN6_PMIMR);
1212 pm_isr = I915_READ(GEN6_PMISR);
1213 pm_iir = I915_READ(GEN6_PMIIR);
1214 pm_mask = I915_READ(GEN6_PMINTRMSK);
1215 } else {
1216 pm_ier = I915_READ(GEN8_GT_IER(2));
1217 pm_imr = I915_READ(GEN8_GT_IMR(2));
1218 pm_isr = I915_READ(GEN8_GT_ISR(2));
1219 pm_iir = I915_READ(GEN8_GT_IIR(2));
1220 pm_mask = I915_READ(GEN6_PMINTRMSK);
1221 }
0d8f9491 1222 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1223 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1224 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91 1225 seq_printf(m, "Render p-state ratio: %d\n",
60260a5b 1226 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
3b8d8d91
JB		 1227 seq_printf(m, "Render p-state VID: %d\n",
1228 gt_perf_status & 0xff);
1229 seq_printf(m, "Render p-state limit: %d\n",
1230 rp_state_limits & 0xff);
0d8f9491
CW		 1231 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1232 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1233 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1234 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1235 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1236 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1237 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1238 GEN6_CURICONT_MASK);
1239 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1240 GEN6_CURBSYTAVG_MASK);
1241 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1242 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1243 seq_printf(m, "Up threshold: %d%%\n",
1244 dev_priv->rps.up_threshold);
1245
ccab5c82
JB		 1246 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1247 GEN6_CURIAVG_MASK);
1248 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1249 GEN6_CURBSYTAVG_MASK);
1250 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1251 GEN6_CURBSYTAVG_MASK);
d86ed34a
CW		 1252 seq_printf(m, "Down threshold: %d%%\n",
1253 dev_priv->rps.down_threshold);
3b8d8d91 1254
35040562
BP		 1255 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1256 rp_state_cap >> 16) & 0xff;
60260a5b 1257 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1258 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
7c59a9c1 1259 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91
JB		 1260
1261 max_freq = (rp_state_cap & 0xff00) >> 8;
60260a5b 1262 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1263 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
7c59a9c1 1264 intel_gpu_freq(dev_priv, max_freq));
3b8d8d91 1265
35040562
BP		 1266 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1267 rp_state_cap >> 0) & 0xff;
60260a5b 1268 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
3b8d8d91 1269 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
7c59a9c1 1270 intel_gpu_freq(dev_priv, max_freq));
31c77388 1271 seq_printf(m, "Max overclocked frequency: %dMHz\n",
7c59a9c1 1272 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
aed242ff 1273
d86ed34a
CW		 1274 seq_printf(m, "Current freq: %d MHz\n",
1275 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1276 seq_printf(m, "Actual freq: %d MHz\n", cagf);
aed242ff
CW		 1277 seq_printf(m, "Idle freq: %d MHz\n",
1278 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
d86ed34a
CW		 1279 seq_printf(m, "Min freq: %d MHz\n",
1280 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1281 seq_printf(m, "Max freq: %d MHz\n",
1282 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1283 seq_printf(m,
1284 "efficient (RPe) frequency: %d MHz\n",
1285 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84 1286 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1287 u32 freq_sts;
0a073b84 1288
259bd5d4 1289 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1290 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1291 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1292 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1293
d86ed34a
CW		 1294 seq_printf(m, "actual GPU freq: %d MHz\n",
1295 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1296
1297 seq_printf(m, "current GPU freq: %d MHz\n",
1298 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1299
0a073b84 1300 seq_printf(m, "max GPU freq: %d MHz\n",
7c59a9c1 1301 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1302
0a073b84 1303 seq_printf(m, "min GPU freq: %d MHz\n",
7c59a9c1 1304 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045 1305
aed242ff
CW		 1306 seq_printf(m, "idle GPU freq: %d MHz\n",
1307 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1308
7c59a9c1
VS		 1309 seq_printf(m,
1310 "efficient (RPe) frequency: %d MHz\n",
1311 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
259bd5d4 1312 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1313 } else {
267f0c90 1314 seq_puts(m, "no P-state info available\n");
3b8d8d91 1315 }
f97108d1 1316
c8c8fb33
PZ		 1317out:
1318 intel_runtime_pm_put(dev_priv);
1319 return ret;
f97108d1
JB		 1320}
1321
f654449a
CW		 1322static int i915_hangcheck_info(struct seq_file *m, void *unused)
1323{
1324 struct drm_info_node *node = m->private;
ebbc7546
MK		 1325 struct drm_device *dev = node->minor->dev;
1326 struct drm_i915_private *dev_priv = dev->dev_private;
f654449a 1327 struct intel_engine_cs *ring;
ebbc7546
MK		 1328 u64 acthd[I915_NUM_RINGS];
1329 u32 seqno[I915_NUM_RINGS];
f654449a
CW		 1330 int i;
1331
1332 if (!i915.enable_hangcheck) {
1333 seq_printf(m, "Hangcheck disabled\n");
1334 return 0;
1335 }
1336
ebbc7546
MK		 1337 intel_runtime_pm_get(dev_priv);
1338
1339 for_each_ring(ring, dev_priv, i) {
1340 seqno[i] = ring->get_seqno(ring, false);
1341 acthd[i] = intel_ring_get_active_head(ring);
1342 }
1343
1344 intel_runtime_pm_put(dev_priv);
1345
f654449a
CW		 1346 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1347 seq_printf(m, "Hangcheck active, fires in %dms\n",
1348 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1349 jiffies));
1350 } else
1351 seq_printf(m, "Hangcheck inactive\n");
1352
1353 for_each_ring(ring, dev_priv, i) {
1354 seq_printf(m, "%s:\n", ring->name);
1355 seq_printf(m, "\tseqno = %x [current %x]\n",
ebbc7546 1356 ring->hangcheck.seqno, seqno[i]);
f654449a
CW		 1357 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1358 (long long)ring->hangcheck.acthd,
ebbc7546 1359 (long long)acthd[i]);
f654449a
CW		 1360 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1361 (long long)ring->hangcheck.max_acthd);
ebbc7546
MK		 1362 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1363 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
f654449a
CW		 1364 }
1365
1366 return 0;
1367}
1368
4d85529d 1369static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1370{
9f25d007 1371 struct drm_info_node *node = m->private;
f97108d1 1372 struct drm_device *dev = node->minor->dev;
e277a1f8 1373 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1374 u32 rgvmodectl, rstdbyctl;
1375 u16 crstandvid;
1376 int ret;
1377
1378 ret = mutex_lock_interruptible(&dev->struct_mutex);
1379 if (ret)
1380 return ret;
c8c8fb33 1381 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1382
1383 rgvmodectl = I915_READ(MEMMODECTL);
1384 rstdbyctl = I915_READ(RSTDBYCTL);
1385 crstandvid = I915_READ16(CRSTANDVID);
1386
c8c8fb33 1387 intel_runtime_pm_put(dev_priv);
616fdb5a 1388 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1389
1390 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1391 "yes" : "no");
1392 seq_printf(m, "Boost freq: %d\n",
1393 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1394 MEMMODE_BOOST_FREQ_SHIFT);
1395 seq_printf(m, "HW control enabled: %s\n",
1396 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1397 seq_printf(m, "SW control enabled: %s\n",
1398 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1399 seq_printf(m, "Gated voltage change: %s\n",
1400 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1401 seq_printf(m, "Starting frequency: P%d\n",
1402 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1403 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1404 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1405 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1406 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1407 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1408 seq_printf(m, "Render standby enabled: %s\n",
1409 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1410 seq_puts(m, "Current RS state: ");
88271da3
JB		 1411 switch (rstdbyctl & RSX_STATUS_MASK) {
1412 case RSX_STATUS_ON:
267f0c90 1413 seq_puts(m, "on\n");
88271da3
JB		 1414 break;
1415 case RSX_STATUS_RC1:
267f0c90 1416 seq_puts(m, "RC1\n");
88271da3
JB		 1417 break;
1418 case RSX_STATUS_RC1E:
267f0c90 1419 seq_puts(m, "RC1E\n");
88271da3
JB		 1420 break;
1421 case RSX_STATUS_RS1:
267f0c90 1422 seq_puts(m, "RS1\n");
88271da3
JB		 1423 break;
1424 case RSX_STATUS_RS2:
267f0c90 1425 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1426 break;
1427 case RSX_STATUS_RS3:
267f0c90 1428 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1429 break;
1430 default:
267f0c90 1431 seq_puts(m, "unknown\n");
88271da3
JB		 1432 break;
1433 }
f97108d1
JB		 1434
1435 return 0;
1436}
1437
f65367b5 1438static int i915_forcewake_domains(struct seq_file *m, void *data)
669ab5aa 1439{
b2cff0db
CW		 1440 struct drm_info_node *node = m->private;
1441 struct drm_device *dev = node->minor->dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 struct intel_uncore_forcewake_domain *fw_domain;
b2cff0db
CW		 1444 int i;
1445
1446 spin_lock_irq(&dev_priv->uncore.lock);
1447 for_each_fw_domain(fw_domain, dev_priv, i) {
1448 seq_printf(m, "%s.wake_count = %u\n",
05a2fb15 1449 intel_uncore_forcewake_domain_to_str(i),
b2cff0db
CW		 1450 fw_domain->wake_count);
1451 }
1452 spin_unlock_irq(&dev_priv->uncore.lock);
669ab5aa 1453
b2cff0db
CW		 1454 return 0;
1455}
1456
1457static int vlv_drpc_info(struct seq_file *m)
1458{
9f25d007 1459 struct drm_info_node *node = m->private;
669ab5aa
D		 1460 struct drm_device *dev = node->minor->dev;
1461 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1462 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa 1463
d46c0517
ID		 1464 intel_runtime_pm_get(dev_priv);
1465
6b312cd3 1466 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1467 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1468 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1469
d46c0517
ID		 1470 intel_runtime_pm_put(dev_priv);
1471
669ab5aa
D		 1472 seq_printf(m, "Video Turbo Mode: %s\n",
1473 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1474 seq_printf(m, "Turbo enabled: %s\n",
1475 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1476 seq_printf(m, "HW control enabled: %s\n",
1477 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1478 seq_printf(m, "SW control enabled: %s\n",
1479 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1480 GEN6_RP_MEDIA_SW_MODE));
1481 seq_printf(m, "RC6 Enabled: %s\n",
1482 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1483 GEN6_RC_CTL_EI_MODE(1))));
1484 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1485 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1486 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1487 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1488
9cc19be5
ID		 1489 seq_printf(m, "Render RC6 residency since boot: %u\n",
1490 I915_READ(VLV_GT_RENDER_RC6));
1491 seq_printf(m, "Media RC6 residency since boot: %u\n",
1492 I915_READ(VLV_GT_MEDIA_RC6));
1493
f65367b5 1494 return i915_forcewake_domains(m, NULL);
669ab5aa
D		 1495}
1496
4d85529d
BW		 1497static int gen6_drpc_info(struct seq_file *m)
1498{
9f25d007 1499 struct drm_info_node *node = m->private;
4d85529d
BW		 1500 struct drm_device *dev = node->minor->dev;
1501 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1502 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1503 unsigned forcewake_count;
aee56cff 1504 int count = 0, ret;
4d85529d
BW		 1505
1506 ret = mutex_lock_interruptible(&dev->struct_mutex);
1507 if (ret)
1508 return ret;
c8c8fb33 1509 intel_runtime_pm_get(dev_priv);
4d85529d 1510
907b28c5 1511 spin_lock_irq(&dev_priv->uncore.lock);
b2cff0db 1512 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
907b28c5 1513 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1514
1515 if (forcewake_count) {
267f0c90
DL		 1516 seq_puts(m, "RC information inaccurate because somebody "
1517 "holds a forcewake reference \n");
4d85529d
BW		 1518 } else {
1519 /* NB: we cannot use forcewake, else we read the wrong values */
1520 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1521 udelay(10);
1522 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1523 }
1524
1525 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1526 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1527
1528 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1529 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1530 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1531 mutex_lock(&dev_priv->rps.hw_lock);
1532 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1533 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1534
c8c8fb33
PZ		 1535 intel_runtime_pm_put(dev_priv);
1536
4d85529d
BW		 1537 seq_printf(m, "Video Turbo Mode: %s\n",
1538 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1539 seq_printf(m, "HW control enabled: %s\n",
1540 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1541 seq_printf(m, "SW control enabled: %s\n",
1542 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1543 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1544 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1545 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1546 seq_printf(m, "RC6 Enabled: %s\n",
1547 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1548 seq_printf(m, "Deep RC6 Enabled: %s\n",
1549 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1550 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1551 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1552 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1553 switch (gt_core_status & GEN6_RCn_MASK) {
1554 case GEN6_RC0:
1555 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1556 seq_puts(m, "Core Power Down\n");
4d85529d 1557 else
267f0c90 1558 seq_puts(m, "on\n");
4d85529d
BW		 1559 break;
1560 case GEN6_RC3:
267f0c90 1561 seq_puts(m, "RC3\n");
4d85529d
BW		 1562 break;
1563 case GEN6_RC6:
267f0c90 1564 seq_puts(m, "RC6\n");
4d85529d
BW		 1565 break;
1566 case GEN6_RC7:
267f0c90 1567 seq_puts(m, "RC7\n");
4d85529d
BW		 1568 break;
1569 default:
267f0c90 1570 seq_puts(m, "Unknown\n");
4d85529d
BW		 1571 break;
1572 }
1573
1574 seq_printf(m, "Core Power Down: %s\n",
1575 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1576
1577 /* Not exactly sure what this is */
1578 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1579 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1580 seq_printf(m, "RC6 residency since boot: %u\n",
1581 I915_READ(GEN6_GT_GFX_RC6));
1582 seq_printf(m, "RC6+ residency since boot: %u\n",
1583 I915_READ(GEN6_GT_GFX_RC6p));
1584 seq_printf(m, "RC6++ residency since boot: %u\n",
1585 I915_READ(GEN6_GT_GFX_RC6pp));
1586
ecd8faea
BW		 1587 seq_printf(m, "RC6 voltage: %dmV\n",
1588 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1589 seq_printf(m, "RC6+ voltage: %dmV\n",
1590 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1591 seq_printf(m, "RC6++ voltage: %dmV\n",
1592 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1593 return 0;
1594}
1595
1596static int i915_drpc_info(struct seq_file *m, void *unused)
1597{
9f25d007 1598 struct drm_info_node *node = m->private;
4d85529d
BW		 1599 struct drm_device *dev = node->minor->dev;
1600
669ab5aa
D		 1601 if (IS_VALLEYVIEW(dev))
1602 return vlv_drpc_info(m);
ac66cf4b 1603 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1604 return gen6_drpc_info(m);
1605 else
1606 return ironlake_drpc_info(m);
1607}
1608
9a851789
DV		 1609static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1610{
1611 struct drm_info_node *node = m->private;
1612 struct drm_device *dev = node->minor->dev;
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614
1615 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1616 dev_priv->fb_tracking.busy_bits);
1617
1618 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1619 dev_priv->fb_tracking.flip_bits);
1620
1621 return 0;
1622}
1623
b5e50c3f
JB		 1624static int i915_fbc_status(struct seq_file *m, void *unused)
1625{
9f25d007 1626 struct drm_info_node *node = m->private;
b5e50c3f 1627 struct drm_device *dev = node->minor->dev;
e277a1f8 1628 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1629
3a77c4c4 1630 if (!HAS_FBC(dev)) {
267f0c90 1631 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1632 return 0;
1633 }
1634
36623ef8 1635 intel_runtime_pm_get(dev_priv);
25ad93fd 1636 mutex_lock(&dev_priv->fbc.lock);
36623ef8 1637
7733b49b 1638 if (intel_fbc_enabled(dev_priv))
267f0c90 1639 seq_puts(m, "FBC enabled\n");
2e8144a5
PZ		 1640 else
1641 seq_printf(m, "FBC disabled: %s\n",
1642 intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
36623ef8 1643
31b9df10
PZ		 1644 if (INTEL_INFO(dev_priv)->gen >= 7)
1645 seq_printf(m, "Compressing: %s\n",
1646 yesno(I915_READ(FBC_STATUS2) &
1647 FBC_COMPRESSION_MASK));
1648
25ad93fd 1649 mutex_unlock(&dev_priv->fbc.lock);
36623ef8
PZ		 1650 intel_runtime_pm_put(dev_priv);
1651
b5e50c3f
JB		 1652 return 0;
1653}
1654
da46f936
RV		 1655static int i915_fbc_fc_get(void *data, u64 *val)
1656{
1657 struct drm_device *dev = data;
1658 struct drm_i915_private *dev_priv = dev->dev_private;
1659
1660 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1661 return -ENODEV;
1662
da46f936 1663 *val = dev_priv->fbc.false_color;
da46f936
RV		 1664
1665 return 0;
1666}
1667
1668static int i915_fbc_fc_set(void *data, u64 val)
1669{
1670 struct drm_device *dev = data;
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 u32 reg;
1673
1674 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1675 return -ENODEV;
1676
25ad93fd 1677 mutex_lock(&dev_priv->fbc.lock);
da46f936
RV		 1678
1679 reg = I915_READ(ILK_DPFC_CONTROL);
1680 dev_priv->fbc.false_color = val;
1681
1682 I915_WRITE(ILK_DPFC_CONTROL, val ?
1683 (reg | FBC_CTL_FALSE_COLOR) :
1684 (reg & ~FBC_CTL_FALSE_COLOR));
1685
25ad93fd 1686 mutex_unlock(&dev_priv->fbc.lock);
da46f936
RV		 1687 return 0;
1688}
1689
1690DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1691 i915_fbc_fc_get, i915_fbc_fc_set,
1692 "%llu\n");
1693
92d44621
PZ		 1694static int i915_ips_status(struct seq_file *m, void *unused)
1695{
9f25d007 1696 struct drm_info_node *node = m->private;
92d44621
PZ		 1697 struct drm_device *dev = node->minor->dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699
f5adf94e 1700 if (!HAS_IPS(dev)) {
92d44621
PZ		 1701 seq_puts(m, "not supported\n");
1702 return 0;
1703 }
1704
36623ef8
PZ		 1705 intel_runtime_pm_get(dev_priv);
1706
0eaa53f0
RV		 1707 seq_printf(m, "Enabled by kernel parameter: %s\n",
1708 yesno(i915.enable_ips));
1709
1710 if (INTEL_INFO(dev)->gen >= 8) {
1711 seq_puts(m, "Currently: unknown\n");
1712 } else {
1713 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1714 seq_puts(m, "Currently: enabled\n");
1715 else
1716 seq_puts(m, "Currently: disabled\n");
1717 }
92d44621 1718
36623ef8
PZ		 1719 intel_runtime_pm_put(dev_priv);
1720
92d44621
PZ		 1721 return 0;
1722}
1723
4a9bef37
JB		 1724static int i915_sr_status(struct seq_file *m, void *unused)
1725{
9f25d007 1726 struct drm_info_node *node = m->private;
4a9bef37 1727 struct drm_device *dev = node->minor->dev;
e277a1f8 1728 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1729 bool sr_enabled = false;
1730
36623ef8
PZ		 1731 intel_runtime_pm_get(dev_priv);
1732
1398261a 1733 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1734 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
77b64555
ACO		 1735 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1736 IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1737 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1738 else if (IS_I915GM(dev))
1739 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1740 else if (IS_PINEVIEW(dev))
1741 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
77b64555
ACO		 1742 else if (IS_VALLEYVIEW(dev))
1743 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4a9bef37 1744
36623ef8
PZ		 1745 intel_runtime_pm_put(dev_priv);
1746
5ba2aaaa
CW		 1747 seq_printf(m, "self-refresh: %s\n",
1748 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1749
1750 return 0;
1751}
1752
7648fa99
JB		 1753static int i915_emon_status(struct seq_file *m, void *unused)
1754{
9f25d007 1755 struct drm_info_node *node = m->private;
7648fa99 1756 struct drm_device *dev = node->minor->dev;
e277a1f8 1757 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1758 unsigned long temp, chipset, gfx;
de227ef0
CW		 1759 int ret;
1760
582be6b4
CW		 1761 if (!IS_GEN5(dev))
1762 return -ENODEV;
1763
de227ef0
CW		 1764 ret = mutex_lock_interruptible(&dev->struct_mutex);
1765 if (ret)
1766 return ret;
7648fa99
JB		 1767
1768 temp = i915_mch_val(dev_priv);
1769 chipset = i915_chipset_val(dev_priv);
1770 gfx = i915_gfx_val(dev_priv);
de227ef0 1771 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1772
1773 seq_printf(m, "GMCH temp: %ld\n", temp);
1774 seq_printf(m, "Chipset power: %ld\n", chipset);
1775 seq_printf(m, "GFX power: %ld\n", gfx);
1776 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1777
1778 return 0;
1779}
1780
23b2f8bb
JB		 1781static int i915_ring_freq_table(struct seq_file *m, void *unused)
1782{
9f25d007 1783 struct drm_info_node *node = m->private;
23b2f8bb 1784 struct drm_device *dev = node->minor->dev;
e277a1f8 1785 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1786 int ret = 0;
23b2f8bb 1787 int gpu_freq, ia_freq;
f936ec34 1788 unsigned int max_gpu_freq, min_gpu_freq;
23b2f8bb 1789
97d3308a 1790 if (!HAS_CORE_RING_FREQ(dev)) {
267f0c90 1791 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1792 return 0;
1793 }
1794
5bfa0199
PZ		 1795 intel_runtime_pm_get(dev_priv);
1796
5c9669ce
TR		 1797 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1798
4fc688ce 1799 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1800 if (ret)
5bfa0199 1801 goto out;
23b2f8bb 1802
f936ec34
AG		 1803 if (IS_SKYLAKE(dev)) {
1804 /* Convert GT frequency to 50 HZ units */
1805 min_gpu_freq =
1806 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1807 max_gpu_freq =
1808 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1809 } else {
1810 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1811 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1812 }
1813
267f0c90 1814 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1815
f936ec34 1816 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
42c0526c
BW		 1817 ia_freq = gpu_freq;
1818 sandybridge_pcode_read(dev_priv,
1819 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1820 &ia_freq);
3ebecd07 1821 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
f936ec34
AG		 1822 intel_gpu_freq(dev_priv, (gpu_freq *
1823 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
3ebecd07
CW		 1824 ((ia_freq >> 0) & 0xff) * 100,
1825 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1826 }
1827
4fc688ce 1828 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1829
5bfa0199
PZ		 1830out:
1831 intel_runtime_pm_put(dev_priv);
1832 return ret;
23b2f8bb
JB		 1833}
1834
44834a67
CW		 1835static int i915_opregion(struct seq_file *m, void *unused)
1836{
9f25d007 1837 struct drm_info_node *node = m->private;
44834a67 1838 struct drm_device *dev = node->minor->dev;
e277a1f8 1839 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1840 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1841 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1842 int ret;
1843
0d38f009
DV		 1844 if (data == NULL)
1845 return -ENOMEM;
1846
44834a67
CW		 1847 ret = mutex_lock_interruptible(&dev->struct_mutex);
1848 if (ret)
0d38f009 1849 goto out;
44834a67 1850
0d38f009
DV		 1851 if (opregion->header) {
1852 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1853 seq_write(m, data, OPREGION_SIZE);
1854 }
44834a67
CW		 1855
1856 mutex_unlock(&dev->struct_mutex);
1857
0d38f009
DV		 1858out:
1859 kfree(data);
44834a67
CW		 1860 return 0;
1861}
1862
37811fcc
CW		 1863static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1864{
9f25d007 1865 struct drm_info_node *node = m->private;
37811fcc 1866 struct drm_device *dev = node->minor->dev;
4520f53a 1867 struct intel_fbdev *ifbdev = NULL;
37811fcc 1868 struct intel_framebuffer *fb;
37811fcc 1869
4520f53a
DV		 1870#ifdef CONFIG_DRM_I915_FBDEV
1871 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1872
1873 ifbdev = dev_priv->fbdev;
1874 fb = to_intel_framebuffer(ifbdev->helper.fb);
1875
c1ca506d 1876 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1877 fb->base.width,
1878 fb->base.height,
1879 fb->base.depth,
623f9783 1880 fb->base.bits_per_pixel,
c1ca506d 1881 fb->base.modifier[0],
623f9783 1882 atomic_read(&fb->base.refcount.refcount));
05394f39 1883 describe_obj(m, fb->obj);
267f0c90 1884 seq_putc(m, '\n');
4520f53a 1885#endif
37811fcc 1886
4b096ac1 1887 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1888 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1889 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1890 continue;
1891
c1ca506d 1892 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
37811fcc
CW		 1893 fb->base.width,
1894 fb->base.height,
1895 fb->base.depth,
623f9783 1896 fb->base.bits_per_pixel,
c1ca506d 1897 fb->base.modifier[0],
623f9783 1898 atomic_read(&fb->base.refcount.refcount));
05394f39 1899 describe_obj(m, fb->obj);
267f0c90 1900 seq_putc(m, '\n');
37811fcc 1901 }
4b096ac1 1902 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1903
1904 return 0;
1905}
1906
c9fe99bd
OM		 1907static void describe_ctx_ringbuf(struct seq_file *m,
1908 struct intel_ringbuffer *ringbuf)
1909{
1910 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1911 ringbuf->space, ringbuf->head, ringbuf->tail,
1912 ringbuf->last_retired_head);
1913}
1914
e76d3630
BW		 1915static int i915_context_status(struct seq_file *m, void *unused)
1916{
9f25d007 1917 struct drm_info_node *node = m->private;
e76d3630 1918 struct drm_device *dev = node->minor->dev;
e277a1f8 1919 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1920 struct intel_engine_cs *ring;
273497e5 1921 struct intel_context *ctx;
a168c293 1922 int ret, i;
e76d3630 1923
f3d28878 1924 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1925 if (ret)
1926 return ret;
1927
a33afea5 1928 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1929 if (!i915.enable_execlists &&
1930 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1931 continue;
1932
a33afea5 1933 seq_puts(m, "HW context ");
3ccfd19d 1934 describe_ctx(m, ctx);
c9fe99bd 1935 for_each_ring(ring, dev_priv, i) {
a33afea5 1936 if (ring->default_context == ctx)
c9fe99bd
OM		 1937 seq_printf(m, "(default context %s) ",
1938 ring->name);
1939 }
1940
1941 if (i915.enable_execlists) {
1942 seq_putc(m, '\n');
1943 for_each_ring(ring, dev_priv, i) {
1944 struct drm_i915_gem_object *ctx_obj =
1945 ctx->engine[i].state;
1946 struct intel_ringbuffer *ringbuf =
1947 ctx->engine[i].ringbuf;
1948
1949 seq_printf(m, "%s: ", ring->name);
1950 if (ctx_obj)
1951 describe_obj(m, ctx_obj);
1952 if (ringbuf)
1953 describe_ctx_ringbuf(m, ringbuf);
1954 seq_putc(m, '\n');
1955 }
1956 } else {
1957 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1958 }
a33afea5 1959
a33afea5 1960 seq_putc(m, '\n');
a168c293
BW		 1961 }
1962
f3d28878 1963 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1964
1965 return 0;
1966}
1967
064ca1d2
TD		 1968static void i915_dump_lrc_obj(struct seq_file *m,
1969 struct intel_engine_cs *ring,
1970 struct drm_i915_gem_object *ctx_obj)
1971{
1972 struct page *page;
1973 uint32_t *reg_state;
1974 int j;
1975 unsigned long ggtt_offset = 0;
1976
1977 if (ctx_obj == NULL) {
1978 seq_printf(m, "Context on %s with no gem object\n",
1979 ring->name);
1980 return;
1981 }
1982
1983 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1984 intel_execlists_ctx_id(ctx_obj));
1985
1986 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1987 seq_puts(m, "\tNot bound in GGTT\n");
1988 else
1989 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1990
1991 if (i915_gem_object_get_pages(ctx_obj)) {
1992 seq_puts(m, "\tFailed to get pages for context object\n");
1993 return;
1994 }
1995
1996 page = i915_gem_object_get_page(ctx_obj, 1);
1997 if (!WARN_ON(page == NULL)) {
1998 reg_state = kmap_atomic(page);
1999
2000 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2001 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2002 ggtt_offset + 4096 + (j * 4),
2003 reg_state[j], reg_state[j + 1],
2004 reg_state[j + 2], reg_state[j + 3]);
2005 }
2006 kunmap_atomic(reg_state);
2007 }
2008
2009 seq_putc(m, '\n');
2010}
2011
c0ab1ae9
BW		 2012static int i915_dump_lrc(struct seq_file *m, void *unused)
2013{
2014 struct drm_info_node *node = (struct drm_info_node *) m->private;
2015 struct drm_device *dev = node->minor->dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 struct intel_engine_cs *ring;
2018 struct intel_context *ctx;
2019 int ret, i;
2020
2021 if (!i915.enable_execlists) {
2022 seq_printf(m, "Logical Ring Contexts are disabled\n");
2023 return 0;
2024 }
2025
2026 ret = mutex_lock_interruptible(&dev->struct_mutex);
2027 if (ret)
2028 return ret;
2029
2030 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2031 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 2032 if (ring->default_context != ctx)
2033 i915_dump_lrc_obj(m, ring,
2034 ctx->engine[i].state);
c0ab1ae9
BW		 2035 }
2036 }
2037
2038 mutex_unlock(&dev->struct_mutex);
2039
2040 return 0;
2041}
2042
4ba70e44
OM		 2043static int i915_execlists(struct seq_file *m, void *data)
2044{
2045 struct drm_info_node *node = (struct drm_info_node *)m->private;
2046 struct drm_device *dev = node->minor->dev;
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 struct intel_engine_cs *ring;
2049 u32 status_pointer;
2050 u8 read_pointer;
2051 u8 write_pointer;
2052 u32 status;
2053 u32 ctx_id;
2054 struct list_head *cursor;
2055 int ring_id, i;
2056 int ret;
2057
2058 if (!i915.enable_execlists) {
2059 seq_puts(m, "Logical Ring Contexts are disabled\n");
2060 return 0;
2061 }
2062
2063 ret = mutex_lock_interruptible(&dev->struct_mutex);
2064 if (ret)
2065 return ret;
2066
fc0412ec
MT		 2067 intel_runtime_pm_get(dev_priv);
2068
4ba70e44 2069 for_each_ring(ring, dev_priv, ring_id) {
6d3d8274 2070 struct drm_i915_gem_request *head_req = NULL;
4ba70e44
OM		 2071 int count = 0;
2072 unsigned long flags;
2073
2074 seq_printf(m, "%s\n", ring->name);
2075
2076 status = I915_READ(RING_EXECLIST_STATUS(ring));
2077 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2078 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2079 status, ctx_id);
2080
2081 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2082 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2083
2084 read_pointer = ring->next_context_status_buffer;
2085 write_pointer = status_pointer & 0x07;
2086 if (read_pointer > write_pointer)
2087 write_pointer += 6;
2088 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2089 read_pointer, write_pointer);
2090
2091 for (i = 0; i < 6; i++) {
2092 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2093 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2094
2095 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2096 i, status, ctx_id);
2097 }
2098
2099 spin_lock_irqsave(&ring->execlist_lock, flags);
2100 list_for_each(cursor, &ring->execlist_queue)
2101 count++;
2102 head_req = list_first_entry_or_null(&ring->execlist_queue,
6d3d8274 2103 struct drm_i915_gem_request, execlist_link);
4ba70e44
OM		 2104 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2105
2106 seq_printf(m, "\t%d requests in queue\n", count);
2107 if (head_req) {
2108 struct drm_i915_gem_object *ctx_obj;
2109
6d3d8274 2110 ctx_obj = head_req->ctx->engine[ring_id].state;
4ba70e44
OM		 2111 seq_printf(m, "\tHead request id: %u\n",
2112 intel_execlists_ctx_id(ctx_obj));
2113 seq_printf(m, "\tHead request tail: %u\n",
6d3d8274 2114 head_req->tail);
4ba70e44
OM		 2115 }
2116
2117 seq_putc(m, '\n');
2118 }
2119
fc0412ec 2120 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 2121 mutex_unlock(&dev->struct_mutex);
2122
2123 return 0;
2124}
2125
ea16a3cd
DV		 2126static const char *swizzle_string(unsigned swizzle)
2127{
aee56cff 2128 switch (swizzle) {
ea16a3cd
DV		 2129 case I915_BIT_6_SWIZZLE_NONE:
2130 return "none";
2131 case I915_BIT_6_SWIZZLE_9:
2132 return "bit9";
2133 case I915_BIT_6_SWIZZLE_9_10:
2134 return "bit9/bit10";
2135 case I915_BIT_6_SWIZZLE_9_11:
2136 return "bit9/bit11";
2137 case I915_BIT_6_SWIZZLE_9_10_11:
2138 return "bit9/bit10/bit11";
2139 case I915_BIT_6_SWIZZLE_9_17:
2140 return "bit9/bit17";
2141 case I915_BIT_6_SWIZZLE_9_10_17:
2142 return "bit9/bit10/bit17";
2143 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 2144 return "unknown";
ea16a3cd
DV		 2145 }
2146
2147 return "bug";
2148}
2149
2150static int i915_swizzle_info(struct seq_file *m, void *data)
2151{
9f25d007 2152 struct drm_info_node *node = m->private;
ea16a3cd
DV		 2153 struct drm_device *dev = node->minor->dev;
2154 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 2155 int ret;
2156
2157 ret = mutex_lock_interruptible(&dev->struct_mutex);
2158 if (ret)
2159 return ret;
c8c8fb33 2160 intel_runtime_pm_get(dev_priv);
ea16a3cd 2161
ea16a3cd
DV		 2162 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2163 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2164 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2165 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2166
2167 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2168 seq_printf(m, "DDC = 0x%08x\n",
2169 I915_READ(DCC));
656bfa3a
DV		 2170 seq_printf(m, "DDC2 = 0x%08x\n",
2171 I915_READ(DCC2));
ea16a3cd
DV		 2172 seq_printf(m, "C0DRB3 = 0x%04x\n",
2173 I915_READ16(C0DRB3));
2174 seq_printf(m, "C1DRB3 = 0x%04x\n",
2175 I915_READ16(C1DRB3));
9d3203e1 2176 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2177 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2178 I915_READ(MAD_DIMM_C0));
2179 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2180 I915_READ(MAD_DIMM_C1));
2181 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2182 I915_READ(MAD_DIMM_C2));
2183 seq_printf(m, "TILECTL = 0x%08x\n",
2184 I915_READ(TILECTL));
5907f5fb 2185 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2186 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2187 I915_READ(GAMTARBMODE));
2188 else
2189 seq_printf(m, "ARB_MODE = 0x%08x\n",
2190 I915_READ(ARB_MODE));
3fa7d235
DV		 2191 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2192 I915_READ(DISP_ARB_CTL));
ea16a3cd 2193 }
656bfa3a
DV		 2194
2195 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2196 seq_puts(m, "L-shaped memory detected\n");
2197
c8c8fb33 2198 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2199 mutex_unlock(&dev->struct_mutex);
2200
2201 return 0;
2202}
2203
1c60fef5
BW		 2204static int per_file_ctx(int id, void *ptr, void *data)
2205{
273497e5 2206 struct intel_context *ctx = ptr;
1c60fef5 2207 struct seq_file *m = data;
ae6c4806
DV		 2208 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2209
2210 if (!ppgtt) {
2211 seq_printf(m, " no ppgtt for context %d\n",
2212 ctx->user_handle);
2213 return 0;
2214 }
1c60fef5 2215
f83d6518
OM		 2216 if (i915_gem_context_is_default(ctx))
2217 seq_puts(m, " default context:\n");
2218 else
821d66dd 2219 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2220 ppgtt->debug_dump(ppgtt, m);
2221
2222 return 0;
2223}
2224
77df6772 2225static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2226{
3cf17fc5 2227 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2228 struct intel_engine_cs *ring;
77df6772
BW		 2229 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2230 int unused, i;
3cf17fc5 2231
77df6772
BW		 2232 if (!ppgtt)
2233 return;
2234
77df6772
BW		 2235 for_each_ring(ring, dev_priv, unused) {
2236 seq_printf(m, "%s\n", ring->name);
2237 for (i = 0; i < 4; i++) {
2238 u32 offset = 0x270 + i * 8;
2239 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2240 pdp <<= 32;
2241 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2242 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2243 }
2244 }
2245}
2246
2247static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2248{
2249 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2250 struct intel_engine_cs *ring;
1c60fef5 2251 struct drm_file *file;
77df6772 2252 int i;
3cf17fc5 2253
3cf17fc5
DV		 2254 if (INTEL_INFO(dev)->gen == 6)
2255 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2256
a2c7f6fd 2257 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2258 seq_printf(m, "%s\n", ring->name);
2259 if (INTEL_INFO(dev)->gen == 7)
2260 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2261 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2262 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2263 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2264 }
2265 if (dev_priv->mm.aliasing_ppgtt) {
2266 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2267
267f0c90 2268 seq_puts(m, "aliasing PPGTT:\n");
44159ddb 2269 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
1c60fef5 2270
87d60b63 2271 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2272 }
1c60fef5
BW		 2273
2274 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2275 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2276
1c60fef5
BW		 2277 seq_printf(m, "proc: %s\n",
2278 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2279 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2280 }
2281 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2282}
2283
2284static int i915_ppgtt_info(struct seq_file *m, void *data)
2285{
9f25d007 2286 struct drm_info_node *node = m->private;
77df6772 2287 struct drm_device *dev = node->minor->dev;
c8c8fb33 2288 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2289
2290 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2291 if (ret)
2292 return ret;
c8c8fb33 2293 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2294
2295 if (INTEL_INFO(dev)->gen >= 8)
2296 gen8_ppgtt_info(m, dev);
2297 else if (INTEL_INFO(dev)->gen >= 6)
2298 gen6_ppgtt_info(m, dev);
2299
c8c8fb33 2300 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2301 mutex_unlock(&dev->struct_mutex);
2302
2303 return 0;
2304}
2305
f5a4c67d
CW		 2306static int count_irq_waiters(struct drm_i915_private *i915)
2307{
2308 struct intel_engine_cs *ring;
2309 int count = 0;
2310 int i;
2311
2312 for_each_ring(ring, i915, i)
2313 count += ring->irq_refcount;
2314
2315 return count;
2316}
2317
1854d5ca
CW		 2318static int i915_rps_boost_info(struct seq_file *m, void *data)
2319{
2320 struct drm_info_node *node = m->private;
2321 struct drm_device *dev = node->minor->dev;
2322 struct drm_i915_private *dev_priv = dev->dev_private;
2323 struct drm_file *file;
1854d5ca 2324
f5a4c67d
CW		 2325 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2326 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2327 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2328 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2329 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2330 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2331 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2332 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2333 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
8d3afd7d 2334 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 2335 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2336 struct drm_i915_file_private *file_priv = file->driver_priv;
2337 struct task_struct *task;
2338
2339 rcu_read_lock();
2340 task = pid_task(file->pid, PIDTYPE_PID);
2341 seq_printf(m, "%s [%d]: %d boosts%s\n",
2342 task ? task->comm : "<unknown>",
2343 task ? task->pid : -1,
2e1b8730
CW		 2344 file_priv->rps.boosts,
2345 list_empty(&file_priv->rps.link) ? "" : ", active");
1854d5ca
CW		 2346 rcu_read_unlock();
2347 }
2e1b8730
CW		 2348 seq_printf(m, "Semaphore boosts: %d%s\n",
2349 dev_priv->rps.semaphores.boosts,
2350 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2351 seq_printf(m, "MMIO flip boosts: %d%s\n",
2352 dev_priv->rps.mmioflips.boosts,
2353 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
1854d5ca 2354 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
8d3afd7d 2355 spin_unlock(&dev_priv->rps.client_lock);
1854d5ca 2356
8d3afd7d 2357 return 0;
1854d5ca
CW		 2358}
2359
63573eb7
BW		 2360static int i915_llc(struct seq_file *m, void *data)
2361{
9f25d007 2362 struct drm_info_node *node = m->private;
63573eb7
BW		 2363 struct drm_device *dev = node->minor->dev;
2364 struct drm_i915_private *dev_priv = dev->dev_private;
2365
2366 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2367 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2368 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2369
2370 return 0;
2371}
2372
e91fd8c6
RV		 2373static int i915_edp_psr_status(struct seq_file *m, void *data)
2374{
2375 struct drm_info_node *node = m->private;
2376 struct drm_device *dev = node->minor->dev;
2377 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2378 u32 psrperf = 0;
a6cbdb8e
RV		 2379 u32 stat[3];
2380 enum pipe pipe;
a031d709 2381 bool enabled = false;
e91fd8c6 2382
3553a8ea
DL		 2383 if (!HAS_PSR(dev)) {
2384 seq_puts(m, "PSR not supported\n");
2385 return 0;
2386 }
2387
c8c8fb33
PZ		 2388 intel_runtime_pm_get(dev_priv);
2389
fa128fa6 2390 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2391 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2392 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2393 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2394 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2395 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2396 dev_priv->psr.busy_frontbuffer_bits);
2397 seq_printf(m, "Re-enable work scheduled: %s\n",
2398 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2399
3553a8ea
DL		 2400 if (HAS_DDI(dev))
2401 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2402 else {
2403 for_each_pipe(dev_priv, pipe) {
2404 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2405 VLV_EDP_PSR_CURR_STATE_MASK;
2406 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2407 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2408 enabled = true;
a6cbdb8e
RV		 2409 }
2410 }
2411 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2412
2413 if (!HAS_DDI(dev))
2414 for_each_pipe(dev_priv, pipe) {
2415 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2416 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2417 seq_printf(m, " pipe %c", pipe_name(pipe));
2418 }
2419 seq_puts(m, "\n");
e91fd8c6 2420
a6cbdb8e 2421 /* CHV PSR has no kind of performance counter */
3553a8ea 2422 if (HAS_DDI(dev)) {
a031d709
RV		 2423 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2424 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2425
2426 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2427 }
fa128fa6 2428 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2429
c8c8fb33 2430 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2431 return 0;
2432}
2433
d2e216d0
RV		 2434static int i915_sink_crc(struct seq_file *m, void *data)
2435{
2436 struct drm_info_node *node = m->private;
2437 struct drm_device *dev = node->minor->dev;
2438 struct intel_encoder *encoder;
2439 struct intel_connector *connector;
2440 struct intel_dp *intel_dp = NULL;
2441 int ret;
2442 u8 crc[6];
2443
2444 drm_modeset_lock_all(dev);
aca5e361 2445 for_each_intel_connector(dev, connector) {
d2e216d0
RV		 2446
2447 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2448 continue;
2449
b6ae3c7c
PZ		 2450 if (!connector->base.encoder)
2451 continue;
2452
d2e216d0
RV		 2453 encoder = to_intel_encoder(connector->base.encoder);
2454 if (encoder->type != INTEL_OUTPUT_EDP)
2455 continue;
2456
2457 intel_dp = enc_to_intel_dp(&encoder->base);
2458
2459 ret = intel_dp_sink_crc(intel_dp, crc);
2460 if (ret)
2461 goto out;
2462
2463 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2464 crc[0], crc[1], crc[2],
2465 crc[3], crc[4], crc[5]);
2466 goto out;
2467 }
2468 ret = -ENODEV;
2469out:
2470 drm_modeset_unlock_all(dev);
2471 return ret;
2472}
2473
ec013e7f
JB		 2474static int i915_energy_uJ(struct seq_file *m, void *data)
2475{
2476 struct drm_info_node *node = m->private;
2477 struct drm_device *dev = node->minor->dev;
2478 struct drm_i915_private *dev_priv = dev->dev_private;
2479 u64 power;
2480 u32 units;
2481
2482 if (INTEL_INFO(dev)->gen < 6)
2483 return -ENODEV;
2484
36623ef8
PZ		 2485 intel_runtime_pm_get(dev_priv);
2486
ec013e7f
JB		 2487 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2488 power = (power & 0x1f00) >> 8;
2489 units = 1000000 / (1 << power); /* convert to uJ */
2490 power = I915_READ(MCH_SECP_NRG_STTS);
2491 power *= units;
2492
36623ef8
PZ		 2493 intel_runtime_pm_put(dev_priv);
2494
ec013e7f 2495 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2496
2497 return 0;
2498}
2499
6455c870 2500static int i915_runtime_pm_status(struct seq_file *m, void *unused)
371db66a 2501{
9f25d007 2502 struct drm_info_node *node = m->private;
371db66a
PZ		 2503 struct drm_device *dev = node->minor->dev;
2504 struct drm_i915_private *dev_priv = dev->dev_private;
2505
6455c870 2506 if (!HAS_RUNTIME_PM(dev)) {
371db66a
PZ		 2507 seq_puts(m, "not supported\n");
2508 return 0;
2509 }
2510
86c4ec0d 2511 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2512 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2513 yesno(!intel_irqs_enabled(dev_priv)));
0d804184 2514#ifdef CONFIG_PM
a6aaec8b
DL		 2515 seq_printf(m, "Usage count: %d\n",
2516 atomic_read(&dev->dev->power.usage_count));
0d804184
CW		 2517#else
2518 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2519#endif
371db66a 2520
ec013e7f
JB		 2521 return 0;
2522}
2523
1da51581
ID		 2524static const char *power_domain_str(enum intel_display_power_domain domain)
2525{
2526 switch (domain) {
2527 case POWER_DOMAIN_PIPE_A:
2528 return "PIPE_A";
2529 case POWER_DOMAIN_PIPE_B:
2530 return "PIPE_B";
2531 case POWER_DOMAIN_PIPE_C:
2532 return "PIPE_C";
2533 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2534 return "PIPE_A_PANEL_FITTER";
2535 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2536 return "PIPE_B_PANEL_FITTER";
2537 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2538 return "PIPE_C_PANEL_FITTER";
2539 case POWER_DOMAIN_TRANSCODER_A:
2540 return "TRANSCODER_A";
2541 case POWER_DOMAIN_TRANSCODER_B:
2542 return "TRANSCODER_B";
2543 case POWER_DOMAIN_TRANSCODER_C:
2544 return "TRANSCODER_C";
2545 case POWER_DOMAIN_TRANSCODER_EDP:
2546 return "TRANSCODER_EDP";
319be8ae
ID		 2547 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2548 return "PORT_DDI_A_2_LANES";
2549 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2550 return "PORT_DDI_A_4_LANES";
2551 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2552 return "PORT_DDI_B_2_LANES";
2553 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2554 return "PORT_DDI_B_4_LANES";
2555 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2556 return "PORT_DDI_C_2_LANES";
2557 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2558 return "PORT_DDI_C_4_LANES";
2559 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2560 return "PORT_DDI_D_2_LANES";
2561 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2562 return "PORT_DDI_D_4_LANES";
2563 case POWER_DOMAIN_PORT_DSI:
2564 return "PORT_DSI";
2565 case POWER_DOMAIN_PORT_CRT:
2566 return "PORT_CRT";
2567 case POWER_DOMAIN_PORT_OTHER:
2568 return "PORT_OTHER";
1da51581
ID		 2569 case POWER_DOMAIN_VGA:
2570 return "VGA";
2571 case POWER_DOMAIN_AUDIO:
2572 return "AUDIO";
bd2bb1b9
PZ		 2573 case POWER_DOMAIN_PLLS:
2574 return "PLLS";
1407121a
S		 2575 case POWER_DOMAIN_AUX_A:
2576 return "AUX_A";
2577 case POWER_DOMAIN_AUX_B:
2578 return "AUX_B";
2579 case POWER_DOMAIN_AUX_C:
2580 return "AUX_C";
2581 case POWER_DOMAIN_AUX_D:
2582 return "AUX_D";
1da51581
ID		 2583 case POWER_DOMAIN_INIT:
2584 return "INIT";
2585 default:
5f77eeb0 2586 MISSING_CASE(domain);
1da51581
ID		 2587 return "?";
2588 }
2589}
2590
2591static int i915_power_domain_info(struct seq_file *m, void *unused)
2592{
9f25d007 2593 struct drm_info_node *node = m->private;
1da51581
ID		 2594 struct drm_device *dev = node->minor->dev;
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2597 int i;
2598
2599 mutex_lock(&power_domains->lock);
2600
2601 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2602 for (i = 0; i < power_domains->power_well_count; i++) {
2603 struct i915_power_well *power_well;
2604 enum intel_display_power_domain power_domain;
2605
2606 power_well = &power_domains->power_wells[i];
2607 seq_printf(m, "%-25s %d\n", power_well->name,
2608 power_well->count);
2609
2610 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2611 power_domain++) {
2612 if (!(BIT(power_domain) & power_well->domains))
2613 continue;
2614
2615 seq_printf(m, " %-23s %d\n",
2616 power_domain_str(power_domain),
2617 power_domains->domain_use_count[power_domain]);
2618 }
2619 }
2620
2621 mutex_unlock(&power_domains->lock);
2622
2623 return 0;
2624}
2625
53f5e3ca
JB		 2626static void intel_seq_print_mode(struct seq_file *m, int tabs,
2627 struct drm_display_mode *mode)
2628{
2629 int i;
2630
2631 for (i = 0; i < tabs; i++)
2632 seq_putc(m, '\t');
2633
2634 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2635 mode->base.id, mode->name,
2636 mode->vrefresh, mode->clock,
2637 mode->hdisplay, mode->hsync_start,
2638 mode->hsync_end, mode->htotal,
2639 mode->vdisplay, mode->vsync_start,
2640 mode->vsync_end, mode->vtotal,
2641 mode->type, mode->flags);
2642}
2643
2644static void intel_encoder_info(struct seq_file *m,
2645 struct intel_crtc *intel_crtc,
2646 struct intel_encoder *intel_encoder)
2647{
9f25d007 2648 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2649 struct drm_device *dev = node->minor->dev;
2650 struct drm_crtc *crtc = &intel_crtc->base;
2651 struct intel_connector *intel_connector;
2652 struct drm_encoder *encoder;
2653
2654 encoder = &intel_encoder->base;
2655 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2656 encoder->base.id, encoder->name);
53f5e3ca
JB		 2657 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2658 struct drm_connector *connector = &intel_connector->base;
2659 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2660 connector->base.id,
c23cc417 2661 connector->name,
53f5e3ca
JB		 2662 drm_get_connector_status_name(connector->status));
2663 if (connector->status == connector_status_connected) {
2664 struct drm_display_mode *mode = &crtc->mode;
2665 seq_printf(m, ", mode:\n");
2666 intel_seq_print_mode(m, 2, mode);
2667 } else {
2668 seq_putc(m, '\n');
2669 }
2670 }
2671}
2672
2673static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2674{
9f25d007 2675 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2676 struct drm_device *dev = node->minor->dev;
2677 struct drm_crtc *crtc = &intel_crtc->base;
2678 struct intel_encoder *intel_encoder;
2679
5aa8a937
MR		 2680 if (crtc->primary->fb)
2681 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2682 crtc->primary->fb->base.id, crtc->x, crtc->y,
2683 crtc->primary->fb->width, crtc->primary->fb->height);
2684 else
2685 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2686 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2687 intel_encoder_info(m, intel_crtc, intel_encoder);
2688}
2689
2690static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2691{
2692 struct drm_display_mode *mode = panel->fixed_mode;
2693
2694 seq_printf(m, "\tfixed mode:\n");
2695 intel_seq_print_mode(m, 2, mode);
2696}
2697
2698static void intel_dp_info(struct seq_file *m,
2699 struct intel_connector *intel_connector)
2700{
2701 struct intel_encoder *intel_encoder = intel_connector->encoder;
2702 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2703
2704 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2705 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2706 "no");
2707 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2708 intel_panel_info(m, &intel_connector->panel);
2709}
2710
2711static void intel_hdmi_info(struct seq_file *m,
2712 struct intel_connector *intel_connector)
2713{
2714 struct intel_encoder *intel_encoder = intel_connector->encoder;
2715 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2716
2717 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2718 "no");
2719}
2720
2721static void intel_lvds_info(struct seq_file *m,
2722 struct intel_connector *intel_connector)
2723{
2724 intel_panel_info(m, &intel_connector->panel);
2725}
2726
2727static void intel_connector_info(struct seq_file *m,
2728 struct drm_connector *connector)
2729{
2730 struct intel_connector *intel_connector = to_intel_connector(connector);
2731 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2732 struct drm_display_mode *mode;
53f5e3ca
JB		 2733
2734 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2735 connector->base.id, connector->name,
53f5e3ca
JB		 2736 drm_get_connector_status_name(connector->status));
2737 if (connector->status == connector_status_connected) {
2738 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2739 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2740 connector->display_info.width_mm,
2741 connector->display_info.height_mm);
2742 seq_printf(m, "\tsubpixel order: %s\n",
2743 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2744 seq_printf(m, "\tCEA rev: %d\n",
2745 connector->display_info.cea_rev);
2746 }
36cd7444
DA		 2747 if (intel_encoder) {
2748 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2749 intel_encoder->type == INTEL_OUTPUT_EDP)
2750 intel_dp_info(m, intel_connector);
2751 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2752 intel_hdmi_info(m, intel_connector);
2753 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2754 intel_lvds_info(m, intel_connector);
2755 }
53f5e3ca 2756
f103fc7d
JB		 2757 seq_printf(m, "\tmodes:\n");
2758 list_for_each_entry(mode, &connector->modes, head)
2759 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2760}
2761
065f2ec2
CW		 2762static bool cursor_active(struct drm_device *dev, int pipe)
2763{
2764 struct drm_i915_private *dev_priv = dev->dev_private;
2765 u32 state;
2766
2767 if (IS_845G(dev) || IS_I865G(dev))
2768 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2769 else
5efb3e28 2770 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2771
2772 return state;
2773}
2774
2775static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2776{
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 u32 pos;
2779
5efb3e28 2780 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2781
2782 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2783 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2784 *x = -*x;
2785
2786 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2787 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2788 *y = -*y;
2789
2790 return cursor_active(dev, pipe);
2791}
2792
53f5e3ca
JB		 2793static int i915_display_info(struct seq_file *m, void *unused)
2794{
9f25d007 2795 struct drm_info_node *node = m->private;
53f5e3ca 2796 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2797 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2798 struct intel_crtc *crtc;
53f5e3ca
JB		 2799 struct drm_connector *connector;
2800
b0e5ddf3 2801 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2802 drm_modeset_lock_all(dev);
2803 seq_printf(m, "CRTC info\n");
2804 seq_printf(m, "---------\n");
d3fcc808 2805 for_each_intel_crtc(dev, crtc) {
065f2ec2 2806 bool active;
f77076c9 2807 struct intel_crtc_state *pipe_config;
065f2ec2 2808 int x, y;
53f5e3ca 2809
f77076c9
ML		 2810 pipe_config = to_intel_crtc_state(crtc->base.state);
2811
57127efa 2812 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2813 crtc->base.base.id, pipe_name(crtc->pipe),
f77076c9
ML		 2814 yesno(pipe_config->base.active),
2815 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2816 if (pipe_config->base.active) {
065f2ec2
CW		 2817 intel_crtc_info(m, crtc);
2818
a23dc658 2819 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2820 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2821 yesno(crtc->cursor_base),
3dd512fb
MR		 2822 x, y, crtc->base.cursor->state->crtc_w,
2823 crtc->base.cursor->state->crtc_h,
57127efa 2824 crtc->cursor_addr, yesno(active));
a23dc658 2825 }
cace841c
DV		 2826
2827 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2828 yesno(!crtc->cpu_fifo_underrun_disabled),
2829 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2830 }
2831
2832 seq_printf(m, "\n");
2833 seq_printf(m, "Connector info\n");
2834 seq_printf(m, "--------------\n");
2835 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2836 intel_connector_info(m, connector);
2837 }
2838 drm_modeset_unlock_all(dev);
b0e5ddf3 2839 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2840
2841 return 0;
2842}
2843
e04934cf
BW		 2844static int i915_semaphore_status(struct seq_file *m, void *unused)
2845{
2846 struct drm_info_node *node = (struct drm_info_node *) m->private;
2847 struct drm_device *dev = node->minor->dev;
2848 struct drm_i915_private *dev_priv = dev->dev_private;
2849 struct intel_engine_cs *ring;
2850 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2851 int i, j, ret;
2852
2853 if (!i915_semaphore_is_enabled(dev)) {
2854 seq_puts(m, "Semaphores are disabled\n");
2855 return 0;
2856 }
2857
2858 ret = mutex_lock_interruptible(&dev->struct_mutex);
2859 if (ret)
2860 return ret;
03872064 2861 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2862
2863 if (IS_BROADWELL(dev)) {
2864 struct page *page;
2865 uint64_t *seqno;
2866
2867 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2868
2869 seqno = (uint64_t *)kmap_atomic(page);
2870 for_each_ring(ring, dev_priv, i) {
2871 uint64_t offset;
2872
2873 seq_printf(m, "%s\n", ring->name);
2874
2875 seq_puts(m, " Last signal:");
2876 for (j = 0; j < num_rings; j++) {
2877 offset = i * I915_NUM_RINGS + j;
2878 seq_printf(m, "0x%08llx (0x%02llx) ",
2879 seqno[offset], offset * 8);
2880 }
2881 seq_putc(m, '\n');
2882
2883 seq_puts(m, " Last wait: ");
2884 for (j = 0; j < num_rings; j++) {
2885 offset = i + (j * I915_NUM_RINGS);
2886 seq_printf(m, "0x%08llx (0x%02llx) ",
2887 seqno[offset], offset * 8);
2888 }
2889 seq_putc(m, '\n');
2890
2891 }
2892 kunmap_atomic(seqno);
2893 } else {
2894 seq_puts(m, " Last signal:");
2895 for_each_ring(ring, dev_priv, i)
2896 for (j = 0; j < num_rings; j++)
2897 seq_printf(m, "0x%08x\n",
2898 I915_READ(ring->semaphore.mbox.signal[j]));
2899 seq_putc(m, '\n');
2900 }
2901
2902 seq_puts(m, "\nSync seqno:\n");
2903 for_each_ring(ring, dev_priv, i) {
2904 for (j = 0; j < num_rings; j++) {
2905 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2906 }
2907 seq_putc(m, '\n');
2908 }
2909 seq_putc(m, '\n');
2910
03872064 2911 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2912 mutex_unlock(&dev->struct_mutex);
2913 return 0;
2914}
2915
728e29d7
DV		 2916static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2917{
2918 struct drm_info_node *node = (struct drm_info_node *) m->private;
2919 struct drm_device *dev = node->minor->dev;
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921 int i;
2922
2923 drm_modeset_lock_all(dev);
2924 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2925 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2926
2927 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2928 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2929 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2930 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2931 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2932 seq_printf(m, " dpll_md: 0x%08x\n",
2933 pll->config.hw_state.dpll_md);
2934 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2935 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2936 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2937 }
2938 drm_modeset_unlock_all(dev);
2939
2940 return 0;
2941}
2942
1ed1ef9d 2943static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2944{
2945 int i;
2946 int ret;
2947 struct drm_info_node *node = (struct drm_info_node *) m->private;
2948 struct drm_device *dev = node->minor->dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950
888b5995
AS		 2951 ret = mutex_lock_interruptible(&dev->struct_mutex);
2952 if (ret)
2953 return ret;
2954
2955 intel_runtime_pm_get(dev_priv);
2956
7225342a
MK		 2957 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2958 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2959 u32 addr, mask, value, read;
2960 bool ok;
888b5995 2961
7225342a
MK		 2962 addr = dev_priv->workarounds.reg[i].addr;
2963 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2964 value = dev_priv->workarounds.reg[i].value;
2965 read = I915_READ(addr);
2966 ok = (value & mask) == (read & mask);
2967 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2968 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2969 }
2970
2971 intel_runtime_pm_put(dev_priv);
2972 mutex_unlock(&dev->struct_mutex);
2973
2974 return 0;
2975}
2976
c5511e44
DL		 2977static int i915_ddb_info(struct seq_file *m, void *unused)
2978{
2979 struct drm_info_node *node = m->private;
2980 struct drm_device *dev = node->minor->dev;
2981 struct drm_i915_private *dev_priv = dev->dev_private;
2982 struct skl_ddb_allocation *ddb;
2983 struct skl_ddb_entry *entry;
2984 enum pipe pipe;
2985 int plane;
2986
2fcffe19
DL		 2987 if (INTEL_INFO(dev)->gen < 9)
2988 return 0;
2989
c5511e44
DL		 2990 drm_modeset_lock_all(dev);
2991
2992 ddb = &dev_priv->wm.skl_hw.ddb;
2993
2994 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2995
2996 for_each_pipe(dev_priv, pipe) {
2997 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2998
dd740780 2999 for_each_plane(dev_priv, pipe, plane) {
c5511e44
DL		 3000 entry = &ddb->plane[pipe][plane];
3001 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3002 entry->start, entry->end,
3003 skl_ddb_entry_size(entry));
3004 }
3005
3006 entry = &ddb->cursor[pipe];
3007 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3008 entry->end, skl_ddb_entry_size(entry));
3009 }
3010
3011 drm_modeset_unlock_all(dev);
3012
3013 return 0;
3014}
3015
a54746e3
VK		 3016static void drrs_status_per_crtc(struct seq_file *m,
3017 struct drm_device *dev, struct intel_crtc *intel_crtc)
3018{
3019 struct intel_encoder *intel_encoder;
3020 struct drm_i915_private *dev_priv = dev->dev_private;
3021 struct i915_drrs *drrs = &dev_priv->drrs;
3022 int vrefresh = 0;
3023
3024 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3025 /* Encoder connected on this CRTC */
3026 switch (intel_encoder->type) {
3027 case INTEL_OUTPUT_EDP:
3028 seq_puts(m, "eDP:\n");
3029 break;
3030 case INTEL_OUTPUT_DSI:
3031 seq_puts(m, "DSI:\n");
3032 break;
3033 case INTEL_OUTPUT_HDMI:
3034 seq_puts(m, "HDMI:\n");
3035 break;
3036 case INTEL_OUTPUT_DISPLAYPORT:
3037 seq_puts(m, "DP:\n");
3038 break;
3039 default:
3040 seq_printf(m, "Other encoder (id=%d).\n",
3041 intel_encoder->type);
3042 return;
3043 }
3044 }
3045
3046 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3047 seq_puts(m, "\tVBT: DRRS_type: Static");
3048 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3049 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3050 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3051 seq_puts(m, "\tVBT: DRRS_type: None");
3052 else
3053 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3054
3055 seq_puts(m, "\n\n");
3056
f77076c9 3057 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
a54746e3
VK		 3058 struct intel_panel *panel;
3059
3060 mutex_lock(&drrs->mutex);
3061 /* DRRS Supported */
3062 seq_puts(m, "\tDRRS Supported: Yes\n");
3063
3064 /* disable_drrs() will make drrs->dp NULL */
3065 if (!drrs->dp) {
3066 seq_puts(m, "Idleness DRRS: Disabled");
3067 mutex_unlock(&drrs->mutex);
3068 return;
3069 }
3070
3071 panel = &drrs->dp->attached_connector->panel;
3072 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3073 drrs->busy_frontbuffer_bits);
3074
3075 seq_puts(m, "\n\t\t");
3076 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3077 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3078 vrefresh = panel->fixed_mode->vrefresh;
3079 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3080 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3081 vrefresh = panel->downclock_mode->vrefresh;
3082 } else {
3083 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3084 drrs->refresh_rate_type);
3085 mutex_unlock(&drrs->mutex);
3086 return;
3087 }
3088 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3089
3090 seq_puts(m, "\n\t\t");
3091 mutex_unlock(&drrs->mutex);
3092 } else {
3093 /* DRRS not supported. Print the VBT parameter*/
3094 seq_puts(m, "\tDRRS Supported : No");
3095 }
3096 seq_puts(m, "\n");
3097}
3098
3099static int i915_drrs_status(struct seq_file *m, void *unused)
3100{
3101 struct drm_info_node *node = m->private;
3102 struct drm_device *dev = node->minor->dev;
3103 struct intel_crtc *intel_crtc;
3104 int active_crtc_cnt = 0;
3105
3106 for_each_intel_crtc(dev, intel_crtc) {
3107 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3108
f77076c9 3109 if (intel_crtc->base.state->active) {
a54746e3
VK		 3110 active_crtc_cnt++;
3111 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3112
3113 drrs_status_per_crtc(m, dev, intel_crtc);
3114 }
3115
3116 drm_modeset_unlock(&intel_crtc->base.mutex);
3117 }
3118
3119 if (!active_crtc_cnt)
3120 seq_puts(m, "No active crtc found\n");
3121
3122 return 0;
3123}
3124
07144428
DL		 3125struct pipe_crc_info {
3126 const char *name;
3127 struct drm_device *dev;
3128 enum pipe pipe;
3129};
3130
11bed958
DA		 3131static int i915_dp_mst_info(struct seq_file *m, void *unused)
3132{
3133 struct drm_info_node *node = (struct drm_info_node *) m->private;
3134 struct drm_device *dev = node->minor->dev;
3135 struct drm_encoder *encoder;
3136 struct intel_encoder *intel_encoder;
3137 struct intel_digital_port *intel_dig_port;
3138 drm_modeset_lock_all(dev);
3139 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3140 intel_encoder = to_intel_encoder(encoder);
3141 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3142 continue;
3143 intel_dig_port = enc_to_dig_port(encoder);
3144 if (!intel_dig_port->dp.can_mst)
3145 continue;
3146
3147 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3148 }
3149 drm_modeset_unlock_all(dev);
3150 return 0;
3151}
3152
07144428
DL		 3153static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3154{
be5c7a90
DL		 3155 struct pipe_crc_info *info = inode->i_private;
3156 struct drm_i915_private *dev_priv = info->dev->dev_private;
3157 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3158
7eb1c496
DV		 3159 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3160 return -ENODEV;
3161
d538bbdf
DL		 3162 spin_lock_irq(&pipe_crc->lock);
3163
3164 if (pipe_crc->opened) {
3165 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 3166 return -EBUSY; /* already open */
3167 }
3168
d538bbdf 3169 pipe_crc->opened = true;
07144428
DL		 3170 filep->private_data = inode->i_private;
3171
d538bbdf
DL		 3172 spin_unlock_irq(&pipe_crc->lock);
3173
07144428
DL		 3174 return 0;
3175}
3176
3177static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3178{
be5c7a90
DL		 3179 struct pipe_crc_info *info = inode->i_private;
3180 struct drm_i915_private *dev_priv = info->dev->dev_private;
3181 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3182
d538bbdf
DL		 3183 spin_lock_irq(&pipe_crc->lock);
3184 pipe_crc->opened = false;
3185 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 3186
07144428
DL		 3187 return 0;
3188}
3189
3190/* (6 fields, 8 chars each, space separated (5) + '\n') */
3191#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3192/* account for \'0' */
3193#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3194
3195static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 3196{
d538bbdf
DL		 3197 assert_spin_locked(&pipe_crc->lock);
3198 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3199 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 3200}
3201
3202static ssize_t
3203i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3204 loff_t *pos)
3205{
3206 struct pipe_crc_info *info = filep->private_data;
3207 struct drm_device *dev = info->dev;
3208 struct drm_i915_private *dev_priv = dev->dev_private;
3209 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3210 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 3211 int n_entries;
07144428
DL		 3212 ssize_t bytes_read;
3213
3214 /*
3215 * Don't allow user space to provide buffers not big enough to hold
3216 * a line of data.
3217 */
3218 if (count < PIPE_CRC_LINE_LEN)
3219 return -EINVAL;
3220
3221 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 3222 return 0;
07144428
DL		 3223
3224 /* nothing to read */
d538bbdf 3225 spin_lock_irq(&pipe_crc->lock);
07144428 3226 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 3227 int ret;
3228
3229 if (filep->f_flags & O_NONBLOCK) {
3230 spin_unlock_irq(&pipe_crc->lock);
07144428 3231 return -EAGAIN;
d538bbdf 3232 }
07144428 3233
d538bbdf
DL		 3234 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3235 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3236 if (ret) {
3237 spin_unlock_irq(&pipe_crc->lock);
3238 return ret;
3239 }
8bf1e9f1
SH		 3240 }
3241
07144428 3242 /* We now have one or more entries to read */
9ad6d99f 3243 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 3244
07144428 3245 bytes_read = 0;
9ad6d99f
VS		 3246 while (n_entries > 0) {
3247 struct intel_pipe_crc_entry *entry =
3248 &pipe_crc->entries[pipe_crc->tail];
07144428 3249 int ret;
8bf1e9f1 3250
9ad6d99f
VS		 3251 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3252 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3253 break;
3254
3255 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3256 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3257
07144428
DL		 3258 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3259 "%8u %8x %8x %8x %8x %8x\n",
3260 entry->frame, entry->crc[0],
3261 entry->crc[1], entry->crc[2],
3262 entry->crc[3], entry->crc[4]);
3263
9ad6d99f
VS		 3264 spin_unlock_irq(&pipe_crc->lock);
3265
3266 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 3267 if (ret == PIPE_CRC_LINE_LEN)
3268 return -EFAULT;
b2c88f5b 3269
9ad6d99f
VS		 3270 user_buf += PIPE_CRC_LINE_LEN;
3271 n_entries--;
3272
3273 spin_lock_irq(&pipe_crc->lock);
3274 }
8bf1e9f1 3275
d538bbdf
DL		 3276 spin_unlock_irq(&pipe_crc->lock);
3277
07144428
DL		 3278 return bytes_read;
3279}
3280
3281static const struct file_operations i915_pipe_crc_fops = {
3282 .owner = THIS_MODULE,
3283 .open = i915_pipe_crc_open,
3284 .read = i915_pipe_crc_read,
3285 .release = i915_pipe_crc_release,
3286};
3287
3288static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3289 {
3290 .name = "i915_pipe_A_crc",
3291 .pipe = PIPE_A,
3292 },
3293 {
3294 .name = "i915_pipe_B_crc",
3295 .pipe = PIPE_B,
3296 },
3297 {
3298 .name = "i915_pipe_C_crc",
3299 .pipe = PIPE_C,
3300 },
3301};
3302
3303static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3304 enum pipe pipe)
3305{
3306 struct drm_device *dev = minor->dev;
3307 struct dentry *ent;
3308 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3309
3310 info->dev = dev;
3311 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3312 &i915_pipe_crc_fops);
f3c5fe97
WY		 3313 if (!ent)
3314 return -ENOMEM;
07144428
DL		 3315
3316 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 3317}
3318
e8dfcf78 3319static const char * const pipe_crc_sources[] = {
926321d5
DV		 3320 "none",
3321 "plane1",
3322 "plane2",
3323 "pf",
5b3a856b 3324 "pipe",
3d099a05
DV		 3325 "TV",
3326 "DP-B",
3327 "DP-C",
3328 "DP-D",
46a19188 3329 "auto",
926321d5
DV		 3330};
3331
3332static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3333{
3334 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3335 return pipe_crc_sources[source];
3336}
3337
bd9db02f 3338static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 3339{
3340 struct drm_device *dev = m->private;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342 int i;
3343
3344 for (i = 0; i < I915_MAX_PIPES; i++)
3345 seq_printf(m, "%c %s\n", pipe_name(i),
3346 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3347
3348 return 0;
3349}
3350
bd9db02f 3351static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3352{
3353 struct drm_device *dev = inode->i_private;
3354
bd9db02f 3355 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3356}
3357
46a19188 3358static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3359 uint32_t *val)
3360{
46a19188
DV		 3361 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3362 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3363
3364 switch (*source) {
52f843f6
DV		 3365 case INTEL_PIPE_CRC_SOURCE_PIPE:
3366 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3367 break;
3368 case INTEL_PIPE_CRC_SOURCE_NONE:
3369 *val = 0;
3370 break;
3371 default:
3372 return -EINVAL;
3373 }
3374
3375 return 0;
3376}
3377
46a19188
DV		 3378static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3379 enum intel_pipe_crc_source *source)
3380{
3381 struct intel_encoder *encoder;
3382 struct intel_crtc *crtc;
26756809 3383 struct intel_digital_port *dig_port;
46a19188
DV		 3384 int ret = 0;
3385
3386 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3387
6e9f798d 3388 drm_modeset_lock_all(dev);
b2784e15 3389 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3390 if (!encoder->base.crtc)
3391 continue;
3392
3393 crtc = to_intel_crtc(encoder->base.crtc);
3394
3395 if (crtc->pipe != pipe)
3396 continue;
3397
3398 switch (encoder->type) {
3399 case INTEL_OUTPUT_TVOUT:
3400 *source = INTEL_PIPE_CRC_SOURCE_TV;
3401 break;
3402 case INTEL_OUTPUT_DISPLAYPORT:
3403 case INTEL_OUTPUT_EDP:
26756809
DV		 3404 dig_port = enc_to_dig_port(&encoder->base);
3405 switch (dig_port->port) {
3406 case PORT_B:
3407 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3408 break;
3409 case PORT_C:
3410 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3411 break;
3412 case PORT_D:
3413 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3414 break;
3415 default:
3416 WARN(1, "nonexisting DP port %c\n",
3417 port_name(dig_port->port));
3418 break;
3419 }
46a19188 3420 break;
6847d71b
PZ		 3421 default:
3422 break;
46a19188
DV		 3423 }
3424 }
6e9f798d 3425 drm_modeset_unlock_all(dev);
46a19188
DV		 3426
3427 return ret;
3428}
3429
3430static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3431 enum pipe pipe,
3432 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3433 uint32_t *val)
3434{
8d2f24ca
DV		 3435 struct drm_i915_private *dev_priv = dev->dev_private;
3436 bool need_stable_symbols = false;
3437
46a19188
DV		 3438 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3439 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3440 if (ret)
3441 return ret;
3442 }
3443
3444 switch (*source) {
7ac0129b
DV		 3445 case INTEL_PIPE_CRC_SOURCE_PIPE:
3446 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3447 break;
3448 case INTEL_PIPE_CRC_SOURCE_DP_B:
3449 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3450 need_stable_symbols = true;
7ac0129b
DV		 3451 break;
3452 case INTEL_PIPE_CRC_SOURCE_DP_C:
3453 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3454 need_stable_symbols = true;
7ac0129b 3455 break;
2be57922
VS		 3456 case INTEL_PIPE_CRC_SOURCE_DP_D:
3457 if (!IS_CHERRYVIEW(dev))
3458 return -EINVAL;
3459 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3460 need_stable_symbols = true;
3461 break;
7ac0129b
DV		 3462 case INTEL_PIPE_CRC_SOURCE_NONE:
3463 *val = 0;
3464 break;
3465 default:
3466 return -EINVAL;
3467 }
3468
8d2f24ca
DV		 3469 /*
3470 * When the pipe CRC tap point is after the transcoders we need
3471 * to tweak symbol-level features to produce a deterministic series of
3472 * symbols for a given frame. We need to reset those features only once
3473 * a frame (instead of every nth symbol):
3474 * - DC-balance: used to ensure a better clock recovery from the data
3475 * link (SDVO)
3476 * - DisplayPort scrambling: used for EMI reduction
3477 */
3478 if (need_stable_symbols) {
3479 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3480
8d2f24ca 3481 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3482 switch (pipe) {
3483 case PIPE_A:
8d2f24ca 3484 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3485 break;
3486 case PIPE_B:
8d2f24ca 3487 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3488 break;
3489 case PIPE_C:
3490 tmp |= PIPE_C_SCRAMBLE_RESET;
3491 break;
3492 default:
3493 return -EINVAL;
3494 }
8d2f24ca
DV		 3495 I915_WRITE(PORT_DFT2_G4X, tmp);
3496 }
3497
7ac0129b
DV		 3498 return 0;
3499}
3500
4b79ebf7 3501static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3502 enum pipe pipe,
3503 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3504 uint32_t *val)
3505{
84093603
DV		 3506 struct drm_i915_private *dev_priv = dev->dev_private;
3507 bool need_stable_symbols = false;
3508
46a19188
DV		 3509 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3510 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3511 if (ret)
3512 return ret;
3513 }
3514
3515 switch (*source) {
4b79ebf7
DV		 3516 case INTEL_PIPE_CRC_SOURCE_PIPE:
3517 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3518 break;
3519 case INTEL_PIPE_CRC_SOURCE_TV:
3520 if (!SUPPORTS_TV(dev))
3521 return -EINVAL;
3522 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3523 break;
3524 case INTEL_PIPE_CRC_SOURCE_DP_B:
3525 if (!IS_G4X(dev))
3526 return -EINVAL;
3527 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3528 need_stable_symbols = true;
4b79ebf7
DV		 3529 break;
3530 case INTEL_PIPE_CRC_SOURCE_DP_C:
3531 if (!IS_G4X(dev))
3532 return -EINVAL;
3533 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3534 need_stable_symbols = true;
4b79ebf7
DV		 3535 break;
3536 case INTEL_PIPE_CRC_SOURCE_DP_D:
3537 if (!IS_G4X(dev))
3538 return -EINVAL;
3539 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3540 need_stable_symbols = true;
4b79ebf7
DV		 3541 break;
3542 case INTEL_PIPE_CRC_SOURCE_NONE:
3543 *val = 0;
3544 break;
3545 default:
3546 return -EINVAL;
3547 }
3548
84093603
DV		 3549 /*
3550 * When the pipe CRC tap point is after the transcoders we need
3551 * to tweak symbol-level features to produce a deterministic series of
3552 * symbols for a given frame. We need to reset those features only once
3553 * a frame (instead of every nth symbol):
3554 * - DC-balance: used to ensure a better clock recovery from the data
3555 * link (SDVO)
3556 * - DisplayPort scrambling: used for EMI reduction
3557 */
3558 if (need_stable_symbols) {
3559 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3560
3561 WARN_ON(!IS_G4X(dev));
3562
3563 I915_WRITE(PORT_DFT_I9XX,
3564 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3565
3566 if (pipe == PIPE_A)
3567 tmp |= PIPE_A_SCRAMBLE_RESET;
3568 else
3569 tmp |= PIPE_B_SCRAMBLE_RESET;
3570
3571 I915_WRITE(PORT_DFT2_G4X, tmp);
3572 }
3573
4b79ebf7
DV		 3574 return 0;
3575}
3576
8d2f24ca
DV		 3577static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3578 enum pipe pipe)
3579{
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3582
eb736679
VS		 3583 switch (pipe) {
3584 case PIPE_A:
8d2f24ca 3585 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3586 break;
3587 case PIPE_B:
8d2f24ca 3588 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3589 break;
3590 case PIPE_C:
3591 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3592 break;
3593 default:
3594 return;
3595 }
8d2f24ca
DV		 3596 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3597 tmp &= ~DC_BALANCE_RESET_VLV;
3598 I915_WRITE(PORT_DFT2_G4X, tmp);
3599
3600}
3601
84093603
DV		 3602static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3603 enum pipe pipe)
3604{
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3607
3608 if (pipe == PIPE_A)
3609 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3610 else
3611 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3612 I915_WRITE(PORT_DFT2_G4X, tmp);
3613
3614 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3615 I915_WRITE(PORT_DFT_I9XX,
3616 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3617 }
3618}
3619
46a19188 3620static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3621 uint32_t *val)
3622{
46a19188
DV		 3623 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3624 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3625
3626 switch (*source) {
5b3a856b
DV		 3627 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3628 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3629 break;
3630 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3631 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3632 break;
5b3a856b
DV		 3633 case INTEL_PIPE_CRC_SOURCE_PIPE:
3634 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3635 break;
3d099a05 3636 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3637 *val = 0;
3638 break;
3d099a05
DV		 3639 default:
3640 return -EINVAL;
5b3a856b
DV		 3641 }
3642
3643 return 0;
3644}
3645
fabf6e51
DV		 3646static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3647{
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 struct intel_crtc *crtc =
3650 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3651 struct intel_crtc_state *pipe_config;
fabf6e51
DV		 3652
3653 drm_modeset_lock_all(dev);
f77076c9
ML		 3654 pipe_config = to_intel_crtc_state(crtc->base.state);
3655
fabf6e51
DV		 3656 /*
3657 * If we use the eDP transcoder we need to make sure that we don't
3658 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3659 * relevant on hsw with pipe A when using the always-on power well
3660 * routing.
3661 */
f77076c9
ML		 3662 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3663 !pipe_config->pch_pfit.enabled) {
3664 bool active = pipe_config->base.active;
1b509259 3665
f77076c9 3666 if (active) {
1b509259 3667 intel_crtc_control(&crtc->base, false);
f77076c9
ML		 3668 pipe_config = to_intel_crtc_state(crtc->base.state);
3669 }
1b509259 3670
f77076c9 3671 pipe_config->pch_pfit.force_thru = true;
fabf6e51
DV		 3672
3673 intel_display_power_get(dev_priv,
3674 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3675
1b509259
ML		 3676 if (active)
3677 intel_crtc_control(&crtc->base, true);
fabf6e51
DV		 3678 }
3679 drm_modeset_unlock_all(dev);
3680}
3681
3682static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3683{
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *crtc =
3686 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
f77076c9 3687 struct intel_crtc_state *pipe_config;
fabf6e51
DV		 3688
3689 drm_modeset_lock_all(dev);
3690 /*
3691 * If we use the eDP transcoder we need to make sure that we don't
3692 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3693 * relevant on hsw with pipe A when using the always-on power well
3694 * routing.
3695 */
f77076c9
ML		 3696 pipe_config = to_intel_crtc_state(crtc->base.state);
3697 if (pipe_config->pch_pfit.force_thru) {
3698 bool active = pipe_config->base.active;
fabf6e51 3699
f77076c9 3700 if (active) {
1b509259 3701 intel_crtc_control(&crtc->base, false);
f77076c9
ML		 3702 pipe_config = to_intel_crtc_state(crtc->base.state);
3703 }
fabf6e51 3704
f77076c9 3705 pipe_config->pch_pfit.force_thru = false;
fabf6e51
DV		 3706
3707 intel_display_power_put(dev_priv,
3708 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
1b509259
ML		 3709
3710 if (active)
3711 intel_crtc_control(&crtc->base, true);
fabf6e51
DV		 3712 }
3713 drm_modeset_unlock_all(dev);
3714}
3715
3716static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3717 enum pipe pipe,
3718 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3719 uint32_t *val)
3720{
46a19188
DV		 3721 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3722 *source = INTEL_PIPE_CRC_SOURCE_PF;
3723
3724 switch (*source) {
5b3a856b
DV		 3725 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3726 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3727 break;
3728 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3729 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3730 break;
3731 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3732 if (IS_HASWELL(dev) && pipe == PIPE_A)
3733 hsw_trans_edp_pipe_A_crc_wa(dev);
3734
5b3a856b
DV		 3735 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3736 break;
3d099a05 3737 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3738 *val = 0;
3739 break;
3d099a05
DV		 3740 default:
3741 return -EINVAL;
5b3a856b
DV		 3742 }
3743
3744 return 0;
3745}
3746
926321d5
DV		 3747static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3748 enum intel_pipe_crc_source source)
3749{
3750 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3751 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3752 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3753 pipe));
432f3342 3754 u32 val = 0; /* shut up gcc */
5b3a856b 3755 int ret;
926321d5 3756
cc3da175
DL		 3757 if (pipe_crc->source == source)
3758 return 0;
3759
ae676fcd
DL		 3760 /* forbid changing the source without going back to 'none' */
3761 if (pipe_crc->source && source)
3762 return -EINVAL;
3763
9d8b0588
DV		 3764 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3765 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3766 return -EIO;
3767 }
3768
52f843f6 3769 if (IS_GEN2(dev))
46a19188 3770 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3771 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3772 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3773 else if (IS_VALLEYVIEW(dev))
fabf6e51 3774 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3775 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3776 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3777 else
fabf6e51 3778 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3779
3780 if (ret != 0)
3781 return ret;
3782
4b584369
DL		 3783 /* none -> real source transition */
3784 if (source) {
4252fbc3
VS		 3785 struct intel_pipe_crc_entry *entries;
3786
7cd6ccff
DL		 3787 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3788 pipe_name(pipe), pipe_crc_source_name(source));
3789
3cf54b34
VS		 3790 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3791 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3792 GFP_KERNEL);
3793 if (!entries)
e5f75aca
DL		 3794 return -ENOMEM;
3795
8c740dce
PZ		 3796 /*
3797 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3798 * enabled and disabled dynamically based on package C states,
3799 * user space can't make reliable use of the CRCs, so let's just
3800 * completely disable it.
3801 */
3802 hsw_disable_ips(crtc);
3803
d538bbdf 3804 spin_lock_irq(&pipe_crc->lock);
64387b61 3805 kfree(pipe_crc->entries);
4252fbc3 3806 pipe_crc->entries = entries;
d538bbdf
DL		 3807 pipe_crc->head = 0;
3808 pipe_crc->tail = 0;
3809 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3810 }
3811
cc3da175 3812 pipe_crc->source = source;
926321d5 3813
926321d5
DV		 3814 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3815 POSTING_READ(PIPE_CRC_CTL(pipe));
3816
e5f75aca
DL		 3817 /* real source -> none transition */
3818 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3819 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3820 struct intel_crtc *crtc =
3821 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3822
7cd6ccff
DL		 3823 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3824 pipe_name(pipe));
3825
a33d7105 3826 drm_modeset_lock(&crtc->base.mutex, NULL);
f77076c9 3827 if (crtc->base.state->active)
a33d7105
DV		 3828 intel_wait_for_vblank(dev, pipe);
3829 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3830
d538bbdf
DL		 3831 spin_lock_irq(&pipe_crc->lock);
3832 entries = pipe_crc->entries;
e5f75aca 3833 pipe_crc->entries = NULL;
9ad6d99f
VS		 3834 pipe_crc->head = 0;
3835 pipe_crc->tail = 0;
d538bbdf
DL		 3836 spin_unlock_irq(&pipe_crc->lock);
3837
3838 kfree(entries);
84093603
DV		 3839
3840 if (IS_G4X(dev))
3841 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3842 else if (IS_VALLEYVIEW(dev))
3843 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3844 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3845 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3846
3847 hsw_enable_ips(crtc);
e5f75aca
DL		 3848 }
3849
926321d5
DV		 3850 return 0;
3851}
3852
3853/*
3854 * Parse pipe CRC command strings:
b94dec87
DL		 3855 * command: wsp* object wsp+ name wsp+ source wsp*
3856 * object: 'pipe'
3857 * name: (A | B | C)
926321d5
DV		 3858 * source: (none | plane1 | plane2 | pf)
3859 * wsp: (#0x20 | #0x9 | #0xA)+
3860 *
3861 * eg.:
b94dec87
DL		 3862 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3863 * "pipe A none" -> Stop CRC
926321d5 3864 */
bd9db02f 3865static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3866{
3867 int n_words = 0;
3868
3869 while (*buf) {
3870 char *end;
3871
3872 /* skip leading white space */
3873 buf = skip_spaces(buf);
3874 if (!*buf)
3875 break; /* end of buffer */
3876
3877 /* find end of word */
3878 for (end = buf; *end && !isspace(*end); end++)
3879 ;
3880
3881 if (n_words == max_words) {
3882 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3883 max_words);
3884 return -EINVAL; /* ran out of words[] before bytes */
3885 }
3886
3887 if (*end)
3888 *end++ = '\0';
3889 words[n_words++] = buf;
3890 buf = end;
3891 }
3892
3893 return n_words;
3894}
3895
b94dec87
DL		 3896enum intel_pipe_crc_object {
3897 PIPE_CRC_OBJECT_PIPE,
3898};
3899
e8dfcf78 3900static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3901 "pipe",
3902};
3903
3904static int
bd9db02f 3905display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3906{
3907 int i;
3908
3909 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3910 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3911 *o = i;
b94dec87
DL		 3912 return 0;
3913 }
3914
3915 return -EINVAL;
3916}
3917
bd9db02f 3918static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3919{
3920 const char name = buf[0];
3921
3922 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3923 return -EINVAL;
3924
3925 *pipe = name - 'A';
3926
3927 return 0;
3928}
3929
3930static int
bd9db02f 3931display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3932{
3933 int i;
3934
3935 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3936 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3937 *s = i;
926321d5
DV		 3938 return 0;
3939 }
3940
3941 return -EINVAL;
3942}
3943
bd9db02f 3944static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3945{
b94dec87 3946#define N_WORDS 3
926321d5 3947 int n_words;
b94dec87 3948 char *words[N_WORDS];
926321d5 3949 enum pipe pipe;
b94dec87 3950 enum intel_pipe_crc_object object;
926321d5
DV		 3951 enum intel_pipe_crc_source source;
3952
bd9db02f 3953 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3954 if (n_words != N_WORDS) {
3955 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3956 N_WORDS);
3957 return -EINVAL;
3958 }
3959
bd9db02f 3960 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3961 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3962 return -EINVAL;
3963 }
3964
bd9db02f 3965 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3966 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3967 return -EINVAL;
3968 }
3969
bd9db02f 3970 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3971 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3972 return -EINVAL;
3973 }
3974
3975 return pipe_crc_set_source(dev, pipe, source);
3976}
3977
bd9db02f
DL		 3978static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3979 size_t len, loff_t *offp)
926321d5
DV		 3980{
3981 struct seq_file *m = file->private_data;
3982 struct drm_device *dev = m->private;
3983 char *tmpbuf;
3984 int ret;
3985
3986 if (len == 0)
3987 return 0;
3988
3989 if (len > PAGE_SIZE - 1) {
3990 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3991 PAGE_SIZE);
3992 return -E2BIG;
3993 }
3994
3995 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3996 if (!tmpbuf)
3997 return -ENOMEM;
3998
3999 if (copy_from_user(tmpbuf, ubuf, len)) {
4000 ret = -EFAULT;
4001 goto out;
4002 }
4003 tmpbuf[len] = '\0';
4004
bd9db02f 4005 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 4006
4007out:
4008 kfree(tmpbuf);
4009 if (ret < 0)
4010 return ret;
4011
4012 *offp += len;
4013 return len;
4014}
4015
bd9db02f 4016static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 4017 .owner = THIS_MODULE,
bd9db02f 4018 .open = display_crc_ctl_open,
926321d5
DV		 4019 .read = seq_read,
4020 .llseek = seq_lseek,
4021 .release = single_release,
bd9db02f 4022 .write = display_crc_ctl_write
926321d5
DV		 4023};
4024
eb3394fa
TP		 4025static ssize_t i915_displayport_test_active_write(struct file *file,
4026 const char __user *ubuf,
4027 size_t len, loff_t *offp)
4028{
4029 char *input_buffer;
4030 int status = 0;
4031 struct seq_file *m;
4032 struct drm_device *dev;
4033 struct drm_connector *connector;
4034 struct list_head *connector_list;
4035 struct intel_dp *intel_dp;
4036 int val = 0;
4037
4038 m = file->private_data;
4039 if (!m) {
4040 status = -ENODEV;
4041 return status;
4042 }
4043 dev = m->private;
4044
4045 if (!dev) {
4046 status = -ENODEV;
4047 return status;
4048 }
4049 connector_list = &dev->mode_config.connector_list;
4050
4051 if (len == 0)
4052 return 0;
4053
4054 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4055 if (!input_buffer)
4056 return -ENOMEM;
4057
4058 if (copy_from_user(input_buffer, ubuf, len)) {
4059 status = -EFAULT;
4060 goto out;
4061 }
4062
4063 input_buffer[len] = '\0';
4064 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4065
4066 list_for_each_entry(connector, connector_list, head) {
4067
4068 if (connector->connector_type !=
4069 DRM_MODE_CONNECTOR_DisplayPort)
4070 continue;
4071
4072 if (connector->connector_type ==
4073 DRM_MODE_CONNECTOR_DisplayPort &&
4074 connector->status == connector_status_connected &&
4075 connector->encoder != NULL) {
4076 intel_dp = enc_to_intel_dp(connector->encoder);
4077 status = kstrtoint(input_buffer, 10, &val);
4078 if (status < 0)
4079 goto out;
4080 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4081 /* To prevent erroneous activation of the compliance
4082 * testing code, only accept an actual value of 1 here
4083 */
4084 if (val == 1)
4085 intel_dp->compliance_test_active = 1;
4086 else
4087 intel_dp->compliance_test_active = 0;
4088 }
4089 }
4090out:
4091 kfree(input_buffer);
4092 if (status < 0)
4093 return status;
4094
4095 *offp += len;
4096 return len;
4097}
4098
4099static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4100{
4101 struct drm_device *dev = m->private;
4102 struct drm_connector *connector;
4103 struct list_head *connector_list = &dev->mode_config.connector_list;
4104 struct intel_dp *intel_dp;
4105
4106 if (!dev)
4107 return -ENODEV;
4108
4109 list_for_each_entry(connector, connector_list, head) {
4110
4111 if (connector->connector_type !=
4112 DRM_MODE_CONNECTOR_DisplayPort)
4113 continue;
4114
4115 if (connector->status == connector_status_connected &&
4116 connector->encoder != NULL) {
4117 intel_dp = enc_to_intel_dp(connector->encoder);
4118 if (intel_dp->compliance_test_active)
4119 seq_puts(m, "1");
4120 else
4121 seq_puts(m, "0");
4122 } else
4123 seq_puts(m, "0");
4124 }
4125
4126 return 0;
4127}
4128
4129static int i915_displayport_test_active_open(struct inode *inode,
4130 struct file *file)
4131{
4132 struct drm_device *dev = inode->i_private;
4133
4134 return single_open(file, i915_displayport_test_active_show, dev);
4135}
4136
4137static const struct file_operations i915_displayport_test_active_fops = {
4138 .owner = THIS_MODULE,
4139 .open = i915_displayport_test_active_open,
4140 .read = seq_read,
4141 .llseek = seq_lseek,
4142 .release = single_release,
4143 .write = i915_displayport_test_active_write
4144};
4145
4146static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4147{
4148 struct drm_device *dev = m->private;
4149 struct drm_connector *connector;
4150 struct list_head *connector_list = &dev->mode_config.connector_list;
4151 struct intel_dp *intel_dp;
4152
4153 if (!dev)
4154 return -ENODEV;
4155
4156 list_for_each_entry(connector, connector_list, head) {
4157
4158 if (connector->connector_type !=
4159 DRM_MODE_CONNECTOR_DisplayPort)
4160 continue;
4161
4162 if (connector->status == connector_status_connected &&
4163 connector->encoder != NULL) {
4164 intel_dp = enc_to_intel_dp(connector->encoder);
4165 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4166 } else
4167 seq_puts(m, "0");
4168 }
4169
4170 return 0;
4171}
4172static int i915_displayport_test_data_open(struct inode *inode,
4173 struct file *file)
4174{
4175 struct drm_device *dev = inode->i_private;
4176
4177 return single_open(file, i915_displayport_test_data_show, dev);
4178}
4179
4180static const struct file_operations i915_displayport_test_data_fops = {
4181 .owner = THIS_MODULE,
4182 .open = i915_displayport_test_data_open,
4183 .read = seq_read,
4184 .llseek = seq_lseek,
4185 .release = single_release
4186};
4187
4188static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4189{
4190 struct drm_device *dev = m->private;
4191 struct drm_connector *connector;
4192 struct list_head *connector_list = &dev->mode_config.connector_list;
4193 struct intel_dp *intel_dp;
4194
4195 if (!dev)
4196 return -ENODEV;
4197
4198 list_for_each_entry(connector, connector_list, head) {
4199
4200 if (connector->connector_type !=
4201 DRM_MODE_CONNECTOR_DisplayPort)
4202 continue;
4203
4204 if (connector->status == connector_status_connected &&
4205 connector->encoder != NULL) {
4206 intel_dp = enc_to_intel_dp(connector->encoder);
4207 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4208 } else
4209 seq_puts(m, "0");
4210 }
4211
4212 return 0;
4213}
4214
4215static int i915_displayport_test_type_open(struct inode *inode,
4216 struct file *file)
4217{
4218 struct drm_device *dev = inode->i_private;
4219
4220 return single_open(file, i915_displayport_test_type_show, dev);
4221}
4222
4223static const struct file_operations i915_displayport_test_type_fops = {
4224 .owner = THIS_MODULE,
4225 .open = i915_displayport_test_type_open,
4226 .read = seq_read,
4227 .llseek = seq_lseek,
4228 .release = single_release
4229};
4230
97e94b22 4231static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 4232{
4233 struct drm_device *dev = m->private;
369a1342 4234 int level;
de38b95c
VS		 4235 int num_levels;
4236
4237 if (IS_CHERRYVIEW(dev))
4238 num_levels = 3;
4239 else if (IS_VALLEYVIEW(dev))
4240 num_levels = 1;
4241 else
4242 num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 4243
4244 drm_modeset_lock_all(dev);
4245
4246 for (level = 0; level < num_levels; level++) {
4247 unsigned int latency = wm[level];
4248
97e94b22
DL		 4249 /*
4250 * - WM1+ latency values in 0.5us units
de38b95c 4251 * - latencies are in us on gen9/vlv/chv
97e94b22 4252 */
de38b95c 4253 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
97e94b22
DL		 4254 latency *= 10;
4255 else if (level > 0)
369a1342
VS		 4256 latency *= 5;
4257
4258 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 4259 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 4260 }
4261
4262 drm_modeset_unlock_all(dev);
4263}
4264
4265static int pri_wm_latency_show(struct seq_file *m, void *data)
4266{
4267 struct drm_device *dev = m->private;
97e94b22
DL		 4268 struct drm_i915_private *dev_priv = dev->dev_private;
4269 const uint16_t *latencies;
4270
4271 if (INTEL_INFO(dev)->gen >= 9)
4272 latencies = dev_priv->wm.skl_latency;
4273 else
4274 latencies = to_i915(dev)->wm.pri_latency;
369a1342 4275
97e94b22 4276 wm_latency_show(m, latencies);
369a1342
VS		 4277
4278 return 0;
4279}
4280
4281static int spr_wm_latency_show(struct seq_file *m, void *data)
4282{
4283 struct drm_device *dev = m->private;
97e94b22
DL		 4284 struct drm_i915_private *dev_priv = dev->dev_private;
4285 const uint16_t *latencies;
4286
4287 if (INTEL_INFO(dev)->gen >= 9)
4288 latencies = dev_priv->wm.skl_latency;
4289 else
4290 latencies = to_i915(dev)->wm.spr_latency;
369a1342 4291
97e94b22 4292 wm_latency_show(m, latencies);
369a1342
VS		 4293
4294 return 0;
4295}
4296
4297static int cur_wm_latency_show(struct seq_file *m, void *data)
4298{
4299 struct drm_device *dev = m->private;
97e94b22
DL		 4300 struct drm_i915_private *dev_priv = dev->dev_private;
4301 const uint16_t *latencies;
4302
4303 if (INTEL_INFO(dev)->gen >= 9)
4304 latencies = dev_priv->wm.skl_latency;
4305 else
4306 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4307
97e94b22 4308 wm_latency_show(m, latencies);
369a1342
VS		 4309
4310 return 0;
4311}
4312
4313static int pri_wm_latency_open(struct inode *inode, struct file *file)
4314{
4315 struct drm_device *dev = inode->i_private;
4316
de38b95c 4317 if (INTEL_INFO(dev)->gen < 5)
369a1342
VS		 4318 return -ENODEV;
4319
4320 return single_open(file, pri_wm_latency_show, dev);
4321}
4322
4323static int spr_wm_latency_open(struct inode *inode, struct file *file)
4324{
4325 struct drm_device *dev = inode->i_private;
4326
9ad0257c 4327 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4328 return -ENODEV;
4329
4330 return single_open(file, spr_wm_latency_show, dev);
4331}
4332
4333static int cur_wm_latency_open(struct inode *inode, struct file *file)
4334{
4335 struct drm_device *dev = inode->i_private;
4336
9ad0257c 4337 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 4338 return -ENODEV;
4339
4340 return single_open(file, cur_wm_latency_show, dev);
4341}
4342
4343static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 4344 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 4345{
4346 struct seq_file *m = file->private_data;
4347 struct drm_device *dev = m->private;
97e94b22 4348 uint16_t new[8] = { 0 };
de38b95c 4349 int num_levels;
369a1342
VS		 4350 int level;
4351 int ret;
4352 char tmp[32];
4353
de38b95c
VS		 4354 if (IS_CHERRYVIEW(dev))
4355 num_levels = 3;
4356 else if (IS_VALLEYVIEW(dev))
4357 num_levels = 1;
4358 else
4359 num_levels = ilk_wm_max_level(dev) + 1;
4360
369a1342
VS		 4361 if (len >= sizeof(tmp))
4362 return -EINVAL;
4363
4364 if (copy_from_user(tmp, ubuf, len))
4365 return -EFAULT;
4366
4367 tmp[len] = '\0';
4368
97e94b22
DL		 4369 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4370 &new[0], &new[1], &new[2], &new[3],
4371 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 4372 if (ret != num_levels)
4373 return -EINVAL;
4374
4375 drm_modeset_lock_all(dev);
4376
4377 for (level = 0; level < num_levels; level++)
4378 wm[level] = new[level];
4379
4380 drm_modeset_unlock_all(dev);
4381
4382 return len;
4383}
4384
4385
4386static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4387 size_t len, loff_t *offp)
4388{
4389 struct seq_file *m = file->private_data;
4390 struct drm_device *dev = m->private;
97e94b22
DL		 4391 struct drm_i915_private *dev_priv = dev->dev_private;
4392 uint16_t *latencies;
369a1342 4393
97e94b22
DL		 4394 if (INTEL_INFO(dev)->gen >= 9)
4395 latencies = dev_priv->wm.skl_latency;
4396 else
4397 latencies = to_i915(dev)->wm.pri_latency;
4398
4399 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4400}
4401
4402static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4403 size_t len, loff_t *offp)
4404{
4405 struct seq_file *m = file->private_data;
4406 struct drm_device *dev = m->private;
97e94b22
DL		 4407 struct drm_i915_private *dev_priv = dev->dev_private;
4408 uint16_t *latencies;
369a1342 4409
97e94b22
DL		 4410 if (INTEL_INFO(dev)->gen >= 9)
4411 latencies = dev_priv->wm.skl_latency;
4412 else
4413 latencies = to_i915(dev)->wm.spr_latency;
4414
4415 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4416}
4417
4418static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4419 size_t len, loff_t *offp)
4420{
4421 struct seq_file *m = file->private_data;
4422 struct drm_device *dev = m->private;
97e94b22
DL		 4423 struct drm_i915_private *dev_priv = dev->dev_private;
4424 uint16_t *latencies;
4425
4426 if (INTEL_INFO(dev)->gen >= 9)
4427 latencies = dev_priv->wm.skl_latency;
4428 else
4429 latencies = to_i915(dev)->wm.cur_latency;
369a1342 4430
97e94b22 4431 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 4432}
4433
4434static const struct file_operations i915_pri_wm_latency_fops = {
4435 .owner = THIS_MODULE,
4436 .open = pri_wm_latency_open,
4437 .read = seq_read,
4438 .llseek = seq_lseek,
4439 .release = single_release,
4440 .write = pri_wm_latency_write
4441};
4442
4443static const struct file_operations i915_spr_wm_latency_fops = {
4444 .owner = THIS_MODULE,
4445 .open = spr_wm_latency_open,
4446 .read = seq_read,
4447 .llseek = seq_lseek,
4448 .release = single_release,
4449 .write = spr_wm_latency_write
4450};
4451
4452static const struct file_operations i915_cur_wm_latency_fops = {
4453 .owner = THIS_MODULE,
4454 .open = cur_wm_latency_open,
4455 .read = seq_read,
4456 .llseek = seq_lseek,
4457 .release = single_release,
4458 .write = cur_wm_latency_write
4459};
4460
647416f9
KC		 4461static int
4462i915_wedged_get(void *data, u64 *val)
f3cd474b 4463{
647416f9 4464 struct drm_device *dev = data;
e277a1f8 4465 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 4466
647416f9 4467 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 4468
647416f9 4469 return 0;
f3cd474b
CW		 4470}
4471
647416f9
KC		 4472static int
4473i915_wedged_set(void *data, u64 val)
f3cd474b 4474{
647416f9 4475 struct drm_device *dev = data;
d46c0517
ID		 4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477
b8d24a06
MK		 4478 /*
4479 * There is no safeguard against this debugfs entry colliding
4480 * with the hangcheck calling same i915_handle_error() in
4481 * parallel, causing an explosion. For now we assume that the
4482 * test harness is responsible enough not to inject gpu hangs
4483 * while it is writing to 'i915_wedged'
4484 */
4485
4486 if (i915_reset_in_progress(&dev_priv->gpu_error))
4487 return -EAGAIN;
4488
d46c0517 4489 intel_runtime_pm_get(dev_priv);
f3cd474b 4490
58174462
MK		 4491 i915_handle_error(dev, val,
4492 "Manually setting wedged to %llu", val);
d46c0517
ID		 4493
4494 intel_runtime_pm_put(dev_priv);
4495
647416f9 4496 return 0;
f3cd474b
CW		 4497}
4498
647416f9
KC		 4499DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4500 i915_wedged_get, i915_wedged_set,
3a3b4f98 4501 "%llu\n");
f3cd474b 4502
647416f9
KC		 4503static int
4504i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 4505{
647416f9 4506 struct drm_device *dev = data;
e277a1f8 4507 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 4508
647416f9 4509 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 4510
647416f9 4511 return 0;
e5eb3d63
DV		 4512}
4513
647416f9
KC		 4514static int
4515i915_ring_stop_set(void *data, u64 val)
e5eb3d63 4516{
647416f9 4517 struct drm_device *dev = data;
e5eb3d63 4518 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4519 int ret;
e5eb3d63 4520
647416f9 4521 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 4522
22bcfc6a
DV		 4523 ret = mutex_lock_interruptible(&dev->struct_mutex);
4524 if (ret)
4525 return ret;
4526
99584db3 4527 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 4528 mutex_unlock(&dev->struct_mutex);
4529
647416f9 4530 return 0;
e5eb3d63
DV		 4531}
4532
647416f9
KC		 4533DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4534 i915_ring_stop_get, i915_ring_stop_set,
4535 "0x%08llx\n");
d5442303 4536
094f9a54
CW		 4537static int
4538i915_ring_missed_irq_get(void *data, u64 *val)
4539{
4540 struct drm_device *dev = data;
4541 struct drm_i915_private *dev_priv = dev->dev_private;
4542
4543 *val = dev_priv->gpu_error.missed_irq_rings;
4544 return 0;
4545}
4546
4547static int
4548i915_ring_missed_irq_set(void *data, u64 val)
4549{
4550 struct drm_device *dev = data;
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4552 int ret;
4553
4554 /* Lock against concurrent debugfs callers */
4555 ret = mutex_lock_interruptible(&dev->struct_mutex);
4556 if (ret)
4557 return ret;
4558 dev_priv->gpu_error.missed_irq_rings = val;
4559 mutex_unlock(&dev->struct_mutex);
4560
4561 return 0;
4562}
4563
4564DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4565 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4566 "0x%08llx\n");
4567
4568static int
4569i915_ring_test_irq_get(void *data, u64 *val)
4570{
4571 struct drm_device *dev = data;
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573
4574 *val = dev_priv->gpu_error.test_irq_rings;
4575
4576 return 0;
4577}
4578
4579static int
4580i915_ring_test_irq_set(void *data, u64 val)
4581{
4582 struct drm_device *dev = data;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584 int ret;
4585
4586 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4587
4588 /* Lock against concurrent debugfs callers */
4589 ret = mutex_lock_interruptible(&dev->struct_mutex);
4590 if (ret)
4591 return ret;
4592
4593 dev_priv->gpu_error.test_irq_rings = val;
4594 mutex_unlock(&dev->struct_mutex);
4595
4596 return 0;
4597}
4598
4599DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4600 i915_ring_test_irq_get, i915_ring_test_irq_set,
4601 "0x%08llx\n");
4602
dd624afd
CW		 4603#define DROP_UNBOUND 0x1
4604#define DROP_BOUND 0x2
4605#define DROP_RETIRE 0x4
4606#define DROP_ACTIVE 0x8
4607#define DROP_ALL (DROP_UNBOUND | \
4608 DROP_BOUND | \
4609 DROP_RETIRE | \
4610 DROP_ACTIVE)
647416f9
KC		 4611static int
4612i915_drop_caches_get(void *data, u64 *val)
dd624afd 4613{
647416f9 4614 *val = DROP_ALL;
dd624afd 4615
647416f9 4616 return 0;
dd624afd
CW		 4617}
4618
647416f9
KC		 4619static int
4620i915_drop_caches_set(void *data, u64 val)
dd624afd 4621{
647416f9 4622 struct drm_device *dev = data;
dd624afd 4623 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4624 int ret;
dd624afd 4625
2f9fe5ff 4626 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4627
4628 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4629 * on ioctls on -EAGAIN. */
4630 ret = mutex_lock_interruptible(&dev->struct_mutex);
4631 if (ret)
4632 return ret;
4633
4634 if (val & DROP_ACTIVE) {
4635 ret = i915_gpu_idle(dev);
4636 if (ret)
4637 goto unlock;
4638 }
4639
4640 if (val & (DROP_RETIRE | DROP_ACTIVE))
4641 i915_gem_retire_requests(dev);
4642
21ab4e74
CW		 4643 if (val & DROP_BOUND)
4644 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4645
21ab4e74
CW		 4646 if (val & DROP_UNBOUND)
4647 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4648
4649unlock:
4650 mutex_unlock(&dev->struct_mutex);
4651
647416f9 4652 return ret;
dd624afd
CW		 4653}
4654
647416f9
KC		 4655DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4656 i915_drop_caches_get, i915_drop_caches_set,
4657 "0x%08llx\n");
dd624afd 4658
647416f9
KC		 4659static int
4660i915_max_freq_get(void *data, u64 *val)
358733e9 4661{
647416f9 4662 struct drm_device *dev = data;
e277a1f8 4663 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4664 int ret;
004777cb 4665
daa3afb2 4666 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4667 return -ENODEV;
4668
5c9669ce
TR		 4669 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4670
4fc688ce 4671 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4672 if (ret)
4673 return ret;
358733e9 4674
7c59a9c1 4675 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4fc688ce 4676 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4677
647416f9 4678 return 0;
358733e9
JB		 4679}
4680
647416f9
KC		 4681static int
4682i915_max_freq_set(void *data, u64 val)
358733e9 4683{
647416f9 4684 struct drm_device *dev = data;
358733e9 4685 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4686 u32 hw_max, hw_min;
647416f9 4687 int ret;
004777cb 4688
daa3afb2 4689 if (INTEL_INFO(dev)->gen < 6)
004777cb 4690 return -ENODEV;
358733e9 4691
5c9669ce
TR		 4692 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4693
647416f9 4694 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4695
4fc688ce 4696 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4697 if (ret)
4698 return ret;
4699
358733e9
JB		 4700 /*
4701 * Turbo will still be enabled, but won't go above the set value.
4702 */
bc4d91f6 4703 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4704
bc4d91f6
AG		 4705 hw_max = dev_priv->rps.max_freq;
4706 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4707
b39fb297 4708 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4709 mutex_unlock(&dev_priv->rps.hw_lock);
4710 return -EINVAL;
0a073b84
JB		 4711 }
4712
b39fb297 4713 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1 4714
ffe02b40 4715 intel_set_rps(dev, val);
dd0a1aa1 4716
4fc688ce 4717 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4718
647416f9 4719 return 0;
358733e9
JB		 4720}
4721
647416f9
KC		 4722DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4723 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4724 "%llu\n");
358733e9 4725
647416f9
KC		 4726static int
4727i915_min_freq_get(void *data, u64 *val)
1523c310 4728{
647416f9 4729 struct drm_device *dev = data;
e277a1f8 4730 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4731 int ret;
004777cb 4732
daa3afb2 4733 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4734 return -ENODEV;
4735
5c9669ce
TR		 4736 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4737
4fc688ce 4738 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4739 if (ret)
4740 return ret;
1523c310 4741
7c59a9c1 4742 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4fc688ce 4743 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4744
647416f9 4745 return 0;
1523c310
JB		 4746}
4747
647416f9
KC		 4748static int
4749i915_min_freq_set(void *data, u64 val)
1523c310 4750{
647416f9 4751 struct drm_device *dev = data;
1523c310 4752 struct drm_i915_private *dev_priv = dev->dev_private;
bc4d91f6 4753 u32 hw_max, hw_min;
647416f9 4754 int ret;
004777cb 4755
daa3afb2 4756 if (INTEL_INFO(dev)->gen < 6)
004777cb 4757 return -ENODEV;
1523c310 4758
5c9669ce
TR		 4759 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4760
647416f9 4761 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4762
4fc688ce 4763 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4764 if (ret)
4765 return ret;
4766
1523c310
JB		 4767 /*
4768 * Turbo will still be enabled, but won't go below the set value.
4769 */
bc4d91f6 4770 val = intel_freq_opcode(dev_priv, val);
dd0a1aa1 4771
bc4d91f6
AG		 4772 hw_max = dev_priv->rps.max_freq;
4773 hw_min = dev_priv->rps.min_freq;
dd0a1aa1 4774
b39fb297 4775 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4776 mutex_unlock(&dev_priv->rps.hw_lock);
4777 return -EINVAL;
0a073b84 4778 }
dd0a1aa1 4779
b39fb297 4780 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1 4781
ffe02b40 4782 intel_set_rps(dev, val);
dd0a1aa1 4783
4fc688ce 4784 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4785
647416f9 4786 return 0;
1523c310
JB		 4787}
4788
647416f9
KC		 4789DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4790 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4791 "%llu\n");
1523c310 4792
647416f9
KC		 4793static int
4794i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4795{
647416f9 4796 struct drm_device *dev = data;
e277a1f8 4797 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4798 u32 snpcr;
647416f9 4799 int ret;
07b7ddd9 4800
004777cb
DV		 4801 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4802 return -ENODEV;
4803
22bcfc6a
DV		 4804 ret = mutex_lock_interruptible(&dev->struct_mutex);
4805 if (ret)
4806 return ret;
c8c8fb33 4807 intel_runtime_pm_get(dev_priv);
22bcfc6a 4808
07b7ddd9 4809 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4810
4811 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4812 mutex_unlock(&dev_priv->dev->struct_mutex);
4813
647416f9 4814 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4815
647416f9 4816 return 0;
07b7ddd9
JB		 4817}
4818
647416f9
KC		 4819static int
4820i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4821{
647416f9 4822 struct drm_device *dev = data;
07b7ddd9 4823 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4824 u32 snpcr;
07b7ddd9 4825
004777cb
DV		 4826 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4827 return -ENODEV;
4828
647416f9 4829 if (val > 3)
07b7ddd9
JB		 4830 return -EINVAL;
4831
c8c8fb33 4832 intel_runtime_pm_get(dev_priv);
647416f9 4833 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4834
4835 /* Update the cache sharing policy here as well */
4836 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4837 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4838 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4839 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4840
c8c8fb33 4841 intel_runtime_pm_put(dev_priv);
647416f9 4842 return 0;
07b7ddd9
JB		 4843}
4844
647416f9
KC		 4845DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4846 i915_cache_sharing_get, i915_cache_sharing_set,
4847 "%llu\n");
07b7ddd9 4848
5d39525a
JM		 4849struct sseu_dev_status {
4850 unsigned int slice_total;
4851 unsigned int subslice_total;
4852 unsigned int subslice_per_slice;
4853 unsigned int eu_total;
4854 unsigned int eu_per_subslice;
4855};
4856
4857static void cherryview_sseu_device_status(struct drm_device *dev,
4858 struct sseu_dev_status *stat)
4859{
4860 struct drm_i915_private *dev_priv = dev->dev_private;
4861 const int ss_max = 2;
4862 int ss;
4863 u32 sig1[ss_max], sig2[ss_max];
4864
4865 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4866 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4867 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4868 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4869
4870 for (ss = 0; ss < ss_max; ss++) {
4871 unsigned int eu_cnt;
4872
4873 if (sig1[ss] & CHV_SS_PG_ENABLE)
4874 /* skip disabled subslice */
4875 continue;
4876
4877 stat->slice_total = 1;
4878 stat->subslice_per_slice++;
4879 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4880 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4881 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4882 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4883 stat->eu_total += eu_cnt;
4884 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4885 }
4886 stat->subslice_total = stat->subslice_per_slice;
4887}
4888
4889static void gen9_sseu_device_status(struct drm_device *dev,
4890 struct sseu_dev_status *stat)
4891{
4892 struct drm_i915_private *dev_priv = dev->dev_private;
1c046bc1 4893 int s_max = 3, ss_max = 4;
5d39525a
JM		 4894 int s, ss;
4895 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4896
1c046bc1
JM		 4897 /* BXT has a single slice and at most 3 subslices. */
4898 if (IS_BROXTON(dev)) {
4899 s_max = 1;
4900 ss_max = 3;
4901 }
4902
4903 for (s = 0; s < s_max; s++) {
4904 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4905 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4906 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4907 }
4908
5d39525a
JM		 4909 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4910 GEN9_PGCTL_SSA_EU19_ACK |
4911 GEN9_PGCTL_SSA_EU210_ACK |
4912 GEN9_PGCTL_SSA_EU311_ACK;
4913 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4914 GEN9_PGCTL_SSB_EU19_ACK |
4915 GEN9_PGCTL_SSB_EU210_ACK |
4916 GEN9_PGCTL_SSB_EU311_ACK;
4917
4918 for (s = 0; s < s_max; s++) {
1c046bc1
JM		 4919 unsigned int ss_cnt = 0;
4920
5d39525a
JM		 4921 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4922 /* skip disabled slice */
4923 continue;
4924
4925 stat->slice_total++;
1c046bc1
JM		 4926
4927 if (IS_SKYLAKE(dev))
4928 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4929
5d39525a
JM		 4930 for (ss = 0; ss < ss_max; ss++) {
4931 unsigned int eu_cnt;
4932
1c046bc1
JM		 4933 if (IS_BROXTON(dev) &&
4934 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4935 /* skip disabled subslice */
4936 continue;
4937
4938 if (IS_BROXTON(dev))
4939 ss_cnt++;
4940
5d39525a
JM		 4941 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4942 eu_mask[ss%2]);
4943 stat->eu_total += eu_cnt;
4944 stat->eu_per_subslice = max(stat->eu_per_subslice,
4945 eu_cnt);
4946 }
1c046bc1
JM		 4947
4948 stat->subslice_total += ss_cnt;
4949 stat->subslice_per_slice = max(stat->subslice_per_slice,
4950 ss_cnt);
5d39525a
JM		 4951 }
4952}
4953
3873218f
JM		 4954static int i915_sseu_status(struct seq_file *m, void *unused)
4955{
4956 struct drm_info_node *node = (struct drm_info_node *) m->private;
4957 struct drm_device *dev = node->minor->dev;
5d39525a 4958 struct sseu_dev_status stat;
3873218f 4959
5575f03a 4960 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
3873218f
JM		 4961 return -ENODEV;
4962
4963 seq_puts(m, "SSEU Device Info\n");
4964 seq_printf(m, " Available Slice Total: %u\n",
4965 INTEL_INFO(dev)->slice_total);
4966 seq_printf(m, " Available Subslice Total: %u\n",
4967 INTEL_INFO(dev)->subslice_total);
4968 seq_printf(m, " Available Subslice Per Slice: %u\n",
4969 INTEL_INFO(dev)->subslice_per_slice);
4970 seq_printf(m, " Available EU Total: %u\n",
4971 INTEL_INFO(dev)->eu_total);
4972 seq_printf(m, " Available EU Per Subslice: %u\n",
4973 INTEL_INFO(dev)->eu_per_subslice);
4974 seq_printf(m, " Has Slice Power Gating: %s\n",
4975 yesno(INTEL_INFO(dev)->has_slice_pg));
4976 seq_printf(m, " Has Subslice Power Gating: %s\n",
4977 yesno(INTEL_INFO(dev)->has_subslice_pg));
4978 seq_printf(m, " Has EU Power Gating: %s\n",
4979 yesno(INTEL_INFO(dev)->has_eu_pg));
4980
7f992aba 4981 seq_puts(m, "SSEU Device Status\n");
5d39525a 4982 memset(&stat, 0, sizeof(stat));
5575f03a 4983 if (IS_CHERRYVIEW(dev)) {
5d39525a 4984 cherryview_sseu_device_status(dev, &stat);
1c046bc1 4985 } else if (INTEL_INFO(dev)->gen >= 9) {
5d39525a 4986 gen9_sseu_device_status(dev, &stat);
7f992aba 4987 }
5d39525a
JM		 4988 seq_printf(m, " Enabled Slice Total: %u\n",
4989 stat.slice_total);
4990 seq_printf(m, " Enabled Subslice Total: %u\n",
4991 stat.subslice_total);
4992 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
4993 stat.subslice_per_slice);
4994 seq_printf(m, " Enabled EU Total: %u\n",
4995 stat.eu_total);
4996 seq_printf(m, " Enabled EU Per Subslice: %u\n",
4997 stat.eu_per_subslice);
7f992aba 4998
3873218f
JM		 4999 return 0;
5000}
5001
6d794d42
BW		 5002static int i915_forcewake_open(struct inode *inode, struct file *file)
5003{
5004 struct drm_device *dev = inode->i_private;
5005 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 5006
075edca4 5007 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5008 return 0;
5009
6daccb0b 5010 intel_runtime_pm_get(dev_priv);
59bad947 5011 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 5012
5013 return 0;
5014}
5015
c43b5634 5016static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 5017{
5018 struct drm_device *dev = inode->i_private;
5019 struct drm_i915_private *dev_priv = dev->dev_private;
5020
075edca4 5021 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 5022 return 0;
5023
59bad947 5024 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6daccb0b 5025 intel_runtime_pm_put(dev_priv);
6d794d42
BW		 5026
5027 return 0;
5028}
5029
5030static const struct file_operations i915_forcewake_fops = {
5031 .owner = THIS_MODULE,
5032 .open = i915_forcewake_open,
5033 .release = i915_forcewake_release,
5034};
5035
5036static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5037{
5038 struct drm_device *dev = minor->dev;
5039 struct dentry *ent;
5040
5041 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 5042 S_IRUSR,
6d794d42
BW		 5043 root, dev,
5044 &i915_forcewake_fops);
f3c5fe97
WY		 5045 if (!ent)
5046 return -ENOMEM;
6d794d42 5047
8eb57294 5048 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 5049}
5050
6a9c308d
DV		 5051static int i915_debugfs_create(struct dentry *root,
5052 struct drm_minor *minor,
5053 const char *name,
5054 const struct file_operations *fops)
07b7ddd9
JB		 5055{
5056 struct drm_device *dev = minor->dev;
5057 struct dentry *ent;
5058
6a9c308d 5059 ent = debugfs_create_file(name,
07b7ddd9
JB		 5060 S_IRUGO | S_IWUSR,
5061 root, dev,
6a9c308d 5062 fops);
f3c5fe97
WY		 5063 if (!ent)
5064 return -ENOMEM;
07b7ddd9 5065
6a9c308d 5066 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 5067}
5068
06c5bf8c 5069static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 5070 {"i915_capabilities", i915_capabilities, 0},
73aa808f 5071 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 5072 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 5073 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 5074 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 5075 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 5076 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 5077 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 5078 {"i915_gem_request", i915_gem_request_info, 0},
5079 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 5080 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 5081 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 5082 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5083 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5084 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 5085 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
493018dc 5086 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
adb4bd12 5087 {"i915_frequency_info", i915_frequency_info, 0},
f654449a 5088 {"i915_hangcheck_info", i915_hangcheck_info, 0},
f97108d1 5089 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 5090 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 5091 {"i915_ring_freq_table", i915_ring_freq_table, 0},
9a851789 5092 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
b5e50c3f 5093 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 5094 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 5095 {"i915_sr_status", i915_sr_status, 0},
44834a67 5096 {"i915_opregion", i915_opregion, 0},
37811fcc 5097 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 5098 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 5099 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 5100 {"i915_execlists", i915_execlists, 0},
f65367b5 5101 {"i915_forcewake_domains", i915_forcewake_domains, 0},
ea16a3cd 5102 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 5103 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 5104 {"i915_llc", i915_llc, 0},
e91fd8c6 5105 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 5106 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 5107 {"i915_energy_uJ", i915_energy_uJ, 0},
6455c870 5108 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1da51581 5109 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 5110 {"i915_display_info", i915_display_info, 0},
e04934cf 5111 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 5112 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 5113 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 5114 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 5115 {"i915_ddb_info", i915_ddb_info, 0},
3873218f 5116 {"i915_sseu_status", i915_sseu_status, 0},
a54746e3 5117 {"i915_drrs_status", i915_drrs_status, 0},
1854d5ca 5118 {"i915_rps_boost_info", i915_rps_boost_info, 0},
2017263e 5119};
27c202ad 5120#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 5121
06c5bf8c 5122static const struct i915_debugfs_files {
34b9674c
DV		 5123 const char *name;
5124 const struct file_operations *fops;
5125} i915_debugfs_files[] = {
5126 {"i915_wedged", &i915_wedged_fops},
5127 {"i915_max_freq", &i915_max_freq_fops},
5128 {"i915_min_freq", &i915_min_freq_fops},
5129 {"i915_cache_sharing", &i915_cache_sharing_fops},
5130 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 5131 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5132 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 5133 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5134 {"i915_error_state", &i915_error_state_fops},
5135 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 5136 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 5137 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5138 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5139 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 5140 {"i915_fbc_false_color", &i915_fbc_fc_fops},
eb3394fa
TP		 5141 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5142 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5143 {"i915_dp_test_active", &i915_displayport_test_active_fops}
34b9674c
DV		 5144};
5145
07144428
DL		 5146void intel_display_crc_init(struct drm_device *dev)
5147{
5148 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 5149 enum pipe pipe;
07144428 5150
055e393f 5151 for_each_pipe(dev_priv, pipe) {
b378360e 5152 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 5153
d538bbdf
DL		 5154 pipe_crc->opened = false;
5155 spin_lock_init(&pipe_crc->lock);
07144428
DL		 5156 init_waitqueue_head(&pipe_crc->wq);
5157 }
5158}
5159
27c202ad 5160int i915_debugfs_init(struct drm_minor *minor)
2017263e 5161{
34b9674c 5162 int ret, i;
f3cd474b 5163
6d794d42 5164 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 5165 if (ret)
5166 return ret;
6a9c308d 5167
07144428
DL		 5168 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5169 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5170 if (ret)
5171 return ret;
5172 }
5173
34b9674c
DV		 5174 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5175 ret = i915_debugfs_create(minor->debugfs_root, minor,
5176 i915_debugfs_files[i].name,
5177 i915_debugfs_files[i].fops);
5178 if (ret)
5179 return ret;
5180 }
40633219 5181
27c202ad
BG		 5182 return drm_debugfs_create_files(i915_debugfs_list,
5183 I915_DEBUGFS_ENTRIES,
2017263e
BG		 5184 minor->debugfs_root, minor);
5185}
5186
27c202ad 5187void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 5188{
34b9674c
DV		 5189 int i;
5190
27c202ad
BG		 5191 drm_debugfs_remove_files(i915_debugfs_list,
5192 I915_DEBUGFS_ENTRIES, minor);
07144428 5193
6d794d42
BW		 5194 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5195 1, minor);
07144428 5196
e309a997 5197 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 5198 struct drm_info_list *info_list =
5199 (struct drm_info_list *)&i915_pipe_crc_data[i];
5200
5201 drm_debugfs_remove_files(info_list, 1, minor);
5202 }
5203
34b9674c
DV		 5204 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5205 struct drm_info_list *info_list =
5206 (struct drm_info_list *) i915_debugfs_files[i].fops;
5207
5208 drm_debugfs_remove_files(info_list, 1, minor);
5209 }
2017263e 5210}
aa7471d2
JN		 5211
5212struct dpcd_block {
5213 /* DPCD dump start address. */
5214 unsigned int offset;
5215 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5216 unsigned int end;
5217 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5218 size_t size;
5219 /* Only valid for eDP. */
5220 bool edp;
5221};
5222
5223static const struct dpcd_block i915_dpcd_debug[] = {
5224 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5225 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5226 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5227 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5228 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5229 { .offset = DP_SET_POWER },
5230 { .offset = DP_EDP_DPCD_REV },
5231 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5232 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5233 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5234};
5235
5236static int i915_dpcd_show(struct seq_file *m, void *data)
5237{
5238 struct drm_connector *connector = m->private;
5239 struct intel_dp *intel_dp =
5240 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5241 uint8_t buf[16];
5242 ssize_t err;
5243 int i;
5244
5c1a8875
MK		 5245 if (connector->status != connector_status_connected)
5246 return -ENODEV;
5247
aa7471d2
JN		 5248 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5249 const struct dpcd_block *b = &i915_dpcd_debug[i];
5250 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5251
5252 if (b->edp &&
5253 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5254 continue;
5255
5256 /* low tech for now */
5257 if (WARN_ON(size > sizeof(buf)))
5258 continue;
5259
5260 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5261 if (err <= 0) {
5262 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5263 size, b->offset, err);
5264 continue;
5265 }
5266
5267 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
b3f9d7d7 5268 }
aa7471d2
JN		 5269
5270 return 0;
5271}
5272
5273static int i915_dpcd_open(struct inode *inode, struct file *file)
5274{
5275 return single_open(file, i915_dpcd_show, inode->i_private);
5276}
5277
5278static const struct file_operations i915_dpcd_fops = {
5279 .owner = THIS_MODULE,
5280 .open = i915_dpcd_open,
5281 .read = seq_read,
5282 .llseek = seq_lseek,
5283 .release = single_release,
5284};
5285
5286/**
5287 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5288 * @connector: pointer to a registered drm_connector
5289 *
5290 * Cleanup will be done by drm_connector_unregister() through a call to
5291 * drm_debugfs_connector_remove().
5292 *
5293 * Returns 0 on success, negative error codes on error.
5294 */
5295int i915_debugfs_connector_add(struct drm_connector *connector)
5296{
5297 struct dentry *root = connector->debugfs_entry;
5298
5299 /* The connector must have been registered beforehands. */
5300 if (!root)
5301 return -ENODEV;
5302
5303 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5304 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5305 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5306 &i915_dpcd_fops);
5307
5308 return 0;
5309}
Linux kernel - Deliverables
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