Commit | Line | Data |
---|---|---|
2017263e BG |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Keith Packard <keithp@keithp.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/seq_file.h> | |
b2c88f5b | 30 | #include <linux/circ_buf.h> |
926321d5 | 31 | #include <linux/ctype.h> |
f3cd474b | 32 | #include <linux/debugfs.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
2d1a8a48 | 34 | #include <linux/export.h> |
6d2b8885 | 35 | #include <linux/list_sort.h> |
ec013e7f | 36 | #include <asm/msr-index.h> |
760285e7 | 37 | #include <drm/drmP.h> |
4e5359cd | 38 | #include "intel_drv.h" |
e5c65260 | 39 | #include "intel_ringbuffer.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
2017263e BG |
41 | #include "i915_drv.h" |
42 | ||
f13d3f73 | 43 | enum { |
69dc4987 | 44 | ACTIVE_LIST, |
f13d3f73 | 45 | INACTIVE_LIST, |
d21d5975 | 46 | PINNED_LIST, |
f13d3f73 | 47 | }; |
2017263e | 48 | |
70d39fe4 CW |
49 | static const char *yesno(int v) |
50 | { | |
51 | return v ? "yes" : "no"; | |
52 | } | |
53 | ||
497666d8 DL |
54 | /* As the drm_debugfs_init() routines are called before dev->dev_private is |
55 | * allocated we need to hook into the minor for release. */ | |
56 | static int | |
57 | drm_add_fake_info_node(struct drm_minor *minor, | |
58 | struct dentry *ent, | |
59 | const void *key) | |
60 | { | |
61 | struct drm_info_node *node; | |
62 | ||
63 | node = kmalloc(sizeof(*node), GFP_KERNEL); | |
64 | if (node == NULL) { | |
65 | debugfs_remove(ent); | |
66 | return -ENOMEM; | |
67 | } | |
68 | ||
69 | node->minor = minor; | |
70 | node->dent = ent; | |
71 | node->info_ent = (void *) key; | |
72 | ||
73 | mutex_lock(&minor->debugfs_lock); | |
74 | list_add(&node->list, &minor->debugfs_list); | |
75 | mutex_unlock(&minor->debugfs_lock); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
70d39fe4 CW |
80 | static int i915_capabilities(struct seq_file *m, void *data) |
81 | { | |
9f25d007 | 82 | struct drm_info_node *node = m->private; |
70d39fe4 CW |
83 | struct drm_device *dev = node->minor->dev; |
84 | const struct intel_device_info *info = INTEL_INFO(dev); | |
85 | ||
86 | seq_printf(m, "gen: %d\n", info->gen); | |
03d00ac5 | 87 | seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); |
79fc46df DL |
88 | #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) |
89 | #define SEP_SEMICOLON ; | |
90 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); | |
91 | #undef PRINT_FLAG | |
92 | #undef SEP_SEMICOLON | |
70d39fe4 CW |
93 | |
94 | return 0; | |
95 | } | |
2017263e | 96 | |
05394f39 | 97 | static const char *get_pin_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 98 | { |
baaa5cfb | 99 | if (obj->pin_display) |
a6172a80 CW |
100 | return "p"; |
101 | else | |
102 | return " "; | |
103 | } | |
104 | ||
05394f39 | 105 | static const char *get_tiling_flag(struct drm_i915_gem_object *obj) |
a6172a80 | 106 | { |
0206e353 AJ |
107 | switch (obj->tiling_mode) { |
108 | default: | |
109 | case I915_TILING_NONE: return " "; | |
110 | case I915_TILING_X: return "X"; | |
111 | case I915_TILING_Y: return "Y"; | |
112 | } | |
a6172a80 CW |
113 | } |
114 | ||
1d693bcc BW |
115 | static inline const char *get_global_flag(struct drm_i915_gem_object *obj) |
116 | { | |
aff43766 | 117 | return i915_gem_obj_to_ggtt(obj) ? "g" : " "; |
1d693bcc BW |
118 | } |
119 | ||
37811fcc CW |
120 | static void |
121 | describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) | |
122 | { | |
b4716185 CW |
123 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
124 | struct intel_engine_cs *ring; | |
1d693bcc | 125 | struct i915_vma *vma; |
d7f46fc4 | 126 | int pin_count = 0; |
b4716185 | 127 | int i; |
d7f46fc4 | 128 | |
b4716185 | 129 | seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ", |
37811fcc | 130 | &obj->base, |
481a3d43 | 131 | obj->active ? "*" : " ", |
37811fcc CW |
132 | get_pin_flag(obj), |
133 | get_tiling_flag(obj), | |
1d693bcc | 134 | get_global_flag(obj), |
a05a5862 | 135 | obj->base.size / 1024, |
37811fcc | 136 | obj->base.read_domains, |
b4716185 CW |
137 | obj->base.write_domain); |
138 | for_each_ring(ring, dev_priv, i) | |
139 | seq_printf(m, "%x ", | |
140 | i915_gem_request_get_seqno(obj->last_read_req[i])); | |
141 | seq_printf(m, "] %x %x%s%s%s", | |
97b2a6a1 JH |
142 | i915_gem_request_get_seqno(obj->last_write_req), |
143 | i915_gem_request_get_seqno(obj->last_fenced_req), | |
0a4cd7c8 | 144 | i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), |
37811fcc CW |
145 | obj->dirty ? " dirty" : "", |
146 | obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); | |
147 | if (obj->base.name) | |
148 | seq_printf(m, " (name: %d)", obj->base.name); | |
ba0635ff | 149 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
150 | if (vma->pin_count > 0) |
151 | pin_count++; | |
ba0635ff DC |
152 | } |
153 | seq_printf(m, " (pinned x %d)", pin_count); | |
cc98b413 CW |
154 | if (obj->pin_display) |
155 | seq_printf(m, " (display)"); | |
37811fcc CW |
156 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
157 | seq_printf(m, " (fence: %d)", obj->fence_reg); | |
1d693bcc | 158 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
8d2fdc3f TU |
159 | seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", |
160 | i915_is_ggtt(vma->vm) ? "g" : "pp", | |
161 | vma->node.start, vma->node.size); | |
162 | if (i915_is_ggtt(vma->vm)) | |
163 | seq_printf(m, ", type: %u)", vma->ggtt_view.type); | |
1d693bcc | 164 | else |
8d2fdc3f | 165 | seq_puts(m, ")"); |
1d693bcc | 166 | } |
c1ad11fc | 167 | if (obj->stolen) |
440fd528 | 168 | seq_printf(m, " (stolen: %08llx)", obj->stolen->start); |
30154650 | 169 | if (obj->pin_display || obj->fault_mappable) { |
6299f992 | 170 | char s[3], *t = s; |
30154650 | 171 | if (obj->pin_display) |
6299f992 CW |
172 | *t++ = 'p'; |
173 | if (obj->fault_mappable) | |
174 | *t++ = 'f'; | |
175 | *t = '\0'; | |
176 | seq_printf(m, " (%s mappable)", s); | |
177 | } | |
b4716185 | 178 | if (obj->last_write_req != NULL) |
41c52415 | 179 | seq_printf(m, " (%s)", |
b4716185 | 180 | i915_gem_request_get_ring(obj->last_write_req)->name); |
d5a81ef1 DV |
181 | if (obj->frontbuffer_bits) |
182 | seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); | |
37811fcc CW |
183 | } |
184 | ||
273497e5 | 185 | static void describe_ctx(struct seq_file *m, struct intel_context *ctx) |
3ccfd19d | 186 | { |
ea0c76f8 | 187 | seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); |
3ccfd19d BW |
188 | seq_putc(m, ctx->remap_slice ? 'R' : 'r'); |
189 | seq_putc(m, ' '); | |
190 | } | |
191 | ||
433e12f7 | 192 | static int i915_gem_object_list_info(struct seq_file *m, void *data) |
2017263e | 193 | { |
9f25d007 | 194 | struct drm_info_node *node = m->private; |
433e12f7 BG |
195 | uintptr_t list = (uintptr_t) node->info_ent->data; |
196 | struct list_head *head; | |
2017263e | 197 | struct drm_device *dev = node->minor->dev; |
5cef07e1 BW |
198 | struct drm_i915_private *dev_priv = dev->dev_private; |
199 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
ca191b13 | 200 | struct i915_vma *vma; |
8f2480fb CW |
201 | size_t total_obj_size, total_gtt_size; |
202 | int count, ret; | |
de227ef0 CW |
203 | |
204 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
205 | if (ret) | |
206 | return ret; | |
2017263e | 207 | |
ca191b13 | 208 | /* FIXME: the user of this interface might want more than just GGTT */ |
433e12f7 BG |
209 | switch (list) { |
210 | case ACTIVE_LIST: | |
267f0c90 | 211 | seq_puts(m, "Active:\n"); |
5cef07e1 | 212 | head = &vm->active_list; |
433e12f7 BG |
213 | break; |
214 | case INACTIVE_LIST: | |
267f0c90 | 215 | seq_puts(m, "Inactive:\n"); |
5cef07e1 | 216 | head = &vm->inactive_list; |
433e12f7 | 217 | break; |
433e12f7 | 218 | default: |
de227ef0 CW |
219 | mutex_unlock(&dev->struct_mutex); |
220 | return -EINVAL; | |
2017263e | 221 | } |
2017263e | 222 | |
8f2480fb | 223 | total_obj_size = total_gtt_size = count = 0; |
ca191b13 BW |
224 | list_for_each_entry(vma, head, mm_list) { |
225 | seq_printf(m, " "); | |
226 | describe_obj(m, vma->obj); | |
227 | seq_printf(m, "\n"); | |
228 | total_obj_size += vma->obj->base.size; | |
229 | total_gtt_size += vma->node.size; | |
8f2480fb | 230 | count++; |
2017263e | 231 | } |
de227ef0 | 232 | mutex_unlock(&dev->struct_mutex); |
5e118f41 | 233 | |
8f2480fb CW |
234 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", |
235 | count, total_obj_size, total_gtt_size); | |
2017263e BG |
236 | return 0; |
237 | } | |
238 | ||
6d2b8885 CW |
239 | static int obj_rank_by_stolen(void *priv, |
240 | struct list_head *A, struct list_head *B) | |
241 | { | |
242 | struct drm_i915_gem_object *a = | |
b25cb2f8 | 243 | container_of(A, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 | 244 | struct drm_i915_gem_object *b = |
b25cb2f8 | 245 | container_of(B, struct drm_i915_gem_object, obj_exec_link); |
6d2b8885 CW |
246 | |
247 | return a->stolen->start - b->stolen->start; | |
248 | } | |
249 | ||
250 | static int i915_gem_stolen_list_info(struct seq_file *m, void *data) | |
251 | { | |
9f25d007 | 252 | struct drm_info_node *node = m->private; |
6d2b8885 CW |
253 | struct drm_device *dev = node->minor->dev; |
254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
255 | struct drm_i915_gem_object *obj; | |
256 | size_t total_obj_size, total_gtt_size; | |
257 | LIST_HEAD(stolen); | |
258 | int count, ret; | |
259 | ||
260 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
261 | if (ret) | |
262 | return ret; | |
263 | ||
264 | total_obj_size = total_gtt_size = count = 0; | |
265 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
266 | if (obj->stolen == NULL) | |
267 | continue; | |
268 | ||
b25cb2f8 | 269 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
270 | |
271 | total_obj_size += obj->base.size; | |
272 | total_gtt_size += i915_gem_obj_ggtt_size(obj); | |
273 | count++; | |
274 | } | |
275 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
276 | if (obj->stolen == NULL) | |
277 | continue; | |
278 | ||
b25cb2f8 | 279 | list_add(&obj->obj_exec_link, &stolen); |
6d2b8885 CW |
280 | |
281 | total_obj_size += obj->base.size; | |
282 | count++; | |
283 | } | |
284 | list_sort(NULL, &stolen, obj_rank_by_stolen); | |
285 | seq_puts(m, "Stolen:\n"); | |
286 | while (!list_empty(&stolen)) { | |
b25cb2f8 | 287 | obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); |
6d2b8885 CW |
288 | seq_puts(m, " "); |
289 | describe_obj(m, obj); | |
290 | seq_putc(m, '\n'); | |
b25cb2f8 | 291 | list_del_init(&obj->obj_exec_link); |
6d2b8885 CW |
292 | } |
293 | mutex_unlock(&dev->struct_mutex); | |
294 | ||
295 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
296 | count, total_obj_size, total_gtt_size); | |
297 | return 0; | |
298 | } | |
299 | ||
6299f992 CW |
300 | #define count_objects(list, member) do { \ |
301 | list_for_each_entry(obj, list, member) { \ | |
f343c5f6 | 302 | size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
303 | ++count; \ |
304 | if (obj->map_and_fenceable) { \ | |
f343c5f6 | 305 | mappable_size += i915_gem_obj_ggtt_size(obj); \ |
6299f992 CW |
306 | ++mappable_count; \ |
307 | } \ | |
308 | } \ | |
0206e353 | 309 | } while (0) |
6299f992 | 310 | |
2db8e9d6 | 311 | struct file_stats { |
6313c204 | 312 | struct drm_i915_file_private *file_priv; |
2db8e9d6 | 313 | int count; |
c67a17e9 CW |
314 | size_t total, unbound; |
315 | size_t global, shared; | |
316 | size_t active, inactive; | |
2db8e9d6 CW |
317 | }; |
318 | ||
319 | static int per_file_stats(int id, void *ptr, void *data) | |
320 | { | |
321 | struct drm_i915_gem_object *obj = ptr; | |
322 | struct file_stats *stats = data; | |
6313c204 | 323 | struct i915_vma *vma; |
2db8e9d6 CW |
324 | |
325 | stats->count++; | |
326 | stats->total += obj->base.size; | |
327 | ||
c67a17e9 CW |
328 | if (obj->base.name || obj->base.dma_buf) |
329 | stats->shared += obj->base.size; | |
330 | ||
6313c204 CW |
331 | if (USES_FULL_PPGTT(obj->base.dev)) { |
332 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
333 | struct i915_hw_ppgtt *ppgtt; | |
334 | ||
335 | if (!drm_mm_node_allocated(&vma->node)) | |
336 | continue; | |
337 | ||
338 | if (i915_is_ggtt(vma->vm)) { | |
339 | stats->global += obj->base.size; | |
340 | continue; | |
341 | } | |
342 | ||
343 | ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); | |
4d884705 | 344 | if (ppgtt->file_priv != stats->file_priv) |
6313c204 CW |
345 | continue; |
346 | ||
41c52415 | 347 | if (obj->active) /* XXX per-vma statistic */ |
6313c204 CW |
348 | stats->active += obj->base.size; |
349 | else | |
350 | stats->inactive += obj->base.size; | |
351 | ||
352 | return 0; | |
353 | } | |
2db8e9d6 | 354 | } else { |
6313c204 CW |
355 | if (i915_gem_obj_ggtt_bound(obj)) { |
356 | stats->global += obj->base.size; | |
41c52415 | 357 | if (obj->active) |
6313c204 CW |
358 | stats->active += obj->base.size; |
359 | else | |
360 | stats->inactive += obj->base.size; | |
361 | return 0; | |
362 | } | |
2db8e9d6 CW |
363 | } |
364 | ||
6313c204 CW |
365 | if (!list_empty(&obj->global_list)) |
366 | stats->unbound += obj->base.size; | |
367 | ||
2db8e9d6 CW |
368 | return 0; |
369 | } | |
370 | ||
b0da1b79 CW |
371 | #define print_file_stats(m, name, stats) do { \ |
372 | if (stats.count) \ | |
373 | seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \ | |
374 | name, \ | |
375 | stats.count, \ | |
376 | stats.total, \ | |
377 | stats.active, \ | |
378 | stats.inactive, \ | |
379 | stats.global, \ | |
380 | stats.shared, \ | |
381 | stats.unbound); \ | |
382 | } while (0) | |
493018dc BV |
383 | |
384 | static void print_batch_pool_stats(struct seq_file *m, | |
385 | struct drm_i915_private *dev_priv) | |
386 | { | |
387 | struct drm_i915_gem_object *obj; | |
388 | struct file_stats stats; | |
06fbca71 | 389 | struct intel_engine_cs *ring; |
8d9d5744 | 390 | int i, j; |
493018dc BV |
391 | |
392 | memset(&stats, 0, sizeof(stats)); | |
393 | ||
06fbca71 | 394 | for_each_ring(ring, dev_priv, i) { |
8d9d5744 CW |
395 | for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) { |
396 | list_for_each_entry(obj, | |
397 | &ring->batch_pool.cache_list[j], | |
398 | batch_pool_link) | |
399 | per_file_stats(0, obj, &stats); | |
400 | } | |
06fbca71 | 401 | } |
493018dc | 402 | |
b0da1b79 | 403 | print_file_stats(m, "[k]batch pool", stats); |
493018dc BV |
404 | } |
405 | ||
ca191b13 BW |
406 | #define count_vmas(list, member) do { \ |
407 | list_for_each_entry(vma, list, member) { \ | |
408 | size += i915_gem_obj_ggtt_size(vma->obj); \ | |
409 | ++count; \ | |
410 | if (vma->obj->map_and_fenceable) { \ | |
411 | mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ | |
412 | ++mappable_count; \ | |
413 | } \ | |
414 | } \ | |
415 | } while (0) | |
416 | ||
417 | static int i915_gem_object_info(struct seq_file *m, void* data) | |
73aa808f | 418 | { |
9f25d007 | 419 | struct drm_info_node *node = m->private; |
73aa808f CW |
420 | struct drm_device *dev = node->minor->dev; |
421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b7abb714 CW |
422 | u32 count, mappable_count, purgeable_count; |
423 | size_t size, mappable_size, purgeable_size; | |
6299f992 | 424 | struct drm_i915_gem_object *obj; |
5cef07e1 | 425 | struct i915_address_space *vm = &dev_priv->gtt.base; |
2db8e9d6 | 426 | struct drm_file *file; |
ca191b13 | 427 | struct i915_vma *vma; |
73aa808f CW |
428 | int ret; |
429 | ||
430 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
431 | if (ret) | |
432 | return ret; | |
433 | ||
6299f992 CW |
434 | seq_printf(m, "%u objects, %zu bytes\n", |
435 | dev_priv->mm.object_count, | |
436 | dev_priv->mm.object_memory); | |
437 | ||
438 | size = count = mappable_size = mappable_count = 0; | |
35c20a60 | 439 | count_objects(&dev_priv->mm.bound_list, global_list); |
6299f992 CW |
440 | seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", |
441 | count, mappable_count, size, mappable_size); | |
442 | ||
443 | size = count = mappable_size = mappable_count = 0; | |
ca191b13 | 444 | count_vmas(&vm->active_list, mm_list); |
6299f992 CW |
445 | seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", |
446 | count, mappable_count, size, mappable_size); | |
447 | ||
6299f992 | 448 | size = count = mappable_size = mappable_count = 0; |
ca191b13 | 449 | count_vmas(&vm->inactive_list, mm_list); |
6299f992 CW |
450 | seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", |
451 | count, mappable_count, size, mappable_size); | |
452 | ||
b7abb714 | 453 | size = count = purgeable_size = purgeable_count = 0; |
35c20a60 | 454 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { |
6c085a72 | 455 | size += obj->base.size, ++count; |
b7abb714 CW |
456 | if (obj->madv == I915_MADV_DONTNEED) |
457 | purgeable_size += obj->base.size, ++purgeable_count; | |
458 | } | |
6c085a72 CW |
459 | seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); |
460 | ||
6299f992 | 461 | size = count = mappable_size = mappable_count = 0; |
35c20a60 | 462 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6299f992 | 463 | if (obj->fault_mappable) { |
f343c5f6 | 464 | size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
465 | ++count; |
466 | } | |
30154650 | 467 | if (obj->pin_display) { |
f343c5f6 | 468 | mappable_size += i915_gem_obj_ggtt_size(obj); |
6299f992 CW |
469 | ++mappable_count; |
470 | } | |
b7abb714 CW |
471 | if (obj->madv == I915_MADV_DONTNEED) { |
472 | purgeable_size += obj->base.size; | |
473 | ++purgeable_count; | |
474 | } | |
6299f992 | 475 | } |
b7abb714 CW |
476 | seq_printf(m, "%u purgeable objects, %zu bytes\n", |
477 | purgeable_count, purgeable_size); | |
6299f992 CW |
478 | seq_printf(m, "%u pinned mappable objects, %zu bytes\n", |
479 | mappable_count, mappable_size); | |
480 | seq_printf(m, "%u fault mappable objects, %zu bytes\n", | |
481 | count, size); | |
482 | ||
93d18799 | 483 | seq_printf(m, "%zu [%lu] gtt total\n", |
853ba5d2 BW |
484 | dev_priv->gtt.base.total, |
485 | dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); | |
73aa808f | 486 | |
493018dc BV |
487 | seq_putc(m, '\n'); |
488 | print_batch_pool_stats(m, dev_priv); | |
2db8e9d6 CW |
489 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
490 | struct file_stats stats; | |
3ec2f427 | 491 | struct task_struct *task; |
2db8e9d6 CW |
492 | |
493 | memset(&stats, 0, sizeof(stats)); | |
6313c204 | 494 | stats.file_priv = file->driver_priv; |
5b5ffff0 | 495 | spin_lock(&file->table_lock); |
2db8e9d6 | 496 | idr_for_each(&file->object_idr, per_file_stats, &stats); |
5b5ffff0 | 497 | spin_unlock(&file->table_lock); |
3ec2f427 TH |
498 | /* |
499 | * Although we have a valid reference on file->pid, that does | |
500 | * not guarantee that the task_struct who called get_pid() is | |
501 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
502 | * Therefore, we need to protect this ->comm access using RCU. | |
503 | */ | |
504 | rcu_read_lock(); | |
505 | task = pid_task(file->pid, PIDTYPE_PID); | |
493018dc | 506 | print_file_stats(m, task ? task->comm : "<unknown>", stats); |
3ec2f427 | 507 | rcu_read_unlock(); |
2db8e9d6 CW |
508 | } |
509 | ||
73aa808f CW |
510 | mutex_unlock(&dev->struct_mutex); |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
aee56cff | 515 | static int i915_gem_gtt_info(struct seq_file *m, void *data) |
08c18323 | 516 | { |
9f25d007 | 517 | struct drm_info_node *node = m->private; |
08c18323 | 518 | struct drm_device *dev = node->minor->dev; |
1b50247a | 519 | uintptr_t list = (uintptr_t) node->info_ent->data; |
08c18323 CW |
520 | struct drm_i915_private *dev_priv = dev->dev_private; |
521 | struct drm_i915_gem_object *obj; | |
522 | size_t total_obj_size, total_gtt_size; | |
523 | int count, ret; | |
524 | ||
525 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
526 | if (ret) | |
527 | return ret; | |
528 | ||
529 | total_obj_size = total_gtt_size = count = 0; | |
35c20a60 | 530 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
d7f46fc4 | 531 | if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) |
1b50247a CW |
532 | continue; |
533 | ||
267f0c90 | 534 | seq_puts(m, " "); |
08c18323 | 535 | describe_obj(m, obj); |
267f0c90 | 536 | seq_putc(m, '\n'); |
08c18323 | 537 | total_obj_size += obj->base.size; |
f343c5f6 | 538 | total_gtt_size += i915_gem_obj_ggtt_size(obj); |
08c18323 CW |
539 | count++; |
540 | } | |
541 | ||
542 | mutex_unlock(&dev->struct_mutex); | |
543 | ||
544 | seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", | |
545 | count, total_obj_size, total_gtt_size); | |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
4e5359cd SF |
550 | static int i915_gem_pageflip_info(struct seq_file *m, void *data) |
551 | { | |
9f25d007 | 552 | struct drm_info_node *node = m->private; |
4e5359cd | 553 | struct drm_device *dev = node->minor->dev; |
d6bbafa1 | 554 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e5359cd | 555 | struct intel_crtc *crtc; |
8a270ebf DV |
556 | int ret; |
557 | ||
558 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
559 | if (ret) | |
560 | return ret; | |
4e5359cd | 561 | |
d3fcc808 | 562 | for_each_intel_crtc(dev, crtc) { |
9db4a9c7 JB |
563 | const char pipe = pipe_name(crtc->pipe); |
564 | const char plane = plane_name(crtc->plane); | |
4e5359cd SF |
565 | struct intel_unpin_work *work; |
566 | ||
5e2d7afc | 567 | spin_lock_irq(&dev->event_lock); |
4e5359cd SF |
568 | work = crtc->unpin_work; |
569 | if (work == NULL) { | |
9db4a9c7 | 570 | seq_printf(m, "No flip due on pipe %c (plane %c)\n", |
4e5359cd SF |
571 | pipe, plane); |
572 | } else { | |
d6bbafa1 CW |
573 | u32 addr; |
574 | ||
e7d841ca | 575 | if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { |
9db4a9c7 | 576 | seq_printf(m, "Flip queued on pipe %c (plane %c)\n", |
4e5359cd SF |
577 | pipe, plane); |
578 | } else { | |
9db4a9c7 | 579 | seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", |
4e5359cd SF |
580 | pipe, plane); |
581 | } | |
3a8a946e DV |
582 | if (work->flip_queued_req) { |
583 | struct intel_engine_cs *ring = | |
584 | i915_gem_request_get_ring(work->flip_queued_req); | |
585 | ||
20e28fba | 586 | seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", |
3a8a946e | 587 | ring->name, |
f06cc1b9 | 588 | i915_gem_request_get_seqno(work->flip_queued_req), |
d6bbafa1 | 589 | dev_priv->next_seqno, |
3a8a946e | 590 | ring->get_seqno(ring, true), |
1b5a433a | 591 | i915_gem_request_completed(work->flip_queued_req, true)); |
d6bbafa1 CW |
592 | } else |
593 | seq_printf(m, "Flip not associated with any ring\n"); | |
594 | seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", | |
595 | work->flip_queued_vblank, | |
596 | work->flip_ready_vblank, | |
1e3feefd | 597 | drm_crtc_vblank_count(&crtc->base)); |
4e5359cd | 598 | if (work->enable_stall_check) |
267f0c90 | 599 | seq_puts(m, "Stall check enabled, "); |
4e5359cd | 600 | else |
267f0c90 | 601 | seq_puts(m, "Stall check waiting for page flip ioctl, "); |
e7d841ca | 602 | seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); |
4e5359cd | 603 | |
d6bbafa1 CW |
604 | if (INTEL_INFO(dev)->gen >= 4) |
605 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); | |
606 | else | |
607 | addr = I915_READ(DSPADDR(crtc->plane)); | |
608 | seq_printf(m, "Current scanout address 0x%08x\n", addr); | |
609 | ||
4e5359cd | 610 | if (work->pending_flip_obj) { |
d6bbafa1 CW |
611 | seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); |
612 | seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); | |
4e5359cd SF |
613 | } |
614 | } | |
5e2d7afc | 615 | spin_unlock_irq(&dev->event_lock); |
4e5359cd SF |
616 | } |
617 | ||
8a270ebf DV |
618 | mutex_unlock(&dev->struct_mutex); |
619 | ||
4e5359cd SF |
620 | return 0; |
621 | } | |
622 | ||
493018dc BV |
623 | static int i915_gem_batch_pool_info(struct seq_file *m, void *data) |
624 | { | |
625 | struct drm_info_node *node = m->private; | |
626 | struct drm_device *dev = node->minor->dev; | |
627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
628 | struct drm_i915_gem_object *obj; | |
06fbca71 | 629 | struct intel_engine_cs *ring; |
8d9d5744 CW |
630 | int total = 0; |
631 | int ret, i, j; | |
493018dc BV |
632 | |
633 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
634 | if (ret) | |
635 | return ret; | |
636 | ||
06fbca71 | 637 | for_each_ring(ring, dev_priv, i) { |
8d9d5744 CW |
638 | for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) { |
639 | int count; | |
640 | ||
641 | count = 0; | |
642 | list_for_each_entry(obj, | |
643 | &ring->batch_pool.cache_list[j], | |
644 | batch_pool_link) | |
645 | count++; | |
646 | seq_printf(m, "%s cache[%d]: %d objects\n", | |
647 | ring->name, j, count); | |
648 | ||
649 | list_for_each_entry(obj, | |
650 | &ring->batch_pool.cache_list[j], | |
651 | batch_pool_link) { | |
652 | seq_puts(m, " "); | |
653 | describe_obj(m, obj); | |
654 | seq_putc(m, '\n'); | |
655 | } | |
656 | ||
657 | total += count; | |
06fbca71 | 658 | } |
493018dc BV |
659 | } |
660 | ||
8d9d5744 | 661 | seq_printf(m, "total: %d\n", total); |
493018dc BV |
662 | |
663 | mutex_unlock(&dev->struct_mutex); | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
2017263e BG |
668 | static int i915_gem_request_info(struct seq_file *m, void *data) |
669 | { | |
9f25d007 | 670 | struct drm_info_node *node = m->private; |
2017263e | 671 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 672 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 673 | struct intel_engine_cs *ring; |
eed29a5b | 674 | struct drm_i915_gem_request *req; |
2d1070b2 | 675 | int ret, any, i; |
de227ef0 CW |
676 | |
677 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
678 | if (ret) | |
679 | return ret; | |
2017263e | 680 | |
2d1070b2 | 681 | any = 0; |
a2c7f6fd | 682 | for_each_ring(ring, dev_priv, i) { |
2d1070b2 CW |
683 | int count; |
684 | ||
685 | count = 0; | |
eed29a5b | 686 | list_for_each_entry(req, &ring->request_list, list) |
2d1070b2 CW |
687 | count++; |
688 | if (count == 0) | |
a2c7f6fd CW |
689 | continue; |
690 | ||
2d1070b2 | 691 | seq_printf(m, "%s requests: %d\n", ring->name, count); |
eed29a5b | 692 | list_for_each_entry(req, &ring->request_list, list) { |
2d1070b2 CW |
693 | struct task_struct *task; |
694 | ||
695 | rcu_read_lock(); | |
696 | task = NULL; | |
eed29a5b DV |
697 | if (req->pid) |
698 | task = pid_task(req->pid, PIDTYPE_PID); | |
2d1070b2 | 699 | seq_printf(m, " %x @ %d: %s [%d]\n", |
eed29a5b DV |
700 | req->seqno, |
701 | (int) (jiffies - req->emitted_jiffies), | |
2d1070b2 CW |
702 | task ? task->comm : "<unknown>", |
703 | task ? task->pid : -1); | |
704 | rcu_read_unlock(); | |
c2c347a9 | 705 | } |
2d1070b2 CW |
706 | |
707 | any++; | |
2017263e | 708 | } |
de227ef0 CW |
709 | mutex_unlock(&dev->struct_mutex); |
710 | ||
2d1070b2 | 711 | if (any == 0) |
267f0c90 | 712 | seq_puts(m, "No requests\n"); |
c2c347a9 | 713 | |
2017263e BG |
714 | return 0; |
715 | } | |
716 | ||
b2223497 | 717 | static void i915_ring_seqno_info(struct seq_file *m, |
a4872ba6 | 718 | struct intel_engine_cs *ring) |
b2223497 CW |
719 | { |
720 | if (ring->get_seqno) { | |
20e28fba | 721 | seq_printf(m, "Current sequence (%s): %x\n", |
b2eadbc8 | 722 | ring->name, ring->get_seqno(ring, false)); |
b2223497 CW |
723 | } |
724 | } | |
725 | ||
2017263e BG |
726 | static int i915_gem_seqno_info(struct seq_file *m, void *data) |
727 | { | |
9f25d007 | 728 | struct drm_info_node *node = m->private; |
2017263e | 729 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 730 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 731 | struct intel_engine_cs *ring; |
1ec14ad3 | 732 | int ret, i; |
de227ef0 CW |
733 | |
734 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
735 | if (ret) | |
736 | return ret; | |
c8c8fb33 | 737 | intel_runtime_pm_get(dev_priv); |
2017263e | 738 | |
a2c7f6fd CW |
739 | for_each_ring(ring, dev_priv, i) |
740 | i915_ring_seqno_info(m, ring); | |
de227ef0 | 741 | |
c8c8fb33 | 742 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
743 | mutex_unlock(&dev->struct_mutex); |
744 | ||
2017263e BG |
745 | return 0; |
746 | } | |
747 | ||
748 | ||
749 | static int i915_interrupt_info(struct seq_file *m, void *data) | |
750 | { | |
9f25d007 | 751 | struct drm_info_node *node = m->private; |
2017263e | 752 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 753 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 754 | struct intel_engine_cs *ring; |
9db4a9c7 | 755 | int ret, i, pipe; |
de227ef0 CW |
756 | |
757 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
758 | if (ret) | |
759 | return ret; | |
c8c8fb33 | 760 | intel_runtime_pm_get(dev_priv); |
2017263e | 761 | |
74e1ca8c | 762 | if (IS_CHERRYVIEW(dev)) { |
74e1ca8c VS |
763 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
764 | I915_READ(GEN8_MASTER_IRQ)); | |
765 | ||
766 | seq_printf(m, "Display IER:\t%08x\n", | |
767 | I915_READ(VLV_IER)); | |
768 | seq_printf(m, "Display IIR:\t%08x\n", | |
769 | I915_READ(VLV_IIR)); | |
770 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
771 | I915_READ(VLV_IIR_RW)); | |
772 | seq_printf(m, "Display IMR:\t%08x\n", | |
773 | I915_READ(VLV_IMR)); | |
055e393f | 774 | for_each_pipe(dev_priv, pipe) |
74e1ca8c VS |
775 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
776 | pipe_name(pipe), | |
777 | I915_READ(PIPESTAT(pipe))); | |
778 | ||
779 | seq_printf(m, "Port hotplug:\t%08x\n", | |
780 | I915_READ(PORT_HOTPLUG_EN)); | |
781 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
782 | I915_READ(VLV_DPFLIPSTAT)); | |
783 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
784 | I915_READ(DPINVGTT)); | |
785 | ||
786 | for (i = 0; i < 4; i++) { | |
787 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
788 | i, I915_READ(GEN8_GT_IMR(i))); | |
789 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
790 | i, I915_READ(GEN8_GT_IIR(i))); | |
791 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
792 | i, I915_READ(GEN8_GT_IER(i))); | |
793 | } | |
794 | ||
795 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
796 | I915_READ(GEN8_PCU_IMR)); | |
797 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
798 | I915_READ(GEN8_PCU_IIR)); | |
799 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
800 | I915_READ(GEN8_PCU_IER)); | |
801 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
a123f157 BW |
802 | seq_printf(m, "Master Interrupt Control:\t%08x\n", |
803 | I915_READ(GEN8_MASTER_IRQ)); | |
804 | ||
805 | for (i = 0; i < 4; i++) { | |
806 | seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", | |
807 | i, I915_READ(GEN8_GT_IMR(i))); | |
808 | seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", | |
809 | i, I915_READ(GEN8_GT_IIR(i))); | |
810 | seq_printf(m, "GT Interrupt IER %d:\t%08x\n", | |
811 | i, I915_READ(GEN8_GT_IER(i))); | |
812 | } | |
813 | ||
055e393f | 814 | for_each_pipe(dev_priv, pipe) { |
f458ebbc | 815 | if (!intel_display_power_is_enabled(dev_priv, |
22c59960 PZ |
816 | POWER_DOMAIN_PIPE(pipe))) { |
817 | seq_printf(m, "Pipe %c power disabled\n", | |
818 | pipe_name(pipe)); | |
819 | continue; | |
820 | } | |
a123f157 | 821 | seq_printf(m, "Pipe %c IMR:\t%08x\n", |
07d27e20 DL |
822 | pipe_name(pipe), |
823 | I915_READ(GEN8_DE_PIPE_IMR(pipe))); | |
a123f157 | 824 | seq_printf(m, "Pipe %c IIR:\t%08x\n", |
07d27e20 DL |
825 | pipe_name(pipe), |
826 | I915_READ(GEN8_DE_PIPE_IIR(pipe))); | |
a123f157 | 827 | seq_printf(m, "Pipe %c IER:\t%08x\n", |
07d27e20 DL |
828 | pipe_name(pipe), |
829 | I915_READ(GEN8_DE_PIPE_IER(pipe))); | |
a123f157 BW |
830 | } |
831 | ||
832 | seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", | |
833 | I915_READ(GEN8_DE_PORT_IMR)); | |
834 | seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", | |
835 | I915_READ(GEN8_DE_PORT_IIR)); | |
836 | seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", | |
837 | I915_READ(GEN8_DE_PORT_IER)); | |
838 | ||
839 | seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", | |
840 | I915_READ(GEN8_DE_MISC_IMR)); | |
841 | seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", | |
842 | I915_READ(GEN8_DE_MISC_IIR)); | |
843 | seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", | |
844 | I915_READ(GEN8_DE_MISC_IER)); | |
845 | ||
846 | seq_printf(m, "PCU interrupt mask:\t%08x\n", | |
847 | I915_READ(GEN8_PCU_IMR)); | |
848 | seq_printf(m, "PCU interrupt identity:\t%08x\n", | |
849 | I915_READ(GEN8_PCU_IIR)); | |
850 | seq_printf(m, "PCU interrupt enable:\t%08x\n", | |
851 | I915_READ(GEN8_PCU_IER)); | |
852 | } else if (IS_VALLEYVIEW(dev)) { | |
7e231dbe JB |
853 | seq_printf(m, "Display IER:\t%08x\n", |
854 | I915_READ(VLV_IER)); | |
855 | seq_printf(m, "Display IIR:\t%08x\n", | |
856 | I915_READ(VLV_IIR)); | |
857 | seq_printf(m, "Display IIR_RW:\t%08x\n", | |
858 | I915_READ(VLV_IIR_RW)); | |
859 | seq_printf(m, "Display IMR:\t%08x\n", | |
860 | I915_READ(VLV_IMR)); | |
055e393f | 861 | for_each_pipe(dev_priv, pipe) |
7e231dbe JB |
862 | seq_printf(m, "Pipe %c stat:\t%08x\n", |
863 | pipe_name(pipe), | |
864 | I915_READ(PIPESTAT(pipe))); | |
865 | ||
866 | seq_printf(m, "Master IER:\t%08x\n", | |
867 | I915_READ(VLV_MASTER_IER)); | |
868 | ||
869 | seq_printf(m, "Render IER:\t%08x\n", | |
870 | I915_READ(GTIER)); | |
871 | seq_printf(m, "Render IIR:\t%08x\n", | |
872 | I915_READ(GTIIR)); | |
873 | seq_printf(m, "Render IMR:\t%08x\n", | |
874 | I915_READ(GTIMR)); | |
875 | ||
876 | seq_printf(m, "PM IER:\t\t%08x\n", | |
877 | I915_READ(GEN6_PMIER)); | |
878 | seq_printf(m, "PM IIR:\t\t%08x\n", | |
879 | I915_READ(GEN6_PMIIR)); | |
880 | seq_printf(m, "PM IMR:\t\t%08x\n", | |
881 | I915_READ(GEN6_PMIMR)); | |
882 | ||
883 | seq_printf(m, "Port hotplug:\t%08x\n", | |
884 | I915_READ(PORT_HOTPLUG_EN)); | |
885 | seq_printf(m, "DPFLIPSTAT:\t%08x\n", | |
886 | I915_READ(VLV_DPFLIPSTAT)); | |
887 | seq_printf(m, "DPINVGTT:\t%08x\n", | |
888 | I915_READ(DPINVGTT)); | |
889 | ||
890 | } else if (!HAS_PCH_SPLIT(dev)) { | |
5f6a1695 ZW |
891 | seq_printf(m, "Interrupt enable: %08x\n", |
892 | I915_READ(IER)); | |
893 | seq_printf(m, "Interrupt identity: %08x\n", | |
894 | I915_READ(IIR)); | |
895 | seq_printf(m, "Interrupt mask: %08x\n", | |
896 | I915_READ(IMR)); | |
055e393f | 897 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
898 | seq_printf(m, "Pipe %c stat: %08x\n", |
899 | pipe_name(pipe), | |
900 | I915_READ(PIPESTAT(pipe))); | |
5f6a1695 ZW |
901 | } else { |
902 | seq_printf(m, "North Display Interrupt enable: %08x\n", | |
903 | I915_READ(DEIER)); | |
904 | seq_printf(m, "North Display Interrupt identity: %08x\n", | |
905 | I915_READ(DEIIR)); | |
906 | seq_printf(m, "North Display Interrupt mask: %08x\n", | |
907 | I915_READ(DEIMR)); | |
908 | seq_printf(m, "South Display Interrupt enable: %08x\n", | |
909 | I915_READ(SDEIER)); | |
910 | seq_printf(m, "South Display Interrupt identity: %08x\n", | |
911 | I915_READ(SDEIIR)); | |
912 | seq_printf(m, "South Display Interrupt mask: %08x\n", | |
913 | I915_READ(SDEIMR)); | |
914 | seq_printf(m, "Graphics Interrupt enable: %08x\n", | |
915 | I915_READ(GTIER)); | |
916 | seq_printf(m, "Graphics Interrupt identity: %08x\n", | |
917 | I915_READ(GTIIR)); | |
918 | seq_printf(m, "Graphics Interrupt mask: %08x\n", | |
919 | I915_READ(GTIMR)); | |
920 | } | |
a2c7f6fd | 921 | for_each_ring(ring, dev_priv, i) { |
a123f157 | 922 | if (INTEL_INFO(dev)->gen >= 6) { |
a2c7f6fd CW |
923 | seq_printf(m, |
924 | "Graphics Interrupt mask (%s): %08x\n", | |
925 | ring->name, I915_READ_IMR(ring)); | |
9862e600 | 926 | } |
a2c7f6fd | 927 | i915_ring_seqno_info(m, ring); |
9862e600 | 928 | } |
c8c8fb33 | 929 | intel_runtime_pm_put(dev_priv); |
de227ef0 CW |
930 | mutex_unlock(&dev->struct_mutex); |
931 | ||
2017263e BG |
932 | return 0; |
933 | } | |
934 | ||
a6172a80 CW |
935 | static int i915_gem_fence_regs_info(struct seq_file *m, void *data) |
936 | { | |
9f25d007 | 937 | struct drm_info_node *node = m->private; |
a6172a80 | 938 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 939 | struct drm_i915_private *dev_priv = dev->dev_private; |
de227ef0 CW |
940 | int i, ret; |
941 | ||
942 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
943 | if (ret) | |
944 | return ret; | |
a6172a80 CW |
945 | |
946 | seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); | |
947 | seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); | |
948 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
05394f39 | 949 | struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; |
a6172a80 | 950 | |
6c085a72 CW |
951 | seq_printf(m, "Fence %d, pin count = %d, object = ", |
952 | i, dev_priv->fence_regs[i].pin_count); | |
c2c347a9 | 953 | if (obj == NULL) |
267f0c90 | 954 | seq_puts(m, "unused"); |
c2c347a9 | 955 | else |
05394f39 | 956 | describe_obj(m, obj); |
267f0c90 | 957 | seq_putc(m, '\n'); |
a6172a80 CW |
958 | } |
959 | ||
05394f39 | 960 | mutex_unlock(&dev->struct_mutex); |
a6172a80 CW |
961 | return 0; |
962 | } | |
963 | ||
2017263e BG |
964 | static int i915_hws_info(struct seq_file *m, void *data) |
965 | { | |
9f25d007 | 966 | struct drm_info_node *node = m->private; |
2017263e | 967 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 968 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 969 | struct intel_engine_cs *ring; |
1a240d4d | 970 | const u32 *hws; |
4066c0ae CW |
971 | int i; |
972 | ||
1ec14ad3 | 973 | ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; |
1a240d4d | 974 | hws = ring->status_page.page_addr; |
2017263e BG |
975 | if (hws == NULL) |
976 | return 0; | |
977 | ||
978 | for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { | |
979 | seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
980 | i * 4, | |
981 | hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); | |
982 | } | |
983 | return 0; | |
984 | } | |
985 | ||
d5442303 DV |
986 | static ssize_t |
987 | i915_error_state_write(struct file *filp, | |
988 | const char __user *ubuf, | |
989 | size_t cnt, | |
990 | loff_t *ppos) | |
991 | { | |
edc3d884 | 992 | struct i915_error_state_file_priv *error_priv = filp->private_data; |
d5442303 | 993 | struct drm_device *dev = error_priv->dev; |
22bcfc6a | 994 | int ret; |
d5442303 DV |
995 | |
996 | DRM_DEBUG_DRIVER("Resetting error state\n"); | |
997 | ||
22bcfc6a DV |
998 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
999 | if (ret) | |
1000 | return ret; | |
1001 | ||
d5442303 DV |
1002 | i915_destroy_error_state(dev); |
1003 | mutex_unlock(&dev->struct_mutex); | |
1004 | ||
1005 | return cnt; | |
1006 | } | |
1007 | ||
1008 | static int i915_error_state_open(struct inode *inode, struct file *file) | |
1009 | { | |
1010 | struct drm_device *dev = inode->i_private; | |
d5442303 | 1011 | struct i915_error_state_file_priv *error_priv; |
d5442303 DV |
1012 | |
1013 | error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); | |
1014 | if (!error_priv) | |
1015 | return -ENOMEM; | |
1016 | ||
1017 | error_priv->dev = dev; | |
1018 | ||
95d5bfb3 | 1019 | i915_error_state_get(dev, error_priv); |
d5442303 | 1020 | |
edc3d884 MK |
1021 | file->private_data = error_priv; |
1022 | ||
1023 | return 0; | |
d5442303 DV |
1024 | } |
1025 | ||
1026 | static int i915_error_state_release(struct inode *inode, struct file *file) | |
1027 | { | |
edc3d884 | 1028 | struct i915_error_state_file_priv *error_priv = file->private_data; |
d5442303 | 1029 | |
95d5bfb3 | 1030 | i915_error_state_put(error_priv); |
d5442303 DV |
1031 | kfree(error_priv); |
1032 | ||
edc3d884 MK |
1033 | return 0; |
1034 | } | |
1035 | ||
4dc955f7 MK |
1036 | static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, |
1037 | size_t count, loff_t *pos) | |
1038 | { | |
1039 | struct i915_error_state_file_priv *error_priv = file->private_data; | |
1040 | struct drm_i915_error_state_buf error_str; | |
1041 | loff_t tmp_pos = 0; | |
1042 | ssize_t ret_count = 0; | |
1043 | int ret; | |
1044 | ||
0a4cd7c8 | 1045 | ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); |
4dc955f7 MK |
1046 | if (ret) |
1047 | return ret; | |
edc3d884 | 1048 | |
fc16b48b | 1049 | ret = i915_error_state_to_str(&error_str, error_priv); |
edc3d884 MK |
1050 | if (ret) |
1051 | goto out; | |
1052 | ||
edc3d884 MK |
1053 | ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, |
1054 | error_str.buf, | |
1055 | error_str.bytes); | |
1056 | ||
1057 | if (ret_count < 0) | |
1058 | ret = ret_count; | |
1059 | else | |
1060 | *pos = error_str.start + ret_count; | |
1061 | out: | |
4dc955f7 | 1062 | i915_error_state_buf_release(&error_str); |
edc3d884 | 1063 | return ret ?: ret_count; |
d5442303 DV |
1064 | } |
1065 | ||
1066 | static const struct file_operations i915_error_state_fops = { | |
1067 | .owner = THIS_MODULE, | |
1068 | .open = i915_error_state_open, | |
edc3d884 | 1069 | .read = i915_error_state_read, |
d5442303 DV |
1070 | .write = i915_error_state_write, |
1071 | .llseek = default_llseek, | |
1072 | .release = i915_error_state_release, | |
1073 | }; | |
1074 | ||
647416f9 KC |
1075 | static int |
1076 | i915_next_seqno_get(void *data, u64 *val) | |
40633219 | 1077 | { |
647416f9 | 1078 | struct drm_device *dev = data; |
e277a1f8 | 1079 | struct drm_i915_private *dev_priv = dev->dev_private; |
40633219 MK |
1080 | int ret; |
1081 | ||
1082 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1083 | if (ret) | |
1084 | return ret; | |
1085 | ||
647416f9 | 1086 | *val = dev_priv->next_seqno; |
40633219 MK |
1087 | mutex_unlock(&dev->struct_mutex); |
1088 | ||
647416f9 | 1089 | return 0; |
40633219 MK |
1090 | } |
1091 | ||
647416f9 KC |
1092 | static int |
1093 | i915_next_seqno_set(void *data, u64 val) | |
1094 | { | |
1095 | struct drm_device *dev = data; | |
40633219 MK |
1096 | int ret; |
1097 | ||
40633219 MK |
1098 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1099 | if (ret) | |
1100 | return ret; | |
1101 | ||
e94fbaa8 | 1102 | ret = i915_gem_set_seqno(dev, val); |
40633219 MK |
1103 | mutex_unlock(&dev->struct_mutex); |
1104 | ||
647416f9 | 1105 | return ret; |
40633219 MK |
1106 | } |
1107 | ||
647416f9 KC |
1108 | DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, |
1109 | i915_next_seqno_get, i915_next_seqno_set, | |
3a3b4f98 | 1110 | "0x%llx\n"); |
40633219 | 1111 | |
adb4bd12 | 1112 | static int i915_frequency_info(struct seq_file *m, void *unused) |
f97108d1 | 1113 | { |
9f25d007 | 1114 | struct drm_info_node *node = m->private; |
f97108d1 | 1115 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1116 | struct drm_i915_private *dev_priv = dev->dev_private; |
c8c8fb33 PZ |
1117 | int ret = 0; |
1118 | ||
1119 | intel_runtime_pm_get(dev_priv); | |
3b8d8d91 | 1120 | |
5c9669ce TR |
1121 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1122 | ||
3b8d8d91 JB |
1123 | if (IS_GEN5(dev)) { |
1124 | u16 rgvswctl = I915_READ16(MEMSWCTL); | |
1125 | u16 rgvstat = I915_READ16(MEMSTAT_ILK); | |
1126 | ||
1127 | seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); | |
1128 | seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); | |
1129 | seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> | |
1130 | MEMSTAT_VID_SHIFT); | |
1131 | seq_printf(m, "Current P-state: %d\n", | |
1132 | (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); | |
daa3afb2 | 1133 | } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) || |
60260a5b | 1134 | IS_BROADWELL(dev) || IS_GEN9(dev)) { |
3b8d8d91 JB |
1135 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
1136 | u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); | |
1137 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
0d8f9491 | 1138 | u32 rpmodectl, rpinclimit, rpdeclimit; |
8e8c06cd | 1139 | u32 rpstat, cagf, reqf; |
ccab5c82 JB |
1140 | u32 rpupei, rpcurup, rpprevup; |
1141 | u32 rpdownei, rpcurdown, rpprevdown; | |
9dd3c605 | 1142 | u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; |
3b8d8d91 JB |
1143 | int max_freq; |
1144 | ||
1145 | /* RPSTAT1 is in the GT power well */ | |
d1ebd816 BW |
1146 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1147 | if (ret) | |
c8c8fb33 | 1148 | goto out; |
d1ebd816 | 1149 | |
59bad947 | 1150 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
3b8d8d91 | 1151 | |
8e8c06cd | 1152 | reqf = I915_READ(GEN6_RPNSWREQ); |
60260a5b AG |
1153 | if (IS_GEN9(dev)) |
1154 | reqf >>= 23; | |
1155 | else { | |
1156 | reqf &= ~GEN6_TURBO_DISABLE; | |
1157 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
1158 | reqf >>= 24; | |
1159 | else | |
1160 | reqf >>= 25; | |
1161 | } | |
7c59a9c1 | 1162 | reqf = intel_gpu_freq(dev_priv, reqf); |
8e8c06cd | 1163 | |
0d8f9491 CW |
1164 | rpmodectl = I915_READ(GEN6_RP_CONTROL); |
1165 | rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); | |
1166 | rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); | |
1167 | ||
ccab5c82 JB |
1168 | rpstat = I915_READ(GEN6_RPSTAT1); |
1169 | rpupei = I915_READ(GEN6_RP_CUR_UP_EI); | |
1170 | rpcurup = I915_READ(GEN6_RP_CUR_UP); | |
1171 | rpprevup = I915_READ(GEN6_RP_PREV_UP); | |
1172 | rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); | |
1173 | rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); | |
1174 | rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); | |
60260a5b AG |
1175 | if (IS_GEN9(dev)) |
1176 | cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; | |
1177 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
f82855d3 BW |
1178 | cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; |
1179 | else | |
1180 | cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; | |
7c59a9c1 | 1181 | cagf = intel_gpu_freq(dev_priv, cagf); |
ccab5c82 | 1182 | |
59bad947 | 1183 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d1ebd816 BW |
1184 | mutex_unlock(&dev->struct_mutex); |
1185 | ||
9dd3c605 PZ |
1186 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1187 | pm_ier = I915_READ(GEN6_PMIER); | |
1188 | pm_imr = I915_READ(GEN6_PMIMR); | |
1189 | pm_isr = I915_READ(GEN6_PMISR); | |
1190 | pm_iir = I915_READ(GEN6_PMIIR); | |
1191 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1192 | } else { | |
1193 | pm_ier = I915_READ(GEN8_GT_IER(2)); | |
1194 | pm_imr = I915_READ(GEN8_GT_IMR(2)); | |
1195 | pm_isr = I915_READ(GEN8_GT_ISR(2)); | |
1196 | pm_iir = I915_READ(GEN8_GT_IIR(2)); | |
1197 | pm_mask = I915_READ(GEN6_PMINTRMSK); | |
1198 | } | |
0d8f9491 | 1199 | seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", |
9dd3c605 | 1200 | pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); |
3b8d8d91 | 1201 | seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); |
3b8d8d91 | 1202 | seq_printf(m, "Render p-state ratio: %d\n", |
60260a5b | 1203 | (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); |
3b8d8d91 JB |
1204 | seq_printf(m, "Render p-state VID: %d\n", |
1205 | gt_perf_status & 0xff); | |
1206 | seq_printf(m, "Render p-state limit: %d\n", | |
1207 | rp_state_limits & 0xff); | |
0d8f9491 CW |
1208 | seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); |
1209 | seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); | |
1210 | seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); | |
1211 | seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); | |
8e8c06cd | 1212 | seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); |
f82855d3 | 1213 | seq_printf(m, "CAGF: %dMHz\n", cagf); |
ccab5c82 JB |
1214 | seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & |
1215 | GEN6_CURICONT_MASK); | |
1216 | seq_printf(m, "RP CUR UP: %dus\n", rpcurup & | |
1217 | GEN6_CURBSYTAVG_MASK); | |
1218 | seq_printf(m, "RP PREV UP: %dus\n", rpprevup & | |
1219 | GEN6_CURBSYTAVG_MASK); | |
d86ed34a CW |
1220 | seq_printf(m, "Up threshold: %d%%\n", |
1221 | dev_priv->rps.up_threshold); | |
1222 | ||
ccab5c82 JB |
1223 | seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & |
1224 | GEN6_CURIAVG_MASK); | |
1225 | seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & | |
1226 | GEN6_CURBSYTAVG_MASK); | |
1227 | seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & | |
1228 | GEN6_CURBSYTAVG_MASK); | |
d86ed34a CW |
1229 | seq_printf(m, "Down threshold: %d%%\n", |
1230 | dev_priv->rps.down_threshold); | |
3b8d8d91 JB |
1231 | |
1232 | max_freq = (rp_state_cap & 0xff0000) >> 16; | |
60260a5b | 1233 | max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1234 | seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", |
7c59a9c1 | 1235 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1236 | |
1237 | max_freq = (rp_state_cap & 0xff00) >> 8; | |
60260a5b | 1238 | max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1239 | seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", |
7c59a9c1 | 1240 | intel_gpu_freq(dev_priv, max_freq)); |
3b8d8d91 JB |
1241 | |
1242 | max_freq = rp_state_cap & 0xff; | |
60260a5b | 1243 | max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); |
3b8d8d91 | 1244 | seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", |
7c59a9c1 | 1245 | intel_gpu_freq(dev_priv, max_freq)); |
31c77388 | 1246 | seq_printf(m, "Max overclocked frequency: %dMHz\n", |
7c59a9c1 | 1247 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
aed242ff | 1248 | |
d86ed34a CW |
1249 | seq_printf(m, "Current freq: %d MHz\n", |
1250 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1251 | seq_printf(m, "Actual freq: %d MHz\n", cagf); | |
aed242ff CW |
1252 | seq_printf(m, "Idle freq: %d MHz\n", |
1253 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
d86ed34a CW |
1254 | seq_printf(m, "Min freq: %d MHz\n", |
1255 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); | |
1256 | seq_printf(m, "Max freq: %d MHz\n", | |
1257 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
1258 | seq_printf(m, | |
1259 | "efficient (RPe) frequency: %d MHz\n", | |
1260 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
0a073b84 | 1261 | } else if (IS_VALLEYVIEW(dev)) { |
03af2045 | 1262 | u32 freq_sts; |
0a073b84 | 1263 | |
259bd5d4 | 1264 | mutex_lock(&dev_priv->rps.hw_lock); |
64936258 | 1265 | freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
1266 | seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); |
1267 | seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); | |
1268 | ||
d86ed34a CW |
1269 | seq_printf(m, "actual GPU freq: %d MHz\n", |
1270 | intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); | |
1271 | ||
1272 | seq_printf(m, "current GPU freq: %d MHz\n", | |
1273 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); | |
1274 | ||
0a073b84 | 1275 | seq_printf(m, "max GPU freq: %d MHz\n", |
7c59a9c1 | 1276 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); |
0a073b84 | 1277 | |
0a073b84 | 1278 | seq_printf(m, "min GPU freq: %d MHz\n", |
7c59a9c1 | 1279 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); |
03af2045 | 1280 | |
aed242ff CW |
1281 | seq_printf(m, "idle GPU freq: %d MHz\n", |
1282 | intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); | |
1283 | ||
7c59a9c1 VS |
1284 | seq_printf(m, |
1285 | "efficient (RPe) frequency: %d MHz\n", | |
1286 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); | |
259bd5d4 | 1287 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 | 1288 | } else { |
267f0c90 | 1289 | seq_puts(m, "no P-state info available\n"); |
3b8d8d91 | 1290 | } |
f97108d1 | 1291 | |
c8c8fb33 PZ |
1292 | out: |
1293 | intel_runtime_pm_put(dev_priv); | |
1294 | return ret; | |
f97108d1 JB |
1295 | } |
1296 | ||
f654449a CW |
1297 | static int i915_hangcheck_info(struct seq_file *m, void *unused) |
1298 | { | |
1299 | struct drm_info_node *node = m->private; | |
ebbc7546 MK |
1300 | struct drm_device *dev = node->minor->dev; |
1301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f654449a | 1302 | struct intel_engine_cs *ring; |
ebbc7546 MK |
1303 | u64 acthd[I915_NUM_RINGS]; |
1304 | u32 seqno[I915_NUM_RINGS]; | |
f654449a CW |
1305 | int i; |
1306 | ||
1307 | if (!i915.enable_hangcheck) { | |
1308 | seq_printf(m, "Hangcheck disabled\n"); | |
1309 | return 0; | |
1310 | } | |
1311 | ||
ebbc7546 MK |
1312 | intel_runtime_pm_get(dev_priv); |
1313 | ||
1314 | for_each_ring(ring, dev_priv, i) { | |
1315 | seqno[i] = ring->get_seqno(ring, false); | |
1316 | acthd[i] = intel_ring_get_active_head(ring); | |
1317 | } | |
1318 | ||
1319 | intel_runtime_pm_put(dev_priv); | |
1320 | ||
f654449a CW |
1321 | if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { |
1322 | seq_printf(m, "Hangcheck active, fires in %dms\n", | |
1323 | jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - | |
1324 | jiffies)); | |
1325 | } else | |
1326 | seq_printf(m, "Hangcheck inactive\n"); | |
1327 | ||
1328 | for_each_ring(ring, dev_priv, i) { | |
1329 | seq_printf(m, "%s:\n", ring->name); | |
1330 | seq_printf(m, "\tseqno = %x [current %x]\n", | |
ebbc7546 | 1331 | ring->hangcheck.seqno, seqno[i]); |
f654449a CW |
1332 | seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", |
1333 | (long long)ring->hangcheck.acthd, | |
ebbc7546 | 1334 | (long long)acthd[i]); |
f654449a CW |
1335 | seq_printf(m, "\tmax ACTHD = 0x%08llx\n", |
1336 | (long long)ring->hangcheck.max_acthd); | |
ebbc7546 MK |
1337 | seq_printf(m, "\tscore = %d\n", ring->hangcheck.score); |
1338 | seq_printf(m, "\taction = %d\n", ring->hangcheck.action); | |
f654449a CW |
1339 | } |
1340 | ||
1341 | return 0; | |
1342 | } | |
1343 | ||
4d85529d | 1344 | static int ironlake_drpc_info(struct seq_file *m) |
f97108d1 | 1345 | { |
9f25d007 | 1346 | struct drm_info_node *node = m->private; |
f97108d1 | 1347 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1348 | struct drm_i915_private *dev_priv = dev->dev_private; |
616fdb5a BW |
1349 | u32 rgvmodectl, rstdbyctl; |
1350 | u16 crstandvid; | |
1351 | int ret; | |
1352 | ||
1353 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1354 | if (ret) | |
1355 | return ret; | |
c8c8fb33 | 1356 | intel_runtime_pm_get(dev_priv); |
616fdb5a BW |
1357 | |
1358 | rgvmodectl = I915_READ(MEMMODECTL); | |
1359 | rstdbyctl = I915_READ(RSTDBYCTL); | |
1360 | crstandvid = I915_READ16(CRSTANDVID); | |
1361 | ||
c8c8fb33 | 1362 | intel_runtime_pm_put(dev_priv); |
616fdb5a | 1363 | mutex_unlock(&dev->struct_mutex); |
f97108d1 JB |
1364 | |
1365 | seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? | |
1366 | "yes" : "no"); | |
1367 | seq_printf(m, "Boost freq: %d\n", | |
1368 | (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> | |
1369 | MEMMODE_BOOST_FREQ_SHIFT); | |
1370 | seq_printf(m, "HW control enabled: %s\n", | |
1371 | rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); | |
1372 | seq_printf(m, "SW control enabled: %s\n", | |
1373 | rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); | |
1374 | seq_printf(m, "Gated voltage change: %s\n", | |
1375 | rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); | |
1376 | seq_printf(m, "Starting frequency: P%d\n", | |
1377 | (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); | |
7648fa99 | 1378 | seq_printf(m, "Max P-state: P%d\n", |
f97108d1 | 1379 | (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); |
7648fa99 JB |
1380 | seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); |
1381 | seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); | |
1382 | seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); | |
1383 | seq_printf(m, "Render standby enabled: %s\n", | |
1384 | (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); | |
267f0c90 | 1385 | seq_puts(m, "Current RS state: "); |
88271da3 JB |
1386 | switch (rstdbyctl & RSX_STATUS_MASK) { |
1387 | case RSX_STATUS_ON: | |
267f0c90 | 1388 | seq_puts(m, "on\n"); |
88271da3 JB |
1389 | break; |
1390 | case RSX_STATUS_RC1: | |
267f0c90 | 1391 | seq_puts(m, "RC1\n"); |
88271da3 JB |
1392 | break; |
1393 | case RSX_STATUS_RC1E: | |
267f0c90 | 1394 | seq_puts(m, "RC1E\n"); |
88271da3 JB |
1395 | break; |
1396 | case RSX_STATUS_RS1: | |
267f0c90 | 1397 | seq_puts(m, "RS1\n"); |
88271da3 JB |
1398 | break; |
1399 | case RSX_STATUS_RS2: | |
267f0c90 | 1400 | seq_puts(m, "RS2 (RC6)\n"); |
88271da3 JB |
1401 | break; |
1402 | case RSX_STATUS_RS3: | |
267f0c90 | 1403 | seq_puts(m, "RC3 (RC6+)\n"); |
88271da3 JB |
1404 | break; |
1405 | default: | |
267f0c90 | 1406 | seq_puts(m, "unknown\n"); |
88271da3 JB |
1407 | break; |
1408 | } | |
f97108d1 JB |
1409 | |
1410 | return 0; | |
1411 | } | |
1412 | ||
f65367b5 | 1413 | static int i915_forcewake_domains(struct seq_file *m, void *data) |
669ab5aa | 1414 | { |
b2cff0db CW |
1415 | struct drm_info_node *node = m->private; |
1416 | struct drm_device *dev = node->minor->dev; | |
1417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1418 | struct intel_uncore_forcewake_domain *fw_domain; | |
b2cff0db CW |
1419 | int i; |
1420 | ||
1421 | spin_lock_irq(&dev_priv->uncore.lock); | |
1422 | for_each_fw_domain(fw_domain, dev_priv, i) { | |
1423 | seq_printf(m, "%s.wake_count = %u\n", | |
05a2fb15 | 1424 | intel_uncore_forcewake_domain_to_str(i), |
b2cff0db CW |
1425 | fw_domain->wake_count); |
1426 | } | |
1427 | spin_unlock_irq(&dev_priv->uncore.lock); | |
669ab5aa | 1428 | |
b2cff0db CW |
1429 | return 0; |
1430 | } | |
1431 | ||
1432 | static int vlv_drpc_info(struct seq_file *m) | |
1433 | { | |
9f25d007 | 1434 | struct drm_info_node *node = m->private; |
669ab5aa D |
1435 | struct drm_device *dev = node->minor->dev; |
1436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6b312cd3 | 1437 | u32 rpmodectl1, rcctl1, pw_status; |
669ab5aa | 1438 | |
d46c0517 ID |
1439 | intel_runtime_pm_get(dev_priv); |
1440 | ||
6b312cd3 | 1441 | pw_status = I915_READ(VLV_GTLC_PW_STATUS); |
669ab5aa D |
1442 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); |
1443 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1444 | ||
d46c0517 ID |
1445 | intel_runtime_pm_put(dev_priv); |
1446 | ||
669ab5aa D |
1447 | seq_printf(m, "Video Turbo Mode: %s\n", |
1448 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1449 | seq_printf(m, "Turbo enabled: %s\n", | |
1450 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1451 | seq_printf(m, "HW control enabled: %s\n", | |
1452 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1453 | seq_printf(m, "SW control enabled: %s\n", | |
1454 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1455 | GEN6_RP_MEDIA_SW_MODE)); | |
1456 | seq_printf(m, "RC6 Enabled: %s\n", | |
1457 | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | | |
1458 | GEN6_RC_CTL_EI_MODE(1)))); | |
1459 | seq_printf(m, "Render Power Well: %s\n", | |
6b312cd3 | 1460 | (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1461 | seq_printf(m, "Media Power Well: %s\n", |
6b312cd3 | 1462 | (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); |
669ab5aa | 1463 | |
9cc19be5 ID |
1464 | seq_printf(m, "Render RC6 residency since boot: %u\n", |
1465 | I915_READ(VLV_GT_RENDER_RC6)); | |
1466 | seq_printf(m, "Media RC6 residency since boot: %u\n", | |
1467 | I915_READ(VLV_GT_MEDIA_RC6)); | |
1468 | ||
f65367b5 | 1469 | return i915_forcewake_domains(m, NULL); |
669ab5aa D |
1470 | } |
1471 | ||
4d85529d BW |
1472 | static int gen6_drpc_info(struct seq_file *m) |
1473 | { | |
9f25d007 | 1474 | struct drm_info_node *node = m->private; |
4d85529d BW |
1475 | struct drm_device *dev = node->minor->dev; |
1476 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ecd8faea | 1477 | u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; |
93b525dc | 1478 | unsigned forcewake_count; |
aee56cff | 1479 | int count = 0, ret; |
4d85529d BW |
1480 | |
1481 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1482 | if (ret) | |
1483 | return ret; | |
c8c8fb33 | 1484 | intel_runtime_pm_get(dev_priv); |
4d85529d | 1485 | |
907b28c5 | 1486 | spin_lock_irq(&dev_priv->uncore.lock); |
b2cff0db | 1487 | forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; |
907b28c5 | 1488 | spin_unlock_irq(&dev_priv->uncore.lock); |
93b525dc DV |
1489 | |
1490 | if (forcewake_count) { | |
267f0c90 DL |
1491 | seq_puts(m, "RC information inaccurate because somebody " |
1492 | "holds a forcewake reference \n"); | |
4d85529d BW |
1493 | } else { |
1494 | /* NB: we cannot use forcewake, else we read the wrong values */ | |
1495 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
1496 | udelay(10); | |
1497 | seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); | |
1498 | } | |
1499 | ||
1500 | gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); | |
ed71f1b4 | 1501 | trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); |
4d85529d BW |
1502 | |
1503 | rpmodectl1 = I915_READ(GEN6_RP_CONTROL); | |
1504 | rcctl1 = I915_READ(GEN6_RC_CONTROL); | |
1505 | mutex_unlock(&dev->struct_mutex); | |
44cbd338 BW |
1506 | mutex_lock(&dev_priv->rps.hw_lock); |
1507 | sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
1508 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4d85529d | 1509 | |
c8c8fb33 PZ |
1510 | intel_runtime_pm_put(dev_priv); |
1511 | ||
4d85529d BW |
1512 | seq_printf(m, "Video Turbo Mode: %s\n", |
1513 | yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); | |
1514 | seq_printf(m, "HW control enabled: %s\n", | |
1515 | yesno(rpmodectl1 & GEN6_RP_ENABLE)); | |
1516 | seq_printf(m, "SW control enabled: %s\n", | |
1517 | yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == | |
1518 | GEN6_RP_MEDIA_SW_MODE)); | |
fff24e21 | 1519 | seq_printf(m, "RC1e Enabled: %s\n", |
4d85529d BW |
1520 | yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); |
1521 | seq_printf(m, "RC6 Enabled: %s\n", | |
1522 | yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); | |
1523 | seq_printf(m, "Deep RC6 Enabled: %s\n", | |
1524 | yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); | |
1525 | seq_printf(m, "Deepest RC6 Enabled: %s\n", | |
1526 | yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); | |
267f0c90 | 1527 | seq_puts(m, "Current RC state: "); |
4d85529d BW |
1528 | switch (gt_core_status & GEN6_RCn_MASK) { |
1529 | case GEN6_RC0: | |
1530 | if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) | |
267f0c90 | 1531 | seq_puts(m, "Core Power Down\n"); |
4d85529d | 1532 | else |
267f0c90 | 1533 | seq_puts(m, "on\n"); |
4d85529d BW |
1534 | break; |
1535 | case GEN6_RC3: | |
267f0c90 | 1536 | seq_puts(m, "RC3\n"); |
4d85529d BW |
1537 | break; |
1538 | case GEN6_RC6: | |
267f0c90 | 1539 | seq_puts(m, "RC6\n"); |
4d85529d BW |
1540 | break; |
1541 | case GEN6_RC7: | |
267f0c90 | 1542 | seq_puts(m, "RC7\n"); |
4d85529d BW |
1543 | break; |
1544 | default: | |
267f0c90 | 1545 | seq_puts(m, "Unknown\n"); |
4d85529d BW |
1546 | break; |
1547 | } | |
1548 | ||
1549 | seq_printf(m, "Core Power Down: %s\n", | |
1550 | yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); | |
cce66a28 BW |
1551 | |
1552 | /* Not exactly sure what this is */ | |
1553 | seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", | |
1554 | I915_READ(GEN6_GT_GFX_RC6_LOCKED)); | |
1555 | seq_printf(m, "RC6 residency since boot: %u\n", | |
1556 | I915_READ(GEN6_GT_GFX_RC6)); | |
1557 | seq_printf(m, "RC6+ residency since boot: %u\n", | |
1558 | I915_READ(GEN6_GT_GFX_RC6p)); | |
1559 | seq_printf(m, "RC6++ residency since boot: %u\n", | |
1560 | I915_READ(GEN6_GT_GFX_RC6pp)); | |
1561 | ||
ecd8faea BW |
1562 | seq_printf(m, "RC6 voltage: %dmV\n", |
1563 | GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); | |
1564 | seq_printf(m, "RC6+ voltage: %dmV\n", | |
1565 | GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); | |
1566 | seq_printf(m, "RC6++ voltage: %dmV\n", | |
1567 | GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); | |
4d85529d BW |
1568 | return 0; |
1569 | } | |
1570 | ||
1571 | static int i915_drpc_info(struct seq_file *m, void *unused) | |
1572 | { | |
9f25d007 | 1573 | struct drm_info_node *node = m->private; |
4d85529d BW |
1574 | struct drm_device *dev = node->minor->dev; |
1575 | ||
669ab5aa D |
1576 | if (IS_VALLEYVIEW(dev)) |
1577 | return vlv_drpc_info(m); | |
ac66cf4b | 1578 | else if (INTEL_INFO(dev)->gen >= 6) |
4d85529d BW |
1579 | return gen6_drpc_info(m); |
1580 | else | |
1581 | return ironlake_drpc_info(m); | |
1582 | } | |
1583 | ||
b5e50c3f JB |
1584 | static int i915_fbc_status(struct seq_file *m, void *unused) |
1585 | { | |
9f25d007 | 1586 | struct drm_info_node *node = m->private; |
b5e50c3f | 1587 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1588 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5e50c3f | 1589 | |
3a77c4c4 | 1590 | if (!HAS_FBC(dev)) { |
267f0c90 | 1591 | seq_puts(m, "FBC unsupported on this chipset\n"); |
b5e50c3f JB |
1592 | return 0; |
1593 | } | |
1594 | ||
36623ef8 PZ |
1595 | intel_runtime_pm_get(dev_priv); |
1596 | ||
ee5382ae | 1597 | if (intel_fbc_enabled(dev)) { |
267f0c90 | 1598 | seq_puts(m, "FBC enabled\n"); |
b5e50c3f | 1599 | } else { |
267f0c90 | 1600 | seq_puts(m, "FBC disabled: "); |
5c3fe8b0 | 1601 | switch (dev_priv->fbc.no_fbc_reason) { |
29ebf90f CW |
1602 | case FBC_OK: |
1603 | seq_puts(m, "FBC actived, but currently disabled in hardware"); | |
1604 | break; | |
1605 | case FBC_UNSUPPORTED: | |
1606 | seq_puts(m, "unsupported by this chipset"); | |
1607 | break; | |
bed4a673 | 1608 | case FBC_NO_OUTPUT: |
267f0c90 | 1609 | seq_puts(m, "no outputs"); |
bed4a673 | 1610 | break; |
b5e50c3f | 1611 | case FBC_STOLEN_TOO_SMALL: |
267f0c90 | 1612 | seq_puts(m, "not enough stolen memory"); |
b5e50c3f JB |
1613 | break; |
1614 | case FBC_UNSUPPORTED_MODE: | |
267f0c90 | 1615 | seq_puts(m, "mode not supported"); |
b5e50c3f JB |
1616 | break; |
1617 | case FBC_MODE_TOO_LARGE: | |
267f0c90 | 1618 | seq_puts(m, "mode too large"); |
b5e50c3f JB |
1619 | break; |
1620 | case FBC_BAD_PLANE: | |
267f0c90 | 1621 | seq_puts(m, "FBC unsupported on plane"); |
b5e50c3f JB |
1622 | break; |
1623 | case FBC_NOT_TILED: | |
267f0c90 | 1624 | seq_puts(m, "scanout buffer not tiled"); |
b5e50c3f | 1625 | break; |
9c928d16 | 1626 | case FBC_MULTIPLE_PIPES: |
267f0c90 | 1627 | seq_puts(m, "multiple pipes are enabled"); |
9c928d16 | 1628 | break; |
c1a9f047 | 1629 | case FBC_MODULE_PARAM: |
267f0c90 | 1630 | seq_puts(m, "disabled per module param (default off)"); |
c1a9f047 | 1631 | break; |
8a5729a3 | 1632 | case FBC_CHIP_DEFAULT: |
267f0c90 | 1633 | seq_puts(m, "disabled per chip default"); |
8a5729a3 | 1634 | break; |
87f5ff01 PZ |
1635 | case FBC_ROTATION: |
1636 | seq_puts(m, "rotation not supported"); | |
1637 | break; | |
b5e50c3f | 1638 | default: |
267f0c90 | 1639 | seq_puts(m, "unknown reason"); |
b5e50c3f | 1640 | } |
267f0c90 | 1641 | seq_putc(m, '\n'); |
b5e50c3f | 1642 | } |
36623ef8 | 1643 | |
31b9df10 PZ |
1644 | if (INTEL_INFO(dev_priv)->gen >= 7) |
1645 | seq_printf(m, "Compressing: %s\n", | |
1646 | yesno(I915_READ(FBC_STATUS2) & | |
1647 | FBC_COMPRESSION_MASK)); | |
1648 | ||
36623ef8 PZ |
1649 | intel_runtime_pm_put(dev_priv); |
1650 | ||
b5e50c3f JB |
1651 | return 0; |
1652 | } | |
1653 | ||
da46f936 RV |
1654 | static int i915_fbc_fc_get(void *data, u64 *val) |
1655 | { | |
1656 | struct drm_device *dev = data; | |
1657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1658 | ||
1659 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1660 | return -ENODEV; | |
1661 | ||
1662 | drm_modeset_lock_all(dev); | |
1663 | *val = dev_priv->fbc.false_color; | |
1664 | drm_modeset_unlock_all(dev); | |
1665 | ||
1666 | return 0; | |
1667 | } | |
1668 | ||
1669 | static int i915_fbc_fc_set(void *data, u64 val) | |
1670 | { | |
1671 | struct drm_device *dev = data; | |
1672 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1673 | u32 reg; | |
1674 | ||
1675 | if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) | |
1676 | return -ENODEV; | |
1677 | ||
1678 | drm_modeset_lock_all(dev); | |
1679 | ||
1680 | reg = I915_READ(ILK_DPFC_CONTROL); | |
1681 | dev_priv->fbc.false_color = val; | |
1682 | ||
1683 | I915_WRITE(ILK_DPFC_CONTROL, val ? | |
1684 | (reg | FBC_CTL_FALSE_COLOR) : | |
1685 | (reg & ~FBC_CTL_FALSE_COLOR)); | |
1686 | ||
1687 | drm_modeset_unlock_all(dev); | |
1688 | return 0; | |
1689 | } | |
1690 | ||
1691 | DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, | |
1692 | i915_fbc_fc_get, i915_fbc_fc_set, | |
1693 | "%llu\n"); | |
1694 | ||
92d44621 PZ |
1695 | static int i915_ips_status(struct seq_file *m, void *unused) |
1696 | { | |
9f25d007 | 1697 | struct drm_info_node *node = m->private; |
92d44621 PZ |
1698 | struct drm_device *dev = node->minor->dev; |
1699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1700 | ||
f5adf94e | 1701 | if (!HAS_IPS(dev)) { |
92d44621 PZ |
1702 | seq_puts(m, "not supported\n"); |
1703 | return 0; | |
1704 | } | |
1705 | ||
36623ef8 PZ |
1706 | intel_runtime_pm_get(dev_priv); |
1707 | ||
0eaa53f0 RV |
1708 | seq_printf(m, "Enabled by kernel parameter: %s\n", |
1709 | yesno(i915.enable_ips)); | |
1710 | ||
1711 | if (INTEL_INFO(dev)->gen >= 8) { | |
1712 | seq_puts(m, "Currently: unknown\n"); | |
1713 | } else { | |
1714 | if (I915_READ(IPS_CTL) & IPS_ENABLE) | |
1715 | seq_puts(m, "Currently: enabled\n"); | |
1716 | else | |
1717 | seq_puts(m, "Currently: disabled\n"); | |
1718 | } | |
92d44621 | 1719 | |
36623ef8 PZ |
1720 | intel_runtime_pm_put(dev_priv); |
1721 | ||
92d44621 PZ |
1722 | return 0; |
1723 | } | |
1724 | ||
4a9bef37 JB |
1725 | static int i915_sr_status(struct seq_file *m, void *unused) |
1726 | { | |
9f25d007 | 1727 | struct drm_info_node *node = m->private; |
4a9bef37 | 1728 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1729 | struct drm_i915_private *dev_priv = dev->dev_private; |
4a9bef37 JB |
1730 | bool sr_enabled = false; |
1731 | ||
36623ef8 PZ |
1732 | intel_runtime_pm_get(dev_priv); |
1733 | ||
1398261a | 1734 | if (HAS_PCH_SPLIT(dev)) |
5ba2aaaa | 1735 | sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; |
a6c45cf0 | 1736 | else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) |
4a9bef37 JB |
1737 | sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
1738 | else if (IS_I915GM(dev)) | |
1739 | sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; | |
1740 | else if (IS_PINEVIEW(dev)) | |
1741 | sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; | |
1742 | ||
36623ef8 PZ |
1743 | intel_runtime_pm_put(dev_priv); |
1744 | ||
5ba2aaaa CW |
1745 | seq_printf(m, "self-refresh: %s\n", |
1746 | sr_enabled ? "enabled" : "disabled"); | |
4a9bef37 JB |
1747 | |
1748 | return 0; | |
1749 | } | |
1750 | ||
7648fa99 JB |
1751 | static int i915_emon_status(struct seq_file *m, void *unused) |
1752 | { | |
9f25d007 | 1753 | struct drm_info_node *node = m->private; |
7648fa99 | 1754 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1755 | struct drm_i915_private *dev_priv = dev->dev_private; |
7648fa99 | 1756 | unsigned long temp, chipset, gfx; |
de227ef0 CW |
1757 | int ret; |
1758 | ||
582be6b4 CW |
1759 | if (!IS_GEN5(dev)) |
1760 | return -ENODEV; | |
1761 | ||
de227ef0 CW |
1762 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1763 | if (ret) | |
1764 | return ret; | |
7648fa99 JB |
1765 | |
1766 | temp = i915_mch_val(dev_priv); | |
1767 | chipset = i915_chipset_val(dev_priv); | |
1768 | gfx = i915_gfx_val(dev_priv); | |
de227ef0 | 1769 | mutex_unlock(&dev->struct_mutex); |
7648fa99 JB |
1770 | |
1771 | seq_printf(m, "GMCH temp: %ld\n", temp); | |
1772 | seq_printf(m, "Chipset power: %ld\n", chipset); | |
1773 | seq_printf(m, "GFX power: %ld\n", gfx); | |
1774 | seq_printf(m, "Total power: %ld\n", chipset + gfx); | |
1775 | ||
1776 | return 0; | |
1777 | } | |
1778 | ||
23b2f8bb JB |
1779 | static int i915_ring_freq_table(struct seq_file *m, void *unused) |
1780 | { | |
9f25d007 | 1781 | struct drm_info_node *node = m->private; |
23b2f8bb | 1782 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1783 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfa0199 | 1784 | int ret = 0; |
23b2f8bb JB |
1785 | int gpu_freq, ia_freq; |
1786 | ||
1c70c0ce | 1787 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) { |
267f0c90 | 1788 | seq_puts(m, "unsupported on this chipset\n"); |
23b2f8bb JB |
1789 | return 0; |
1790 | } | |
1791 | ||
5bfa0199 PZ |
1792 | intel_runtime_pm_get(dev_priv); |
1793 | ||
5c9669ce TR |
1794 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
1795 | ||
4fc688ce | 1796 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
23b2f8bb | 1797 | if (ret) |
5bfa0199 | 1798 | goto out; |
23b2f8bb | 1799 | |
267f0c90 | 1800 | seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); |
23b2f8bb | 1801 | |
b39fb297 BW |
1802 | for (gpu_freq = dev_priv->rps.min_freq_softlimit; |
1803 | gpu_freq <= dev_priv->rps.max_freq_softlimit; | |
23b2f8bb | 1804 | gpu_freq++) { |
42c0526c BW |
1805 | ia_freq = gpu_freq; |
1806 | sandybridge_pcode_read(dev_priv, | |
1807 | GEN6_PCODE_READ_MIN_FREQ_TABLE, | |
1808 | &ia_freq); | |
3ebecd07 | 1809 | seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", |
7c59a9c1 | 1810 | intel_gpu_freq(dev_priv, gpu_freq), |
3ebecd07 CW |
1811 | ((ia_freq >> 0) & 0xff) * 100, |
1812 | ((ia_freq >> 8) & 0xff) * 100); | |
23b2f8bb JB |
1813 | } |
1814 | ||
4fc688ce | 1815 | mutex_unlock(&dev_priv->rps.hw_lock); |
23b2f8bb | 1816 | |
5bfa0199 PZ |
1817 | out: |
1818 | intel_runtime_pm_put(dev_priv); | |
1819 | return ret; | |
23b2f8bb JB |
1820 | } |
1821 | ||
44834a67 CW |
1822 | static int i915_opregion(struct seq_file *m, void *unused) |
1823 | { | |
9f25d007 | 1824 | struct drm_info_node *node = m->private; |
44834a67 | 1825 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1826 | struct drm_i915_private *dev_priv = dev->dev_private; |
44834a67 | 1827 | struct intel_opregion *opregion = &dev_priv->opregion; |
0d38f009 | 1828 | void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); |
44834a67 CW |
1829 | int ret; |
1830 | ||
0d38f009 DV |
1831 | if (data == NULL) |
1832 | return -ENOMEM; | |
1833 | ||
44834a67 CW |
1834 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
1835 | if (ret) | |
0d38f009 | 1836 | goto out; |
44834a67 | 1837 | |
0d38f009 DV |
1838 | if (opregion->header) { |
1839 | memcpy_fromio(data, opregion->header, OPREGION_SIZE); | |
1840 | seq_write(m, data, OPREGION_SIZE); | |
1841 | } | |
44834a67 CW |
1842 | |
1843 | mutex_unlock(&dev->struct_mutex); | |
1844 | ||
0d38f009 DV |
1845 | out: |
1846 | kfree(data); | |
44834a67 CW |
1847 | return 0; |
1848 | } | |
1849 | ||
37811fcc CW |
1850 | static int i915_gem_framebuffer_info(struct seq_file *m, void *data) |
1851 | { | |
9f25d007 | 1852 | struct drm_info_node *node = m->private; |
37811fcc | 1853 | struct drm_device *dev = node->minor->dev; |
4520f53a | 1854 | struct intel_fbdev *ifbdev = NULL; |
37811fcc | 1855 | struct intel_framebuffer *fb; |
37811fcc | 1856 | |
4520f53a DV |
1857 | #ifdef CONFIG_DRM_I915_FBDEV |
1858 | struct drm_i915_private *dev_priv = dev->dev_private; | |
37811fcc CW |
1859 | |
1860 | ifbdev = dev_priv->fbdev; | |
1861 | fb = to_intel_framebuffer(ifbdev->helper.fb); | |
1862 | ||
c1ca506d | 1863 | seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1864 | fb->base.width, |
1865 | fb->base.height, | |
1866 | fb->base.depth, | |
623f9783 | 1867 | fb->base.bits_per_pixel, |
c1ca506d | 1868 | fb->base.modifier[0], |
623f9783 | 1869 | atomic_read(&fb->base.refcount.refcount)); |
05394f39 | 1870 | describe_obj(m, fb->obj); |
267f0c90 | 1871 | seq_putc(m, '\n'); |
4520f53a | 1872 | #endif |
37811fcc | 1873 | |
4b096ac1 | 1874 | mutex_lock(&dev->mode_config.fb_lock); |
37811fcc | 1875 | list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { |
131a56dc | 1876 | if (ifbdev && &fb->base == ifbdev->helper.fb) |
37811fcc CW |
1877 | continue; |
1878 | ||
c1ca506d | 1879 | seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", |
37811fcc CW |
1880 | fb->base.width, |
1881 | fb->base.height, | |
1882 | fb->base.depth, | |
623f9783 | 1883 | fb->base.bits_per_pixel, |
c1ca506d | 1884 | fb->base.modifier[0], |
623f9783 | 1885 | atomic_read(&fb->base.refcount.refcount)); |
05394f39 | 1886 | describe_obj(m, fb->obj); |
267f0c90 | 1887 | seq_putc(m, '\n'); |
37811fcc | 1888 | } |
4b096ac1 | 1889 | mutex_unlock(&dev->mode_config.fb_lock); |
37811fcc CW |
1890 | |
1891 | return 0; | |
1892 | } | |
1893 | ||
c9fe99bd OM |
1894 | static void describe_ctx_ringbuf(struct seq_file *m, |
1895 | struct intel_ringbuffer *ringbuf) | |
1896 | { | |
1897 | seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", | |
1898 | ringbuf->space, ringbuf->head, ringbuf->tail, | |
1899 | ringbuf->last_retired_head); | |
1900 | } | |
1901 | ||
e76d3630 BW |
1902 | static int i915_context_status(struct seq_file *m, void *unused) |
1903 | { | |
9f25d007 | 1904 | struct drm_info_node *node = m->private; |
e76d3630 | 1905 | struct drm_device *dev = node->minor->dev; |
e277a1f8 | 1906 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1907 | struct intel_engine_cs *ring; |
273497e5 | 1908 | struct intel_context *ctx; |
a168c293 | 1909 | int ret, i; |
e76d3630 | 1910 | |
f3d28878 | 1911 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
e76d3630 BW |
1912 | if (ret) |
1913 | return ret; | |
1914 | ||
a33afea5 | 1915 | list_for_each_entry(ctx, &dev_priv->context_list, link) { |
c9fe99bd OM |
1916 | if (!i915.enable_execlists && |
1917 | ctx->legacy_hw_ctx.rcs_state == NULL) | |
b77f6997 CW |
1918 | continue; |
1919 | ||
a33afea5 | 1920 | seq_puts(m, "HW context "); |
3ccfd19d | 1921 | describe_ctx(m, ctx); |
c9fe99bd | 1922 | for_each_ring(ring, dev_priv, i) { |
a33afea5 | 1923 | if (ring->default_context == ctx) |
c9fe99bd OM |
1924 | seq_printf(m, "(default context %s) ", |
1925 | ring->name); | |
1926 | } | |
1927 | ||
1928 | if (i915.enable_execlists) { | |
1929 | seq_putc(m, '\n'); | |
1930 | for_each_ring(ring, dev_priv, i) { | |
1931 | struct drm_i915_gem_object *ctx_obj = | |
1932 | ctx->engine[i].state; | |
1933 | struct intel_ringbuffer *ringbuf = | |
1934 | ctx->engine[i].ringbuf; | |
1935 | ||
1936 | seq_printf(m, "%s: ", ring->name); | |
1937 | if (ctx_obj) | |
1938 | describe_obj(m, ctx_obj); | |
1939 | if (ringbuf) | |
1940 | describe_ctx_ringbuf(m, ringbuf); | |
1941 | seq_putc(m, '\n'); | |
1942 | } | |
1943 | } else { | |
1944 | describe_obj(m, ctx->legacy_hw_ctx.rcs_state); | |
1945 | } | |
a33afea5 | 1946 | |
a33afea5 | 1947 | seq_putc(m, '\n'); |
a168c293 BW |
1948 | } |
1949 | ||
f3d28878 | 1950 | mutex_unlock(&dev->struct_mutex); |
e76d3630 BW |
1951 | |
1952 | return 0; | |
1953 | } | |
1954 | ||
064ca1d2 TD |
1955 | static void i915_dump_lrc_obj(struct seq_file *m, |
1956 | struct intel_engine_cs *ring, | |
1957 | struct drm_i915_gem_object *ctx_obj) | |
1958 | { | |
1959 | struct page *page; | |
1960 | uint32_t *reg_state; | |
1961 | int j; | |
1962 | unsigned long ggtt_offset = 0; | |
1963 | ||
1964 | if (ctx_obj == NULL) { | |
1965 | seq_printf(m, "Context on %s with no gem object\n", | |
1966 | ring->name); | |
1967 | return; | |
1968 | } | |
1969 | ||
1970 | seq_printf(m, "CONTEXT: %s %u\n", ring->name, | |
1971 | intel_execlists_ctx_id(ctx_obj)); | |
1972 | ||
1973 | if (!i915_gem_obj_ggtt_bound(ctx_obj)) | |
1974 | seq_puts(m, "\tNot bound in GGTT\n"); | |
1975 | else | |
1976 | ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); | |
1977 | ||
1978 | if (i915_gem_object_get_pages(ctx_obj)) { | |
1979 | seq_puts(m, "\tFailed to get pages for context object\n"); | |
1980 | return; | |
1981 | } | |
1982 | ||
1983 | page = i915_gem_object_get_page(ctx_obj, 1); | |
1984 | if (!WARN_ON(page == NULL)) { | |
1985 | reg_state = kmap_atomic(page); | |
1986 | ||
1987 | for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { | |
1988 | seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
1989 | ggtt_offset + 4096 + (j * 4), | |
1990 | reg_state[j], reg_state[j + 1], | |
1991 | reg_state[j + 2], reg_state[j + 3]); | |
1992 | } | |
1993 | kunmap_atomic(reg_state); | |
1994 | } | |
1995 | ||
1996 | seq_putc(m, '\n'); | |
1997 | } | |
1998 | ||
c0ab1ae9 BW |
1999 | static int i915_dump_lrc(struct seq_file *m, void *unused) |
2000 | { | |
2001 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2002 | struct drm_device *dev = node->minor->dev; | |
2003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2004 | struct intel_engine_cs *ring; | |
2005 | struct intel_context *ctx; | |
2006 | int ret, i; | |
2007 | ||
2008 | if (!i915.enable_execlists) { | |
2009 | seq_printf(m, "Logical Ring Contexts are disabled\n"); | |
2010 | return 0; | |
2011 | } | |
2012 | ||
2013 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2014 | if (ret) | |
2015 | return ret; | |
2016 | ||
2017 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
2018 | for_each_ring(ring, dev_priv, i) { | |
064ca1d2 TD |
2019 | if (ring->default_context != ctx) |
2020 | i915_dump_lrc_obj(m, ring, | |
2021 | ctx->engine[i].state); | |
c0ab1ae9 BW |
2022 | } |
2023 | } | |
2024 | ||
2025 | mutex_unlock(&dev->struct_mutex); | |
2026 | ||
2027 | return 0; | |
2028 | } | |
2029 | ||
4ba70e44 OM |
2030 | static int i915_execlists(struct seq_file *m, void *data) |
2031 | { | |
2032 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
2033 | struct drm_device *dev = node->minor->dev; | |
2034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2035 | struct intel_engine_cs *ring; | |
2036 | u32 status_pointer; | |
2037 | u8 read_pointer; | |
2038 | u8 write_pointer; | |
2039 | u32 status; | |
2040 | u32 ctx_id; | |
2041 | struct list_head *cursor; | |
2042 | int ring_id, i; | |
2043 | int ret; | |
2044 | ||
2045 | if (!i915.enable_execlists) { | |
2046 | seq_puts(m, "Logical Ring Contexts are disabled\n"); | |
2047 | return 0; | |
2048 | } | |
2049 | ||
2050 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2051 | if (ret) | |
2052 | return ret; | |
2053 | ||
fc0412ec MT |
2054 | intel_runtime_pm_get(dev_priv); |
2055 | ||
4ba70e44 | 2056 | for_each_ring(ring, dev_priv, ring_id) { |
6d3d8274 | 2057 | struct drm_i915_gem_request *head_req = NULL; |
4ba70e44 OM |
2058 | int count = 0; |
2059 | unsigned long flags; | |
2060 | ||
2061 | seq_printf(m, "%s\n", ring->name); | |
2062 | ||
2063 | status = I915_READ(RING_EXECLIST_STATUS(ring)); | |
2064 | ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4); | |
2065 | seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", | |
2066 | status, ctx_id); | |
2067 | ||
2068 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
2069 | seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); | |
2070 | ||
2071 | read_pointer = ring->next_context_status_buffer; | |
2072 | write_pointer = status_pointer & 0x07; | |
2073 | if (read_pointer > write_pointer) | |
2074 | write_pointer += 6; | |
2075 | seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", | |
2076 | read_pointer, write_pointer); | |
2077 | ||
2078 | for (i = 0; i < 6; i++) { | |
2079 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i); | |
2080 | ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4); | |
2081 | ||
2082 | seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", | |
2083 | i, status, ctx_id); | |
2084 | } | |
2085 | ||
2086 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2087 | list_for_each(cursor, &ring->execlist_queue) | |
2088 | count++; | |
2089 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
6d3d8274 | 2090 | struct drm_i915_gem_request, execlist_link); |
4ba70e44 OM |
2091 | spin_unlock_irqrestore(&ring->execlist_lock, flags); |
2092 | ||
2093 | seq_printf(m, "\t%d requests in queue\n", count); | |
2094 | if (head_req) { | |
2095 | struct drm_i915_gem_object *ctx_obj; | |
2096 | ||
6d3d8274 | 2097 | ctx_obj = head_req->ctx->engine[ring_id].state; |
4ba70e44 OM |
2098 | seq_printf(m, "\tHead request id: %u\n", |
2099 | intel_execlists_ctx_id(ctx_obj)); | |
2100 | seq_printf(m, "\tHead request tail: %u\n", | |
6d3d8274 | 2101 | head_req->tail); |
4ba70e44 OM |
2102 | } |
2103 | ||
2104 | seq_putc(m, '\n'); | |
2105 | } | |
2106 | ||
fc0412ec | 2107 | intel_runtime_pm_put(dev_priv); |
4ba70e44 OM |
2108 | mutex_unlock(&dev->struct_mutex); |
2109 | ||
2110 | return 0; | |
2111 | } | |
2112 | ||
ea16a3cd DV |
2113 | static const char *swizzle_string(unsigned swizzle) |
2114 | { | |
aee56cff | 2115 | switch (swizzle) { |
ea16a3cd DV |
2116 | case I915_BIT_6_SWIZZLE_NONE: |
2117 | return "none"; | |
2118 | case I915_BIT_6_SWIZZLE_9: | |
2119 | return "bit9"; | |
2120 | case I915_BIT_6_SWIZZLE_9_10: | |
2121 | return "bit9/bit10"; | |
2122 | case I915_BIT_6_SWIZZLE_9_11: | |
2123 | return "bit9/bit11"; | |
2124 | case I915_BIT_6_SWIZZLE_9_10_11: | |
2125 | return "bit9/bit10/bit11"; | |
2126 | case I915_BIT_6_SWIZZLE_9_17: | |
2127 | return "bit9/bit17"; | |
2128 | case I915_BIT_6_SWIZZLE_9_10_17: | |
2129 | return "bit9/bit10/bit17"; | |
2130 | case I915_BIT_6_SWIZZLE_UNKNOWN: | |
8a168ca7 | 2131 | return "unknown"; |
ea16a3cd DV |
2132 | } |
2133 | ||
2134 | return "bug"; | |
2135 | } | |
2136 | ||
2137 | static int i915_swizzle_info(struct seq_file *m, void *data) | |
2138 | { | |
9f25d007 | 2139 | struct drm_info_node *node = m->private; |
ea16a3cd DV |
2140 | struct drm_device *dev = node->minor->dev; |
2141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22bcfc6a DV |
2142 | int ret; |
2143 | ||
2144 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2145 | if (ret) | |
2146 | return ret; | |
c8c8fb33 | 2147 | intel_runtime_pm_get(dev_priv); |
ea16a3cd | 2148 | |
ea16a3cd DV |
2149 | seq_printf(m, "bit6 swizzle for X-tiling = %s\n", |
2150 | swizzle_string(dev_priv->mm.bit_6_swizzle_x)); | |
2151 | seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", | |
2152 | swizzle_string(dev_priv->mm.bit_6_swizzle_y)); | |
2153 | ||
2154 | if (IS_GEN3(dev) || IS_GEN4(dev)) { | |
2155 | seq_printf(m, "DDC = 0x%08x\n", | |
2156 | I915_READ(DCC)); | |
656bfa3a DV |
2157 | seq_printf(m, "DDC2 = 0x%08x\n", |
2158 | I915_READ(DCC2)); | |
ea16a3cd DV |
2159 | seq_printf(m, "C0DRB3 = 0x%04x\n", |
2160 | I915_READ16(C0DRB3)); | |
2161 | seq_printf(m, "C1DRB3 = 0x%04x\n", | |
2162 | I915_READ16(C1DRB3)); | |
9d3203e1 | 2163 | } else if (INTEL_INFO(dev)->gen >= 6) { |
3fa7d235 DV |
2164 | seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", |
2165 | I915_READ(MAD_DIMM_C0)); | |
2166 | seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", | |
2167 | I915_READ(MAD_DIMM_C1)); | |
2168 | seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", | |
2169 | I915_READ(MAD_DIMM_C2)); | |
2170 | seq_printf(m, "TILECTL = 0x%08x\n", | |
2171 | I915_READ(TILECTL)); | |
5907f5fb | 2172 | if (INTEL_INFO(dev)->gen >= 8) |
9d3203e1 BW |
2173 | seq_printf(m, "GAMTARBMODE = 0x%08x\n", |
2174 | I915_READ(GAMTARBMODE)); | |
2175 | else | |
2176 | seq_printf(m, "ARB_MODE = 0x%08x\n", | |
2177 | I915_READ(ARB_MODE)); | |
3fa7d235 DV |
2178 | seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", |
2179 | I915_READ(DISP_ARB_CTL)); | |
ea16a3cd | 2180 | } |
656bfa3a DV |
2181 | |
2182 | if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2183 | seq_puts(m, "L-shaped memory detected\n"); | |
2184 | ||
c8c8fb33 | 2185 | intel_runtime_pm_put(dev_priv); |
ea16a3cd DV |
2186 | mutex_unlock(&dev->struct_mutex); |
2187 | ||
2188 | return 0; | |
2189 | } | |
2190 | ||
1c60fef5 BW |
2191 | static int per_file_ctx(int id, void *ptr, void *data) |
2192 | { | |
273497e5 | 2193 | struct intel_context *ctx = ptr; |
1c60fef5 | 2194 | struct seq_file *m = data; |
ae6c4806 DV |
2195 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
2196 | ||
2197 | if (!ppgtt) { | |
2198 | seq_printf(m, " no ppgtt for context %d\n", | |
2199 | ctx->user_handle); | |
2200 | return 0; | |
2201 | } | |
1c60fef5 | 2202 | |
f83d6518 OM |
2203 | if (i915_gem_context_is_default(ctx)) |
2204 | seq_puts(m, " default context:\n"); | |
2205 | else | |
821d66dd | 2206 | seq_printf(m, " context %d:\n", ctx->user_handle); |
1c60fef5 BW |
2207 | ppgtt->debug_dump(ppgtt, m); |
2208 | ||
2209 | return 0; | |
2210 | } | |
2211 | ||
77df6772 | 2212 | static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) |
3cf17fc5 | 2213 | { |
3cf17fc5 | 2214 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2215 | struct intel_engine_cs *ring; |
77df6772 BW |
2216 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
2217 | int unused, i; | |
3cf17fc5 | 2218 | |
77df6772 BW |
2219 | if (!ppgtt) |
2220 | return; | |
2221 | ||
77df6772 BW |
2222 | for_each_ring(ring, dev_priv, unused) { |
2223 | seq_printf(m, "%s\n", ring->name); | |
2224 | for (i = 0; i < 4; i++) { | |
2225 | u32 offset = 0x270 + i * 8; | |
2226 | u64 pdp = I915_READ(ring->mmio_base + offset + 4); | |
2227 | pdp <<= 32; | |
2228 | pdp |= I915_READ(ring->mmio_base + offset); | |
a2a5b15c | 2229 | seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); |
77df6772 BW |
2230 | } |
2231 | } | |
2232 | } | |
2233 | ||
2234 | static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) | |
2235 | { | |
2236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2237 | struct intel_engine_cs *ring; |
1c60fef5 | 2238 | struct drm_file *file; |
77df6772 | 2239 | int i; |
3cf17fc5 | 2240 | |
3cf17fc5 DV |
2241 | if (INTEL_INFO(dev)->gen == 6) |
2242 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); | |
2243 | ||
a2c7f6fd | 2244 | for_each_ring(ring, dev_priv, i) { |
3cf17fc5 DV |
2245 | seq_printf(m, "%s\n", ring->name); |
2246 | if (INTEL_INFO(dev)->gen == 7) | |
2247 | seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); | |
2248 | seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); | |
2249 | seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); | |
2250 | seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); | |
2251 | } | |
2252 | if (dev_priv->mm.aliasing_ppgtt) { | |
2253 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2254 | ||
267f0c90 | 2255 | seq_puts(m, "aliasing PPGTT:\n"); |
7324cc04 | 2256 | seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset); |
1c60fef5 | 2257 | |
87d60b63 | 2258 | ppgtt->debug_dump(ppgtt, m); |
ae6c4806 | 2259 | } |
1c60fef5 BW |
2260 | |
2261 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { | |
2262 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1c60fef5 | 2263 | |
1c60fef5 BW |
2264 | seq_printf(m, "proc: %s\n", |
2265 | get_pid_task(file->pid, PIDTYPE_PID)->comm); | |
1c60fef5 | 2266 | idr_for_each(&file_priv->context_idr, per_file_ctx, m); |
3cf17fc5 DV |
2267 | } |
2268 | seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); | |
77df6772 BW |
2269 | } |
2270 | ||
2271 | static int i915_ppgtt_info(struct seq_file *m, void *data) | |
2272 | { | |
9f25d007 | 2273 | struct drm_info_node *node = m->private; |
77df6772 | 2274 | struct drm_device *dev = node->minor->dev; |
c8c8fb33 | 2275 | struct drm_i915_private *dev_priv = dev->dev_private; |
77df6772 BW |
2276 | |
2277 | int ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2278 | if (ret) | |
2279 | return ret; | |
c8c8fb33 | 2280 | intel_runtime_pm_get(dev_priv); |
77df6772 BW |
2281 | |
2282 | if (INTEL_INFO(dev)->gen >= 8) | |
2283 | gen8_ppgtt_info(m, dev); | |
2284 | else if (INTEL_INFO(dev)->gen >= 6) | |
2285 | gen6_ppgtt_info(m, dev); | |
2286 | ||
c8c8fb33 | 2287 | intel_runtime_pm_put(dev_priv); |
3cf17fc5 DV |
2288 | mutex_unlock(&dev->struct_mutex); |
2289 | ||
2290 | return 0; | |
2291 | } | |
2292 | ||
f5a4c67d CW |
2293 | static int count_irq_waiters(struct drm_i915_private *i915) |
2294 | { | |
2295 | struct intel_engine_cs *ring; | |
2296 | int count = 0; | |
2297 | int i; | |
2298 | ||
2299 | for_each_ring(ring, i915, i) | |
2300 | count += ring->irq_refcount; | |
2301 | ||
2302 | return count; | |
2303 | } | |
2304 | ||
1854d5ca CW |
2305 | static int i915_rps_boost_info(struct seq_file *m, void *data) |
2306 | { | |
2307 | struct drm_info_node *node = m->private; | |
2308 | struct drm_device *dev = node->minor->dev; | |
2309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2310 | struct drm_file *file; | |
1854d5ca | 2311 | |
f5a4c67d CW |
2312 | seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); |
2313 | seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); | |
2314 | seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); | |
2315 | seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n", | |
2316 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
2317 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
2318 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), | |
2319 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), | |
2320 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); | |
8d3afd7d | 2321 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
2322 | list_for_each_entry_reverse(file, &dev->filelist, lhead) { |
2323 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2324 | struct task_struct *task; | |
2325 | ||
2326 | rcu_read_lock(); | |
2327 | task = pid_task(file->pid, PIDTYPE_PID); | |
2328 | seq_printf(m, "%s [%d]: %d boosts%s\n", | |
2329 | task ? task->comm : "<unknown>", | |
2330 | task ? task->pid : -1, | |
2e1b8730 CW |
2331 | file_priv->rps.boosts, |
2332 | list_empty(&file_priv->rps.link) ? "" : ", active"); | |
1854d5ca CW |
2333 | rcu_read_unlock(); |
2334 | } | |
2e1b8730 CW |
2335 | seq_printf(m, "Semaphore boosts: %d%s\n", |
2336 | dev_priv->rps.semaphores.boosts, | |
2337 | list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active"); | |
2338 | seq_printf(m, "MMIO flip boosts: %d%s\n", | |
2339 | dev_priv->rps.mmioflips.boosts, | |
2340 | list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); | |
1854d5ca | 2341 | seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); |
8d3afd7d | 2342 | spin_unlock(&dev_priv->rps.client_lock); |
1854d5ca | 2343 | |
8d3afd7d | 2344 | return 0; |
1854d5ca CW |
2345 | } |
2346 | ||
63573eb7 BW |
2347 | static int i915_llc(struct seq_file *m, void *data) |
2348 | { | |
9f25d007 | 2349 | struct drm_info_node *node = m->private; |
63573eb7 BW |
2350 | struct drm_device *dev = node->minor->dev; |
2351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2352 | ||
2353 | /* Size calculation for LLC is a bit of a pain. Ignore for now. */ | |
2354 | seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); | |
2355 | seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); | |
2356 | ||
2357 | return 0; | |
2358 | } | |
2359 | ||
e91fd8c6 RV |
2360 | static int i915_edp_psr_status(struct seq_file *m, void *data) |
2361 | { | |
2362 | struct drm_info_node *node = m->private; | |
2363 | struct drm_device *dev = node->minor->dev; | |
2364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a031d709 | 2365 | u32 psrperf = 0; |
a6cbdb8e RV |
2366 | u32 stat[3]; |
2367 | enum pipe pipe; | |
a031d709 | 2368 | bool enabled = false; |
e91fd8c6 | 2369 | |
3553a8ea DL |
2370 | if (!HAS_PSR(dev)) { |
2371 | seq_puts(m, "PSR not supported\n"); | |
2372 | return 0; | |
2373 | } | |
2374 | ||
c8c8fb33 PZ |
2375 | intel_runtime_pm_get(dev_priv); |
2376 | ||
fa128fa6 | 2377 | mutex_lock(&dev_priv->psr.lock); |
a031d709 RV |
2378 | seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); |
2379 | seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); | |
2807cf69 | 2380 | seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); |
5755c78f | 2381 | seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); |
fa128fa6 DV |
2382 | seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", |
2383 | dev_priv->psr.busy_frontbuffer_bits); | |
2384 | seq_printf(m, "Re-enable work scheduled: %s\n", | |
2385 | yesno(work_busy(&dev_priv->psr.work.work))); | |
e91fd8c6 | 2386 | |
3553a8ea DL |
2387 | if (HAS_DDI(dev)) |
2388 | enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; | |
2389 | else { | |
2390 | for_each_pipe(dev_priv, pipe) { | |
2391 | stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & | |
2392 | VLV_EDP_PSR_CURR_STATE_MASK; | |
2393 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2394 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2395 | enabled = true; | |
a6cbdb8e RV |
2396 | } |
2397 | } | |
2398 | seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); | |
2399 | ||
2400 | if (!HAS_DDI(dev)) | |
2401 | for_each_pipe(dev_priv, pipe) { | |
2402 | if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || | |
2403 | (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) | |
2404 | seq_printf(m, " pipe %c", pipe_name(pipe)); | |
2405 | } | |
2406 | seq_puts(m, "\n"); | |
e91fd8c6 | 2407 | |
a6cbdb8e | 2408 | /* CHV PSR has no kind of performance counter */ |
3553a8ea | 2409 | if (HAS_DDI(dev)) { |
a031d709 RV |
2410 | psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & |
2411 | EDP_PSR_PERF_CNT_MASK; | |
a6cbdb8e RV |
2412 | |
2413 | seq_printf(m, "Performance_Counter: %u\n", psrperf); | |
2414 | } | |
fa128fa6 | 2415 | mutex_unlock(&dev_priv->psr.lock); |
e91fd8c6 | 2416 | |
c8c8fb33 | 2417 | intel_runtime_pm_put(dev_priv); |
e91fd8c6 RV |
2418 | return 0; |
2419 | } | |
2420 | ||
d2e216d0 RV |
2421 | static int i915_sink_crc(struct seq_file *m, void *data) |
2422 | { | |
2423 | struct drm_info_node *node = m->private; | |
2424 | struct drm_device *dev = node->minor->dev; | |
2425 | struct intel_encoder *encoder; | |
2426 | struct intel_connector *connector; | |
2427 | struct intel_dp *intel_dp = NULL; | |
2428 | int ret; | |
2429 | u8 crc[6]; | |
2430 | ||
2431 | drm_modeset_lock_all(dev); | |
aca5e361 | 2432 | for_each_intel_connector(dev, connector) { |
d2e216d0 RV |
2433 | |
2434 | if (connector->base.dpms != DRM_MODE_DPMS_ON) | |
2435 | continue; | |
2436 | ||
b6ae3c7c PZ |
2437 | if (!connector->base.encoder) |
2438 | continue; | |
2439 | ||
d2e216d0 RV |
2440 | encoder = to_intel_encoder(connector->base.encoder); |
2441 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2442 | continue; | |
2443 | ||
2444 | intel_dp = enc_to_intel_dp(&encoder->base); | |
2445 | ||
2446 | ret = intel_dp_sink_crc(intel_dp, crc); | |
2447 | if (ret) | |
2448 | goto out; | |
2449 | ||
2450 | seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", | |
2451 | crc[0], crc[1], crc[2], | |
2452 | crc[3], crc[4], crc[5]); | |
2453 | goto out; | |
2454 | } | |
2455 | ret = -ENODEV; | |
2456 | out: | |
2457 | drm_modeset_unlock_all(dev); | |
2458 | return ret; | |
2459 | } | |
2460 | ||
ec013e7f JB |
2461 | static int i915_energy_uJ(struct seq_file *m, void *data) |
2462 | { | |
2463 | struct drm_info_node *node = m->private; | |
2464 | struct drm_device *dev = node->minor->dev; | |
2465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2466 | u64 power; | |
2467 | u32 units; | |
2468 | ||
2469 | if (INTEL_INFO(dev)->gen < 6) | |
2470 | return -ENODEV; | |
2471 | ||
36623ef8 PZ |
2472 | intel_runtime_pm_get(dev_priv); |
2473 | ||
ec013e7f JB |
2474 | rdmsrl(MSR_RAPL_POWER_UNIT, power); |
2475 | power = (power & 0x1f00) >> 8; | |
2476 | units = 1000000 / (1 << power); /* convert to uJ */ | |
2477 | power = I915_READ(MCH_SECP_NRG_STTS); | |
2478 | power *= units; | |
2479 | ||
36623ef8 PZ |
2480 | intel_runtime_pm_put(dev_priv); |
2481 | ||
ec013e7f | 2482 | seq_printf(m, "%llu", (long long unsigned)power); |
371db66a PZ |
2483 | |
2484 | return 0; | |
2485 | } | |
2486 | ||
6455c870 | 2487 | static int i915_runtime_pm_status(struct seq_file *m, void *unused) |
371db66a | 2488 | { |
9f25d007 | 2489 | struct drm_info_node *node = m->private; |
371db66a PZ |
2490 | struct drm_device *dev = node->minor->dev; |
2491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2492 | ||
6455c870 | 2493 | if (!HAS_RUNTIME_PM(dev)) { |
371db66a PZ |
2494 | seq_puts(m, "not supported\n"); |
2495 | return 0; | |
2496 | } | |
2497 | ||
86c4ec0d | 2498 | seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); |
371db66a | 2499 | seq_printf(m, "IRQs disabled: %s\n", |
9df7575f | 2500 | yesno(!intel_irqs_enabled(dev_priv))); |
0d804184 | 2501 | #ifdef CONFIG_PM |
a6aaec8b DL |
2502 | seq_printf(m, "Usage count: %d\n", |
2503 | atomic_read(&dev->dev->power.usage_count)); | |
0d804184 CW |
2504 | #else |
2505 | seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); | |
2506 | #endif | |
371db66a | 2507 | |
ec013e7f JB |
2508 | return 0; |
2509 | } | |
2510 | ||
1da51581 ID |
2511 | static const char *power_domain_str(enum intel_display_power_domain domain) |
2512 | { | |
2513 | switch (domain) { | |
2514 | case POWER_DOMAIN_PIPE_A: | |
2515 | return "PIPE_A"; | |
2516 | case POWER_DOMAIN_PIPE_B: | |
2517 | return "PIPE_B"; | |
2518 | case POWER_DOMAIN_PIPE_C: | |
2519 | return "PIPE_C"; | |
2520 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
2521 | return "PIPE_A_PANEL_FITTER"; | |
2522 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
2523 | return "PIPE_B_PANEL_FITTER"; | |
2524 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
2525 | return "PIPE_C_PANEL_FITTER"; | |
2526 | case POWER_DOMAIN_TRANSCODER_A: | |
2527 | return "TRANSCODER_A"; | |
2528 | case POWER_DOMAIN_TRANSCODER_B: | |
2529 | return "TRANSCODER_B"; | |
2530 | case POWER_DOMAIN_TRANSCODER_C: | |
2531 | return "TRANSCODER_C"; | |
2532 | case POWER_DOMAIN_TRANSCODER_EDP: | |
2533 | return "TRANSCODER_EDP"; | |
319be8ae ID |
2534 | case POWER_DOMAIN_PORT_DDI_A_2_LANES: |
2535 | return "PORT_DDI_A_2_LANES"; | |
2536 | case POWER_DOMAIN_PORT_DDI_A_4_LANES: | |
2537 | return "PORT_DDI_A_4_LANES"; | |
2538 | case POWER_DOMAIN_PORT_DDI_B_2_LANES: | |
2539 | return "PORT_DDI_B_2_LANES"; | |
2540 | case POWER_DOMAIN_PORT_DDI_B_4_LANES: | |
2541 | return "PORT_DDI_B_4_LANES"; | |
2542 | case POWER_DOMAIN_PORT_DDI_C_2_LANES: | |
2543 | return "PORT_DDI_C_2_LANES"; | |
2544 | case POWER_DOMAIN_PORT_DDI_C_4_LANES: | |
2545 | return "PORT_DDI_C_4_LANES"; | |
2546 | case POWER_DOMAIN_PORT_DDI_D_2_LANES: | |
2547 | return "PORT_DDI_D_2_LANES"; | |
2548 | case POWER_DOMAIN_PORT_DDI_D_4_LANES: | |
2549 | return "PORT_DDI_D_4_LANES"; | |
2550 | case POWER_DOMAIN_PORT_DSI: | |
2551 | return "PORT_DSI"; | |
2552 | case POWER_DOMAIN_PORT_CRT: | |
2553 | return "PORT_CRT"; | |
2554 | case POWER_DOMAIN_PORT_OTHER: | |
2555 | return "PORT_OTHER"; | |
1da51581 ID |
2556 | case POWER_DOMAIN_VGA: |
2557 | return "VGA"; | |
2558 | case POWER_DOMAIN_AUDIO: | |
2559 | return "AUDIO"; | |
bd2bb1b9 PZ |
2560 | case POWER_DOMAIN_PLLS: |
2561 | return "PLLS"; | |
1407121a S |
2562 | case POWER_DOMAIN_AUX_A: |
2563 | return "AUX_A"; | |
2564 | case POWER_DOMAIN_AUX_B: | |
2565 | return "AUX_B"; | |
2566 | case POWER_DOMAIN_AUX_C: | |
2567 | return "AUX_C"; | |
2568 | case POWER_DOMAIN_AUX_D: | |
2569 | return "AUX_D"; | |
1da51581 ID |
2570 | case POWER_DOMAIN_INIT: |
2571 | return "INIT"; | |
2572 | default: | |
5f77eeb0 | 2573 | MISSING_CASE(domain); |
1da51581 ID |
2574 | return "?"; |
2575 | } | |
2576 | } | |
2577 | ||
2578 | static int i915_power_domain_info(struct seq_file *m, void *unused) | |
2579 | { | |
9f25d007 | 2580 | struct drm_info_node *node = m->private; |
1da51581 ID |
2581 | struct drm_device *dev = node->minor->dev; |
2582 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2583 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2584 | int i; | |
2585 | ||
2586 | mutex_lock(&power_domains->lock); | |
2587 | ||
2588 | seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); | |
2589 | for (i = 0; i < power_domains->power_well_count; i++) { | |
2590 | struct i915_power_well *power_well; | |
2591 | enum intel_display_power_domain power_domain; | |
2592 | ||
2593 | power_well = &power_domains->power_wells[i]; | |
2594 | seq_printf(m, "%-25s %d\n", power_well->name, | |
2595 | power_well->count); | |
2596 | ||
2597 | for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; | |
2598 | power_domain++) { | |
2599 | if (!(BIT(power_domain) & power_well->domains)) | |
2600 | continue; | |
2601 | ||
2602 | seq_printf(m, " %-23s %d\n", | |
2603 | power_domain_str(power_domain), | |
2604 | power_domains->domain_use_count[power_domain]); | |
2605 | } | |
2606 | } | |
2607 | ||
2608 | mutex_unlock(&power_domains->lock); | |
2609 | ||
2610 | return 0; | |
2611 | } | |
2612 | ||
53f5e3ca JB |
2613 | static void intel_seq_print_mode(struct seq_file *m, int tabs, |
2614 | struct drm_display_mode *mode) | |
2615 | { | |
2616 | int i; | |
2617 | ||
2618 | for (i = 0; i < tabs; i++) | |
2619 | seq_putc(m, '\t'); | |
2620 | ||
2621 | seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", | |
2622 | mode->base.id, mode->name, | |
2623 | mode->vrefresh, mode->clock, | |
2624 | mode->hdisplay, mode->hsync_start, | |
2625 | mode->hsync_end, mode->htotal, | |
2626 | mode->vdisplay, mode->vsync_start, | |
2627 | mode->vsync_end, mode->vtotal, | |
2628 | mode->type, mode->flags); | |
2629 | } | |
2630 | ||
2631 | static void intel_encoder_info(struct seq_file *m, | |
2632 | struct intel_crtc *intel_crtc, | |
2633 | struct intel_encoder *intel_encoder) | |
2634 | { | |
9f25d007 | 2635 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2636 | struct drm_device *dev = node->minor->dev; |
2637 | struct drm_crtc *crtc = &intel_crtc->base; | |
2638 | struct intel_connector *intel_connector; | |
2639 | struct drm_encoder *encoder; | |
2640 | ||
2641 | encoder = &intel_encoder->base; | |
2642 | seq_printf(m, "\tencoder %d: type: %s, connectors:\n", | |
8e329a03 | 2643 | encoder->base.id, encoder->name); |
53f5e3ca JB |
2644 | for_each_connector_on_encoder(dev, encoder, intel_connector) { |
2645 | struct drm_connector *connector = &intel_connector->base; | |
2646 | seq_printf(m, "\t\tconnector %d: type: %s, status: %s", | |
2647 | connector->base.id, | |
c23cc417 | 2648 | connector->name, |
53f5e3ca JB |
2649 | drm_get_connector_status_name(connector->status)); |
2650 | if (connector->status == connector_status_connected) { | |
2651 | struct drm_display_mode *mode = &crtc->mode; | |
2652 | seq_printf(m, ", mode:\n"); | |
2653 | intel_seq_print_mode(m, 2, mode); | |
2654 | } else { | |
2655 | seq_putc(m, '\n'); | |
2656 | } | |
2657 | } | |
2658 | } | |
2659 | ||
2660 | static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) | |
2661 | { | |
9f25d007 | 2662 | struct drm_info_node *node = m->private; |
53f5e3ca JB |
2663 | struct drm_device *dev = node->minor->dev; |
2664 | struct drm_crtc *crtc = &intel_crtc->base; | |
2665 | struct intel_encoder *intel_encoder; | |
2666 | ||
5aa8a937 MR |
2667 | if (crtc->primary->fb) |
2668 | seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", | |
2669 | crtc->primary->fb->base.id, crtc->x, crtc->y, | |
2670 | crtc->primary->fb->width, crtc->primary->fb->height); | |
2671 | else | |
2672 | seq_puts(m, "\tprimary plane disabled\n"); | |
53f5e3ca JB |
2673 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
2674 | intel_encoder_info(m, intel_crtc, intel_encoder); | |
2675 | } | |
2676 | ||
2677 | static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) | |
2678 | { | |
2679 | struct drm_display_mode *mode = panel->fixed_mode; | |
2680 | ||
2681 | seq_printf(m, "\tfixed mode:\n"); | |
2682 | intel_seq_print_mode(m, 2, mode); | |
2683 | } | |
2684 | ||
2685 | static void intel_dp_info(struct seq_file *m, | |
2686 | struct intel_connector *intel_connector) | |
2687 | { | |
2688 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2689 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
2690 | ||
2691 | seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); | |
2692 | seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : | |
2693 | "no"); | |
2694 | if (intel_encoder->type == INTEL_OUTPUT_EDP) | |
2695 | intel_panel_info(m, &intel_connector->panel); | |
2696 | } | |
2697 | ||
2698 | static void intel_hdmi_info(struct seq_file *m, | |
2699 | struct intel_connector *intel_connector) | |
2700 | { | |
2701 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
2702 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
2703 | ||
2704 | seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : | |
2705 | "no"); | |
2706 | } | |
2707 | ||
2708 | static void intel_lvds_info(struct seq_file *m, | |
2709 | struct intel_connector *intel_connector) | |
2710 | { | |
2711 | intel_panel_info(m, &intel_connector->panel); | |
2712 | } | |
2713 | ||
2714 | static void intel_connector_info(struct seq_file *m, | |
2715 | struct drm_connector *connector) | |
2716 | { | |
2717 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
2718 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
f103fc7d | 2719 | struct drm_display_mode *mode; |
53f5e3ca JB |
2720 | |
2721 | seq_printf(m, "connector %d: type %s, status: %s\n", | |
c23cc417 | 2722 | connector->base.id, connector->name, |
53f5e3ca JB |
2723 | drm_get_connector_status_name(connector->status)); |
2724 | if (connector->status == connector_status_connected) { | |
2725 | seq_printf(m, "\tname: %s\n", connector->display_info.name); | |
2726 | seq_printf(m, "\tphysical dimensions: %dx%dmm\n", | |
2727 | connector->display_info.width_mm, | |
2728 | connector->display_info.height_mm); | |
2729 | seq_printf(m, "\tsubpixel order: %s\n", | |
2730 | drm_get_subpixel_order_name(connector->display_info.subpixel_order)); | |
2731 | seq_printf(m, "\tCEA rev: %d\n", | |
2732 | connector->display_info.cea_rev); | |
2733 | } | |
36cd7444 DA |
2734 | if (intel_encoder) { |
2735 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
2736 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
2737 | intel_dp_info(m, intel_connector); | |
2738 | else if (intel_encoder->type == INTEL_OUTPUT_HDMI) | |
2739 | intel_hdmi_info(m, intel_connector); | |
2740 | else if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
2741 | intel_lvds_info(m, intel_connector); | |
2742 | } | |
53f5e3ca | 2743 | |
f103fc7d JB |
2744 | seq_printf(m, "\tmodes:\n"); |
2745 | list_for_each_entry(mode, &connector->modes, head) | |
2746 | intel_seq_print_mode(m, 2, mode); | |
53f5e3ca JB |
2747 | } |
2748 | ||
065f2ec2 CW |
2749 | static bool cursor_active(struct drm_device *dev, int pipe) |
2750 | { | |
2751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2752 | u32 state; | |
2753 | ||
2754 | if (IS_845G(dev) || IS_I865G(dev)) | |
2755 | state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
065f2ec2 | 2756 | else |
5efb3e28 | 2757 | state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
065f2ec2 CW |
2758 | |
2759 | return state; | |
2760 | } | |
2761 | ||
2762 | static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) | |
2763 | { | |
2764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2765 | u32 pos; | |
2766 | ||
5efb3e28 | 2767 | pos = I915_READ(CURPOS(pipe)); |
065f2ec2 CW |
2768 | |
2769 | *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; | |
2770 | if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) | |
2771 | *x = -*x; | |
2772 | ||
2773 | *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; | |
2774 | if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) | |
2775 | *y = -*y; | |
2776 | ||
2777 | return cursor_active(dev, pipe); | |
2778 | } | |
2779 | ||
53f5e3ca JB |
2780 | static int i915_display_info(struct seq_file *m, void *unused) |
2781 | { | |
9f25d007 | 2782 | struct drm_info_node *node = m->private; |
53f5e3ca | 2783 | struct drm_device *dev = node->minor->dev; |
b0e5ddf3 | 2784 | struct drm_i915_private *dev_priv = dev->dev_private; |
065f2ec2 | 2785 | struct intel_crtc *crtc; |
53f5e3ca JB |
2786 | struct drm_connector *connector; |
2787 | ||
b0e5ddf3 | 2788 | intel_runtime_pm_get(dev_priv); |
53f5e3ca JB |
2789 | drm_modeset_lock_all(dev); |
2790 | seq_printf(m, "CRTC info\n"); | |
2791 | seq_printf(m, "---------\n"); | |
d3fcc808 | 2792 | for_each_intel_crtc(dev, crtc) { |
065f2ec2 | 2793 | bool active; |
f77076c9 | 2794 | struct intel_crtc_state *pipe_config; |
065f2ec2 | 2795 | int x, y; |
53f5e3ca | 2796 | |
f77076c9 ML |
2797 | pipe_config = to_intel_crtc_state(crtc->base.state); |
2798 | ||
57127efa | 2799 | seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", |
065f2ec2 | 2800 | crtc->base.base.id, pipe_name(crtc->pipe), |
f77076c9 ML |
2801 | yesno(pipe_config->base.active), |
2802 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
2803 | if (pipe_config->base.active) { | |
065f2ec2 CW |
2804 | intel_crtc_info(m, crtc); |
2805 | ||
a23dc658 | 2806 | active = cursor_position(dev, crtc->pipe, &x, &y); |
57127efa | 2807 | seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", |
4b0e333e | 2808 | yesno(crtc->cursor_base), |
3dd512fb MR |
2809 | x, y, crtc->base.cursor->state->crtc_w, |
2810 | crtc->base.cursor->state->crtc_h, | |
57127efa | 2811 | crtc->cursor_addr, yesno(active)); |
a23dc658 | 2812 | } |
cace841c DV |
2813 | |
2814 | seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", | |
2815 | yesno(!crtc->cpu_fifo_underrun_disabled), | |
2816 | yesno(!crtc->pch_fifo_underrun_disabled)); | |
53f5e3ca JB |
2817 | } |
2818 | ||
2819 | seq_printf(m, "\n"); | |
2820 | seq_printf(m, "Connector info\n"); | |
2821 | seq_printf(m, "--------------\n"); | |
2822 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2823 | intel_connector_info(m, connector); | |
2824 | } | |
2825 | drm_modeset_unlock_all(dev); | |
b0e5ddf3 | 2826 | intel_runtime_pm_put(dev_priv); |
53f5e3ca JB |
2827 | |
2828 | return 0; | |
2829 | } | |
2830 | ||
e04934cf BW |
2831 | static int i915_semaphore_status(struct seq_file *m, void *unused) |
2832 | { | |
2833 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2834 | struct drm_device *dev = node->minor->dev; | |
2835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2836 | struct intel_engine_cs *ring; | |
2837 | int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
2838 | int i, j, ret; | |
2839 | ||
2840 | if (!i915_semaphore_is_enabled(dev)) { | |
2841 | seq_puts(m, "Semaphores are disabled\n"); | |
2842 | return 0; | |
2843 | } | |
2844 | ||
2845 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
2846 | if (ret) | |
2847 | return ret; | |
03872064 | 2848 | intel_runtime_pm_get(dev_priv); |
e04934cf BW |
2849 | |
2850 | if (IS_BROADWELL(dev)) { | |
2851 | struct page *page; | |
2852 | uint64_t *seqno; | |
2853 | ||
2854 | page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); | |
2855 | ||
2856 | seqno = (uint64_t *)kmap_atomic(page); | |
2857 | for_each_ring(ring, dev_priv, i) { | |
2858 | uint64_t offset; | |
2859 | ||
2860 | seq_printf(m, "%s\n", ring->name); | |
2861 | ||
2862 | seq_puts(m, " Last signal:"); | |
2863 | for (j = 0; j < num_rings; j++) { | |
2864 | offset = i * I915_NUM_RINGS + j; | |
2865 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
2866 | seqno[offset], offset * 8); | |
2867 | } | |
2868 | seq_putc(m, '\n'); | |
2869 | ||
2870 | seq_puts(m, " Last wait: "); | |
2871 | for (j = 0; j < num_rings; j++) { | |
2872 | offset = i + (j * I915_NUM_RINGS); | |
2873 | seq_printf(m, "0x%08llx (0x%02llx) ", | |
2874 | seqno[offset], offset * 8); | |
2875 | } | |
2876 | seq_putc(m, '\n'); | |
2877 | ||
2878 | } | |
2879 | kunmap_atomic(seqno); | |
2880 | } else { | |
2881 | seq_puts(m, " Last signal:"); | |
2882 | for_each_ring(ring, dev_priv, i) | |
2883 | for (j = 0; j < num_rings; j++) | |
2884 | seq_printf(m, "0x%08x\n", | |
2885 | I915_READ(ring->semaphore.mbox.signal[j])); | |
2886 | seq_putc(m, '\n'); | |
2887 | } | |
2888 | ||
2889 | seq_puts(m, "\nSync seqno:\n"); | |
2890 | for_each_ring(ring, dev_priv, i) { | |
2891 | for (j = 0; j < num_rings; j++) { | |
2892 | seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); | |
2893 | } | |
2894 | seq_putc(m, '\n'); | |
2895 | } | |
2896 | seq_putc(m, '\n'); | |
2897 | ||
03872064 | 2898 | intel_runtime_pm_put(dev_priv); |
e04934cf BW |
2899 | mutex_unlock(&dev->struct_mutex); |
2900 | return 0; | |
2901 | } | |
2902 | ||
728e29d7 DV |
2903 | static int i915_shared_dplls_info(struct seq_file *m, void *unused) |
2904 | { | |
2905 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2906 | struct drm_device *dev = node->minor->dev; | |
2907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2908 | int i; | |
2909 | ||
2910 | drm_modeset_lock_all(dev); | |
2911 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
2912 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
2913 | ||
2914 | seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); | |
1e6f2ddc | 2915 | seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n", |
3e369b76 | 2916 | pll->config.crtc_mask, pll->active, yesno(pll->on)); |
728e29d7 | 2917 | seq_printf(m, " tracked hardware state:\n"); |
3e369b76 ACO |
2918 | seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); |
2919 | seq_printf(m, " dpll_md: 0x%08x\n", | |
2920 | pll->config.hw_state.dpll_md); | |
2921 | seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); | |
2922 | seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); | |
2923 | seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); | |
728e29d7 DV |
2924 | } |
2925 | drm_modeset_unlock_all(dev); | |
2926 | ||
2927 | return 0; | |
2928 | } | |
2929 | ||
1ed1ef9d | 2930 | static int i915_wa_registers(struct seq_file *m, void *unused) |
888b5995 AS |
2931 | { |
2932 | int i; | |
2933 | int ret; | |
2934 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2935 | struct drm_device *dev = node->minor->dev; | |
2936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2937 | ||
888b5995 AS |
2938 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
2939 | if (ret) | |
2940 | return ret; | |
2941 | ||
2942 | intel_runtime_pm_get(dev_priv); | |
2943 | ||
7225342a MK |
2944 | seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count); |
2945 | for (i = 0; i < dev_priv->workarounds.count; ++i) { | |
2fa60f6d MK |
2946 | u32 addr, mask, value, read; |
2947 | bool ok; | |
888b5995 | 2948 | |
7225342a MK |
2949 | addr = dev_priv->workarounds.reg[i].addr; |
2950 | mask = dev_priv->workarounds.reg[i].mask; | |
2fa60f6d MK |
2951 | value = dev_priv->workarounds.reg[i].value; |
2952 | read = I915_READ(addr); | |
2953 | ok = (value & mask) == (read & mask); | |
2954 | seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", | |
2955 | addr, value, mask, read, ok ? "OK" : "FAIL"); | |
888b5995 AS |
2956 | } |
2957 | ||
2958 | intel_runtime_pm_put(dev_priv); | |
2959 | mutex_unlock(&dev->struct_mutex); | |
2960 | ||
2961 | return 0; | |
2962 | } | |
2963 | ||
c5511e44 DL |
2964 | static int i915_ddb_info(struct seq_file *m, void *unused) |
2965 | { | |
2966 | struct drm_info_node *node = m->private; | |
2967 | struct drm_device *dev = node->minor->dev; | |
2968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2969 | struct skl_ddb_allocation *ddb; | |
2970 | struct skl_ddb_entry *entry; | |
2971 | enum pipe pipe; | |
2972 | int plane; | |
2973 | ||
2fcffe19 DL |
2974 | if (INTEL_INFO(dev)->gen < 9) |
2975 | return 0; | |
2976 | ||
c5511e44 DL |
2977 | drm_modeset_lock_all(dev); |
2978 | ||
2979 | ddb = &dev_priv->wm.skl_hw.ddb; | |
2980 | ||
2981 | seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); | |
2982 | ||
2983 | for_each_pipe(dev_priv, pipe) { | |
2984 | seq_printf(m, "Pipe %c\n", pipe_name(pipe)); | |
2985 | ||
dd740780 | 2986 | for_each_plane(dev_priv, pipe, plane) { |
c5511e44 DL |
2987 | entry = &ddb->plane[pipe][plane]; |
2988 | seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, | |
2989 | entry->start, entry->end, | |
2990 | skl_ddb_entry_size(entry)); | |
2991 | } | |
2992 | ||
2993 | entry = &ddb->cursor[pipe]; | |
2994 | seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, | |
2995 | entry->end, skl_ddb_entry_size(entry)); | |
2996 | } | |
2997 | ||
2998 | drm_modeset_unlock_all(dev); | |
2999 | ||
3000 | return 0; | |
3001 | } | |
3002 | ||
a54746e3 VK |
3003 | static void drrs_status_per_crtc(struct seq_file *m, |
3004 | struct drm_device *dev, struct intel_crtc *intel_crtc) | |
3005 | { | |
3006 | struct intel_encoder *intel_encoder; | |
3007 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3008 | struct i915_drrs *drrs = &dev_priv->drrs; | |
3009 | int vrefresh = 0; | |
3010 | ||
3011 | for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { | |
3012 | /* Encoder connected on this CRTC */ | |
3013 | switch (intel_encoder->type) { | |
3014 | case INTEL_OUTPUT_EDP: | |
3015 | seq_puts(m, "eDP:\n"); | |
3016 | break; | |
3017 | case INTEL_OUTPUT_DSI: | |
3018 | seq_puts(m, "DSI:\n"); | |
3019 | break; | |
3020 | case INTEL_OUTPUT_HDMI: | |
3021 | seq_puts(m, "HDMI:\n"); | |
3022 | break; | |
3023 | case INTEL_OUTPUT_DISPLAYPORT: | |
3024 | seq_puts(m, "DP:\n"); | |
3025 | break; | |
3026 | default: | |
3027 | seq_printf(m, "Other encoder (id=%d).\n", | |
3028 | intel_encoder->type); | |
3029 | return; | |
3030 | } | |
3031 | } | |
3032 | ||
3033 | if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) | |
3034 | seq_puts(m, "\tVBT: DRRS_type: Static"); | |
3035 | else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) | |
3036 | seq_puts(m, "\tVBT: DRRS_type: Seamless"); | |
3037 | else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) | |
3038 | seq_puts(m, "\tVBT: DRRS_type: None"); | |
3039 | else | |
3040 | seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); | |
3041 | ||
3042 | seq_puts(m, "\n\n"); | |
3043 | ||
f77076c9 | 3044 | if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { |
a54746e3 VK |
3045 | struct intel_panel *panel; |
3046 | ||
3047 | mutex_lock(&drrs->mutex); | |
3048 | /* DRRS Supported */ | |
3049 | seq_puts(m, "\tDRRS Supported: Yes\n"); | |
3050 | ||
3051 | /* disable_drrs() will make drrs->dp NULL */ | |
3052 | if (!drrs->dp) { | |
3053 | seq_puts(m, "Idleness DRRS: Disabled"); | |
3054 | mutex_unlock(&drrs->mutex); | |
3055 | return; | |
3056 | } | |
3057 | ||
3058 | panel = &drrs->dp->attached_connector->panel; | |
3059 | seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", | |
3060 | drrs->busy_frontbuffer_bits); | |
3061 | ||
3062 | seq_puts(m, "\n\t\t"); | |
3063 | if (drrs->refresh_rate_type == DRRS_HIGH_RR) { | |
3064 | seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); | |
3065 | vrefresh = panel->fixed_mode->vrefresh; | |
3066 | } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { | |
3067 | seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); | |
3068 | vrefresh = panel->downclock_mode->vrefresh; | |
3069 | } else { | |
3070 | seq_printf(m, "DRRS_State: Unknown(%d)\n", | |
3071 | drrs->refresh_rate_type); | |
3072 | mutex_unlock(&drrs->mutex); | |
3073 | return; | |
3074 | } | |
3075 | seq_printf(m, "\t\tVrefresh: %d", vrefresh); | |
3076 | ||
3077 | seq_puts(m, "\n\t\t"); | |
3078 | mutex_unlock(&drrs->mutex); | |
3079 | } else { | |
3080 | /* DRRS not supported. Print the VBT parameter*/ | |
3081 | seq_puts(m, "\tDRRS Supported : No"); | |
3082 | } | |
3083 | seq_puts(m, "\n"); | |
3084 | } | |
3085 | ||
3086 | static int i915_drrs_status(struct seq_file *m, void *unused) | |
3087 | { | |
3088 | struct drm_info_node *node = m->private; | |
3089 | struct drm_device *dev = node->minor->dev; | |
3090 | struct intel_crtc *intel_crtc; | |
3091 | int active_crtc_cnt = 0; | |
3092 | ||
3093 | for_each_intel_crtc(dev, intel_crtc) { | |
3094 | drm_modeset_lock(&intel_crtc->base.mutex, NULL); | |
3095 | ||
f77076c9 | 3096 | if (intel_crtc->base.state->active) { |
a54746e3 VK |
3097 | active_crtc_cnt++; |
3098 | seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); | |
3099 | ||
3100 | drrs_status_per_crtc(m, dev, intel_crtc); | |
3101 | } | |
3102 | ||
3103 | drm_modeset_unlock(&intel_crtc->base.mutex); | |
3104 | } | |
3105 | ||
3106 | if (!active_crtc_cnt) | |
3107 | seq_puts(m, "No active crtc found\n"); | |
3108 | ||
3109 | return 0; | |
3110 | } | |
3111 | ||
07144428 DL |
3112 | struct pipe_crc_info { |
3113 | const char *name; | |
3114 | struct drm_device *dev; | |
3115 | enum pipe pipe; | |
3116 | }; | |
3117 | ||
11bed958 DA |
3118 | static int i915_dp_mst_info(struct seq_file *m, void *unused) |
3119 | { | |
3120 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
3121 | struct drm_device *dev = node->minor->dev; | |
3122 | struct drm_encoder *encoder; | |
3123 | struct intel_encoder *intel_encoder; | |
3124 | struct intel_digital_port *intel_dig_port; | |
3125 | drm_modeset_lock_all(dev); | |
3126 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
3127 | intel_encoder = to_intel_encoder(encoder); | |
3128 | if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) | |
3129 | continue; | |
3130 | intel_dig_port = enc_to_dig_port(encoder); | |
3131 | if (!intel_dig_port->dp.can_mst) | |
3132 | continue; | |
3133 | ||
3134 | drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); | |
3135 | } | |
3136 | drm_modeset_unlock_all(dev); | |
3137 | return 0; | |
3138 | } | |
3139 | ||
07144428 DL |
3140 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
3141 | { | |
be5c7a90 DL |
3142 | struct pipe_crc_info *info = inode->i_private; |
3143 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3144 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3145 | ||
7eb1c496 DV |
3146 | if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) |
3147 | return -ENODEV; | |
3148 | ||
d538bbdf DL |
3149 | spin_lock_irq(&pipe_crc->lock); |
3150 | ||
3151 | if (pipe_crc->opened) { | |
3152 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 DL |
3153 | return -EBUSY; /* already open */ |
3154 | } | |
3155 | ||
d538bbdf | 3156 | pipe_crc->opened = true; |
07144428 DL |
3157 | filep->private_data = inode->i_private; |
3158 | ||
d538bbdf DL |
3159 | spin_unlock_irq(&pipe_crc->lock); |
3160 | ||
07144428 DL |
3161 | return 0; |
3162 | } | |
3163 | ||
3164 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
3165 | { | |
be5c7a90 DL |
3166 | struct pipe_crc_info *info = inode->i_private; |
3167 | struct drm_i915_private *dev_priv = info->dev->dev_private; | |
3168 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3169 | ||
d538bbdf DL |
3170 | spin_lock_irq(&pipe_crc->lock); |
3171 | pipe_crc->opened = false; | |
3172 | spin_unlock_irq(&pipe_crc->lock); | |
be5c7a90 | 3173 | |
07144428 DL |
3174 | return 0; |
3175 | } | |
3176 | ||
3177 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
3178 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
3179 | /* account for \'0' */ | |
3180 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
3181 | ||
3182 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
8bf1e9f1 | 3183 | { |
d538bbdf DL |
3184 | assert_spin_locked(&pipe_crc->lock); |
3185 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
3186 | INTEL_PIPE_CRC_ENTRIES_NR); | |
07144428 DL |
3187 | } |
3188 | ||
3189 | static ssize_t | |
3190 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
3191 | loff_t *pos) | |
3192 | { | |
3193 | struct pipe_crc_info *info = filep->private_data; | |
3194 | struct drm_device *dev = info->dev; | |
3195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3196 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
3197 | char buf[PIPE_CRC_BUFFER_LEN]; | |
9ad6d99f | 3198 | int n_entries; |
07144428 DL |
3199 | ssize_t bytes_read; |
3200 | ||
3201 | /* | |
3202 | * Don't allow user space to provide buffers not big enough to hold | |
3203 | * a line of data. | |
3204 | */ | |
3205 | if (count < PIPE_CRC_LINE_LEN) | |
3206 | return -EINVAL; | |
3207 | ||
3208 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
8bf1e9f1 | 3209 | return 0; |
07144428 DL |
3210 | |
3211 | /* nothing to read */ | |
d538bbdf | 3212 | spin_lock_irq(&pipe_crc->lock); |
07144428 | 3213 | while (pipe_crc_data_count(pipe_crc) == 0) { |
d538bbdf DL |
3214 | int ret; |
3215 | ||
3216 | if (filep->f_flags & O_NONBLOCK) { | |
3217 | spin_unlock_irq(&pipe_crc->lock); | |
07144428 | 3218 | return -EAGAIN; |
d538bbdf | 3219 | } |
07144428 | 3220 | |
d538bbdf DL |
3221 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, |
3222 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
3223 | if (ret) { | |
3224 | spin_unlock_irq(&pipe_crc->lock); | |
3225 | return ret; | |
3226 | } | |
8bf1e9f1 SH |
3227 | } |
3228 | ||
07144428 | 3229 | /* We now have one or more entries to read */ |
9ad6d99f | 3230 | n_entries = count / PIPE_CRC_LINE_LEN; |
d538bbdf | 3231 | |
07144428 | 3232 | bytes_read = 0; |
9ad6d99f VS |
3233 | while (n_entries > 0) { |
3234 | struct intel_pipe_crc_entry *entry = | |
3235 | &pipe_crc->entries[pipe_crc->tail]; | |
07144428 | 3236 | int ret; |
8bf1e9f1 | 3237 | |
9ad6d99f VS |
3238 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
3239 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
3240 | break; | |
3241 | ||
3242 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
3243 | pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
3244 | ||
07144428 DL |
3245 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, |
3246 | "%8u %8x %8x %8x %8x %8x\n", | |
3247 | entry->frame, entry->crc[0], | |
3248 | entry->crc[1], entry->crc[2], | |
3249 | entry->crc[3], entry->crc[4]); | |
3250 | ||
9ad6d99f VS |
3251 | spin_unlock_irq(&pipe_crc->lock); |
3252 | ||
3253 | ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); | |
07144428 DL |
3254 | if (ret == PIPE_CRC_LINE_LEN) |
3255 | return -EFAULT; | |
b2c88f5b | 3256 | |
9ad6d99f VS |
3257 | user_buf += PIPE_CRC_LINE_LEN; |
3258 | n_entries--; | |
3259 | ||
3260 | spin_lock_irq(&pipe_crc->lock); | |
3261 | } | |
8bf1e9f1 | 3262 | |
d538bbdf DL |
3263 | spin_unlock_irq(&pipe_crc->lock); |
3264 | ||
07144428 DL |
3265 | return bytes_read; |
3266 | } | |
3267 | ||
3268 | static const struct file_operations i915_pipe_crc_fops = { | |
3269 | .owner = THIS_MODULE, | |
3270 | .open = i915_pipe_crc_open, | |
3271 | .read = i915_pipe_crc_read, | |
3272 | .release = i915_pipe_crc_release, | |
3273 | }; | |
3274 | ||
3275 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
3276 | { | |
3277 | .name = "i915_pipe_A_crc", | |
3278 | .pipe = PIPE_A, | |
3279 | }, | |
3280 | { | |
3281 | .name = "i915_pipe_B_crc", | |
3282 | .pipe = PIPE_B, | |
3283 | }, | |
3284 | { | |
3285 | .name = "i915_pipe_C_crc", | |
3286 | .pipe = PIPE_C, | |
3287 | }, | |
3288 | }; | |
3289 | ||
3290 | static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, | |
3291 | enum pipe pipe) | |
3292 | { | |
3293 | struct drm_device *dev = minor->dev; | |
3294 | struct dentry *ent; | |
3295 | struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; | |
3296 | ||
3297 | info->dev = dev; | |
3298 | ent = debugfs_create_file(info->name, S_IRUGO, root, info, | |
3299 | &i915_pipe_crc_fops); | |
f3c5fe97 WY |
3300 | if (!ent) |
3301 | return -ENOMEM; | |
07144428 DL |
3302 | |
3303 | return drm_add_fake_info_node(minor, ent, info); | |
8bf1e9f1 SH |
3304 | } |
3305 | ||
e8dfcf78 | 3306 | static const char * const pipe_crc_sources[] = { |
926321d5 DV |
3307 | "none", |
3308 | "plane1", | |
3309 | "plane2", | |
3310 | "pf", | |
5b3a856b | 3311 | "pipe", |
3d099a05 DV |
3312 | "TV", |
3313 | "DP-B", | |
3314 | "DP-C", | |
3315 | "DP-D", | |
46a19188 | 3316 | "auto", |
926321d5 DV |
3317 | }; |
3318 | ||
3319 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
3320 | { | |
3321 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
3322 | return pipe_crc_sources[source]; | |
3323 | } | |
3324 | ||
bd9db02f | 3325 | static int display_crc_ctl_show(struct seq_file *m, void *data) |
926321d5 DV |
3326 | { |
3327 | struct drm_device *dev = m->private; | |
3328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3329 | int i; | |
3330 | ||
3331 | for (i = 0; i < I915_MAX_PIPES; i++) | |
3332 | seq_printf(m, "%c %s\n", pipe_name(i), | |
3333 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
3334 | ||
3335 | return 0; | |
3336 | } | |
3337 | ||
bd9db02f | 3338 | static int display_crc_ctl_open(struct inode *inode, struct file *file) |
926321d5 DV |
3339 | { |
3340 | struct drm_device *dev = inode->i_private; | |
3341 | ||
bd9db02f | 3342 | return single_open(file, display_crc_ctl_show, dev); |
926321d5 DV |
3343 | } |
3344 | ||
46a19188 | 3345 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
52f843f6 DV |
3346 | uint32_t *val) |
3347 | { | |
46a19188 DV |
3348 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3349 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3350 | ||
3351 | switch (*source) { | |
52f843f6 DV |
3352 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3353 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
3354 | break; | |
3355 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3356 | *val = 0; | |
3357 | break; | |
3358 | default: | |
3359 | return -EINVAL; | |
3360 | } | |
3361 | ||
3362 | return 0; | |
3363 | } | |
3364 | ||
46a19188 DV |
3365 | static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, |
3366 | enum intel_pipe_crc_source *source) | |
3367 | { | |
3368 | struct intel_encoder *encoder; | |
3369 | struct intel_crtc *crtc; | |
26756809 | 3370 | struct intel_digital_port *dig_port; |
46a19188 DV |
3371 | int ret = 0; |
3372 | ||
3373 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3374 | ||
6e9f798d | 3375 | drm_modeset_lock_all(dev); |
b2784e15 | 3376 | for_each_intel_encoder(dev, encoder) { |
46a19188 DV |
3377 | if (!encoder->base.crtc) |
3378 | continue; | |
3379 | ||
3380 | crtc = to_intel_crtc(encoder->base.crtc); | |
3381 | ||
3382 | if (crtc->pipe != pipe) | |
3383 | continue; | |
3384 | ||
3385 | switch (encoder->type) { | |
3386 | case INTEL_OUTPUT_TVOUT: | |
3387 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
3388 | break; | |
3389 | case INTEL_OUTPUT_DISPLAYPORT: | |
3390 | case INTEL_OUTPUT_EDP: | |
26756809 DV |
3391 | dig_port = enc_to_dig_port(&encoder->base); |
3392 | switch (dig_port->port) { | |
3393 | case PORT_B: | |
3394 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
3395 | break; | |
3396 | case PORT_C: | |
3397 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
3398 | break; | |
3399 | case PORT_D: | |
3400 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
3401 | break; | |
3402 | default: | |
3403 | WARN(1, "nonexisting DP port %c\n", | |
3404 | port_name(dig_port->port)); | |
3405 | break; | |
3406 | } | |
46a19188 | 3407 | break; |
6847d71b PZ |
3408 | default: |
3409 | break; | |
46a19188 DV |
3410 | } |
3411 | } | |
6e9f798d | 3412 | drm_modeset_unlock_all(dev); |
46a19188 DV |
3413 | |
3414 | return ret; | |
3415 | } | |
3416 | ||
3417 | static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, | |
3418 | enum pipe pipe, | |
3419 | enum intel_pipe_crc_source *source, | |
7ac0129b DV |
3420 | uint32_t *val) |
3421 | { | |
8d2f24ca DV |
3422 | struct drm_i915_private *dev_priv = dev->dev_private; |
3423 | bool need_stable_symbols = false; | |
3424 | ||
46a19188 DV |
3425 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3426 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3427 | if (ret) | |
3428 | return ret; | |
3429 | } | |
3430 | ||
3431 | switch (*source) { | |
7ac0129b DV |
3432 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3433 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
3434 | break; | |
3435 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3436 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
8d2f24ca | 3437 | need_stable_symbols = true; |
7ac0129b DV |
3438 | break; |
3439 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3440 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
8d2f24ca | 3441 | need_stable_symbols = true; |
7ac0129b | 3442 | break; |
2be57922 VS |
3443 | case INTEL_PIPE_CRC_SOURCE_DP_D: |
3444 | if (!IS_CHERRYVIEW(dev)) | |
3445 | return -EINVAL; | |
3446 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
3447 | need_stable_symbols = true; | |
3448 | break; | |
7ac0129b DV |
3449 | case INTEL_PIPE_CRC_SOURCE_NONE: |
3450 | *val = 0; | |
3451 | break; | |
3452 | default: | |
3453 | return -EINVAL; | |
3454 | } | |
3455 | ||
8d2f24ca DV |
3456 | /* |
3457 | * When the pipe CRC tap point is after the transcoders we need | |
3458 | * to tweak symbol-level features to produce a deterministic series of | |
3459 | * symbols for a given frame. We need to reset those features only once | |
3460 | * a frame (instead of every nth symbol): | |
3461 | * - DC-balance: used to ensure a better clock recovery from the data | |
3462 | * link (SDVO) | |
3463 | * - DisplayPort scrambling: used for EMI reduction | |
3464 | */ | |
3465 | if (need_stable_symbols) { | |
3466 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3467 | ||
8d2f24ca | 3468 | tmp |= DC_BALANCE_RESET_VLV; |
eb736679 VS |
3469 | switch (pipe) { |
3470 | case PIPE_A: | |
8d2f24ca | 3471 | tmp |= PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3472 | break; |
3473 | case PIPE_B: | |
8d2f24ca | 3474 | tmp |= PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3475 | break; |
3476 | case PIPE_C: | |
3477 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
3478 | break; | |
3479 | default: | |
3480 | return -EINVAL; | |
3481 | } | |
8d2f24ca DV |
3482 | I915_WRITE(PORT_DFT2_G4X, tmp); |
3483 | } | |
3484 | ||
7ac0129b DV |
3485 | return 0; |
3486 | } | |
3487 | ||
4b79ebf7 | 3488 | static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, |
46a19188 DV |
3489 | enum pipe pipe, |
3490 | enum intel_pipe_crc_source *source, | |
4b79ebf7 DV |
3491 | uint32_t *val) |
3492 | { | |
84093603 DV |
3493 | struct drm_i915_private *dev_priv = dev->dev_private; |
3494 | bool need_stable_symbols = false; | |
3495 | ||
46a19188 DV |
3496 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { |
3497 | int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); | |
3498 | if (ret) | |
3499 | return ret; | |
3500 | } | |
3501 | ||
3502 | switch (*source) { | |
4b79ebf7 DV |
3503 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3504 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
3505 | break; | |
3506 | case INTEL_PIPE_CRC_SOURCE_TV: | |
3507 | if (!SUPPORTS_TV(dev)) | |
3508 | return -EINVAL; | |
3509 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
3510 | break; | |
3511 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
3512 | if (!IS_G4X(dev)) | |
3513 | return -EINVAL; | |
3514 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
84093603 | 3515 | need_stable_symbols = true; |
4b79ebf7 DV |
3516 | break; |
3517 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
3518 | if (!IS_G4X(dev)) | |
3519 | return -EINVAL; | |
3520 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
84093603 | 3521 | need_stable_symbols = true; |
4b79ebf7 DV |
3522 | break; |
3523 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
3524 | if (!IS_G4X(dev)) | |
3525 | return -EINVAL; | |
3526 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
84093603 | 3527 | need_stable_symbols = true; |
4b79ebf7 DV |
3528 | break; |
3529 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
3530 | *val = 0; | |
3531 | break; | |
3532 | default: | |
3533 | return -EINVAL; | |
3534 | } | |
3535 | ||
84093603 DV |
3536 | /* |
3537 | * When the pipe CRC tap point is after the transcoders we need | |
3538 | * to tweak symbol-level features to produce a deterministic series of | |
3539 | * symbols for a given frame. We need to reset those features only once | |
3540 | * a frame (instead of every nth symbol): | |
3541 | * - DC-balance: used to ensure a better clock recovery from the data | |
3542 | * link (SDVO) | |
3543 | * - DisplayPort scrambling: used for EMI reduction | |
3544 | */ | |
3545 | if (need_stable_symbols) { | |
3546 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3547 | ||
3548 | WARN_ON(!IS_G4X(dev)); | |
3549 | ||
3550 | I915_WRITE(PORT_DFT_I9XX, | |
3551 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
3552 | ||
3553 | if (pipe == PIPE_A) | |
3554 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
3555 | else | |
3556 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
3557 | ||
3558 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3559 | } | |
3560 | ||
4b79ebf7 DV |
3561 | return 0; |
3562 | } | |
3563 | ||
8d2f24ca DV |
3564 | static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, |
3565 | enum pipe pipe) | |
3566 | { | |
3567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3568 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3569 | ||
eb736679 VS |
3570 | switch (pipe) { |
3571 | case PIPE_A: | |
8d2f24ca | 3572 | tmp &= ~PIPE_A_SCRAMBLE_RESET; |
eb736679 VS |
3573 | break; |
3574 | case PIPE_B: | |
8d2f24ca | 3575 | tmp &= ~PIPE_B_SCRAMBLE_RESET; |
eb736679 VS |
3576 | break; |
3577 | case PIPE_C: | |
3578 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
3579 | break; | |
3580 | default: | |
3581 | return; | |
3582 | } | |
8d2f24ca DV |
3583 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) |
3584 | tmp &= ~DC_BALANCE_RESET_VLV; | |
3585 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3586 | ||
3587 | } | |
3588 | ||
84093603 DV |
3589 | static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, |
3590 | enum pipe pipe) | |
3591 | { | |
3592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3593 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
3594 | ||
3595 | if (pipe == PIPE_A) | |
3596 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
3597 | else | |
3598 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
3599 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
3600 | ||
3601 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
3602 | I915_WRITE(PORT_DFT_I9XX, | |
3603 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
3604 | } | |
3605 | } | |
3606 | ||
46a19188 | 3607 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, |
5b3a856b DV |
3608 | uint32_t *val) |
3609 | { | |
46a19188 DV |
3610 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3611 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
3612 | ||
3613 | switch (*source) { | |
5b3a856b DV |
3614 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3615 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
3616 | break; | |
3617 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3618 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
3619 | break; | |
5b3a856b DV |
3620 | case INTEL_PIPE_CRC_SOURCE_PIPE: |
3621 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
3622 | break; | |
3d099a05 | 3623 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3624 | *val = 0; |
3625 | break; | |
3d099a05 DV |
3626 | default: |
3627 | return -EINVAL; | |
5b3a856b DV |
3628 | } |
3629 | ||
3630 | return 0; | |
3631 | } | |
3632 | ||
fabf6e51 DV |
3633 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) |
3634 | { | |
3635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3636 | struct intel_crtc *crtc = | |
3637 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 3638 | struct intel_crtc_state *pipe_config; |
fabf6e51 DV |
3639 | |
3640 | drm_modeset_lock_all(dev); | |
f77076c9 ML |
3641 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3642 | ||
fabf6e51 DV |
3643 | /* |
3644 | * If we use the eDP transcoder we need to make sure that we don't | |
3645 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only | |
3646 | * relevant on hsw with pipe A when using the always-on power well | |
3647 | * routing. | |
3648 | */ | |
f77076c9 ML |
3649 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && |
3650 | !pipe_config->pch_pfit.enabled) { | |
3651 | bool active = pipe_config->base.active; | |
1b509259 | 3652 | |
f77076c9 | 3653 | if (active) { |
1b509259 | 3654 | intel_crtc_control(&crtc->base, false); |
f77076c9 ML |
3655 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3656 | } | |
1b509259 | 3657 | |
f77076c9 | 3658 | pipe_config->pch_pfit.force_thru = true; |
fabf6e51 DV |
3659 | |
3660 | intel_display_power_get(dev_priv, | |
3661 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); | |
3662 | ||
1b509259 ML |
3663 | if (active) |
3664 | intel_crtc_control(&crtc->base, true); | |
fabf6e51 DV |
3665 | } |
3666 | drm_modeset_unlock_all(dev); | |
3667 | } | |
3668 | ||
3669 | static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) | |
3670 | { | |
3671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3672 | struct intel_crtc *crtc = | |
3673 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); | |
f77076c9 | 3674 | struct intel_crtc_state *pipe_config; |
fabf6e51 DV |
3675 | |
3676 | drm_modeset_lock_all(dev); | |
3677 | /* | |
3678 | * If we use the eDP transcoder we need to make sure that we don't | |
3679 | * bypass the pfit, since otherwise the pipe CRC source won't work. Only | |
3680 | * relevant on hsw with pipe A when using the always-on power well | |
3681 | * routing. | |
3682 | */ | |
f77076c9 ML |
3683 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3684 | if (pipe_config->pch_pfit.force_thru) { | |
3685 | bool active = pipe_config->base.active; | |
fabf6e51 | 3686 | |
f77076c9 | 3687 | if (active) { |
1b509259 | 3688 | intel_crtc_control(&crtc->base, false); |
f77076c9 ML |
3689 | pipe_config = to_intel_crtc_state(crtc->base.state); |
3690 | } | |
fabf6e51 | 3691 | |
f77076c9 | 3692 | pipe_config->pch_pfit.force_thru = false; |
fabf6e51 DV |
3693 | |
3694 | intel_display_power_put(dev_priv, | |
3695 | POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); | |
1b509259 ML |
3696 | |
3697 | if (active) | |
3698 | intel_crtc_control(&crtc->base, true); | |
fabf6e51 DV |
3699 | } |
3700 | drm_modeset_unlock_all(dev); | |
3701 | } | |
3702 | ||
3703 | static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, | |
3704 | enum pipe pipe, | |
3705 | enum intel_pipe_crc_source *source, | |
5b3a856b DV |
3706 | uint32_t *val) |
3707 | { | |
46a19188 DV |
3708 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) |
3709 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
3710 | ||
3711 | switch (*source) { | |
5b3a856b DV |
3712 | case INTEL_PIPE_CRC_SOURCE_PLANE1: |
3713 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
3714 | break; | |
3715 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
3716 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
3717 | break; | |
3718 | case INTEL_PIPE_CRC_SOURCE_PF: | |
fabf6e51 DV |
3719 | if (IS_HASWELL(dev) && pipe == PIPE_A) |
3720 | hsw_trans_edp_pipe_A_crc_wa(dev); | |
3721 | ||
5b3a856b DV |
3722 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; |
3723 | break; | |
3d099a05 | 3724 | case INTEL_PIPE_CRC_SOURCE_NONE: |
5b3a856b DV |
3725 | *val = 0; |
3726 | break; | |
3d099a05 DV |
3727 | default: |
3728 | return -EINVAL; | |
5b3a856b DV |
3729 | } |
3730 | ||
3731 | return 0; | |
3732 | } | |
3733 | ||
926321d5 DV |
3734 | static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, |
3735 | enum intel_pipe_crc_source source) | |
3736 | { | |
3737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cc3da175 | 3738 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
8c740dce PZ |
3739 | struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, |
3740 | pipe)); | |
432f3342 | 3741 | u32 val = 0; /* shut up gcc */ |
5b3a856b | 3742 | int ret; |
926321d5 | 3743 | |
cc3da175 DL |
3744 | if (pipe_crc->source == source) |
3745 | return 0; | |
3746 | ||
ae676fcd DL |
3747 | /* forbid changing the source without going back to 'none' */ |
3748 | if (pipe_crc->source && source) | |
3749 | return -EINVAL; | |
3750 | ||
9d8b0588 DV |
3751 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) { |
3752 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); | |
3753 | return -EIO; | |
3754 | } | |
3755 | ||
52f843f6 | 3756 | if (IS_GEN2(dev)) |
46a19188 | 3757 | ret = i8xx_pipe_crc_ctl_reg(&source, &val); |
52f843f6 | 3758 | else if (INTEL_INFO(dev)->gen < 5) |
46a19188 | 3759 | ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
7ac0129b | 3760 | else if (IS_VALLEYVIEW(dev)) |
fabf6e51 | 3761 | ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
4b79ebf7 | 3762 | else if (IS_GEN5(dev) || IS_GEN6(dev)) |
46a19188 | 3763 | ret = ilk_pipe_crc_ctl_reg(&source, &val); |
5b3a856b | 3764 | else |
fabf6e51 | 3765 | ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); |
5b3a856b DV |
3766 | |
3767 | if (ret != 0) | |
3768 | return ret; | |
3769 | ||
4b584369 DL |
3770 | /* none -> real source transition */ |
3771 | if (source) { | |
4252fbc3 VS |
3772 | struct intel_pipe_crc_entry *entries; |
3773 | ||
7cd6ccff DL |
3774 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", |
3775 | pipe_name(pipe), pipe_crc_source_name(source)); | |
3776 | ||
3cf54b34 VS |
3777 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, |
3778 | sizeof(pipe_crc->entries[0]), | |
4252fbc3 VS |
3779 | GFP_KERNEL); |
3780 | if (!entries) | |
e5f75aca DL |
3781 | return -ENOMEM; |
3782 | ||
8c740dce PZ |
3783 | /* |
3784 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
3785 | * enabled and disabled dynamically based on package C states, | |
3786 | * user space can't make reliable use of the CRCs, so let's just | |
3787 | * completely disable it. | |
3788 | */ | |
3789 | hsw_disable_ips(crtc); | |
3790 | ||
d538bbdf | 3791 | spin_lock_irq(&pipe_crc->lock); |
64387b61 | 3792 | kfree(pipe_crc->entries); |
4252fbc3 | 3793 | pipe_crc->entries = entries; |
d538bbdf DL |
3794 | pipe_crc->head = 0; |
3795 | pipe_crc->tail = 0; | |
3796 | spin_unlock_irq(&pipe_crc->lock); | |
4b584369 DL |
3797 | } |
3798 | ||
cc3da175 | 3799 | pipe_crc->source = source; |
926321d5 | 3800 | |
926321d5 DV |
3801 | I915_WRITE(PIPE_CRC_CTL(pipe), val); |
3802 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
3803 | ||
e5f75aca DL |
3804 | /* real source -> none transition */ |
3805 | if (source == INTEL_PIPE_CRC_SOURCE_NONE) { | |
d538bbdf | 3806 | struct intel_pipe_crc_entry *entries; |
a33d7105 DV |
3807 | struct intel_crtc *crtc = |
3808 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
d538bbdf | 3809 | |
7cd6ccff DL |
3810 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", |
3811 | pipe_name(pipe)); | |
3812 | ||
a33d7105 | 3813 | drm_modeset_lock(&crtc->base.mutex, NULL); |
f77076c9 | 3814 | if (crtc->base.state->active) |
a33d7105 DV |
3815 | intel_wait_for_vblank(dev, pipe); |
3816 | drm_modeset_unlock(&crtc->base.mutex); | |
bcf17ab2 | 3817 | |
d538bbdf DL |
3818 | spin_lock_irq(&pipe_crc->lock); |
3819 | entries = pipe_crc->entries; | |
e5f75aca | 3820 | pipe_crc->entries = NULL; |
9ad6d99f VS |
3821 | pipe_crc->head = 0; |
3822 | pipe_crc->tail = 0; | |
d538bbdf DL |
3823 | spin_unlock_irq(&pipe_crc->lock); |
3824 | ||
3825 | kfree(entries); | |
84093603 DV |
3826 | |
3827 | if (IS_G4X(dev)) | |
3828 | g4x_undo_pipe_scramble_reset(dev, pipe); | |
8d2f24ca DV |
3829 | else if (IS_VALLEYVIEW(dev)) |
3830 | vlv_undo_pipe_scramble_reset(dev, pipe); | |
fabf6e51 DV |
3831 | else if (IS_HASWELL(dev) && pipe == PIPE_A) |
3832 | hsw_undo_trans_edp_pipe_A_crc_wa(dev); | |
8c740dce PZ |
3833 | |
3834 | hsw_enable_ips(crtc); | |
e5f75aca DL |
3835 | } |
3836 | ||
926321d5 DV |
3837 | return 0; |
3838 | } | |
3839 | ||
3840 | /* | |
3841 | * Parse pipe CRC command strings: | |
b94dec87 DL |
3842 | * command: wsp* object wsp+ name wsp+ source wsp* |
3843 | * object: 'pipe' | |
3844 | * name: (A | B | C) | |
926321d5 DV |
3845 | * source: (none | plane1 | plane2 | pf) |
3846 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
3847 | * | |
3848 | * eg.: | |
b94dec87 DL |
3849 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A |
3850 | * "pipe A none" -> Stop CRC | |
926321d5 | 3851 | */ |
bd9db02f | 3852 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) |
926321d5 DV |
3853 | { |
3854 | int n_words = 0; | |
3855 | ||
3856 | while (*buf) { | |
3857 | char *end; | |
3858 | ||
3859 | /* skip leading white space */ | |
3860 | buf = skip_spaces(buf); | |
3861 | if (!*buf) | |
3862 | break; /* end of buffer */ | |
3863 | ||
3864 | /* find end of word */ | |
3865 | for (end = buf; *end && !isspace(*end); end++) | |
3866 | ; | |
3867 | ||
3868 | if (n_words == max_words) { | |
3869 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
3870 | max_words); | |
3871 | return -EINVAL; /* ran out of words[] before bytes */ | |
3872 | } | |
3873 | ||
3874 | if (*end) | |
3875 | *end++ = '\0'; | |
3876 | words[n_words++] = buf; | |
3877 | buf = end; | |
3878 | } | |
3879 | ||
3880 | return n_words; | |
3881 | } | |
3882 | ||
b94dec87 DL |
3883 | enum intel_pipe_crc_object { |
3884 | PIPE_CRC_OBJECT_PIPE, | |
3885 | }; | |
3886 | ||
e8dfcf78 | 3887 | static const char * const pipe_crc_objects[] = { |
b94dec87 DL |
3888 | "pipe", |
3889 | }; | |
3890 | ||
3891 | static int | |
bd9db02f | 3892 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) |
b94dec87 DL |
3893 | { |
3894 | int i; | |
3895 | ||
3896 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
3897 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
bd9db02f | 3898 | *o = i; |
b94dec87 DL |
3899 | return 0; |
3900 | } | |
3901 | ||
3902 | return -EINVAL; | |
3903 | } | |
3904 | ||
bd9db02f | 3905 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) |
926321d5 DV |
3906 | { |
3907 | const char name = buf[0]; | |
3908 | ||
3909 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
3910 | return -EINVAL; | |
3911 | ||
3912 | *pipe = name - 'A'; | |
3913 | ||
3914 | return 0; | |
3915 | } | |
3916 | ||
3917 | static int | |
bd9db02f | 3918 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) |
926321d5 DV |
3919 | { |
3920 | int i; | |
3921 | ||
3922 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) | |
3923 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
bd9db02f | 3924 | *s = i; |
926321d5 DV |
3925 | return 0; |
3926 | } | |
3927 | ||
3928 | return -EINVAL; | |
3929 | } | |
3930 | ||
bd9db02f | 3931 | static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) |
926321d5 | 3932 | { |
b94dec87 | 3933 | #define N_WORDS 3 |
926321d5 | 3934 | int n_words; |
b94dec87 | 3935 | char *words[N_WORDS]; |
926321d5 | 3936 | enum pipe pipe; |
b94dec87 | 3937 | enum intel_pipe_crc_object object; |
926321d5 DV |
3938 | enum intel_pipe_crc_source source; |
3939 | ||
bd9db02f | 3940 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); |
b94dec87 DL |
3941 | if (n_words != N_WORDS) { |
3942 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
3943 | N_WORDS); | |
3944 | return -EINVAL; | |
3945 | } | |
3946 | ||
bd9db02f | 3947 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { |
b94dec87 | 3948 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); |
926321d5 DV |
3949 | return -EINVAL; |
3950 | } | |
3951 | ||
bd9db02f | 3952 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { |
b94dec87 | 3953 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); |
926321d5 DV |
3954 | return -EINVAL; |
3955 | } | |
3956 | ||
bd9db02f | 3957 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { |
b94dec87 | 3958 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); |
926321d5 DV |
3959 | return -EINVAL; |
3960 | } | |
3961 | ||
3962 | return pipe_crc_set_source(dev, pipe, source); | |
3963 | } | |
3964 | ||
bd9db02f DL |
3965 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, |
3966 | size_t len, loff_t *offp) | |
926321d5 DV |
3967 | { |
3968 | struct seq_file *m = file->private_data; | |
3969 | struct drm_device *dev = m->private; | |
3970 | char *tmpbuf; | |
3971 | int ret; | |
3972 | ||
3973 | if (len == 0) | |
3974 | return 0; | |
3975 | ||
3976 | if (len > PAGE_SIZE - 1) { | |
3977 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
3978 | PAGE_SIZE); | |
3979 | return -E2BIG; | |
3980 | } | |
3981 | ||
3982 | tmpbuf = kmalloc(len + 1, GFP_KERNEL); | |
3983 | if (!tmpbuf) | |
3984 | return -ENOMEM; | |
3985 | ||
3986 | if (copy_from_user(tmpbuf, ubuf, len)) { | |
3987 | ret = -EFAULT; | |
3988 | goto out; | |
3989 | } | |
3990 | tmpbuf[len] = '\0'; | |
3991 | ||
bd9db02f | 3992 | ret = display_crc_ctl_parse(dev, tmpbuf, len); |
926321d5 DV |
3993 | |
3994 | out: | |
3995 | kfree(tmpbuf); | |
3996 | if (ret < 0) | |
3997 | return ret; | |
3998 | ||
3999 | *offp += len; | |
4000 | return len; | |
4001 | } | |
4002 | ||
bd9db02f | 4003 | static const struct file_operations i915_display_crc_ctl_fops = { |
926321d5 | 4004 | .owner = THIS_MODULE, |
bd9db02f | 4005 | .open = display_crc_ctl_open, |
926321d5 DV |
4006 | .read = seq_read, |
4007 | .llseek = seq_lseek, | |
4008 | .release = single_release, | |
bd9db02f | 4009 | .write = display_crc_ctl_write |
926321d5 DV |
4010 | }; |
4011 | ||
eb3394fa TP |
4012 | static ssize_t i915_displayport_test_active_write(struct file *file, |
4013 | const char __user *ubuf, | |
4014 | size_t len, loff_t *offp) | |
4015 | { | |
4016 | char *input_buffer; | |
4017 | int status = 0; | |
4018 | struct seq_file *m; | |
4019 | struct drm_device *dev; | |
4020 | struct drm_connector *connector; | |
4021 | struct list_head *connector_list; | |
4022 | struct intel_dp *intel_dp; | |
4023 | int val = 0; | |
4024 | ||
4025 | m = file->private_data; | |
4026 | if (!m) { | |
4027 | status = -ENODEV; | |
4028 | return status; | |
4029 | } | |
4030 | dev = m->private; | |
4031 | ||
4032 | if (!dev) { | |
4033 | status = -ENODEV; | |
4034 | return status; | |
4035 | } | |
4036 | connector_list = &dev->mode_config.connector_list; | |
4037 | ||
4038 | if (len == 0) | |
4039 | return 0; | |
4040 | ||
4041 | input_buffer = kmalloc(len + 1, GFP_KERNEL); | |
4042 | if (!input_buffer) | |
4043 | return -ENOMEM; | |
4044 | ||
4045 | if (copy_from_user(input_buffer, ubuf, len)) { | |
4046 | status = -EFAULT; | |
4047 | goto out; | |
4048 | } | |
4049 | ||
4050 | input_buffer[len] = '\0'; | |
4051 | DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); | |
4052 | ||
4053 | list_for_each_entry(connector, connector_list, head) { | |
4054 | ||
4055 | if (connector->connector_type != | |
4056 | DRM_MODE_CONNECTOR_DisplayPort) | |
4057 | continue; | |
4058 | ||
4059 | if (connector->connector_type == | |
4060 | DRM_MODE_CONNECTOR_DisplayPort && | |
4061 | connector->status == connector_status_connected && | |
4062 | connector->encoder != NULL) { | |
4063 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4064 | status = kstrtoint(input_buffer, 10, &val); | |
4065 | if (status < 0) | |
4066 | goto out; | |
4067 | DRM_DEBUG_DRIVER("Got %d for test active\n", val); | |
4068 | /* To prevent erroneous activation of the compliance | |
4069 | * testing code, only accept an actual value of 1 here | |
4070 | */ | |
4071 | if (val == 1) | |
4072 | intel_dp->compliance_test_active = 1; | |
4073 | else | |
4074 | intel_dp->compliance_test_active = 0; | |
4075 | } | |
4076 | } | |
4077 | out: | |
4078 | kfree(input_buffer); | |
4079 | if (status < 0) | |
4080 | return status; | |
4081 | ||
4082 | *offp += len; | |
4083 | return len; | |
4084 | } | |
4085 | ||
4086 | static int i915_displayport_test_active_show(struct seq_file *m, void *data) | |
4087 | { | |
4088 | struct drm_device *dev = m->private; | |
4089 | struct drm_connector *connector; | |
4090 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4091 | struct intel_dp *intel_dp; | |
4092 | ||
4093 | if (!dev) | |
4094 | return -ENODEV; | |
4095 | ||
4096 | list_for_each_entry(connector, connector_list, head) { | |
4097 | ||
4098 | if (connector->connector_type != | |
4099 | DRM_MODE_CONNECTOR_DisplayPort) | |
4100 | continue; | |
4101 | ||
4102 | if (connector->status == connector_status_connected && | |
4103 | connector->encoder != NULL) { | |
4104 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4105 | if (intel_dp->compliance_test_active) | |
4106 | seq_puts(m, "1"); | |
4107 | else | |
4108 | seq_puts(m, "0"); | |
4109 | } else | |
4110 | seq_puts(m, "0"); | |
4111 | } | |
4112 | ||
4113 | return 0; | |
4114 | } | |
4115 | ||
4116 | static int i915_displayport_test_active_open(struct inode *inode, | |
4117 | struct file *file) | |
4118 | { | |
4119 | struct drm_device *dev = inode->i_private; | |
4120 | ||
4121 | return single_open(file, i915_displayport_test_active_show, dev); | |
4122 | } | |
4123 | ||
4124 | static const struct file_operations i915_displayport_test_active_fops = { | |
4125 | .owner = THIS_MODULE, | |
4126 | .open = i915_displayport_test_active_open, | |
4127 | .read = seq_read, | |
4128 | .llseek = seq_lseek, | |
4129 | .release = single_release, | |
4130 | .write = i915_displayport_test_active_write | |
4131 | }; | |
4132 | ||
4133 | static int i915_displayport_test_data_show(struct seq_file *m, void *data) | |
4134 | { | |
4135 | struct drm_device *dev = m->private; | |
4136 | struct drm_connector *connector; | |
4137 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4138 | struct intel_dp *intel_dp; | |
4139 | ||
4140 | if (!dev) | |
4141 | return -ENODEV; | |
4142 | ||
4143 | list_for_each_entry(connector, connector_list, head) { | |
4144 | ||
4145 | if (connector->connector_type != | |
4146 | DRM_MODE_CONNECTOR_DisplayPort) | |
4147 | continue; | |
4148 | ||
4149 | if (connector->status == connector_status_connected && | |
4150 | connector->encoder != NULL) { | |
4151 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4152 | seq_printf(m, "%lx", intel_dp->compliance_test_data); | |
4153 | } else | |
4154 | seq_puts(m, "0"); | |
4155 | } | |
4156 | ||
4157 | return 0; | |
4158 | } | |
4159 | static int i915_displayport_test_data_open(struct inode *inode, | |
4160 | struct file *file) | |
4161 | { | |
4162 | struct drm_device *dev = inode->i_private; | |
4163 | ||
4164 | return single_open(file, i915_displayport_test_data_show, dev); | |
4165 | } | |
4166 | ||
4167 | static const struct file_operations i915_displayport_test_data_fops = { | |
4168 | .owner = THIS_MODULE, | |
4169 | .open = i915_displayport_test_data_open, | |
4170 | .read = seq_read, | |
4171 | .llseek = seq_lseek, | |
4172 | .release = single_release | |
4173 | }; | |
4174 | ||
4175 | static int i915_displayport_test_type_show(struct seq_file *m, void *data) | |
4176 | { | |
4177 | struct drm_device *dev = m->private; | |
4178 | struct drm_connector *connector; | |
4179 | struct list_head *connector_list = &dev->mode_config.connector_list; | |
4180 | struct intel_dp *intel_dp; | |
4181 | ||
4182 | if (!dev) | |
4183 | return -ENODEV; | |
4184 | ||
4185 | list_for_each_entry(connector, connector_list, head) { | |
4186 | ||
4187 | if (connector->connector_type != | |
4188 | DRM_MODE_CONNECTOR_DisplayPort) | |
4189 | continue; | |
4190 | ||
4191 | if (connector->status == connector_status_connected && | |
4192 | connector->encoder != NULL) { | |
4193 | intel_dp = enc_to_intel_dp(connector->encoder); | |
4194 | seq_printf(m, "%02lx", intel_dp->compliance_test_type); | |
4195 | } else | |
4196 | seq_puts(m, "0"); | |
4197 | } | |
4198 | ||
4199 | return 0; | |
4200 | } | |
4201 | ||
4202 | static int i915_displayport_test_type_open(struct inode *inode, | |
4203 | struct file *file) | |
4204 | { | |
4205 | struct drm_device *dev = inode->i_private; | |
4206 | ||
4207 | return single_open(file, i915_displayport_test_type_show, dev); | |
4208 | } | |
4209 | ||
4210 | static const struct file_operations i915_displayport_test_type_fops = { | |
4211 | .owner = THIS_MODULE, | |
4212 | .open = i915_displayport_test_type_open, | |
4213 | .read = seq_read, | |
4214 | .llseek = seq_lseek, | |
4215 | .release = single_release | |
4216 | }; | |
4217 | ||
97e94b22 | 4218 | static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) |
369a1342 VS |
4219 | { |
4220 | struct drm_device *dev = m->private; | |
546c81fd | 4221 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
4222 | int level; |
4223 | ||
4224 | drm_modeset_lock_all(dev); | |
4225 | ||
4226 | for (level = 0; level < num_levels; level++) { | |
4227 | unsigned int latency = wm[level]; | |
4228 | ||
97e94b22 DL |
4229 | /* |
4230 | * - WM1+ latency values in 0.5us units | |
4231 | * - latencies are in us on gen9 | |
4232 | */ | |
4233 | if (INTEL_INFO(dev)->gen >= 9) | |
4234 | latency *= 10; | |
4235 | else if (level > 0) | |
369a1342 VS |
4236 | latency *= 5; |
4237 | ||
4238 | seq_printf(m, "WM%d %u (%u.%u usec)\n", | |
97e94b22 | 4239 | level, wm[level], latency / 10, latency % 10); |
369a1342 VS |
4240 | } |
4241 | ||
4242 | drm_modeset_unlock_all(dev); | |
4243 | } | |
4244 | ||
4245 | static int pri_wm_latency_show(struct seq_file *m, void *data) | |
4246 | { | |
4247 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4248 | struct drm_i915_private *dev_priv = dev->dev_private; |
4249 | const uint16_t *latencies; | |
4250 | ||
4251 | if (INTEL_INFO(dev)->gen >= 9) | |
4252 | latencies = dev_priv->wm.skl_latency; | |
4253 | else | |
4254 | latencies = to_i915(dev)->wm.pri_latency; | |
369a1342 | 4255 | |
97e94b22 | 4256 | wm_latency_show(m, latencies); |
369a1342 VS |
4257 | |
4258 | return 0; | |
4259 | } | |
4260 | ||
4261 | static int spr_wm_latency_show(struct seq_file *m, void *data) | |
4262 | { | |
4263 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4264 | struct drm_i915_private *dev_priv = dev->dev_private; |
4265 | const uint16_t *latencies; | |
4266 | ||
4267 | if (INTEL_INFO(dev)->gen >= 9) | |
4268 | latencies = dev_priv->wm.skl_latency; | |
4269 | else | |
4270 | latencies = to_i915(dev)->wm.spr_latency; | |
369a1342 | 4271 | |
97e94b22 | 4272 | wm_latency_show(m, latencies); |
369a1342 VS |
4273 | |
4274 | return 0; | |
4275 | } | |
4276 | ||
4277 | static int cur_wm_latency_show(struct seq_file *m, void *data) | |
4278 | { | |
4279 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4280 | struct drm_i915_private *dev_priv = dev->dev_private; |
4281 | const uint16_t *latencies; | |
4282 | ||
4283 | if (INTEL_INFO(dev)->gen >= 9) | |
4284 | latencies = dev_priv->wm.skl_latency; | |
4285 | else | |
4286 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4287 | |
97e94b22 | 4288 | wm_latency_show(m, latencies); |
369a1342 VS |
4289 | |
4290 | return 0; | |
4291 | } | |
4292 | ||
4293 | static int pri_wm_latency_open(struct inode *inode, struct file *file) | |
4294 | { | |
4295 | struct drm_device *dev = inode->i_private; | |
4296 | ||
9ad0257c | 4297 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4298 | return -ENODEV; |
4299 | ||
4300 | return single_open(file, pri_wm_latency_show, dev); | |
4301 | } | |
4302 | ||
4303 | static int spr_wm_latency_open(struct inode *inode, struct file *file) | |
4304 | { | |
4305 | struct drm_device *dev = inode->i_private; | |
4306 | ||
9ad0257c | 4307 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4308 | return -ENODEV; |
4309 | ||
4310 | return single_open(file, spr_wm_latency_show, dev); | |
4311 | } | |
4312 | ||
4313 | static int cur_wm_latency_open(struct inode *inode, struct file *file) | |
4314 | { | |
4315 | struct drm_device *dev = inode->i_private; | |
4316 | ||
9ad0257c | 4317 | if (HAS_GMCH_DISPLAY(dev)) |
369a1342 VS |
4318 | return -ENODEV; |
4319 | ||
4320 | return single_open(file, cur_wm_latency_show, dev); | |
4321 | } | |
4322 | ||
4323 | static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, | |
97e94b22 | 4324 | size_t len, loff_t *offp, uint16_t wm[8]) |
369a1342 VS |
4325 | { |
4326 | struct seq_file *m = file->private_data; | |
4327 | struct drm_device *dev = m->private; | |
97e94b22 | 4328 | uint16_t new[8] = { 0 }; |
546c81fd | 4329 | int num_levels = ilk_wm_max_level(dev) + 1; |
369a1342 VS |
4330 | int level; |
4331 | int ret; | |
4332 | char tmp[32]; | |
4333 | ||
4334 | if (len >= sizeof(tmp)) | |
4335 | return -EINVAL; | |
4336 | ||
4337 | if (copy_from_user(tmp, ubuf, len)) | |
4338 | return -EFAULT; | |
4339 | ||
4340 | tmp[len] = '\0'; | |
4341 | ||
97e94b22 DL |
4342 | ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", |
4343 | &new[0], &new[1], &new[2], &new[3], | |
4344 | &new[4], &new[5], &new[6], &new[7]); | |
369a1342 VS |
4345 | if (ret != num_levels) |
4346 | return -EINVAL; | |
4347 | ||
4348 | drm_modeset_lock_all(dev); | |
4349 | ||
4350 | for (level = 0; level < num_levels; level++) | |
4351 | wm[level] = new[level]; | |
4352 | ||
4353 | drm_modeset_unlock_all(dev); | |
4354 | ||
4355 | return len; | |
4356 | } | |
4357 | ||
4358 | ||
4359 | static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, | |
4360 | size_t len, loff_t *offp) | |
4361 | { | |
4362 | struct seq_file *m = file->private_data; | |
4363 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4364 | struct drm_i915_private *dev_priv = dev->dev_private; |
4365 | uint16_t *latencies; | |
369a1342 | 4366 | |
97e94b22 DL |
4367 | if (INTEL_INFO(dev)->gen >= 9) |
4368 | latencies = dev_priv->wm.skl_latency; | |
4369 | else | |
4370 | latencies = to_i915(dev)->wm.pri_latency; | |
4371 | ||
4372 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4373 | } |
4374 | ||
4375 | static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, | |
4376 | size_t len, loff_t *offp) | |
4377 | { | |
4378 | struct seq_file *m = file->private_data; | |
4379 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4380 | struct drm_i915_private *dev_priv = dev->dev_private; |
4381 | uint16_t *latencies; | |
369a1342 | 4382 | |
97e94b22 DL |
4383 | if (INTEL_INFO(dev)->gen >= 9) |
4384 | latencies = dev_priv->wm.skl_latency; | |
4385 | else | |
4386 | latencies = to_i915(dev)->wm.spr_latency; | |
4387 | ||
4388 | return wm_latency_write(file, ubuf, len, offp, latencies); | |
369a1342 VS |
4389 | } |
4390 | ||
4391 | static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, | |
4392 | size_t len, loff_t *offp) | |
4393 | { | |
4394 | struct seq_file *m = file->private_data; | |
4395 | struct drm_device *dev = m->private; | |
97e94b22 DL |
4396 | struct drm_i915_private *dev_priv = dev->dev_private; |
4397 | uint16_t *latencies; | |
4398 | ||
4399 | if (INTEL_INFO(dev)->gen >= 9) | |
4400 | latencies = dev_priv->wm.skl_latency; | |
4401 | else | |
4402 | latencies = to_i915(dev)->wm.cur_latency; | |
369a1342 | 4403 | |
97e94b22 | 4404 | return wm_latency_write(file, ubuf, len, offp, latencies); |
369a1342 VS |
4405 | } |
4406 | ||
4407 | static const struct file_operations i915_pri_wm_latency_fops = { | |
4408 | .owner = THIS_MODULE, | |
4409 | .open = pri_wm_latency_open, | |
4410 | .read = seq_read, | |
4411 | .llseek = seq_lseek, | |
4412 | .release = single_release, | |
4413 | .write = pri_wm_latency_write | |
4414 | }; | |
4415 | ||
4416 | static const struct file_operations i915_spr_wm_latency_fops = { | |
4417 | .owner = THIS_MODULE, | |
4418 | .open = spr_wm_latency_open, | |
4419 | .read = seq_read, | |
4420 | .llseek = seq_lseek, | |
4421 | .release = single_release, | |
4422 | .write = spr_wm_latency_write | |
4423 | }; | |
4424 | ||
4425 | static const struct file_operations i915_cur_wm_latency_fops = { | |
4426 | .owner = THIS_MODULE, | |
4427 | .open = cur_wm_latency_open, | |
4428 | .read = seq_read, | |
4429 | .llseek = seq_lseek, | |
4430 | .release = single_release, | |
4431 | .write = cur_wm_latency_write | |
4432 | }; | |
4433 | ||
647416f9 KC |
4434 | static int |
4435 | i915_wedged_get(void *data, u64 *val) | |
f3cd474b | 4436 | { |
647416f9 | 4437 | struct drm_device *dev = data; |
e277a1f8 | 4438 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3cd474b | 4439 | |
647416f9 | 4440 | *val = atomic_read(&dev_priv->gpu_error.reset_counter); |
f3cd474b | 4441 | |
647416f9 | 4442 | return 0; |
f3cd474b CW |
4443 | } |
4444 | ||
647416f9 KC |
4445 | static int |
4446 | i915_wedged_set(void *data, u64 val) | |
f3cd474b | 4447 | { |
647416f9 | 4448 | struct drm_device *dev = data; |
d46c0517 ID |
4449 | struct drm_i915_private *dev_priv = dev->dev_private; |
4450 | ||
b8d24a06 MK |
4451 | /* |
4452 | * There is no safeguard against this debugfs entry colliding | |
4453 | * with the hangcheck calling same i915_handle_error() in | |
4454 | * parallel, causing an explosion. For now we assume that the | |
4455 | * test harness is responsible enough not to inject gpu hangs | |
4456 | * while it is writing to 'i915_wedged' | |
4457 | */ | |
4458 | ||
4459 | if (i915_reset_in_progress(&dev_priv->gpu_error)) | |
4460 | return -EAGAIN; | |
4461 | ||
d46c0517 | 4462 | intel_runtime_pm_get(dev_priv); |
f3cd474b | 4463 | |
58174462 MK |
4464 | i915_handle_error(dev, val, |
4465 | "Manually setting wedged to %llu", val); | |
d46c0517 ID |
4466 | |
4467 | intel_runtime_pm_put(dev_priv); | |
4468 | ||
647416f9 | 4469 | return 0; |
f3cd474b CW |
4470 | } |
4471 | ||
647416f9 KC |
4472 | DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, |
4473 | i915_wedged_get, i915_wedged_set, | |
3a3b4f98 | 4474 | "%llu\n"); |
f3cd474b | 4475 | |
647416f9 KC |
4476 | static int |
4477 | i915_ring_stop_get(void *data, u64 *val) | |
e5eb3d63 | 4478 | { |
647416f9 | 4479 | struct drm_device *dev = data; |
e277a1f8 | 4480 | struct drm_i915_private *dev_priv = dev->dev_private; |
e5eb3d63 | 4481 | |
647416f9 | 4482 | *val = dev_priv->gpu_error.stop_rings; |
e5eb3d63 | 4483 | |
647416f9 | 4484 | return 0; |
e5eb3d63 DV |
4485 | } |
4486 | ||
647416f9 KC |
4487 | static int |
4488 | i915_ring_stop_set(void *data, u64 val) | |
e5eb3d63 | 4489 | { |
647416f9 | 4490 | struct drm_device *dev = data; |
e5eb3d63 | 4491 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4492 | int ret; |
e5eb3d63 | 4493 | |
647416f9 | 4494 | DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); |
e5eb3d63 | 4495 | |
22bcfc6a DV |
4496 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4497 | if (ret) | |
4498 | return ret; | |
4499 | ||
99584db3 | 4500 | dev_priv->gpu_error.stop_rings = val; |
e5eb3d63 DV |
4501 | mutex_unlock(&dev->struct_mutex); |
4502 | ||
647416f9 | 4503 | return 0; |
e5eb3d63 DV |
4504 | } |
4505 | ||
647416f9 KC |
4506 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, |
4507 | i915_ring_stop_get, i915_ring_stop_set, | |
4508 | "0x%08llx\n"); | |
d5442303 | 4509 | |
094f9a54 CW |
4510 | static int |
4511 | i915_ring_missed_irq_get(void *data, u64 *val) | |
4512 | { | |
4513 | struct drm_device *dev = data; | |
4514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4515 | ||
4516 | *val = dev_priv->gpu_error.missed_irq_rings; | |
4517 | return 0; | |
4518 | } | |
4519 | ||
4520 | static int | |
4521 | i915_ring_missed_irq_set(void *data, u64 val) | |
4522 | { | |
4523 | struct drm_device *dev = data; | |
4524 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4525 | int ret; | |
4526 | ||
4527 | /* Lock against concurrent debugfs callers */ | |
4528 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4529 | if (ret) | |
4530 | return ret; | |
4531 | dev_priv->gpu_error.missed_irq_rings = val; | |
4532 | mutex_unlock(&dev->struct_mutex); | |
4533 | ||
4534 | return 0; | |
4535 | } | |
4536 | ||
4537 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, | |
4538 | i915_ring_missed_irq_get, i915_ring_missed_irq_set, | |
4539 | "0x%08llx\n"); | |
4540 | ||
4541 | static int | |
4542 | i915_ring_test_irq_get(void *data, u64 *val) | |
4543 | { | |
4544 | struct drm_device *dev = data; | |
4545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4546 | ||
4547 | *val = dev_priv->gpu_error.test_irq_rings; | |
4548 | ||
4549 | return 0; | |
4550 | } | |
4551 | ||
4552 | static int | |
4553 | i915_ring_test_irq_set(void *data, u64 val) | |
4554 | { | |
4555 | struct drm_device *dev = data; | |
4556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4557 | int ret; | |
4558 | ||
4559 | DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); | |
4560 | ||
4561 | /* Lock against concurrent debugfs callers */ | |
4562 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4563 | if (ret) | |
4564 | return ret; | |
4565 | ||
4566 | dev_priv->gpu_error.test_irq_rings = val; | |
4567 | mutex_unlock(&dev->struct_mutex); | |
4568 | ||
4569 | return 0; | |
4570 | } | |
4571 | ||
4572 | DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, | |
4573 | i915_ring_test_irq_get, i915_ring_test_irq_set, | |
4574 | "0x%08llx\n"); | |
4575 | ||
dd624afd CW |
4576 | #define DROP_UNBOUND 0x1 |
4577 | #define DROP_BOUND 0x2 | |
4578 | #define DROP_RETIRE 0x4 | |
4579 | #define DROP_ACTIVE 0x8 | |
4580 | #define DROP_ALL (DROP_UNBOUND | \ | |
4581 | DROP_BOUND | \ | |
4582 | DROP_RETIRE | \ | |
4583 | DROP_ACTIVE) | |
647416f9 KC |
4584 | static int |
4585 | i915_drop_caches_get(void *data, u64 *val) | |
dd624afd | 4586 | { |
647416f9 | 4587 | *val = DROP_ALL; |
dd624afd | 4588 | |
647416f9 | 4589 | return 0; |
dd624afd CW |
4590 | } |
4591 | ||
647416f9 KC |
4592 | static int |
4593 | i915_drop_caches_set(void *data, u64 val) | |
dd624afd | 4594 | { |
647416f9 | 4595 | struct drm_device *dev = data; |
dd624afd | 4596 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4597 | int ret; |
dd624afd | 4598 | |
2f9fe5ff | 4599 | DRM_DEBUG("Dropping caches: 0x%08llx\n", val); |
dd624afd CW |
4600 | |
4601 | /* No need to check and wait for gpu resets, only libdrm auto-restarts | |
4602 | * on ioctls on -EAGAIN. */ | |
4603 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
4604 | if (ret) | |
4605 | return ret; | |
4606 | ||
4607 | if (val & DROP_ACTIVE) { | |
4608 | ret = i915_gpu_idle(dev); | |
4609 | if (ret) | |
4610 | goto unlock; | |
4611 | } | |
4612 | ||
4613 | if (val & (DROP_RETIRE | DROP_ACTIVE)) | |
4614 | i915_gem_retire_requests(dev); | |
4615 | ||
21ab4e74 CW |
4616 | if (val & DROP_BOUND) |
4617 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); | |
4ad72b7f | 4618 | |
21ab4e74 CW |
4619 | if (val & DROP_UNBOUND) |
4620 | i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); | |
dd624afd CW |
4621 | |
4622 | unlock: | |
4623 | mutex_unlock(&dev->struct_mutex); | |
4624 | ||
647416f9 | 4625 | return ret; |
dd624afd CW |
4626 | } |
4627 | ||
647416f9 KC |
4628 | DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, |
4629 | i915_drop_caches_get, i915_drop_caches_set, | |
4630 | "0x%08llx\n"); | |
dd624afd | 4631 | |
647416f9 KC |
4632 | static int |
4633 | i915_max_freq_get(void *data, u64 *val) | |
358733e9 | 4634 | { |
647416f9 | 4635 | struct drm_device *dev = data; |
e277a1f8 | 4636 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4637 | int ret; |
004777cb | 4638 | |
daa3afb2 | 4639 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4640 | return -ENODEV; |
4641 | ||
5c9669ce TR |
4642 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4643 | ||
4fc688ce | 4644 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4645 | if (ret) |
4646 | return ret; | |
358733e9 | 4647 | |
7c59a9c1 | 4648 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); |
4fc688ce | 4649 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4650 | |
647416f9 | 4651 | return 0; |
358733e9 JB |
4652 | } |
4653 | ||
647416f9 KC |
4654 | static int |
4655 | i915_max_freq_set(void *data, u64 val) | |
358733e9 | 4656 | { |
647416f9 | 4657 | struct drm_device *dev = data; |
358733e9 | 4658 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 4659 | u32 hw_max, hw_min; |
647416f9 | 4660 | int ret; |
004777cb | 4661 | |
daa3afb2 | 4662 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4663 | return -ENODEV; |
358733e9 | 4664 | |
5c9669ce TR |
4665 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4666 | ||
647416f9 | 4667 | DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); |
358733e9 | 4668 | |
4fc688ce | 4669 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4670 | if (ret) |
4671 | return ret; | |
4672 | ||
358733e9 JB |
4673 | /* |
4674 | * Turbo will still be enabled, but won't go above the set value. | |
4675 | */ | |
bc4d91f6 | 4676 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4677 | |
bc4d91f6 AG |
4678 | hw_max = dev_priv->rps.max_freq; |
4679 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4680 | |
b39fb297 | 4681 | if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { |
dd0a1aa1 JM |
4682 | mutex_unlock(&dev_priv->rps.hw_lock); |
4683 | return -EINVAL; | |
0a073b84 JB |
4684 | } |
4685 | ||
b39fb297 | 4686 | dev_priv->rps.max_freq_softlimit = val; |
dd0a1aa1 | 4687 | |
ffe02b40 | 4688 | intel_set_rps(dev, val); |
dd0a1aa1 | 4689 | |
4fc688ce | 4690 | mutex_unlock(&dev_priv->rps.hw_lock); |
358733e9 | 4691 | |
647416f9 | 4692 | return 0; |
358733e9 JB |
4693 | } |
4694 | ||
647416f9 KC |
4695 | DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, |
4696 | i915_max_freq_get, i915_max_freq_set, | |
3a3b4f98 | 4697 | "%llu\n"); |
358733e9 | 4698 | |
647416f9 KC |
4699 | static int |
4700 | i915_min_freq_get(void *data, u64 *val) | |
1523c310 | 4701 | { |
647416f9 | 4702 | struct drm_device *dev = data; |
e277a1f8 | 4703 | struct drm_i915_private *dev_priv = dev->dev_private; |
647416f9 | 4704 | int ret; |
004777cb | 4705 | |
daa3afb2 | 4706 | if (INTEL_INFO(dev)->gen < 6) |
004777cb DV |
4707 | return -ENODEV; |
4708 | ||
5c9669ce TR |
4709 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4710 | ||
4fc688ce | 4711 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4712 | if (ret) |
4713 | return ret; | |
1523c310 | 4714 | |
7c59a9c1 | 4715 | *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); |
4fc688ce | 4716 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4717 | |
647416f9 | 4718 | return 0; |
1523c310 JB |
4719 | } |
4720 | ||
647416f9 KC |
4721 | static int |
4722 | i915_min_freq_set(void *data, u64 val) | |
1523c310 | 4723 | { |
647416f9 | 4724 | struct drm_device *dev = data; |
1523c310 | 4725 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc4d91f6 | 4726 | u32 hw_max, hw_min; |
647416f9 | 4727 | int ret; |
004777cb | 4728 | |
daa3afb2 | 4729 | if (INTEL_INFO(dev)->gen < 6) |
004777cb | 4730 | return -ENODEV; |
1523c310 | 4731 | |
5c9669ce TR |
4732 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
4733 | ||
647416f9 | 4734 | DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); |
1523c310 | 4735 | |
4fc688ce | 4736 | ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); |
004777cb DV |
4737 | if (ret) |
4738 | return ret; | |
4739 | ||
1523c310 JB |
4740 | /* |
4741 | * Turbo will still be enabled, but won't go below the set value. | |
4742 | */ | |
bc4d91f6 | 4743 | val = intel_freq_opcode(dev_priv, val); |
dd0a1aa1 | 4744 | |
bc4d91f6 AG |
4745 | hw_max = dev_priv->rps.max_freq; |
4746 | hw_min = dev_priv->rps.min_freq; | |
dd0a1aa1 | 4747 | |
b39fb297 | 4748 | if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { |
dd0a1aa1 JM |
4749 | mutex_unlock(&dev_priv->rps.hw_lock); |
4750 | return -EINVAL; | |
0a073b84 | 4751 | } |
dd0a1aa1 | 4752 | |
b39fb297 | 4753 | dev_priv->rps.min_freq_softlimit = val; |
dd0a1aa1 | 4754 | |
ffe02b40 | 4755 | intel_set_rps(dev, val); |
dd0a1aa1 | 4756 | |
4fc688ce | 4757 | mutex_unlock(&dev_priv->rps.hw_lock); |
1523c310 | 4758 | |
647416f9 | 4759 | return 0; |
1523c310 JB |
4760 | } |
4761 | ||
647416f9 KC |
4762 | DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, |
4763 | i915_min_freq_get, i915_min_freq_set, | |
3a3b4f98 | 4764 | "%llu\n"); |
1523c310 | 4765 | |
647416f9 KC |
4766 | static int |
4767 | i915_cache_sharing_get(void *data, u64 *val) | |
07b7ddd9 | 4768 | { |
647416f9 | 4769 | struct drm_device *dev = data; |
e277a1f8 | 4770 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 4771 | u32 snpcr; |
647416f9 | 4772 | int ret; |
07b7ddd9 | 4773 | |
004777cb DV |
4774 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
4775 | return -ENODEV; | |
4776 | ||
22bcfc6a DV |
4777 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
4778 | if (ret) | |
4779 | return ret; | |
c8c8fb33 | 4780 | intel_runtime_pm_get(dev_priv); |
22bcfc6a | 4781 | |
07b7ddd9 | 4782 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
c8c8fb33 PZ |
4783 | |
4784 | intel_runtime_pm_put(dev_priv); | |
07b7ddd9 JB |
4785 | mutex_unlock(&dev_priv->dev->struct_mutex); |
4786 | ||
647416f9 | 4787 | *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; |
07b7ddd9 | 4788 | |
647416f9 | 4789 | return 0; |
07b7ddd9 JB |
4790 | } |
4791 | ||
647416f9 KC |
4792 | static int |
4793 | i915_cache_sharing_set(void *data, u64 val) | |
07b7ddd9 | 4794 | { |
647416f9 | 4795 | struct drm_device *dev = data; |
07b7ddd9 | 4796 | struct drm_i915_private *dev_priv = dev->dev_private; |
07b7ddd9 | 4797 | u32 snpcr; |
07b7ddd9 | 4798 | |
004777cb DV |
4799 | if (!(IS_GEN6(dev) || IS_GEN7(dev))) |
4800 | return -ENODEV; | |
4801 | ||
647416f9 | 4802 | if (val > 3) |
07b7ddd9 JB |
4803 | return -EINVAL; |
4804 | ||
c8c8fb33 | 4805 | intel_runtime_pm_get(dev_priv); |
647416f9 | 4806 | DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); |
07b7ddd9 JB |
4807 | |
4808 | /* Update the cache sharing policy here as well */ | |
4809 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4810 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4811 | snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); | |
4812 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
4813 | ||
c8c8fb33 | 4814 | intel_runtime_pm_put(dev_priv); |
647416f9 | 4815 | return 0; |
07b7ddd9 JB |
4816 | } |
4817 | ||
647416f9 KC |
4818 | DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, |
4819 | i915_cache_sharing_get, i915_cache_sharing_set, | |
4820 | "%llu\n"); | |
07b7ddd9 | 4821 | |
5d39525a JM |
4822 | struct sseu_dev_status { |
4823 | unsigned int slice_total; | |
4824 | unsigned int subslice_total; | |
4825 | unsigned int subslice_per_slice; | |
4826 | unsigned int eu_total; | |
4827 | unsigned int eu_per_subslice; | |
4828 | }; | |
4829 | ||
4830 | static void cherryview_sseu_device_status(struct drm_device *dev, | |
4831 | struct sseu_dev_status *stat) | |
4832 | { | |
4833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4834 | const int ss_max = 2; | |
4835 | int ss; | |
4836 | u32 sig1[ss_max], sig2[ss_max]; | |
4837 | ||
4838 | sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); | |
4839 | sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); | |
4840 | sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); | |
4841 | sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); | |
4842 | ||
4843 | for (ss = 0; ss < ss_max; ss++) { | |
4844 | unsigned int eu_cnt; | |
4845 | ||
4846 | if (sig1[ss] & CHV_SS_PG_ENABLE) | |
4847 | /* skip disabled subslice */ | |
4848 | continue; | |
4849 | ||
4850 | stat->slice_total = 1; | |
4851 | stat->subslice_per_slice++; | |
4852 | eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + | |
4853 | ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + | |
4854 | ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + | |
4855 | ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); | |
4856 | stat->eu_total += eu_cnt; | |
4857 | stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); | |
4858 | } | |
4859 | stat->subslice_total = stat->subslice_per_slice; | |
4860 | } | |
4861 | ||
4862 | static void gen9_sseu_device_status(struct drm_device *dev, | |
4863 | struct sseu_dev_status *stat) | |
4864 | { | |
4865 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1c046bc1 | 4866 | int s_max = 3, ss_max = 4; |
5d39525a JM |
4867 | int s, ss; |
4868 | u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; | |
4869 | ||
1c046bc1 JM |
4870 | /* BXT has a single slice and at most 3 subslices. */ |
4871 | if (IS_BROXTON(dev)) { | |
4872 | s_max = 1; | |
4873 | ss_max = 3; | |
4874 | } | |
4875 | ||
4876 | for (s = 0; s < s_max; s++) { | |
4877 | s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); | |
4878 | eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); | |
4879 | eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); | |
4880 | } | |
4881 | ||
5d39525a JM |
4882 | eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | |
4883 | GEN9_PGCTL_SSA_EU19_ACK | | |
4884 | GEN9_PGCTL_SSA_EU210_ACK | | |
4885 | GEN9_PGCTL_SSA_EU311_ACK; | |
4886 | eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | | |
4887 | GEN9_PGCTL_SSB_EU19_ACK | | |
4888 | GEN9_PGCTL_SSB_EU210_ACK | | |
4889 | GEN9_PGCTL_SSB_EU311_ACK; | |
4890 | ||
4891 | for (s = 0; s < s_max; s++) { | |
1c046bc1 JM |
4892 | unsigned int ss_cnt = 0; |
4893 | ||
5d39525a JM |
4894 | if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) |
4895 | /* skip disabled slice */ | |
4896 | continue; | |
4897 | ||
4898 | stat->slice_total++; | |
1c046bc1 JM |
4899 | |
4900 | if (IS_SKYLAKE(dev)) | |
4901 | ss_cnt = INTEL_INFO(dev)->subslice_per_slice; | |
4902 | ||
5d39525a JM |
4903 | for (ss = 0; ss < ss_max; ss++) { |
4904 | unsigned int eu_cnt; | |
4905 | ||
1c046bc1 JM |
4906 | if (IS_BROXTON(dev) && |
4907 | !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) | |
4908 | /* skip disabled subslice */ | |
4909 | continue; | |
4910 | ||
4911 | if (IS_BROXTON(dev)) | |
4912 | ss_cnt++; | |
4913 | ||
5d39525a JM |
4914 | eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & |
4915 | eu_mask[ss%2]); | |
4916 | stat->eu_total += eu_cnt; | |
4917 | stat->eu_per_subslice = max(stat->eu_per_subslice, | |
4918 | eu_cnt); | |
4919 | } | |
1c046bc1 JM |
4920 | |
4921 | stat->subslice_total += ss_cnt; | |
4922 | stat->subslice_per_slice = max(stat->subslice_per_slice, | |
4923 | ss_cnt); | |
5d39525a JM |
4924 | } |
4925 | } | |
4926 | ||
3873218f JM |
4927 | static int i915_sseu_status(struct seq_file *m, void *unused) |
4928 | { | |
4929 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
4930 | struct drm_device *dev = node->minor->dev; | |
5d39525a | 4931 | struct sseu_dev_status stat; |
3873218f | 4932 | |
5575f03a | 4933 | if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev)) |
3873218f JM |
4934 | return -ENODEV; |
4935 | ||
4936 | seq_puts(m, "SSEU Device Info\n"); | |
4937 | seq_printf(m, " Available Slice Total: %u\n", | |
4938 | INTEL_INFO(dev)->slice_total); | |
4939 | seq_printf(m, " Available Subslice Total: %u\n", | |
4940 | INTEL_INFO(dev)->subslice_total); | |
4941 | seq_printf(m, " Available Subslice Per Slice: %u\n", | |
4942 | INTEL_INFO(dev)->subslice_per_slice); | |
4943 | seq_printf(m, " Available EU Total: %u\n", | |
4944 | INTEL_INFO(dev)->eu_total); | |
4945 | seq_printf(m, " Available EU Per Subslice: %u\n", | |
4946 | INTEL_INFO(dev)->eu_per_subslice); | |
4947 | seq_printf(m, " Has Slice Power Gating: %s\n", | |
4948 | yesno(INTEL_INFO(dev)->has_slice_pg)); | |
4949 | seq_printf(m, " Has Subslice Power Gating: %s\n", | |
4950 | yesno(INTEL_INFO(dev)->has_subslice_pg)); | |
4951 | seq_printf(m, " Has EU Power Gating: %s\n", | |
4952 | yesno(INTEL_INFO(dev)->has_eu_pg)); | |
4953 | ||
7f992aba | 4954 | seq_puts(m, "SSEU Device Status\n"); |
5d39525a | 4955 | memset(&stat, 0, sizeof(stat)); |
5575f03a | 4956 | if (IS_CHERRYVIEW(dev)) { |
5d39525a | 4957 | cherryview_sseu_device_status(dev, &stat); |
1c046bc1 | 4958 | } else if (INTEL_INFO(dev)->gen >= 9) { |
5d39525a | 4959 | gen9_sseu_device_status(dev, &stat); |
7f992aba | 4960 | } |
5d39525a JM |
4961 | seq_printf(m, " Enabled Slice Total: %u\n", |
4962 | stat.slice_total); | |
4963 | seq_printf(m, " Enabled Subslice Total: %u\n", | |
4964 | stat.subslice_total); | |
4965 | seq_printf(m, " Enabled Subslice Per Slice: %u\n", | |
4966 | stat.subslice_per_slice); | |
4967 | seq_printf(m, " Enabled EU Total: %u\n", | |
4968 | stat.eu_total); | |
4969 | seq_printf(m, " Enabled EU Per Subslice: %u\n", | |
4970 | stat.eu_per_subslice); | |
7f992aba | 4971 | |
3873218f JM |
4972 | return 0; |
4973 | } | |
4974 | ||
6d794d42 BW |
4975 | static int i915_forcewake_open(struct inode *inode, struct file *file) |
4976 | { | |
4977 | struct drm_device *dev = inode->i_private; | |
4978 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d794d42 | 4979 | |
075edca4 | 4980 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
4981 | return 0; |
4982 | ||
6daccb0b | 4983 | intel_runtime_pm_get(dev_priv); |
59bad947 | 4984 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6d794d42 BW |
4985 | |
4986 | return 0; | |
4987 | } | |
4988 | ||
c43b5634 | 4989 | static int i915_forcewake_release(struct inode *inode, struct file *file) |
6d794d42 BW |
4990 | { |
4991 | struct drm_device *dev = inode->i_private; | |
4992 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4993 | ||
075edca4 | 4994 | if (INTEL_INFO(dev)->gen < 6) |
6d794d42 BW |
4995 | return 0; |
4996 | ||
59bad947 | 4997 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6daccb0b | 4998 | intel_runtime_pm_put(dev_priv); |
6d794d42 BW |
4999 | |
5000 | return 0; | |
5001 | } | |
5002 | ||
5003 | static const struct file_operations i915_forcewake_fops = { | |
5004 | .owner = THIS_MODULE, | |
5005 | .open = i915_forcewake_open, | |
5006 | .release = i915_forcewake_release, | |
5007 | }; | |
5008 | ||
5009 | static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) | |
5010 | { | |
5011 | struct drm_device *dev = minor->dev; | |
5012 | struct dentry *ent; | |
5013 | ||
5014 | ent = debugfs_create_file("i915_forcewake_user", | |
8eb57294 | 5015 | S_IRUSR, |
6d794d42 BW |
5016 | root, dev, |
5017 | &i915_forcewake_fops); | |
f3c5fe97 WY |
5018 | if (!ent) |
5019 | return -ENOMEM; | |
6d794d42 | 5020 | |
8eb57294 | 5021 | return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); |
6d794d42 BW |
5022 | } |
5023 | ||
6a9c308d DV |
5024 | static int i915_debugfs_create(struct dentry *root, |
5025 | struct drm_minor *minor, | |
5026 | const char *name, | |
5027 | const struct file_operations *fops) | |
07b7ddd9 JB |
5028 | { |
5029 | struct drm_device *dev = minor->dev; | |
5030 | struct dentry *ent; | |
5031 | ||
6a9c308d | 5032 | ent = debugfs_create_file(name, |
07b7ddd9 JB |
5033 | S_IRUGO | S_IWUSR, |
5034 | root, dev, | |
6a9c308d | 5035 | fops); |
f3c5fe97 WY |
5036 | if (!ent) |
5037 | return -ENOMEM; | |
07b7ddd9 | 5038 | |
6a9c308d | 5039 | return drm_add_fake_info_node(minor, ent, fops); |
07b7ddd9 JB |
5040 | } |
5041 | ||
06c5bf8c | 5042 | static const struct drm_info_list i915_debugfs_list[] = { |
311bd68e | 5043 | {"i915_capabilities", i915_capabilities, 0}, |
73aa808f | 5044 | {"i915_gem_objects", i915_gem_object_info, 0}, |
08c18323 | 5045 | {"i915_gem_gtt", i915_gem_gtt_info, 0}, |
1b50247a | 5046 | {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, |
433e12f7 | 5047 | {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, |
433e12f7 | 5048 | {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, |
6d2b8885 | 5049 | {"i915_gem_stolen", i915_gem_stolen_list_info }, |
4e5359cd | 5050 | {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, |
2017263e BG |
5051 | {"i915_gem_request", i915_gem_request_info, 0}, |
5052 | {"i915_gem_seqno", i915_gem_seqno_info, 0}, | |
a6172a80 | 5053 | {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, |
2017263e | 5054 | {"i915_gem_interrupt", i915_interrupt_info, 0}, |
1ec14ad3 CW |
5055 | {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, |
5056 | {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, | |
5057 | {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, | |
9010ebfd | 5058 | {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, |
493018dc | 5059 | {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, |
adb4bd12 | 5060 | {"i915_frequency_info", i915_frequency_info, 0}, |
f654449a | 5061 | {"i915_hangcheck_info", i915_hangcheck_info, 0}, |
f97108d1 | 5062 | {"i915_drpc_info", i915_drpc_info, 0}, |
7648fa99 | 5063 | {"i915_emon_status", i915_emon_status, 0}, |
23b2f8bb | 5064 | {"i915_ring_freq_table", i915_ring_freq_table, 0}, |
b5e50c3f | 5065 | {"i915_fbc_status", i915_fbc_status, 0}, |
92d44621 | 5066 | {"i915_ips_status", i915_ips_status, 0}, |
4a9bef37 | 5067 | {"i915_sr_status", i915_sr_status, 0}, |
44834a67 | 5068 | {"i915_opregion", i915_opregion, 0}, |
37811fcc | 5069 | {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, |
e76d3630 | 5070 | {"i915_context_status", i915_context_status, 0}, |
c0ab1ae9 | 5071 | {"i915_dump_lrc", i915_dump_lrc, 0}, |
4ba70e44 | 5072 | {"i915_execlists", i915_execlists, 0}, |
f65367b5 | 5073 | {"i915_forcewake_domains", i915_forcewake_domains, 0}, |
ea16a3cd | 5074 | {"i915_swizzle_info", i915_swizzle_info, 0}, |
3cf17fc5 | 5075 | {"i915_ppgtt_info", i915_ppgtt_info, 0}, |
63573eb7 | 5076 | {"i915_llc", i915_llc, 0}, |
e91fd8c6 | 5077 | {"i915_edp_psr_status", i915_edp_psr_status, 0}, |
d2e216d0 | 5078 | {"i915_sink_crc_eDP1", i915_sink_crc, 0}, |
ec013e7f | 5079 | {"i915_energy_uJ", i915_energy_uJ, 0}, |
6455c870 | 5080 | {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, |
1da51581 | 5081 | {"i915_power_domain_info", i915_power_domain_info, 0}, |
53f5e3ca | 5082 | {"i915_display_info", i915_display_info, 0}, |
e04934cf | 5083 | {"i915_semaphore_status", i915_semaphore_status, 0}, |
728e29d7 | 5084 | {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, |
11bed958 | 5085 | {"i915_dp_mst_info", i915_dp_mst_info, 0}, |
1ed1ef9d | 5086 | {"i915_wa_registers", i915_wa_registers, 0}, |
c5511e44 | 5087 | {"i915_ddb_info", i915_ddb_info, 0}, |
3873218f | 5088 | {"i915_sseu_status", i915_sseu_status, 0}, |
a54746e3 | 5089 | {"i915_drrs_status", i915_drrs_status, 0}, |
1854d5ca | 5090 | {"i915_rps_boost_info", i915_rps_boost_info, 0}, |
2017263e | 5091 | }; |
27c202ad | 5092 | #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) |
2017263e | 5093 | |
06c5bf8c | 5094 | static const struct i915_debugfs_files { |
34b9674c DV |
5095 | const char *name; |
5096 | const struct file_operations *fops; | |
5097 | } i915_debugfs_files[] = { | |
5098 | {"i915_wedged", &i915_wedged_fops}, | |
5099 | {"i915_max_freq", &i915_max_freq_fops}, | |
5100 | {"i915_min_freq", &i915_min_freq_fops}, | |
5101 | {"i915_cache_sharing", &i915_cache_sharing_fops}, | |
5102 | {"i915_ring_stop", &i915_ring_stop_fops}, | |
094f9a54 CW |
5103 | {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, |
5104 | {"i915_ring_test_irq", &i915_ring_test_irq_fops}, | |
34b9674c DV |
5105 | {"i915_gem_drop_caches", &i915_drop_caches_fops}, |
5106 | {"i915_error_state", &i915_error_state_fops}, | |
5107 | {"i915_next_seqno", &i915_next_seqno_fops}, | |
bd9db02f | 5108 | {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, |
369a1342 VS |
5109 | {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, |
5110 | {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, | |
5111 | {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, | |
da46f936 | 5112 | {"i915_fbc_false_color", &i915_fbc_fc_fops}, |
eb3394fa TP |
5113 | {"i915_dp_test_data", &i915_displayport_test_data_fops}, |
5114 | {"i915_dp_test_type", &i915_displayport_test_type_fops}, | |
5115 | {"i915_dp_test_active", &i915_displayport_test_active_fops} | |
34b9674c DV |
5116 | }; |
5117 | ||
07144428 DL |
5118 | void intel_display_crc_init(struct drm_device *dev) |
5119 | { | |
5120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b378360e | 5121 | enum pipe pipe; |
07144428 | 5122 | |
055e393f | 5123 | for_each_pipe(dev_priv, pipe) { |
b378360e | 5124 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; |
07144428 | 5125 | |
d538bbdf DL |
5126 | pipe_crc->opened = false; |
5127 | spin_lock_init(&pipe_crc->lock); | |
07144428 DL |
5128 | init_waitqueue_head(&pipe_crc->wq); |
5129 | } | |
5130 | } | |
5131 | ||
27c202ad | 5132 | int i915_debugfs_init(struct drm_minor *minor) |
2017263e | 5133 | { |
34b9674c | 5134 | int ret, i; |
f3cd474b | 5135 | |
6d794d42 | 5136 | ret = i915_forcewake_create(minor->debugfs_root, minor); |
358733e9 JB |
5137 | if (ret) |
5138 | return ret; | |
6a9c308d | 5139 | |
07144428 DL |
5140 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
5141 | ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); | |
5142 | if (ret) | |
5143 | return ret; | |
5144 | } | |
5145 | ||
34b9674c DV |
5146 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5147 | ret = i915_debugfs_create(minor->debugfs_root, minor, | |
5148 | i915_debugfs_files[i].name, | |
5149 | i915_debugfs_files[i].fops); | |
5150 | if (ret) | |
5151 | return ret; | |
5152 | } | |
40633219 | 5153 | |
27c202ad BG |
5154 | return drm_debugfs_create_files(i915_debugfs_list, |
5155 | I915_DEBUGFS_ENTRIES, | |
2017263e BG |
5156 | minor->debugfs_root, minor); |
5157 | } | |
5158 | ||
27c202ad | 5159 | void i915_debugfs_cleanup(struct drm_minor *minor) |
2017263e | 5160 | { |
34b9674c DV |
5161 | int i; |
5162 | ||
27c202ad BG |
5163 | drm_debugfs_remove_files(i915_debugfs_list, |
5164 | I915_DEBUGFS_ENTRIES, minor); | |
07144428 | 5165 | |
6d794d42 BW |
5166 | drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, |
5167 | 1, minor); | |
07144428 | 5168 | |
e309a997 | 5169 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { |
07144428 DL |
5170 | struct drm_info_list *info_list = |
5171 | (struct drm_info_list *)&i915_pipe_crc_data[i]; | |
5172 | ||
5173 | drm_debugfs_remove_files(info_list, 1, minor); | |
5174 | } | |
5175 | ||
34b9674c DV |
5176 | for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { |
5177 | struct drm_info_list *info_list = | |
5178 | (struct drm_info_list *) i915_debugfs_files[i].fops; | |
5179 | ||
5180 | drm_debugfs_remove_files(info_list, 1, minor); | |
5181 | } | |
2017263e | 5182 | } |
aa7471d2 JN |
5183 | |
5184 | struct dpcd_block { | |
5185 | /* DPCD dump start address. */ | |
5186 | unsigned int offset; | |
5187 | /* DPCD dump end address, inclusive. If unset, .size will be used. */ | |
5188 | unsigned int end; | |
5189 | /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ | |
5190 | size_t size; | |
5191 | /* Only valid for eDP. */ | |
5192 | bool edp; | |
5193 | }; | |
5194 | ||
5195 | static const struct dpcd_block i915_dpcd_debug[] = { | |
5196 | { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, | |
5197 | { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, | |
5198 | { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, | |
5199 | { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, | |
5200 | { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, | |
5201 | { .offset = DP_SET_POWER }, | |
5202 | { .offset = DP_EDP_DPCD_REV }, | |
5203 | { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, | |
5204 | { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, | |
5205 | { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, | |
5206 | }; | |
5207 | ||
5208 | static int i915_dpcd_show(struct seq_file *m, void *data) | |
5209 | { | |
5210 | struct drm_connector *connector = m->private; | |
5211 | struct intel_dp *intel_dp = | |
5212 | enc_to_intel_dp(&intel_attached_encoder(connector)->base); | |
5213 | uint8_t buf[16]; | |
5214 | ssize_t err; | |
5215 | int i; | |
5216 | ||
5c1a8875 MK |
5217 | if (connector->status != connector_status_connected) |
5218 | return -ENODEV; | |
5219 | ||
aa7471d2 JN |
5220 | for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { |
5221 | const struct dpcd_block *b = &i915_dpcd_debug[i]; | |
5222 | size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); | |
5223 | ||
5224 | if (b->edp && | |
5225 | connector->connector_type != DRM_MODE_CONNECTOR_eDP) | |
5226 | continue; | |
5227 | ||
5228 | /* low tech for now */ | |
5229 | if (WARN_ON(size > sizeof(buf))) | |
5230 | continue; | |
5231 | ||
5232 | err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); | |
5233 | if (err <= 0) { | |
5234 | DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", | |
5235 | size, b->offset, err); | |
5236 | continue; | |
5237 | } | |
5238 | ||
5239 | seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); | |
b3f9d7d7 | 5240 | } |
aa7471d2 JN |
5241 | |
5242 | return 0; | |
5243 | } | |
5244 | ||
5245 | static int i915_dpcd_open(struct inode *inode, struct file *file) | |
5246 | { | |
5247 | return single_open(file, i915_dpcd_show, inode->i_private); | |
5248 | } | |
5249 | ||
5250 | static const struct file_operations i915_dpcd_fops = { | |
5251 | .owner = THIS_MODULE, | |
5252 | .open = i915_dpcd_open, | |
5253 | .read = seq_read, | |
5254 | .llseek = seq_lseek, | |
5255 | .release = single_release, | |
5256 | }; | |
5257 | ||
5258 | /** | |
5259 | * i915_debugfs_connector_add - add i915 specific connector debugfs files | |
5260 | * @connector: pointer to a registered drm_connector | |
5261 | * | |
5262 | * Cleanup will be done by drm_connector_unregister() through a call to | |
5263 | * drm_debugfs_connector_remove(). | |
5264 | * | |
5265 | * Returns 0 on success, negative error codes on error. | |
5266 | */ | |
5267 | int i915_debugfs_connector_add(struct drm_connector *connector) | |
5268 | { | |
5269 | struct dentry *root = connector->debugfs_entry; | |
5270 | ||
5271 | /* The connector must have been registered beforehands. */ | |
5272 | if (!root) | |
5273 | return -ENODEV; | |
5274 | ||
5275 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || | |
5276 | connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
5277 | debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, | |
5278 | &i915_dpcd_fops); | |
5279 | ||
5280 | return 0; | |
5281 | } |